diff --git a/.github/scripts/hostsetup.sh b/.github/scripts/hostsetup.sh index a136f61a43e..835c3e95c81 100755 --- a/.github/scripts/hostsetup.sh +++ b/.github/scripts/hostsetup.sh @@ -70,6 +70,8 @@ apt install -y \ g++-9 \ gcc-9 \ wget \ + openssl \ + libssl-dev \ libtbb-dev # installing the latest version of cmake diff --git a/.github/scripts/install_dependencies.sh b/.github/scripts/install_dependencies.sh index 383b237a89e..61ad671d30b 100755 --- a/.github/scripts/install_dependencies.sh +++ b/.github/scripts/install_dependencies.sh @@ -56,7 +56,8 @@ sudo apt install -y \ clang-17 \ clang-18 \ clang-format-18 \ - libtbb-dev + libtbb-dev \ + openssl pip install -r requirements.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 5a1a2150b84..653c3f17173 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,6 +31,7 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers ( option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF) option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF) option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF) +option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON) option(VTR_ENABLE_VERBOSE "Enable increased debug verbosity" OFF) option(SPEC_CPU "Enable SPEC CPU v8 support" OFF) diff --git a/doc/src/Images/VIB.png b/doc/src/Images/VIB.png new file mode 100644 index 00000000000..4d84eee75e6 Binary files /dev/null and b/doc/src/Images/VIB.png differ diff --git a/doc/src/Images/bent_wires.png b/doc/src/Images/bent_wires.png new file mode 100644 index 00000000000..99e236a29c2 Binary files /dev/null and b/doc/src/Images/bent_wires.png differ diff --git a/doc/src/Images/double-level.png b/doc/src/Images/double-level.png new file mode 100644 index 00000000000..3f26df480d9 Binary files /dev/null and b/doc/src/Images/double-level.png differ diff --git a/doc/src/Images/vib_example.png b/doc/src/Images/vib_example.png new file mode 100644 index 00000000000..20a5b7177bf Binary files /dev/null and b/doc/src/Images/vib_example.png differ diff --git a/doc/src/vpr/VIB.rst b/doc/src/vpr/VIB.rst new file mode 100644 index 00000000000..b48675ab174 --- /dev/null +++ b/doc/src/vpr/VIB.rst @@ -0,0 +1,254 @@ +.. _VIB: + +VIB Architecture +============ +The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing MUXes, whose inputs are driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes. + +Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure. + +.. figure:: ../Images/VIB.png + :align: center + :height: 300 + + Figure 1. VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB. + +.. figure:: ../Images/double-level.png + :align: center + + Figure 2. Double-level MUX topology. + +Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. The bent wires can connect to both bent and straight wire segments. + +.. figure:: ../Images/bent_wires.png + :align: center + + Figure 3. Presentation for bent wires. + +FPGA Architecture File Modification (.xml) +-------------------------- +For original tags of FPGA architecture file see :ref:`fpga_architecture_description`. + +Modification for ```` Tag +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The content within the ```` tag consists of a group of ```` tags. +The ```` tag and its contents are described below. + +.. arch:tag:: content + + :req_param content: + The switch names and the depopulation pattern as described below. + +.. arch:tag:: int list + +.. arch:tag:: int list + +.. arch:tag:: + +For bent wires, a new content ```` is added in the ```` tag. + +.. arch:tag:: bent pattern list + + This tag describes the bent pattern for this particular wire segment. + For example, a length 4 wire has a bent pattern of ``- - U``. + A ``-`` indicates no bent at this position and a ``U`` indicates a conterclockwise bent at the position. (``D`` indicates a clockwise bent.) + + .. note:: A bent wire should remain consistent in both the x and y axes. + +New Added Top Level Tag ```` +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The content within the ```` tag consists of a group of ```` tags. Different ```` tags describe the paradigms of VIB, which apply to different positions. + +.. arch:tag:: content + + :req_param name: + A unique alphanumeric name to identify this VIB type. + + :req_param pbtype_name: + The name of the block type (e.g. clb, memory) that this VIB connects to. + + .. note:: A block (e.g. clb, dsp) is connected to the VIB on its top-right side, so the input and output pins of the block should be on the top or right side. + + :req_param vib_seg_group: + The number of the segment types in this VIB. + + :req_param arch_vib_switch: + Name of the mux switch type used to drive wires in the VIB by default, and a custom switch can override this switch type for specific connections if desired. + + :req_param content: + The segment groups and the multistage MUX topology as described below. + +The ``content`` of ```` tag consists of several ```` tags and a ```` tag. +For example: + +.. code-block:: xml + + + + + + + + + + ... + + + ... + + + + + ... + + + +.. arch:tag:: + + :req_param name: + The name of the segment in this VIB described in ````. + + :req_param track_nums: + The track number of the segment in this VIB. + + .. note:: When using unidirectional segments, the track number of the segment represents the number for one direction. For example, the ``track_nums`` is ``10``, which means total ``20`` tracks of the segment in the channel for both (INC & DEC) directions. + +.. arch:tag:: content + + :req_param content: + The detaild information for first and second MUXes. + +The ``content`` of ```` tag consists of a ```` tag and a ```` tag. + +.. arch:tag:: content + + :req_param switch_name: + Name of the mux switch type used to drive first stage MUXes in the VIB. + + :req_param content: + The details of each MUX. + +The ``content`` of ```` tag consists of many ```` tags. + +.. arch:tag:: content + + :req_param name: + Name of the MUX. + + :req_param content: + A ```` tag to describe what pins and wires connect to this MUX. + +For example: + +.. code-block:: xml + + + + clb.O[0] clb.O[1:3] clb.O[4] + + + L1.E1 L1.S1 L2.E0 + + ... + + +The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. + +.. arch:tag:: content + + :req_param content: + The details of each MUX. + +The ``content`` of ```` tag consists of many ```` tags. + +.. arch:tag:: content + + :req_param name: + Name of the MUX. + + :req_param content: + A ```` tag to describe where this MUX connect to and a ```` tag to describe what pins and wires connect to this MUX. + +For example: + +.. code-block:: xml + + + + clb.I[0] + clb.O[4] f_mux_0 f_mux_1 + + + L1.E1 + L1.S2 f_mux_0 f_mux_1 + + ... + + +The ```` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. The ```` tag in ```` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.S2`` means the track ``2`` in the ``South`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX. + +Here is a complete example of the ```` tag: + +.. code-block:: xml + + + + + + + + clb.O[0] clb.O[1:3] clb.O[4] + + + L1.E1 L1.S1 L2.E0 + + + + + clb.I[0] + clb.O[4] f_mux_0 f_mux_1 + + + L1.E1 + L1.S2 f_mux_0 f_mux_1 + + + + + +Its corresponding detailed architecture is shown in Figure 4. + +.. figure:: ../Images/vib_example.png + :align: center + :height: 600 + + Figure 4. The corresponding detaied architecture of the example. + +New Added Top Level Tag ```` +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Content inside this tag specifies VIB grid layout to describe different VIBs applied on different locations. + +.. arch:tag:: content + + :req_param name: + The name identifying this VIB grid layout. It should be the same as the corresponding layout name inside the ```` tag. + + :req_param content: + The content should contain a set of grid location tags. For grid location tags of vib_layout see :ref:`fpga_architecture_description`; ref:`grid_expressions` + +For example: + +.. code-block:: xml + + + + + + + ... + + + +In this VIB grid layout, ``perimeter``, ``fill``, ``col`` and so on are tags in original ```` tag to describe positions of each type of VIB block. The attibute ``type`` should correspond to the ``name`` of a ```` tag in ````. +Besides, the ``pbtype_name`` of corresponding ```` must be the same as the physical block type at this position. + +In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively. diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 6070663eddc..039b8ea2e43 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -379,7 +379,7 @@ Use the options below to override this default naming behaviour. .. seealso:: :ref:`Routing Resource XML File `. -.. option:: --read_vpr_constraints +.. option:: --read_vpr_constraints ::...: Reads the :ref:`VPR constraints ` that the flow must respect from the specified XML file. diff --git a/doc/src/vpr/index.rst b/doc/src/vpr/index.rst index 61d60030bdb..ceefa3debaa 100644 --- a/doc/src/vpr/index.rst +++ b/doc/src/vpr/index.rst @@ -60,3 +60,5 @@ The purpose of VPR is to make the packing, placement, and routing stages of the file_formats debug_aids + + VIB diff --git a/doc/src/vpr/route_constraints.rst b/doc/src/vpr/route_constraints.rst new file mode 100644 index 00000000000..fe921cd5a23 --- /dev/null +++ b/doc/src/vpr/route_constraints.rst @@ -0,0 +1,44 @@ + +VPR Route Constraints +========================= +.. _vpr_constraints_file: +VPR supports running flows with route constraints. Route constraints are set on global signals to specify if they should be routed or not. For example, a user may want to route a specific internal clock even clock modeling option is set to not route it. + +.. note:: The constraint specified in this file overrides the setting of option "--clock_modeling" if it is specified. A message will be issued in such case: "Route constraint(s) detected and will override clock modeling setting". + +The route constraints should be specified by the user using an XML constraints file format, as described in the section below. + +A Constraints File Example +-------------------------- + +.. code-block:: xml + :caption: An example of a route constraints file in XML format. + :linenos: + + + + + + + + + + +.. _end: + +.. note:: The "route_model" in constraint specified in this file only support "ideal" and "route" only. + +Constraints File Format +----------------------- + +VPR has a specific XML format which must be used when creating a route constraints file. The purpose of this constraints file is to specify + +#. The signals that should be constrained for routing +#. The route model for such signals + +The file is passed as an input to VPR when running with route constraints. When the file is read in, its information is used to guide VPR route or not route such signals. + +.. note:: Use the VPR option :vpr:option:`--read_vpr_constraints` to specify the VPR route constraints file that is to be loaded. + +.. note:: Wildcard names of signals are supported to specify a list of signals. The wildcard expression should follow the C/C++ regexpr rule. + diff --git a/install_apt_packages.sh b/install_apt_packages.sh index 76c705a2c34..ede554a197c 100755 --- a/install_apt_packages.sh +++ b/install_apt_packages.sh @@ -9,7 +9,9 @@ sudo apt-get install -y \ bison \ flex \ python3-dev \ - python3-venv + python3-venv \ + openssl \ + libssl-dev # Required for graphics sudo apt-get install -y \ diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index 094f7694cad..a02d6ae1cc7 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -9,6 +9,8 @@ link_libraries(${ADDITIONAL_FLAGS}) add_subdirectory(libarchfpga) add_subdirectory(libvtrutil) add_subdirectory(liblog) +add_subdirectory(libencrypt) +add_subdirectory(libdecrypt) add_subdirectory(libpugiutil) add_subdirectory(libvqm) add_subdirectory(librtlnumber) diff --git a/libs/EXTERNAL/libcatch2 b/libs/EXTERNAL/libcatch2 index 76f70b1403d..fa43b77429b 160000 --- a/libs/EXTERNAL/libcatch2 +++ b/libs/EXTERNAL/libcatch2 @@ -1 +1 @@ -Subproject commit 76f70b1403dbc0781216f49e20e45b71f7eccdd8 +Subproject commit fa43b77429ba76c462b1898d6cd2f2d7a9416b14 diff --git a/libs/EXTERNAL/sockpp b/libs/EXTERNAL/sockpp index 599f750c8b6..5388c4b5659 160000 --- a/libs/EXTERNAL/sockpp +++ b/libs/EXTERNAL/sockpp @@ -1 +1 @@ -Subproject commit 599f750c8b6532950d4bb43b2b756700e41dbae9 +Subproject commit 5388c4b5659e99a86bc906dd6ac2eef66f1dd51e diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 5a32cd2df0c..7480a8fb081 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -46,6 +46,8 @@ #include "logic_types.h" #include "clock_types.h" +#include "vib_inf.h" + //Forward declarations struct t_clock_arch; struct t_clock_network; @@ -166,8 +168,11 @@ enum e_pin_type { enum e_interconnect { COMPLETE_INTERC = 1, DIRECT_INTERC = 2, - MUX_INTERC = 3 + MUX_INTERC = 3, + NUM_INTERC_TYPES /* Invalid type */ }; +/* String version of interconnect types. Use for debugging messages */ +constexpr std::array INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}}; /* Orientations. */ enum e_side : unsigned char { @@ -1563,7 +1568,7 @@ enum e_directionality { BI_DIRECTIONAL }; /* X_AXIS: Data that describes an x-directed wire segment (CHANX) * - * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * + * Y_AXIS: Data that describes an y-directed wire segment (CHANY) * * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */ enum e_parallel_axis { X_AXIS, @@ -1695,6 +1700,24 @@ struct t_segment_inf { */ std::vector sb; + /** + * @brief This segment is bend or not + */ + bool isbend; + + /** + * @brief The bend type of the segment, "-"-0, "U"-1, "D"-2 + * For example: bend pattern <- - U ->; corresponding bend: [0,0,1,0] + */ + std::vector bend; + + /** + * @brief Divide the segment into several parts based on bend position. + * For example: length-5 bend segment: <- - U ->; + * Corresponding part_len: [3,2] + */ + std::vector part_len; + /** * @brief The index of the segment as stored in the appropriate Segs list. * Upon loading the architecture, we use this field to keep track of the @@ -1759,12 +1782,12 @@ constexpr std::array SWITCH_T /* Constant/Reserved names for switches in architecture XML * Delayless switch: - * The zero-delay switch created by VPR internally + * The zero-delay switch created by VPR internally * This is a special switch just to ease CAD algorithms * It is mainly used in - * - the edges between SOURCE and SINK nodes in routing resource graphs + * - the edges between SOURCE and SINK nodes in routing resource graphs * - the edges in CLB-to-CLB connections (defined by in arch XML) - * + * */ constexpr const char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__"; @@ -2124,7 +2147,9 @@ struct t_noc_inf { std::string noc_router_tile_name; }; -/* Detailed routing architecture */ + + +/* Detailed routing architecture */ struct t_arch { /** Stores unique strings used as key and values in tags, * i.e. implements a flyweight pattern to save memory.*/ @@ -2134,12 +2159,23 @@ struct t_arch { /// Secure hash digest of the architecture file to uniquely identify this architecture char* architecture_id; + /* Xifan Tang: options for tileable routing architectures */ + bool tileable; + bool perimeter_cb; + bool shrink_boundary; + bool through_channel; + bool opin2all_sides; + bool concat_wire; + bool concat_pass_wire; + t_chan_width_dist Chans; enum e_switch_block_type SBType; + enum e_switch_block_type SBSubType; std::vector switchblocks; float R_minW_nmos; float R_minW_pmos; int Fs; + int subFs; float grid_logic_tile_area; std::vector Segments; @@ -2198,8 +2234,14 @@ struct t_arch { //If the layout is not specified in the command line options, this variable will be set to "auto" std::string device_layout; + std::vector vib_grid_layouts; + t_clock_arch_spec clock_arch; // Clock related data types /// Stores NoC-related architectural information when there is an embedded NoC t_noc_inf* noc = nullptr; + + // added for vib + //bool is_vib_arch = false; + std::vector vib_infs; }; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 5ac6acf6b9a..cac087bf681 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -123,6 +123,11 @@ static std::pair ProcessPinString(pugi::xml_node Locations, T type, const char* pin_loc_string, const pugiutil::loc_data& loc_data); +template +static std::pair ProcessInstanceString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ static void ProcessTiles(pugi::xml_node Node, @@ -297,8 +302,24 @@ static void ProcessChanWidthDistrDir(pugi::xml_node Node, t_chan* chan, const pu static void ProcessModels(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::set& port_names, const pugiutil::loc_data& loc_data); static void ProcessLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data, int& num_of_avail_layer); + +/* Added for vib_layout*/ +static void ProcessVibLayout(pugi::xml_node Node, t_arch* arch, const pugiutil::loc_data& loc_data); + +/* Added for vib_layout*/ +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); + +/* Added for vib_layout*/ +static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, + int die_number, + vtr::string_internment& strings, + pugi::xml_node layout_block_type_tag, + const pugiutil::loc_data& loc_data); + + static t_grid_def ProcessGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer); static void ProcessBlockTypeLocs(t_grid_def& grid_def, int die_number, vtr::string_internment& strings, pugi::xml_node layout_block_type_tag, const pugiutil::loc_data& loc_data); + static int get_number_of_layers(pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data); static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& arch_def_fc, const pugiutil::loc_data& loc_data); @@ -352,6 +373,7 @@ static std::vector ProcessSegments(pugi::xml_node Parent, static void ProcessSwitchblocks(pugi::xml_node Parent, t_arch* arch, const pugiutil::loc_data& loc_data); static void ProcessCB_SB(pugi::xml_node Node, std::vector& list, const pugiutil::loc_data& loc_data); +static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector& part_len, bool& isbend, const int len, const pugiutil::loc_data& loc_data); static void ProcessPower(pugi::xml_node parent, t_power_arch* power_arch, const pugiutil::loc_data& loc_data); @@ -381,6 +403,22 @@ static e_side string_to_side(const std::string& side_str); template static T* get_type_by_name(std::string_view type_name, std::vector& types); +// static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size); + +// static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info); + +// static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info); + +// static void verify_noc_topology(std::map>& routers_in_arch_info); + +/* for vib arch */ +static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); +static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data); +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data); +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data); +// static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector& froms); +void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); + /* * * @@ -398,10 +436,10 @@ void XmlReadArch(const char* ArchFile, pugi::xml_node Next; ReqOpt POWER_REQD, SWITCHBLOCKLIST_REQD; - if (!vtr::check_file_name_extension(ArchFile, ".xml")) { + if ((vtr::check_file_name_extension(ArchFile, ".xml") == false) && (vtr::check_file_name_extension(ArchFile, ".xmle") == false)) { VTR_LOG_WARN( "Architecture file '%s' may be in incorrect format. " - "Expecting .xml format for architecture files.\n", + "Expecting .xml or .xmle format for architecture files.\n", ArchFile); } @@ -441,6 +479,12 @@ void XmlReadArch(const char* ArchFile, Next = get_single_child(architecture, "layout", loc_data); ProcessLayout(Next, arch, loc_data, num_of_avail_layers); + /* Precess vib_layout */ + Next = get_single_child(architecture, "vib_layout", loc_data, ReqOpt::OPTIONAL); + if (Next) { + ProcessVibLayout(Next, arch, loc_data); + } + /* Process device */ Next = get_single_child(architecture, "device", loc_data); ProcessDevice(Next, arch, arch_def_fc, loc_data); @@ -479,6 +523,12 @@ void XmlReadArch(const char* ArchFile, arch->directs = ProcessDirects(Next, arch->switches, loc_data); } + /* Process vib_arch */ + Next = get_single_child(architecture, "vib_arch", loc_data, ReqOpt::OPTIONAL); + if (Next) { + ProcessVibArch(Next, PhysicalTileTypes, arch, loc_data); + } + /* Process Clock Networks */ Next = get_single_child(architecture, "clocknetworks", loc_data, ReqOpt::OPTIONAL); if (Next) { @@ -708,10 +758,15 @@ static void LoadPinLoc(pugi::xml_node Locations, &sub_tile, token.c_str(), loc_data); - + /* Get the offset in the capacity range */ + auto capacity_range = ProcessInstanceString(Locations, + &sub_tile, + token.c_str(), + loc_data); + VTR_ASSERT(0 <= capacity_range.first && capacity_range.second < sub_tile_capacity); for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); - for (int capacity = 0; capacity < sub_tile_capacity; ++capacity) { + for (int capacity = capacity_range.first; capacity <= capacity_range.second; ++capacity) { int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; type->pinloc[width][height][side][physical_pin_index] = true; @@ -741,6 +796,99 @@ static void LoadPinLoc(pugi::xml_node Locations, } } +/* Parse the string to extract instance range, e.g., io[4:7] -> (4, 7) + * If no instance range is explicitly defined, we assume the range of type capacity, i.e., (0, capacity - 1) */ +template +static std::pair ProcessInstanceString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data) { + int num_tokens; + auto tokens = GetTokensFromString(pin_loc_string, &num_tokens); + + int token_index = 0; + auto token = tokens[token_index]; + + if (token.type != TOKEN_STRING || 0 != strcmp(token.data, type->name.c_str())) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Wrong physical type name of the port: %s\n", pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + int first_inst = 0; + int last_inst = type->capacity.total() - 1; + + /* If there is a dot, such as io.input[0:3], it indicates the full range of the capacity, the default value should be returned */ + if (token.type == TOKEN_DOT) { + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, last_inst); + } + + /* If the string contains index for capacity range, e.g., io[3:3].in[0:5], we skip the capacity range here. */ + if (token.type != TOKEN_OPEN_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No open square bracket present: %s\n", pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No integer to indicate least significant instance index: %s\n", pin_loc_string); + } + + first_inst = vtr::atoi(token.data); + + token_index++; + token = tokens[token_index]; + + // Single pin is specified + if (token.type != TOKEN_COLON) { + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No closing bracket: %s\n", pin_loc_string); + } + + token_index++; + + if (token_index != num_tokens) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "instance of pin location should be completed, but more tokens are present: %s\n", pin_loc_string); + } + + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, first_inst); + } + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No integer to indicate most significant instance index: %s\n", pin_loc_string); + } + + last_inst = vtr::atoi(token.data); + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "No closed square bracket: %s\n", pin_loc_string); + } + + if (first_inst > last_inst) { + std::swap(first_inst, last_inst); + } + + freeTokens(tokens, num_tokens); + return std::make_pair(first_inst, last_inst); +} + template static std::pair ProcessPinString(pugi::xml_node Locations, T type, @@ -760,6 +908,20 @@ static std::pair ProcessPinString(pugi::xml_node Locations, token_index++; token = tokens[token_index]; + /* If the string contains index for capacity range, e.g., io[3:3].in[0:5], we skip the capacity range here. */ + if (token.type == TOKEN_OPEN_SQUARE_BRACKET) { + while (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + token_index++; + token = tokens[token_index]; + if (token_index == num_tokens) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Found an open '[' but miss close ']' of the port: %s\n", pin_loc_string); + } + } + token_index++; + token = tokens[token_index]; + } + if (token.type != TOKEN_DOT) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "No dot is present to separate type name and port name: %s\n", pin_loc_string); @@ -2417,7 +2579,15 @@ static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiuti VTR_ASSERT(layout_tag.name() == std::string("layout")); //Expect no attributes on - expect_only_attributes(layout_tag, {}, loc_data); + //expect_only_attributes(layout_tag, {}, loc_data); + + arch->tileable = get_attribute(layout_tag, "tileable", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->perimeter_cb = get_attribute(layout_tag, "perimeter_cb", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->shrink_boundary = get_attribute(layout_tag, "shrink_boundary", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->through_channel = get_attribute(layout_tag, "through_channel", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->opin2all_sides = get_attribute(layout_tag, "opin2all_sides", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->concat_wire = get_attribute(layout_tag, "concat_wire", loc_data, ReqOpt::OPTIONAL).as_bool(false); + arch->concat_pass_wire = get_attribute(layout_tag, "concat_pass_wire", loc_data, ReqOpt::OPTIONAL).as_bool(false); //Count the number of or tags size_t auto_layout_cnt = 0; @@ -2825,8 +2995,9 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& // tag Cur = get_single_child(Node, "switch_block", loc_data); - expect_only_attributes(Cur, {"type", "fs"}, loc_data); + expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data); Prop = get_attribute(Cur, "type", loc_data).value(); + /* Parse attribute 'type', representing the major connectivity pattern for switch blocks */ if (strcmp(Prop, "wilton") == 0) { arch->SBType = WILTON; } else if (strcmp(Prop, "universal") == 0) { @@ -2840,9 +3011,31 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec& archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), "Unknown property %s for switch block type x\n", Prop); } + /* Parse attribute 'sub_type', representing the minor connectivity pattern for switch blocks + * If not specified, the 'sub_type' is the same as major type + * This option is only valid for tileable routing resource graph builder + * Note that sub_type does not support custom switch block pattern!!! + * If 'sub_type' is specified, the custom switch block for 'type' is not allowed! + */ + std::string sub_type_str = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).as_string(""); + if (!sub_type_str.empty()) { + if (sub_type_str == std::string("wilton")) { + arch->SBSubType = WILTON; + } else if (sub_type_str == std::string("universal")) { + arch->SBSubType = UNIVERSAL; + } else if (sub_type_str == std::string("subset")) { + arch->SBSubType = SUBSET; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur), + "Unknown property %s for switch block subtype x\n", sub_type_str.c_str()); + } + } else { + arch->SBSubType = arch->SBType; + } ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block); arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3); + arch->subFs = get_attribute(Cur, "sub_fs", loc_data, BoolToReqOpt(false)).as_int(arch->Fs); Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL); if (Cur) { @@ -3392,8 +3585,8 @@ static void ProcessPinLocations(pugi::xml_node Locations, //Verify that all top-level pins have had their locations specified - //Record all the specified pins - std::map> port_pins_with_specified_locations; + //Record all the specified pins, (capacity, port_name, index) + std::map>> port_pins_with_specified_locations; for (int l = 0; l < num_of_avail_layer; ++l) { for (int w = 0; w < PhysicalTileType->width; ++w) { for (int h = 0; h < PhysicalTileType->height; ++h) { @@ -3402,10 +3595,22 @@ static void ProcessPinLocations(pugi::xml_node Locations, InstPort inst_port(token); //A pin specification should contain only the block name, and not any instance count information + //A pin specification may contain instance count, but should be in the range of capacity + int inst_lsb = 0; + int inst_msb = SubTile->capacity.total() - 1; if (inst_port.instance_low_index() != InstPort::UNSPECIFIED || inst_port.instance_high_index() != InstPort::UNSPECIFIED) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin location specification '%s' should not contain an instance range (should only be the block name)", - token.c_str()); + /* Extract range numbers */ + inst_lsb = inst_port.instance_low_index(); + inst_msb = inst_port.instance_high_index(); + if (inst_lsb > inst_msb) { + std::swap(inst_lsb, inst_msb); + } + /* Check if we have a valid range */ + if (inst_lsb < 0 || inst_msb > SubTile->capacity.total() - 1) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin location specification '%s' contain an out-of-range instance. Expect [%d:%d]", + token.c_str(), 0, SubTile->capacity.total() - 1); + } } //Check that the block name matches @@ -3442,9 +3647,11 @@ static void ProcessPinLocations(pugi::xml_node Locations, VTR_ASSERT(pin_low_idx >= 0); VTR_ASSERT(pin_high_idx >= 0); - for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { - //Record that the pin has its location specified - port_pins_with_specified_locations[inst_port.port_name()].insert(ipin); + for (int iinst = inst_lsb + SubTile->capacity.low; iinst <= inst_msb + SubTile->capacity.low; ++iinst) { + for (int ipin = pin_low_idx; ipin <= pin_high_idx; ++ipin) { + //Record that the pin has it's location specified + port_pins_with_specified_locations[iinst][inst_port.port_name()].insert(ipin); + } } } } @@ -3453,13 +3660,15 @@ static void ProcessPinLocations(pugi::xml_node Locations, } //Check for any pins missing location specs - for (const auto& port : SubTile->ports) { - for (int ipin = 0; ipin < port.num_pins; ++ipin) { - if (!port_pins_with_specified_locations[port.name].count(ipin)) { - //Missing - archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), - "Pin '%s.%s[%d]' has no pin location specified (a location is required for pattern=\"custom\")", - SubTile->name.c_str(), port.name, ipin); + for (int iinst = SubTile->capacity.low; iinst < SubTile->capacity.high; ++iinst) { + for (const auto& port : SubTile->ports) { + for (int ipin = 0; ipin < port.num_pins; ++ipin) { + if (!port_pins_with_specified_locations[iinst][port.name].count(ipin)) { + //Missing + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Pin '%s[%d].%s[%d]' has no pin location specificed (a location is required for pattern=\"custom\")", + SubTile->name.c_str(), iinst, port.name, ipin); + } } } } @@ -3768,7 +3977,9 @@ static std::vector ProcessSegments(pugi::xml_node Parent, //Unidir requires the following tags expected_subtags.emplace_back("mux"); + expected_subtags.emplace_back("bend"); expected_subtags.emplace_back("mux_inter_die"); + //with the following two tags, we can allow the architecture file to define //different muxes with different delays for wires with different directions expected_subtags.emplace_back("mux_inc"); @@ -3901,6 +4112,15 @@ static std::vector ProcessSegments(pugi::xml_node Parent, ProcessCB_SB(SubElem, Segs[i].sb, loc_data); } + /* Setup the bend list if they give one, otherwise use default */ + if (length > 1) { + Segs[i].isbend = false; + SubElem = get_single_child(Node, "bend", loc_data, ReqOpt::OPTIONAL); + if (SubElem) { + ProcessBend(SubElem, Segs[i].bend, Segs[i].part_len, Segs[i].isbend, (length - 1), loc_data); + } + } + /*Store the index of this segment in Segs vector*/ Segs[i].seg_index = i; /* Get next Node */ @@ -3916,7 +4136,80 @@ static std::vector ProcessSegments(pugi::xml_node Parent, return Segs; } -static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb) { +static void ProcessBend(pugi::xml_node Node, std::vector& list, std::vector& part_len, bool& isbend, const int len, const pugiutil::loc_data& loc_data) { + const char* tmp = nullptr; + int i; + + tmp = get_attribute(Node, "type", loc_data).value(); + if (0 == strcmp(tmp, "pattern")) { + i = 0; + + /* Get the content string */ + tmp = Node.child_value(); + while (*tmp) { + switch (*tmp) { + case ' ': + case '\t': + case '\n': + break; + case '-': + list.push_back(0); + break; + case 'U': + list.push_back(1); + isbend = true; + break; + case 'D': + list.push_back(2); + isbend = true; + break; + case 'B': + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "B pattern is not supported in current version\n", + *tmp); + // list.push_back(3); + // isbend = true; + break; + default: + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Invalid character %c in CB or SB depopulation list.\n", + *tmp); + } + ++tmp; + } + + if (list.size() != size_t(len)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Wrong length of bend list (%d). Expect %d symbols.\n", + i, len); + } + } + + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "'%s' is not a valid type for specifying bend list.\n", + tmp); + } + + int tmp_len = 1; + int sum_len = 0; + for(size_t i_len = 0; i_len < list.size(); i_len++){ + if (list[i_len] == 0) { + tmp_len++; + } else if (list[i_len] != 0) { + VTR_ASSERT(tmp_len < (int) list.size()+1); + part_len.push_back(tmp_len); + sum_len += tmp_len; + tmp_len = 1; + } + } + + // add the last clip of segment + if (sum_len < (int) list.size()+1) + part_len.push_back(list.size() + 1 - sum_len); +} + +static void calculate_custom_SB_locations(const pugiutil::loc_data& loc_data, const pugi::xml_node& SubElem, const int grid_width, const int grid_height, t_switchblock_inf& sb){ auto startx_attr = get_attribute(SubElem, "startx", loc_data, ReqOpt::OPTIONAL); auto endx_attr = get_attribute(SubElem, "endx", loc_data, ReqOpt::OPTIONAL); @@ -4819,3 +5112,1003 @@ static T* get_type_by_name(std::string_view type_name, std::vector& types) { archfpga_throw(__FILE__, __LINE__, "Could not find type: %s\n", type_name); } + +// /* +// * Create routers and set their properties so that a mesh grid of routers is created. Then connect the routers together so that a mesh topology is created. +// */ +// static void generate_noc_mesh(pugi::xml_node mesh_topology_tag, const pugiutil::loc_data& loc_data, t_noc_inf* noc_ref, double mesh_region_start_x, double mesh_region_end_x, double mesh_region_start_y, double mesh_region_end_y, int mesh_size) { +// // check that the mesh size of the router is not 0 +// if (mesh_size == 0) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), +// "The NoC mesh size cannot be 0."); +// } + +// // calculating the vertical horizontal distances between routers in the supplied region +// // we decrease the mesh size by 1 when calculating the spacing so that the first and last routers of each row or column are positioned on the mesh boundary +// /* +// * For example: +// * - If we had a mesh size of 3, then using 3 would result in a spacing that would result in one router positions being placed in either the start of the reigion or end of the region. This is because the distance calculation resulted in having 3 spaces between the ends of the region +// * +// * start end +// *** *** *** *** +// * +// * - if we instead used 2 in the distance calculation, the the resulting positions would result in having 2 routers positioned on the start and end of the region. This is beacuse we now specified 2 spaces between the region and this allows us to place 2 routers on the regions edges and one router in the center. +// * +// * start end +// *** *** *** +// * +// * THe reasoning for this is to reduce the number of calculated router positions. +// */ +// double vertical_router_separation = (mesh_region_end_y - mesh_region_start_y) / (mesh_size - 1); +// double horizontal_router_separation = (mesh_region_end_x - mesh_region_start_x) / (mesh_size - 1); + +// t_router temp_router; + +// // improper region check +// if ((vertical_router_separation <= 0) || (horizontal_router_separation <= 0)) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(mesh_topology_tag), +// "The NoC region is invalid."); +// } + +// // create routers and their connections +// // start with router id 0 (bottom left of the chip) to the maximum router id (top right of the chip) +// for (int j = 0; j < mesh_size; j++) { +// for (int i = 0; i < mesh_size; i++) { +// // assign router id +// temp_router.id = (mesh_size * j) + i; + +// // calculate router position +// /* The first and last router of each column or row will be located on the mesh region boundary, the remaining routers will be placed within the region and seperated from other routers using the distance calculated previously. +// */ +// temp_router.device_x_position = (i * horizontal_router_separation) + mesh_region_start_x; +// temp_router.device_y_position = (j * vertical_router_separation) + mesh_region_start_y; + +// // assign connections +// // check if there is a router to the left +// if ((i - 1) >= 0) { +// // add the left router as a connection +// temp_router.connection_list.push_back((mesh_size * j) + i - 1); +// } + +// // check if there is a router to the top +// if ((j + 1) <= (mesh_size - 1)) { +// // add the top router as a connection +// temp_router.connection_list.push_back((mesh_size * (j + 1)) + i); +// } + +// // check if there is a router to the right +// if ((i + 1) <= (mesh_size - 1)) { +// // add the router located to the right +// temp_router.connection_list.push_back((mesh_size * j) + i + 1); +// } + +// // check of there is a router below +// if ((j - 1) >= (0)) { +// // add the bottom router as a connection +// temp_router.connection_list.push_back((mesh_size * (j - 1)) + i); +// } + +// // add the router to the list +// noc_ref->router_list.push_back(temp_router); + +// // clear the current router information for the next router +// temp_router.connection_list.clear(); +// } +// } + +// return; +// } + +// /* +// * THe user provides the list of routers any given router is connected to by the router ids seperated by spaces. For example: +// * +// * connections= 1 2 3 4 5 +// * +// * Go through the connections here and store them. Also make sure the list is legal. +// */ +// static bool parse_noc_router_connection_list(pugi::xml_node router_tag, const pugiutil::loc_data& loc_data, int router_id, std::vector& connection_list, std::string connection_list_attribute_value, std::map>& routers_in_arch_info) { +// // we wil be modifying the string so store it in a temporary variable +// // additinally, we peocess substrings seperated by spaces, so we add a space at the end of the string to be able to process the last sub-string +// std::string modified_attribute_value = connection_list_attribute_value + " "; +// std::string delimiter = " "; +// std::stringstream single_connection; +// int converted_connection; + +// size_t position = 0; + +// bool result = true; + +// // find the position of the first space in the connection list string +// while ((position = modified_attribute_value.find(delimiter)) != std::string::npos) { +// // the string upto the space represent a single connection, so grab the substring +// single_connection << modified_attribute_value.substr(0, position); + +// // convert the connection to an integer +// single_connection >> converted_connection; + +// /* we expect the connection list to be a string of integers seperated by spaces, where each integer represents a router id that the current router is connected to. So we make sure that the router id was an integer. +// */ +// if (single_connection.fail()) { +// // if we are here, then an integer was not supplied +// result = false; +// break; +// } + +// // check the case where a duplicate connection was provided +// if (std::find(connection_list.begin(), connection_list.end(), converted_connection) != connection_list.end()) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), +// "The router with id:'%d' was included multiple times in the connection list for another router.", converted_connection); +// } + +// // make sure that the current router isn't connected to itself +// if (router_id == converted_connection) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(router_tag), +// "The router with id:%d was added to its own connection list. A router cannot connect to itself.", router_id); +// } + +// // if we are here then a legal router id was supplied, so store it +// connection_list.push_back(converted_connection); +// // update the connection information for the current router in the connection list +// update_router_info_in_arch(converted_connection, true, routers_in_arch_info); + +// // before we process the next router connection, we need to delete the substring (current router connection) +// modified_attribute_value.erase(0, position + delimiter.length()); +// // clear the buffer that stores the router connection in a string format for the next iteration +// single_connection.clear(); +// } + +// return result; +// } + +// /* Each router needs a sperate tag in the architecture description +// * to declare it. The number of declarations for each router in the +// * architecture file is updated here. +// * +// * Additionally, for any given topology, a router can connect to other routers. +// * THe number of connections for each router is also updated here. +// * +// */ +// static void update_router_info_in_arch(int router_id, bool router_updated_as_a_connection, std::map>& routers_in_arch_info) { +// // get the corresponding router info for the given router id +// std::map>::iterator curr_router_info = routers_in_arch_info.find(router_id); + +// // check if the router previously existed in the router indo database +// if (curr_router_info == routers_in_arch_info.end()) { +// // case where the router did not exist previosuly, so we add it here and also get a reference to it +// // initially a router has no declarations or connections +// curr_router_info = routers_in_arch_info.insert(std::pair>(router_id, std::pair(0, 0))).first; +// } + +// // case where the current router was provided while parsing the connections of another router +// if (router_updated_as_a_connection) { +// // since we are within the case where the current router is being processed as a connection to another router we just increment its number of connections +// (curr_router_info->second.second)++; + +// } else { +// // since we are within the case where the current router is processed from a tag, we just increment its number of declarations +// (curr_router_info->second.first)++; +// } + +// return; +// } + +// /* +// * Verify each router in the noc by checking whether they satisfy the following conditions: +// * - The router has only one declaration in the arch file +// * - The router has atleast one connection to another router +// * If any of the conditions above are not met, then an error is thrown. +// */ +// static void verify_noc_topology(std::map>& routers_in_arch_info) { +// for (auto router_info = routers_in_arch_info.begin(); router_info != routers_in_arch_info.end(); router_info++) { +// // case where the router was included in the architecture and had no connections to other routers +// if ((router_info->second.first == 1) && (router_info->second.second == 0)) { +// archfpga_throw("", -1, +// "The router with id:'%d' is not connected to any other router in the NoC.", router_info->first); + +// } // case where a router was found to be connected to another router but not declared using the tag in the arch file (ie. missing) +// else if ((router_info->second.first == 0) && (router_info->second.second > 0)) { +// archfpga_throw("", -1, +// "The router with id:'%d' was found to be connected to another router but missing in the architecture file. Add the router using the tag.", router_info->first); + +// } // case where the router was delcared multiple times in the architecture file (multiple tags for the same router) +// else if (router_info->second.first > 1) { +// archfpga_throw("", -1, +// "The router with id:'%d' was included more than once in the architecture file. Routers should only be declared once.", router_info->first); +// } +// } + +// return; +// } + +/* for vib arch*/ +static void ProcessVibArch(pugi::xml_node Parent, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + //pugi::xml_node SubElem; + + //arch->is_vib_arch = true; + int num_vibs = count_children(Parent, "vib", loc_data); + arch->vib_infs.reserve(num_vibs); + Node = get_first_child(Parent, "vib", loc_data); + + for (int i_vib = 0; i_vib < num_vibs; i_vib++) { + ProcessVib(Node, PhysicalTileTypes, arch, loc_data); + Node = Node.next_sibling(Node.name()); + } +} + +static void ProcessVib(pugi::xml_node Vib_node, std::vector& PhysicalTileTypes, t_arch* arch, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + const char* tmp; + int itmp; + + VibInf vib; + // std::vector segments = arch->Segments; + // t_arch_switch_inf* switches = arch->Switches; + + tmp = get_attribute(Vib_node, "name", loc_data).as_string(nullptr); + if (tmp) { + vib.set_name(tmp); + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No name specified for the vib!\n"); + } + + tmp = get_attribute(Vib_node, "pbtype_name", loc_data).as_string(nullptr); + if (tmp) { + vib.set_pbtype_name(tmp); + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No pbtype_name specified for the vib!\n"); + } + + vib.set_seg_group_num(get_attribute(Vib_node, "vib_seg_group", loc_data).as_int(1)); + + tmp = get_attribute(Vib_node, "arch_vib_switch", loc_data).as_string(nullptr); + + if (tmp) { + std::string str_tmp; + str_tmp = tmp; + vib.set_switch_name(str_tmp); + // for (int i_switch = 0; i_switch < arch->num_switches; i_switch++) { + // if (!strcmp(tmp, switches[i_switch].name.c_str())) { + // vib.set_switch_idx(i_switch); + // break; + // } + // } + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Vib_node), + "No switch specified for the vib!\n"); + } + + expect_only_children(Vib_node, {"seg_group", "multistage_muxs"}, loc_data); + + int group_num = count_children(Vib_node, "seg_group", loc_data); + VTR_ASSERT(vib.get_seg_group_num() == group_num); + //vib.seg_groups.reserve(group_num); + Node = get_first_child(Vib_node, "seg_group", loc_data); + for (int i_group = 0; i_group < group_num; i_group++) { + t_seg_group seg_group; + + tmp = get_attribute(Node, "name", loc_data).as_string(nullptr); + + if (tmp) { + seg_group.name = tmp; + // for (int i_seg = 0; i_seg < (int)segments.size(); i_seg++) { + // if (segments[i_seg].name == seg_group.name) { + // seg_group.seg_index = i_seg; + // break; + // } + // } + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "No name specified for the vib seg group!\n"); + } + + seg_group.axis = BOTH_DIR; /*DEFAULT value if no axis is specified*/ + tmp = get_attribute(Node, "axis", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + + if (tmp) { + if (strcmp(tmp, "x") == 0) { + seg_group.axis = X; + } else if (strcmp(tmp, "y") == 0) { + seg_group.axis = Y; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Unsopported parralel axis type: %s\n", tmp); + } + } + + itmp = get_attribute(Node, "track_nums", loc_data).as_int(); + if (itmp) { + seg_group.track_num = itmp; + } + else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "No track_num specified for the vib seg group!\n"); + } + + vib.push_seg_group(seg_group); + + Node = Node.next_sibling(Node.name()); + } + + Node = get_single_child(Vib_node, "multistage_muxs", loc_data); + expect_only_children(Node, {"first_stage", "second_stage"}, loc_data); + + SubElem = get_single_child(Node, "first_stage", loc_data); + if (SubElem) { + std::vector first_stages; + ProcessFirstStage(SubElem, PhysicalTileTypes, first_stages, loc_data); + + for (auto first_stage : first_stages) { + vib.push_first_stage(first_stage); + } + + } + + SubElem = get_single_child(Node, "second_stage", loc_data); + if (SubElem) { + std::vector second_stages; + ProcessSecondStage(SubElem, PhysicalTileTypes, second_stages, loc_data); + + for (auto second_stage : second_stages) { + vib.push_second_stage(second_stage); + } + + } + + arch->vib_infs.push_back(vib); +} + +static void ProcessFirstStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& first_stages, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + //pugi::xml_node Cur; + //const char* tmp; + + expect_only_children(Stage_node, {"mux"}, loc_data); + int num_mux = count_children(Stage_node, "mux", loc_data); + first_stages.reserve(num_mux); + Node = get_first_child(Stage_node, "mux", loc_data); + for (int i_mux = 0; i_mux < num_mux; i_mux++) { + t_first_stage_mux_inf first_stage_mux; + first_stage_mux.mux_name = get_attribute(Node, "name", loc_data).as_string(); + + expect_only_children(Node, {"from"}, loc_data); + SubElem = get_first_child(Node, "from", loc_data); + int from_num = count_children(Node, "from", loc_data); + for (int i_from = 0; i_from < from_num; i_from++) { + std::vector from_tokens = vtr::split(SubElem.child_value()); + first_stage_mux.from_tokens.push_back(from_tokens); + //ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, first_stage_mux.froms); + SubElem = SubElem.next_sibling(SubElem.name()); + } + first_stages.push_back(first_stage_mux); + + Node = Node.next_sibling(Node.name()); + } +} + +static void ProcessSecondStage(pugi::xml_node Stage_node, std::vector& PhysicalTileTypes, std::vector& second_stages, const pugiutil::loc_data& loc_data) { + pugi::xml_node Node; + pugi::xml_node SubElem; + //pugi::xml_node Cur; + //const char* tmp; + + expect_only_children(Stage_node, {"mux"}, loc_data); + int num_mux = count_children(Stage_node, "mux", loc_data); + second_stages.reserve(num_mux); + Node = get_first_child(Stage_node, "mux", loc_data); + for (int i_mux = 0; i_mux < num_mux; i_mux++) { + t_second_stage_mux_inf second_stage_mux; + second_stage_mux.mux_name = get_attribute(Node, "name", loc_data).as_string(); + + expect_only_children(Node, {"to", "from"}, loc_data); + + SubElem = get_first_child(Node, "to", loc_data); + int to_num = count_children(Node, "to", loc_data); + VTR_ASSERT(to_num == 1); + std::vector to_tokens = vtr::split(SubElem.child_value()); + VTR_ASSERT(to_tokens.size() == 1); + second_stage_mux.to_tokens = to_tokens; + // std::vector tos; + + // ProcessFromOrToTokens(to_tokens, PhysicalTileTypes, segments, tos); + // for (auto to : tos) { + // //VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); + // second_stage_mux.to.push_back(to); + // } + + SubElem = get_first_child(Node, "from", loc_data); + int from_num = count_children(Node, "from", loc_data); + for (int i_from = 0; i_from < from_num; i_from++) { + std::vector from_tokens = vtr::split(SubElem.child_value()); + second_stage_mux.from_tokens.push_back(from_tokens); + //ProcessFromOrToTokens(from_tokens, PhysicalTileTypes, segments, second_stage_mux.froms); + SubElem = SubElem.next_sibling(SubElem.name()); + } + + second_stages.push_back(second_stage_mux); + + Node = Node.next_sibling(Node.name()); + } +} + +// static void ProcessFromOrToTokens(const std::vector Tokens, std::vector& PhysicalTileTypes, std::vector segments, std::vector& froms) { +// for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { +// std::string Token = Tokens[i_token]; +// const char* Token_char = Token.c_str(); +// auto token = vtr::split(Token, "."); +// if (token.size() == 1) { +// t_from_or_to_inf from_inf; +// from_inf.type_name = token[0]; +// from_inf.from_type = MUX; +// froms.push_back(from_inf); +// } +// else if (token.size() == 2) { +// std::string from_type_name = token[0]; +// e_multistage_mux_from_or_to_type from_type; +// for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { +// if (from_type_name == PhysicalTileTypes[i_phy_type].name) { +// from_type = PB; +// int start_pin_index, end_pin_index; +// char *pb_type_name, *port_name; +// pb_type_name = nullptr; +// port_name = nullptr; +// pb_type_name = new char[strlen(Token_char)]; +// port_name = new char[strlen(Token_char)]; +// parse_pin_name((char*)Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + +// std::vector all_sub_tile_to_tile_pin_indices; +// for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { +// int sub_tile_capacity = sub_tile.capacity.total(); + +// int start = 0; +// int end = 0; +// int i_port = 0; +// for (; i_port < (int)sub_tile.ports.size(); ++i_port) { +// if (!strcmp(sub_tile.ports[i_port].name, port_name)) { +// start = sub_tile.ports[i_port].absolute_first_pin_index; +// end = start + sub_tile.ports[i_port].num_pins - 1; +// break; +// } +// } +// if (i_port == (int)sub_tile.ports.size()) { +// continue; +// } +// for (int pin_num = start; pin_num <= end; ++pin_num) { +// VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); +// for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { +// int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; +// int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; +// all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); +// } +// } +// } + +// if (start_pin_index == end_pin_index && start_pin_index < 0) { +// start_pin_index = 0; +// end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; +// } + +// if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { +// VTR_LOGF_ERROR(__FILE__, __LINE__, +// "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); +// } + +// for (int i = start_pin_index; i <= end_pin_index; i++) { +// t_from_or_to_inf from_inf; +// from_inf.type_name = from_type_name; +// from_inf.from_type = from_type; +// from_inf.type_index = i_phy_type; +// from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; +// froms.push_back(from_inf); +// } + +// // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { +// // //int sub_tile_index = sub_tile.index; +// // int sub_tile_capacity = sub_tile.capacity.total(); + +// // int i_port = 0; +// // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + +// // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { +// // if (start_pin_index == end_pin_index && start_pin_index < 0) { +// // start_pin_index = 0; +// // end_pin_index = sub_tile.ports[i_port].num_pins - 1; +// // } +// // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; +// // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; +// // break; +// // } +// // } + +// // if (i_port == (int)sub_tile.ports.size()) { +// // continue; +// // } + +// // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { +// // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); +// // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { +// // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; +// // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; +// // t_from_or_to_inf from_inf; +// // from_inf.type_name = from_type_name; +// // from_inf.from_type = from_type; +// // from_inf.type_index = i_phy_type; +// // from_inf.phy_pin_index = physical_pin_index; +// // froms.push_back(from_inf); +// // } +// // } +// // } + +// } +// } +// for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { +// if (from_type_name == segments[i_seg_type].name) { +// from_type = SEGMENT; +// std::string from_detail = token[1]; +// if (from_detail.length() >= 2) { +// char dir = from_detail.c_str()[0]; +// from_detail.erase(from_detail.begin()); +// int seg_index = std::stoi(from_detail); + +// t_from_or_to_inf from_inf; +// from_inf.type_name = from_type_name; +// from_inf.from_type = from_type; +// from_inf.type_index = i_seg_type; +// from_inf.seg_dir = dir; +// from_inf.seg_index = seg_index; +// froms.push_back(from_inf); +// } + +// break; +// } +// } +// VTR_ASSERT(from_type == PB || from_type == SEGMENT); + +// } +// else { +// std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); +// throw ArchFpgaError(msg); +// } +// } +// } + +void parse_pin_name(char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { + /* Parses out the pb_type_name and port_name * + * If the start_pin_index and end_pin_index is specified, parse them too. * + * Return the values parsed by reference. */ + + char* source_string = nullptr; + char* find_format = nullptr; + int ichar, match_count; + + // parse out the pb_type and port name, possibly pin_indices + find_format = strstr(src_string, "["); + if (find_format == nullptr) { + /* Format "pb_type_name.port_name" */ + *start_pin_index = *end_pin_index = -1; + + + strcpy(source_string, src_string); + + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); + if (match_count != 2) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } else { + /* Format "pb_type_name.port_name[end_pin_index:start_pin_index]" */ + strcpy(source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + //Need white space between the components when using %s with + //sscanf + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + if (source_string[ichar] == '[') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s %d:%d]", + pb_type_name, port_name, + end_pin_index, start_pin_index); + if (match_count != 4) { + match_count = sscanf(source_string, "%s %s %d]", + pb_type_name, port_name, + end_pin_index); + *start_pin_index = *end_pin_index; + if (match_count != 3) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } + if (*end_pin_index < 0 || *start_pin_index < 0) { + VTR_LOG_ERROR( + "Invalid pin - %s, the pin_index in " + "[end_pin_index:start_pin_index] should not be a negative value.\n", + src_string); + exit(1); + } + if (*end_pin_index < *start_pin_index) { + int temp; + temp = *end_pin_index; + *end_pin_index = *start_pin_index; + *start_pin_index = temp; + } + } +} + +/* Process vib layout */ +static void ProcessVibLayout(pugi::xml_node vib_layout_tag, t_arch* arch, const pugiutil::loc_data& loc_data) { + VTR_ASSERT(vib_layout_tag.name() == std::string("vib_layout")); + + size_t auto_layout_cnt = 0; + size_t fixed_layout_cnt = 0; + for (auto layout_type_tag : vib_layout_tag.children()) { + if (layout_type_tag.name() == std::string("auto_layout")) { + ++auto_layout_cnt; + } else if (layout_type_tag.name() == std::string("fixed_layout")) { + ++fixed_layout_cnt; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "Unexpected tag type '<%s>', expected '' or ''", layout_type_tag.name()); + } + } + + if (auto_layout_cnt == 0 && fixed_layout_cnt == 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(vib_layout_tag), + "Expected either an or tag"); + } + if (auto_layout_cnt > 1) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(vib_layout_tag), + "Expected at most one tag"); + } + VTR_ASSERT_MSG(auto_layout_cnt == 0 || auto_layout_cnt == 1, " may appear at most once"); + + // for (auto vib_layout_type_tag : vib_layout_tag.children()) { + // for (auto grid_layout : arch->grid_layouts) { + // std::string layout_name = grid_layout.name; + // } + // } + + int num_of_avail_layer; + + for (auto vib_layout_type_tag : vib_layout_tag.children()) { + t_vib_grid_def grid_def = ProcessVibGridLayout(arch->strings, vib_layout_type_tag, loc_data, arch, num_of_avail_layer); + + arch->vib_grid_layouts.emplace_back(std::move(grid_def)); + } + +} + +static t_vib_grid_def ProcessVibGridLayout(vtr::string_internment& strings, pugi::xml_node layout_type_tag, const pugiutil::loc_data& loc_data, t_arch* arch, int& num_of_avail_layer) { + t_vib_grid_def grid_def; + num_of_avail_layer = get_number_of_layers(layout_type_tag, loc_data); + bool has_layer = layout_type_tag.child("layer"); + + //Determine the grid specification type + if (layout_type_tag.name() == std::string("auto_layout")) { + //expect_only_attributes(layout_type_tag, {"aspect_ratio"}, loc_data); + + grid_def.grid_type = VibGridDefType::VIB_AUTO; + grid_def.name = "auto"; + + for (size_t i = 0;i < arch->grid_layouts.size(); i++) { + if (arch->grid_layouts[i].name == grid_def.name) { + grid_def.aspect_ratio = arch->grid_layouts[i].aspect_ratio; + } + } + //grid_def.aspect_ratio = get_attribute(layout_type_tag, "aspect_ratio", loc_data, ReqOpt::OPTIONAL).as_float(1.); + + } else if (layout_type_tag.name() == std::string("fixed_layout")) { + expect_only_attributes(layout_type_tag, {"name"}, loc_data); + + grid_def.grid_type = VibGridDefType::VIB_FIXED; + //grid_def.width = get_attribute(layout_type_tag, "width", loc_data).as_int(); + //grid_def.height = get_attribute(layout_type_tag, "height", loc_data).as_int(); + std::string name = get_attribute(layout_type_tag, "name", loc_data).value(); + + if (name == "auto") { + //We name as 'auto', so don't allow a user to specify it + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "The name '%s' is reserved for auto-sized layouts; please choose another name"); + } + + for (size_t i = 0; i < arch->grid_layouts.size(); i++) { + if (arch->grid_layouts[i].name == name) { + grid_def.width = arch->grid_layouts[i].width; + grid_def.height = arch->grid_layouts[i].height; + } + } + grid_def.name = name; + + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(layout_type_tag), + "Unexpected tag '<%s>'. Expected '' or ''.", + layout_type_tag.name()); + } + + grid_def.layers.resize(num_of_avail_layer); + arch->layer_global_routing.resize(num_of_avail_layer); + //No layer tag is specified (only one die is specified in the arch file) + //Need to process layout_type_tag children to get block types locations in the grid + if (has_layer) { + std::set seen_die_numbers; //Check that die numbers in the specific layout tag are unique + //One or more than one layer tag is specified + auto layer_tag_specified = layout_type_tag.children("layer"); + for (auto layer_child : layer_tag_specified) { + int die_number; + bool has_global_routing; + //More than one layer tag is specified, meaning that multi-die FPGA is specified in the arch file + //Need to process each tag children to get block types locations for each grid + die_number = get_attribute(layer_child, "die", loc_data).as_int(0); + has_global_routing = get_attribute(layer_child, "has_prog_routing", loc_data, ReqOpt::OPTIONAL).as_bool(true); + arch->layer_global_routing.at(die_number) = has_global_routing; + VTR_ASSERT(die_number >= 0 && die_number < num_of_avail_layer); + auto insert_res = seen_die_numbers.insert(die_number); + VTR_ASSERT_MSG(insert_res.second, "Two different layers with a same die number may have been specified in the Architecture file"); + ProcessVibBlockTypeLocs(grid_def, die_number, strings, layer_child, loc_data); + } + } else { + //if only one die is available, then global routing resources must exist in that die + int die_number = 0; + arch->layer_global_routing.at(die_number) = true; + ProcessVibBlockTypeLocs(grid_def, die_number, strings, layout_type_tag, loc_data); + } + return grid_def; +} + +static void ProcessVibBlockTypeLocs(t_vib_grid_def& grid_def, + int die_number, + vtr::string_internment& strings, + pugi::xml_node layout_block_type_tag, + const pugiutil::loc_data& loc_data) { + //Process all the block location specifications + for (auto loc_spec_tag : layout_block_type_tag.children()) { + auto loc_type = loc_spec_tag.name(); + auto type_name = get_attribute(loc_spec_tag, "type", loc_data).value(); + int priority = get_attribute(loc_spec_tag, "priority", loc_data).as_int(); + t_metadata_dict meta = ProcessMetadata(strings, loc_spec_tag, loc_data); + + if (loc_type == std::string("perimeter")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + //The edges + t_vib_grid_loc_def left_edge(type_name, priority); //Including corners + left_edge.x.start_expr = "0"; + left_edge.x.end_expr = "0"; + left_edge.y.start_expr = "0"; + left_edge.y.end_expr = "H - 1"; + + t_vib_grid_loc_def right_edge(type_name, priority); //Including corners + right_edge.x.start_expr = "W - 1"; + right_edge.x.end_expr = "W - 1"; + right_edge.y.start_expr = "0"; + right_edge.y.end_expr = "H - 1"; + + t_vib_grid_loc_def bottom_edge(type_name, priority); //Exclucing corners + bottom_edge.x.start_expr = "1"; + bottom_edge.x.end_expr = "W - 2"; + bottom_edge.y.start_expr = "0"; + bottom_edge.y.end_expr = "0"; + + t_vib_grid_loc_def top_edge(type_name, priority); //Excluding corners + top_edge.x.start_expr = "1"; + top_edge.x.end_expr = "W - 2"; + top_edge.y.start_expr = "H - 1"; + top_edge.y.end_expr = "H - 1"; + + // left_edge.owned_meta = std::make_unique(meta); + // left_edge.meta = left_edge.owned_meta.get(); + // right_edge.meta = left_edge.owned_meta.get(); + // top_edge.meta = left_edge.owned_meta.get(); + // bottom_edge.meta = left_edge.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(left_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(right_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_edge)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_edge)); + + } else if (loc_type == std::string("corners")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + //The corners + t_vib_grid_loc_def bottom_left(type_name, priority); + bottom_left.x.start_expr = "0"; + bottom_left.x.end_expr = "0"; + bottom_left.y.start_expr = "0"; + bottom_left.y.end_expr = "0"; + + t_vib_grid_loc_def top_left(type_name, priority); + top_left.x.start_expr = "0"; + top_left.x.end_expr = "0"; + top_left.y.start_expr = "H-1"; + top_left.y.end_expr = "H-1"; + + t_vib_grid_loc_def bottom_right(type_name, priority); + bottom_right.x.start_expr = "W-1"; + bottom_right.x.end_expr = "W-1"; + bottom_right.y.start_expr = "0"; + bottom_right.y.end_expr = "0"; + + t_vib_grid_loc_def top_right(type_name, priority); + top_right.x.start_expr = "W-1"; + top_right.x.end_expr = "W-1"; + top_right.y.start_expr = "H-1"; + top_right.y.end_expr = "H-1"; + + // bottom_left.owned_meta = std::make_unique(meta); + // bottom_left.meta = bottom_left.owned_meta.get(); + // top_left.meta = bottom_left.owned_meta.get(); + // bottom_right.meta = bottom_left.owned_meta.get(); + // top_right.meta = bottom_left.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_left)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_left)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(bottom_right)); + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(top_right)); + + } else if (loc_type == std::string("fill")) { + expect_only_attributes(loc_spec_tag, {"type", "priority"}, loc_data); + + t_vib_grid_loc_def fill(type_name, priority); + fill.x.start_expr = "0"; + fill.x.end_expr = "W - 1"; + fill.y.start_expr = "0"; + fill.y.end_expr = "H - 1"; + + // fill.owned_meta = std::make_unique(meta); + // fill.meta = fill.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(fill)); + + } else if (loc_type == std::string("single")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "x", "y"}, loc_data); + + t_vib_grid_loc_def single(type_name, priority); + single.x.start_expr = get_attribute(loc_spec_tag, "x", loc_data).value(); + single.y.start_expr = get_attribute(loc_spec_tag, "y", loc_data).value(); + single.x.end_expr = single.x.start_expr + " + w - 1"; + single.y.end_expr = single.y.start_expr + " + h - 1"; + + // single.owned_meta = std::make_unique(meta); + // single.meta = single.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(single)); + + } else if (loc_type == std::string("col")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "startx", "repeatx", "starty", "incry"}, loc_data); + + t_vib_grid_loc_def col(type_name, priority); + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data); + + col.x.start_expr = startx_attr.value(); + col.x.end_expr = startx_attr.value() + std::string(" + w - 1"); //end is inclusive so need to include block width + + auto repeat_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL); + if (repeat_attr) { + col.x.repeat_expr = repeat_attr.value(); + } + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL); + if (starty_attr) { + col.y.start_expr = starty_attr.value(); + } + + auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL); + if (incry_attr) { + col.y.incr_expr = incry_attr.value(); + } + + // col.owned_meta = std::make_unique(meta); + // col.meta = col.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(col)); + + } else if (loc_type == std::string("row")) { + expect_only_attributes(loc_spec_tag, {"type", "priority", "starty", "repeaty", "startx", "incrx"}, loc_data); + + t_vib_grid_loc_def row(type_name, priority); + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data); + + row.y.start_expr = starty_attr.value(); + row.y.end_expr = starty_attr.value() + std::string(" + h - 1"); //end is inclusive so need to include block height + + auto repeat_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL); + if (repeat_attr) { + row.y.repeat_expr = repeat_attr.value(); + } + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL); + if (startx_attr) { + row.x.start_expr = startx_attr.value(); + } + + auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL); + if (incrx_attr) { + row.x.incr_expr = incrx_attr.value(); + } + + // row.owned_meta = std::make_unique(meta); + // row.meta = row.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(row)); + } else if (loc_type == std::string("region")) { + expect_only_attributes(loc_spec_tag, + {"type", "priority", + "startx", "endx", "repeatx", "incrx", + "starty", "endy", "repeaty", "incry"}, + loc_data); + t_vib_grid_loc_def region(type_name, priority); + + auto startx_attr = get_attribute(loc_spec_tag, "startx", loc_data, ReqOpt::OPTIONAL); + if (startx_attr) { + region.x.start_expr = startx_attr.value(); + } + + auto endx_attr = get_attribute(loc_spec_tag, "endx", loc_data, ReqOpt::OPTIONAL); + if (endx_attr) { + region.x.end_expr = endx_attr.value(); + } + + auto starty_attr = get_attribute(loc_spec_tag, "starty", loc_data, ReqOpt::OPTIONAL); + if (starty_attr) { + region.y.start_expr = starty_attr.value(); + } + + auto endy_attr = get_attribute(loc_spec_tag, "endy", loc_data, ReqOpt::OPTIONAL); + if (endy_attr) { + region.y.end_expr = endy_attr.value(); + } + + auto repeatx_attr = get_attribute(loc_spec_tag, "repeatx", loc_data, ReqOpt::OPTIONAL); + if (repeatx_attr) { + region.x.repeat_expr = repeatx_attr.value(); + } + + auto repeaty_attr = get_attribute(loc_spec_tag, "repeaty", loc_data, ReqOpt::OPTIONAL); + if (repeaty_attr) { + region.y.repeat_expr = repeaty_attr.value(); + } + + auto incrx_attr = get_attribute(loc_spec_tag, "incrx", loc_data, ReqOpt::OPTIONAL); + if (incrx_attr) { + region.x.incr_expr = incrx_attr.value(); + } + + auto incry_attr = get_attribute(loc_spec_tag, "incry", loc_data, ReqOpt::OPTIONAL); + if (incry_attr) { + region.y.incr_expr = incry_attr.value(); + } + + // region.owned_meta = std::make_unique(meta); + // region.meta = region.owned_meta.get(); + + grid_def.layers.at(die_number).loc_defs.emplace_back(std::move(region)); + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(loc_spec_tag), + "Unrecognized grid location specification type '%s'\n", loc_type); + } + } +} + diff --git a/libs/libarchfpga/src/vib_inf.cpp b/libs/libarchfpga/src/vib_inf.cpp new file mode 100644 index 00000000000..4fcebadfebd --- /dev/null +++ b/libs/libarchfpga/src/vib_inf.cpp @@ -0,0 +1,136 @@ +#include "vib_inf.h" +// #include "vtr_math.h" +// #include "vtr_util.h" +// #include "vtr_log.h" + +// #include "arch_util.h" + +VibInf::VibInf() { + name_.clear(); + pbtype_name_.clear(); + seg_group_num_ = 0; + switch_idx_ = -1; + seg_groups_.clear(); + first_stages_.clear(); + second_stages_.clear(); +} + +void VibInf::set_name(const std::string name) { + VTR_ASSERT(!name.empty()); + name_ = name; +} + +void VibInf::set_pbtype_name(const std::string pbtype_name) { + VTR_ASSERT(!pbtype_name.empty()); + pbtype_name_ = pbtype_name; +} + +void VibInf::set_seg_group_num(const int seg_group_num) { + VTR_ASSERT(seg_group_num >= 0); + seg_group_num_ = seg_group_num; +} + +void VibInf::set_switch_idx(const int switch_idx) { + VTR_ASSERT(switch_idx != -1); + switch_idx_ = switch_idx; +} + +void VibInf::set_switch_name(const std::string switch_name) { + VTR_ASSERT(!switch_name.empty()); + switch_name_ = switch_name; +} + +void VibInf::set_seg_groups(const std::vector seg_groups) { + VTR_ASSERT(!seg_groups.empty()); + seg_groups_.clear(); + for(auto seg_group : seg_groups) { + seg_groups_.push_back(seg_group); + } +} + +void VibInf::push_seg_group(const t_seg_group seg_group) { + VTR_ASSERT(!seg_group.name.empty()); + seg_groups_.push_back(seg_group); +} + +void VibInf::set_first_stages(const std::vector first_stages) { + VTR_ASSERT(!first_stages.empty()); + first_stages_.clear(); + for(auto first_stage : first_stages) { + first_stages_.push_back(first_stage); + } +} + +void VibInf::push_first_stage(const t_first_stage_mux_inf first_stage) { + VTR_ASSERT(!first_stage.mux_name.empty()); + first_stages_.push_back(first_stage); +} + +void VibInf::set_second_stages(const std::vector second_stages) { + VTR_ASSERT(!second_stages.empty()); + second_stages_.clear(); + for(auto second_stage : second_stages) { + second_stages_.push_back(second_stage); + } +} + +void VibInf::push_second_stage(const t_second_stage_mux_inf second_stage) { + VTR_ASSERT(!second_stage.mux_name.empty()); + second_stages_.push_back(second_stage); +} + +std::string VibInf::get_name() const{ + VTR_ASSERT(!name_.empty()); + return name_; +} + +std::string VibInf::get_pbtype_name() const{ + VTR_ASSERT(!pbtype_name_.empty()); + return pbtype_name_; +} + +int VibInf::get_seg_group_num() const{ + VTR_ASSERT(seg_group_num_ >= 0); + return seg_group_num_; +} + +int VibInf::get_switch_idx() const{ + VTR_ASSERT(switch_idx_ != -1); + return switch_idx_; +} + +std::string VibInf::get_switch_name() const{ + VTR_ASSERT(!switch_name_.empty()); + return switch_name_; +} + +std::vector VibInf::get_seg_groups() const{ + VTR_ASSERT(!seg_groups_.empty()); + return seg_groups_; +} + +std::vector VibInf::get_first_stages() const{ + VTR_ASSERT(!first_stages_.empty()); + return first_stages_; +} + +std::vector VibInf::get_second_stages() const{ + VTR_ASSERT(!second_stages_.empty()); + return second_stages_; +} + +size_t VibInf::medium_mux_index_by_name(const std::string& name) const{ + for (size_t i_medium = 0; i_medium < first_stages_.size(); ++i_medium) { + if (name == first_stages_[i_medium].mux_name) { + return i_medium; + } + } + VTR_LOG_ERROR("No medium mux named %s!", name.c_str()); +} + + +VibDeviceGrid::VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid) + : name_(std::move(grid_name)) + , vib_grid_(std::move(vib_grid)) { + +} diff --git a/libs/libarchfpga/src/vib_inf.h b/libs/libarchfpga/src/vib_inf.h new file mode 100644 index 00000000000..d4766fb7f88 --- /dev/null +++ b/libs/libarchfpga/src/vib_inf.h @@ -0,0 +1,290 @@ +#ifndef VIB_INF_H +#define VIB_INF_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "vtr_ndmatrix.h" +#include "vtr_hash.h" +#include "vtr_bimap.h" +#include "vtr_string_interning.h" +#include "vtr_log.h" + +#include "logic_types.h" +#include "clock_types.h" + +//#include "physical_types.h" + + + +/* for vib tag */ +enum e_parallel_axis_vib { + X, + Y, + BOTH_DIR +}; + +struct t_seg_group { + std::string name; + e_parallel_axis_vib axis; + int seg_index; + int track_num; +}; + +enum e_multistage_mux_from_or_to_type { + PB = 0, + SEGMENT, + MUX +}; + +struct t_from_or_to_inf { + std::string type_name; + e_multistage_mux_from_or_to_type from_type; //from_or_to_type + int type_index = -1; + int phy_pin_index = -1; + char seg_dir = ' '; + int seg_index = -1; +}; + +struct t_first_stage_mux_inf { + std::string mux_name; + std::vector> from_tokens; + std::vector froms; +}; + +struct t_second_stage_mux_inf : t_first_stage_mux_inf { + std::vector to_tokens; + std::vector to; // for io type, port[pin] may map to several sinks +}; + +// struct t_vib_inf { +// std::string name; /* vib name */ +// std::string pbtype_name; /* pbtype name of vib */ +// int seg_group_num; /* seg group number of vib */ +// int switch_idx; /* vib switch index */ +// std::vector seg_groups; +// std::vector first_stages; +// std::vector second_stages; +// }; + +/* VibInf is used to reserve the VIB information. * + * For example, a VIB is described: * + * + + + + + + + L1.E0 L1.E1 + clb.O[0] L1.E2 + + + clb.I[0] MUX0 MUX1 + L1.N0 MUX0 MUX1 + + + + + Its corresponding figure is shown: + + * | L1.N0 + * +-----------------|-------+ + * L1.E0-----------------|>|\ MUX-1 _| vib0|----------\ + * L1.E1-----------------|>| |----| /__\ |... } l1: 20 tracks + * | |/ | | | | / + * | MUX0 |-------| | |----------\ + * L1.E2-----------------|>|\ | | |... } l2: 20 tracks + * | | |--| | | | / + * |------------------|>|/ | | | |----------\ + * | | MUX1 |-|---------| |... } l4: 16 tracks + * | | | | | / + * | ... | | | |----------\ + * | | _|_| |... } l8: 16 tracks + * | | \__/ MUX-0 | / + * | +-------------------------+ + * O[0]| | + * +-------------+ | + * | |<---------------------- + * | clb | I[0] + * +-------------+ + * + * Attributes: + * name_: The name of the VIB type, "vib0" in the example. + * pbtype_name_: The pbtype of the VIB, "clb" in the example. + * seg_group_num_: The number of segment groups. + * seg_groups_: The segments applied in the VIB. Their names correspond to segment names in . + * switch_name_:The name of the switch type used in the VIB, "mux0" in the example. + * switch_idx_: The index of corresponding switch in . + * first_stages_: The info of first stage MUXes, including the names of the MUXes and their from info. + * second_stages_: The info of second stage MUXes, including the names of the MUXes and their from/to info.*/ + +class VibInf { + public: + VibInf(); + + public: + void set_name(const std::string name); + void set_pbtype_name(const std::string pbtype_name); + void set_seg_group_num(const int seg_group_num); + void set_switch_idx(const int switch_idx); + void set_switch_name(const std::string switch_name); + void set_seg_groups(const std::vector seg_groups); + void push_seg_group(const t_seg_group seg_group); + void set_first_stages(const std::vector first_stages); + void push_first_stage(const t_first_stage_mux_inf first_stage); + void set_second_stages(const std::vector second_stages); + void push_second_stage(const t_second_stage_mux_inf second_stage); + + std::string get_name() const; + std::string get_pbtype_name() const; + int get_seg_group_num() const; + int get_switch_idx() const; + std::string get_switch_name() const; + std::vector get_seg_groups() const; + std::vector get_first_stages() const; + std::vector get_second_stages() const; + size_t medium_mux_index_by_name(const std::string& name) const; + + + private: + std::string name_; /* vib name */ + std::string pbtype_name_; /* pbtype name of vib */ + int seg_group_num_; /* seg group number of vib */ + int switch_idx_; /* vib switch index */ + std::string switch_name_; /* vib switch name */ + std::vector seg_groups_; + std::vector first_stages_; + std::vector second_stages_; +}; + +/************************* VIB_GRID ***********************************/ +/* Describe different VIB type on different locations by immitating t_grid_loc_def. */ + +struct t_vib_grid_loc_spec { + t_vib_grid_loc_spec(std::string start, std::string end, std::string repeat, std::string incr) + : start_expr(std::move(start)) + , end_expr(std::move(end)) + , repeat_expr(std::move(repeat)) + , incr_expr(std::move(incr)) {} + + std::string start_expr; //Starting position (inclusive) + std::string end_expr; //Ending position (inclusive) + + std::string repeat_expr; //Distance between repeated + // region instances + + std::string incr_expr; //Distance between block instantiations + // with the region +}; + +enum VibGridDefType { + VIB_AUTO, + VIB_FIXED +}; + +struct t_vib_grid_loc_def { + t_vib_grid_loc_def(std::string block_type_val, int priority_val) + : block_type(block_type_val) + , priority(priority_val) + , x("0", "W-1", "max(w+1,W)", "w") //Fill in x direction, no repeat, incr by block width + , y("0", "H-1", "max(h+1,H)", "h") //Fill in y direction, no repeat, incr by block height + {} + + std::string block_type; //The block type name + + int priority = 0; //Priority of the specification. + // In case of conflicting specifications + // the largest priority wins. + + t_vib_grid_loc_spec x; //Horizontal location specification + t_vib_grid_loc_spec y; //Veritcal location specification + +}; + +struct t_vib_layer_def { + std::vector loc_defs; //The list of block location definitions for this layer specification +}; + +struct t_vib_grid_def { + VibGridDefType grid_type = VibGridDefType::VIB_AUTO; //The type of this grid specification + + std::string name = ""; //The name of this device + + int width = -1; //Fixed device width (only valid for grid_type == FIXED) + int height = -1; //Fixed device height (only valid for grid_type == FIXED) + + float aspect_ratio = 1.; //Aspect ratio for auto-sized devices (only valid for + //grid_type == AUTO) + std::vector layers; +}; + +///@brief DeviceGrid represents the FPGA fabric. It is used to get information about different layers and tiles. +// TODO: All of the function that use helper functions of this class should pass the layer_num to the functions, and the default value of layer_num should be deleted eventually. +class VibDeviceGrid { + public: + VibDeviceGrid() = default; + VibDeviceGrid(std::string grid_name, vtr::NdMatrix vib_grid); + + const std::string& name() const { return name_; } + + ///@brief Return the number of layers(number of dies) + inline int get_num_layers() const { + return (int)vib_grid_.dim_size(0); + } + + ///@brief Return the width of the grid at the specified layer + size_t width() const { return vib_grid_.dim_size(1); } + ///@brief Return the height of the grid at the specified layer + size_t height() const { return vib_grid_.dim_size(2); } + + ///@brief Return the size of the flattened grid on the given layer + inline size_t grid_size() const { + return vib_grid_.size(); + } + + const VibInf* get_vib(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]; + } + + size_t num_medium_nodes(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]->get_first_stages().size(); + } + + std::string medium_node_name(size_t layer, size_t x, size_t y, size_t medium_index) const { + return vib_grid_[layer][x][y]->get_first_stages()[medium_index].mux_name; + } + + std::string vib_pbtype_name(size_t layer, size_t x, size_t y) const { + return vib_grid_[layer][x][y]->get_pbtype_name(); + } + + bool is_empty() const { + return vib_grid_.empty(); + } + + private: + + std::string name_; + + /** + * @brief grid_ is a 3D matrix that represents the grid of the FPGA chip. + * @note The first dimension is the layer number (grid_[0] corresponds to the bottom layer), the second dimension is the x coordinate, and the third dimension is the y coordinate. + * @note Note that vtr::Matrix operator[] returns and intermediate type + * @note which can be used for indexing in the second dimension, allowing + * @note traditional 2-d indexing to be used + */ + vtr::NdMatrix vib_grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1] + +}; + +#endif diff --git a/libs/libdecrypt/ README.md b/libs/libdecrypt/ README.md new file mode 100644 index 00000000000..e6a4193bf43 --- /dev/null +++ b/libs/libdecrypt/ README.md @@ -0,0 +1,98 @@ + # libdecrypt + +libdecrypt is a C++ library for decrypting encrypted files. It provides a simple interface to decrypt files using OpenSSL for encryption and decryption operations and pugixml for XML parsing. + +## Features + +- Decrypts encrypted files using RSA encryption algorithm. +- Supports loading private key from PEM string. +- Retrieves encrypted data and session key from XML file. +- Decrypts session key using RSA private key. +- Decrypts XML string using the decrypted session key. +- Outputs the decrypted content as a string. + +## Installation + +1. Build the library using CMake + + cd libdecrypt + mkdir build + cd build + cmake .. + make +2. Install the library (optional): + + make install +## Dependencies + +Make sure you have the following dependencies installed on your system: + +- **OpenSSL**: The library depends on OpenSSL for encryption and decryption operations. Make sure you have OpenSSL installed on your system. + +- **pugixml**: The library uses pugixml for XML parsing. It is included as a submodule in the project. + +## Usage + +To use the `libdecrypt` library in your C++ projects, follow the steps below: + +1. Include the `decryption.h` header file in your source code: + + ```cpp + #include "decryption.h" + +2. Create a `Decryption` object with the path to the encrypted file: + + std::string encryptedFile = "path/to/encrypted/file"; + Decryption decryption(encryptedFile); + +3. Decrypt the contents of the encrypted file: + + decryption.decryptFile(); + +4. Retrieve the decrypted content as a string: + + std::string decryptedContent = decryption.getDecryptedContent(); + +5. Optional: Write the decrypted content to a file: + + std::ofstream outputFile("output.txt"); + outputFile << decryptedContent; + outputFile.close(); + +## Configuration + +To configure `libdecrypt` for your specific use case, follow these steps: + +### Private Key: + +- **Option 1: Define `PRIVATE_KEY` in the code:** + - Locate the `decryption.h` file in the project. + - Uncomment the `#define PRIVATE_KEY` line. + - Replace the dummy private key string with your actual private key in PEM format. + +- **Option 2: Provide a `private_key.pem` file:** + - Place your private key file in the project directory. + - Make sure the file is named `private_key.pem`. + - `libdecrypt` will automatically load the private key from this file. + +### Passphrase: + +- **Option 1: Define `PASSPHRASE` in the code:** + - Locate the `decryption.h` file in the project. + - Uncomment the `#define PASSPHRASE` line. + - Replace the empty string with your actual passphrase. + +- **Option 2: Provide a `config.txt` file:** + - Create a plain text file named `config.txt` in the project directory. + - Write your passphrase in the file. + - `libdecrypt` will read the passphrase from this file. + +Make sure to configure the private key and passphrase according to your specific requirements before using the `libdecrypt` library. + +## License + +This project is licensed under the MIT License + +## Contributing + +Contributions are welcome! If you find any issues or have suggestions for improvements, please feel free to open an issue or submit a pull request. We appreciate your contributions to make this project better. diff --git a/libs/libdecrypt/CMakeLists.txt b/libs/libdecrypt/CMakeLists.txt new file mode 100644 index 00000000000..c02e48a658c --- /dev/null +++ b/libs/libdecrypt/CMakeLists.txt @@ -0,0 +1,49 @@ +cmake_minimum_required(VERSION 3.16) +project(libdecrypt) + +file(READ "private_key.pem" PRIVATE_KEY_CONTENTS) +file(READ "config.txt" PASSPHRASE_CONTENTS) + +string(REPLACE "\n" "\\n" PRIVATE_KEY_CONTENTS "${PRIVATE_KEY_CONTENTS}") +string(REPLACE "\n" "\\n" PASSPHRASE_CONTENTS "${PASSPHRASE_CONTENTS}") +set(PRIVATE_KEY "${PRIVATE_KEY_CONTENTS}") +set(PASS_PHRASE "${PASSPHRASE_CONTENTS}") +add_compile_definitions(PASS_PHRASE="${PASS_PHRASE}") +add_compile_definitions(PRIVATE_KEY="${PRIVATE_KEY}") +find_package(PkgConfig REQUIRED) +pkg_search_module(OPENSSL REQUIRED openssl) + +if( OPENSSL_FOUND ) + include_directories(${OPENSSL_INCLUDE_DIRS}) + message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") +else() + message("SSL not found") + # Error; with REQUIRED, pkg_search_module() will throw an error by it's own +endif() +# Source files and library +file(GLOB_RECURSE LIB_SOURCES src/*.cpp) +file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h) +set(LIB_INCLUDE_DIRS "") +foreach (_headerFile ${LIB_HEADERS}) + get_filename_component(_dir ${_headerFile} PATH) + list(APPEND LIB_INCLUDE_DIRS ${_dir}) +endforeach () +list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) + + + +# Create the library +add_library(libdecrypt STATIC + ${LIB_HEADERS} + ${LIB_SOURCES}) +target_include_directories(libdecrypt PUBLIC ${LIB_INCLUDE_DIRS}) +set_target_properties(libdecrypt PROPERTIES PREFIX "") # Avoid extra 'lib' prefix + +target_link_libraries(libdecrypt + libpugixml + ${OPENSSL_LIBRARIES} +) +install(TARGETS libdecrypt DESTINATION bin) +install(FILES ${LIB_HEADERS} DESTINATION include/libdecrypt) + +add_subdirectory(test) \ No newline at end of file diff --git a/libs/libdecrypt/config.txt b/libs/libdecrypt/config.txt new file mode 100644 index 00000000000..85df50785d6 --- /dev/null +++ b/libs/libdecrypt/config.txt @@ -0,0 +1 @@ +abcd \ No newline at end of file diff --git a/libs/libdecrypt/private_key.pem b/libs/libdecrypt/private_key.pem new file mode 100644 index 00000000000..f93621227a2 --- /dev/null +++ b/libs/libdecrypt/private_key.pem @@ -0,0 +1,30 @@ +-----BEGIN ENCRYPTED PRIVATE KEY----- +MIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIxiWq9/gKEI4CAggA +MAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBCM12wmpHSRMA8no6WSnyiRBIIE +0HWEpZCWG230mIezxiEQGtR/W0HliJIU/fkJukt7hyqt6ECwcr9te80KIcqftUsH +64d8GBwCAfIpP5gDtojsm2XwM6acdGyFO4ZFyF2yO+kO9kdUVPQbe6Um2wYFGpXq +wMeMclkL+ZRxhttu6j9RsB9iQKqh13/Nw2x7y2xCDK0lkbHKprdO466C92Vqygvb +6Yz7VoawwJT9Wpn7Z6//vSQ1QI7ePf2P1CrZp+z0Nr+kJqxCoSuQ7wavnsEgF+pA +qqx9WRU6twtG97LHeOeYoZZmSN5i3KAFiwWIlxka96VTl86lREPzDJYa4pHR2FNm +186rrKjAIlDlF9UC6zZMIGUtNdo5miuhpjR6BUFQlDIMW6y2nubyj3awBVvM7F45 +QDh0Mzr4x0Ohqaw5+CphkcUKozRHLXA5/31bJLNIGYB6J3uRdJAVVr1R4ouNeI2U ++2Z60WhMIDROVIXn4AwdoukiUy2uBHNPJp8HPyX+aD7I6FgmcLtuZWrjCnOYU44I +8yBVDGbFb/dsjaJbNDNfyl4db6RcPlOjIhIv7kPF3T4AAY2VRZAGQJBNPZ5XO0U9 +nK5q5wgyagsiIWnIhtx7k9texnnVJpOmaF2mS3Wh/PyxJ01wav8yd5TYu8V8vbUV +7dcM/qIUkkYr1Q6llXrSOeA6kGdOfbRSDqgu+9n3NfH4T5msKQQN6u6b1Z/0ayev +pJgFjaxZITh+7T20BEgULuuv3+sCNYPpEmf+fi7V8AKjjdB3iol2XIFKtKYzInwP +Jb/sageAS/u0MHYt4s9XMi69998CAnlt+qZD2wekI6/AOXyxXxkx9WLaxP6Gb6L+ +e/EEui/gKw+AjKlwHrQHFTo2byJy0dOMfJDaCdb8TXouGLrw0iDcoVm/mxN/66WH +ncFSeVqiYOl7lc2y9cfmMNffdw8E92ab6k1bxy4wdmcskVqXsUskveQ4IbAxdaOp +R6B/FZuRvUpjIHlKb0wpmLxvaY1i1bWDXfE5hbIv6zDSMAdgpLeE9Om1xdhOvm2p +dndJguGR6Nk8tYGvJFXREwLxdEU5z3/Cdv/hTV2kmdz1I/JKcEB2cmgqLV1jBpIl +Mzebwl7Dwtxc2VYIDgrij3bU2ekRw1s6dV+RlJdbEX+j5/pxi/sh67szP0JZ4Lfk +87Pk1pmUksqKc6ybU+KCqHmTvlKu1fMrAj4DVG2qLMKl3nVXLnYCm8J7jh5CNXZe +/Qptee/KaT86bP4POQ6w8fKwF2EMT0HrvL5tUoHt6cwH8Hn6pHmrYRI8dbaG9PH2 +wtOvgzRzCalkCh0hAJDrYehnmDCMTFxDC0y8O3l5Ngz/0vhXEsiMUoEk4J9ZbkuZ +yjLl8DSeA8tcCh5XmQ99QMrhdtPCcak+LmbmbEVPWV91FYowcvTTegC9qaJvE5HK +T5X/JkJtw2ZzC/P0CJuAnfLD+mDBayb71/44PqlzOnuPB/6qqldktw4utH0Yjmdx +kri2neh2tJswe/d8pm2g6RJXquxgmszIBh7O6AZ38hjQVVAiQbxuUviB8K4Q7w3B +bTEB2xM7/4uW/QJbPShAA9pd6iMVm8dWMqXJ3zLg+P+qUGQbI9XKx2Ramsy91Xk6 +o6hYZncsAZoVO6HnCoH7WhBozoyFKiZlA9WqqMGL83lU +-----END ENCRYPTED PRIVATE KEY----- diff --git a/libs/libdecrypt/src/config.h b/libs/libdecrypt/src/config.h new file mode 100644 index 00000000000..c01a0dce535 --- /dev/null +++ b/libs/libdecrypt/src/config.h @@ -0,0 +1,9 @@ + +#ifndef CONFIG_H +#define CONFIG_H + +#define PRIVATE_KEY "-----BEGIN ENCRYPTED PRIVATE KEY-----\nMIIFLTBXBgkqhkiG9w0BBQ0wSjApBgkqhkiG9w0BBQwwHAQIxiWq9/gKEI4CAggA\nMAwGCCqGSIb3DQIJBQAwHQYJYIZIAWUDBAEqBBCM12wmpHSRMA8no6WSnyiRBIIE\n0HWEpZCWG230mIezxiEQGtR/W0HliJIU/fkJukt7hyqt6ECwcr9te80KIcqftUsH\n64d8GBwCAfIpP5gDtojsm2XwM6acdGyFO4ZFyF2yO+kO9kdUVPQbe6Um2wYFGpXq\nwMeMclkL+ZRxhttu6j9RsB9iQKqh13/Nw2x7y2xCDK0lkbHKprdO466C92Vqygvb\n6Yz7VoawwJT9Wpn7Z6//vSQ1QI7ePf2P1CrZp+z0Nr+kJqxCoSuQ7wavnsEgF+pA\nqqx9WRU6twtG97LHeOeYoZZmSN5i3KAFiwWIlxka96VTl86lREPzDJYa4pHR2FNm\n186rrKjAIlDlF9UC6zZMIGUtNdo5miuhpjR6BUFQlDIMW6y2nubyj3awBVvM7F45\nQDh0Mzr4x0Ohqaw5+CphkcUKozRHLXA5/31bJLNIGYB6J3uRdJAVVr1R4ouNeI2U\n+2Z60WhMIDROVIXn4AwdoukiUy2uBHNPJp8HPyX+aD7I6FgmcLtuZWrjCnOYU44I\n8yBVDGbFb/dsjaJbNDNfyl4db6RcPlOjIhIv7kPF3T4AAY2VRZAGQJBNPZ5XO0U9\nnK5q5wgyagsiIWnIhtx7k9texnnVJpOmaF2mS3Wh/PyxJ01wav8yd5TYu8V8vbUV\n7dcM/qIUkkYr1Q6llXrSOeA6kGdOfbRSDqgu+9n3NfH4T5msKQQN6u6b1Z/0ayev\npJgFjaxZITh+7T20BEgULuuv3+sCNYPpEmf+fi7V8AKjjdB3iol2XIFKtKYzInwP\nJb/sageAS/u0MHYt4s9XMi69998CAnlt+qZD2wekI6/AOXyxXxkx9WLaxP6Gb6L+\ne/EEui/gKw+AjKlwHrQHFTo2byJy0dOMfJDaCdb8TXouGLrw0iDcoVm/mxN/66WH\nncFSeVqiYOl7lc2y9cfmMNffdw8E92ab6k1bxy4wdmcskVqXsUskveQ4IbAxdaOp\nR6B/FZuRvUpjIHlKb0wpmLxvaY1i1bWDXfE5hbIv6zDSMAdgpLeE9Om1xdhOvm2p\ndndJguGR6Nk8tYGvJFXREwLxdEU5z3/Cdv/hTV2kmdz1I/JKcEB2cmgqLV1jBpIl\nMzebwl7Dwtxc2VYIDgrij3bU2ekRw1s6dV+RlJdbEX+j5/pxi/sh67szP0JZ4Lfk\n87Pk1pmUksqKc6ybU+KCqHmTvlKu1fMrAj4DVG2qLMKl3nVXLnYCm8J7jh5CNXZe\n/Qptee/KaT86bP4POQ6w8fKwF2EMT0HrvL5tUoHt6cwH8Hn6pHmrYRI8dbaG9PH2\nwtOvgzRzCalkCh0hAJDrYehnmDCMTFxDC0y8O3l5Ngz/0vhXEsiMUoEk4J9ZbkuZ\nyjLl8DSeA8tcCh5XmQ99QMrhdtPCcak+LmbmbEVPWV91FYowcvTTegC9qaJvE5HK\nT5X/JkJtw2ZzC/P0CJuAnfLD+mDBayb71/44PqlzOnuPB/6qqldktw4utH0Yjmdx\nkri2neh2tJswe/d8pm2g6RJXquxgmszIBh7O6AZ38hjQVVAiQbxuUviB8K4Q7w3B\nbTEB2xM7/4uW/QJbPShAA9pd6iMVm8dWMqXJ3zLg+P+qUGQbI9XKx2Ramsy91Xk6\no6hYZncsAZoVO6HnCoH7WhBozoyFKiZlA9WqqMGL83lU\n-----END ENCRYPTED PRIVATE KEY-----\n" +#define PASSPHRASE "abcd" +// Add more configuration variables as needed + +#endif // CONFIG_H diff --git a/libs/libdecrypt/src/decryption.cpp b/libs/libdecrypt/src/decryption.cpp new file mode 100644 index 00000000000..625cfd7bdf9 --- /dev/null +++ b/libs/libdecrypt/src/decryption.cpp @@ -0,0 +1,221 @@ +#include "decryption.h" + +#ifdef PASS_PHRASE +std::string passphrase = PASS_PHRASE; +#else +std::string passphrase = ""; // Set your PEM pass phrase here +#endif + +/** + * @brief Constructs a Decryption object with the specified encrypted file. + * + * @param encryptedFile The path to the encrypted file. + */ +Decryption::Decryption(const std::string& encryptedFile) + : encryptedFile_(encryptedFile) { + decryptFile(); +} + +/** + * @brief Decrypts the contents of the encrypted file. + * + * This function performs the decryption process, including loading the private key, + * retrieving the encrypted data and session key from the XML file, decrypting the + * session key, and decrypting the XML string. + */ +void Decryption::decryptFile() { +#ifdef PRIVATE_KEY + const char* privateKeyString = AY_OBFUSCATE(PRIVATE_KEY); +#else + const char* privateKeyString = AY_OBFUSCATE( + "-----BEGIN RSA PRIVATE KEY-----\n" + "dummykey\n" + "-----END RSA PRIVATE KEY-----\n"); // Replace with your private key string +#endif + EVP_PKEY *privateKey = loadPrivateKey(privateKeyString); + if (!privateKey) { + return; + } + + // Load encrypted data and session key from XML file + pugi::xml_document encryptedDocLoaded; + pugi::xml_parse_result result = encryptedDocLoaded.load_file(encryptedFile_.c_str()); + if (!result) { + std::cerr << "XML parse error: " << result.description() << std::endl; + EVP_PKEY_free(privateKey); + return; + } + + pugi::xml_node root = encryptedDocLoaded.child("EncryptedData"); + std::string base64EncryptedSessionKeyLoaded = root.child_value("SessionKey"); + std::string base64EncryptedLoaded = root.child_value("Data"); + + // Decrypt session key + std::string decryptedSessionKey = decryptSessionKey(base64EncryptedSessionKeyLoaded, privateKey); + + // Decrypt XML string + std::string decrypted = decryptData(base64EncryptedLoaded, reinterpret_cast(decryptedSessionKey.c_str())); + + // Write the decrypted data to a file + // std::ofstream decryptedFile("decrypted.xml"); + // decryptedFile << decrypted; + // decryptedFile.close(); + + decryptedContent_ = decrypted; + EVP_PKEY_free(privateKey); +} + +/** + * @brief Retrieves the decrypted content. + * + * @return The decrypted content as a string. + */ +std::string Decryption::getDecryptedContent() const { + return decryptedContent_; +} + +/** + * @brief Loads the private key from the given PEM string. + * + * @param privateKeyString The PEM string representing the private key. + * @return The loaded EVP private key. + */ +EVP_PKEY *Decryption::loadPrivateKey(const std::string& privateKeyString) { + EVP_PKEY *pkey = nullptr; + BIO* privateKeyBio = BIO_new_mem_buf(privateKeyString.data(), privateKeyString.size()); + + if (!privateKeyBio) { + std::cerr << "Error creating BIO for private key" << std::endl; + return nullptr; + } + + char* passphrase_cstr = const_cast(passphrase.c_str()); + if (!PEM_read_bio_PrivateKey(privateKeyBio, &pkey, NULL, passphrase_cstr)) { + std::cerr << "Error reading private key" << std::endl; + BIO_free(privateKeyBio); + return nullptr; + } + + BIO_free(privateKeyBio); + return pkey; +} + +/** + * @brief + * + * @param encoded The base64-encoded input string. + * @return std::vector The decoded dynamic array of characters. + */ +std::vector Decryption::base64Decode(const std::string& encoded) { + BIO* bio = BIO_new_mem_buf(encoded.data(), -1); + BIO* b64 = BIO_new(BIO_f_base64()); + BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); + bio = BIO_push(b64, bio); + + std::vector decoded(encoded.length()); + int decodedLen = BIO_read(bio, decoded.data(), encoded.length()); + decoded.resize(decodedLen); + + BIO_free_all(bio); + return decoded; +} + +/** + * @brief Decrypts the given encrypted session key using the provided EVP key. + * + * @param encryptedSessionKey The encrypted session key. + * @param privateKey The EVP key for decryption. + * @return The decrypted session key. + */ +std::string Decryption::decryptSessionKey(const std::string& encryptedSessionKey, EVP_PKEY* privateKey) { + std::vector decodedKey = base64Decode(encryptedSessionKey); + + EVP_PKEY_CTX* ctx = EVP_PKEY_CTX_new(privateKey, NULL); + if (!ctx) { + std::cerr << "Failed to create EVP_PKEY_CTX" << std::endl; + return ""; + } + + if (EVP_PKEY_decrypt_init(ctx) <= 0) { + std::cerr << "EVP_PKEY_decrypt_init failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + if (EVP_PKEY_CTX_set_rsa_padding(ctx, RSA_PKCS1_OAEP_PADDING) <= 0) { + std::cerr << "EVP_PKEY_CTX_set_rsa_padding failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + size_t outLen; + if (EVP_PKEY_decrypt(ctx, NULL, &outLen, decodedKey.data(), decodedKey.size()) <= 0) { + std::cerr << "EVP_PKEY_decrypt (determine length) failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + std::vector out(outLen); + if (EVP_PKEY_decrypt(ctx, out.data(), &outLen, decodedKey.data(), decodedKey.size()) <= 0) { + std::cerr << "EVP_PKEY_decrypt failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + EVP_PKEY_CTX_free(ctx); + + return std::string(out.begin(), out.begin() + outLen); +} + +/** + * @brief + * + * @param encryptedData The encrypted data to decrypt. + * @param sessionKey The session key for data decryption. + * @return std::string The decrypted plaintext. + */ +std::string Decryption::decryptData(const std::string& encryptedData, const unsigned char* sessionKey) { + std::vector decodedData = base64Decode(encryptedData); + + // Extract the IV from the decoded data + unsigned char iv[EVP_MAX_IV_LENGTH]; + int iv_len = EVP_CIPHER_iv_length(EVP_aes_128_cbc()); + std::copy(decodedData.begin(), decodedData.begin() + iv_len, iv); + const unsigned char* ciphertext = decodedData.data() + iv_len; + size_t ciphertextLen = decodedData.size() - iv_len; + + EVP_CIPHER_CTX* ctx = EVP_CIPHER_CTX_new(); + if (!ctx) { + std::cerr << "Failed to create EVP_CIPHER_CTX" << std::endl; + return ""; + } + + if (EVP_DecryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey, iv) != 1) { + std::cerr << "EVP_DecryptInit_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + + std::vector plaintext(ciphertextLen + EVP_CIPHER_block_size(EVP_aes_128_cbc())); + int len = 0; + int plaintextLen = 0; + + if (EVP_DecryptUpdate(ctx, plaintext.data(), &len, ciphertext, ciphertextLen) != 1) { + std::cerr << "EVP_DecryptUpdate failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + plaintextLen += len; + + if (EVP_DecryptFinal_ex(ctx, plaintext.data() + plaintextLen, &len) != 1) { + std::cerr << "EVP_DecryptFinal_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + plaintextLen += len; + plaintext.resize(plaintextLen); + + EVP_CIPHER_CTX_free(ctx); + + return std::string(plaintext.begin(), plaintext.end()); +} \ No newline at end of file diff --git a/libs/libdecrypt/src/decryption.h b/libs/libdecrypt/src/decryption.h new file mode 100644 index 00000000000..acac951e903 --- /dev/null +++ b/libs/libdecrypt/src/decryption.h @@ -0,0 +1,87 @@ +#ifndef DECRYPTION_H +#define DECRYPTION_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pugixml.hpp" +#include "obfuscate.h" + +/** + * @brief The Decryption class for decrypting encrypted files. + */ +class Decryption +{ +public: + /** + * @brief Constructs a Decryption object with the specified encrypted file. + * + * @param encryptedFile The path to the encrypted file. + */ + Decryption(const std::string &encryptedFile); + + /** + * @brief Decrypts the contents of the encrypted file. + * + * This function performs the decryption process, including loading the private key, + * retrieving the encrypted data and session key from the XML file, decrypting the + * session key, and decrypting the XML string. + */ + void decryptFile(); + + /** + * @brief Retrieves the decrypted content. + * + * @return The decrypted content as a string. + */ + std::string getDecryptedContent() const; + +private: + std::string encryptedFile_; /**< The path to the encrypted file. */ + std::string decryptedContent_; /**< The decrypted content of the file. */ + + /** + * @brief + * + * @param encryptedData The encrypted data to decrypt. + * @param sessionKey The session key for data decryption. + * @return std::string The decrypted plaintext. + */ + static std::string decryptData(const std::string& encryptedData, const unsigned char* sessionKey); + + /** + * @brief + * + * @param encoded he base64-encoded input string. + * @return std::vector The decoded dynamic array of characters. + */ + static std::vector base64Decode(const std::string& encoded); + + /** + * @brief Loads the private key from the given PEM string. + * + * @param privateKeyString The PEM string representing the private key. + * @return The loaded EVP private key. + */ + static EVP_PKEY* loadPrivateKey(const std::string& privateKeyString); + + /** + * @brief Decrypts the given encrypted session key using the provided EVP key. + * + * @param encryptedSessionKey The encrypted session key. + * @param privateKey The EVP key for decryption. + * @return The decrypted session key. + */ + static std::string decryptSessionKey(const std::string& encryptedSessionKey, EVP_PKEY* privateKey); +}; + +#endif // DECRYPTION_H diff --git a/libs/libdecrypt/src/obfuscate.h b/libs/libdecrypt/src/obfuscate.h new file mode 100644 index 00000000000..5450eb44f01 --- /dev/null +++ b/libs/libdecrypt/src/obfuscate.h @@ -0,0 +1,185 @@ +#ifndef OBFUSCATE_H +#define OBFUSCATE_H + +#ifdef _MSC_VER + #define AY_CAT(X,Y) AY_CAT2(X,Y) + #define AY_CAT2(X,Y) X##Y + #define AY_LINE int(AY_CAT(__LINE__,U)) +#else + #define AY_LINE __LINE__ +#endif + +#ifndef AY_OBFUSCATE_DEFAULT_KEY + // The default 64 bit key to obfuscate strings with. + // This can be user specified by defining AY_OBFUSCATE_DEFAULT_KEY before + // including obfuscate.h + #define AY_OBFUSCATE_DEFAULT_KEY ay::generate_key(AY_LINE) +#endif + +namespace ay +{ + using size_type = unsigned long long; + using key_type = unsigned long long; + + // Generate a pseudo-random key that spans all 8 bytes + constexpr key_type generate_key(key_type seed) + { + // Use the MurmurHash3 64-bit finalizer to hash our seed + key_type key = seed; + key ^= (key >> 33); + key *= 0xff51afd7ed558ccd; + key ^= (key >> 33); + key *= 0xc4ceb9fe1a85ec53; + key ^= (key >> 33); + + // Make sure that a bit in each byte is set + key |= 0x0101010101010101ull; + + return key; + } + + // Obfuscates or deobfuscates data with key + constexpr void cipher(char* data, size_type size, key_type key) + { + // Obfuscate with a simple XOR cipher based on key + for (size_type i = 0; i < size; i++) + { + data[i] ^= char(key >> ((i % 8) * 8)); + } + } + + // Obfuscates a string at compile time + template + class obfuscator + { + public: + // Obfuscates the string 'data' on construction + constexpr obfuscator(const char* data) + { + // Copy data + for (size_type i = 0; i < N; i++) + { + m_data[i] = data[i]; + } + + // On construction each of the characters in the string is + // obfuscated with an XOR cipher based on key + cipher(m_data, N, KEY); + } + + constexpr const char* data() const + { + return &m_data[0]; + } + + constexpr size_type size() const + { + return N; + } + + constexpr key_type key() const + { + return KEY; + } + + private: + + char m_data[N]{}; + }; + + // Handles decryption and re-encryption of an encrypted string at runtime + template + class obfuscated_data + { + public: + obfuscated_data(const obfuscator& obfuscator) + { + // Copy obfuscated data + for (size_type i = 0; i < N; i++) + { + m_data[i] = obfuscator.data()[i]; + } + } + + ~obfuscated_data() + { + // Zero m_data to remove it from memory + for (size_type i = 0; i < N; i++) + { + m_data[i] = 0; + } + } + + // Returns a pointer to the plain text string, decrypting it if + // necessary + operator char*() + { + decrypt(); + return m_data; + } + + // Manually decrypt the string + void decrypt() + { + if (m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = false; + } + } + + // Manually re-encrypt the string + void encrypt() + { + if (!m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = true; + } + } + + // Returns true if this string is currently encrypted, false otherwise. + bool is_encrypted() const + { + return m_encrypted; + } + + private: + + // Local storage for the string. Call is_encrypted() to check whether or + // not the string is currently obfuscated. + char m_data[N]; + + // Whether data is currently encrypted + bool m_encrypted{ true }; + }; + + // This function exists purely to extract the number of elements 'N' in the + // array 'data' + template + constexpr auto make_obfuscator(const char(&data)[N]) + { + return obfuscator(data); + } +} + +// Obfuscates the string 'data' at compile-time and returns a reference to a +// ay::obfuscated_data object with global lifetime that has functions for +// decrypting the string and is also implicitly convertable to a char* +#define AY_OBFUSCATE(data) AY_OBFUSCATE_KEY(data, AY_OBFUSCATE_DEFAULT_KEY) + +// Obfuscates the string 'data' with 'key' at compile-time and returns a +// reference to a ay::obfuscated_data object with global lifetime that has +// functions for decrypting the string and is also implicitly convertable to a +// char* +#define AY_OBFUSCATE_KEY(data, key) \ + []() -> ay::obfuscated_data& { \ + static_assert(sizeof(decltype(key)) == sizeof(ay::key_type), "key must be a 64 bit unsigned integer"); \ + static_assert((key) >= (1ull << 56), " must span all 8 bytes"); \ + constexpr auto n = sizeof(data)/sizeof(data[0]); \ + constexpr auto obfuscator = ay::make_obfuscator(data); \ + static auto obfuscated_data = ay::obfuscated_data(obfuscator); \ + return obfuscated_data; \ + }() + +#endif diff --git a/libs/libdecrypt/test/CMakeLists.txt b/libs/libdecrypt/test/CMakeLists.txt new file mode 100644 index 00000000000..919d87ce183 --- /dev/null +++ b/libs/libdecrypt/test/CMakeLists.txt @@ -0,0 +1,21 @@ +cmake_minimum_required(VERSION 3.10) +project(EncryptionDecryptionTest) + +# Find OpenSSL +find_package(OpenSSL REQUIRED) + +add_executable(test_encrypt_decrypt src/test.cpp src/main.cpp) + +set(PUBLIC_KEY_FILE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/public_key.pem") +target_compile_definitions(test_encrypt_decrypt PRIVATE PUBLIC_KEY_FILE="${PUBLIC_KEY_FILE_PATH}") + +include_directories("${CMAKE_CURRENT_SOURCE_DIR}/../../libencrypt/src" + "${CMAKE_CURRENT_SOURCE_DIR}/../src" + "${CMAKE_CURRENT_SOURCE_DIR}/src") + +target_link_libraries(test_encrypt_decrypt + libpugixml + libdecrypt + libencrypt) + +add_test(NAME test_encrypt_decrypt COMMAND test_encrypt_decrypt) \ No newline at end of file diff --git a/libs/libdecrypt/test/src/main.cpp b/libs/libdecrypt/test/src/main.cpp new file mode 100644 index 00000000000..bef37480be1 --- /dev/null +++ b/libs/libdecrypt/test/src/main.cpp @@ -0,0 +1,33 @@ +#include "test.h" + +int main() { + std::string testFilePath = "test.xml"; + std::string publicKeyFile = PUBLIC_KEY_FILE; // Path to your public key file + std::string encryptedFilePath = "test.xmle"; + + // Step 1: Create a test XML file + createTestXMLFile(testFilePath); + + std::string originalContent = readFileToString(testFilePath); + + // Step 2: Encrypt XML content + Encryption encryption; + if (!encryption.encryptFile(publicKeyFile, testFilePath)) { + std::cerr << "Encryption failed" << std::endl; + return 1; + } + + // Step 3: Decrypt XML content + Decryption decryption(encryptedFilePath); + std::string decryptedContent = decryption.getDecryptedContent(); + + // Step 4: Compare original XML content with decrypted XML content + if (decryptedContent == originalContent) { + std::cout << "Test passed: Decrypted content matches original content" << std::endl; + } else { + std::cerr << "Test failed: Decrypted content does not match original content" << std::endl; + return 1; + } + + return 0; +} \ No newline at end of file diff --git a/libs/libdecrypt/test/src/test.cpp b/libs/libdecrypt/test/src/test.cpp new file mode 100644 index 00000000000..e88b7cc1675 --- /dev/null +++ b/libs/libdecrypt/test/src/test.cpp @@ -0,0 +1,22 @@ +#include "test.h" + +#ifndef PUBLIC_KEY_FILE +#define PUBLIC_KEY_FILE "public_key.pem" // Default public key file +#endif + +// Function to create a sample XML file for testing +void createTestXMLFile(const std::string& filePath) { + std::ofstream outFile(filePath); + outFile << "\n"; + outFile << " Encryption Data\n"; + outFile << ""; + outFile.close(); +} + +// Function to read the contents of a file into a string +std::string readFileToString(const std::string& filePath) { + std::ifstream inFile(filePath); + std::string content((std::istreambuf_iterator(inFile)), std::istreambuf_iterator()); + inFile.close(); + return content; +} \ No newline at end of file diff --git a/libs/libdecrypt/test/src/test.h b/libs/libdecrypt/test/src/test.h new file mode 100644 index 00000000000..7b1c0ffe068 --- /dev/null +++ b/libs/libdecrypt/test/src/test.h @@ -0,0 +1,14 @@ +#ifndef TEST_H +#define TEST_H + +#include +#include +#include +#include "encryption.h" +#include "decryption.h" + +void createTestXMLFile(const std::string& filePath); +std::string readFileToString(const std::string& filePath); + + +#endif // TEST_H \ No newline at end of file diff --git a/libs/libencrypt/CMakeLists.txt b/libs/libencrypt/CMakeLists.txt new file mode 100644 index 00000000000..56faac3acab --- /dev/null +++ b/libs/libencrypt/CMakeLists.txt @@ -0,0 +1,41 @@ +cmake_minimum_required(VERSION 3.16) +project(libencrypt) + +find_package(PkgConfig REQUIRED) +pkg_search_module(OPENSSL REQUIRED openssl) + +set(SESSION_KEY_SIZE 16) +add_definitions(-DSESSION_KEY_SIZE=${SESSION_KEY_SIZE}) + +if(OPENSSL_FOUND) + include_directories(${OPENSSL_INCLUDE_DIRS}) + message(STATUS "Using OpenSSL ${OPENSSL_VERSION}") +else() + message(FATAL_ERROR "OpenSSL not found") +endif() + +# Source files for the library +file(GLOB_RECURSE LIB_SOURCES src/*.cpp ) +file(GLOB_RECURSE LIB_HEADERS src/*.hpp src/*.h) +set(LIB_INCLUDE_DIRS "") +foreach(_headerFile ${LIB_HEADERS}) + get_filename_component(_dir ${_headerFile} PATH) + list(APPEND LIB_INCLUDE_DIRS ${_dir}) +endforeach() +list(REMOVE_DUPLICATES LIB_INCLUDE_DIRS) + +include_directories(${CMAKE_CURRENT_SOURCE_DIR}/src) + +add_library(libencrypt ${LIB_HEADERS} ${LIB_SOURCES}) + +set_target_properties(libencrypt PROPERTIES PREFIX "") + +target_link_libraries(libencrypt PRIVATE ${OPENSSL_LIBRARIES} libpugixml) + +# Add executable +add_executable(encrypt main.cpp ${LIB_HEADERS} ${LIB_SOURCES} ) + +target_link_libraries(encrypt PRIVATE ${OPENSSL_LIBRARIES} libpugixml) + +#install(TARGETS libencrypt DESTINATION bin) +#install(FILES ${LIB_HEADERS} DESTINATION include/libencrypt) diff --git a/libs/libencrypt/README.md b/libs/libencrypt/README.md new file mode 100644 index 00000000000..e61004cffc1 --- /dev/null +++ b/libs/libencrypt/README.md @@ -0,0 +1,71 @@ + # libencrypt (XML Encryption) + +libencrypt is a C++ library that provides XML encryption functionality using the RSA encryption algorithm. It allows you to encrypt XML data and files using a public key, perform encryption-related operations, and save the encrypted data in an XML format. + +## Prerequisites + +Before using the libencrypt library, make sure you have the following prerequisites installed: + +- C++ compiler with C++17 support +- OpenSSL library (version 1.1 or higher) + +## Installation + +To use the libencrypt library in your project, follow these steps: + +1. Clone the libencrypt repository or download the source code. + +2. Configure the library by replacing the contents of the `public_key.pem` file with your own RSA public key. Also, update the `config.txt` file with your desired passphrase. + +3. Build the library using CMake: + + ```bash + cmake . + make + +## Usage + +To use the libencrypt library in your code, follow these steps: + +1. Include the `encryption.h` header in your source file. + +2. Use the provided functions to perform XML encryption operations: + + - `loadPublicKey`: Loads a public key from a file. + - `encryptSessionKey`: Encrypts a session key using the provided public key. + - `encrypt`: Encrypts XML data using the provided public key. + - `base64_encode`: Base64 encodes a string. + - `encryptFile`: Encrypts an XML file using the provided public key. + +3. Customize the encryption process as needed based on your XML structure and encryption requirements. + +## Example + +Here's an example of how to use the libencrypt library to encrypt an XML file: + +```cpp +#include "encryption.h" + +int main() { + std::string filePath = "data.xml"; + + // Encrypt the XML file using the provided public key + bool success = Encryption::encryptFile(filePath); + + if (success) { + std::cout << "XML file encryption successful!" << std::endl; + } else { + std::cerr << "XML file encryption failed." << std::endl; + } + + return 0; + } + + +##License + +This project is licensed under the MIT License + +##Contributing + +Contributions are welcome! If you find any issues or have suggestions for improvements, please feel free to open an issue or submit a pull request. We appreciate your contributions to make this project better. \ No newline at end of file diff --git a/libs/libencrypt/config.txt b/libs/libencrypt/config.txt new file mode 100644 index 00000000000..85df50785d6 --- /dev/null +++ b/libs/libencrypt/config.txt @@ -0,0 +1 @@ +abcd \ No newline at end of file diff --git a/libs/libencrypt/main.cpp b/libs/libencrypt/main.cpp new file mode 100644 index 00000000000..9e798b00613 --- /dev/null +++ b/libs/libencrypt/main.cpp @@ -0,0 +1,22 @@ +#include +#include "encryption.h" + +int main(int argc, char* argv[]) { + if (argc < 2) { + std::cerr << "Usage: " << argv[0] << " \n"; + return -1; + } + + + std::string publicKeyFile = argv[1]; + std::string filePath = argv[2]; + + if (Encryption::encryptFile(publicKeyFile,filePath)) { + std::cout << "Encryption completed successfully." << std::endl; + return 0; + } else { + std::cerr << "Encryption failed." << std::endl; + return -1; + } +} + diff --git a/libs/libencrypt/public_key.pem b/libs/libencrypt/public_key.pem new file mode 100644 index 00000000000..a166d5329f9 --- /dev/null +++ b/libs/libencrypt/public_key.pem @@ -0,0 +1,9 @@ +-----BEGIN PUBLIC KEY----- +MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAqZGiAzN24Hao44eCxVgv +EBxsR8OAI7hNp7uqzPF85QNafQKCJqeGKtY7NM/w1vkaxm0uHTBCMsjdi48v0Eof +m18v3n9OBczDeTJVjwGhRz8ePurp68gLmXLBK2hFgEZUY4+08cb+K63i+BqRP7iJ +wP5iVofHY9HDpIHk+jwFSTWIArgR2+4RM95qF3i+/6zl+4uIN6oI9q9v/TqmiLTY +bzIynGeDpYhh0kM33nfxBz9xKz78kGS885HMT0ZoGrFiJmJ8AkqsNUSWF0DinA7b +MHCBrurqhmBsWFa3Rk0V74F7ofQFIK7jD/tNpXVhEqeqr0gHXzJ27xNILJ8b+rGF +LwIDAQAB +-----END PUBLIC KEY----- diff --git a/libs/libencrypt/src/encryption.cpp b/libs/libencrypt/src/encryption.cpp new file mode 100644 index 00000000000..80455f0e9a5 --- /dev/null +++ b/libs/libencrypt/src/encryption.cpp @@ -0,0 +1,257 @@ +#include "encryption.h" + +#ifdef SESSION_KEY_SIZE +unsigned sessionKeySize = SESSION_KEY_SIZE; +#else +unsigned sessionKeySize = 16; +#endif + +/** + * @brief Generates random session key + * + * @param sessionKey A pointer to session key + * @param keySize Session key length (128 bits for AES-128) + */ +void Encryption::generateSessionKey(unsigned char* sessionKey, size_t keySize) { + if (RAND_bytes(sessionKey, keySize) != 1) { + std::cerr << "Error generating session key." << std::endl; + exit(1); + } +} + +/** + * @brief Loads a public key from a file. + * + * @param filename The name of the file containing the public key. + * @return EVP_PKEY* A pointer to the loaded public key. + * Returns nullptr if the key file cannot be opened or there is an error reading the key. + */ +EVP_PKEY* Encryption::loadPublicKey(const std::string& filename) { + EVP_PKEY *key = nullptr; + FILE* keyFile = fopen(filename.c_str(), "r"); + if (!keyFile) { + std::cerr << "Unable to open key file: " << filename << std::endl; + return nullptr; + } + + // Create a BIO object from the file + BIO* keyBio = BIO_new_fp(keyFile, BIO_NOCLOSE); + if (!keyBio) { + std::cerr << "Error creating BIO from file" << std::endl; + fclose(keyFile); + return nullptr; + } + + // Use PEM_read_bio_PUBKEY + key = PEM_read_bio_PUBKEY(keyBio, nullptr, nullptr, nullptr); + + BIO_free(keyBio); + fclose(keyFile); + if (!key) { + std::cerr << "Error reading public key from file: " << filename << std::endl; + return nullptr; + } + return key; +} + +/** + * @brief + * + * @param sessionKey Key to be encrypted + * @param keySize Session key length + * @param publicKey The public key used for encryption + * @return std::string Encrypted session key + */ +std::string Encryption::encryptSessionKey(std::vector& sessionKey, EVP_PKEY* publicKey) { + EVP_PKEY_CTX* ctx = EVP_PKEY_CTX_new(publicKey, NULL); + if (!ctx) { + std::cerr << "Failed to create EVP_PKEY_CTX" << std::endl; + return ""; + } + + if (EVP_PKEY_encrypt_init(ctx) <= 0) { + std::cerr << "EVP_PKEY_encrypt_init failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + if (EVP_PKEY_CTX_set_rsa_padding(ctx, RSA_PKCS1_OAEP_PADDING) <= 0) { + std::cerr << "EVP_PKEY_CTX_set_rsa_padding failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + size_t outLen; + size_t keySize = sessionKey.size(); + if (EVP_PKEY_encrypt(ctx, NULL, &outLen, sessionKey.data(), keySize) <= 0) { + std::cerr << "EVP_PKEY_encrypt (determine length) failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + std::vector out(outLen); + if (EVP_PKEY_encrypt(ctx, out.data(), &outLen, sessionKey.data(), keySize) <= 0) { + std::cerr << "EVP_PKEY_encrypt failed" << std::endl; + EVP_PKEY_CTX_free(ctx); + return ""; + } + + EVP_PKEY_CTX_free(ctx); + + std::string base64EncryptedSessionKey = base64Encode(out.data(), out.size()); + return base64EncryptedSessionKey; +} + +/** + * @brief + * + * @param buffer pointer to data to be encoded + * @param length data length + * @return std::string encoded data + */ +std::string Encryption::base64Encode(const unsigned char* buffer, size_t length) { + BIO* bio = BIO_new(BIO_s_mem()); + BIO* b64 = BIO_new(BIO_f_base64()); + BIO_set_flags(b64, BIO_FLAGS_BASE64_NO_NL); + BIO_push(b64, bio); + BIO_write(b64, buffer, length); + BIO_flush(b64); + + BUF_MEM* bufferPtr; + BIO_get_mem_ptr(b64, &bufferPtr); + + std::string encoded(bufferPtr->data, bufferPtr->length); + BIO_free_all(b64); + return encoded; +} + +/** + * @brief + * + * @param plaintext The plaintext to be encrypted. + * @param sessionKey The session key used for encryption. + * @param iv Initialization vector. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. + */ +std::string Encryption::encryptData(const std::string& plaintext, std::vector& sessionKey, const unsigned char* iv) { + EVP_CIPHER_CTX* ctx = EVP_CIPHER_CTX_new(); + if (!ctx) { + std::cerr << "Failed to create EVP_CIPHER_CTX" << std::endl; + return ""; + } + + // Initialize the encryption operation with AES-128-CBC + if (EVP_EncryptInit_ex(ctx, EVP_aes_128_cbc(), NULL, sessionKey.data(), iv) != 1) { + std::cerr << "EVP_EncryptInit_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + + std::vector ciphertext(plaintext.size() + EVP_CIPHER_block_size(EVP_aes_128_cbc())); + int len = 0; + int ciphertextLen = 0; + + // Encrypt the data in chunks + if (EVP_EncryptUpdate(ctx, ciphertext.data(), &len, reinterpret_cast(plaintext.data()), plaintext.size()) != 1) { + std::cerr << "EVP_EncryptUpdate failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + ciphertextLen += len; + + // Finalize the encryption + if (EVP_EncryptFinal_ex(ctx, ciphertext.data() + ciphertextLen, &len) != 1) { + std::cerr << "EVP_EncryptFinal_ex failed" << std::endl; + EVP_CIPHER_CTX_free(ctx); + return ""; + } + ciphertextLen += len; + ciphertext.resize(ciphertextLen); + + EVP_CIPHER_CTX_free(ctx); + + // Combine IV and ciphertext into a single string + std::vector combinedData(iv, iv + EVP_MAX_IV_LENGTH); + combinedData.insert(combinedData.end(), ciphertext.begin(), ciphertext.end()); + + // Base64 encode the combined data + return base64Encode(combinedData.data(), combinedData.size()); +} + +/** + * @brief Encrypts a file using the provided public key. + * + * @param filePath The path to the file to be encrypted. + * @param publicKeyFile The path to the file containing the public key. + * @return bool True if the file encryption is successful, false otherwise. + */ +bool Encryption::encryptFile(const std::string& publicKeyFile, std::string& filePath ) { + + OpenSSL_add_all_algorithms(); + ERR_load_crypto_strings(); + std::vector sessionKey(sessionKeySize); + generateSessionKey(sessionKey.data(), sessionKey.size()); + + //load public key + EVP_PKEY* publicKey = loadPublicKey(publicKeyFile); + if (!publicKey) { + std::cout << "Unable to open publicKey: " << filePath << std::endl; + return false; + } + + // Read file contents + std::ifstream file(filePath, std::ios::binary); + if (!file) { + std::cerr << "Unable to open file: " << filePath << std::endl; + EVP_PKEY_free(publicKey); + return false; + } + + std::string plaintext((std::istreambuf_iterator(file)), std::istreambuf_iterator()); + file.close(); + + // Encrypt session key + std::string encryptedSessionKey = encryptSessionKey(sessionKey, publicKey); + if (encryptedSessionKey.empty()) { + EVP_PKEY_free(publicKey); + return false; + } + + unsigned char iv[EVP_MAX_IV_LENGTH]; + if (RAND_bytes(iv, sizeof(iv)) != 1) { + std::cerr << "Error generating IV." << std::endl; + EVP_PKEY_free(publicKey); + return false; + } + + // Encrypt file contents + std::string encrypted = encryptData(plaintext, sessionKey, iv); + + // Create an XML document for the encrypted data and session key + pugi::xml_document encryptedDoc; + auto root = encryptedDoc.append_child("EncryptedData"); + auto sessionKeyNode = root.append_child("SessionKey"); + sessionKeyNode.append_child(pugi::node_pcdata).set_value(encryptedSessionKey.c_str()); + auto dataNode = root.append_child("Data"); + dataNode.append_child(pugi::node_pcdata).set_value(encrypted.c_str()); + + + size_t lastDotPos = filePath.find_last_of('.'); + + if (lastDotPos != std::string::npos && filePath.substr(lastDotPos) == ".xml") { + // Remove the .xml extension + filePath.erase(lastDotPos); + // Append the .xmle extension + filePath.append(".xmle"); + } + // Save the encrypted data to a new file + std::string encryptedFilePath = filePath; + encryptedDoc.save_file(encryptedFilePath.c_str(), " "); + + std::cout << "File encrypted successfully. Encrypted file saved as: " << encryptedFilePath << std::endl; + + EVP_PKEY_free(publicKey); + + return true; +} diff --git a/libs/libencrypt/src/encryption.h b/libs/libencrypt/src/encryption.h new file mode 100644 index 00000000000..340d4b5e55d --- /dev/null +++ b/libs/libencrypt/src/encryption.h @@ -0,0 +1,85 @@ +#ifndef ENCRYPTION_H +#define ENCRYPTION_H + +#include +#include +#include +#include +#include +#include +#include "pugixml.hpp" +#include +#include +#include +#include +#include +#include "obfuscate.h" +#include +#include +#include +#include +//#include "config.h" +/** + * @class Encryption + * @brief Provides encryption and decryption functionality using RSA encryption algorithm. + */ +class Encryption { +public: + /** + * @brief Generates random session key + * + * @param sessionKey A pointer to session key + * @param keySize Session key length (128 bits for AES-128) + */ + static void generateSessionKey(unsigned char* sessionKey, size_t keySize); + + /** + * @brief Loads a public key from a file. + * + * @param filename The name of the file containing the public key. + * @return EVP_PKEY* A pointer to the loaded public key. + * Returns nullptr if the key file cannot be opened or there is an error reading the key. + */ + static EVP_PKEY* loadPublicKey(const std::string& filename); + + /** + * @brief + * + * @param sessionKey Key to be encrypted + * @param keySize Session key length + * @param publicKey The public key used for encryption + * @return std::string Encrypted session key + */ + static std::string encryptSessionKey(std::vector& sessionKey, EVP_PKEY* publicKey); + + /** + * @brief + * + * @param buffer pointer to data to be encoded + * @param length data length + * @return std::string encoded data + */ + static std::string base64Encode(const unsigned char* buffer, size_t length); + + /** + * @brief + * + * @param plaintext The plaintext to be encrypted. + * @param sessionKey The session key used for encryption. + * @param iv Initialization vector. + * @return std::string The encrypted ciphertext. + * Returns an empty string if there is an error during encryption. + */ + static std::string encryptData(const std::string& plaintext, std::vector& sessionKey, const unsigned char* iv); + + /** + * @brief Encrypts a file using the provided public key. + * + * @param filePath The path to the file to be encrypted. + * @param publicKeyFile The path to the file containing the public key. + * @return bool True if the file encryption is successful, false otherwise. + */ + static bool encryptFile(const std::string& publicKeyFile, std::string& filePath); +}; + +#endif // ENCRYPTION_H diff --git a/libs/libencrypt/src/obfuscate.h b/libs/libencrypt/src/obfuscate.h new file mode 100644 index 00000000000..5450eb44f01 --- /dev/null +++ b/libs/libencrypt/src/obfuscate.h @@ -0,0 +1,185 @@ +#ifndef OBFUSCATE_H +#define OBFUSCATE_H + +#ifdef _MSC_VER + #define AY_CAT(X,Y) AY_CAT2(X,Y) + #define AY_CAT2(X,Y) X##Y + #define AY_LINE int(AY_CAT(__LINE__,U)) +#else + #define AY_LINE __LINE__ +#endif + +#ifndef AY_OBFUSCATE_DEFAULT_KEY + // The default 64 bit key to obfuscate strings with. + // This can be user specified by defining AY_OBFUSCATE_DEFAULT_KEY before + // including obfuscate.h + #define AY_OBFUSCATE_DEFAULT_KEY ay::generate_key(AY_LINE) +#endif + +namespace ay +{ + using size_type = unsigned long long; + using key_type = unsigned long long; + + // Generate a pseudo-random key that spans all 8 bytes + constexpr key_type generate_key(key_type seed) + { + // Use the MurmurHash3 64-bit finalizer to hash our seed + key_type key = seed; + key ^= (key >> 33); + key *= 0xff51afd7ed558ccd; + key ^= (key >> 33); + key *= 0xc4ceb9fe1a85ec53; + key ^= (key >> 33); + + // Make sure that a bit in each byte is set + key |= 0x0101010101010101ull; + + return key; + } + + // Obfuscates or deobfuscates data with key + constexpr void cipher(char* data, size_type size, key_type key) + { + // Obfuscate with a simple XOR cipher based on key + for (size_type i = 0; i < size; i++) + { + data[i] ^= char(key >> ((i % 8) * 8)); + } + } + + // Obfuscates a string at compile time + template + class obfuscator + { + public: + // Obfuscates the string 'data' on construction + constexpr obfuscator(const char* data) + { + // Copy data + for (size_type i = 0; i < N; i++) + { + m_data[i] = data[i]; + } + + // On construction each of the characters in the string is + // obfuscated with an XOR cipher based on key + cipher(m_data, N, KEY); + } + + constexpr const char* data() const + { + return &m_data[0]; + } + + constexpr size_type size() const + { + return N; + } + + constexpr key_type key() const + { + return KEY; + } + + private: + + char m_data[N]{}; + }; + + // Handles decryption and re-encryption of an encrypted string at runtime + template + class obfuscated_data + { + public: + obfuscated_data(const obfuscator& obfuscator) + { + // Copy obfuscated data + for (size_type i = 0; i < N; i++) + { + m_data[i] = obfuscator.data()[i]; + } + } + + ~obfuscated_data() + { + // Zero m_data to remove it from memory + for (size_type i = 0; i < N; i++) + { + m_data[i] = 0; + } + } + + // Returns a pointer to the plain text string, decrypting it if + // necessary + operator char*() + { + decrypt(); + return m_data; + } + + // Manually decrypt the string + void decrypt() + { + if (m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = false; + } + } + + // Manually re-encrypt the string + void encrypt() + { + if (!m_encrypted) + { + cipher(m_data, N, KEY); + m_encrypted = true; + } + } + + // Returns true if this string is currently encrypted, false otherwise. + bool is_encrypted() const + { + return m_encrypted; + } + + private: + + // Local storage for the string. Call is_encrypted() to check whether or + // not the string is currently obfuscated. + char m_data[N]; + + // Whether data is currently encrypted + bool m_encrypted{ true }; + }; + + // This function exists purely to extract the number of elements 'N' in the + // array 'data' + template + constexpr auto make_obfuscator(const char(&data)[N]) + { + return obfuscator(data); + } +} + +// Obfuscates the string 'data' at compile-time and returns a reference to a +// ay::obfuscated_data object with global lifetime that has functions for +// decrypting the string and is also implicitly convertable to a char* +#define AY_OBFUSCATE(data) AY_OBFUSCATE_KEY(data, AY_OBFUSCATE_DEFAULT_KEY) + +// Obfuscates the string 'data' with 'key' at compile-time and returns a +// reference to a ay::obfuscated_data object with global lifetime that has +// functions for decrypting the string and is also implicitly convertable to a +// char* +#define AY_OBFUSCATE_KEY(data, key) \ + []() -> ay::obfuscated_data& { \ + static_assert(sizeof(decltype(key)) == sizeof(ay::key_type), "key must be a 64 bit unsigned integer"); \ + static_assert((key) >= (1ull << 56), " must span all 8 bytes"); \ + constexpr auto n = sizeof(data)/sizeof(data[0]); \ + constexpr auto obfuscator = ay::make_obfuscator(data); \ + static auto obfuscated_data = ay::obfuscated_data(obfuscator); \ + return obfuscated_data; \ + }() + +#endif diff --git a/libs/libpugiutil/CMakeLists.txt b/libs/libpugiutil/CMakeLists.txt index b7c2640c549..183afc81dad 100644 --- a/libs/libpugiutil/CMakeLists.txt +++ b/libs/libpugiutil/CMakeLists.txt @@ -17,7 +17,8 @@ target_include_directories(libpugiutil PUBLIC ${LIB_INCLUDE_DIRS}) set_target_properties(libpugiutil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix target_link_libraries(libpugiutil - libpugixml) + libpugixml + libdecrypt) install(TARGETS libpugiutil DESTINATION bin) install(FILES ${LIB_HEADERS} DESTINATION include/libpugiutil) diff --git a/libs/libpugiutil/src/pugixml_loc.cpp b/libs/libpugiutil/src/pugixml_loc.cpp index 138b7f39903..027b32a108d 100644 --- a/libs/libpugiutil/src/pugixml_loc.cpp +++ b/libs/libpugiutil/src/pugixml_loc.cpp @@ -52,4 +52,13 @@ void loc_data::build_loc_data() { fclose(f); } +void loc_data::build_loc_data_from_string(char* filename_val, size_t buffersize) { + for (std::size_t i = 0; i < buffersize; ++i) { + if (filename_val[i] == '\0') + break; + else if (filename_val[i] == '\n') { + offsets_.push_back(i); + } + } +} } // namespace pugiutil diff --git a/libs/libpugiutil/src/pugixml_loc.hpp b/libs/libpugiutil/src/pugixml_loc.hpp index 0f597a593b1..b8e11fded7d 100644 --- a/libs/libpugiutil/src/pugixml_loc.hpp +++ b/libs/libpugiutil/src/pugixml_loc.hpp @@ -7,7 +7,8 @@ #include #include "pugixml.hpp" - +#include "decryption.h" +#include namespace pugiutil { //pugi offset to line/col data based on: https://stackoverflow.com/questions/21003471/convert-pugixmls-result-offset-to-column-line @@ -20,6 +21,10 @@ class loc_data { build_loc_data(); } + loc_data(char* filename_val, size_t buffersize) { + build_loc_data_from_string(filename_val, buffersize); + } + //The filename this location data is for const std::string& filename() const { return filename_; } const char* filename_c_str() const { return filename_.c_str(); } @@ -42,7 +47,7 @@ class loc_data { private: void build_loc_data(); - + void build_loc_data_from_string(char* filename_val, size_t buffersize); std::string filename_; std::vector offsets_; }; diff --git a/libs/libpugiutil/src/pugixml_util.cpp b/libs/libpugiutil/src/pugixml_util.cpp index 1353f2114d1..6c5e8951cd9 100644 --- a/libs/libpugiutil/src/pugixml_util.cpp +++ b/libs/libpugiutil/src/pugixml_util.cpp @@ -8,21 +8,46 @@ namespace pugiutil { //Returns loc_data look-up for xml node line numbers loc_data load_xml(pugi::xml_document& doc, //Document object to be loaded with file contents const std::string filename) { //Filename to load from - auto location_data = loc_data(filename); - - auto load_result = doc.load_file(filename.c_str()); - if (!load_result) { - std::string msg = load_result.description(); - auto line = location_data.line(load_result.offset); - auto col = location_data.col(load_result.offset); - throw XmlError("Unable to load XML file '" + filename + "', " + msg - + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", - filename.c_str(), line); + //store the position of last '.' in the file name + size_t position = filename.find_last_of("."); + std::string result = ""; + if (position != std::string::npos) { + //store the characters after the '.' from the file_name string + result = filename.substr(position); + } + if (result == ".xmle") { + Decryption E1(filename); + std::string fn_file = E1.getDecryptedContent(); + size_t buffersize = fn_file.size(); + char* final = new char[buffersize]; + strcpy(final, fn_file.c_str()); + auto location_data = loc_data(final, buffersize); + auto load_result = doc.load_buffer(final, buffersize); + if (!load_result) { + std::string msg = load_result.description(); + auto line = location_data.line(load_result.offset); + auto col = location_data.col(load_result.offset); + throw XmlError("Unable to load XML file '" + filename + "', " + msg + + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", + filename.c_str(), line); + } + delete (final); + return location_data; + } else { + //auto location_data = loc_data(end_result_fname); + auto location_data = loc_data(filename); + auto load_result = doc.load_file(filename.c_str()); + if (!load_result) { + std::string msg = load_result.description(); + auto line = location_data.line(load_result.offset); + auto col = location_data.col(load_result.offset); + throw XmlError("Unable to load XML file '" + filename + "', " + msg + + " (line: " + std::to_string(line) + " col: " + std::to_string(col) + ")", + filename.c_str(), line); + } + return location_data; } - - return location_data; } - //Gets the first child element of the given name and returns it. // // node - The parent xml node diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index d23d3022baa..2bb43da89cb 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -52,6 +52,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat) { @@ -83,7 +84,7 @@ void check_rr_graph(const RRGraphView& rr_graph, t_rr_type rr_type = rr_graph.node_type(rr_node); int num_edges = rr_graph.num_edges(RRNodeId(inode)); - check_rr_node(rr_graph, rr_indexed_data, grid, chan_width, route_type, inode, is_flat); + check_rr_node(rr_graph, rr_indexed_data, grid, vib_grid, chan_width, route_type, inode, is_flat); /* Check all the connectivity (edges, etc.) information. */ edges.resize(0); @@ -270,7 +271,8 @@ void check_rr_graph(const RRGraphView& rr_graph, || (rr_graph.node_xhigh(rr_node) == int(grid.width()) - 2) || (rr_graph.node_yhigh(rr_node) == int(grid.height()) - 2)); bool is_wire = (rr_graph.node_type(rr_node) == CHANX - || rr_graph.node_type(rr_node) == CHANY); + || rr_graph.node_type(rr_node) == CHANY + || rr_graph.node_type(rr_node) == MEDIUM); if (!is_chain && !is_fringe && !is_wire) { if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) { @@ -331,6 +333,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, @@ -387,6 +390,13 @@ void check_rr_node(const RRGraphView& rr_graph, /* Check that the segment is within the array and such. */ type = grid.get_physical_type({xlow, ylow, layer_num}); + const VibInf* vib_type; + if (vib_grid.get_num_layers() > 0) { + vib_type = vib_grid.get_vib(layer_num, xlow, ylow); + } + else { + vib_type = nullptr; + } switch (rr_type) { case SOURCE: @@ -400,6 +410,7 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh); } break; + case SINK: { if (type == nullptr) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -413,6 +424,7 @@ void check_rr_node(const RRGraphView& rr_graph, } break; } + case MEDIUM: case IPIN: case OPIN: if (type == nullptr) { @@ -426,7 +438,7 @@ void check_rr_node(const RRGraphView& rr_graph, break; case CHANX: - if (xlow < 1 || xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { + if (xhigh > int(grid.width()) - 1 || yhigh > int(grid.height()) - 2 || yhigh != ylow) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: CHANX out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); } @@ -437,7 +449,7 @@ void check_rr_node(const RRGraphView& rr_graph, break; case CHANY: - if (xhigh > int(grid.width()) - 2 || ylow < 1 || yhigh > int(grid.height()) - 2 || xlow != xhigh) { + if (xhigh > int(grid.width()) - 2 || yhigh > int(grid.height()) - 1 || xlow != xhigh) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Error in check_rr_node: CHANY out of range for endpoints (%d,%d) and (%d,%d)\n", xlow, ylow, xhigh, yhigh); } @@ -456,6 +468,10 @@ void check_rr_node(const RRGraphView& rr_graph, int class_max_ptc = get_tile_class_max_ptc(type, is_flat); int pin_max_ptc = get_tile_pin_max_ptc(type, is_flat); + int medium_max_ptc = -1; + if (vib_type) { + medium_max_ptc = (int)vib_type->get_first_stages().size(); + } e_pin_type class_type = OPEN; int class_num_pins = -1; switch (rr_type) { @@ -473,7 +489,17 @@ void check_rr_node(const RRGraphView& rr_graph, "in check_rr_node: inode %d (type %d) had a capacity of %d.\n", inode, rr_type, capacity); } break; - + case MEDIUM: + VTR_ASSERT(medium_max_ptc >= 0); + if (ptc_num >= medium_max_ptc) { + VPR_ERROR(VPR_ERROR_ROUTE, + "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); + } + if (capacity != 1) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "in check_rr_node: inode %d (type %d) has a capacity of %d.\n", inode, rr_type, capacity); + } + break; case OPIN: case IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); diff --git a/libs/librrgraph/src/base/check_rr_graph.h b/libs/librrgraph/src/base/check_rr_graph.h index ee137e8a956..65f7d7c60d1 100644 --- a/libs/librrgraph/src/base/check_rr_graph.h +++ b/libs/librrgraph/src/base/check_rr_graph.h @@ -9,6 +9,7 @@ void check_rr_graph(const RRGraphView& rr_graph, const std::vector& types, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const t_graph_type graph_type, bool is_flat); @@ -16,6 +17,7 @@ void check_rr_graph(const RRGraphView& rr_graph, void check_rr_node(const RRGraphView& rr_graph, const vtr::vector& rr_indexed_data, const DeviceGrid& grid, + const VibDeviceGrid& vib_grid, const t_chan_width& chan_width, const enum e_route_type route_type, const int inode, diff --git a/libs/librrgraph/src/base/get_parallel_segs.cpp b/libs/librrgraph/src/base/get_parallel_segs.cpp index d20b3066992..adc3bce4f64 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.cpp +++ b/libs/librrgraph/src/base/get_parallel_segs.cpp @@ -4,14 +4,17 @@ *Segments that have BOTH_AXIS attribute value are always included in the returned vector.*/ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, - enum e_parallel_axis parallel_axis) { + enum e_parallel_axis parallel_axis, + bool keep_original_index) { std::vector result; for (size_t i = 0; i < segment_inf.size(); ++i) { if (segment_inf[i].parallel_axis == parallel_axis || segment_inf[i].parallel_axis == BOTH_AXIS) { result.push_back(segment_inf[i]); - result[result.size() - 1].seg_index = i; + if (!keep_original_index) { + result[result.size() - 1].seg_index = i; + } seg_index_map.insert(std::make_pair(i, std::make_pair(result.size() - 1, parallel_axis))); } } return result; -} \ No newline at end of file +} diff --git a/libs/librrgraph/src/base/get_parallel_segs.h b/libs/librrgraph/src/base/get_parallel_segs.h index c88b2c88701..70539863dda 100644 --- a/libs/librrgraph/src/base/get_parallel_segs.h +++ b/libs/librrgraph/src/base/get_parallel_segs.h @@ -6,6 +6,7 @@ std::vector get_parallel_segs(const std::vector& segment_inf, t_unified_to_parallel_seg_index& seg_index_map, - enum e_parallel_axis parallel_axis); + enum e_parallel_axis parallel_axis, + bool keep_original_index = false); -#endif \ No newline at end of file +#endif diff --git a/libs/librrgraph/src/base/rr_graph_builder.cpp b/libs/librrgraph/src/base/rr_graph_builder.cpp index 565c99e3f75..fbf442e1972 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.cpp +++ b/libs/librrgraph/src/base/rr_graph_builder.cpp @@ -1,13 +1,18 @@ +#include "vtr_assert.h" #include "vtr_log.h" #include "rr_graph_builder.h" #include "vtr_time.h" +#include "vtr_tokenizer.h" #include #include //#include //#include "globals.h" -RRGraphBuilder::RRGraphBuilder() {} +RRGraphBuilder::RRGraphBuilder() { + is_edge_dirty_ = true; + is_incoming_edge_dirty_ = true; +} t_rr_graph_storage& RRGraphBuilder::rr_nodes() { return node_storage_; @@ -25,6 +30,14 @@ MetadataStorage>& RRGraphBuilder::rr_edge_metadata() return rr_edge_metadata_; } +vtr::vector>& RRGraphBuilder::node_in_edge_storage() { + return node_in_edges_; +} + +vtr::vector>& RRGraphBuilder::node_ptc_storage() { + return node_ptc_nums_; +} + void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { t_rr_type node_type = node_storage_.node_type(node); short node_ptc_num = node_storage_.node_ptc_num(node); @@ -64,6 +77,32 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) { } } +RRNodeId RRGraphBuilder::create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side) { + e_side node_side = TOTAL_2D_SIDES[0]; + /* Only OPIN and IPIN nodes have sides, otherwise force to use a default side */ + if (OPIN == type || IPIN == type) { + node_side = side; + } + node_storage_.emplace_back(); + node_ptc_nums_.emplace_back(); + RRNodeId new_node = RRNodeId(node_storage_.size() - 1); + node_storage_.set_node_layer(new_node, layer); + node_storage_.set_node_type(new_node, type); + node_storage_.set_node_coordinates(new_node, x, y, x, y); + node_storage_.set_node_ptc_num(new_node, ptc); + if (OPIN == type || IPIN == type) { + node_storage_.add_node_side(new_node, node_side); + } + /* Special for CHANX, being consistent with the rule in find_node() */ + if (CHANX == type) { + node_lookup_.add_node(new_node, layer, y, x, type, ptc, node_side); + } else { + node_lookup_.add_node(new_node, layer, x, y, type, ptc, node_side); + } + + return new_node; +} + void RRGraphBuilder::init_edge_remap(bool val) { node_storage_.init_edge_remap(val); } @@ -75,10 +114,15 @@ void RRGraphBuilder::clear_temp_storage() { void RRGraphBuilder::clear() { node_lookup_.clear(); node_storage_.clear(); + node_in_edges_.clear(); + node_ptc_nums_.clear(); rr_node_metadata_.clear(); rr_edge_metadata_.clear(); rr_segments_.clear(); rr_switch_inf_.clear(); + edges_to_build_.clear(); + is_edge_dirty_ = true; + is_incoming_edge_dirty_ = true; } void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_nodes_algorithm, @@ -150,3 +194,135 @@ void RRGraphBuilder::reorder_nodes(e_rr_node_reorder_algorithm reorder_rr_graph_ std::get<2>(edge)); }); } + +void RRGraphBuilder::create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch, bool remapped) { + edges_to_build_.emplace_back(src, dest, size_t(edge_switch), remapped); + is_edge_dirty_ = true; /* Adding a new edge revokes the flag */ + is_incoming_edge_dirty_ = true; +} + +void RRGraphBuilder::build_edges(const bool& uniquify) { + if (uniquify) { + std::sort(edges_to_build_.begin(), edges_to_build_.end()); + edges_to_build_.erase(std::unique(edges_to_build_.begin(), edges_to_build_.end()), edges_to_build_.end()); + } + alloc_and_load_edges(&edges_to_build_); + edges_to_build_.clear(); + is_edge_dirty_ = false; +} + +void RRGraphBuilder::build_in_edges() { + VTR_ASSERT(validate()); + node_in_edges_.clear(); + node_in_edges_.resize(node_storage_.size()); + + for (RRNodeId src_node : vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + for (auto iedge : node_storage_.edges(src_node)) { + VTR_ASSERT(src_node == node_storage_.edge_source_node(node_storage_.edge_id(src_node, iedge))); + RRNodeId des_node = node_storage_.edge_sink_node(node_storage_.edge_id(src_node, iedge)); + node_in_edges_[des_node].push_back(node_storage_.edge_id(src_node, iedge)); + } + } + is_incoming_edge_dirty_ = false; +} + +std::vector RRGraphBuilder::node_in_edges(RRNodeId node) const { + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (is_incoming_edge_dirty_) { + VTR_LOG_ERROR("Incoming edges are not built yet in routing resource graph. Please call build_in_edges()."); + return std::vector(); + } + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; +} + +void RRGraphBuilder::set_node_ptc_nums(RRNodeId node, const std::string& ptc_str) { + VTR_ASSERT(size_t(node) < node_storage_.size()); + std::vector ptc_tokens = vtr::StringToken(ptc_str).split(","); + VTR_ASSERT(ptc_tokens.size() >= 1); + set_node_ptc_num(node, std::stoi(ptc_tokens[0])); + if (ptc_tokens.size() > 1) { + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + node_ptc_nums_[node].resize(ptc_tokens.size()); + for (size_t iptc = 0; iptc < ptc_tokens.size(); iptc++) { + node_ptc_nums_[node][iptc] = std::stoi(ptc_tokens[iptc]); + } + } +} + +std::string RRGraphBuilder::node_ptc_nums_to_string(RRNodeId node) const { + if (node_ptc_nums_.empty()) { + return std::to_string(size_t(node_storage_.node_ptc_num(node))); +// VTR_LOG("Node ptc single: %d -> string %s\n", node_storage_.node_ptc_num(node), ret.c_str()); + } + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + if (node_ptc_nums_[node].empty()) { + return std::to_string(size_t(node_storage_.node_ptc_num(node))); + } + std::string ret; + for (size_t iptc = 0; iptc < node_ptc_nums_[node].size(); iptc++) { + ret += std::to_string(size_t(node_ptc_nums_[node][iptc])) + ","; + } + /* Remove the last comma */ + ret.pop_back(); + return ret; +} + +bool RRGraphBuilder::node_contain_multiple_ptc(RRNodeId node) const { + if (node_ptc_nums_.empty()) { + return false; + } + return node_ptc_nums_[node].size() > 1; +} + +void RRGraphBuilder::add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id) { + VTR_ASSERT(size_t(node) < node_storage_.size()); + VTR_ASSERT(size_t(node) < node_ptc_nums_.size()); + VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Track number valid only for CHANX/CHANY RR nodes"); + + size_t node_length = std::abs(node_storage_.node_xhigh(node) - node_storage_.node_xlow(node)) + + std::abs(node_storage_.node_yhigh(node) - node_storage_.node_ylow(node)); + if (node_length + 1 != node_ptc_nums_[node].size()) { + node_ptc_nums_[node].resize(node_length + 1); + } + + size_t offset = node_offset.x() - node_storage_.node_xlow(node) + node_offset.y() - node_storage_.node_ylow(node); + VTR_ASSERT(offset < node_ptc_nums_[node].size()); + + node_ptc_nums_[node][offset] = track_id; +} + +void RRGraphBuilder::add_track_node_to_lookup(RRNodeId node) { + VTR_ASSERT_MSG(node_storage_.node_type(node) == CHANX || node_storage_.node_type(node) == CHANY, "Update track node look-up is only valid to CHANX/CHANY nodes"); + + /* Compute the track id based on the (x, y) coordinate */ + size_t x_start = std::min(node_storage_.node_xlow(node), node_storage_.node_xhigh(node)); + size_t y_start = std::min(node_storage_.node_ylow(node), node_storage_.node_yhigh(node)); + std::vector node_x(std::abs(node_storage_.node_xlow(node) - node_storage_.node_xhigh(node)) + 1); + std::vector node_y(std::abs(node_storage_.node_ylow(node) - node_storage_.node_yhigh(node)) + 1); + + std::iota(node_x.begin(), node_x.end(), x_start); + std::iota(node_y.begin(), node_y.end(), y_start); + + VTR_ASSERT(size_t(std::max(node_storage_.node_xlow(node), node_storage_.node_xhigh(node))) == node_x.back()); + VTR_ASSERT(size_t(std::max(node_storage_.node_ylow(node), node_storage_.node_yhigh(node))) == node_y.back()); + + for (const size_t& x : node_x) { + for (const size_t& y : node_y) { + size_t ptc = node_storage_.node_ptc_num(node); + /* Routing channel nodes may have different ptc num + * Find the track ids using the x/y offset + * FIXME: Special case on assigning CHANX (x,y) should be changed to a natural way! + */ + if (CHANX == node_storage_.node_type(node)) { + ptc = node_ptc_nums_[node][x - node_storage_.node_xlow(node)]; + node_lookup_.add_node(node, node_storage_.node_layer(node), y, x, CHANX, ptc); + } else if (CHANY == node_storage_.node_type(node)) { + ptc = node_ptc_nums_[node][y - node_storage_.node_ylow(node)]; + node_lookup_.add_node(node, node_storage_.node_layer(node), x, y, CHANY, ptc); + } + } + } +} diff --git a/libs/librrgraph/src/base/rr_graph_builder.h b/libs/librrgraph/src/base/rr_graph_builder.h index cc367395bc6..f07e135b515 100644 --- a/libs/librrgraph/src/base/rr_graph_builder.h +++ b/libs/librrgraph/src/base/rr_graph_builder.h @@ -16,6 +16,7 @@ #include "rr_graph_storage.h" #include "rr_spatial_lookup.h" #include "metadata_storage.h" +#include "rr_edge.h" class RRGraphBuilder { /* -- Constructors -- */ @@ -44,6 +45,10 @@ class RRGraphBuilder { MetadataStorage& rr_node_metadata(); /** @brief Return a writable object for the meta data on the edge */ MetadataStorage>& rr_edge_metadata(); + /** @brief Return a writable object fo the incoming edge storage */ + vtr::vector>& node_in_edge_storage(); + /** @brief Return a writable object of the node ptc storage (for tileable routing resource graph) */ + vtr::vector>& node_ptc_storage(); /** @brief Return the size for rr_node_metadata */ inline size_t rr_node_metadata_size() const { @@ -123,10 +128,16 @@ class RRGraphBuilder { node_storage_.set_node_type(id, type); } + /** @brief Create a new rr_node in the node storage and register it to the node look-up. + * Return a valid node id if succeed. Otherwise, return an invalid id. + */ + RRNodeId create_node(int layer, int x, int y, t_rr_type type, int ptc, e_side side = NUM_2D_SIDES); + /** @brief Set the node name with a given valid id */ inline void set_node_name(RRNodeId id, std::string name) { node_storage_.set_node_name(id, name); } + /** * @brief Add an existing rr_node in the node storage to the node look-up * @@ -181,10 +192,13 @@ class RRGraphBuilder { inline void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2) { node_storage_.set_node_coordinates(id, x1, y1, x2, y2); } - - /** @brief Set the node layer (specifies which die the node is located at) */ - inline void set_node_layer(RRNodeId id, short layer){ - node_storage_.set_node_layer(id,layer); + + inline void set_node_bend_start(RRNodeId id, size_t bend_start) { + node_storage_.set_node_bend_start(id, bend_start); + } + + inline void set_node_bend_end(RRNodeId id, size_t bend_end) { + node_storage_.set_node_bend_end(id, bend_end); } /** @brief The ptc_num carries different meanings for different node types @@ -211,7 +225,6 @@ class RRGraphBuilder { node_storage_.set_node_ptc_twist_incr(id, twist); } - /** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */ inline void set_node_pin_num(RRNodeId id, int new_pin_num) { node_storage_.set_node_pin_num(id, new_pin_num); @@ -222,16 +235,57 @@ class RRGraphBuilder { node_storage_.set_node_track_num(id, new_track_num); } - /** @brief set_ node_class_num() is designed for routing source and sinks, which are SOURCE and SINK nodes */ + /** @brief Add a track id for a given node base on the offset in coordinate, applicable only to CHANX and CHANY nodes. + * This API is used by tileable routing resource graph generator, which requires each routing track has a different + * track id depending their location in FPGA fabric. + */ + void add_node_track_num(RRNodeId node, vtr::Point node_offset, short track_id); + + /** @brief Update the node_lookup for a track node. This is applicable to tileable routing graph */ + void add_track_node_to_lookup(RRNodeId node); + + /** @brief set_node_class_num() is designed for routing source and sinks, which are SOURCE and SINK nodes */ inline void set_node_class_num(RRNodeId id, int new_class_num) { node_storage_.set_node_class_num(id, new_class_num); } + /** @brief set_node_medium_num() is designed for routing medium nodes */ + inline void set_node_medium_num(RRNodeId id, int new_class_num) { + node_storage_.set_node_medium_num(id, new_class_num); + } + + /** @brief Add a list of ptc number in string (split by comma) to a given node. This function is used by rr graph reader only. Not suggested for internal builder!!! */ + void set_node_ptc_nums(RRNodeId node, const std::string& ptc_str); + + /** @brief With a given node, output ptc numbers into a string (use comma as delima). This function is used by rr graph writer only. Not suggested for internal builder!!! */ + std::string node_ptc_nums_to_string(RRNodeId node) const; + + /** @brief Identify if a node contains multiple ptc numbers. Mainly used by I/O reader only. Not suggest for internal builder */ + bool node_contain_multiple_ptc(RRNodeId node) const; + /** @brief Set the node direction; The node direction is only available of routing channel nodes, such as x-direction routing tracks (CHANX) and y-direction routing tracks (CHANY). For other nodes types, this value is not meaningful and should be set to NONE. */ inline void set_node_direction(RRNodeId id, Direction new_direction) { node_storage_.set_node_direction(id, new_direction); } + /** @brief Add a new edge to the cache of edges to be built + * .. note:: This will not add an edge to storage! You need to call build_edges() after all the edges are cached! */ + void create_edge(RRNodeId src, RRNodeId dest, RRSwitchId edge_switch, bool remapped); + + /** @brief Allocate and build actual edges in storage. + * Once called, the cached edges will be uniquified and added to routing resource nodes, + * while the cache will be empty once build-up is accomplished */ + void build_edges(const bool& uniquify = true); + + /** @brief Allocate and build incoming edges for each node. + * By default, no incoming edges are kept in storage, to be memory efficient */ + void build_in_edges(); + + /** @brief Return incoming edges for a given routing resource node + * Require build_in_edges() to be called first + */ + std::vector node_in_edges(RRNodeId node) const; + /** @brief Set the node id for clock network virtual sink */ inline void set_virtual_clock_network_root_idx(RRNodeId virtual_clock_network_root_idx) { node_storage_.set_virtual_clock_network_root_idx(virtual_clock_network_root_idx); @@ -301,6 +355,9 @@ class RRGraphBuilder { return node_storage_.count_rr_switches(arch_switch_inf, arch_switch_fanins); } + /* Unlock storage; required to modify an routing resource graph after edge is read */ + inline void unlock_storage() { node_storage_.edges_read_ = false; node_storage_.partitioned_ = false; node_storage_.clear_node_first_edge();} + /** @brief Reserve the lists of nodes, edges, switches etc. to be memory efficient. * This function is mainly used to reserve memory space inside RRGraph, * when adding a large number of nodes/edge/switches/segments, @@ -319,6 +376,11 @@ class RRGraphBuilder { inline void resize_nodes(size_t size) { node_storage_.resize(size); } + /** @brief This function resize node ptc nums. Only used by RR graph I/O reader and writers. Do not use for internal builder */ + inline void resize_node_ptc_nums(size_t size) { + node_ptc_nums_.resize(size); + } + /** @brief This function resize node ptc twist increment; Since it is only used for tileable rr-graph, we don't put it in general resize function*/ inline void resize_ptc_twist_incr(size_t size){ @@ -330,13 +392,13 @@ class RRGraphBuilder { rr_switch_inf_.resize(size); } - /** @brief Validate that edge data is partitioned correctly + /** @brief Validate that edge data is partitioned correctly. Also there are no edges left to be built! * @note This function is used to validate the correctness of the routing resource graph in terms * of graph attributes. Strongly recommend to call it when you finish the building a routing resource * graph. If you need more advance checks, which are related to architecture features, you should * consider to use the check_rr_graph() function or build your own check_rr_graph() function. */ inline bool validate() const { - return node_storage_.validate(rr_switch_inf_); + return node_storage_.validate(rr_switch_inf_) && edges_to_build_.empty(); } /** @brief Sorts edge data such that configurable edges appears before @@ -383,6 +445,14 @@ class RRGraphBuilder { /* Fast look-up for rr nodes */ RRSpatialLookup node_lookup_; + /* A cache for edge-related information, required to build edges for routing resource nodes. + * It is used when building a routing resource graph by considering memory efficiency. + * It will be clear up after calling build_edges(). + * + * .. warning:: This is a temporary data which is used to collect edges to be built for nodes + */ + t_rr_edge_info_set edges_to_build_; + /** Wire segment types in RR graph * - Each rr_segment contains the detailed information of a routing track, which is denoted by a node in CHANX or CHANY type. * - We use a fly-weight data structure here, in the same philosophy as the rr_indexed_data. See detailed explanation in the t_segment_inf data structure @@ -396,6 +466,29 @@ class RRGraphBuilder { /* Detailed information about the switches, which are used in the RRGraph */ vtr::vector rr_switch_inf_; + /** A list of incoming edges for each routing resource node. This can be built optionally, as required by applications. + * By default, it is empty! Call build_in_edges() to construct it!!! */ + vtr::vector> node_in_edges_; + + /* Extra ptc number for each routing resource node. This is required by tileable routing resource graph. + * In a tileable routing architecture, routing tracks, e.g., CHANX and CHANY, follows a staggered organization. + * Hence, a routing track may appear in different routing channels, representing different ptc/track id. + * Here is an illustrative example of a X-direction routing track (CHANX) in INC direction, which is organized in staggered way. + * + * Coord(x,y) (1,0) (2,0) (3,0) (4,0) Another track (node) + * ptc=0 ------> ------> + * \ / + * ptc=1 ------> / + * \ / + * ptc=2 ------> / + * \ / + * ptc=3 -------> + * ^ ^ + * | | + * starting point ending point + */ + vtr::vector> node_ptc_nums_; + /** @warning The Metadata should stay as an independent data structure from the rest of the internal data, * e.g., node_lookup! */ /* Metadata is an extra data on rr-nodes and edges, respectively, that is not used by vpr @@ -420,6 +513,11 @@ class RRGraphBuilder { * value: map of */ MetadataStorage> rr_edge_metadata_; + + /** @brief a flag to mark the status of edge storage + * dirty means that the edge storage is not complete, should call related APIs to build */ + bool is_edge_dirty_; + bool is_incoming_edge_dirty_; }; #endif diff --git a/libs/librrgraph/src/base/rr_graph_cost.h b/libs/librrgraph/src/base/rr_graph_cost.h index 00c14c912c2..6ad8be9e1b8 100644 --- a/libs/librrgraph/src/base/rr_graph_cost.h +++ b/libs/librrgraph/src/base/rr_graph_cost.h @@ -15,9 +15,10 @@ enum e_base_cost_type { enum e_cost_indices { SOURCE_COST_INDEX = 0, SINK_COST_INDEX, + MEDIUM_COST_INDEX, OPIN_COST_INDEX, IPIN_COST_INDEX, CHANX_COST_INDEX_START }; -#endif \ No newline at end of file +#endif diff --git a/libs/librrgraph/src/base/rr_graph_fwd.h b/libs/librrgraph/src/base/rr_graph_fwd.h index 41d0b8f3d58..2f685e4c15a 100644 --- a/libs/librrgraph/src/base/rr_graph_fwd.h +++ b/libs/librrgraph/src/base/rr_graph_fwd.h @@ -1,8 +1,7 @@ -#ifndef RR_GRAPH_OBJ_FWD_H -#define RR_GRAPH_OBJ_FWD_H +#ifndef RR_GRAPH_FWD_H +#define RR_GRAPH_FWD_H #include - #include "vtr_strong_id.h" /*************************************************************** @@ -14,8 +13,6 @@ //Forward declaration class t_rr_graph_storage; -class RRGraph; - struct rr_node_id_tag; struct rr_edge_id_tag; struct rr_indexed_data_id_tag; diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 8d8dcd5ac20..e76de6e4e83 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -389,7 +389,10 @@ void t_rr_graph_storage::assign_first_edges() { bool t_rr_graph_storage::verify_first_edges() const { size_t num_edges = edge_src_node_.size(); - VTR_ASSERT(node_first_edge_[RRNodeId(node_storage_.size())] == RREdgeId(num_edges)); + if (node_first_edge_[RRNodeId(node_storage_.size())] != RREdgeId(num_edges)) { + VTR_LOG("node first edge is '%lu' while expected edge id is '%lu'\n", size_t(node_first_edge_[RRNodeId(node_storage_.size())]), num_edges); + VTR_ASSERT(node_first_edge_[RRNodeId(node_storage_.size())] == RREdgeId(num_edges)); + } // Each edge should belong with the edge range defined by // [node_first_edge_[src_node], node_first_edge_[src_node+1]). @@ -567,6 +570,11 @@ t_edge_size t_rr_graph_storage::num_non_configurable_edges(RRNodeId node, const return num_edges(node) - num_configurable_edges(node, rr_switches); } +bool t_rr_graph_storage::edge_is_configurable(RREdgeId edge, const vtr::vector& rr_switches) const { + auto iswitch = edge_switch(edge); + return rr_switches[RRSwitchId(iswitch)].configurable(); +} + bool t_rr_graph_storage::edge_is_configurable(RRNodeId id, t_edge_size iedge, const vtr::vector& rr_switches) const { auto iswitch = edge_switch(id, iedge); return rr_switches[RRSwitchId(iswitch)].configurable(); @@ -641,25 +649,32 @@ void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) { } void t_rr_graph_storage::set_node_pin_num(RRNodeId id, int new_pin_num) { if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.pin_num = new_pin_num; } void t_rr_graph_storage::set_node_track_num(RRNodeId id, int new_track_num) { if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'track_num' for non-CHANX/CHANY type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.track_num = new_track_num; } void t_rr_graph_storage::set_node_class_num(RRNodeId id, int new_class_num) { if (node_type(id) != SOURCE && node_type(id) != SINK) { - VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'class_num' for non-SOURCE/SINK type '%s'\n", node_type_string(id)); } node_ptc_[id].ptc_.class_num = new_class_num; } +void t_rr_graph_storage::set_node_medium_num(RRNodeId id, int new_medium_num) { + if (node_type(id) != MEDIUM) { + VTR_LOG_ERROR("Attempted to set RR node 'medium_num' for non-MEDIUM type '%s'\n", node_type_string(id)); + } + node_ptc_[id].ptc_.medium_num = new_medium_num; +} + int t_rr_graph_storage::node_ptc_num(RRNodeId id) const { return node_ptc_[id].ptc_.pin_num; } @@ -670,7 +685,7 @@ static int get_node_pin_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != IPIN && node_type != OPIN) { - VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'pin_num' for non-IPIN/OPIN type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.pin_num; } @@ -681,7 +696,7 @@ static int get_node_track_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != CHANX && node_type != CHANY) { - VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'track_num' for non-CHANX/CHANY type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.track_num; } @@ -692,11 +707,22 @@ static int get_node_class_num( RRNodeId id) { auto node_type = node_storage[id].type_; if (node_type != SOURCE && node_type != SINK) { - VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'", rr_node_typename[node_type]); + VTR_LOG_ERROR("Attempted to access RR node 'class_num' for non-SOURCE/SINK type '%s'\n", rr_node_typename[node_type]); } return node_ptc[id].ptc_.class_num; } +static int get_node_medium_num( + vtr::array_view_id node_storage, + vtr::array_view_id node_ptc, + RRNodeId id) { + auto node_type = node_storage[id].type_; + if (node_type != MEDIUM) { + VTR_LOG_ERROR("Attempted to access RR node 'medium_num' for non-MEDIUM type '%s'\n", rr_node_typename[node_type]); + } + return node_ptc[id].ptc_.medium_num; +} + int t_rr_graph_storage::node_pin_num(RRNodeId id) const { return get_node_pin_num( vtr::make_const_array_view_id(node_storage_), @@ -715,6 +741,12 @@ int t_rr_graph_storage::node_class_num(RRNodeId id) const { vtr::make_const_array_view_id(node_ptc_), id); } +int t_rr_graph_storage::node_medium_num(RRNodeId id) const { + return get_node_medium_num( + vtr::make_const_array_view_id(node_storage_), + vtr::make_const_array_view_id(node_ptc_), + id); +} void t_rr_graph_storage::set_node_type(RRNodeId id, t_rr_type new_type) { node_storage_[id].type_ = new_type; @@ -742,10 +774,20 @@ void t_rr_graph_storage::set_node_coordinates(RRNodeId id, short x1, short y1, s } } +void t_rr_graph_storage::set_node_bend_start(RRNodeId id, size_t bend_start) { + auto& node = node_storage_[id]; + node.node_bend_start_ = bend_start; +} + +void t_rr_graph_storage::set_node_bend_end(RRNodeId id, size_t bend_end) { + auto& node = node_storage_[id]; + node.node_bend_end_ = bend_end; +} + void t_rr_graph_storage::set_node_cost_index(RRNodeId id, RRIndexedDataId new_cost_index) { auto& node = node_storage_[id]; if ((size_t)new_cost_index >= std::numeric_limits::max()) { - VTR_LOG_ERROR("Attempted to set cost_index_ %zu above cost_index storage max value.", + VTR_LOG_ERROR("Attempted to set cost_index_ %zu above cost_index storage max value.\n", new_cost_index); } node.cost_index_ = (size_t)new_cost_index; @@ -762,14 +804,14 @@ void t_rr_graph_storage::set_node_capacity(RRNodeId id, short new_capacity) { void t_rr_graph_storage::set_node_direction(RRNodeId id, Direction new_direction) { if (node_type(id) != CHANX && node_type(id) != CHANY) { - VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'direction' for non-channel type '%s'\n", node_type_string(id)); } node_storage_[id].dir_side_.direction = new_direction; } void t_rr_graph_storage::add_node_side(RRNodeId id, e_side new_side) { if (node_type(id) != IPIN && node_type(id) != OPIN) { - VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'", node_type_string(id)); + VTR_LOG_ERROR("Attempted to set RR node 'side' for non-channel type '%s'\n", node_type_string(id)); } std::bitset side_bits = node_storage_[id].dir_side_.sides; side_bits[size_t(new_side)] = true; @@ -805,6 +847,9 @@ int t_rr_graph_view::node_track_num(RRNodeId id) const { int t_rr_graph_view::node_class_num(RRNodeId id) const { return get_node_class_num(node_storage_, node_ptc_, id); } +int t_rr_graph_view::node_medium_num(RRNodeId id) const { + return get_node_medium_num(node_storage_, node_ptc_, id); +} t_rr_graph_view t_rr_graph_storage::view() const { diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index 82c8f0b2326..adc2f507483 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -54,7 +54,7 @@ * side: The side of a grid location where an IPIN or OPIN is located. * * This field is valid only for IPINs and OPINs and should be ignored * * otherwise. */ -struct alignas(16) t_rr_node_data { +struct alignas(32) t_rr_node_data { int16_t cost_index_ = -1; int16_t rc_index_ = -1; @@ -62,17 +62,20 @@ struct alignas(16) t_rr_node_data { int16_t ylow_ = -1; int16_t xhigh_ = -1; int16_t yhigh_ = -1; + + int16_t node_bend_start_ = 0; + int16_t node_bend_end_ = 0; t_rr_type type_ = NUM_RR_TYPES; /* The character is a hex number which is a 4-bit truth table for node sides - * The 4-bits in serial represent 4 sides on which a node could appear - * It follows a fixed sequence, which is (LEFT, BOTTOM, RIGHT, TOP) whose indices are (3, 2, 1, 0) + * The 4-bits in serial represent 4 sides on which a node could appear + * It follows a fixed sequence, which is (LEFT, BOTTOM, RIGHT, TOP) whose indices are (3, 2, 1, 0) * - When a node appears on a given side, it is set to "1" * - When a node does not appear on a given side, it is set to "0" * For example, - * - '1' means '0001' in hex number, which means the node appears on TOP - * - 'A' means '1100' in hex number, which means the node appears on LEFT and BOTTOM sides, + * - '1' means '0001' in hex number, which means the node appears on TOP + * - 'A' means '1100' in hex number, which means the node appears on LEFT and BOTTOM sides, */ union { Direction direction; //Valid only for CHANX/CHANY @@ -86,8 +89,8 @@ struct alignas(16) t_rr_node_data { // t_rr_node_data is a key data structure, so fail at compile time if the // structure gets bigger than expected (16 bytes right now). Developers // should only expand it after careful consideration and measurement. -static_assert(sizeof(t_rr_node_data) == 16, "Check t_rr_node_data size"); -static_assert(alignof(t_rr_node_data) == 16, "Check t_rr_node_data size"); +static_assert(sizeof(t_rr_node_data) == 32, "Check t_rr_node_data size"); +static_assert(alignof(t_rr_node_data) == 32, "Check t_rr_node_data size"); /* t_rr_node_ptc_data is cold data is therefore kept seperate from * t_rr_node_data. @@ -99,6 +102,7 @@ struct t_rr_node_ptc_data { int pin_num; int track_num; int class_num; + int medium_num; } ptc_; }; @@ -185,6 +189,13 @@ class t_rr_graph_storage { short node_yhigh(RRNodeId id) const { return node_storage_[id].yhigh_; } + + short node_bend_start(RRNodeId id) const { + return node_storage_[id].node_bend_start_; + } + short node_bend_end(RRNodeId id) const { + return node_storage_[id].node_bend_end_; + } short node_capacity(RRNodeId id) const { return node_storage_[id].capacity_; @@ -223,6 +234,7 @@ class t_rr_graph_storage { int node_pin_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_track_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_class_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent + int node_medium_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent /** @brief Retrieve fan_in for RRNodeId, init_fan_in must have been called first. */ t_edge_size fan_in(RRNodeId id) const { @@ -338,6 +350,7 @@ class t_rr_graph_storage { * - num_non_configurable_edges(RRNodeId) * - edge_id(RRNodeId, t_edge_size) * - edge_sink_node(RRNodeId, t_edge_size) + * - edge_source_node(RRNodeId, t_edge_size) * - edge_switch(RRNodeId, t_edge_size) * * Only call these methods after partition_edges has been invoked. @@ -356,6 +369,7 @@ class t_rr_graph_storage { t_edge_size num_edges(const RRNodeId& id) const { return size_t(last_edge(id)) - size_t(first_edge(id)); } + bool edge_is_configurable(RREdgeId edge, const vtr::vector& rr_switches) const; bool edge_is_configurable(RRNodeId id, t_edge_size iedge, const vtr::vector& rr_switches) const; t_edge_size num_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; t_edge_size num_non_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; @@ -412,6 +426,11 @@ class t_rr_graph_storage { return edge_dest_node_[edge]; } + // Get the source node for the specified edge. + RRNodeId edge_source_node(const RREdgeId& edge) const { + return edge_src_node_[edge]; + } + /** @brief Call the `apply` function with the edge id, source, and sink nodes of every edge. */ void for_each_edge(std::function apply) const { for (size_t i = 0; i < edge_dest_node_.size(); i++) { @@ -429,6 +448,11 @@ class t_rr_graph_storage { return edge_sink_node(edge_id(id, iedge)); } + // Get the source node for the iedge'th edge from specified RRNodeId. + RRNodeId edge_source_node(const RRNodeId& id, t_edge_size iedge) const { + return edge_source_node(edge_id(id, iedge)); + } + /** @brief Get the switch used for the specified edge. */ short edge_switch(const RREdgeId& edge) const { return edge_switch_[edge]; @@ -604,6 +628,7 @@ class t_rr_graph_storage { void set_node_pin_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_track_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_class_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent + void set_node_medium_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_type(RRNodeId id, t_rr_type new_type); void set_node_name(RRNodeId id, std::string new_name); @@ -611,6 +636,8 @@ class t_rr_graph_storage { void set_node_layer(RRNodeId id, short layer); void set_node_ptc_twist_incr(RRNodeId id, short twist); void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index); + void set_node_bend_start(RRNodeId id, size_t bend_start); + void set_node_bend_end(RRNodeId id, size_t bend_end); void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index); void set_node_capacity(RRNodeId, short new_capacity); void set_node_direction(RRNodeId, Direction new_direction); @@ -773,6 +800,7 @@ class t_rr_graph_storage { return side_tt[size_t(side)]; } + public: inline void clear_node_first_edge() { node_first_edge_.clear(); } @@ -1003,6 +1031,7 @@ class t_rr_graph_view { int node_pin_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_track_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_class_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent + int node_medium_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent /** * @brief Retrieve the fan-in for a given RRNodeId. diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index c7fb3fd66c8..e3f2d3cdfb9 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -11,8 +11,8 @@ * the function declaration */ #include -#include "rr_graph_fwd.h" #include "rr_node_types.h" +#include "rr_graph_obj.h" #include "rr_graph_view.h" #include "device_grid.h" @@ -99,4 +99,4 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) * @return limited_to_opin */ bool inter_layer_connections_limited_to_opin(const RRGraphView& rr_graph); -#endif \ No newline at end of file +#endif diff --git a/libs/librrgraph/src/base/rr_graph_view.cpp b/libs/librrgraph/src/base/rr_graph_view.cpp index 0ddc5445d42..225af722e5b 100644 --- a/libs/librrgraph/src/base/rr_graph_view.cpp +++ b/libs/librrgraph/src/base/rr_graph_view.cpp @@ -1,3 +1,4 @@ +#include #include "rr_graph_view.h" #include "rr_node.h" #include "physical_types.h" @@ -9,7 +10,9 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, const vtr::vector& rr_indexed_data, const std::vector& rr_rc_data, const vtr::vector& rr_segments, - const vtr::vector& rr_switch_inf) + const vtr::vector& rr_switch_inf, + const vtr::vector>& node_in_edges, + const vtr::vector>& node_ptc_nums) : node_storage_(node_storage) , node_lookup_(node_lookup) , rr_node_metadata_(rr_node_metadata) @@ -17,5 +20,117 @@ RRGraphView::RRGraphView(const t_rr_graph_storage& node_storage, , rr_indexed_data_(rr_indexed_data) , rr_rc_data_(rr_rc_data) , rr_segments_(rr_segments) - , rr_switch_inf_(rr_switch_inf) { + , rr_switch_inf_(rr_switch_inf) + , node_in_edges_(node_in_edges) + , node_ptc_nums_(node_ptc_nums) { } + +std::vector RRGraphView::node_in_edges(RRNodeId node) const { + VTR_ASSERT(size_t(node) < node_storage_.size()); + if (node_in_edges_.empty()) { + return std::vector(); + } + return node_in_edges_[node]; +} + +std::vector RRGraphView::node_configurable_in_edges(RRNodeId node) const { + /* Note: This is not efficient in runtime, should sort edges by configurability when allocating the array! */ + VTR_ASSERT(size_t(node) < node_storage_.size()); + std::vector ret_edges; + if (node_in_edges_.empty()) { + return ret_edges; + } + for (const RREdgeId& edge : node_in_edges_[node]) { + if (rr_switch_inf_[edge_switch(edge)].configurable()) { + ret_edges.push_back(edge); + } + } + return ret_edges; +} + +std::vector RRGraphView::node_non_configurable_in_edges(RRNodeId node) const { + /* Note: This is not efficient in runtime, should sort edges by configurability when allocating the array! */ + VTR_ASSERT(size_t(node) < node_storage_.size()); + std::vector ret_edges; + if (node_in_edges_.empty()) { + return ret_edges; + } + for (const RREdgeId& edge : node_in_edges_[node]) { + if (!rr_switch_inf_[edge_switch(edge)].configurable()) { + ret_edges.push_back(edge); + } + } + return ret_edges; +} + +std::vector RRGraphView::find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const { + std::vector edge_list; + for (auto iedge : node_out_edges(src_node)) { + if (edge_sink_node(RREdgeId(iedge)) == des_node) { + edge_list.push_back(RREdgeId(iedge)); + } + } + return edge_list; +} + +RRSegmentId RRGraphView::node_segment(RRNodeId node) const { + RRIndexedDataId cost_index = node_cost_index(node); + return RRSegmentId(rr_indexed_data_[cost_index].seg_index); +} + +size_t RRGraphView::in_edges_count() const { + size_t edge_count = 0; + for (auto edge_list : node_in_edges_) { + edge_count += edge_list.size(); + } + return edge_count; +} + +bool RRGraphView::validate_in_edges() const { + size_t num_err = 0; + /* For each edge, validate that + * - The source node is in the fan-in edge list of the destination node + * - The sink node is in the fan-out edge list of the source node + */ + for (RRNodeId curr_node : vtr::StrongIdRange(RRNodeId(0), RRNodeId(node_storage_.size()))) { + /* curr_node ---> des_node + * <-?- check if the incoming edge is correct or not + */ + for (auto iedge : node_storage_.edges(curr_node)) { + RRNodeId des_node = node_storage_.edge_sink_node(node_storage_.edge_id(curr_node, iedge)); + std::vector des_fanin_nodes; + for (auto next_edge : node_in_edges(des_node)) { + RRNodeId prev_edge_des_node = node_storage_.edge_source_node(next_edge); + des_fanin_nodes.push_back(prev_edge_des_node); + } + if (des_fanin_nodes.end() == std::find(des_fanin_nodes.begin(), des_fanin_nodes.end(), curr_node)) { + VTR_LOG_ERROR("Node '%s' does not appear in the fan-in edges of Node '%s', while does drive it in its fan-out list\n", + node_coordinate_to_string(curr_node).c_str(), node_coordinate_to_string(des_node).c_str()); + num_err++; + } + } + /* src_node -?-> curr_node + * <--- check if the fan-out edge is correct or not + */ + for (auto iedge : node_in_edges(curr_node)) { + RRNodeId src_node = node_storage_.edge_source_node(iedge); + std::vector src_fanout_nodes; + for (auto prev_edge : node_storage_.edges(src_node)) { + RRNodeId prev_edge_des_node = node_storage_.edge_sink_node(node_storage_.edge_id(src_node, prev_edge)); + src_fanout_nodes.push_back(prev_edge_des_node); + } + if (src_fanout_nodes.end() == std::find(src_fanout_nodes.begin(), src_fanout_nodes.end(), curr_node)) { + VTR_LOG_ERROR("Node '%s' does not appear in the fan-out edges of Node '%s', while does exist in its fan-in list\n", + node_coordinate_to_string(curr_node).c_str(), node_coordinate_to_string(src_node).c_str()); + num_err++; + } + } + } + if (num_err) { + VTR_LOG_ERROR("Found %ld errors when validating incoming edges for routing resource graph\n", num_err); + return false; + } + return true; +} + + diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index d0fffc04307..f28a5883cbe 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -47,6 +47,11 @@ * - Timing analyzer * - GUI * + * Note that each client of rr_graph may get a frame view of the object + * The RRGraphView is the complete frame view of the routing resource graph + * - This helps to reduce the memory footprint for each client + * - This avoids massive changes for each client on using the APIs + * as each frame view provides adhoc APIs for each client * \internal * TODO: More compact frame views will be created, such as: * - A mini frame view: Contains only nodes and edges, representing the @@ -70,19 +75,21 @@ class RRGraphView { const vtr::vector& rr_indexed_data, const std::vector& rr_rc_data, const vtr::vector& rr_segments, - const vtr::vector& rr_switch_inf); + const vtr::vector& rr_switch_inf, + const vtr::vector>& node_in_edges, + const vtr::vector>& node_ptc_nums); /* Disable copy constructors and copy assignment operator - * This is to avoid accidental copy because it could be an expensive operation considering that the + * This is to avoid accidental copy because it could be an expensive operation considering that the * memory footprint of the data structure could ~ Gb - * Using the following syntax, we prohibit accidental 'pass-by-value' which can be immediately caught + * Using the following syntax, we prohibit accidental 'pass-by-value' which can be immediately caught * by compiler */ RRGraphView(const RRGraphView&) = delete; void operator=(const RRGraphView&) = delete; /* -- Accessors -- */ - /* TODO: The accessors may be turned into private later if they are replacable by 'questionin' + /* TODO: The accessors may be turned into private later if they are replacable by 'questionin' * kind of accessors */ public: @@ -221,10 +228,16 @@ class RRGraphView { inline short node_layer(RRNodeId node) const { return node_storage_.node_layer(node); } - - /** @brief Return the ptc number twist of a specified node. - */ - inline short node_ptc_twist(RRNodeId node) const { + + inline short node_bend_start(RRNodeId node) const { + return node_storage_.node_bend_start(node); + } + inline short node_bend_end(RRNodeId node) const { + return node_storage_.node_bend_end(node); + } + + /** @brief Get the ptc number twist of a routing resource node. This function is inlined for runtime optimization. */ + inline short node_ptc_twist(RRNodeId node) const{ return node_storage_.node_ptc_twist(node); } @@ -283,7 +296,6 @@ class RRGraphView { * @note To return true, the RRNode must be completely contained within the specified bounding box, * with the edges of the bounding box being inclusive. */ - inline bool node_is_inside_bounding_box(RRNodeId node, vtr::Rect bounding_box) const { return (node_xhigh(node) <= bounding_box.xmax() && node_xlow(node) >= bounding_box.xmin() @@ -413,8 +425,12 @@ class RRGraphView { return node_storage_.edge_switch(id, iedge); } - /** @brief Return the source node for the specified edge. - */ + inline RRSwitchId edge_switch(RREdgeId edge) const { + return RRSwitchId(node_storage_.edge_switch(edge)); + } + /** @brief Get the source node for the iedge'th edge from specified RRNodeId. + * This method should generally not be used, and instead first_edge and + * last_edge should be used.*/ inline RRNodeId edge_src_node(const RREdgeId edge_id) const { return node_storage_.edge_src_node(edge_id); } @@ -428,6 +444,16 @@ class RRGraphView { inline RRNodeId edge_sink_node(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_sink_node(id, iedge); } + inline RRNodeId edge_sink_node(RREdgeId edge) const { + return node_storage_.edge_sink_node(edge); + } + + /** @brief Get the source node for the iedge'th edge from specified RRNodeId. + * This method should generally not be used, and instead first_edge and + * last_edge should be used.*/ + inline RRNodeId edge_source_node(RRNodeId id, t_edge_size iedge) const { + return node_storage_.edge_source_node(id, iedge); + } /** @brief Check if the edge is a configurable edge * @note A configurable edge represents a programmable switch between routing resources, which could be @@ -438,6 +464,9 @@ class RRGraphView { inline bool edge_is_configurable(RRNodeId id, t_edge_size iedge) const { return node_storage_.edge_is_configurable(id, iedge, rr_switch_inf_); } + inline bool edge_is_configurable(RREdgeId edge) const { + return node_storage_.edge_is_configurable(edge, rr_switch_inf_); + } /** @brief Return the number of configurable edges. */ @@ -451,11 +480,18 @@ class RRGraphView { return node_storage_.num_non_configurable_edges(node, rr_switch_inf_); } - /** @brief Return ID range for configurable edges. - */ + + /** @brief A configurable edge represents a programmable switch between routing resources, which could be + * a multiplexer + * a tri-state buffer + * a pass gate + * This API gets ID range for configurable edges. This function is inlined for runtime optimization. */ inline edge_idx_range configurable_edges(RRNodeId node) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(node_storage_.num_edges(node) - num_non_configurable_edges(node))); } + inline edge_idx_range node_configurable_out_edges(RRNodeId node) const { + return configurable_edges(node); + } /** @brief Return ID range for non-configurable edges. * @note A non-configurable edge represents a hard-wired connection between routing resources, which could be @@ -465,6 +501,9 @@ class RRGraphView { inline edge_idx_range non_configurable_edges(RRNodeId node) const { return vtr::make_range(edge_idx_iterator(node_storage_.num_edges(node) - num_non_configurable_edges(node)), edge_idx_iterator(num_edges(node))); } + inline edge_idx_range node_non_configurable_out_edges(RRNodeId node) const { + return non_configurable_edges(node); + } /** * @brief Retrieve the outgoing edges for a specified node. This API is designed to facilitate range-based loops for traversing the outgoing edges of a node. @@ -480,6 +519,12 @@ class RRGraphView { inline edge_idx_range edges(const RRNodeId& id) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); } + inline edge_idx_range node_out_edges(const RRNodeId& id) const { + return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); + } + + /** @brief find the edges between two nodes */ + std::vector find_edges(const RRNodeId& src_node, const RRNodeId& des_node) const; /** @brief Return the number of edges. */ @@ -530,6 +575,16 @@ class RRGraphView { return node_storage_.node_cost_index(node); } + /** @brief Get the segment id which a routing resource node represents. Only applicable to nodes whose type is CHANX or CHANY */ + RRSegmentId node_segment(RRNodeId node) const; + + /** @brief Return incoming edges for a given routing resource node + * Require build_in_edges() to be called first + */ + std::vector node_in_edges(RRNodeId node) const; + std::vector node_configurable_in_edges(RRNodeId node) const; + std::vector node_non_configurable_in_edges(RRNodeId node) const; + /** @brief Return detailed routing segment information of a specified segment * @note The routing segments here may not be exactly same as those defined in architecture file. They have been * adapted to fit the context of routing resource graphs. @@ -604,6 +659,21 @@ class RRGraphView { return node_storage_.validate_node(node_id, rr_switch_inf_); } + /** @brief Check if the node id is a valid one in storage */ + inline bool valid_node(RRNodeId node_id) const { + return size_t(node_id) < node_storage_.size(); + } + + /** @brief Check if the switch is a valid one in storage */ + inline bool valid_switch(RRSwitchId switch_id) const { + return (size_t(switch_id) < rr_switch_inf_.size()); + } + + /** @brief Validate if all the fan-in edge lists are valid */ + bool validate_in_edges() const; + /** @brief Count the number of incoming edges for all the nodes */ + size_t in_edges_count() const; + /* -- Internal data storage -- */ /* Note: only read-only object or data structures are allowed!!! */ private: @@ -645,6 +715,13 @@ class RRGraphView { const vtr::vector& rr_segments_; /// switch info for rr nodes const vtr::vector& rr_switch_inf_; + + /** A list of incoming edges for each routing resource node. This can be built optionally, as required by applications. + * By default, it is empty! Call build_in_edges() to construct it!!! */ + const vtr::vector>& node_in_edges_; + + /** A list of extra ptc numbers for each routing resource node. See details in RRGraphBuilder class */ + const vtr::vector>& node_ptc_nums_; }; #endif diff --git a/libs/librrgraph/src/base/rr_node_types.h b/libs/librrgraph/src/base/rr_node_types.h index 32cf5a71629..383f79d8024 100644 --- a/libs/librrgraph/src/base/rr_node_types.h +++ b/libs/librrgraph/src/base/rr_node_types.h @@ -28,11 +28,12 @@ typedef enum e_rr_type : unsigned char { OPIN, ///Output pin of a block CHANX, ///x-directed routing wire, or an x-directed segment of a channel for global routing CHANY, ///y-directed routing wire, or a y-directed segment of a channel for global routing + MEDIUM, NUM_RR_TYPES } t_rr_type; -constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; -constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; +constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY, MEDIUM}}; +constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY", "MEDIUM"}}; /* * Direction::INC: wire driver is positioned at the low-coordinate end of the wire. diff --git a/libs/librrgraph/src/base/rr_spatial_lookup.cpp b/libs/librrgraph/src/base/rr_spatial_lookup.cpp index 6cc8102f502..fb1780e72ce 100644 --- a/libs/librrgraph/src/base/rr_spatial_lookup.cpp +++ b/libs/librrgraph/src/base/rr_spatial_lookup.cpp @@ -1,4 +1,5 @@ #include "vtr_assert.h" +#include "vtr_log.h" #include "rr_spatial_lookup.h" RRSpatialLookup::RRSpatialLookup() { @@ -215,16 +216,16 @@ std::vector RRSpatialLookup::find_grid_nodes_at_all_sides(int layer, int x, int y, t_rr_type rr_type) const { - VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK); - if (rr_type == SOURCE || rr_type == SINK) { - return find_nodes(layer,x, y, rr_type); + VTR_ASSERT(rr_type == SOURCE || rr_type == OPIN || rr_type == IPIN || rr_type == SINK || rr_type == MEDIUM); + if (rr_type == SOURCE || rr_type == SINK || rr_type == MEDIUM) { + return find_nodes(layer, x, y, rr_type); } std::vector nodes; /* Reserve space to avoid memory fragmentation */ size_t num_nodes = 0; for (e_side node_side : TOTAL_2D_SIDES) { - num_nodes += find_nodes(layer,x, y, rr_type, node_side).size(); + num_nodes += find_nodes(layer, x, y, rr_type, node_side).size(); } nodes.reserve(num_nodes); @@ -315,7 +316,7 @@ void RRSpatialLookup::mirror_nodes(const int layer, const vtr::Point& des_coord, t_rr_type type, e_side side) { - VTR_ASSERT(SOURCE == type); + VTR_ASSERT(SOURCE == type || SINK == type); resize_nodes(layer, des_coord.x(), des_coord.y(), type, side); rr_node_indices_[type][layer][des_coord.x()][des_coord.y()][side] = rr_node_indices_[type][layer][src_coord.x()][src_coord.y()][side]; } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index 9687e819805..6b65633e771 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -88,7 +88,7 @@ template inline void load_grid_locs(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); template inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); -inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * ptc, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error); +inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error); template inline void load_node_timing(const pugi::xml_node &root, T &out, Context &context, const std::function *report_error, ptrdiff_t *offset_debug); inline void load_node_timing_required_attributes(const pugi::xml_node &root, float * C, float * R, const std::function * report_error); @@ -1625,7 +1625,7 @@ template constexpr const char *lookup_switch_type[] = {"UXSD_INVALID", "mux", "tristate", "pass_gate", "short", "buffer"}; constexpr const char *lookup_segment_res_type[] = {"UXSD_INVALID", "GENERAL", "GCLK"}; constexpr const char *lookup_pin_type[] = {"UXSD_INVALID", "OPEN", "OUTPUT", "INPUT"}; -constexpr const char *lookup_node_type[] = {"UXSD_INVALID", "CHANX", "CHANY", "SOURCE", "SINK", "OPIN", "IPIN"}; +constexpr const char *lookup_node_type[] = {"UXSD_INVALID", "CHANX", "CHANY", "SOURCE", "SINK", "OPIN", "IPIN", "MEDIUM"}; constexpr const char *lookup_node_direction[] = {"UXSD_INVALID", "INC_DIR", "DEC_DIR", "BI_DIR", "NONE"}; constexpr const char *lookup_node_clk_res_type[] = {"UXSD_INVALID", "VIRTUAL_SINK"}; constexpr const char *lookup_loc_side[] = {"UXSD_INVALID", "LEFT", "RIGHT", "TOP", "BOTTOM", "RIGHT_LEFT", "RIGHT_BOTTOM", "RIGHT_BOTTOM_LEFT", "TOP_RIGHT", "TOP_BOTTOM", "TOP_LEFT", "TOP_RIGHT_BOTTOM", "TOP_RIGHT_LEFT", "TOP_BOTTOM_LEFT", "TOP_RIGHT_BOTTOM_LEFT", "BOTTOM_LEFT"}; @@ -2474,7 +2474,7 @@ inline void load_grid_loc_required_attributes(const pugi::xml_node &root, int * if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_grid_loc, report_error); } -inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * ptc, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error){ +inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * xhigh, int * xlow, int * yhigh, int * ylow, const std::function * report_error){ std::bitset<8> astate = 0; for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ atok_t_node_loc in = lex_attr_t_node_loc(attr.name(), report_error); @@ -2485,7 +2485,7 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * /* Attribute layer set after element init */ break; case atok_t_node_loc::PTC: - *ptc = load_int(attr.value(), report_error); + /* Attribute ptc set after element init */ break; case atok_t_node_loc::SIDE: /* Attribute side set after element init */ @@ -3427,7 +3427,7 @@ inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context, out.set_node_loc_layer(load_int(attr.value(), report_error), context); break; case atok_t_node_loc::PTC: - /* Attribute ptc is already set */ + out.set_node_loc_ptc(attr.value(), context); break; case atok_t_node_loc::SIDE: out.set_node_loc_side(lex_enum_loc_side(attr.value(), true, report_error), context); @@ -3616,8 +3616,6 @@ inline void load_node(const pugi::xml_node &root, T &out, Context &context, cons switch(in){ case gtok_t_node::LOC: { - int node_loc_ptc; - memset(&node_loc_ptc, 0, sizeof(node_loc_ptc)); int node_loc_xhigh; memset(&node_loc_xhigh, 0, sizeof(node_loc_xhigh)); int node_loc_xlow; @@ -3626,8 +3624,8 @@ inline void load_node(const pugi::xml_node &root, T &out, Context &context, cons memset(&node_loc_yhigh, 0, sizeof(node_loc_yhigh)); int node_loc_ylow; memset(&node_loc_ylow, 0, sizeof(node_loc_ylow)); - load_node_loc_required_attributes(node, &node_loc_ptc, &node_loc_xhigh, &node_loc_xlow, &node_loc_yhigh, &node_loc_ylow, report_error); - auto child_context = out.init_node_loc(context, node_loc_ptc, node_loc_xhigh, node_loc_xlow, node_loc_yhigh, node_loc_ylow); + load_node_loc_required_attributes(node, &node_loc_xhigh, &node_loc_xlow, &node_loc_yhigh, &node_loc_ylow, report_error); + auto child_context = out.init_node_loc(context, node_loc_xhigh, node_loc_xlow, node_loc_yhigh, node_loc_ylow); load_node_loc(node, out, child_context, report_error, offset_debug); out.finish_node_loc(child_context); } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h index 7cfea1aa19b..29ab05eb209 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h @@ -763,6 +763,7 @@ inline void load_node_loc_capnp_type(const ucap::NodeLoc::Reader &root, T &out, (void)stack; out.set_node_loc_layer(root.getLayer(), context); + out.set_node_loc_ptc(root.getPtc().cStr(), context); out.set_node_loc_side(conv_enum_loc_side(root.getSide(), report_error), context); out.set_node_loc_twist(root.getTwist(), context); } @@ -837,7 +838,7 @@ inline void load_node_capnp_type(const ucap::Node::Reader &root, T &out, Context stack->push_back(std::make_pair("getLoc", 0)); if (root.hasLoc()) { auto child_el = root.getLoc(); - auto child_context = out.init_node_loc(context, child_el.getPtc(), child_el.getXhigh(), child_el.getXlow(), child_el.getYhigh(), child_el.getYlow()); + auto child_context = out.init_node_loc(context, child_el.getXhigh(), child_el.getXlow(), child_el.getYhigh(), child_el.getYlow()); load_node_loc_capnp_type(child_el, out, child_context, report_error, stack); out.finish_node_loc(child_context); } diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index 9dbac04ef7f..211b3d5733b 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -28,7 +28,7 @@ enum class enum_segment_res_type {UXSD_INVALID = 0, GENERAL, GCLK}; enum class enum_pin_type {UXSD_INVALID = 0, OPEN, OUTPUT, INPUT}; -enum class enum_node_type {UXSD_INVALID = 0, CHANX, CHANY, SOURCE, SINK, OPIN, IPIN}; +enum class enum_node_type {UXSD_INVALID = 0, CHANX, CHANY, SOURCE, SINK, OPIN, IPIN, MEDIUM}; enum class enum_node_direction {UXSD_INVALID = 0, INC_DIR, DEC_DIR, BI_DIR, NONE}; @@ -378,13 +378,14 @@ class RrGraphBase { * * * - * + * * * */ virtual inline int get_node_loc_layer(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline void set_node_loc_layer(int layer, typename ContextTypes::NodeLocWriteContext &ctx) = 0; - virtual inline int get_node_loc_ptc(typename ContextTypes::NodeLocReadContext &ctx) = 0; + virtual inline const char * get_node_loc_ptc(typename ContextTypes::NodeLocReadContext &ctx) = 0; + virtual inline void set_node_loc_ptc(const char * ptc, typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline enum_loc_side get_node_loc_side(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline void set_node_loc_side(enum_loc_side side, typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline int get_node_loc_twist(typename ContextTypes::NodeLocReadContext &ctx) = 0; @@ -462,7 +463,7 @@ class RrGraphBase { virtual inline const char * get_node_name(typename ContextTypes::NodeReadContext &ctx) = 0; virtual inline void set_node_name(const char * name, typename ContextTypes::NodeWriteContext &ctx) = 0; virtual inline enum_node_type get_node_type(typename ContextTypes::NodeReadContext &ctx) = 0; - virtual inline typename ContextTypes::NodeLocWriteContext init_node_loc(typename ContextTypes::NodeWriteContext &ctx, int ptc, int xhigh, int xlow, int yhigh, int ylow) = 0; + virtual inline typename ContextTypes::NodeLocWriteContext init_node_loc(typename ContextTypes::NodeWriteContext &ctx, int xhigh, int xlow, int yhigh, int ylow) = 0; virtual inline void finish_node_loc(typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline typename ContextTypes::NodeLocReadContext get_node_loc(typename ContextTypes::NodeReadContext &ctx) = 0; virtual inline typename ContextTypes::NodeTimingWriteContext init_node_timing(typename ContextTypes::NodeWriteContext &ctx, float C, float R) = 0; diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index dfb63641cbb..8894d96fab2 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -233,6 +233,7 @@ + @@ -281,7 +282,7 @@ - + diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index e9e83988d0b..cebd33c9aa0 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -687,27 +687,33 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { * * * - * + * * */ - inline int init_node_loc(int& inode, int ptc, int xhigh, int xlow, int yhigh, int ylow) final { + inline int init_node_loc(int& inode, int xhigh, int xlow, int yhigh, int ylow) final { auto node = (*rr_nodes_)[inode]; RRNodeId node_id = node.id(); rr_graph_builder_->set_node_coordinates(node_id, xlow, ylow, xhigh, yhigh); // We set the layer num 0 - If it is specified in the XML, it will be overwritten rr_graph_builder_->set_node_layer(node_id, 0); - rr_graph_builder_->set_node_ptc_num(node_id, ptc); + return inode; } inline void finish_node_loc(int& /*inode*/) final {} inline const t_rr_node get_node_loc(const t_rr_node& node) final { return node; } + inline void set_node_loc_ptc(const char* ptc, int& inode) final { + auto node = (*rr_nodes_)[inode]; + RRNodeId node_id = node.id(); + return rr_graph_builder_->set_node_ptc_nums(node_id, std::string(ptc)); + } - inline int get_node_loc_ptc(const t_rr_node& node) final { - return rr_graph_->node_ptc_num(node.id()); + inline const char* get_node_loc_ptc(const t_rr_node& node) final { + temp_string_ = rr_graph_builder_->node_ptc_nums_to_string(node.id()); + return temp_string_.c_str(); } inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); @@ -874,6 +880,7 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { */ inline void preallocate_rr_nodes_node(void*& /*ctx*/, size_t size) final { rr_graph_builder_->reserve_nodes(size); + rr_graph_builder_->resize_node_ptc_nums(size); } inline int add_rr_nodes_node(void*& /*ctx*/, unsigned int capacity, unsigned int id, uxsd::enum_node_type type) final { // make_room_in_vector will not allocate if preallocate_rr_nodes_node @@ -1830,10 +1837,12 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { read_rr_graph_filename_->assign(read_rr_graph_name_); if (do_check_rr_graph_) { + const VibDeviceGrid vib_grid_; check_rr_graph(*rr_graph_, physical_tile_types_, *rr_indexed_data_, grid_, + vib_grid_, *chan_width_, graph_type_, is_flat_); @@ -1858,7 +1867,14 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { /* Add the correct node into the vector */ for (size_t inode = 0; inode < rr_nodes_->size(); inode++) { auto node = (*rr_nodes_)[inode]; - rr_graph_builder.add_node_to_all_locs(node.id()); + /* Set track numbers as a node may have multiple ptc */ + if (rr_graph_builder.node_contain_multiple_ptc(node.id())) { + if (CHANX == rr_graph_->node_type(node.id()) || CHANY == rr_graph_->node_type(node.id())) { + rr_graph_builder.add_track_node_to_lookup(node.id()); + } + } else { + rr_graph_builder.add_node_to_all_locs(node.id()); + } } } @@ -2018,6 +2034,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return OPIN; case uxsd::enum_node_type::IPIN: return IPIN; + case uxsd::enum_node_type::MEDIUM: + return MEDIUM; default: report_error( "Invalid node type %d", @@ -2038,6 +2056,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { return uxsd::enum_node_type::OPIN; case IPIN: return uxsd::enum_node_type::IPIN; + case MEDIUM: + return uxsd::enum_node_type::MEDIUM; default: report_error( "Invalid type %d", type); diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 1cfdba42f92..fb0cbad32ab 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -350,6 +350,7 @@ static void load_rr_indexed_data_base_costs(const RRGraphView& rr_graph, rr_indexed_data[RRIndexedDataId(SOURCE_COST_INDEX)].base_cost = delay_normalization_fac; rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost = 0.; + rr_indexed_data[RRIndexedDataId(MEDIUM_COST_INDEX)].base_cost = delay_normalization_fac; rr_indexed_data[RRIndexedDataId(OPIN_COST_INDEX)].base_cost = delay_normalization_fac; // The IPIN_COST_INDEX base cost is changed from 0.95 to 0.875 so it is perfectly representable in binary format (this change is made for SPEC benchmark). // This number is perfectly representable in a binary mantissa (without round-off) so we can get the same routing result on different platforms. diff --git a/libs/librrgraph/src/utils/describe_rr_node.cpp b/libs/librrgraph/src/utils/describe_rr_node.cpp index 6383e3489cc..fb1f1a0c172 100644 --- a/libs/librrgraph/src/utils/describe_rr_node.cpp +++ b/libs/librrgraph/src/utils/describe_rr_node.cpp @@ -36,6 +36,11 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += vtr::string_fmt(" pin: %d pin_name: %s", rr_graph.node_pin_num(inode), pin_name.c_str()); + } else if (rr_graph.node_type(inode) == MEDIUM) { + auto index = rr_graph.node_ptc_num(inode); + + msg += vtr::string_fmt(" medium index: %d", + index); } else { VTR_ASSERT(rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK); @@ -49,4 +54,4 @@ std::string describe_rr_node(const RRGraphView& rr_graph, msg += " " + rr_graph.node_coordinate_to_string(inode); return msg; -} \ No newline at end of file +} diff --git a/libs/librrgraph/src/utils/vtr_tokenizer.cpp b/libs/librrgraph/src/utils/vtr_tokenizer.cpp new file mode 100644 index 00000000000..1dc34270b15 --- /dev/null +++ b/libs/librrgraph/src/utils/vtr_tokenizer.cpp @@ -0,0 +1,167 @@ +/************************************************************************ + * Member functions for StringToken class + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_tokenizer.h" +#include "vtr_assert.h" + +/* namespace openfpga begins */ +namespace vtr { + +/************************************************************************ + * Constructors + ***********************************************************************/ +StringToken::StringToken(const std::string& data) { set_data(data); } + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +/* Get the data string */ +std::string StringToken::data() const { return data_; } + +/* Split the string using a given delim */ +std::vector StringToken::split(const std::string& delims) const { + /* Return vector */ + std::vector ret; + + /* Get a writable char array */ + char* tmp = new char[data_.size() + 1]; + std::copy(data_.begin(), data_.end(), tmp); + tmp[data_.size()] = '\0'; + /* Split using strtok */ + char* result = std::strtok(tmp, delims.c_str()); + while (NULL != result) { + std::string result_str(result); + /* Store the token */ + ret.push_back(result_str); + /* Got to next */ + result = std::strtok(NULL, delims.c_str()); + } + + /* Free the tmp */ + delete[] tmp; + + return ret; +} + +/* Split the string using a given delim */ +std::vector StringToken::split(const char& delim) const { + /* Create delims */ + std::string delims(1, delim); + + return split(delims); +} + +/* Split the string using a given delim */ +std::vector StringToken::split(const char* delim) const { + /* Create delims */ + std::string delims(delim); + + return split(delims); +} + +/* Split the string using a given delim */ +std::vector StringToken::split( + const std::vector& delims) const { + /* Create delims */ + std::string delims_str; + for (const auto& delim : delims) { + delims_str.push_back(delim); + } + + return split(delims_str); +} + +/* Split the string */ +std::vector StringToken::split() { + /* Add a default delim */ + if (true == delims_.empty()) { + add_default_delim(); + } + /* Create delims */ + std::string delims; + for (const auto& delim : delims_) { + delims.push_back(delim); + } + + return split(delims); +} + +std::vector StringToken::find_positions(const char& delim) const { + std::vector anchors; + size_t found = data_.find(delim); + while (std::string::npos != found) { + anchors.push_back(found); + found = data_.find(delim, found + 1); + } + return anchors; +} + +std::vector StringToken::split_by_chunks( + const char& chunk_delim, const bool& split_odd_chunk) const { + size_t chunk_idx_mod = 0; + if (split_odd_chunk) { + chunk_idx_mod = 1; + } + std::vector tokens; + /* There are pairs of quotes, identify the chunk which should be split*/ + std::vector token_chunks = split(chunk_delim); + for (size_t ichunk = 0; ichunk < token_chunks.size(); ichunk++) { + /* Chunk with even index (including the first) is always out of two quote -> + * Split! Chunk with odd index is always between two quotes -> Do not split! + */ + if (ichunk % 2 == chunk_idx_mod) { + StringToken chunk_tokenizer(token_chunks[ichunk]); + for (std::string curr_token : chunk_tokenizer.split()) { + tokens.push_back(curr_token); + } + } else { + tokens.push_back(token_chunks[ichunk]); + } + } + return tokens; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void StringToken::set_data(const std::string& data) { + data_ = data; + return; +} + +/* Add a delima to the list */ +void StringToken::add_delim(const char& delim) { delims_.push_back(delim); } + +/* Remove the string repeated at the beginning of string */ +void StringToken::ltrim(const std::string& sensitive_word) { + size_t start = data_.find_first_not_of(sensitive_word); + data_ = (start == std::string::npos) ? "" : data_.substr(start); + return; +} + +/* Remove the string repeated at the end of string */ +void StringToken::rtrim(const std::string& sensitive_word) { + size_t end = data_.find_last_not_of(sensitive_word); + data_ = (end == std::string::npos) ? "" : data_.substr(0, end + 1); + return; +} + +void StringToken::trim() { + rtrim(" "); + ltrim(" "); + return; +} + +/************************************************************************ + * Internal Mutators + ***********************************************************************/ +void StringToken::add_default_delim() { + VTR_ASSERT_SAFE(true == delims_.empty()); + delims_.push_back(' '); + return; +} + +} // namespace openfpga diff --git a/libs/librrgraph/src/utils/vtr_tokenizer.h b/libs/librrgraph/src/utils/vtr_tokenizer.h new file mode 100644 index 00000000000..2c70906413f --- /dev/null +++ b/libs/librrgraph/src/utils/vtr_tokenizer.h @@ -0,0 +1,70 @@ +#ifndef VTR_TOKENIZER_H +#define VTR_TOKENIZER_H + +/******************************************************************** + * Include header files that are required by data structure declaration + *******************************************************************/ +#include +#include + +/* namespace openfpga begins */ +namespace vtr { + +/************************************************************************ + * This file includes a tokenizer for string objects + * It splits a string with given delima and return a vector of tokens + * It can accept different delima in splitting strings + ***********************************************************************/ + +class StringToken { + public: /* Constructors*/ + StringToken(const std::string& data); + + public: /* Public Accessors */ + std::string data() const; + std::vector split(const std::string& delims) const; + std::vector split(const char& delim) const; + std::vector split(const char* delim) const; + std::vector split(const std::vector& delim) const; + std::vector split(); + /** @brief Find the position (i-th charactor) in a string for a given + * delimiter, it will return a list of positions For example, to find the + * position of all quotes (") in a string: "we" are good The following code is + * suggested: StringToken tokenizer("\"we\" are good"); std::vector + * anchors = tokenizer.find_positions('\"') The following vector will be + * returned: [0, 3] */ + std::vector find_positions(const char& delim) const; + /** @brief split the string for each chunk. This is useful where there are + * chunks of substring should not be splitted by the given delimiter For + * example, to split the string with quotes (") in a string: source "cmdA + * --opt1 val1;cmdB --opt2 val2" --verbose where the string between the two + * quotes should not be splitted The following code is suggested: StringToken + * tokenizer("source \"cmdA --opt1 val1;cmdB --opt2 val2\" --verbose"); + * std::vector tokenizer.split_by_chunks('\"', true); + * The following vector will be returned: + * ["source" "cmdA --opt1 val1;cmdB --opt2 val2" "--verbose"] + * + * .. note:: The option ``split_odd_chunk`` is useful when the chunk delimiter + * appears at the beginning of the string. + */ + std::vector split_by_chunks( + const char& chunk_delim, const bool& split_odd_chunk = false) const; + + public: /* Public Mutators */ + void set_data(const std::string& data); + void add_delim(const char& delim); + void ltrim(const std::string& sensitive_word); + void rtrim(const std::string& sensitive_word); + void trim(); + + private: /* Private Mutators */ + void add_default_delim(); + + private: /* Internal data */ + std::string data_; /* Lines to be splited */ + std::vector delims_; +}; + +} // namespace openfpga + +#endif diff --git a/libs/libvtrcapnproto/CMakeLists.txt b/libs/libvtrcapnproto/CMakeLists.txt index cd97b0ec4f1..0f66a10856a 100644 --- a/libs/libvtrcapnproto/CMakeLists.txt +++ b/libs/libvtrcapnproto/CMakeLists.txt @@ -32,7 +32,7 @@ capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS ) if (VPR_ENABLE_INTERCHANGE) - set(IC_DIR ${CMAKE_SOURCE_DIR}/libs/EXTERNAL/libinterchange/interchange) + set(IC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../EXTERNAL/libinterchange/interchange) set(CAPNPC_SRC_PREFIX ${IC_DIR}) find_program(WGET wget REQUIRED) diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index d78d2dd2b3d..1a044dfa116 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -178,7 +178,7 @@ struct GridLocs { struct NodeLoc { layer @0 :Int32 = 0; - ptc @1 :Int32; + ptc @1 :Text; side @2 :LocSide; twist @3 :Int32; xhigh @4 :Int32; diff --git a/libs/libvtrutil/CMakeLists.txt b/libs/libvtrutil/CMakeLists.txt index 0362295ef1c..e35d0246b8b 100644 --- a/libs/libvtrutil/CMakeLists.txt +++ b/libs/libvtrutil/CMakeLists.txt @@ -61,24 +61,28 @@ endif() # 2) The custom command depends on the touched version input file and generates the processed # version file, with updated values. The custom command uses the configure_version.cmake # script to generate the up-to-date vtr_version.cpp -add_custom_target(version ALL - COMMAND ${CMAKE_COMMAND} -E touch ${VTR_VERSION_FILE_IN}) - -add_custom_command(OUTPUT ${VTR_VERSION_FILE_OUT} - COMMAND ${CMAKE_COMMAND} - -D IN_FILE=${VTR_VERSION_FILE_IN} - -D OUT_FILE=${VTR_VERSION_FILE_OUT} - -D VTR_VERSION_MAJOR=${VTR_VERSION_MAJOR} - -D VTR_VERSION_MINOR=${VTR_VERSION_MINOR} - -D VTR_VERSION_PATCH=${VTR_VERSION_PATCH} - -D VTR_VERSION_PRERELEASE=${VTR_VERSION_PRERELEASE} - -D VTR_COMPILER_INFO=${VTR_COMPILER_INFO} - -D VTR_BUILD_INFO=${VTR_BUILD_INFO} - -P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules/configure_version.cmake - MAIN_DEPENDENCY ${VTR_VERSION_FILE_IN} - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - VERBATIM) - +if (VTR_ENABLE_VERSION) + add_custom_target(version ALL + COMMAND ${CMAKE_COMMAND} -E touch ${VTR_VERSION_FILE_IN}) + + add_custom_command(OUTPUT ${VTR_VERSION_FILE_OUT} + COMMAND ${CMAKE_COMMAND} + -D IN_FILE=${VTR_VERSION_FILE_IN} + -D OUT_FILE=${VTR_VERSION_FILE_OUT} + -D VTR_VERSION_MAJOR=${VTR_VERSION_MAJOR} + -D VTR_VERSION_MINOR=${VTR_VERSION_MINOR} + -D VTR_VERSION_PATCH=${VTR_VERSION_PATCH} + -D VTR_VERSION_PRERELEASE=${VTR_VERSION_PRERELEASE} + -D VTR_COMPILER_INFO=${VTR_COMPILER_INFO} + -D VTR_BUILD_INFO=${VTR_BUILD_INFO} + -P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules/configure_version.cmake + MAIN_DEPENDENCY ${VTR_VERSION_FILE_IN} + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + VERBATIM) +else() +# Just copy the input file to output file with version number + configure_file(${VTR_VERSION_FILE_IN} ${VTR_VERSION_FILE_OUT}) +endif() # # Source files and library @@ -98,7 +102,9 @@ target_include_directories(libvtrutil PUBLIC ${LIB_INCLUDE_DIRS}) set_target_properties(libvtrutil PROPERTIES PREFIX "") #Avoid extra 'lib' prefix #Ensure version is always up to date by requiring version to be run first -add_dependencies(libvtrutil version) +if (VTR_ENABLE_VERSION) + add_dependencies(libvtrutil version) +endif() #Specify link-time dependencies target_link_libraries(libvtrutil diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 3c45a7a8379..d459653b0a1 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -61,6 +61,9 @@ bool operator!=(const RectUnion& lhs, const RectUnion& rhs); template class Point { public: //Constructors + // below is to create a no argument constructor for libopenfpga/libopenfpgautil/src/openfpga_pb_parser.cpp + // need to figure out a better solution to avoid change this in libs from vtr + Point(); Point(T x_val, T y_val) noexcept; public: //Accessors diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 6d421a856db..6cc932ae4a9 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -3,6 +3,11 @@ namespace vtr { * Point */ +template +Point::Point() { + //pass +} + template Point::Point(T x_val, T y_val) noexcept : x_(x_val) diff --git a/libs/libvtrutil/src/vtr_logic.h b/libs/libvtrutil/src/vtr_logic.h index 896d78fe842..21b08fea22b 100644 --- a/libs/libvtrutil/src/vtr_logic.h +++ b/libs/libvtrutil/src/vtr_logic.h @@ -16,6 +16,8 @@ constexpr int FALSE = 0; constexpr int TRUE = 1; +#include + namespace vtr { /** @@ -25,9 +27,12 @@ enum class LogicValue { FALSE = 0, TRUE = 1, DONT_CARE = 2, - UNKOWN = 3 + UNKOWN = 3, + NUM_LOGIC_VALUE_TYPES }; +constexpr std::array LOGIC_VALUE_STRING = {{"false", "true", "don't care", "unknown"}}; + } // namespace vtr #endif diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index 3c7c03b1782..7c12a8a9a7f 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -34,6 +34,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, const std::map& instance_counts, float maximum_utilization); static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, const std::vector& limiting_resources = std::vector()); +// static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); static void CheckGrid(const DeviceGrid& grid); @@ -46,6 +47,14 @@ static void set_grid_block_type(int priority, vtr::NdMatrix& grid_priorities, const t_metadata_dict* meta); +// static void set_vib_grid_block_type(int priority, +// const VibInf* type, +// int layer_num, +// size_t x_root, +// size_t y_root, +// vtr::NdMatrix& vib_grid, +// vtr::NdMatrix& grid_priorities); + ///@brief Create the device grid based on resource requirements DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, const std::map& minimum_instance_counts, float target_device_utilization) { if (layout_name == "auto") { @@ -139,6 +148,37 @@ DeviceGrid create_device_grid(const std::string& layout_name, const std::vector< } } +// VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { +// if (layout_name == "auto") { +// //We do not support auto layout now +// // +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); + +// } else { +// //Use the specified device + +// //Find the matching grid definition +// auto cmp = [&](const t_vib_grid_def& grid_def) { +// return grid_def.name == layout_name; +// }; + +// auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); +// if (iter == vib_grid_layouts.end()) { +// //Not found +// std::string valid_names; +// for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { +// if (i != 0) { +// valid_names += ", "; +// } +// valid_names += "'" + vib_grid_layouts[i].name + "'"; +// } +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); +// } + +// return build_vib_device_grid(*iter, iter->width, iter->height); +// } +// } + /** * @brief Create a device grid which satisfies the minimum block counts * @@ -550,6 +590,226 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt return device_grid; } +// ///@brief Build the specified device grid +// static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { +// if (grid_def.grid_type == VibGridDefType::VIB_FIXED) { +// if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { +// VPR_FATAL_ERROR(VPR_ERROR_OTHER, +// "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", +// grid_width, grid_height, grid_def.width, grid_def.height); +// } +// } + +// auto& device_ctx = g_vpr_ctx.device(); + +// //Initialize the grid and each location priority based on available dies in the architecture file +// vtr::NdMatrix vib_grid; +// vtr::NdMatrix grid_priorities; +// int num_layers = (int)grid_def.layers.size(); +// vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); + +// //Track the current priority for each grid location +// // Note that we initialize it to the lowest (i.e. most negative) possible value, so +// // any user-specified priority will override the default empty grid +// grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); + +// //Initialize the device to all empty blocks +// const VibInf* empty_type = nullptr; +// //VTR_ASSERT(empty_type != nullptr); +// for (int layer = 0; layer < num_layers; ++layer) { +// for (size_t x = 0; x < grid_width; ++x) { +// for (size_t y = 0; y < grid_height; ++y) { +// set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning +// empty_type, +// layer, x, y, +// vib_grid, grid_priorities); +// } +// } +// } + +// FormulaParser p; +// std::set seen_types; +// for (int layer = 0; layer < num_layers; layer++) { +// for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { +// //Fill in the block types according to the specification +// //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); +// const VibInf* type = nullptr; +// for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { +// if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { +// type = &device_ctx.arch->vib_infs[vib_type]; +// break; +// } +// } + +// if (!type) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Failed to find block type '%s' for grid location specification", +// grid_loc_def.block_type.c_str()); +// } + +// seen_types.insert(type); + +// t_formula_data vars; +// vars.set_var_value("W", grid_width); +// vars.set_var_value("H", grid_height); +// vars.set_var_value("w", 1); +// vars.set_var_value("h", 1); + +// //Load the x specification +// auto& xspec = grid_loc_def.x; + +// VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); +// VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); +// VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); +// VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); + +// size_t startx = p.parse_formula(xspec.start_expr, vars); +// size_t endx = p.parse_formula(xspec.end_expr, vars); +// size_t incrx = p.parse_formula(xspec.incr_expr, vars); +// size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); + +// //Load the y specification +// auto& yspec = grid_loc_def.y; + +// VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); +// VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); +// VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); +// VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); + +// size_t starty = p.parse_formula(yspec.start_expr, vars); +// size_t endy = p.parse_formula(yspec.end_expr, vars); +// size_t incry = p.parse_formula(yspec.incr_expr, vars); +// size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); + +// //Check start against the device dimensions +// // Start locations outside the device will never create block instances +// if (startx > grid_width - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", +// type->get_name(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); +// } +// continue; //No instances will be created +// } + +// if (starty > grid_height - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", +// type->get_name(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); +// } +// continue; //No instances will be created +// } + +// //Check end against the device dimensions +// if (endx > grid_width - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", +// type->get_name(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); +// } +// } + +// if (endy > grid_height - 1) { +// if (warn_out_of_range) { +// VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", +// type->get_name(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); +// } +// } + +// //The end must fall after (or equal) to the start +// if (endx < startx) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", +// xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name()); +// } + +// if (endy < starty) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", +// yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name()); +// } + +// //The minimum increment is the block dimension +// //VTR_ASSERT(type->width > 0); +// if (incrx < 1/*size_t(type->width)*/) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification incrx for block type '%s' must be at least" +// " block width (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), 1, xspec.incr_expr.c_str(), incrx); +// } + +// //VTR_ASSERT(type->height > 0); +// if (incry < 1/*size_t(type->height)*/) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification incry for block type '%s' must be at least" +// " block height (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), 1, yspec.incr_expr.c_str(), incry); +// } + +// //The minimum repeat is the region dimension +// size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive +// if (repeatx < region_width) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification repeatx for block type '%s' must be at least" +// " the region width (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), region_width, xspec.repeat_expr.c_str(), repeatx); +// } + +// size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive +// if (repeaty < region_height) { +// VPR_FATAL_ERROR(VPR_ERROR_ARCH, +// "Grid location specification repeaty for block type '%s' must be at least" +// " the region height (%d) to avoid overlapping instances (was %s = %d)", +// type->get_name(), region_height, xspec.repeat_expr.c_str(), repeaty); +// } + +// //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", +// // type->name, grid_loc_def.priority, +// // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, +// // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); + +// size_t x_end = 0; +// for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction +// size_t x_start = startx + kx * repeatx; +// x_end = endx + kx * repeatx; + +// size_t y_end = 0; +// for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction +// size_t y_start = starty + ky * repeaty; +// y_end = endy + ky * repeaty; + +// size_t x_max = std::min(x_end, grid_width - 1); +// size_t y_max = std::min(y_end, grid_height - 1); + +// //Fill in the region +// for (size_t x = x_start; x <= x_max; x += incrx) { +// for (size_t y = y_start; y <= y_max; y += incry) { +// set_vib_grid_block_type(grid_loc_def.priority, +// type, +// layer, x, y, +// vib_grid, grid_priorities); +// } +// } +// } +// } +// } +// } + +// //Warn if any types were not specified in the grid layout +// // for (auto const& type : device_ctx.physical_tile_types) { +// // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified + +// // if (!seen_types.count(&type)) { +// // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", +// // type.name); +// // } +// // } + +// auto vib_device_grid = VibDeviceGrid(grid_def.name, vib_grid); + +// // CheckGrid(device_grid); + +// return vib_device_grid; +// } + static void set_grid_block_type(int priority, const t_physical_tile_type* type, int layer_num, @@ -690,6 +950,146 @@ static void set_grid_block_type(int priority, } } +// static void set_vib_grid_block_type(int priority, +// const VibInf* type, +// int layer_num, +// size_t x_root, +// size_t y_root, +// vtr::NdMatrix& vib_grid, +// vtr::NdMatrix& grid_priorities) { +// struct TypeLocation { +// TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) +// : x(x_val) +// , y(y_val) +// , type(type_val) +// , priority(priority_val) {} +// size_t x; +// size_t y; +// const VibInf* type; +// int priority; + +// bool operator<(const TypeLocation& rhs) const { +// return x < rhs.x || y < rhs.y || type < rhs.type; +// } +// }; + +// //Collect locations effected by this block +// std::set target_locations; +// for (size_t x = x_root; x < x_root + 1; ++x) { +// for (size_t y = y_root; y < y_root + 1; ++y) { +// target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); +// } +// } + +// //Record the highest priority of all effected locations +// auto iter = target_locations.begin(); +// TypeLocation max_priority_type_loc = *iter; +// for (; iter != target_locations.end(); ++iter) { +// if (iter->priority > max_priority_type_loc.priority) { +// max_priority_type_loc = *iter; +// } +// } + +// if (priority < max_priority_type_loc.priority) { +// //Lower priority, do not override +// #ifdef VERBOSE +// VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", +// type->name, x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, +// max_priority_type_loc.priority, priority); +// #endif +// return; +// } + +// if (priority == max_priority_type_loc.priority) { +// //Ambiguous case where current grid block and new specification have equal priority +// // +// //We arbitrarily decide to take the 'last applied' wins approach, and warn the user +// //about the potential ambiguity +// VTR_LOG_WARN( +// "Ambiguous block type specification at grid location (%zu,%zu)." +// " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." +// " The last specification will apply.\n", +// x_root, y_root, +// max_priority_type_loc.type->get_name(), max_priority_type_loc.x, max_priority_type_loc.y, +// priority, type->get_name()); +// } + +// //Mark all the grid tiles 'covered' by this block with the appropriate type +// //and width/height offsets +// std::set root_blocks_to_rip_up; +// auto& device_ctx = g_vpr_ctx.device(); +// for (size_t x = x_root; x < x_root + 1; ++x) { +// VTR_ASSERT(x < vib_grid.end_index(1)); + +// //size_t x_offset = x - x_root; +// for (size_t y = y_root; y < y_root + 1; ++y) { +// VTR_ASSERT(y < vib_grid.end_index(2)); +// //size_t y_offset = y - y_root; + +// auto& grid_tile = vib_grid[layer_num][x][y]; +// VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); + +// if (grid_tile != nullptr +// //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE +// ) { +// //We are overriding a non-empty block, we need to be careful +// //to ensure we remove any blocks which will be invalidated when we +// //overwrite part of their locations + +// size_t orig_root_x = x; +// size_t orig_root_y = y; + +// root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, +// orig_root_y, +// vib_grid[layer_num][x][y], +// grid_priorities[layer_num][x][y])); +// } + +// vib_grid[layer_num][x][y] = type; +// //grid[layer_num][x][y].width_offset = x_offset; +// //grid[layer_num][x][y].height_offset = y_offset; +// //grid[layer_num][x][y].meta = meta; + +// grid_priorities[layer_num][x][y] = priority; +// } +// } + +// //Rip-up any invalidated blocks +// for (auto invalidated_root : root_blocks_to_rip_up) { +// //Mark all the grid locations used by this root block as empty +// for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { +// int x_offset = x - invalidated_root.x; +// for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { +// int y_offset = y - invalidated_root.y; + +// if (vib_grid[layer_num][x][y] == invalidated_root.type +// && 0 == x_offset +// && 0 == y_offset) { +// //This is a left-over invalidated block, mark as empty +// // Note: that we explicitly check the type and offsets, since the original block +// // may have been completely overwritten, and we don't want to change anything +// // in that case +// //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); +// //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); + +// #ifdef VERBOSE +// VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", +// invalidated_root.type->name, invalidated_root.x, invalidated_root.y, +// x_offset, y_offset, +// type->name, x_root, y_root); +// #endif + +// vib_grid[layer_num][x][y] = nullptr; +// //grid[layer_num][x][y].width_offset = 0; +// //grid[layer_num][x][y].height_offset = 0; + +// grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); +// } +// } +// } +// } +// } + ///@brief Check grid is valid static void CheckGrid(const DeviceGrid& grid) { for (int layer_num = 0; layer_num < grid.get_num_layers(); layer_num++) { //Check each die individually diff --git a/vpr/src/base/SetupGrid.h b/vpr/src/base/SetupGrid.h index 5760ba8a7d4..81f97352e33 100644 --- a/vpr/src/base/SetupGrid.h +++ b/vpr/src/base/SetupGrid.h @@ -22,10 +22,8 @@ DeviceGrid create_device_grid(const std::string& layout_name, float target_device_utilization = 0.0); ///@brief Find the device close in size to the specified dimensions -DeviceGrid create_device_grid(const std::string& layout_name, - const std::vector& grid_layouts, - size_t min_width, - size_t min_height); + +DeviceGrid create_device_grid(const std::string& layout_name, const std::vector& grid_layouts, size_t min_width, size_t min_height); /** * @brief Returns the effective size of the device diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 78b8f797ff5..1c906937d02 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -46,6 +46,15 @@ static void SetupSwitches(const t_arch& Arch, static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts); static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch); +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& Switches, + const std::vector& Segments, + std::vector& vib_infs); + +static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms); +static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name); + + /** * @brief Identify which switch must be used for *track* to *IPIN* connections based on architecture file specification. * @param Arch Architecture file specification @@ -237,6 +246,8 @@ void SetupVPR(const t_options* options, routingArch->write_rr_graph_filename = options->write_rr_graph_file; routingArch->read_rr_graph_filename = options->read_rr_graph_file; + SetupVibInf(device_ctx.physical_tile_types, arch->switches, arch->Segments, arch->vib_infs); + for (auto has_global_routing : arch->layer_global_routing) { device_ctx.inter_cluster_prog_routing_resources.emplace_back(has_global_routing); } @@ -416,9 +427,11 @@ static void SetupSwitches(const t_arch& Arch, static void SetupRoutingArch(const t_arch& Arch, t_det_routing_arch* RoutingArch) { RoutingArch->switch_block_type = Arch.SBType; + RoutingArch->switch_block_subtype = Arch.SBSubType; RoutingArch->R_minW_nmos = Arch.R_minW_nmos; RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; + RoutingArch->subFs = Arch.subFs; RoutingArch->directionality = BI_DIRECTIONAL; if (!Arch.Segments.empty()) { RoutingArch->directionality = Arch.Segments[0].directionality; @@ -426,6 +439,15 @@ static void SetupRoutingArch(const t_arch& Arch, /* copy over the switch block information */ RoutingArch->switchblocks = Arch.switchblocks; + + /* Copy the tileable routing setting */ + RoutingArch->tileable = Arch.tileable; + RoutingArch->perimeter_cb = Arch.perimeter_cb; + RoutingArch->shrink_boundary = Arch.shrink_boundary; + RoutingArch->through_channel = Arch.through_channel; + RoutingArch->opin2all_sides = Arch.opin2all_sides; + RoutingArch->concat_wire = Arch.concat_wire; + RoutingArch->concat_pass_wire = Arch.concat_pass_wire; } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { @@ -456,6 +478,11 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->router_algorithm = Options.RouterAlgorithm; RouterOpts->fixed_channel_width = Options.RouteChanWidth; RouterOpts->min_channel_width_hint = Options.min_route_chan_width_hint; + + //TODO document these? + RouterOpts->trim_empty_channels = false; /* DEFAULT */ + RouterOpts->trim_obs_channels = false; /* DEFAULT */ + RouterOpts->read_rr_edge_metadata = Options.read_rr_edge_metadata; RouterOpts->reorder_rr_graph_nodes_algorithm = Options.reorder_rr_graph_nodes_algorithm; RouterOpts->reorder_rr_graph_nodes_threshold = Options.reorder_rr_graph_nodes_threshold; @@ -716,6 +743,8 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi analysis_opts.timing_update_type = Options.timing_update_type; analysis_opts.write_timing_summary = Options.write_timing_summary; + + analysis_opts.skip_sync_clustering_and_routing_results = Options.skip_sync_clustering_and_routing_results; } static void SetupPowerOpts(const t_options& Options, t_power_opts* power_opts, t_arch* Arch) { @@ -1004,3 +1033,273 @@ static void do_reachability_analysis(t_physical_tile_type* physical_tile, } } } + +static void SetupVibInf(const std::vector& PhysicalTileTypes, + const std::vector& switches, + const std::vector& Segments, + std::vector& vib_infs) { + VTR_ASSERT(!vib_infs.empty()); + for (auto& vib_inf : vib_infs) { + for (size_t i_switch = 0; i_switch < switches.size(); i_switch++) { + if (vib_inf.get_switch_name() == switches[i_switch].name) { + vib_inf.set_switch_idx(i_switch); + break; + } + } + + std::vector seg_groups = vib_inf.get_seg_groups(); + for (auto& seg_group : seg_groups) { + for (int i_seg = 0; i_seg < (int)Segments.size(); i_seg++) { + if (Segments[i_seg].name == seg_group.name) { + seg_group.seg_index = i_seg; + break; + } + } + } + vib_inf.set_seg_groups(seg_groups); + + std::vector first_stages = vib_inf.get_first_stages(); + for (auto& first_stage : first_stages) { + auto& from_tokens = first_stage.from_tokens; + for (const auto& from_token : from_tokens) { + ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, first_stage.froms); + } + } + vib_inf.set_first_stages(first_stages); + + auto second_stages = vib_inf.get_second_stages(); + for (auto& second_stage : second_stages) { + std::vector tos; + + ProcessFromOrToTokens(second_stage.to_tokens, PhysicalTileTypes, Segments, tos); + for (auto& to : tos) { + VTR_ASSERT(to.from_type == SEGMENT || to.from_type == PB); + second_stage.to.push_back(to); + } + + auto from_tokens = second_stage.from_tokens; + for (const auto& from_token : from_tokens) { + ProcessFromOrToTokens(from_token, PhysicalTileTypes, Segments, second_stage.froms); + } + } + vib_inf.set_second_stages(second_stages); + + } +} + +static void ProcessFromOrToTokens(const std::vector Tokens, const std::vector& PhysicalTileTypes, const std::vector segments, std::vector& froms) { + for (int i_token = 0; i_token < (int)Tokens.size(); i_token++) { + std::string Token = Tokens[i_token]; + const char* Token_char = Token.c_str(); + auto token = vtr::split(Token, "."); + if (token.size() == 1) { + t_from_or_to_inf from_inf; + from_inf.type_name = token[0]; + from_inf.from_type = MUX; + froms.push_back(from_inf); + } + else if (token.size() == 2) { + std::string from_type_name = token[0]; + e_multistage_mux_from_or_to_type from_type; + for (int i_phy_type = 0; i_phy_type < (int)PhysicalTileTypes.size(); i_phy_type++) { + if (from_type_name == PhysicalTileTypes[i_phy_type].name) { + from_type = PB; + int start_pin_index, end_pin_index; + char *pb_type_name, *port_name; + pb_type_name = nullptr; + port_name = nullptr; + pb_type_name = new char[strlen(Token_char)]; + port_name = new char[strlen(Token_char)]; + parse_pin_name(Token_char, &start_pin_index, &end_pin_index, pb_type_name, port_name); + + std::vector all_sub_tile_to_tile_pin_indices; + for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + int sub_tile_capacity = sub_tile.capacity.total(); + + int start = 0; + int end = 0; + int i_port = 0; + for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + start = sub_tile.ports[i_port].absolute_first_pin_index; + end = start + sub_tile.ports[i_port].num_pins - 1; + break; + } + } + if (i_port == (int)sub_tile.ports.size()) { + continue; + } + for (int pin_num = start; pin_num <= end; ++pin_num) { + VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + all_sub_tile_to_tile_pin_indices.push_back(physical_pin_index); + } + } + } + + if (start_pin_index == end_pin_index && start_pin_index < 0) { + start_pin_index = 0; + end_pin_index = all_sub_tile_to_tile_pin_indices.size() - 1; + } + + if ((int)all_sub_tile_to_tile_pin_indices.size() <= start_pin_index || (int)all_sub_tile_to_tile_pin_indices.size() <= end_pin_index) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "The index of pbtype %s : port %s exceeds its total number!\n", pb_type_name, port_name); + } + + for (int i = start_pin_index; i <= end_pin_index; i++) { + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_phy_type; + from_inf.phy_pin_index = all_sub_tile_to_tile_pin_indices[i]; + froms.push_back(from_inf); + } + + // for (auto& sub_tile : PhysicalTileTypes[i_phy_type].sub_tiles) { + // //int sub_tile_index = sub_tile.index; + // int sub_tile_capacity = sub_tile.capacity.total(); + + // int i_port = 0; + // for (; i_port < (int)sub_tile.ports.size(); ++i_port) { + + // if (!strcmp(sub_tile.ports[i_port].name, port_name)) { + // if (start_pin_index == end_pin_index && start_pin_index < 0) { + // start_pin_index = 0; + // end_pin_index = sub_tile.ports[i_port].num_pins - 1; + // } + // start_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // end_pin_index += sub_tile.ports[i_port].absolute_first_pin_index; + // break; + // } + // } + + // if (i_port == (int)sub_tile.ports.size()) { + // continue; + // } + + // for (int pin_num = start_pin_index; pin_num <= end_pin_index; ++pin_num) { + // VTR_ASSERT(pin_num < (int)sub_tile.sub_tile_to_tile_pin_indices.size() / sub_tile_capacity); + // for (int capacity = 0; capacity < sub_tile_capacity; ++ capacity) { + // int sub_tile_pin_index = pin_num + capacity * sub_tile.num_phy_pins / sub_tile_capacity; + // int physical_pin_index = sub_tile.sub_tile_to_tile_pin_indices[sub_tile_pin_index]; + // t_from_or_to_inf from_inf; + // from_inf.type_name = from_type_name; + // from_inf.from_type = from_type; + // from_inf.type_index = i_phy_type; + // from_inf.phy_pin_index = physical_pin_index; + // froms.push_back(from_inf); + // } + // } + // } + + } + } + for (int i_seg_type = 0; i_seg_type < (int)segments.size(); i_seg_type++) { + if (from_type_name == segments[i_seg_type].name) { + from_type = SEGMENT; + std::string from_detail = token[1]; + if (from_detail.length() >= 2) { + char dir = from_detail.c_str()[0]; + from_detail.erase(from_detail.begin()); + int seg_index = std::stoi(from_detail); + + t_from_or_to_inf from_inf; + from_inf.type_name = from_type_name; + from_inf.from_type = from_type; + from_inf.type_index = i_seg_type; + from_inf.seg_dir = dir; + from_inf.seg_index = seg_index; + froms.push_back(from_inf); + } + + break; + } + } + VTR_ASSERT(from_type == PB || from_type == SEGMENT); + + } + else { + std::string msg = vtr::string_fmt("Failed to parse vib mux from information '%s'", Token.c_str()); + VTR_LOGF_ERROR(__FILE__, __LINE__, msg.c_str()); + } + } +} + +static void parse_pin_name(const char* src_string, int* start_pin_index, int* end_pin_index, char* pb_type_name, char* port_name) { + /* Parses out the pb_type_name and port_name * + * If the start_pin_index and end_pin_index is specified, parse them too. * + * Return the values parsed by reference. */ + + char source_string[128]; + int ichar, match_count; + + // parse out the pb_type and port name, possibly pin_indices + const char* find_format = strstr(src_string, "["); + if (find_format == nullptr) { + /* Format "pb_type_name.port_name" */ + *start_pin_index = *end_pin_index = -1; + + + strcpy(source_string, src_string); + + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s", pb_type_name, port_name); + if (match_count != 2) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } else { + /* Format "pb_type_name.port_name[end_pin_index:start_pin_index]" */ + strcpy(source_string, src_string); + for (ichar = 0; ichar < (int)(strlen(source_string)); ichar++) { + //Need white space between the components when using %s with + //sscanf + if (source_string[ichar] == '.') + source_string[ichar] = ' '; + if (source_string[ichar] == '[') + source_string[ichar] = ' '; + } + + match_count = sscanf(source_string, "%s %s %d:%d]", + pb_type_name, port_name, + end_pin_index, start_pin_index); + if (match_count != 4) { + match_count = sscanf(source_string, "%s %s %d]", + pb_type_name, port_name, + end_pin_index); + *start_pin_index = *end_pin_index; + if (match_count != 3) { + VTR_LOG_ERROR( + "Invalid pin - %s, name should be in the format " + "\"pb_type_name\".\"port_name\" or \"pb_type_name\".\"port_name[end_pin_index:start_pin_index]\". " + "The end_pin_index and start_pin_index can be the same.\n", + src_string); + exit(1); + } + } + if (*end_pin_index < 0 || *start_pin_index < 0) { + VTR_LOG_ERROR( + "Invalid pin - %s, the pin_index in " + "[end_pin_index:start_pin_index] should not be a negative value.\n", + src_string); + exit(1); + } + if (*end_pin_index < *start_pin_index) { + int temp; + temp = *end_pin_index; + *end_pin_index = *start_pin_index; + *start_pin_index = temp; + } + } +} diff --git a/vpr/src/base/SetupVibGrid.cpp b/vpr/src/base/SetupVibGrid.cpp new file mode 100644 index 00000000000..98bd676f058 --- /dev/null +++ b/vpr/src/base/SetupVibGrid.cpp @@ -0,0 +1,421 @@ +#include +#include +#include +#include +#include + +#include "vtr_assert.h" +#include "vtr_math.h" +#include "vtr_log.h" + +#include "vpr_types.h" +#include "vpr_error.h" +#include "vpr_utils.h" + +#include "globals.h" +#include "SetupGrid.h" +#include "SetupVibGrid.h" +#include "vtr_expr_eval.h" + +using vtr::FormulaParser; +using vtr::t_formula_data; + +static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range = true); + +static void set_vib_grid_block_type(int priority, + const VibInf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities); + +VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts) { + if (layout_name == "auto") { + //We do not support auto layout now + // + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "We do not support auto layout now\n"); + + } else { + //Use the specified device + + //Find the matching grid definition + auto cmp = [&](const t_vib_grid_def& grid_def) { + return grid_def.name == layout_name; + }; + + auto iter = std::find_if(vib_grid_layouts.begin(), vib_grid_layouts.end(), cmp); + if (iter == vib_grid_layouts.end()) { + //Not found + std::string valid_names; + for (size_t i = 0; i < vib_grid_layouts.size(); ++i) { + if (i != 0) { + valid_names += ", "; + } + valid_names += "'" + vib_grid_layouts[i].name + "'"; + } + VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find grid layout named '%s' (valid grid layouts: %s)\n", layout_name.c_str(), valid_names.c_str()); + } + + return build_vib_device_grid(*iter, iter->width, iter->height); + } +} + +///@brief Build the specified device grid +static VibDeviceGrid build_vib_device_grid(const t_vib_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range) { + if (grid_def.grid_type == VibGridDefType::VIB_FIXED) { + if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "Requested grid size (%zu%zu) does not match fixed device size (%dx%d)", + grid_width, grid_height, grid_def.width, grid_def.height); + } + } + + auto& device_ctx = g_vpr_ctx.device(); + + //Initialize the grid and each location priority based on available dies in the architecture file + vtr::NdMatrix vib_grid; + vtr::NdMatrix grid_priorities; + int num_layers = (int)grid_def.layers.size(); + vib_grid.resize(std::array{(size_t)num_layers, grid_width, grid_height}); + + //Track the current priority for each grid location + // Note that we initialize it to the lowest (i.e. most negative) possible value, so + // any user-specified priority will override the default empty grid + grid_priorities.resize(std::array{(size_t)num_layers, grid_width, grid_height}, std::numeric_limits::lowest()); + + //Initialize the device to all empty blocks + const VibInf* empty_type = nullptr; + //VTR_ASSERT(empty_type != nullptr); + for (int layer = 0; layer < num_layers; ++layer) { + for (size_t x = 0; x < grid_width; ++x) { + for (size_t y = 0; y < grid_height; ++y) { + set_vib_grid_block_type(std::numeric_limits::lowest() + 1, //+1 so it overrides without warning + empty_type, + layer, x, y, + vib_grid, grid_priorities); + } + } + } + + FormulaParser p; + std::set seen_types; + for (int layer = 0; layer < num_layers; layer++) { + for (const auto& grid_loc_def : grid_def.layers.at(layer).loc_defs) { + //Fill in the block types according to the specification + //auto type = find_tile_type_by_name(grid_loc_def.block_type, device_ctx.physical_tile_types); + const VibInf* type = nullptr; + for (size_t vib_type = 0; vib_type < device_ctx.arch->vib_infs.size(); vib_type++) { + if (grid_loc_def.block_type == device_ctx.arch->vib_infs[vib_type].get_name()) { + type = &device_ctx.arch->vib_infs[vib_type]; + break; + } + } + + if (!type) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Failed to find block type '%s' for grid location specification", + grid_loc_def.block_type.c_str()); + } + + seen_types.insert(type); + + t_formula_data vars; + vars.set_var_value("W", grid_width); + vars.set_var_value("H", grid_height); + vars.set_var_value("w", 1); + vars.set_var_value("h", 1); + + //Load the x specification + auto& xspec = grid_loc_def.x; + + VTR_ASSERT_MSG(!xspec.start_expr.empty(), "x start position must be specified"); + VTR_ASSERT_MSG(!xspec.end_expr.empty(), "x end position must be specified"); + VTR_ASSERT_MSG(!xspec.incr_expr.empty(), "x increment must be specified"); + VTR_ASSERT_MSG(!xspec.repeat_expr.empty(), "x repeat must be specified"); + + size_t startx = p.parse_formula(xspec.start_expr, vars); + size_t endx = p.parse_formula(xspec.end_expr, vars); + size_t incrx = p.parse_formula(xspec.incr_expr, vars); + size_t repeatx = p.parse_formula(xspec.repeat_expr, vars); + + //Load the y specification + auto& yspec = grid_loc_def.y; + + VTR_ASSERT_MSG(!yspec.start_expr.empty(), "y start position must be specified"); + VTR_ASSERT_MSG(!yspec.end_expr.empty(), "y end position must be specified"); + VTR_ASSERT_MSG(!yspec.incr_expr.empty(), "y increment must be specified"); + VTR_ASSERT_MSG(!yspec.repeat_expr.empty(), "y repeat must be specified"); + + size_t starty = p.parse_formula(yspec.start_expr, vars); + size_t endy = p.parse_formula(yspec.end_expr, vars); + size_t incry = p.parse_formula(yspec.incr_expr, vars); + size_t repeaty = p.parse_formula(yspec.repeat_expr, vars); + + //Check start against the device dimensions + // Start locations outside the device will never create block instances + if (startx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification startx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->get_name().c_str(), xspec.start_expr.c_str(), startx, 0, grid_width - 1); + } + continue; //No instances will be created + } + + if (starty > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification starty (%s = %d) falls outside device vertical range [%d,%d]\n", + type->get_name().c_str(), yspec.start_expr.c_str(), starty, 0, grid_height - 1); + } + continue; //No instances will be created + } + + //Check end against the device dimensions + if (endx > grid_width - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endx (%s = %d) falls outside device horizontal range [%d,%d]\n", + type->get_name().c_str(), xspec.end_expr.c_str(), endx, 0, grid_width - 1); + } + } + + if (endy > grid_height - 1) { + if (warn_out_of_range) { + VTR_LOG_WARN("Block type '%s' grid location specification endy (%s = %d) falls outside device vertical range [%d,%d]\n", + type->get_name().c_str(), yspec.end_expr.c_str(), endy, 0, grid_height - 1); + } + } + + //The end must fall after (or equal) to the start + if (endx < startx) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endx (%s = %d) can not come before startx (%s = %d) for block type '%s'", + xspec.end_expr.c_str(), endx, xspec.start_expr.c_str(), startx, type->get_name().c_str()); + } + + if (endy < starty) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification endy (%s = %d) can not come before starty (%s = %d) for block type '%s'", + yspec.end_expr.c_str(), endy, yspec.start_expr.c_str(), starty, type->get_name().c_str()); + } + + //The minimum increment is the block dimension + //VTR_ASSERT(type->width > 0); + if (incrx < 1/*size_t(type->width)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incrx for block type '%s' must be at least" + " block width (%d) to avoid overlapping instances (was %s = %d)", + type->get_name().c_str(), 1, xspec.incr_expr.c_str(), incrx); + } + + //VTR_ASSERT(type->height > 0); + if (incry < 1/*size_t(type->height)*/) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification incry for block type '%s' must be at least" + " block height (%d) to avoid overlapping instances (was %s = %d)", + type->get_name().c_str(), 1, yspec.incr_expr.c_str(), incry); + } + + //The minimum repeat is the region dimension + size_t region_width = endx - startx + 1; //+1 since start/end are both inclusive + if (repeatx < region_width) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeatx for block type '%s' must be at least" + " the region width (%d) to avoid overlapping instances (was %s = %d)", + type->get_name().c_str(), region_width, xspec.repeat_expr.c_str(), repeatx); + } + + size_t region_height = endy - starty + 1; //+1 since start/end are both inclusive + if (repeaty < region_height) { + VPR_FATAL_ERROR(VPR_ERROR_ARCH, + "Grid location specification repeaty for block type '%s' must be at least" + " the region height (%d) to avoid overlapping instances (was %s = %d)", + type->get_name().c_str(), region_height, xspec.repeat_expr.c_str(), repeaty); + } + + //VTR_LOG("Applying grid_loc_def for '%s' priority %d startx=%s=%zu, endx=%s=%zu, starty=%s=%zu, endx=%s=%zu,\n", + // type->name, grid_loc_def.priority, + // xspec.start_expr.c_str(), startx, xspec.end_expr.c_str(), endx, + // yspec.start_expr.c_str(), starty, yspec.end_expr.c_str(), endy); + + size_t x_end = 0; + for (size_t kx = 0; x_end < grid_width; ++kx) { //Repeat in x direction + size_t x_start = startx + kx * repeatx; + x_end = endx + kx * repeatx; + + size_t y_end = 0; + for (size_t ky = 0; y_end < grid_height; ++ky) { //Repeat in y direction + size_t y_start = starty + ky * repeaty; + y_end = endy + ky * repeaty; + + size_t x_max = std::min(x_end, grid_width - 1); + size_t y_max = std::min(y_end, grid_height - 1); + + //Fill in the region + for (size_t x = x_start; x <= x_max; x += incrx) { + for (size_t y = y_start; y <= y_max; y += incry) { + set_vib_grid_block_type(grid_loc_def.priority, + type, + layer, x, y, + vib_grid, grid_priorities); + } + } + } + } + } + } + + //Warn if any types were not specified in the grid layout + // for (auto const& type : device_ctx.physical_tile_types) { + // if (&type == empty_type) continue; //Don't worry if empty hasn't been specified + + // if (!seen_types.count(&type)) { + // VTR_LOG_WARN("Block type '%s' was not specified in device grid layout\n", + // type.name); + // } + // } + + auto vib_device_grid = VibDeviceGrid(grid_def.name, vib_grid); + + // CheckGrid(device_grid); + + return vib_device_grid; +} + +static void set_vib_grid_block_type(int priority, + const VibInf* type, + int layer_num, + size_t x_root, + size_t y_root, + vtr::NdMatrix& vib_grid, + vtr::NdMatrix& grid_priorities) { + struct TypeLocation { + TypeLocation(size_t x_val, size_t y_val, const VibInf* type_val, int priority_val) + : x(x_val) + , y(y_val) + , type(type_val) + , priority(priority_val) {} + size_t x; + size_t y; + const VibInf* type; + int priority; + + bool operator<(const TypeLocation& rhs) const { + return x < rhs.x || y < rhs.y || type < rhs.type; + } + }; + + //Collect locations effected by this block + std::set target_locations; + for (size_t x = x_root; x < x_root + 1; ++x) { + for (size_t y = y_root; y < y_root + 1; ++y) { + target_locations.insert(TypeLocation(x, y, vib_grid[layer_num][x][y], grid_priorities[layer_num][x][y])); + } + } + + //Record the highest priority of all effected locations + auto iter = target_locations.begin(); + TypeLocation max_priority_type_loc = *iter; + for (; iter != target_locations.end(); ++iter) { + if (iter->priority > max_priority_type_loc.priority) { + max_priority_type_loc = *iter; + } + } + + if (priority < max_priority_type_loc.priority) { + //Lower priority, do not override +#ifdef VERBOSE + VTR_LOG("Not creating block '%s' at (%zu,%zu) since overlaps block '%s' at (%zu,%zu) with higher priority (%d > %d)\n", + type->name.c_str(), x_root, y_root, max_priority_type_loc.type->name, max_priority_type_loc.x, max_priority_type_loc.y, + max_priority_type_loc.priority, priority); +#endif + return; + } + + if (priority == max_priority_type_loc.priority) { + //Ambiguous case where current grid block and new specification have equal priority + // + //We arbitrarily decide to take the 'last applied' wins approach, and warn the user + //about the potential ambiguity + VTR_LOG_WARN( + "Ambiguous block type specification at grid location (%zu,%zu)." + " Existing block type '%s' at (%zu,%zu) has the same priority (%d) as new overlapping type '%s'." + " The last specification will apply.\n", + x_root, y_root, + max_priority_type_loc.type->get_name().c_str(), max_priority_type_loc.x, max_priority_type_loc.y, + priority, type->get_name().c_str()); + } + + //Mark all the grid tiles 'covered' by this block with the appropriate type + //and width/height offsets + std::set root_blocks_to_rip_up; + for (size_t x = x_root; x < x_root + 1; ++x) { + VTR_ASSERT(x < vib_grid.end_index(1)); + + //size_t x_offset = x - x_root; + for (size_t y = y_root; y < y_root + 1; ++y) { + VTR_ASSERT(y < vib_grid.end_index(2)); + //size_t y_offset = y - y_root; + + auto& grid_tile = vib_grid[layer_num][x][y]; + VTR_ASSERT(grid_priorities[layer_num][x][y] <= priority); + + if (grid_tile != nullptr + //&& grid_tile.type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE + ) { + //We are overriding a non-empty block, we need to be careful + //to ensure we remove any blocks which will be invalidated when we + //overwrite part of their locations + + size_t orig_root_x = x; + size_t orig_root_y = y; + + root_blocks_to_rip_up.insert(TypeLocation(orig_root_x, + orig_root_y, + vib_grid[layer_num][x][y], + grid_priorities[layer_num][x][y])); + } + + vib_grid[layer_num][x][y] = type; + //grid[layer_num][x][y].width_offset = x_offset; + //grid[layer_num][x][y].height_offset = y_offset; + //grid[layer_num][x][y].meta = meta; + + grid_priorities[layer_num][x][y] = priority; + } + } + + //Rip-up any invalidated blocks + for (auto invalidated_root : root_blocks_to_rip_up) { + //Mark all the grid locations used by this root block as empty + for (size_t x = invalidated_root.x; x < invalidated_root.x + 1; ++x) { + int x_offset = x - invalidated_root.x; + for (size_t y = invalidated_root.y; y < invalidated_root.y + 1; ++y) { + int y_offset = y - invalidated_root.y; + + if (vib_grid[layer_num][x][y] == invalidated_root.type + && 0 == x_offset + && 0 == y_offset) { + //This is a left-over invalidated block, mark as empty + // Note: that we explicitly check the type and offsets, since the original block + // may have been completely overwritten, and we don't want to change anything + // in that case + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->width == 1); + //VTR_ASSERT(device_ctx.EMPTY_PHYSICAL_TILE_TYPE->height == 1); + +#ifdef VERBOSE + VTR_LOG("Ripping up block '%s' at (%d,%d) offset (%d,%d). Overlapped by '%s' at (%d,%d)\n", + invalidated_root.type->name.c_str(), invalidated_root.x, invalidated_root.y, + x_offset, y_offset, + type->name.c_str(), x_root, y_root); +#endif + + vib_grid[layer_num][x][y] = nullptr; + //grid[layer_num][x][y].width_offset = 0; + //grid[layer_num][x][y].height_offset = 0; + + grid_priorities[layer_num][x][y] = std::numeric_limits::lowest(); + } + } + } + } +} diff --git a/vpr/src/base/SetupVibGrid.h b/vpr/src/base/SetupVibGrid.h new file mode 100644 index 00000000000..ddb1f8b7697 --- /dev/null +++ b/vpr/src/base/SetupVibGrid.h @@ -0,0 +1,17 @@ +#ifndef SETUPVIBGRID_H +#define SETUPVIBGRID_H + +/** + * @file + * @author Jason Luu + * @date October 8, 2008 + * + * @brief Initializes and allocates the physical logic block grid for VPR. + */ + +#include +#include "physical_types.h" + +VibDeviceGrid create_vib_device_grid(std::string layout_name, const std::vector& vib_grid_layouts); + +#endif diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 4ee6ce7a94a..3700e0abdb3 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -84,6 +84,10 @@ int binary_search_place_and_route(const Netlist<>& placement_net_list, graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } diff --git a/vpr/src/base/read_blif.cpp b/vpr/src/base/read_blif.cpp index 807e8c4a8c4..ef767444bf6 100644 --- a/vpr/src/base/read_blif.cpp +++ b/vpr/src/base/read_blif.cpp @@ -719,18 +719,15 @@ bool is_binary_param(const std::string& param) { } bool is_real_param(const std::string& param) { - const std::string chars = "012345678."; - /* Must be non-empty */ if (param.empty()) { return false; } - /* The string mustn't contain any other chars that the expected ones */ - for (size_t i = 0; i < param.length(); ++i) { - if (chars.find(param[i]) == std::string::npos) { - return false; - } + /* The string must match the regular expression */ + static const std::regex real_number_expr("[+-]?([0-9]*\\.[0-9]+)|([0-9]+\\.[0-9]*)"); + if (!std::regex_match(param, real_number_expr)) { + return false; } /* This is a real number param */ diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 26f9b5bb132..ece2ec3802d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -2994,6 +2994,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .help("Writes implemented design final timing summary to the specified JSON, XML or TXT file.") .show_in(argparse::ShowIn::HELP_ONLY); + analysis_grp.add_argument(args.skip_sync_clustering_and_routing_results, "--skip_sync_clustering_and_routing_results") + .help( + "Select to skip the synchronization on clustering results based on routing optimization results." + "Note that when this sync-up is disabled, clustering results may be wrong (leading to incorrect bitstreams)!") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& power_grp = parser.add_argument_group("power analysis options"); power_grp.add_argument(args.do_power, "--power") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index dd1be4b2575..ec896919c72 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -265,6 +265,7 @@ struct t_options { argparse::ArgValue post_synth_netlist_unconn_input_handling; argparse::ArgValue post_synth_netlist_unconn_output_handling; argparse::ArgValue write_timing_summary; + argparse::ArgValue skip_sync_clustering_and_routing_results; }; argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_options& args); diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index e06726fe817..ead89961aa1 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -619,6 +619,10 @@ void print_route(const Netlist<>& net_list, } break; + case MEDIUM: + fprintf(fp, " INDEX: "); + break; + default: VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in print_route: Unexpected traceback element type: %d (%s).\n", diff --git a/vpr/src/base/route_constraint.cpp_back b/vpr/src/base/route_constraint.cpp_back new file mode 100644 index 00000000000..4ed76deb108 --- /dev/null +++ b/vpr/src/base/route_constraint.cpp_back @@ -0,0 +1,43 @@ +#include "route_constraint.h" + +RouteConstraint::RouteConstraint() { + net_name_ = std::string(""); + net_type_ = std::string(""); + route_method_ = std::string(""); + is_valid_ = false; +} + +void RouteConstraint::set_net_name(std::string name) { + net_name_ = name; + return; +} + +std::string RouteConstraint::net_name() const { + return net_name_; +} + +void RouteConstraint::set_net_type(std::string type) { + net_type_ = type; + return; +} + +std::string RouteConstraint::net_type() const { + return net_type_; +} + +void RouteConstraint::set_route_model(std::string route_method) { + route_method_ = route_method; + return; +} + +std::string RouteConstraint::route_model() const { + return route_method_; +} + +void RouteConstraint::set_is_valid(bool value) { + is_valid_ = value; +} + +bool RouteConstraint::is_valid() const { + return is_valid_; +} diff --git a/vpr/src/base/route_constraint.h_back b/vpr/src/base/route_constraint.h_back new file mode 100644 index 00000000000..58b2839d060 --- /dev/null +++ b/vpr/src/base/route_constraint.h_back @@ -0,0 +1,65 @@ +#ifndef ROUTE_CONSTRAINT_H +#define ROUTE_CONSTRAINT_H + +#include "vpr_types.h" + +/** + * @file + * @brief This file defines the RouteConstraint class. + */ + +class RouteConstraint { + public: + /** + * @brief Constructor for the RouteConstraint class, sets member variables to invalid values + */ + RouteConstraint(); + + /** + * @brief get net name + */ + std::string net_name() const; + + /** + * @brief set net name + */ + void set_net_name(std::string); + + /** + * @brief get net type + */ + std::string net_type() const; + + /** + * @brief set net type + */ + void set_net_type(std::string); + + /** + * @brief get route model + */ + std::string route_model() const; + + /** + * @brief set route model + */ + void set_route_model(std::string); + + /** + * @brief set is valid + */ + void set_is_valid(bool); + + /** + * @brief get is valid + */ + bool is_valid() const; + + private: + std::string net_name_; + std::string net_type_; + std::string route_method_; + bool is_valid_; +}; + +#endif /* ROUTE_CONSTRAINT_H */ diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index be6115112e4..8ca6799433e 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -40,6 +40,7 @@ #include "pack.h" #include "place.h" #include "SetupGrid.h" +#include "SetupVibGrid.h" #include "setup_clocks.h" #include "setup_noc.h" #include "read_xml_noc_traffic_flows_file.h" @@ -498,6 +499,9 @@ void vpr_create_device_grid(const t_vpr_setup& vpr_setup, const t_arch& Arch) { //Build the device float target_device_utilization = vpr_setup.PackerOpts.target_device_utilization; device_ctx.grid = create_device_grid(vpr_setup.device_layout, Arch.grid_layouts, num_type_instances, target_device_utilization); + if (!Arch.vib_infs.empty()) { + device_ctx.vib_grid = create_vib_device_grid(vpr_setup.device_layout, Arch.vib_grid_layouts); + } VTR_ASSERT_MSG(device_ctx.grid.get_num_layers() <= MAX_NUM_LAYERS, "Number of layers should be less than MAX_NUM_LAYERS. " @@ -1107,6 +1111,9 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } } t_chan_width chan_width = init_chan(chan_width_fac, arch.Chans, graph_directionality); @@ -1359,7 +1366,8 @@ bool vpr_analysis_flow(const Netlist<>& net_list, VTR_LOG("*****************************************************************************************\n"); } - /* If routing is successful, apply post-routing annotations + /* If routing is successful and users do not force to skip the sync-up, + * - apply post-routing annotations * - apply logic block pin fix-up * * Note: @@ -1367,15 +1375,19 @@ bool vpr_analysis_flow(const Netlist<>& net_list, * for packer (default verbosity is set to 2 for compact logs) */ if (route_status.success()) { - if (is_flat) { - sync_netlists_to_routing_flat(); + if (!analysis_opts.skip_sync_clustering_and_routing_results) { + if (is_flat) { + sync_netlists_to_routing_flat(); + } else { + sync_netlists_to_routing(net_list, + g_vpr_ctx.device(), + g_vpr_ctx.mutable_atom(), + g_vpr_ctx.mutable_clustering(), + g_vpr_ctx.placement(), + vpr_setup.PackerOpts.pack_verbosity > 2); + } } else { - sync_netlists_to_routing(net_list, - g_vpr_ctx.device(), - g_vpr_ctx.mutable_atom(), - g_vpr_ctx.mutable_clustering(), - g_vpr_ctx.placement(), - vpr_setup.PackerOpts.pack_verbosity > 2); + VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to users select to skip it\n"); } std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing"; diff --git a/vpr/src/base/vpr_constraints.cpp_back b/vpr/src/base/vpr_constraints.cpp_back new file mode 100644 index 00000000000..9ae678c94e0 --- /dev/null +++ b/vpr/src/base/vpr_constraints.cpp_back @@ -0,0 +1,18 @@ +#include "vpr_constraints.h" + + +UserPlaceConstraints& VprConstraints::mutable_place_constraints() { + return placement_constraints_; +} + +UserRouteConstraints& VprConstraints::mutable_route_constraints() { + return route_constraints_; +} + +const UserPlaceConstraints& VprConstraints::place_constraints() const { + return placement_constraints_; +} + +const UserRouteConstraints& VprConstraints::route_constraints() const { + return route_constraints_; +} diff --git a/vpr/src/base/vpr_constraints.h b/vpr/src/base/vpr_constraints.h index 9d520e0107f..797032f6b7e 100644 --- a/vpr/src/base/vpr_constraints.h +++ b/vpr/src/base/vpr_constraints.h @@ -45,6 +45,34 @@ class VprConstraints { */ const UserRouteConstraints& route_constraints() const; + /** + * @brief add route constraint + * + * @param net_name the route constraint + */ + void add_route_constraint(UserRouteConstraints rc); + + /** + * @brief returns route constraint by index + * + * @param index the constraint index + */ + const UserRouteConstraints get_route_constraint_by_idx(std::size_t index) const; + + /** + * @brief returns route constraint of a specific net + * + * @param net_name the net name + */ + const UserRouteConstraints get_route_constraint_by_net_name(std::string net_name); + + /** + * @brief returns number of route constraints + * + * @param void + */ + int get_route_constraint_num(void) const; + private: UserRouteConstraints route_constraints_; UserPlaceConstraints placement_constraints_; diff --git a/vpr/src/base/vpr_constraints_writer.h b/vpr/src/base/vpr_constraints_writer.h index ddfcd259b43..acff1198a7b 100644 --- a/vpr/src/base/vpr_constraints_writer.h +++ b/vpr/src/base/vpr_constraints_writer.h @@ -27,6 +27,14 @@ class VprConstraints; +/** + * @brief Write out vpr constratins to an XML file based on current placement and + * route constraint settings + * + * @param vpr_setup VPR setup information + */ +void write_vpr_constraints(t_vpr_setup& vpr_setup); + /** * @brief Write out floorplan constraints to an XML file based on current placement * diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index f27bfa0d4ff..9b1744601a5 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -174,6 +174,9 @@ struct DeviceContext : public Context { * in this data structure should be used. */ DeviceGrid grid; + + VibDeviceGrid vib_grid; + /* * Empty types */ @@ -233,7 +236,13 @@ struct DeviceContext : public Context { /* A read-only view of routing resource graph to be the ONLY database * for client functions: GUI, placer, router, timing analyzer etc. */ - RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch()}; + RRGraphView rr_graph{rr_graph_builder.rr_nodes(), rr_graph_builder.node_lookup(), rr_graph_builder.rr_node_metadata(), rr_graph_builder.rr_edge_metadata(), rr_indexed_data, rr_rc_data, rr_graph_builder.rr_segments(), rr_graph_builder.rr_switch(), rr_graph_builder.node_in_edge_storage(), rr_graph_builder.node_ptc_storage()}; + + /* Track ids for each rr_node in the rr_graph. + * This is used by drawer for tileable routing resource graph + */ + std::map> rr_node_track_ids; + std::vector arch_switch_inf; // [0..(num_arch_switches-1)] std::map all_sw_inf; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 92100562dfb..635e4ffedfb 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1208,6 +1208,8 @@ struct t_router_opts { enum e_route_type route_type; int fixed_channel_width; int min_channel_width_hint; /// switchblocks; + /* Xifan Tang: subtype of switch blocks. + * Sub type and Fs are applied to pass tracks + */ + int subFs; + enum e_switch_block_type switch_block_subtype; + + /* Xifan Tang: tileable routing */ + bool tileable; + bool perimeter_cb; + bool shrink_boundary; + bool through_channel; + bool opin2all_sides; + bool concat_wire; + bool concat_pass_wire; + short global_route_switch; short delayless_switch; int wire_to_arch_ipin_switch; diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 8e59103cef9..c6d42b0d731 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -920,6 +920,9 @@ static void power_usage_routing(t_power_usage* power_usage, int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_id)].seg_index; C_wire = wire_length * rr_graph.rr_segments(RRSegmentId(seg_index)).Cmetal; //(double)power_ctx.commonly_used->tile_length); + if (node_fan_in == 0) { + continue; // Bypass some nodes with 0 fan-in + } VTR_ASSERT(node_power->selected_input < node_fan_in); /* Multiplexor */ diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index 096a87c787d..36fe4613ab7 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -355,7 +355,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { case OPIN: from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); - if (to_type == CHANX || to_type == CHANY) { + if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { num_adj += 1; //adjacent } else if (is_flat) { VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster @@ -430,6 +430,8 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } } else if (to_type == CHANY) { num_adj += chanx_chany_adjacent(from_node, to_node); + } else if (to_type == MEDIUM) { + num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_adjacent: %d and %d are not adjacent", from_node, to_node); @@ -462,12 +464,28 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) { } } else if (to_type == CHANX) { num_adj += chanx_chany_adjacent(to_node, from_node); + } else if (to_type == MEDIUM) { + num_adj += 1; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_adjacent: %d and %d are not adjacent", from_node, to_node); } break; + case MEDIUM: + //from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer}); + if (to_type == CHANX || to_type == CHANY || to_type == MEDIUM) { + num_adj += 1; //adjacent + } else if (is_flat) { + VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster + return true; + } else { + VTR_ASSERT(to_type == IPIN); + num_adj += 1; + } + + break; + default: break; } @@ -605,6 +623,7 @@ static void check_node_and_range(RRNodeId inode, check_rr_node(device_ctx.rr_graph, device_ctx.rr_indexed_data, device_ctx.grid, + device_ctx.vib_grid, device_ctx.chan_width, route_type, size_t(inode), diff --git a/vpr/src/route/connection_router.cpp b/vpr/src/route/connection_router.cpp index ee80073c3c6..9f835095da6 100644 --- a/vpr/src/route/connection_router.cpp +++ b/vpr/src/route/connection_router.cpp @@ -1060,11 +1060,20 @@ static inline void update_router_stats(RouterStats* router_stats, router_stats->heap_pops++; } - if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { - auto node_type = rr_graph->node_type(rr_node_id); - VTR_ASSERT(node_type != NUM_RR_TYPES); + auto node_type = rr_graph->node_type(rr_node_id); + VTR_ASSERT(node_type != NUM_RR_TYPES); - if (is_inter_cluster_node(*rr_graph, rr_node_id)) { + /* TODO: Eliminate the use of global var here!!! */ + const VibInf* vib; + if (!g_vpr_ctx.device().arch->vib_infs.empty()) { + vib = g_vpr_ctx.device().vib_grid.get_vib(rr_graph->node_layer(rr_node_id), rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id)); + } + else { + vib = nullptr; + } + if constexpr (VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR) { + t_physical_tile_type_ptr physical_type = g_vpr_ctx.device().grid.get_physical_type({rr_graph->node_xlow(rr_node_id), rr_graph->node_ylow(rr_node_id), rr_graph->node_layer(rr_node_id)}); + if (is_inter_cluster_node(physical_type, vib, node_type, rr_graph->node_ptc_num(rr_node_id))) { if (is_push) { router_stats->inter_cluster_node_pushes++; router_stats->inter_cluster_node_type_cnt_pushes[node_type]++; diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 92c421eccbd..345f8b7e46d 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -235,8 +235,18 @@ static void report_overused_ipin_opin(std::ostream& os, grid_x == rr_graph.node_xhigh(node_id) && grid_y == rr_graph.node_yhigh(node_id), "Non-track RR node should not span across multiple grid blocks."); + t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({grid_x, grid_y, grid_layer}); + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { + vib = device_ctx.vib_grid.get_vib(grid_layer, grid_x, grid_y); + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[grid_layer][grid_x][grid_y]; os << "Pin physical number = " << rr_graph.node_pin_num(node_id) << '\n'; - if (is_inter_cluster_node(rr_graph, node_id)) { + if (is_inter_cluster_node(physical_tile, vib, rr_graph.node_type(node_id), rr_graph.node_ptc_num(node_id))) { + os << "On Tile Pin" << "\n"; } else { diff --git a/vpr/src/route/route.cpp b/vpr/src/route/route.cpp index a237c5368ff..2ed747eff57 100644 --- a/vpr/src/route/route.cpp +++ b/vpr/src/route/route.cpp @@ -41,6 +41,10 @@ bool route(const Netlist<>& net_list, graph_directionality = GRAPH_BIDIR; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + /* Branch on tileable routing */ + if (det_routing_arch->directionality == UNI_DIRECTIONAL && det_routing_arch->tileable) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } graph_directionality = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); } diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 6eb515ccb71..2fa61c1ca23 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -257,6 +257,9 @@ void alloc_routing_structs(const t_chan_width& chan_width, graph_type = GRAPH_GLOBAL; } else { graph_type = (det_routing_arch->directionality == BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR); + if ((UNI_DIRECTIONAL == det_routing_arch->directionality) && (true == det_routing_arch->tileable)) { + graph_type = GRAPH_UNIDIR_TILEABLE; + } } create_rr_graph(graph_type, diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 621690f3bac..e46745f9671 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -200,6 +200,14 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI t_physical_tile_type_ptr from_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node), rr_graph.node_layer(current_node)}); + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(current_node), rr_graph.node_xlow(current_node), rr_graph.node_ylow(current_node)); + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(current_node)][rr_graph.node_xlow(current_node)][rr_graph.node_ylow(current_node)]; int from_node_ptc_num = rr_graph.node_ptc_num(current_node); t_physical_tile_type_ptr to_physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(target_node), rr_graph.node_ylow(target_node), @@ -220,7 +228,12 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost; } else if (from_rr_type == OPIN) { - if (is_inter_cluster_node(rr_graph, current_node)) { + + if (is_inter_cluster_node(from_physical_type, + vib, + from_rr_type, + from_node_ptc_num)) { + // Similar to CHANX and CHANY std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream); @@ -730,7 +743,9 @@ static void compute_tile_lookahead(std::unordered_map& rr_nodes_at_loc = device_ctx.rr_graph.node_lookup().find_grid_nodes_at_all_sides(sample_loc.layer_num, sample_loc.x, sample_loc.y, rr_type); for (RRNodeId node_id : rr_nodes_at_loc) { int ptc = rr_graph.node_ptc_num(node_id); + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { + vib = device_ctx.vib_grid.get_vib(sample_loc.layer_num, sample_loc.x, sample_loc.y); + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[sample_loc.layer_num][sample_loc.x][sample_loc.y]; // For the time being, we decide to not let the lookahead explore the node inside the clusters - if (!is_inter_cluster_node(rr_graph, node_id)) { + + if (!is_inter_cluster_node(&device_ctx.physical_tile_types[itile], + vib, + rr_type, + ptc)) { + continue; } @@ -1011,7 +1024,7 @@ static void dijkstra_flood_to_wires(int itile, src_opin_delays[root_layer_num][itile][ptc][curr_layer_num][seg_index].congestion = curr.congestion; } - } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN) { + } else if (curr_rr_type == SOURCE || curr_rr_type == OPIN || curr_rr_type == IPIN || curr_rr_type == MEDIUM) { //We allow expansion through SOURCE/OPIN/IPIN types auto cost_index = rr_graph.node_cost_index(curr.node); float incr_cong = device_ctx.rr_indexed_data[cost_index].base_cost; //Current nodes congestion cost @@ -1023,7 +1036,22 @@ static void dijkstra_flood_to_wires(int itile, RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge); // For the time being, we decide to not let the lookahead explore the node inside the clusters - if (!is_inter_cluster_node(rr_graph, next_node)) { + t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(next_node), + rr_graph.node_ylow(next_node), + rr_graph.node_layer(next_node)}); + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(next_node), rr_graph.node_xlow(next_node), rr_graph.node_ylow(next_node)); + } + else { + vib = nullptr; + } + //const t_vib_inf* vib = device_ctx.vib_grid[rr_graph.node_layer(next_node)][rr_graph.node_xlow(next_node)][rr_graph.node_ylow(next_node)]; + if (!is_inter_cluster_node(physical_type, + vib, + rr_graph.node_type(next_node), + rr_graph.node_ptc_num(next_node))) { + // Don't go inside the clusters continue; } @@ -1378,8 +1406,22 @@ static void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, for (t_edge_size edge : rr_graph.edges(parent)) { RRNodeId child_node = rr_graph.edge_sink_node(parent, edge); // For the time being, we decide to not let the lookahead explore the node inside the clusters + t_physical_tile_type_ptr physical_type = device_ctx.grid.get_physical_type({rr_graph.node_xlow(child_node), + rr_graph.node_ylow(child_node), + rr_graph.node_layer(child_node)}); + const VibInf* vib; + if (!device_ctx.arch->vib_infs.empty()) { + vib = device_ctx.vib_grid.get_vib(rr_graph.node_layer(child_node), rr_graph.node_xlow(child_node), rr_graph.node_ylow(child_node)); + } + else { + vib = nullptr; + } + + if (!is_inter_cluster_node(physical_type, + vib, + rr_graph.node_type(child_node), + rr_graph.node_ptc_num(child_node))) { - if (!is_inter_cluster_node(rr_graph, child_node)) { continue; } int switch_ind = size_t(rr_graph.edge_switch(parent, edge)); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index b8fb440a172..7eafe62e396 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -35,6 +35,7 @@ #include "rr_graph_clock.h" #include "edge_groups.h" #include "rr_graph_builder.h" +#include "tileable_rr_graph_builder.h" #include "rr_types.h" #include "echo_files.h" @@ -54,16 +55,6 @@ struct t_mux_size_distribution { t_mux_size_distribution* next; }; -struct t_clb_to_clb_directs { - t_physical_tile_type_ptr from_clb_type; - int from_clb_pin_start_index; - int from_clb_pin_end_index; - t_physical_tile_type_ptr to_clb_type; - int to_clb_pin_start_index; - int to_clb_pin_end_index; - int switch_index; //The switch type used by this direct connection -}; - struct t_pin_loc { int pin_index; int width_offset; @@ -585,14 +576,6 @@ void uniquify_edges(t_rr_edge_info_set& rr_edges_to_create); void alloc_and_load_edges(RRGraphBuilder& rr_graph_builder, const t_rr_edge_info_set& rr_edges_to_create); -static void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, - std::vector>& switch_fanin_remap, - const std::map arch_sw_inf, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch); - static void remap_rr_node_switch_indices(RRGraphBuilder& rr_graph_builder, const t_arch_switch_fanin& switch_fanin); @@ -607,27 +590,9 @@ static void alloc_rr_switch_inf(RRGraphBuilder& rr_graph_builder, t_arch_switch_fanin& arch_switch_fanins, const std::map& arch_sw_map); -static void rr_graph_externals(const std::vector& segment_inf, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type); - -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); - static t_seg_details* alloc_and_load_global_route_seg_details(const int global_route_switch, int* num_seg_details = nullptr); -static std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped, - bool is_flat); - static RRNodeId pick_best_direct_connect_target_rr_node(const RRGraphView& rr_graph, RRNodeId from_rr, const std::vector& candidate_rr_nodes); @@ -823,28 +788,55 @@ void create_rr_graph(const t_graph_type graph_type, } } else { free_rr_graph(); - build_rr_graph(graph_type, - block_types, - grid, - nodes_per_chan, - det_routing_arch->switch_block_type, - det_routing_arch->Fs, - det_routing_arch->switchblocks, - segment_inf, - det_routing_arch->global_route_switch, - det_routing_arch->wire_to_arch_ipin_switch, - det_routing_arch->wire_to_arch_ipin_switch_between_dice, - router_opts.custom_3d_sb_fanin_fanout, - det_routing_arch->delayless_switch, - det_routing_arch->R_minW_nmos, - det_routing_arch->R_minW_pmos, - router_opts.base_cost_type, - router_opts.clock_modeling, - directs, - &det_routing_arch->wire_to_rr_ipin_switch, - is_flat, - Warnings, - router_opts.route_verbosity); + if (GRAPH_UNIDIR_TILEABLE != graph_type) { + build_rr_graph(graph_type, + block_types, + grid, + nodes_per_chan, + det_routing_arch->switch_block_type, + det_routing_arch->Fs, + det_routing_arch->switchblocks, + segment_inf, + det_routing_arch->global_route_switch, + det_routing_arch->wire_to_arch_ipin_switch, + det_routing_arch->wire_to_arch_ipin_switch_between_dice, + router_opts.custom_3d_sb_fanin_fanout, + det_routing_arch->delayless_switch, + det_routing_arch->R_minW_nmos, + det_routing_arch->R_minW_pmos, + router_opts.base_cost_type, + router_opts.clock_modeling, + directs, + &det_routing_arch->wire_to_rr_ipin_switch, + is_flat, + Warnings, + router_opts.route_verbosity); + } else { + /* We do not support dedicated network for clocks in tileable rr_graph generation */ + VTR_LOG_WARN("Tileable routing resource graph does not support clock modeling yet! Related options are ignored...\n"); + build_tileable_unidir_rr_graph(block_types, + grid, + nodes_per_chan, + det_routing_arch->switch_block_type, + det_routing_arch->Fs, + det_routing_arch->switch_block_subtype, + det_routing_arch->subFs, + segment_inf, + det_routing_arch->delayless_switch, + det_routing_arch->wire_to_arch_ipin_switch, + det_routing_arch->R_minW_nmos, + det_routing_arch->R_minW_pmos, + router_opts.base_cost_type, + directs, + &det_routing_arch->wire_to_rr_ipin_switch, + det_routing_arch->shrink_boundary, /* Shrink to the smallest boundary, no routing wires for empty zone */ + det_routing_arch->perimeter_cb, /* Now I/O or any programmable blocks on perimeter can have full cb access (both cbx and cby) */ + router_opts.trim_obs_channels || det_routing_arch->through_channel, /* Allow/Prohibit through tracks across multi-height and multi-width grids */ + det_routing_arch->opin2all_sides, /* Allow opin of grid to directly drive routing tracks at all sides of a switch block */ + det_routing_arch->concat_wire, /* Allow end-point tracks to be wired to a starting point track on the opposite in a switch block. It means a wire can be continued in the same direction to another wire */ + det_routing_arch->concat_pass_wire, /* Allow passing tracks to be wired to the routing tracks in the same direction in a switch block. It means that a pass wire can jump in the same direction to another */ + Warnings); + } } } @@ -862,6 +854,7 @@ void create_rr_graph(const t_graph_type graph_type, is_flat, load_rr_graph); + /* Reorder nodes upon needs in algorithms and router options */ if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) { mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm, router_opts.reorder_rr_graph_nodes_threshold, @@ -1538,11 +1531,13 @@ static void build_rr_graph(const t_graph_type graph_type, device_ctx.chan_width = nodes_per_chan; rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, *wire_to_rr_ipin_switch, base_cost_type); - + + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grid, + vib_grid, device_ctx.chan_width, graph_type, is_flat); @@ -1633,10 +1628,12 @@ static void build_intra_cluster_rr_graph(const t_graph_type graph_type, rr_graph_builder.clear_temp_storage(); + const VibDeviceGrid vib_grid; check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grid, + vib_grid, device_ctx.chan_width, graph_type, is_flat); @@ -1717,13 +1714,13 @@ void build_tile_rr_graph(RRGraphBuilder& rr_graph_builder, * and count how many different fan-ins exist for each arch switch. * Then we create these rr switches and update the switch indices * of rr_nodes to index into the rr_switch_inf array. */ -static void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, - std::vector>& switch_fanin_remap, - const std::map arch_sw_inf, - const float R_minW_nmos, - const float R_minW_pmos, - const int wire_to_arch_ipin_switch, - int* wire_to_rr_ipin_switch) { +void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, + std::vector>& switch_fanin_remap, + const std::map arch_sw_inf, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch) { /* we will potentially be creating a couple of versions of each arch switch where * each version corresponds to a different fan-in. We will need to fill device_ctx.rr_switch_inf * with this expanded list of switches. @@ -1905,11 +1902,11 @@ static void remap_rr_node_switch_indices(RRGraphBuilder& rr_graph_builder, rr_graph_builder.remap_rr_node_switch_indices(switch_fanin); } -static void rr_graph_externals(const std::vector& segment_inf, - const std::vector& segment_inf_x, - const std::vector& segment_inf_y, - int wire_to_rr_ipin_switch, - enum e_base_cost_type base_cost_type) { +void rr_graph_externals(const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type) { auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; const auto& grid = device_ctx.grid; @@ -2007,15 +2004,15 @@ static t_seg_details* alloc_and_load_global_route_seg_details(const int global_r } /* Calculates the number of track connections from each block pin to each segment type */ -static std::vector> alloc_and_load_actual_fc(const std::vector& types, - const int max_pins, - const std::vector& segment_inf, - const int* sets_per_seg_type, - const t_chan_width* nodes_per_chan, - const e_fc_type fc_type, - const enum e_directionality directionality, - bool* Fc_clipped, - bool is_flat) { +std::vector> alloc_and_load_actual_fc(const std::vector& types, + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped, + bool is_flat) { //Initialize Fc of all blocks to zero auto zeros = vtr::Matrix({size_t(max_pins), segment_inf.size()}, 0); std::vector> Fc(types.size(), zeros); @@ -2799,6 +2796,8 @@ void free_rr_graph() { device_ctx.rr_graph_builder.clear(); + device_ctx.rr_node_track_ids.clear(); + device_ctx.rr_indexed_data.clear(); device_ctx.switch_fanin_remap.clear(); @@ -4341,7 +4340,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, * This data structure supplements the the info in the "directs" data structure * TODO: The function that does this parsing in placement is poorly done because it lacks generality on heterogeniety, should replace with this one */ -static t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, int delayless_switch) { t_clb_to_clb_directs* clb_to_clb_directs; t_physical_tile_type_ptr physical_tile = nullptr; t_physical_tile_port tile_port; diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index b0b3b7d1f00..0d074f95bb8 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -10,6 +10,7 @@ #include "vpr_types.h" #include "rr_graph_type.h" #include "describe_rr_node.h" +#include "clb2clb_directs.h" /* Warnings about the routing graph that can be returned. * This is to avoid output messages during a value sweep */ @@ -46,6 +47,33 @@ void free_rr_graph(); t_rr_switch_inf create_rr_switch_from_arch_switch(const t_arch_switch_inf& arch_sw_inf, const float R_minW_nmos, const float R_minW_pmos); + +void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, + std::vector>& switch_fanin_remap, + const std::map arch_sw_inf, + const float R_minW_nmos, + const float R_minW_pmos, + const int wire_to_arch_ipin_switch, + int* wire_to_rr_ipin_switch); + +void rr_graph_externals(const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + int wire_to_rr_ipin_switch, + enum e_base_cost_type base_cost_type); + +t_clb_to_clb_directs* alloc_and_load_clb_to_clb_directs(const std::vector& directs, const int delayless_switch); + +std::vector> alloc_and_load_actual_fc(const std::vector& types, + const int max_pins, + const std::vector& segment_inf, + const int* sets_per_seg_type, + const t_chan_width* nodes_per_chan, + const e_fc_type fc_type, + const enum e_directionality directionality, + bool* Fc_clipped, + bool is_flat); + // Sets the spec for the rr_switch based on the arch switch void load_rr_switch_from_arch_switch(RRGraphBuilder& rr_graph_builder, const std::map& arch_sw_inf, diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 755428a8780..62d539765dc 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -1705,8 +1705,10 @@ bool verify_rr_node_indices(const DeviceGrid& grid, y, describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str()); } - } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + + } else if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { // Sources have co-ordinates covering the entire block they are in, but not sinks + if (!rr_graph.x_in_node_range(x, inode)) { VPR_ERROR(VPR_ERROR_ROUTE, "RR node x positions do not agree between rr_nodes (%d <-> %d) and rr_node_indices (%d): %s", rr_graph.node_xlow(inode), @@ -1773,7 +1775,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid, auto& rr_node = rr_nodes[size_t(inode)]; - if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK) { + if (rr_graph.node_type(inode) == SOURCE || rr_graph.node_type(inode) == SINK || rr_graph.node_type(inode) == MEDIUM) { int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1); int rr_height = (rr_graph.node_yhigh(rr_node.id()) - rr_graph.node_ylow(rr_node.id()) + 1); int rr_area = rr_width * rr_height; diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp index 110f056c906..06b1c5e512d 100644 --- a/vpr/src/route/rr_graph_area.cpp +++ b/vpr/src/route/rr_graph_area.cpp @@ -377,6 +377,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* from_rr_type = rr_graph.node_type(from_rr_node); switch (from_rr_type) { + case MEDIUM: case CHANX: case CHANY: num_edges = rr_graph.num_edges(RRNodeId(from_node)); @@ -392,6 +393,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* } switch (to_rr_type) { + case MEDIUM: case CHANX: case CHANY: if (!chan_node_switch_done[size_t(to_node)]) { @@ -465,7 +467,7 @@ void count_unidir_routing_transistors(std::vector& /*segment_inf* for (i = rr_graph.node_xlow(from_rr_node); i <= rr_graph.node_xhigh(from_rr_node); i++) cblock_counted[i] = false; - } else { /* CHANY */ + } else if (from_rr_type == CHANY) { /* CHANY */ for (j = rr_graph.node_ylow(from_rr_node); j <= rr_graph.node_yhigh(from_rr_node); j++) cblock_counted[j] = false; diff --git a/vpr/src/tileable_rr_graph/chan_node_details.cpp b/vpr/src/tileable_rr_graph/chan_node_details.cpp new file mode 100644 index 00000000000..6d420464c3c --- /dev/null +++ b/vpr/src/tileable_rr_graph/chan_node_details.cpp @@ -0,0 +1,303 @@ +/************************************************************************ + * This file contains member functions for class ChanNodeDetails + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" + +#include "chan_node_details.h" + +/************************************************************************ + * Constructors + ***********************************************************************/ +ChanNodeDetails::ChanNodeDetails(const ChanNodeDetails& src) { + /* duplicate */ + size_t chan_width = src.get_chan_width(); + this->reserve(chan_width); + for (size_t itrack = 0; itrack < chan_width; ++itrack) { + track_node_ids_.push_back(src.get_track_node_id(itrack)); + track_direction_.push_back(src.get_track_direction(itrack)); + seg_ids_.push_back(src.get_track_segment_id(itrack)); + seg_length_.push_back(src.get_track_segment_length(itrack)); + track_start_.push_back(src.is_track_start(itrack)); + track_end_.push_back(src.is_track_end(itrack)); + } +} + +ChanNodeDetails::ChanNodeDetails() { + this->clear(); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +size_t ChanNodeDetails::get_chan_width() const { + VTR_ASSERT(validate_chan_width()); + return track_node_ids_.size(); +} + +size_t ChanNodeDetails::get_track_node_id(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_node_ids_[track_id]; +} + +/* Return a copy of vector */ +std::vector ChanNodeDetails::get_track_node_ids() const { + std::vector copy; + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + copy.push_back(track_node_ids_[inode]); + } + return copy; +} + +Direction ChanNodeDetails::get_track_direction(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_direction_[track_id]; +} + +size_t ChanNodeDetails::get_track_segment_length(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return seg_length_[track_id]; +} + +size_t ChanNodeDetails::get_track_segment_id(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return seg_ids_[track_id]; +} + +bool ChanNodeDetails::is_track_start(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_start_[track_id]; +} + +bool ChanNodeDetails::is_track_end(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_end_[track_id]; +} + +size_t ChanNodeDetails::get_track_bend_start(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_bend_start_[track_id]; +} + +size_t ChanNodeDetails::get_track_bend_end(const size_t& track_id) const { + VTR_ASSERT(validate_track_id(track_id)); + return track_bend_end_[track_id]; +} + +/* Track_id is the starting point of group (whose is_start should be true) + * This function will try to find the track_ids with the same directionality as track_id and seg_length + * A group size is the number of such nodes between the starting points (include the 1st starting point) + */ +std::vector ChanNodeDetails::get_seg_group(const size_t& track_id) const { + VTR_ASSERT(validate_chan_width()); + VTR_ASSERT(validate_track_id(track_id)); + VTR_ASSERT(is_track_start(track_id)); + + std::vector group; + /* Make sure a clean start */ + group.clear(); + + for (size_t itrack = track_id; itrack < get_chan_width(); ++itrack) { + if ((get_track_direction(itrack) != get_track_direction(track_id)) + || (get_track_segment_id(itrack) != get_track_segment_id(track_id))) { + /* Bypass any nodes in different direction and segment information*/ + continue; + } + if ((false == is_track_start(itrack)) + || ((true == is_track_start(itrack)) && (itrack == track_id))) { + group.push_back(itrack); + continue; + } + /* Stop if this another starting point */ + if (true == is_track_start(itrack)) { + break; + } + } + return group; +} + +/* Get a list of track_ids with the given list of track indices */ +std::vector ChanNodeDetails::get_seg_group_node_id(const std::vector& seg_group) const { + std::vector group; + /* Make sure a clean start */ + group.clear(); + + for (size_t id = 0; id < seg_group.size(); ++id) { + VTR_ASSERT(validate_track_id(seg_group[id])); + group.push_back(get_track_node_id(seg_group[id])); + } + + return group; +} + +/* Get the number of tracks that starts in this routing channel */ +size_t ChanNodeDetails::get_num_starting_tracks(const Direction& track_direction) const { + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_start(itrack)) { + continue; + } + counter++; + } + return counter; +} + +/* Get the number of tracks that ends in this routing channel */ +size_t ChanNodeDetails::get_num_ending_tracks(const Direction& track_direction) const { + size_t counter = 0; + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass unmatched track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + if (false == is_track_end(itrack)) { + continue; + } + counter++; + } + return counter; +} + +/************************************************************************ + * Mutators + ***********************************************************************/ +/* Reserve the capacitcy of vectors */ +void ChanNodeDetails::reserve(const size_t& chan_width) { + track_node_ids_.reserve(chan_width); + track_direction_.reserve(chan_width); + seg_length_.reserve(chan_width); + seg_ids_.reserve(chan_width); + track_start_.reserve(chan_width); + track_end_.reserve(chan_width); +} + +/* Add a track to the channel */ +void ChanNodeDetails::add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end, const size_t& seg_bend_start, const size_t& seg_bend_end) { + track_node_ids_.push_back(track_node_id); + track_direction_.push_back(track_direction); + seg_ids_.push_back(seg_id); + seg_length_.push_back(seg_length); + track_start_.push_back(is_start); + track_end_.push_back(is_end); + track_bend_start_.push_back(seg_bend_start); + track_bend_end_.push_back(seg_bend_end); +} + +/* Update the node_id of a given track */ +void ChanNodeDetails::set_track_node_id(const size_t& track_index, const size_t& track_node_id) { + VTR_ASSERT(validate_track_id(track_index)); + track_node_ids_[track_index] = track_node_id; +} + +/* Update the node_ids from a vector */ +void ChanNodeDetails::set_track_node_ids(const std::vector& track_node_ids) { + /* the size of vector should match chan_width */ + VTR_ASSERT(get_chan_width() == track_node_ids.size()); + for (size_t inode = 0; inode < track_node_ids.size(); ++inode) { + track_node_ids_[inode] = track_node_ids[inode]; + } +} + +/* Set tracks with a given direction to start */ +void ChanNodeDetails::set_tracks_start(const Direction& track_direction) { + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_start_[inode] = true; + } +} + +/* Set tracks with a given direction to end */ +void ChanNodeDetails::set_tracks_end(const Direction& track_direction) { + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Bypass non-match tracks */ + if (track_direction != get_track_direction(inode)) { + continue; /* Pass condition*/ + } + track_end_[inode] = true; + } +} + +/* rotate the track_node_id by an offset */ +void ChanNodeDetails::rotate_track_node_id(const size_t& offset, const Direction& track_direction, const bool& counter_rotate) { + /* Direct return if offset = 0*/ + if (0 == offset) { + return; + } + + /* Rotate the node_ids by groups + * A group begins from a track_start and ends before another track_start + */ + VTR_ASSERT(validate_chan_width()); + for (size_t itrack = 0; itrack < get_chan_width(); ++itrack) { + /* Bypass non-start segment */ + if (false == is_track_start(itrack)) { + continue; + } + /* Bypass segments do not match track_direction */ + if (track_direction != get_track_direction(itrack)) { + continue; + } + /* Find the group nodes */ + std::vector track_group = get_seg_group(itrack); + /* Build a vector of the node ids of the tracks */ + std::vector track_group_node_id = get_seg_group_node_id(track_group); + /* adapt offset to the range of track_group_node_id */ + size_t actual_offset = offset % track_group_node_id.size(); + /* Rotate or Counter rotate */ + if (true == counter_rotate) { + std::rotate(track_group_node_id.rbegin(), track_group_node_id.rbegin() + actual_offset, track_group_node_id.rend()); + } else { + std::rotate(track_group_node_id.begin(), track_group_node_id.begin() + actual_offset, track_group_node_id.end()); + } + /* Update the node_ids */ + for (size_t inode = 0; inode < track_group.size(); ++inode) { + track_node_ids_[track_group[inode]] = track_group_node_id[inode]; + } + } + return; +} + +void ChanNodeDetails::clear() { + track_node_ids_.clear(); + track_direction_.clear(); + seg_ids_.clear(); + seg_length_.clear(); + track_start_.clear(); + track_end_.clear(); +} + +/************************************************************************ + * Validators + ***********************************************************************/ +bool ChanNodeDetails::validate_chan_width() const { + size_t chan_width = track_node_ids_.size(); + if ((chan_width == track_direction_.size()) + && (chan_width == seg_ids_.size()) + && (chan_width == seg_length_.size()) + && (chan_width == track_start_.size()) + && (chan_width == track_end_.size())) { + return true; + } + return false; +} + +bool ChanNodeDetails::validate_track_id(const size_t& track_id) const { + if ((track_id < track_node_ids_.size()) + && (track_id < track_direction_.size()) + && (track_id < seg_ids_.size()) + && (track_id < seg_length_.size()) + && (track_id < track_start_.size()) + && (track_id < track_end_.size())) { + return true; + } + return false; +} diff --git a/vpr/src/tileable_rr_graph/chan_node_details.h b/vpr/src/tileable_rr_graph/chan_node_details.h new file mode 100644 index 00000000000..6768f84ebf0 --- /dev/null +++ b/vpr/src/tileable_rr_graph/chan_node_details.h @@ -0,0 +1,77 @@ +#ifndef CHAN_NODE_DETAILS_H +#define CHAN_NODE_DETAILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "vpr_types.h" +#include "rr_node_types.h" +#include "rr_graph_types.h" + +/************************************************************************ + * This file contains a class to model the details of routing node + * in a channel: + * 1. segment information: length, frequency etc. + * 2. starting point of segment + * 3. ending point of segment + * 4. potentail track_id(ptc_num) of each segment + ***********************************************************************/ + +/************************************************************************ + * ChanNodeDetails records segment length, directionality and starting of routing tracks + * +---------------------------------+ + * | Index | Direction | Start Point | + * +---------------------------------+ + * | 0 | --------> | Yes | + * +---------------------------------+ + ***********************************************************************/ + +class ChanNodeDetails { + public: /* Constructor */ + ChanNodeDetails(const ChanNodeDetails&); /* Duplication */ + ChanNodeDetails(); /* Initilization */ + public: /* Accessors */ + size_t get_chan_width() const; + size_t get_track_node_id(const size_t& track_id) const; + std::vector get_track_node_ids() const; + Direction get_track_direction(const size_t& track_id) const; + size_t get_track_segment_length(const size_t& track_id) const; + size_t get_track_segment_id(const size_t& track_id) const; + bool is_track_start(const size_t& track_id) const; + bool is_track_end(const size_t& track_id) const; + size_t get_track_bend_start(const size_t& track_id) const; + size_t get_track_bend_end(const size_t& track_id) const; + std::vector get_seg_group(const size_t& track_id) const; + std::vector get_seg_group_node_id(const std::vector& seg_group) const; + size_t get_num_starting_tracks(const Direction& track_direction) const; + size_t get_num_ending_tracks(const Direction& track_direction) const; + + public: /* Mutators */ + void reserve(const size_t& chan_width); /* Reserve the capacitcy of vectors */ + void add_track(const size_t& track_node_id, const Direction& track_direction, const size_t& seg_id, const size_t& seg_length, const size_t& is_start, const size_t& is_end, const size_t& seg_bend_start = 0, const size_t& seg_bend_end = 0); + void set_track_node_id(const size_t& track_index, const size_t& track_node_id); + void set_track_node_ids(const std::vector& track_node_ids); + void set_tracks_start(const Direction& track_direction); + void set_tracks_end(const Direction& track_direction); + void rotate_track_node_id(const size_t& offset, + const Direction& track_direction, + const bool& counter_rotate); /* rotate the track_node_id by an offset */ + void clear(); + + private: /* validators */ + bool validate_chan_width() const; + bool validate_track_id(const size_t& track_id) const; + + private: /* Internal data */ + std::vector track_node_ids_; /* indices of each track */ + std::vector track_direction_; /* direction of each track */ + std::vector seg_ids_; /* id of segment of each track */ + std::vector seg_length_; /* Length of each segment */ + std::vector track_start_; /* flag to identify if this is the starting point of the track */ + std::vector track_end_; /* flag to identify if this is the ending point of the track */ + std::vector track_bend_start_; /* flag to identify if this is the starting point of the track after bend. 0 means it is not a bend start. Int number means the corresponding bend group */ + std::vector track_bend_end_; +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/clb2clb_directs.h b/vpr/src/tileable_rr_graph/clb2clb_directs.h new file mode 100644 index 00000000000..7cc54bb8813 --- /dev/null +++ b/vpr/src/tileable_rr_graph/clb2clb_directs.h @@ -0,0 +1,16 @@ +#ifndef CLB2CLB_DIRECTS_H +#define CLB2CLB_DIRECTS_H + +#include "physical_types.h" + +struct t_clb_to_clb_directs { + t_physical_tile_type_ptr from_clb_type; + int from_clb_pin_start_index; + int from_clb_pin_end_index; + t_physical_tile_type_ptr to_clb_type; + int to_clb_pin_start_index; + int to_clb_pin_end_index; + int switch_index; //The switch type used by this direct connection +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.cpp b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp new file mode 100644 index 00000000000..66ab365b42a --- /dev/null +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.cpp @@ -0,0 +1,106 @@ +#include "device_grid_annotation.h" +#include "vtr_log.h" +#include "vpr_utils.h" + +DeviceGridAnnotation::DeviceGridAnnotation(const DeviceGrid& grid, const bool& perimeter_cb) { + alloc(grid); + init(grid, perimeter_cb); +} + +void DeviceGridAnnotation::alloc(const DeviceGrid& grid) { + /* Allocate */ + chanx_existence_.resize({grid.width(), grid.height()}, false); + chany_existence_.resize({grid.width(), grid.height()}, false); +} + +void DeviceGridAnnotation::init(const DeviceGrid& grid, const bool& perimeter_cb) { + /* If shrink is not considered, perimeters are the borderlines */ + size_t start_x = 1; + size_t end_x = grid.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grid.width(); + } + for (size_t iy = 0; iy < grid.height() - 1; ++iy) { + for (size_t ix = start_x; ix < end_x; ++ix) { + chanx_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy + 1, 0})); + } + } + size_t start_y = 1; + size_t end_y = grid.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grid.height(); + } + for (size_t ix = 0; ix < grid.width() - 1; ++ix) { + for (size_t iy = start_y; iy < end_y; ++iy) { + chany_existence_[ix][iy] = !is_empty_type(grid.get_physical_type({(int)ix, (int)iy, 0})); + } + } +} + +bool DeviceGridAnnotation::is_chanx_exist(const vtr::Point& coord) const { + return chanx_existence_[coord.x()][coord.y()]; +} + +bool DeviceGridAnnotation::is_chany_exist(const vtr::Point& coord) const { + return chany_existence_[coord.x()][coord.y()]; +} + +bool DeviceGridAnnotation::is_chanx_start(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, LEFT); + if (neighbor_coord == coord) { + return true; + } + return chanx_existence_[coord.x()][coord.y()] != chanx_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +bool DeviceGridAnnotation::is_chanx_end(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, RIGHT); + if (neighbor_coord == coord) { + return true; + } + return chanx_existence_[coord.x()][coord.y()] != chanx_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +bool DeviceGridAnnotation::is_chany_start(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, BOTTOM); + if (neighbor_coord == coord) { + return true; + } + return chany_existence_[coord.x()][coord.y()] != chany_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +bool DeviceGridAnnotation::is_chany_end(const vtr::Point& coord) const { + vtr::Point neighbor_coord = get_neighbor_coord(coord, TOP); + if (neighbor_coord == coord) { + return true; + } + return chany_existence_[coord.x()][coord.y()] != chany_existence_[neighbor_coord.x()][neighbor_coord.y()]; +} + +vtr::Point DeviceGridAnnotation::get_neighbor_coord(const vtr::Point& coord, const e_side& side) const { + vtr::Point neighbor_coord(coord.x(), coord.y()); + if (side == LEFT) { + if (coord.x() == 0) { + return coord; + } + neighbor_coord.set_x(coord.x() - 1); + } else if (side == RIGHT) { + if (coord.x() == chanx_existence_.dim_size(0) - 1) { + return coord; + } + neighbor_coord.set_x(coord.x() + 1); + } else if (side == TOP) { + if (coord.y() == chanx_existence_.dim_size(1) - 1) { + return coord; + } + neighbor_coord.set_y(coord.y() + 1); + } else if (side == BOTTOM) { + if (coord.y() == 0) { + return coord; + } + neighbor_coord.set_y(coord.y() - 1); + } + return neighbor_coord; +} diff --git a/vpr/src/tileable_rr_graph/device_grid_annotation.h b/vpr/src/tileable_rr_graph/device_grid_annotation.h new file mode 100644 index 00000000000..6f3f3bad343 --- /dev/null +++ b/vpr/src/tileable_rr_graph/device_grid_annotation.h @@ -0,0 +1,42 @@ +#ifndef DEVICE_GRID_ANNOTATION_H +#define DEVICE_GRID_ANNOTATION_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include +#include "vtr_geometry.h" +#include "vtr_ndmatrix.h" +#include "physical_types.h" +#include "device_grid.h" + +/** @brief This is the data structure to provide additional data for the device grid: + * - Border of the device grid (check where the empty types cover the perimeters) + */ +class DeviceGridAnnotation { + public: /* Constructor */ + DeviceGridAnnotation(const DeviceGrid& grid, const bool& perimeter_cb); + + private: /* Private mutators */ + void alloc(const DeviceGrid& grid); + void init(const DeviceGrid& grid, const bool& perimeter_cb); + + public: /* Public accessors */ + /** @brief Check if at a given coordinate, a X-direction routing channel should exist or not */ + bool is_chanx_exist(const vtr::Point& coord) const; + bool is_chanx_start(const vtr::Point& coord) const; + bool is_chanx_end(const vtr::Point& coord) const; + /** @brief Check if at a given coordinate, a Y-direction routing channel should exist or not */ + bool is_chany_exist(const vtr::Point& coord) const; + bool is_chany_start(const vtr::Point& coord) const; + bool is_chany_end(const vtr::Point& coord) const; + + private: /* Private validators */ + vtr::Point get_neighbor_coord(const vtr::Point& coord, const e_side& side) const; + + private: /* Internal data */ + vtr::NdMatrix chanx_existence_; + vtr::NdMatrix chany_existence_; +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp new file mode 100644 index 00000000000..a73ff2f15d5 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.cpp @@ -0,0 +1,201 @@ +/******************************************************************** + * This file includes most utilized functions for the rr_graph + * data structure in the OpenFPGA context + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "openfpga_rr_graph_utils.h" +#include "rr_graph_types.h" +#include "rr_graph_view.h" +#include "vtr_geometry.h" + +/************************************************************************ + * Get the coordinator of a starting point of a routing track + * For routing tracks in INC_DIRECTION + * (xlow, ylow) should be the starting point + * + * For routing tracks in DEC_DIRECTION + * (xhigh, yhigh) should be the starting point + ***********************************************************************/ +vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, + const RRNodeId& track_rr_node) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + vtr::Point start_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + start_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + start_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } + + return start_coordinator; +} + +/************************************************************************ + * Get the coordinator of a end point of a routing track + * For routing tracks in INC_DIRECTION + * (xhigh, yhigh) should be the starting point + * + * For routing tracks in DEC_DIRECTION + * (xlow, ylow) should be the starting point + ***********************************************************************/ +vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, + const RRNodeId& track_rr_node) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + vtr::Point end_coordinator; + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + end_coordinator.set(rr_graph.node_xhigh(track_rr_node), rr_graph.node_yhigh(track_rr_node)); + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + end_coordinator.set(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + } + + return end_coordinator; +} + +/************************************************************************ + * Find the driver switches for a node in the rr_graph + * This function only return unique driver switches + ***********************************************************************/ +std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph, + const RRNodeId& node) { + std::vector driver_switches; + + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + if (driver_switches.end() == std::find(driver_switches.begin(), driver_switches.end(), rr_graph.edge_switch(edge))) { + driver_switches.push_back(rr_graph.edge_switch(edge)); + } + } + + return driver_switches; +} + +/************************************************************************ + * Find the driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Find the configurable driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass non-configurable edges */ + if (false == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Find the configurable driver nodes for a node in the rr_graph + ***********************************************************************/ +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node) { + std::vector driver_nodes; + + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + /* Bypass configurable edges */ + if (true == rr_graph.edge_is_configurable(edge)) { + continue; + } + driver_nodes.push_back(rr_graph.edge_src_node(edge)); + } + + return driver_nodes; +} + +/************************************************************************ + * Check if an OPIN of a rr_graph is directly driving an IPIN + * To meet this requirement, the OPIN must: + * - Have only 1 fan-out + * - The only fan-out is an IPIN + ***********************************************************************/ +bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, + const RRNodeId& node) { + /* We only accept OPIN */ + VTR_ASSERT(OPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_out_edges(node).size()) { + return false; + } + + VTR_ASSERT(1 == rr_graph.node_out_edges(node).size()); + for (auto edge : rr_graph.node_out_edges(node)) { + const RRNodeId& sink_node = rr_graph.edge_sink_node(node, edge); + if (IPIN != rr_graph.node_type(sink_node)) { + return false; + } + } + + return true; +} + +/************************************************************************ + * Check if an IPIN of a rr_graph is directly connected to an OPIN + * To meet this requirement, the IPIN must: + * - Have only 1 fan-in + * - The only fan-in is an OPIN + ***********************************************************************/ +bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, + const RRNodeId& node) { + /* We only accept IPIN */ + VTR_ASSERT(IPIN == rr_graph.node_type(node)); + + if (1 != rr_graph.node_in_edges(node).size()) { + return false; + } + + VTR_ASSERT(1 == rr_graph.node_in_edges(node).size()); + for (const RREdgeId& edge : rr_graph.node_in_edges(node)) { + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + if (OPIN != rr_graph.node_type(src_node)) { + return false; + } + } + + return true; +} + +/** @brief Get a side of a given node in a routing resource graph. + * Note that this function expect one valid side to be got. Otherwise, it will fail! */ +e_side get_rr_graph_single_node_side(const RRGraphView& rr_graph, + const RRNodeId& node) { + e_side node_side = NUM_2D_SIDES; + int num_sides = 0; + for (e_side candidate_side : TOTAL_2D_SIDES) { + if (rr_graph.is_node_on_specific_side(node, candidate_side)) { + node_side = candidate_side; + num_sides++; + } + } + VTR_ASSERT(1 == num_sides && node_side != NUM_2D_SIDES); + return node_side; +} diff --git a/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h new file mode 100644 index 00000000000..cba64125615 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_rr_graph_utils.h @@ -0,0 +1,45 @@ +#ifndef OPENFPGA_RR_GRAPH_UTILS_H +#define OPENFPGA_RR_GRAPH_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from vpr library */ +#include "rr_graph_obj.h" +#include "rr_graph_view.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +vtr::Point get_track_rr_node_start_coordinate(const RRGraphView& rr_graph, + const RRNodeId& track_rr_node); + +vtr::Point get_track_rr_node_end_coordinate(const RRGraphView& rr_graph, + const RRNodeId& track_rr_node); + +std::vector get_rr_graph_driver_switches(const RRGraphView& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_configurable_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node); + +std::vector get_rr_graph_non_configurable_driver_nodes(const RRGraphView& rr_graph, + const RRNodeId& node); + +bool is_opin_direct_connected_ipin(const RRGraphView& rr_graph, + const RRNodeId& node); + +bool is_ipin_direct_connected_opin(const RRGraphView& rr_graph, + const RRNodeId& node); + +e_side get_rr_graph_single_node_side(const RRGraphView& rr_graph, + const RRNodeId& node); + +#endif diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp new file mode 100644 index 00000000000..ebef0dd0a9c --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.cpp @@ -0,0 +1,170 @@ +/******************************************************************** + * Memeber function for class SideManagerManager + *******************************************************************/ +#include "openfpga_side_manager.h" + +/* Constructors */ +SideManager::SideManager(enum e_side side) { + side_ = side; +} + +SideManager::SideManager() { + side_ = NUM_2D_SIDES; +} + +SideManager::SideManager(size_t side) { + set_side(side); +} + +/* Public Accessors */ +enum e_side SideManager::get_side() const { + return side_; +} + +enum e_side SideManager::get_opposite() const { + switch (side_) { + case TOP: + return BOTTOM; + case RIGHT: + return LEFT; + case BOTTOM: + return TOP; + case LEFT: + return RIGHT; + default: + return NUM_2D_SIDES; + } +} + +enum e_side SideManager::get_rotate_clockwise() const { + switch (side_) { + case TOP: + return RIGHT; + case RIGHT: + return BOTTOM; + case BOTTOM: + return LEFT; + case LEFT: + return TOP; + default: + return NUM_2D_SIDES; + } +} + +enum e_side SideManager::get_rotate_counterclockwise() const { + switch (side_) { + case TOP: + return LEFT; + case RIGHT: + return TOP; + case BOTTOM: + return RIGHT; + case LEFT: + return BOTTOM; + default: + return NUM_2D_SIDES; + } +} + +bool SideManager::validate() const { + if (NUM_2D_SIDES == side_) { + return false; + } + return true; +} + +size_t SideManager::to_size_t() const { + switch (side_) { + case TOP: + return 0; + case RIGHT: + return 1; + case BOTTOM: + return 2; + case LEFT: + return 3; + default: + return 4; + } +} + +/* Convert to char* */ +const char* SideManager::c_str() const { + switch (side_) { + case TOP: + return "top"; + case RIGHT: + return "right"; + case BOTTOM: + return "bottom"; + case LEFT: + return "left"; + default: + return "invalid_side"; + } +} + +/* Convert to char* */ +std::string SideManager::to_string() const { + std::string ret; + switch (side_) { + case TOP: + ret.assign("top"); + break; + case RIGHT: + ret.assign("right"); + break; + case BOTTOM: + ret.assign("bottom"); + break; + case LEFT: + ret.assign("left"); + break; + default: + ret.assign("invalid_side"); + break; + } + + return ret; +} + +/* Public Mutators */ +void SideManager::set_side(size_t side) { + switch (side) { + case 0: + side_ = TOP; + return; + case 1: + side_ = RIGHT; + return; + case 2: + side_ = BOTTOM; + return; + case 3: + side_ = LEFT; + return; + default: + side_ = NUM_2D_SIDES; + return; + } +} + +void SideManager::set_side(enum e_side side) { + side_ = side; + return; +} + +void SideManager::set_opposite() { + side_ = get_opposite(); + return; +} + +void SideManager::rotate_clockwise() { + side_ = get_rotate_clockwise(); + return; +} + +void SideManager::rotate_counterclockwise() { + side_ = get_rotate_counterclockwise(); + return; +} diff --git a/vpr/src/tileable_rr_graph/openfpga_side_manager.h b/vpr/src/tileable_rr_graph/openfpga_side_manager.h new file mode 100644 index 00000000000..a6eb265cd64 --- /dev/null +++ b/vpr/src/tileable_rr_graph/openfpga_side_manager.h @@ -0,0 +1,47 @@ +#ifndef OPENFPGA_SIDE_MANAGER_H +#define OPENFPGA_SIDE_MANAGER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include + +/* Header files form archfpga library */ +#include "physical_types.h" + +/******************************************************************** + * Define a class for the sides of a physical block in FPGA architecture + * Basically, each block has four sides : + * TOP, RIGHT, BOTTOM, LEFT + * This class aims to provide a easy proctol for manipulating a side + ********************************************************************/ + +class SideManager { + public: /* Constructor */ + SideManager(enum e_side side); + SideManager(); + SideManager(size_t side); + + public: /* Accessors */ + enum e_side get_side() const; + enum e_side get_opposite() const; + enum e_side get_rotate_clockwise() const; + enum e_side get_rotate_counterclockwise() const; + bool validate() const; + size_t to_size_t() const; + const char* c_str() const; + std::string to_string() const; + + public: /* Mutators */ + void set_side(size_t side); + void set_side(enum e_side side); + void set_opposite(); + void rotate_clockwise(); + void rotate_counterclockwise(); + + private: /* internal data */ + enum e_side side_; +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_chan.cpp b/vpr/src/tileable_rr_graph/rr_chan.cpp new file mode 100644 index 00000000000..c6a991ea524 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_chan.cpp @@ -0,0 +1,190 @@ +/************************************************************************ + * Member functions for class RRChan + ***********************************************************************/ +#include "vtr_log.h" +#include "vtr_assert.h" +#include "rr_chan.h" + +/************************************************************************ + * Constructors + ***********************************************************************/ +/* default constructor */ +RRChan::RRChan() { + type_ = NUM_RR_TYPES; + nodes_.resize(0); + node_segments_.resize(0); +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +t_rr_type RRChan::get_type() const { + return type_; +} + +/* get the number of tracks in this channel */ +size_t RRChan::get_chan_width() const { + return nodes_.size(); +} + +/* get the track_id of a node */ +int RRChan::get_node_track_id(const RRNodeId& node) const { + /* if the given node is NULL, we return an invalid id */ + if (RRNodeId::INVALID() == node) { + return -1; + } + /* check each member and return if we find a match in content */ + std::vector::const_iterator it = std::find(nodes_.begin(), nodes_.end(), node); + if (nodes_.end() == it) { + return -1; + } + return it - nodes_.begin(); +} + +/* get the rr_node with the track_id */ +RRNodeId RRChan::get_node(const size_t& track_num) const { + if (false == valid_node_id(track_num)) { + return RRNodeId::INVALID(); + } + return nodes_[track_num]; +} + +/* get the segment id of a node */ +RRSegmentId RRChan::get_node_segment(const RRNodeId& node) const { + int node_id = get_node_track_id(node); + if (false == valid_node_id(node_id)) { + return RRSegmentId::INVALID(); + } + return get_node_segment(node_id); +} + +/* get the segment id of a node */ +RRSegmentId RRChan::get_node_segment(const size_t& track_num) const { + if (false == valid_node_id(track_num)) { + return RRSegmentId::INVALID(); + } + return node_segments_[track_num]; +} + +/* Get a list of segments used in this routing channel */ +std::vector RRChan::get_segment_ids() const { + std::vector seg_list; + + /* make sure a clean start */ + seg_list.clear(); + + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + std::vector::iterator it; + /* Try to find the node_segment id in the list */ + it = find(seg_list.begin(), seg_list.end(), node_segments_[inode]); + if (it == seg_list.end()) { + /* Not found, add it to the list */ + seg_list.push_back(node_segments_[inode]); + } + } + + return seg_list; +} + +/* Get a list of nodes whose segment_id is specified */ +std::vector RRChan::get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const { + std::vector node_list; + + /* make sure a clean start */ + node_list.clear(); + + /* Traverse node_segments */ + for (size_t inode = 0; inode < get_chan_width(); ++inode) { + /* Try to find the node_segment id in the list */ + if (seg_id == node_segments_[inode]) { + node_list.push_back(inode); + } + } + + return node_list; +} + +/************************************************************************ + * Mutators + ***********************************************************************/ +void RRChan::set(const RRChan& rr_chan) { + /* Ensure a clean start */ + this->clear(); + /* Assign type of this routing channel */ + this->type_ = rr_chan.get_type(); + /* Copy node and node_segments */ + this->nodes_.resize(rr_chan.get_chan_width()); + this->node_segments_.resize(rr_chan.get_chan_width()); + for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { + this->nodes_[inode] = rr_chan.get_node(inode); + this->node_segments_[inode] = rr_chan.get_node_segment(inode); + } + return; +} + +/* modify type */ +void RRChan::set_type(const t_rr_type& type) { + VTR_ASSERT(valid_type(type)); + type_ = type; +} + +/* Reserve node list */ +void RRChan::reserve_node(const size_t& node_size) { + nodes_.reserve(node_size); /* reserve to the maximum */ + node_segments_.reserve(node_size); /* reserve to the maximum */ +} + +/* add a node to the array */ +void RRChan::add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment) { + /* fill the dedicated element in the vector */ + nodes_.push_back(node); + node_segments_.push_back(node_segment); + + if (NUM_RR_TYPES == type_) { + type_ = rr_graph.node_type(node); + } else { + VTR_ASSERT(type_ == rr_graph.node_type(node)); + } + + VTR_ASSERT(valid_node_type(rr_graph, node)); +} + +/* Clear content */ +void RRChan::clear() { + nodes_.clear(); + node_segments_.clear(); +} + +/************************************************************************ + * Internal validators + ***********************************************************************/ +/* for type, only valid type is CHANX and CHANY */ +bool RRChan::valid_type(const t_rr_type& type) const { + if ((CHANX == type) || (CHANY == type)) { + return true; + } + return false; +} + +/* Check each node, see if the node type is consistent with the type */ +bool RRChan::valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const { + valid_type(rr_graph.node_type(node)); + if (NUM_RR_TYPES == type_) { + return true; + } + valid_type(type_); + if (type_ != rr_graph.node_type(node)) { + return false; + } + return true; +} + +/* check if the node id is valid */ +bool RRChan::valid_node_id(const size_t& node_id) const { + if (node_id < nodes_.size()) { + return true; + } + + return false; +} diff --git a/vpr/src/tileable_rr_graph/rr_chan.h b/vpr/src/tileable_rr_graph/rr_chan.h new file mode 100644 index 00000000000..5ba9bc09af5 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_chan.h @@ -0,0 +1,83 @@ +#ifndef RR_CHAN_H +#define RR_CHAN_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from vpr library */ +#include "rr_graph_view.h" + +/******************************************************************** + * RRChan object aim to describe a routing channel in a routing resource graph + * - What are the nodes in the RRGraph object, for each routing track + * - What are routing segments used by each node in the channel + * - What are the directions of each routing channel + * being either X-direction or Y-direction + * + * Note : + * - This is a collection of rr_nodes from the RRGraph Object + * It does not rebuild or contruct any connects between rr_nodes + * It is just an annotation on an existing RRGraph + * ------------- ------ + * | | | | + * | | | Y | + * | CLB | | Chan | + * | | | | + * | | | | + * ------------- ------ + * ------------- + * | X | + * | Channel | + * ------------- + *******************************************************************/ +class RRChan { + public: /* Constructors */ + RRChan(); + + public: /* Accessors */ + t_rr_type get_type() const; + size_t get_chan_width() const; /* get the number of tracks in this channel */ + int get_node_track_id(const RRNodeId& node) const; /* get the track_id of a node */ + RRNodeId get_node(const size_t& track_num) const; /* get the rr_node with the track_id */ + RRSegmentId get_node_segment(const RRNodeId& node) const; + RRSegmentId get_node_segment(const size_t& track_num) const; + std::vector get_segment_ids() const; /* Get a list of segments used in this routing channel */ + std::vector get_node_ids_by_segment_ids(const RRSegmentId& seg_id) const; /* Get a list of segments used in this routing channel */ + public: /* Mutators */ + /* copy */ + void set(const RRChan&); + + /* modify the type of routing channel */ + void set_type(const t_rr_type& type); + + /* reseve a number of nodes to the array */ + void reserve_node(const size_t& node_size); + + /* add a node to the routing channel */ + void add_node(const RRGraphView& rr_graph, const RRNodeId& node, const RRSegmentId& node_segment); + + /* clear the content */ + void clear(); + + private: /* internal functions */ + /* For the type of a routing channel, only valid type is CHANX and CHANY */ + bool valid_type(const t_rr_type& type) const; + + /* Check each node, see if the node type is consistent with the type of routing channel */ + bool valid_node_type(const RRGraphView& rr_graph, const RRNodeId& node) const; + + /* Validate if the track number in the range */ + bool valid_node_id(const size_t& node_id) const; + + private: /* Internal Data */ + t_rr_type type_; /* channel type: CHANX or CHANY */ + std::vector nodes_; /* rr nodes of each track in the channel */ + std::vector node_segments_; /* segment of each track */ +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp new file mode 100644 index 00000000000..3b9e21bab9b --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp @@ -0,0 +1,652 @@ +/************************************************************************ + * This file contains most utilized functions for rr_graph builders + ***********************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "vpr_utils.h" + +#include "rr_graph_builder_utils.h" + +/************************************************************************ + * Correct number of routing channel width to be compatible to + * uni-directional routing architecture + ***********************************************************************/ +size_t find_unidir_routing_channel_width(const size_t& chan_width) { + size_t actual_chan_width = chan_width; + /* Correct the chan_width: it should be an even number */ + if (0 != actual_chan_width % 2) { + actual_chan_width++; /* increment it to be even */ + } + VTR_ASSERT(0 == actual_chan_width % 2); + + return actual_chan_width; +} + +/************************************************************************ + * Get the class index of a grid pin + ***********************************************************************/ +int get_grid_pin_class_index(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const int pin_index) { + /* check */ + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + VTR_ASSERT(pin_index < phy_tile_type->num_pins); + return phy_tile_type->pin_class[pin_index]; +} + +/* Deteremine the side of a io grid */ +std::vector determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const bool& perimeter_cb) { + std::vector pin_sides; + /* TOP side IO of FPGA */ + if (device_size.y() == grid_coordinate.y()) { + /* Such I/O has only bottom side pins */ + pin_sides.push_back(BOTTOM); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(LEFT); + pin_sides.push_back(RIGHT); + } + } else if (device_size.x() == grid_coordinate.x()) { /* RIGHT side IO of FPGA */ + /* Such I/O has only Left side pins */ + pin_sides.push_back(LEFT); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(TOP); + pin_sides.push_back(BOTTOM); + } + } else if (0 == grid_coordinate.y()) { /* BOTTOM side IO of FPGA */ + /* Such I/O has only Top side pins */ + pin_sides.push_back(TOP); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(LEFT); + pin_sides.push_back(RIGHT); + } + } else if (0 == grid_coordinate.x()) { /* LEFT side IO of FPGA */ + /* Such I/O has only Right side pins */ + pin_sides.push_back(RIGHT); + /* If cbs are allowed around boundary I/Os, add two more sides */ + if (perimeter_cb) { + pin_sides.push_back(TOP); + pin_sides.push_back(BOTTOM); + } + } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) { + /* I/O grid in the center grid */ + return {TOP, RIGHT, BOTTOM, LEFT}; + } else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n", + grid_coordinate.x(), grid_coordinate.y(), + device_size.x(), device_size.y()); + exit(1); + } + return pin_sides; +} + +/* Deteremine the side of a pin of a grid */ +std::vector find_grid_pin_sides(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const size_t& pin_id) { + std::vector pin_sides; + + t_physical_tile_loc tile_loc(x, y, layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + int width_offset = grids.get_width_offset(tile_loc); + int height_offset = grids.get_height_offset(tile_loc); + for (const e_side& side : {TOP, RIGHT, BOTTOM, LEFT}) { + if (true == phy_tile_type->pinloc[width_offset][height_offset][size_t(side)][pin_id]) { + pin_sides.push_back(side); + } + } + + return pin_sides; +} + +/************************************************************************ + * Get a list of pin_index for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +std::vector get_grid_side_pins(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type, + const e_side& pin_side, + const int& pin_width, + const int& pin_height) { + std::vector pin_list; + /* Make sure a clear start */ + pin_list.clear(); + + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); + for (int ipin = 0; ipin < phy_tile_type->num_pins; ++ipin) { + int class_id = phy_tile_type->pin_class[ipin]; + if ((1 == phy_tile_type->pinloc[pin_width][pin_height][pin_side][ipin]) + && (pin_type == phy_tile_type->class_inf[class_id].type)) { + pin_list.push_back(ipin); + } + } + return pin_list; +} + +/************************************************************************ + * Get the number of pins for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +size_t get_grid_num_pins(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type, + const std::vector& io_side) { + size_t num_pins = 0; + + /* For IO_TYPE sides */ + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); + for (const e_side& side : io_side) { + /* Get pin list */ + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { + std::vector pin_list = get_grid_side_pins(grids, layer, x, y, pin_type, side, width, height); + num_pins += pin_list.size(); + } + } + } + + return num_pins; +} + +/************************************************************************ + * Get the number of pins for a grid (either OPIN or IPIN) + * For IO_TYPE, only one side will be used, we consider one side of pins + * For others, we consider all the sides + ***********************************************************************/ +size_t get_grid_num_classes(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type) { + size_t num_classes = 0; + + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(x, y, layer)); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { + /* Bypass unmatched pin_type */ + if (pin_type != phy_tile_type->class_inf[iclass].type) { + continue; + } + num_classes++; + } + + return num_classes; +} + +/************************************************************************ + * Idenfity if a X-direction routing channel exist in the fabric + * This could be entirely possible that a routig channel + * is in the middle of a multi-width and multi-height grid + * + * As the chanx always locates on top of a grid with the same coord + * + * +----------+ + * | CHANX | + * | [x][y] | + * +----------+ + * + * +----------+ + * | Grid | height_offset = height - 1 + * | [x][y] | + * +----------+ + * + * +----------+ + * | Grid | height_offset = height - 2 + * | [x][y-1] | + * +----------+ + * If the CHANX is in the middle of a multi-width and multi-height grid + * it should locate at a grid whose height_offset is lower than the its height defined in physical_tile + * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block + ***********************************************************************/ +bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel) { + size_t chanx_start = 1; + size_t chanx_end = grids.width() - 2; + if (perimeter_cb) { + chanx_start = 0; + chanx_end = grids.width() - 1; + } + if ((chanx_start > chanx_coord.x()) || (chanx_coord.x() > chanx_end)) { + return false; + } + + if (chanx_coord.y() > grids.height() - 2) { + return false; + } + + if (true == through_channel) { + return true; + } + + return (grids.get_height_offset(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chanx_coord.x(), chanx_coord.y(), layer))->height - 1); +} + +/************************************************************************ + * Idenfity if a Y-direction routing channel exist in the fabric + * This could be entirely possible that a routig channel + * is in the middle of a multi-width and multi-height grid + * + * As the chany always locates on right of a grid with the same coord + * + * +-----------+ +---------+ +--------+ + * | Grid | | Grid | | CHANY | + * | [x-1][y] | | [x][y] | | [x][y] | + * +-----------+ +---------+ +--------+ + * width_offset width_offset + * = width - 2 = width -1 + * If the CHANY is in the middle of a multi-width and multi-height grid + * it should locate at a grid whose width_offset is lower than the its width defined in physical_tile + * When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block + * + * If through channel is allowed, the chany will always exists + * unless it falls out of the grid array + ***********************************************************************/ +bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel) { + size_t chany_start = 1; + size_t chany_end = grids.height() - 2; + if (perimeter_cb) { + chany_start = 0; + chany_end = grids.height() - 1; + } + if (chany_coord.x() > grids.width() - 2) { + return false; + } + + if ((chany_start > chany_coord.y()) || (chany_coord.y() > chany_end)) { + return false; + } + + if (true == through_channel) { + return true; + } + + return (grids.get_width_offset(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer)) == grids.get_physical_type(t_physical_tile_loc(chany_coord.x(), chany_coord.y(), layer))->width - 1); +} + +/************************************************************************ + * Identify if a X-direction routing channel is at the right side of a + * multi-height grid + * + * +-----------------+ + * | | + * | | +-------------+ + * | Grid | | CHANX | + * | [x-1][y] | | [x][y] | + * | | +-------------+ + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel) { + size_t start_x = 1; + if (perimeter_cb) { + start_x = 0; + } else { + VTR_ASSERT(0 < chanx_coord.x()); + } + if (start_x == chanx_coord.x()) { + /* This is already the LEFT side of FPGA fabric, + * it is the same results as chanx is right to a multi-height grid + */ + return true; + } + + if (false == through_channel) { + /* We check the left neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point left_chanx_coord(chanx_coord.x() - 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, layer, left_chanx_coord, perimeter_cb)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a X-direction routing channel is at the left side of a + * multi-height grid + * + * +-----------------+ + * | | + * +---------------+ | | + * | CHANX | | Grid | + * | [x][y] | | [x+1][y] | + * +---------------+ | | + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel) { + VTR_ASSERT(chanx_coord.x() <= grids.width() - 1); + size_t end_x = grids.width() - 2; + if (perimeter_cb) { + end_x = grids.width() - 1; + } + + if (end_x == chanx_coord.x()) { + /* This is already the RIGHT side of FPGA fabric, + * it is the same results as chanx is right to a multi-height grid + */ + return true; + } + + if (false == through_channel) { + /* We check the right neighbor of chanx, if it does not exist, the chanx is left to a multi-height grid */ + vtr::Point right_chanx_coord(chanx_coord.x() + 1, chanx_coord.y()); + if (false == is_chanx_exist(grids, layer, right_chanx_coord, perimeter_cb)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a Y-direction routing channel is at the top side of a + * multi-width grid + * + * +--------+ + * | CHANY | + * | [x][y] | + * +--------+ + * + * +-----------------+ + * | | + * | | + * | Grid | + * | [x-1][y] | + * | | + * | | + * +-----------------+ + ***********************************************************************/ +bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel) { + size_t start_y = 1; + if (perimeter_cb) { + start_y = 0; + } else { + VTR_ASSERT(0 < chany_coord.y()); + } + if (start_y == chany_coord.y()) { + /* This is already the BOTTOM side of FPGA fabric, + * it is the same results as chany is at the top of a multi-width grid + */ + return true; + } + + if (false == through_channel) { + /* We check the bottom neighbor of chany, if it does not exist, the chany is top to a multi-height grid */ + vtr::Point bottom_chany_coord(chany_coord.x(), chany_coord.y() - 1); + if (false == is_chany_exist(grids, layer, bottom_chany_coord, perimeter_cb)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Identify if a Y-direction routing channel is at the bottom side of a + * multi-width grid + * + * +-----------------+ + * | | + * | | + * | Grid | + * | [x][y+1] | + * | | + * | | + * +-----------------+ + * +--------+ + * | CHANY | + * | [x][y] | + * +--------+ + * + ***********************************************************************/ +bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel) { + VTR_ASSERT(chany_coord.y() <= grids.height() - 1); + size_t end_y = grids.height() - 2; + if (perimeter_cb) { + end_y = grids.height() - 1; + } + + if (end_y == chany_coord.y()) { + /* This is already the TOP side of FPGA fabric, + * it is the same results as chany is at the bottom of a multi-width grid + */ + return true; + } + + if (false == through_channel) { + /* We check the top neighbor of chany, if it does not exist, the chany is left to a multi-height grid */ + vtr::Point top_chany_coord(chany_coord.x(), chany_coord.y() + 1); + if (false == is_chany_exist(grids, layer, top_chany_coord, perimeter_cb)) { + return true; + } + } + + return false; +} + +/************************************************************************ + * Get the track_id of a routing track w.r.t its coordinator + * In tileable routing architecture, the track_id changes SB by SB. + * Therefore the track_ids are stored in a vector, indexed by the relative coordinator + * based on the starting point of the track + * For routing tracks in INC_DIRECTION + * (xlow, ylow) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] -------------------------------> track_id[xhigh - xlow + yhigh - ylow] + * + * For routing tracks in DEC_DIRECTION + * (xhigh, yhigh) should be the starting point + * + * (xlow, ylow) (xhigh, yhigh) + * track_id[0] <------------------------------- track_id[xhigh - xlow + yhigh - ylow] + * + * + ***********************************************************************/ +short get_rr_node_actual_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::Point& coord, + const vtr::vector>& tileable_rr_graph_node_track_ids) { + vtr::Point low_coord(rr_graph.node_xlow(track_rr_node), rr_graph.node_ylow(track_rr_node)); + size_t offset = (int)abs((int)coord.x() - (int)low_coord.x() + (int)coord.y() - (int)low_coord.y()); + return tileable_rr_graph_node_track_ids[track_rr_node][offset]; +} + +/************************************************************************ + * Get the ptc of a routing track in the channel where it ends + * For routing tracks in INC_DIRECTION + * the ptc is the last of track_ids + * + * For routing tracks in DEC_DIRECTION + * the ptc is the first of track_ids + ***********************************************************************/ +short get_track_rr_node_end_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::vector>& tileable_rr_graph_node_track_ids) { + /* Make sure we have CHANX or CHANY */ + VTR_ASSERT((CHANX == rr_graph.node_type(track_rr_node)) + || (CHANY == rr_graph.node_type(track_rr_node))); + + if (Direction::INC == rr_graph.node_direction(track_rr_node)) { + return tileable_rr_graph_node_track_ids[track_rr_node].back(); + } + + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(track_rr_node)); + return tileable_rr_graph_node_track_ids[track_rr_node].front(); +} + +/************************************************************************ + * Find the number of nodes in the same class + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_num_nodes(const RRGraph& rr_graph, + const std::vector& node_types) { + short counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + counter++; + } + + return counter; +} + +/************************************************************************ + * Find the maximum fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_max_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + short max_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + max_fan_in = std::max(rr_graph.node_fan_in(node), max_fan_in); + } + + return max_fan_in; +} + +/************************************************************************ + * Find the minimum fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_min_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + short min_fan_in = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + min_fan_in = std::min(rr_graph.node_fan_in(node), min_fan_in); + } + + return min_fan_in; +} + +/************************************************************************ + * Find the average fan-in for a given class of nodes + * in a routing resource graph + ************************************************************************/ +short find_rr_graph_average_fan_in(const RRGraph& rr_graph, + const std::vector& node_types) { + /* Get the maximum SB mux size */ + size_t sum = 0; + size_t counter = 0; + + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass the nodes not in the class */ + if (node_types.end() == std::find(node_types.begin(), node_types.end(), rr_graph.node_type(node))) { + continue; + } + + sum += rr_graph.node_fan_in(node); + counter++; + } + + return sum / counter; +} + +/************************************************************************ + * Print statistics of multiplexers in a routing resource graph + ************************************************************************/ +void print_rr_graph_mux_stats(const RRGraph& rr_graph) { + /* Print MUX size distribution */ + std::vector sb_node_types; + sb_node_types.push_back(CHANX); + sb_node_types.push_back(CHANY); + + /* Print statistics */ + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Switch Block multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, sb_node_types)); + VTR_LOG("Maximum Switch Block multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Minimum Switch Block multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, sb_node_types)); + VTR_LOG("Average Switch Block multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, sb_node_types)); + VTR_LOG("------------------------------------------------\n"); + + /* Get the maximum CB mux size */ + std::vector cb_node_types(1, IPIN); + + VTR_LOG("------------------------------------------------\n"); + VTR_LOG("Total No. of Connection Block Multiplexer size: %d\n", + find_rr_graph_num_nodes(rr_graph, cb_node_types)); + VTR_LOG("Maximum Connection Block Multiplexer size: %d\n", + find_rr_graph_max_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Minimum Connection Block Multiplexer size: %d\n", + find_rr_graph_min_fan_in(rr_graph, cb_node_types)); + VTR_LOG("Average Connection Block Multiplexer size: %lu\n", + find_rr_graph_average_fan_in(rr_graph, cb_node_types)); + VTR_LOG("------------------------------------------------\n"); +} + +int find_parallel_seg_index(const int abs_index, + const t_unified_to_parallel_seg_index& index_map, + const e_parallel_axis parallel_axis) { + int index = -1; + auto itr_pair = index_map.equal_range(abs_index); + + for (auto itr = itr_pair.first; itr != itr_pair.second; ++itr) { + if (itr->second.second == parallel_axis) { + index = itr->second.first; + } + } + + return index; +} diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h new file mode 100644 index 00000000000..c73ebb8206f --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h @@ -0,0 +1,126 @@ +#ifndef RR_GRAPH_BUILDER_UTILS_H +#define RR_GRAPH_BUILDER_UTILS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "device_grid.h" +#include "rr_graph_obj.h" +#include "rr_graph_type.h" +#include "vtr_geometry.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +size_t find_unidir_routing_channel_width(const size_t& chan_width); + +int get_grid_pin_class_index(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const int pin_index); + +std::vector find_grid_pin_sides(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const size_t& pin_id); + +std::vector determine_io_grid_pin_side(const vtr::Point& device_size, + const vtr::Point& grid_coordinate, + const bool& perimeter_cb); + +std::vector get_grid_side_pins(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type, + const e_side& pin_side, + const int& pin_width, + const int& pin_height); + +size_t get_grid_num_pins(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type, + const std::vector& io_side); + +size_t get_grid_num_classes(const DeviceGrid& grids, + const size_t& layer, + const size_t& x, + const size_t& y, + const e_pin_type& pin_type); + +bool is_chanx_exist(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel = false); + +bool is_chany_exist(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel = false); + +bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel); + +bool is_chanx_left_to_multi_height_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chanx_coord, + const bool& perimeter_cb, + const bool& through_channel); + +bool is_chany_top_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel); + +bool is_chany_bottom_to_multi_width_grid(const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& chany_coord, + const bool& perimeter_cb, + const bool& through_channel); + +short get_rr_node_actual_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::Point& coord, + const vtr::vector>& tileable_rr_graph_node_track_ids); + +vtr::Point get_track_rr_node_start_coordinator(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +vtr::Point get_track_rr_node_end_coordinator(const RRGraph& rr_graph, + const RRNodeId& track_rr_node); + +short get_track_rr_node_end_track_id(const RRGraph& rr_graph, + const RRNodeId& track_rr_node, + const vtr::vector>& tileable_rr_graph_node_track_ids); + +short find_rr_graph_num_nodes(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_max_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_min_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +short find_rr_graph_average_fan_in(const RRGraph& rr_graph, + const std::vector& node_types); + +void print_rr_graph_mux_stats(const RRGraph& rr_graph); + +/* A copy of the function from rr_graph2.cpp; This is keep tilable rr_graph builder self-contained */ +int find_parallel_seg_index(const int abs_index, + const t_unified_to_parallel_seg_index& index_map, + const e_parallel_axis parallel_axis); + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_types.h b/vpr/src/tileable_rr_graph/rr_graph_types.h new file mode 100644 index 00000000000..ca97d7d38a9 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_types.h @@ -0,0 +1,45 @@ +#ifndef RR_GRAPH_TYPES_H +#define RR_GRAPH_TYPES_H + +/******************************************************************** + * Data types required by routing resource graph (RRGraph) definition + *******************************************************************/ + +/******************************************************************** + * Directionality of a routing track (node type CHANX and CHANY) in + * a routing resource graph + *******************************************************************/ +enum e_direction : unsigned char { + INC_DIRECTION = 0, + DEC_DIRECTION = 1, + BI_DIRECTION = 2, + NO_DIRECTION = 3, + NUM_DIRECTIONS +}; + +/* Xifan Tang - string used in describe_rr_node() and write_xml_rr_graph_obj() */ +constexpr std::array DIRECTION_STRING_WRITE_XML = {{"INC_DIR", "DEC_DIR", "BI_DIR", "NO_DIR"}}; + +#if 0 +/* Type of a routing resource node. x-directed channel segment, * + * y-directed channel segment, input pin to a clb to pad, output * + * from a clb or pad (i.e. output pin of a net) and: * + * SOURCE: A dummy node that is a logical output within a block * + * -- i.e., the gate that generates a signal. * + * SINK: A dummy node that is a logical input within a block * + * -- i.e. the gate that needs a signal. */ +typedef enum e_rr_type : unsigned char { + SOURCE = 0, + SINK, + IPIN, + OPIN, + CHANX, + CHANY, + NUM_RR_TYPES +} t_rr_type; +#endif + +// constexpr std::array RR_TYPES = {{SOURCE, SINK, IPIN, OPIN, CHANX, CHANY}}; +// constexpr std::array rr_node_typename{{"SOURCE", "SINK", "IPIN", "OPIN", "CHANX", "CHANY"}}; + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp new file mode 100644 index 00000000000..9698ac03b45 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.cpp @@ -0,0 +1,137 @@ +/**************************************************************************** + * This file include most-utilized functions that manipulate on the + * RRGraph object + ***************************************************************************/ +#include "rr_graph_view_util.h" + +/**************************************************************************** + * Find the switches interconnecting two nodes + * Return a vector of switch ids + ***************************************************************************/ +std::vector find_rr_graph_switches(const RRGraphView& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node) { + std::vector switches; + + std::vector edges = rr_graph.find_edges(from_node, to_node); + if (true == edges.empty()) { + /* edge is open, we return an empty vector of switches */ + return switches; + } + + /* Reach here, edge list is not empty, find switch id one by one + * and update the switch list + */ + for (auto edge : edges) { + switches.push_back(rr_graph.edge_switch(edge)); + } + + return switches; +} + +/********************************************************************* + * Like the RRGraph.find_node() but returns all matching nodes, + * rather than just the first. This is particularly useful for getting all instances + * of a specific IPIN/OPIN at a specific grid tile (x,y) location. + **********************************************************************/ +std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc) { + std::vector indices; + + if (rr_type == IPIN || rr_type == OPIN) { + //For pins we need to look at all the sides of the current grid tile + + for (e_side side : TOTAL_2D_SIDES) { + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, ptc, side); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + } else { + //Sides do not effect non-pins so there should only be one per ptc + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, ptc); + + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + + return indices; +} + +/********************************************************************* + * Find a list of rr nodes in a routing channel at (x,y) + **********************************************************************/ +std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type) { + std::vector indices; + + VTR_ASSERT(rr_type == CHANX || rr_type == CHANY); + + for (const RRNodeId& rr_node_index : rr_graph.node_lookup().find_channel_nodes(layer, x, y, rr_type)) { + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + + return indices; +} + +/********************************************************************* + * Find a list of rr_nodes that locate at a side of a grid + **********************************************************************/ +std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, + const DeviceGrid& device_grid, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type, + const e_side& side, + bool include_clock) { + std::vector indices; + + VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); + + /* Ensure that (x, y) is a valid location in grids */ + if (size_t(x) > device_grid.width() - 1 || size_t(y) > device_grid.height() - 1) { + return indices; + } + + /* Ensure we have a valid side */ + VTR_ASSERT(side != NUM_2D_SIDES); + + /* Find all the pins on the side of the grid */ + t_physical_tile_loc tile_loc(x, y, layer); + int width_offset = device_grid.get_width_offset(tile_loc); + int height_offset = device_grid.get_height_offset(tile_loc); + + for (int pin = 0; pin < device_grid.get_physical_type(tile_loc)->num_pins; ++pin) { + /* Skip those pins have been ignored during rr_graph build-up */ + if (true == device_grid.get_physical_type(tile_loc)->is_ignored_pin[pin]) { + /* If specified, force to include all the clock pins */ + if (!include_clock || std::find(device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().begin(), device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().end(), pin) == device_grid.get_physical_type(tile_loc)->get_clock_pins_indices().end()) { + continue; + } + } + if (false == device_grid.get_physical_type(tile_loc)->pinloc[width_offset][height_offset][side][pin]) { + /* Not the pin on this side, we skip */ + continue; + } + + /* Try to find the rr node */ + RRNodeId rr_node_index = rr_graph.node_lookup().find_node(layer, x, y, rr_type, pin, side); + if (rr_node_index != RRNodeId::INVALID()) { + indices.push_back(rr_node_index); + } + } + + return indices; +} diff --git a/vpr/src/tileable_rr_graph/rr_graph_view_util.h b/vpr/src/tileable_rr_graph/rr_graph_view_util.h new file mode 100644 index 00000000000..4ccb1c614e1 --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_graph_view_util.h @@ -0,0 +1,38 @@ +#ifndef RR_GRAPH_VIEW_UTIL_H +#define RR_GRAPH_VIEW_UTIL_H + +/* Include header files which include data structures used by + * the function declaration + */ +#include +#include "device_grid.h" +#include "rr_graph_view.h" + +/* Get node-to-node switches in a RRGraph */ +std::vector find_rr_graph_switches(const RRGraphView& rr_graph, + const RRNodeId& from_node, + const RRNodeId& to_node); + +std::vector find_rr_graph_nodes(const RRGraphView& rr_graph, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type, + const int& ptc); + +std::vector find_rr_graph_chan_nodes(const RRGraphView& rr_graph, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type); + +std::vector find_rr_graph_grid_nodes(const RRGraphView& rr_graph, + const DeviceGrid& device_grid, + const size_t& layer, + const int& x, + const int& y, + const t_rr_type& rr_type, + const e_side& side, + bool include_clock = false); + +#endif diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp new file mode 100644 index 00000000000..36663b21e2a --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp @@ -0,0 +1,1251 @@ +/************************************************************************ + * Member functions for class RRGSB + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_log.h" +#include "vtr_assert.h" + +#include "openfpga_rr_graph_utils.h" +#include "openfpga_side_manager.h" + +#include "rr_gsb.h" +#include "vtr_geometry.h" + +/************************************************************************ + * Constructors + ***********************************************************************/ +/* Constructor for an empty object */ +RRGSB::RRGSB() { + /* Set a clean start! */ + coordinate_.set(0, 0); + + chan_node_.clear(); + chan_node_direction_.clear(); + chan_node_in_edges_.clear(); + ipin_node_in_edges_.clear(); + + ipin_node_.clear(); + + opin_node_.clear(); + + medium_node_.clear(); + for (size_t icb_type = 0; icb_type < 2; icb_type++) { + for (size_t iside = 0; iside < NUM_2D_SIDES; iside++) { + cb_opin_node_[icb_type][iside].clear(); + } + } +} + +/************************************************************************ + * Accessors + ***********************************************************************/ +/* Get the number of sides of this SB */ +size_t RRGSB::get_num_sides() const { + VTR_ASSERT(validate_num_sides()); + return chan_node_direction_.size(); +} + +/* Get the number of routing tracks on a side */ +size_t RRGSB::get_chan_width(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_chan_width(); +} + +/* Get the number of routing tracks on a side */ +t_rr_type RRGSB::get_chan_type(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return chan_node_[side_manager.to_size_t()].get_type(); +} + +/* Get the maximum number of routing tracks on all sides */ +size_t RRGSB::get_max_chan_width() const { + size_t max_chan_width = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + max_chan_width = std::max(max_chan_width, get_chan_width(side_manager.get_side())); + } + return max_chan_width; +} + +const RRChan& RRGSB::chan(const e_side& chan_side) const { + return chan_node_[size_t(chan_side)]; +} + +/* Get the number of routing tracks of a X/Y-direction CB */ +size_t RRGSB::get_cb_chan_width(const t_rr_type& cb_type) const { + return get_chan_width(get_cb_chan_side(cb_type)); +} + +/* Get the sides of ipin_nodes belong to the cb */ +std::vector RRGSB::get_cb_ipin_sides(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + + std::vector ipin_sides; + + /* Make sure a clean start */ + ipin_sides.clear(); + + switch (cb_type) { + case CHANX: + ipin_sides.push_back(TOP); + ipin_sides.push_back(BOTTOM); + break; + case CHANY: + ipin_sides.push_back(RIGHT); + ipin_sides.push_back(LEFT); + break; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } + + return ipin_sides; +} + +/* Get the sides of ipin_nodes belong to the cb */ +std::vector RRGSB::get_cb_opin_sides(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + + std::vector opin_sides; + + /* Make sure a clean start */ + opin_sides.clear(); + + switch (cb_type) { + case CHANX: + case CHANY: + opin_sides.push_back(TOP); + opin_sides.push_back(RIGHT); + opin_sides.push_back(BOTTOM); + opin_sides.push_back(LEFT); + break; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } + + return opin_sides; +} + +/* Get the direction of a rr_node at a given side and track_id */ +enum PORTS RRGSB::get_chan_node_direction(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_direction_[side_manager.to_size_t()][track_id]; +} + +/* Get a list of segments used in this routing channel */ +std::vector RRGSB::get_chan_segment_ids(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + return chan_node_[side_manager.to_size_t()].get_segment_ids(); +} + +/* Get a list of rr_nodes whose sed_id is specified */ +std::vector RRGSB::get_chan_node_ids_by_segment_ids(const e_side& side, + const RRSegmentId& seg_id) const { + return chan_node_[size_t(side)].get_node_ids_by_segment_ids(seg_id); +} + +/* get a rr_node at a given side and track_id */ +RRNodeId RRGSB::get_chan_node(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_[side_manager.to_size_t()].get_node(track_id); +} + +std::vector RRGSB::get_chan_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + /* The chan node must be an output port for the GSB, we allow users to access input edges*/ + VTR_ASSERT(OUT_PORT == get_chan_node_direction(side, track_id)); + + /* if sorted, we give sorted edges + * if not sorted, we give the empty vector + */ + if (0 == chan_node_in_edges_.size()) { + std::vector unsorted_edges; + + for (const RREdgeId& edge : rr_graph.node_in_edges(get_chan_node(side, track_id))) { + unsorted_edges.push_back(edge); + } + + return unsorted_edges; + } + + return chan_node_in_edges_[side_manager.to_size_t()][track_id]; +} + +std::vector RRGSB::get_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& ipin_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_ipin_node_id(side, ipin_id)); + + /* if sorted, we give sorted edges + * if not sorted, we give the empty vector + */ + if (0 == ipin_node_in_edges_.size()) { + std::vector unsorted_edges; + + for (const RREdgeId& edge : rr_graph.node_in_edges(get_ipin_node(side, ipin_id))) { + unsorted_edges.push_back(edge); + } + + return unsorted_edges; + } + + return ipin_node_in_edges_[side_manager.to_size_t()][ipin_id]; +} + +/* get the segment id of a channel rr_node */ +RRSegmentId RRGSB::get_chan_node_segment(const e_side& side, const size_t& track_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_track_id(side, track_id)); + + return chan_node_[side_manager.to_size_t()].get_node_segment(track_id); +} + +/* Get the number of IPIN rr_nodes on a side */ +size_t RRGSB::get_num_ipin_nodes(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return ipin_node_[side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_ipin_node(const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_ipin_node_id(side, node_id)); + + return ipin_node_[side_manager.to_size_t()][node_id]; +} + +/* Get the number of OPIN rr_nodes on a side */ +size_t RRGSB::get_num_opin_nodes(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + return opin_node_[side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_opin_node(const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_opin_node_id(side, node_id)); + + return opin_node_[side_manager.to_size_t()][node_id]; +} + +/* Get the number of OPIN rr_nodes on a side */ +size_t RRGSB::get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + size_t icb_type = get_cb_opin_type_id(cb_type); + return cb_opin_node_[icb_type][side_manager.to_size_t()].size(); +} + +/* get a opin_node at a given side and track_id */ +RRNodeId RRGSB::get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + + /* Ensure the side is valid in the context of this switch block */ + VTR_ASSERT(validate_side(side)); + + /* Ensure the track is valid in the context of this switch block at a specific side */ + VTR_ASSERT(validate_cb_opin_node_id(cb_type, side, node_id)); + + size_t icb_type = get_cb_opin_type_id(cb_type); + return cb_opin_node_[icb_type][side_manager.to_size_t()][node_id]; +} + +/* Get the number of MEDIUM rr_nodes */ +size_t RRGSB::get_num_medium_nodes() const { + VTR_ASSERT(!medium_node_.empty()); + return medium_node_.size(); +} + +/* get a rr_node at a given ptc number */ +RRNodeId RRGSB::get_medium_node(const size_t& ptc) const { + VTR_ASSERT(!medium_node_.empty() && medium_node_.size() > ptc); + return medium_node_[ptc]; +} + +/* Get the node index of a routing track of a connection block, return -1 if not found */ +int RRGSB::get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const { + enum e_side chan_side = get_cb_chan_side(cb_type); + return get_chan_node_index(chan_side, node); +} + +/* Get the node index in the array, return -1 if not found */ +int RRGSB::get_chan_node_index(const e_side& node_side, const RRNodeId& node) const { + VTR_ASSERT(validate_side(node_side)); + return chan_node_[size_t(node_side)].get_node_track_id(node); +} + +/* Get the node index in the array, return -1 if not found */ +int RRGSB::get_node_index(const RRGraphView& rr_graph, + const RRNodeId& node, + const e_side& node_side, + const PORTS& node_direction) const { + size_t cnt; + int ret; + + cnt = 0; + ret = -1; + + /* Depending on the type of rr_node, we search different arrays */ + switch (rr_graph.node_type(node)) { + case CHANX: + case CHANY: + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { + if ((node == chan_node_[size_t(node_side)].get_node(inode)) + /* Check if direction meets specification */ + && (node_direction == chan_node_direction_[size_t(node_side)][inode])) { + cnt++; + ret = inode; + break; + } + } + break; + case IPIN: + for (size_t inode = 0; inode < get_num_ipin_nodes(node_side); ++inode) { + if (node == ipin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + case OPIN: + for (size_t inode = 0; inode < get_num_opin_nodes(node_side); ++inode) { + if (node == opin_node_[size_t(node_side)][inode]) { + cnt++; + ret = inode; + break; + } + } + break; + default: + VTR_LOG("Invalid cur_rr_node type! Should be [CHANX|CHANY|IPIN|OPIN]\n"); + exit(1); + } + + VTR_ASSERT((0 == cnt) || (1 == cnt)); + + return ret; /* Return an invalid value: nonthing is found*/ +} + +/* Get the side of a node in this SB */ +void RRGSB::get_node_side_and_index(const RRGraphView& rr_graph, + const RRNodeId& node, + const PORTS& node_direction, + e_side& node_side, + int& node_index) const { + size_t side; + SideManager side_manager; + + /* Count the number of existence of cur_rr_node in cur_sb_info + * It could happen that same cur_rr_node appears on different sides of a SB + * For example, a routing track go vertically across the SB. + * Then its corresponding rr_node appears on both TOP and BOTTOM sides of this SB. + * We need to ensure that the found rr_node has the same direction as user want. + * By specifying the direction of rr_node, There should be only one rr_node can satisfy! + */ + for (side = 0; side < get_num_sides(); ++side) { + side_manager.set_side(side); + node_index = get_node_index(rr_graph, node, side_manager.get_side(), node_direction); + if (-1 != node_index) { + break; + } + } + + if (side == get_num_sides()) { + /* we find nothing, return NUM_SIDES, and a OPEN node (-1) */ + node_side = NUM_2D_SIDES; + VTR_ASSERT(-1 == node_index); + return; + } + + node_side = side_manager.get_side(); + VTR_ASSERT(-1 != node_index); + + return; +} + +/* Check if the node exist in the opposite side of this Switch Block */ +bool RRGSB::is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, + const RRNodeId& node, + const e_side& node_side) const { + SideManager side_manager(node_side); + int index; + + VTR_ASSERT((CHANX == rr_graph.node_type(node)) || (CHANY == rr_graph.node_type(node))); + + /* See if we can find the same src_rr_node in the opposite chan_side + * if there is one, it means a shorted wire across the SB + */ + index = get_node_index(rr_graph, node, side_manager.get_opposite(), IN_PORT); + + return (-1 != index); +} + +bool RRGSB::is_opin_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + for (auto opin_node : opin_node_[side]) { + if (node == opin_node) { + return true; + } + } + } + return false; +} + +bool RRGSB::is_ipin_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + for (auto ipin_node : ipin_node_[side]) { + if (node == ipin_node) { + return true; + } + } + } + return false; +} + +bool RRGSB::is_medium_node(const RRNodeId& node) const { + for (auto medium_node : medium_node_) { + if (node == medium_node) { + return true; + } + } + return false; +} + +bool RRGSB::is_chan_node(const RRNodeId& node) const { + std::vector sides = {TOP, RIGHT, BOTTOM, LEFT}; + for (e_side side : sides) { + RRChan rr_chan = chan_node_[side]; + for (size_t inode = 0; inode < rr_chan.get_chan_width(); ++inode) { + if (node == rr_chan.get_node(inode)) { + return true; + } + } + } + return false; +} + +/* check if the CB exist in this GSB */ +bool RRGSB::is_cb_exist(const t_rr_type& cb_type) const { + /* if channel width is zero, there is no CB */ + return (0 != get_cb_chan_width(cb_type)); +} + +/* check if the SB exist in this GSB */ +bool RRGSB::is_sb_exist(const RRGraphView& rr_graph) const { + /* Count the number of sides that there are routing wires or opin nodes */ + size_t num_sides_contain_routing_wires = 0; + size_t num_sides_contain_opin_nodes = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + if (0 != get_chan_width(side_manager.get_side())) { + num_sides_contain_routing_wires++; + } + if (0 != get_num_opin_nodes(side_manager.get_side())) { + num_sides_contain_opin_nodes++; + } + } + /* When there are zero nodes, the sb does not exist */ + if (num_sides_contain_routing_wires == 0 && num_sides_contain_opin_nodes == 0) { + return false; + } + /* If there is only 1 side of nodes and there are 0 opin nodes, and there are no incoming edges, this is also an empty switch block */ + if (num_sides_contain_routing_wires == 1 && num_sides_contain_opin_nodes == 0) { + size_t num_incoming_edges = 0; + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + for (size_t itrack = 0; itrack < get_chan_width(side_manager.get_side()); ++itrack) { + if (OUT_PORT != get_chan_node_direction(side_manager.get_side(), itrack)) { + continue; + } + num_incoming_edges += get_chan_node_in_edges(rr_graph, side_manager.get_side(), itrack).size(); + } + } + return num_incoming_edges ? true : false; + } + + return true; +} + +/************************************************************************ + * Check if the node indicates a passing wire across the Switch Block part of the GSB + * Therefore, we actually do the following check + * Check if a track starts from this GSB or not + * For INC_DIRECTION + * (xlow, ylow) should be same as the GSB side coordinate + * For DEC_DIRECTION + * (xhigh, yhigh) should be same as the GSB side coordinate + ***********************************************************************/ +bool RRGSB::is_sb_node_passing_wire(const RRGraphView& rr_graph, + const e_side& node_side, + const size_t& track_id) const { + /* Get the rr_node */ + RRNodeId track_node = get_chan_node(node_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = get_side_block_coordinate(node_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ((track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == get_chan_node_direction(node_side, track_id))) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + return false; /* This is a starting point */ + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ((track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == get_chan_node_direction(node_side, track_id))) { + /* Double check: end track should be an INPUT PORT of the GSB */ + return false; /* This is an ending point */ + } + + /* Reach here it means that this will be a passing wire, + * we should be able to find the node on the opposite side of the GSB! + */ + if (true != is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)) { + VTR_LOG("Cannot find a node on the opposite side to GSB[%lu][%lu] track node[%lu] at %s!\nDetailed node information:\n", + get_x(), get_y(), track_id, TOTAL_2D_SIDE_STRINGS[node_side]); + VTR_LOG("Node type: %s\n", rr_graph.node_type_string(track_node)); + VTR_LOG("Node coordinate: %s\n", rr_graph.node_coordinate_to_string(track_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(track_node)); + } + VTR_ASSERT(true == is_sb_node_exist_opposite_side(rr_graph, track_node, node_side)); + + return true; +} + +/* check if the candidate SB satisfy the basic requirements on being a mirror of the current one */ +/* Idenify mirror Switch blocks + * Check each two switch blocks: + * Number of channel/opin/ipin rr_nodes are same + * If all above are satisfied, the two switch blocks may be mirrors ! + */ +bool RRGSB::is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const { + /* check the numbers of sides */ + if (get_num_sides() != cand.get_num_sides()) { + return false; + } + + /* check the numbers/directionality of channel rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + + /* Ensure we have the same channel width on this side */ + if (get_chan_width(side_manager.get_side()) != cand.get_chan_width(side_manager.get_side())) { + return false; + } + + if (((size_t(-1) == get_track_id_first_short_connection(rr_graph, side_manager.get_side())) + && (size_t(-1) != cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side()))) + || ((size_t(-1) != get_track_id_first_short_connection(rr_graph, side_manager.get_side())) + && (size_t(-1) == cand.get_track_id_first_short_connection(rr_graph, side_manager.get_side())))) { + return false; + } + } + + /* check the numbers of opin_rr_nodes */ + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + + if (get_num_opin_nodes(side_manager.get_side()) != cand.get_num_opin_nodes(side_manager.get_side())) { + return false; + } + } + + return true; +} + +/* Public Accessors: Cooridinator conversion */ + +/* get the x coordinate of this GSB */ +size_t RRGSB::get_x() const { + return coordinate_.x(); +} + +/* get the y coordinate of this GSB */ +size_t RRGSB::get_y() const { + return coordinate_.y(); +} + +/* get the x coordinate of this switch block */ +size_t RRGSB::get_sb_x() const { + return coordinate_.x(); +} + +/* get the y coordinate of this switch block */ +size_t RRGSB::get_sb_y() const { + return coordinate_.y(); +} + +/* Get the number of sides of this SB */ +vtr::Point RRGSB::get_sb_coordinate() const { + return coordinate_; +} + +/* get the x coordinate of this X/Y-direction block */ +size_t RRGSB::get_cb_x(const t_rr_type& cb_type) const { + return get_cb_coordinate(cb_type).x(); +} + +/* get the y coordinate of this X/Y-direction block */ +size_t RRGSB::get_cb_y(const t_rr_type& cb_type) const { + return get_cb_coordinate(cb_type).y(); +} + +/* Get the coordinate of the X/Y-direction CB */ +vtr::Point RRGSB::get_cb_coordinate(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return coordinate_; + case CHANY: + return coordinate_; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +e_side RRGSB::get_cb_chan_side(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + switch (cb_type) { + case CHANX: + return LEFT; + case CHANY: + return BOTTOM; + default: + VTR_LOG("Invalid type of connection block!\n"); + exit(1); + } +} + +/* Get the side of routing channel in the GSB according to the side of IPIN */ +e_side RRGSB::get_cb_chan_side(const e_side& ipin_side) const { + switch (ipin_side) { + case TOP: + return LEFT; + case RIGHT: + return BOTTOM; + case BOTTOM: + return LEFT; + case LEFT: + return BOTTOM; + default: + VTR_LOG("Invalid type of ipin_side!\n"); + exit(1); + } +} + +vtr::Point RRGSB::get_side_block_coordinate(const e_side& side) const { + SideManager side_manager(side); + VTR_ASSERT(side_manager.validate()); + vtr::Point ret(get_sb_x(), get_sb_y()); + + switch (side_manager.get_side()) { + case TOP: + /* (0 == side) */ + /* 1. Channel Y [x][y+1] inputs */ + ret.set_y(ret.y() + 1); + break; + case RIGHT: + /* 1 == side */ + /* 2. Channel X [x+1][y] inputs */ + ret.set_x(ret.x() + 1); + break; + case BOTTOM: + /* 2 == side */ + /* 3. Channel Y [x][y] inputs */ + break; + case LEFT: + /* 3 == side */ + /* 4. Channel X [x][y] inputs */ + break; + default: + VTR_LOG(" Invalid side!\n"); + exit(1); + } + + return ret; +} + +vtr::Point RRGSB::get_grid_coordinate() const { + return coordinate_; +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +/* get a copy from a source */ +void RRGSB::set(const RRGSB& src) { + /* Copy coordinate */ + this->set_coordinate(src.get_sb_coordinate().x(), src.get_sb_coordinate().y()); + + /* Initialize sides */ + this->init_num_sides(src.get_num_sides()); + + /* Copy vectors */ + for (size_t side = 0; side < src.get_num_sides(); ++side) { + SideManager side_manager(side); + /* Copy chan_nodes */ + /* skip if there is no channel width */ + if (0 < src.get_chan_width(side_manager.get_side())) { + this->chan_node_[side_manager.get_side()].set(src.chan_node_[side_manager.get_side()]); + /* Copy chan_node_direction_*/ + this->chan_node_direction_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_chan_width(side_manager.get_side()); ++inode) { + this->chan_node_direction_[side_manager.get_side()].push_back(src.get_chan_node_direction(side_manager.get_side(), inode)); + } + } + + /* Copy opin_node and opin_node_grid_side_ */ + this->opin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_opin_nodes(side_manager.get_side()); ++inode) { + this->opin_node_[side_manager.get_side()].push_back(src.get_opin_node(side_manager.get_side(), inode)); + } + + /* Copy ipin_node and ipin_node_grid_side_ */ + this->ipin_node_[side_manager.get_side()].clear(); + for (size_t inode = 0; inode < src.get_num_ipin_nodes(side_manager.get_side()); ++inode) { + this->ipin_node_[side_manager.get_side()].push_back(src.get_ipin_node(side_manager.get_side(), inode)); + } + } +} + +/* Set the coordinate (x,y) for the switch block */ +void RRGSB::set_coordinate(const size_t& x, const size_t& y) { + coordinate_.set(x, y); +} + +/* Allocate the vectors with the given number of sides */ +void RRGSB::init_num_sides(const size_t& num_sides) { + /* Initialize the vectors */ + chan_node_.resize(num_sides); + chan_node_direction_.resize(num_sides); + ipin_node_.resize(num_sides); + opin_node_.resize(num_sides); +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_chan_node(const e_side& node_side, + const RRChan& rr_chan, + const std::vector& rr_chan_dir) { + /* Validate: 1. side is valid, the type of node is valid */ + VTR_ASSERT(validate_side(node_side)); + + /* fill the dedicated element in the vector */ + chan_node_[size_t(node_side)].set(rr_chan); + chan_node_direction_[size_t(node_side)].resize(rr_chan_dir.size()); + for (size_t inode = 0; inode < rr_chan_dir.size(); ++inode) { + chan_node_direction_[size_t(node_side)][inode] = rr_chan_dir[inode]; + } +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_ipin_node(const RRNodeId& node, const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + ipin_node_[size_t(node_side)].push_back(node); +} + +/* Add a node to the chan_node_ list and also assign its direction in chan_node_direction_ */ +void RRGSB::add_opin_node(const RRNodeId& node, const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + /* push pack the dedicated element in the vector */ + opin_node_[size_t(node_side)].push_back(node); +} + +/* Add a node to the medium_node_ */ +void RRGSB::add_medium_node(const RRNodeId& medium_node) { + /* push pack the dedicated element in the vector */ + medium_node_.push_back(medium_node); +} + +void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, + const e_side& chan_side, + const size_t& track_id) { + std::map> from_grid_edge_map; + std::map> from_track_edge_map; + + const RRNodeId& chan_node = chan_node_[size_t(chan_side)].get_node(track_id); + + /* Count the edges and ensure every of them has been sorted */ + size_t edge_counter = 0; + + /* For each incoming edge, find the node side and index in this GSB. + * and cache these. Then we will use the data to sort the edge in the + * following sequence: + * 0----------------------------------------------------------------> num_in_edges() + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * For each side, the edge will be sorted by the node index starting from 0 + * For each side, the edge from grid pins will be the 1st part + * while the edge from routing tracks will be the 2nd part + */ + for (const RREdgeId& edge : rr_graph.node_in_edges(chan_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + e_side side = NUM_2D_SIDES; + int index = 0; + get_node_side_and_index(rr_graph, src_node, IN_PORT, side, index); + + /* Must have valid side and index */ + if (NUM_2D_SIDES == side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + VTR_LOG("\n----------------------------------\n"); + VTR_LOG("Channel node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(chan_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(chan_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& temp_edge : rr_graph.node_in_edges(chan_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); + } + } + + VTR_ASSERT(NUM_2D_SIDES != side); + VTR_ASSERT(OPEN != index); + + if (OPIN == rr_graph.node_type(src_node)) { + from_grid_edge_map[side][index] = edge; + } else { + VTR_ASSERT((CHANX == rr_graph.node_type(src_node)) + || (CHANY == rr_graph.node_type(src_node))); + from_track_edge_map[side][index] = edge; + } + + edge_counter++; + } + + /* Store the sorted edge */ + for (size_t side = 0; side < get_num_sides(); ++side) { + /* Edges from grid outputs are the 1st part */ + for (size_t opin_id = 0; opin_id < opin_node_[side].size(); ++opin_id) { + if ((0 < from_grid_edge_map.count(side)) + && (0 < from_grid_edge_map.at(side).count(opin_id))) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_grid_edge_map[side][opin_id]); + } + } + + /* Edges from routing tracks are the 2nd part */ + for (size_t itrack = 0; itrack < chan_node_[side].get_chan_width(); ++itrack) { + if ((0 < from_track_edge_map.count(side)) + && (0 < from_track_edge_map.at(side).count(itrack))) { + chan_node_in_edges_[size_t(chan_side)][track_id].push_back(from_track_edge_map[side][itrack]); + } + } + } + + VTR_ASSERT(edge_counter == chan_node_in_edges_[size_t(chan_side)][track_id].size()); +} + +void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph) { + /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ + chan_node_in_edges_.resize(get_num_sides()); + + for (size_t side = 0; side < get_num_sides(); ++side) { + SideManager side_manager(side); + /* Bypass boundary GSBs here. When perimeter_cb option is on, Some GSBs may have only 1 side of CHANX or CHANY. There are no edges in the GSB, so we should skip them */ + chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width()); + for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) { + /* Only sort the output nodes and bypass passing wires */ + if ((OUT_PORT == chan_node_direction_[side][track_id]) + && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id))) { + sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); + } + } + } +} + +void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& ipin_side, + const size_t& ipin_id) { + std::map from_track_edge_map; + std::array, NUM_2D_SIDES> from_opin_edge_map; + + e_side chan_side = get_cb_chan_side(ipin_side); + + const RRNodeId& ipin_node = ipin_node_[size_t(ipin_side)][ipin_id]; + + /* Count the edges and ensure every of them has been sorted */ + size_t edge_counter = 0; + + /* For each incoming edge, find the node side and index in this GSB. + * and cache these. Then we will use the data to sort the edge in the + * following sequence: + * 0----------------------------------------------------------------> num_in_edges() + * |<---------------------------1st part routing tracks -------------> + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * |<---------------------------2nd part IPINs -------------> + * |<--TOP side-->|<--RIGHT side-->|<--BOTTOM side-->|<--LEFT side-->| + * For each side, the edge will be sorted by the node index starting from 0 + * For each side, the edge from grid pins will be the 2nd part (sorted by ptc number) + * while the edge from routing tracks will be the 1st part + */ + for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ + if (CHANX != rr_graph.node_type(src_node) && CHANY != rr_graph.node_type(src_node)) { + continue; + } + /* The driver routing channel node can be either an input or an output to the GSB. + * Just try to find a qualified one. */ + int index = OPEN; + index = get_node_index(rr_graph, src_node, chan_side, IN_PORT); + if (OPEN == index) { + index = get_node_index(rr_graph, src_node, chan_side, OUT_PORT); + } + + /* Must have valid side and index */ + if (OPEN == index) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + VTR_LOG("\n----------------------------------\n"); + VTR_LOG("IPIN node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(ipin_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(ipin_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& temp_edge : rr_graph.node_in_edges(ipin_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); + } + } + + VTR_ASSERT(OPEN != index); + + VTR_ASSERT(CHANX == rr_graph.node_type(src_node) || CHANY == rr_graph.node_type(src_node)); + from_track_edge_map[index] = edge; + edge_counter++; + } + + for (const RREdgeId& edge : rr_graph.node_in_edges(ipin_node)) { + /* We care the source node of this edge, and it should be an input of the GSB!!! */ + const RRNodeId& src_node = rr_graph.edge_src_node(edge); + /* In this part, we only sort routing track nodes. IPIN nodes will be handled later */ + if (OPIN != rr_graph.node_type(src_node)) { + continue; + } + enum e_side cb_opin_side = NUM_2D_SIDES; + int cb_opin_index = -1; + get_node_side_and_index(rr_graph, src_node, IN_PORT, cb_opin_side, + cb_opin_index); + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); + /* Must have valid side and index */ + if (OPEN == cb_opin_index || NUM_2D_SIDES == cb_opin_side) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(src_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(src_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(src_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + VTR_LOG("\n----------------------------------\n"); + VTR_LOG("IPIN node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(ipin_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(ipin_node)); + VTR_LOG("Fan-in nodes:\n"); + for (const auto& temp_edge : rr_graph.node_in_edges(ipin_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_src_node(temp_edge)).c_str()); + } + } + from_opin_edge_map[size_t(cb_opin_side)][cb_opin_index] = edge; + edge_counter++; + } + + /* Store the sorted edge */ + for (size_t itrack = 0; itrack < chan_node_[size_t(chan_side)].get_chan_width(); ++itrack) { + if (0 < from_track_edge_map.count(itrack)) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_track_edge_map[itrack]); + } + } + + for (e_side iside : {TOP, RIGHT, BOTTOM, LEFT}) { + for (size_t ipin = 0; ipin < get_num_opin_nodes(iside); ++ipin) { + if (0 < from_opin_edge_map[size_t(iside)].count(ipin)) { + ipin_node_in_edges_[size_t(ipin_side)][ipin_id].push_back(from_opin_edge_map[size_t(iside)][ipin]); + } + } + } + + VTR_ASSERT(edge_counter == ipin_node_in_edges_[size_t(ipin_side)][ipin_id].size()); +} + +void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph) { + /* Allocate here, as sort edge is optional, we do not allocate when adding nodes */ + ipin_node_in_edges_.resize(get_num_sides()); + + for (t_rr_type cb_type : {CHANX, CHANY}) { + for (e_side ipin_side : get_cb_ipin_sides(cb_type)) { + SideManager side_manager(ipin_side); + ipin_node_in_edges_[size_t(ipin_side)].resize(ipin_node_[size_t(ipin_side)].size()); + for (size_t ipin_id = 0; ipin_id < ipin_node_[size_t(ipin_side)].size(); ++ipin_id) { + sort_ipin_node_in_edges(rr_graph, side_manager.get_side(), ipin_id); + } + } + } +} + +void RRGSB::build_cb_opin_nodes(const RRGraphView& rr_graph) { + for (t_rr_type cb_type : {CHANX, CHANY}) { + size_t icb_type = cb_type == CHANX ? 0 : 1; + std::vector cb_ipin_sides = get_cb_ipin_sides(cb_type); + for (size_t iside = 0; iside < cb_ipin_sides.size(); ++iside) { + enum e_side cb_ipin_side = cb_ipin_sides[iside]; + for (size_t inode = 0; inode < get_num_ipin_nodes(cb_ipin_side); + ++inode) { + std::vector driver_rr_edges = + get_ipin_node_in_edges(rr_graph, cb_ipin_side, inode); + for (const RREdgeId curr_edge : driver_rr_edges) { + RRNodeId cand_node = rr_graph.edge_src_node(curr_edge); + if (OPIN != rr_graph.node_type(cand_node)) { + continue; + } + enum e_side cb_opin_side = NUM_2D_SIDES; + int cb_opin_index = -1; + get_node_side_and_index(rr_graph, cand_node, IN_PORT, cb_opin_side, + cb_opin_index); + if ((-1 == cb_opin_index) || (NUM_2D_SIDES == cb_opin_side)) { + VTR_LOG("GSB[%lu][%lu]:\n", get_x(), get_y()); + VTR_LOG("----------------------------------\n"); + VTR_LOG("SRC node:\n"); + VTR_LOG("Node info: %s\n", rr_graph.node_coordinate_to_string(cand_node).c_str()); + VTR_LOG("Node ptc: %d\n", rr_graph.node_ptc_num(cand_node)); + VTR_LOG("Fan-out nodes:\n"); + for (const auto& temp_edge : rr_graph.edge_range(cand_node)) { + VTR_LOG("\t%s\n", rr_graph.node_coordinate_to_string(rr_graph.edge_sink_node(temp_edge)).c_str()); + } + } + VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); + + if (cb_opin_node_[icb_type][size_t(cb_opin_side)].end() == + std::find(cb_opin_node_[icb_type][size_t(cb_opin_side)].begin(), cb_opin_node_[icb_type][size_t(cb_opin_side)].end(), cand_node)) { + cb_opin_node_[icb_type][size_t(cb_opin_side)].push_back(cand_node); + } + } + } + } + } +} + +/************************************************************************ + * Public Mutators: clean-up functions + ***********************************************************************/ +/* Reset the RRGSB to pristine state */ +void RRGSB::clear() { + /* Clean all the vectors */ + VTR_ASSERT(validate_num_sides()); + /* Clear the inner vector of each matrix */ + for (size_t side = 0; side < get_num_sides(); ++side) { + chan_node_direction_[side].clear(); + chan_node_[side].clear(); + ipin_node_[side].clear(); + opin_node_[side].clear(); + } + chan_node_direction_.clear(); + chan_node_.clear(); + ipin_node_.clear(); + opin_node_.clear(); +} + +/* Clean the chan_width of a side */ +void RRGSB::clear_chan_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + chan_node_[size_t(node_side)].clear(); + chan_node_direction_[size_t(node_side)].clear(); +} + +/* Clean the number of IPINs of a side */ +void RRGSB::clear_ipin_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + ipin_node_[size_t(node_side)].clear(); +} + +/* Clean the number of OPINs of a side */ +void RRGSB::clear_opin_nodes(const e_side& node_side) { + VTR_ASSERT(validate_side(node_side)); + + opin_node_[size_t(node_side)].clear(); +} + +/* Clean chan/opin/ipin nodes at one side */ +void RRGSB::clear_one_side(const e_side& node_side) { + clear_chan_nodes(node_side); + clear_ipin_nodes(node_side); + clear_opin_nodes(node_side); +} + +/************************************************************************ + * Internal Accessors: identify mirrors + ***********************************************************************/ +size_t RRGSB::get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const { + VTR_ASSERT(validate_side(node_side)); + + /* Walk through chan_nodes and find the first short connection */ + for (size_t inode = 0; inode < get_chan_width(node_side); ++inode) { + if (true == is_sb_node_passing_wire(rr_graph, node_side, inode)) { + return inode; + } + } + + return size_t(-1); +} + +/************************************************************************ + * Internal validators + ***********************************************************************/ +/* Validate if the number of sides are consistent among internal data arrays ! */ +bool RRGSB::validate_num_sides() const { + size_t num_sides = chan_node_direction_.size(); + + if (num_sides != chan_node_.size()) { + return false; + } + + if (num_sides != ipin_node_.size()) { + return false; + } + + if (num_sides != opin_node_.size()) { + return false; + } + + return true; +} + +/* Check if the side valid in the context: does the switch block have the side? */ +bool RRGSB::validate_side(const e_side& side) const { + return (size_t(side) < get_num_sides()); +} + +/* Check the track_id is valid for chan_node_ and chan_node_direction_ */ +bool RRGSB::validate_track_id(const e_side& side, const size_t& track_id) const { + if (false == validate_side(side)) { + return false; + } + + return ((track_id < chan_node_[size_t(side)].get_chan_width()) + && (track_id < chan_node_direction_[size_t(side)].size())); +} + +/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_opin_node_id(const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + return (node_id < opin_node_[size_t(side)].size()); +} + +/* Check the opin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + size_t icb_type = get_cb_opin_type_id(cb_type); + return (node_id < cb_opin_node_[icb_type][size_t(side)].size()); +} + +/* Check the ipin_node_id is valid for opin_node_ and opin_node_grid_side_ */ +bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) const { + if (false == validate_side(side)) { + return false; + } + return (node_id < ipin_node_[size_t(side)].size()); +} + +bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const { + return ((CHANX == cb_type) || (CHANY == cb_type)); +} + +size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const { + VTR_ASSERT(validate_cb_type(cb_type)); + return cb_type == CHANX ? 0 : 1; +} diff --git a/vpr/src/tileable_rr_graph/rr_gsb.h b/vpr/src/tileable_rr_graph/rr_gsb.h new file mode 100644 index 00000000000..37b2dcc6f9d --- /dev/null +++ b/vpr/src/tileable_rr_graph/rr_gsb.h @@ -0,0 +1,292 @@ +#ifndef RR_GSB_H +#define RR_GSB_H + +/******************************************************************** + * Include header files required by the data structure definition + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +#include "rr_chan.h" +#include "rr_graph_view.h" + +/******************************************************************** + * Object Generic Switch Block + * This block contains + * 1. A switch block + * 2. A X-direction Connection block locates at the left side of the switch block + * 2. A Y-direction Connection block locates at the top side of the switch block + * + * TOP SIDE + * +-------------+ +---------------------------------+ + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | X-direction | | | + * | CB | LEFT SIDE | Switch Block | RIGHT SIDE + * | [x][y] | | [x][y] | + * | | | | + * | | | CHAN_NODES CHAN_NODES | + * | | | | + * | | | OPIN_NODES OPIN_NODES | + * | | | | + * | | | OPIN_NODE CHAN_NODES OPIN_NODES | + * +-------------+ +---------------------------------+ + * BOTTOM SIDE + * +-------------+ +---------------------------------+ + * | Grid | | Y-direction CB | + * | [x][y] | | [x][y] | + * +-------------+ +---------------------------------+ + * + * num_sides: number of sides of this switch block + * chan_rr_node: a collection of rr_nodes as routing tracks locating at each side of the Switch block <0..num_sides-1><0..chan_width-1> + * chan_rr_node_direction: Indicate if this rr_node is an input or an output of the Switch block <0..num_sides-1><0..chan_width-1> + * ipin_rr_node: a collection of rr_nodes as IPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_ipin_rr_nodes-1> + * ipin_rr_node_grid_side: specify the side of the input pins on which side of a GRID <0..num_sides-1><0..num_ipin_rr_nodes-1> + * opin_rr_node: a collection of rr_nodes as OPIN of a GRID locating at each side of the Switch block <0..num_sides-1><0..num_opin_rr_nodes-1> + * opin_rr_node_grid_side: specify the side of the output pins on which side of a GRID <0..num_sides-1><0..num_opin_rr_nodes-1> + * num_reserved_conf_bits: number of reserved configuration bits this switch block requires (mainly due to RRAM-based multiplexers) + * num_conf_bits: number of configuration bits this switch block requires + *******************************************************************/ +class RRGSB { + public: /* Contructors */ + RRGSB(); /* Default constructor */ + public: /* Accessors */ + /* Get the number of sides of this SB */ + size_t get_num_sides() const; + + /* Get the number of routing tracks on a side */ + size_t get_chan_width(const e_side& side) const; + + /* Get the type of routing tracks on a side */ + t_rr_type get_chan_type(const e_side& side) const; + + /* Get the maximum number of routing tracks on all sides */ + size_t get_max_chan_width() const; + + /* Get the number of routing tracks of a X/Y-direction CB */ + size_t get_cb_chan_width(const t_rr_type& cb_type) const; + + /* Return read-only object of the routing channels with a given side */ + const RRChan& chan(const e_side& chan_side) const; + + /* Get the sides of CB ipins in the array */ + std::vector get_cb_ipin_sides(const t_rr_type& cb_type) const; + /* Get the sides of CB opins in the array, OPINs can only be at the same sides of IPINs. Differently, they are inputs to a connection block */ + std::vector get_cb_opin_sides(const t_rr_type& cb_type) const; + + /* Get the direction of a rr_node at a given side and track_id */ + enum PORTS get_chan_node_direction(const e_side& side, const size_t& track_id) const; + + /* Get a list of segments used in this routing channel */ + std::vector get_chan_segment_ids(const e_side& side) const; + + /* Get a list of segments used in this routing channel */ + std::vector get_chan_node_ids_by_segment_ids(const e_side& side, + const RRSegmentId& seg_id) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_chan_node(const e_side& side, const size_t& track_id) const; + + /* get all the sorted incoming edges for a rr_node at a given side and track_id */ + std::vector get_chan_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& track_id) const; + + /* get all the sorted incoming edges for a IPIN rr_node at a given side and ipin_id */ + std::vector get_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& side, + const size_t& ipin_id) const; + + /* get the segment id of a channel rr_node */ + RRSegmentId get_chan_node_segment(const e_side& side, const size_t& track_id) const; + + /* Get the number of IPIN rr_nodes on a side */ + size_t get_num_ipin_nodes(const e_side& side) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_ipin_node(const e_side& side, const size_t& node_id) const; + + /* Get the number of OPIN rr_nodes on a side */ + size_t get_num_opin_nodes(const e_side& side) const; + /* Get the number of OPIN rr_nodes on a side of a connection block */ + size_t get_num_cb_opin_nodes(const t_rr_type& cb_type, const e_side& side) const; + + /* get a rr_node at a given side and track_id */ + RRNodeId get_opin_node(const e_side& side, const size_t& node_id) const; + /* get a rr_node at a given side and track_id for a connection block */ + RRNodeId get_cb_opin_node(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + + /* Get the number of MEDIUM rr_nodes */ + size_t get_num_medium_nodes() const; + + /* get a rr_node at a given ptc number */ + RRNodeId get_medium_node(const size_t& ptc) const; + + int get_cb_chan_node_index(const t_rr_type& cb_type, const RRNodeId& node) const; + + int get_chan_node_index(const e_side& node_side, const RRNodeId& node) const; + + /* Get the node index in the array, return -1 if not found */ + int get_node_index(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side, const PORTS& node_direction) const; + + /* Given a rr_node, try to find its side and index in the Switch block */ + void get_node_side_and_index(const RRGraphView& rr_graph, const RRNodeId& node, const PORTS& node_direction, e_side& node_side, int& node_index) const; + + /* Check if the node exist in the opposite side of this Switch Block */ + bool is_sb_node_exist_opposite_side(const RRGraphView& rr_graph, const RRNodeId& node, const e_side& node_side) const; + + bool is_opin_node(const RRNodeId& node) const; + bool is_ipin_node(const RRNodeId& node) const; + bool is_medium_node(const RRNodeId& node) const; + bool is_chan_node(const RRNodeId& node) const; + + public: /* Accessors: to identify mirrors */ + /* check if the connect block exists in the GSB */ + bool is_cb_exist(const t_rr_type& cb_type) const; + + /* check if the switch block exists in the GSB, this function checks if a switch block physically exists (no routing wires, no OPIN nodes, and no interconnecting wires) */ + bool is_sb_exist(const RRGraphView& rr_graph) const; + + /* Check if the node imply a short connection inside the SB, which happens to long wires across a FPGA fabric */ + bool is_sb_node_passing_wire(const RRGraphView& rr_graph, const e_side& node_side, const size_t& track_id) const; + + /* check if the candidate SB satisfy the basic requirements + * on being a mirror of the current one + */ + bool is_sb_mirrorable(const RRGraphView& rr_graph, const RRGSB& cand) const; + + public: /* Cooridinator conversion and output */ + size_t get_x() const; /* get the x coordinate of this switch block */ + size_t get_y() const; /* get the y coordinate of this switch block */ + size_t get_sb_x() const; /* get the x coordinate of this switch block */ + size_t get_sb_y() const; /* get the y coordinate of this switch block */ + vtr::Point get_sb_coordinate() const; /* Get the coordinate of the SB */ + size_t get_cb_x(const t_rr_type& cb_type) const; /* get the x coordinate of this X/Y-direction block */ + size_t get_cb_y(const t_rr_type& cb_type) const; /* get the y coordinate of this X/Y-direction block */ + vtr::Point get_cb_coordinate(const t_rr_type& cb_type) const; /* Get the coordinate of the X/Y-direction CB */ + e_side get_cb_chan_side(const t_rr_type& cb_type) const; /* get the side of a Connection block */ + e_side get_cb_chan_side(const e_side& ipin_side) const; /* get the side of a Connection block */ + vtr::Point get_side_block_coordinate(const e_side& side) const; + vtr::Point get_grid_coordinate() const; + + public: /* Mutators */ + /* get a copy from a source */ + void set(const RRGSB& src); + void set_coordinate(const size_t& x, const size_t& y); + + /* Allocate the vectors with the given number of sides */ + void init_num_sides(const size_t& num_sides); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_chan_node(const e_side& node_side, + const RRChan& rr_chan, + const std::vector& rr_chan_dir); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_ipin_node(const RRNodeId& node, + const e_side& node_side); + + /* Add a node to the chan_rr_node_ list and also + * assign its direction in chan_rr_node_direction_ + */ + void add_opin_node(const RRNodeId& node, + const e_side& node_side); + + /* Add a node to the medium_node_ */ + void add_medium_node(const RRNodeId& medium_node); + + /* Sort all the incoming edges for routing channel rr_node */ + void sort_chan_node_in_edges(const RRGraphView& rr_graph); + /* Sort all the incoming edges for input pin rr_node */ + void sort_ipin_node_in_edges(const RRGraphView& rr_graph); + /* Build the lists of opin node for connection blocks. This is required after adding all the nodes */ + void build_cb_opin_nodes(const RRGraphView& rr_graph); + + public: /* Mutators: cleaners */ + void clear(); + + /* Clean the chan_width of a side */ + void clear_chan_nodes(const e_side& node_side); + + /* Clean the number of IPINs of a side */ + void clear_ipin_nodes(const e_side& node_side); + + /* Clean the number of OPINs of a side */ + void clear_opin_nodes(const e_side& node_side); + + /* Clean chan/opin/ipin nodes at one side */ + void clear_one_side(const e_side& node_side); + + private: /* Private Mutators: edge sorting */ + /* Sort all the incoming edges for one channel rr_node */ + void sort_chan_node_in_edges(const RRGraphView& rr_graph, + const e_side& chan_side, + const size_t& track_id); + + /* Sort all the incoming edges for one input pin rr_node */ + void sort_ipin_node_in_edges(const RRGraphView& rr_graph, + const e_side& chan_side, + const size_t& ipin_id); + private: /* internal functions */ + size_t get_track_id_first_short_connection(const RRGraphView& rr_graph, const e_side& node_side) const; + + private: /* internal validators */ + bool validate_num_sides() const; + bool validate_side(const e_side& side) const; + bool validate_track_id(const e_side& side, const size_t& track_id) const; + bool validate_cb_opin_node_id(const t_rr_type& cb_type, const e_side& side, const size_t& node_id) const; + bool validate_opin_node_id(const e_side& side, const size_t& node_id) const; + bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const; + bool validate_cb_type(const t_rr_type& cb_type) const; + size_t get_cb_opin_type_id(const t_rr_type& cb_type) const; + + private: /* Internal Data */ + /* Coordinator */ + vtr::Point coordinate_; + + /* Routing channel data + * Each GSB may have four sides of routing track nodes + */ + /* Node id in rr_graph denoting each routing track */ + std::vector chan_node_; + + /* Direction of a port when the channel node appear in the GSB module */ + std::vector> chan_node_direction_; + + /* Sequence of edge ids for each routing channel node, + * this is sorted by the location of edge source nodes in the context of GSB + * The edge sorting is critical to uniquify the routing modules in OpenFPGA + * This is due to that VPR allocate and sort edges randomly when building the rr_graph + * As a result, previous nodes of a chan node may be the same in different GSBs + * but their sequence is not. This will cause graph comparison to fail when uniquifying + * the routing modules. Therefore, edge sorting can be done inside the GSB + * + * Storage organization: + * [chan_side][chan_node][edge_id_in_gsb_context] + */ + std::vector>> chan_node_in_edges_; + /* Sequence of edge ids for each input pin node. Same rules applied as the channel nodes */ + std::vector>> ipin_node_in_edges_; + + /* Logic Block Inputs data */ + std::vector> ipin_node_; + + /* Logic Block Outputs data */ + std::vector> opin_node_; + /* Logic block outputs which directly drive IPINs in connection block, + * CBX -> array[0], CBY -> array[1] + * Each CB may have OPINs from all sides + */ + std::array, NUM_2D_SIDES>, 2> cb_opin_node_; + + /* Medium Nodes Data */ + std::vector medium_node_; + std::map medium_node_name_map_; +}; + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp new file mode 100644 index 00000000000..c1334d81d96 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp @@ -0,0 +1,335 @@ +/************************************************************************ + * This file contains a builder for the ChanNodeDetails data structure + * Different from VPR rr_graph builders, this builder aims to create a + * highly regular routing channel. Thus, it is called tileable, + * which brings significant advantage in producing large FPGA fabrics. + ***********************************************************************/ +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" + +/************************************************************************ + * Generate the number of tracks for each types of routing segments + * w.r.t. the frequency of each of segments and channel width + * Note that if we dertermine the number of tracks per type using + * chan_width * segment_frequency / total_freq may cause + * The total track num may not match the chan_width, + * therefore, we assign tracks one by one until we meet the frequency requirement + * In this way, we can assign the number of tracks with repect to frequency + ***********************************************************************/ +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, + const bool& use_full_seg_groups) { + std::vector result; + std::vector demand; + /* Make sure a clean start */ + result.resize(segment_inf.size()); + demand.resize(segment_inf.size()); + + /* Scale factor so we can divide by any length + * and still use integers */ + /* Get the sum of frequency */ + size_t scale = 1; + size_t freq_sum = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + scale *= segment_inf[iseg].length; + freq_sum += segment_inf[iseg].frequency; + } + size_t reduce = scale * freq_sum; + + /* Init assignments to 0 and set the demand values */ + /* Get the fraction of each segment type considering the frequency: + * num_track_per_seg = chan_width * (freq_of_seg / sum_freq) + */ + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + result[iseg] = 0; + demand[iseg] = scale * chan_width * segment_inf[iseg].frequency; + if (true == use_full_seg_groups) { + demand[iseg] /= segment_inf[iseg].length; + } + } + + /* check if the sum of num_tracks, matches the chan_width */ + /* Keep assigning tracks until we use them up */ + size_t assigned = 0; + size_t size = 0; + size_t imax = 0; + while (assigned < chan_width) { + /* Find current maximum demand */ + double max = 0; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + if (demand[iseg] > max) { + imax = iseg; + } + max = std::max(demand[iseg], max); + } + + /* Assign tracks to the type and reduce the types demand */ + size = (use_full_seg_groups ? segment_inf[imax].length : 1); + demand[imax] -= reduce; + result[imax] += size; + assigned += size; + } + + /* Undo last assignment if we were closer to goal without it */ + if ((assigned - chan_width) > (size / 2)) { + result[imax] -= size; + } + + return result; +} + +/************************************************************************ + * Adapt the number of channel width to a tileable routing architecture + ***********************************************************************/ +int adapt_to_tileable_route_chan_width(const int& chan_width, + const std::vector& segment_infs) { + int tileable_chan_width = 0; + + /* Estimate the number of segments per type by the given ChanW*/ + std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, + segment_infs, + true); /* Force to use the full segment group */ + /* Sum-up the number of tracks */ + for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { + tileable_chan_width += num_tracks_per_seg_type[iseg]; + } + + return tileable_chan_width; +} + +/************************************************************************ + * Build details of routing tracks in a channel + * The function will + * 1. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * + * 2. The starting point of each segment in the channel will be assigned + * For each segment group with same directionality (tracks have the same length), + * every L track will be a starting point (where L denotes the length of segments) + * In this case, if the number of tracks is not a multiple of L, + * indeed we may have some | Yes | No | + * +---------------------------------------+--------------+ + * | 1 | <--------MUX | Yes | No | + * +---------------------------------------+--------------+ + * | 2 | --------> | No | No | + * +---------------------------------------+--------------+ + * | 3 | <-------- | No | No | + * +---------------------------------------+--------------+ + * | 4 | --------> | No | No | + * +---------------------------------------+--------------+ + * | 5 | <-------- | No | No | + * +---------------------------------------+--------------+ + * | 7 | -------->MUX | No | Yes | + * +---------------------------------------+--------------+ + * | 8 | MUX<-------- | No | Yes | + * +---------------------------------------+--------------+ + * | 9 | MUX--------> | Yes | No | + * +---------------------------------------+--------------+ + * | 10 | <--------MUX | Yes | No | + * +---------------------------------------+--------------+ + * | 11 | -------->MUX | No | Yes | + * +------------------------------------------------------+ + * | 12 | <-------- | No | No | + * +------------------------------------------------------+ + * + * 3. SPECIAL for fringes: TOP|RIGHT|BOTTOM|RIGHT + * if device_side is NUM_SIDES, we assume this channel does not locate on borders + * All segments will start and ends with no exception + * + * 4. IMPORTANT: we should be aware that channel width maybe different + * in X-direction and Y-direction channels!!! + * So we will load segment details for different channels + ***********************************************************************/ +ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, + const size_t& max_seg_length, + const bool& force_start, + const bool& force_end, + const std::vector& segment_inf) { + ChanNodeDetails chan_node_details; + size_t actual_chan_width = find_unidir_routing_channel_width(chan_width); + VTR_ASSERT(0 == actual_chan_width % 2); + + /* Reserve channel width */ + chan_node_details.reserve(chan_width); + /* Return if zero width is forced */ + if (0 == actual_chan_width) { + return chan_node_details; + } + + /* Find the number of segments required by each group */ + std::vector num_tracks = get_num_tracks_per_seg_type(actual_chan_width / 2, segment_inf, false); + + /* Add node to ChanNodeDetails */ + size_t cur_track = 0; + size_t bend_num = 0; // The index for bend segments + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + if (!segment_inf[iseg].isbend){ + /* segment length will be set to maxium segment length if this is a longwire */ + size_t seg_len = segment_inf[iseg].length; + if (true == segment_inf[iseg].longline) { + seg_len = max_seg_length; + } + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + /* Every first track of a group of Length-N wires, we set a starting point */ + if (0 == itrack % seg_len) { + seg_start = true; + } + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ + if ((seg_len - 1 == itrack % seg_len) + || (itrack == num_tracks[iseg] - 1)) { + seg_end = true; + } + /* Since this is a unidirectional routing architecture, + * Add a pair of tracks, 1 INC track and 1 DEC track + */ + int seg_index = segment_inf[iseg].seg_index; + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len, seg_start, seg_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len, seg_start, seg_end); + cur_track++; + } + } + else{ // bend segment + bend_num++; + VTR_ASSERT(segment_inf[iseg].isbend); + std::vector seg_len = segment_inf[iseg].part_len; + std::vector bend = segment_inf[iseg].bend; + VTR_ASSERT(seg_len.size() == 2); // Only support one bend position for a segment. + + std::vector num_tracks_bend; + /* Each bend part tracks number * + * For example, a length-5 segment with bend pattern: <- - U -> has 20 tracks. * + * Its num_tracks_bend is [20 * 3/5, 20 * 2/5] = [12, 8] */ + for(size_t i = 0; i < seg_len.size(); i++) + num_tracks_bend.push_back(num_tracks[iseg] * seg_len[i] / segment_inf[iseg].length); + + VTR_ASSERT(num_tracks_bend[0] + num_tracks_bend[1] == num_tracks[iseg]); + + for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) { + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; // seg_bend_start = 0 means not a bend start. + // seg_bend_start = i (i > 0) means a bend start for bend segment i. + size_t seg_bend_end = 0; // The same as seg_bend_start. + // Tracks has same seg_bend_start and seg_bend_end values will be + // connected by a delayless switch. + /* Every first track of a group of Length-N wires, we set a starting point */ + if (0 == itrack % segment_inf[iseg].length) { + seg_start = true; + } + /* Number seg_len[0] track of a group of Length-N wires, we set a bend start point */ + if (seg_len[0] == int(itrack) % segment_inf[iseg].length) { + seg_start = true; + seg_bend_start = bend_num; + } + /* Number seg_len[0] - 1 track of a group of Length-N wires, we set a bend end point */ + if (seg_len[0] - 1 == int(itrack) % segment_inf[iseg].length) { + seg_end = true; + seg_bend_end = bend_num; + } + /* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */ + if ((segment_inf[iseg].length - 1 == int(itrack) % segment_inf[iseg].length) + || (itrack == num_tracks[iseg] - 1)) { + seg_end = true; + } + + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + } + + /*for (size_t itrack = 0; itrack < num_tracks_bend[0]; ++itrack) { + + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; + size_t seg_bend_end = 0; + + if (0 == itrack % seg_len[0]) { + seg_start = true; + } + + if ((seg_len[0] - 1 == itrack % seg_len[0]) + || (itrack == num_tracks_bend[0] - 1)) { + seg_end = true; + seg_bend_end = bend_num; + } + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[0], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + + } + for (size_t itrack = 0; itrack < num_tracks_bend[1]; ++itrack) { + + bool seg_start = false; + bool seg_end = false; + size_t seg_bend_start = 0; + size_t seg_bend_end = 0; + + if (0 == itrack % seg_len[1]) { + seg_start = true; + seg_bend_start = bend_num; + } + + if ((seg_len[1] - 1 == itrack % seg_len[1]) + || (itrack == num_tracks_bend[1] - 1)) { + seg_end = true; + } + int seg_index = segment_inf[iseg].seg_index; + + chan_node_details.add_track(cur_track, Direction::INC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + + chan_node_details.add_track(cur_track, Direction::DEC, seg_index, seg_len[1], seg_start, seg_end, seg_bend_start, seg_bend_end); + cur_track++; + + }*/ + } + } + /* Check if all the tracks have been satisified */ + VTR_ASSERT(cur_track == actual_chan_width); + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_start) { + /* INC should all start */ + chan_node_details.set_tracks_start(Direction::INC); + /* DEC should all end */ + chan_node_details.set_tracks_end(Direction::DEC); + } + + /* If this is on the border of a device/heterogeneous blocks, segments should start/end */ + if (true == force_end) { + /* INC should all end */ + chan_node_details.set_tracks_end(Direction::INC); + /* DEC should all start */ + chan_node_details.set_tracks_start(Direction::DEC); + } + + return chan_node_details; +} diff --git a/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h new file mode 100644 index 00000000000..5ce79b61221 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_chan_details_builder.h @@ -0,0 +1,27 @@ +#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H +#define TILEABLE_CHAN_DETAILS_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include +#include "physical_types.h" +#include "chan_node_details.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +std::vector get_num_tracks_per_seg_type(const size_t& chan_width, + const std::vector& segment_inf, + const bool& use_full_seg_groups); + +int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector& segment_inf); + +ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, + const size_t& max_seg_length, + const bool& force_start, + const bool& force_end, + const std::vector& segment_inf); + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp new file mode 100644 index 00000000000..d8ead463d9e --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp @@ -0,0 +1,337 @@ +/************************************************************************ + * This file contains a builder for the complex rr_graph data structure + * Different from VPR rr_graph builders, this builder aims to create a + * highly regular rr_graph, where each Connection Block (CB), Switch + * Block (SB) is the same (except for those on the borders). Thus, the + * rr_graph is called tileable, which brings significant advantage in + * producing large FPGA fabrics. + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_time.h" +#include "vtr_log.h" +#include "vtr_memory.h" + +#include "vpr_error.h" +#include "vpr_utils.h" + +#include "rr_graph.h" +#include "check_rr_graph.h" +#include "get_parallel_segs.h" +#include "device_grid_annotation.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_node_builder.h" +#include "tileable_rr_graph_edge_builder.h" +#include "tileable_rr_graph_builder.h" + +#include "globals.h" + +/************************************************************************ + * Main function of this file + * Builder for a detailed uni-directional tileable rr_graph + * Global graph is not supported here, the VPR rr_graph generator can be used + * It follows the procedures to complete the rr_graph generation + * 1. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * 2. Estimate the number of nodes in the rr_graph + * This will estimate the number of + * a. IPINs, input pins of each grid + * b. OPINs, output pins of each grid + * c. SOURCE, virtual node which drives OPINs + * d. SINK, virtual node which is connected to IPINs + * e. CHANX and CHANY, routing segments of each channel + * 3. Create the connectivity of OPINs + * a. Evenly assign connections to OPINs to routing tracks + * b. the connection pattern should be same across the fabric + * 4. Create the connectivity of IPINs + * a. Evenly assign connections from routing tracks to IPINs + * b. the connection pattern should be same across the fabric + * 5. Create the switch block patterns, + * It is based on the type of switch block, the supported patterns are + * a. Disjoint, which connects routing track (i)th from (i)th and (i)th routing segments + * b. Universal, which connects routing track (i)th from (i)th and (M-i)th routing segments + * c. Wilton, which rotates the connection of Disjoint by 1 track + * 6. Allocate rr_graph, fill the node information + * For each node, fill + * a. basic information: coordinate(xlow, xhigh, ylow, yhigh), ptc_num + * b. edges (both incoming and outcoming) + * c. handle direct-connections + * 7. Build fast look-up for the rr_graph + * 8. Allocate external data structures + * a. cost_index + * b. RC tree + ***********************************************************************/ + +void build_tileable_unidir_rr_graph(const std::vector& types, + const DeviceGrid& grids, + const t_chan_width& chan_width, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const std::vector& segment_inf, + const int& delayless_switch, + const int& wire_to_arch_ipin_switch, + const float R_minW_nmos, + const float R_minW_pmos, + const enum e_base_cost_type& base_cost_type, + const std::vector& directs, + int* wire_to_rr_ipin_switch, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + int* Warnings) { + vtr::ScopedStartFinishTimer timer("Build tileable routing resource graph"); + + /* Reset warning flag */ + *Warnings = RR_GRAPH_NO_WARN; + + /* Create a matrix of grid */ + /* Create a vector of channel width, we support X-direction and Y-direction has different W */ + vtr::Point device_chan_width(chan_width.x_max, chan_width.y_max); + + VTR_LOG("X-direction routing channel width is %lu\n", device_chan_width.x()); + VTR_LOG("Y-direction routing channel width is %lu\n", device_chan_width.y()); + + /* Get a mutable device ctx so that we have a mutable rr_graph */ + DeviceContext& device_ctx = g_vpr_ctx.mutable_device(); + + /* Annotate the device grid on the boundry */ + DeviceGridAnnotation device_grid_annotation(device_ctx.grid, perimeter_cb); + + /* The number of segments are in general small, reserve segments may not bring + * significant memory efficiency */ + device_ctx.rr_graph_builder.reserve_segments(segment_inf.size()); + /* Create the segments */ + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + device_ctx.rr_graph_builder.add_rr_segment(segment_inf[iseg]); + } + + /* TODO: Load architecture switch to rr_graph switches + * Draft the switches as internal data of RRGraph object + * These are temporary switches copied from arch switches + * We use them to build the edges + * We will reset all the switches in the function + * alloc_and_load_rr_switch_inf() + */ + /* TODO: Spot the switch id in the architecture switch list */ + RRSwitchId wire_to_ipin_rr_switch = RRSwitchId::INVALID(); + RRSwitchId delayless_rr_switch = RRSwitchId::INVALID(); + + device_ctx.rr_graph_builder.reserve_switches(device_ctx.arch_switch_inf.size()); + /* Create the switches */ + for (size_t iswitch = 0; iswitch < device_ctx.arch_switch_inf.size(); ++iswitch) { + const t_rr_switch_inf& temp_rr_switch = create_rr_switch_from_arch_switch(device_ctx.arch_switch_inf[iswitch], R_minW_nmos, R_minW_pmos); + RRSwitchId rr_switch = device_ctx.rr_graph_builder.add_rr_switch(temp_rr_switch); + if ((int)iswitch == wire_to_arch_ipin_switch) { + wire_to_ipin_rr_switch = rr_switch; + } + if ((int)iswitch == delayless_switch) { + delayless_rr_switch = rr_switch; + } + } + + /* Validate the special switches */ + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(wire_to_ipin_rr_switch)); + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(delayless_rr_switch)); + + /* A temp data about the driver switch ids for each rr_node */ + vtr::vector rr_node_driver_switches; + + /* A temp data about the track ids for each CHANX and CHANY rr_node */ + std::map> rr_node_track_ids; + + /* Get the routing segments on X-axis and Y-axis separately */ + t_unified_to_parallel_seg_index segment_index_map; + std::vector segment_inf_x = get_parallel_segs(segment_inf, segment_index_map, X_AXIS, true); + std::vector segment_inf_y = get_parallel_segs(segment_inf, segment_index_map, Y_AXIS, true); + + /* Get vib grid */ + const auto& vib_grid = device_ctx.vib_grid; + //const bool is_vib_arch = !device_ctx.arch->vib_infs.empty(); + + /************************ + * Allocate the rr_nodes + ************************/ + alloc_tileable_rr_graph_nodes(device_ctx.rr_graph_builder, + rr_node_driver_switches, + grids, vib_grid, 0, + device_chan_width, + segment_inf_x, segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + /************************ + * Create all the rr_nodes + ************************/ + create_tileable_rr_graph_nodes(device_ctx.rr_graph, + device_ctx.rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + device_ctx.rr_rc_data, + grids, vib_grid, 0, + device_chan_width, + segment_inf_x, segment_inf_y, + segment_index_map, + wire_to_ipin_rr_switch, + delayless_rr_switch, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + /************************************************************************ + * Create the connectivity of OPINs + * a. Evenly assign connections to OPINs to routing tracks + * b. the connection pattern should be same across the fabric + * + * Create the connectivity of IPINs + * a. Evenly assign connections from routing tracks to IPINs + * b. the connection pattern should be same across the fabric + ***********************************************************************/ + /* Global routing uses a single longwire track */ + int max_chan_width = find_unidir_routing_channel_width(chan_width.max); + VTR_ASSERT(max_chan_width > 0); + + /* get maximum number of pins across all blocks */ + int max_pins = types[0].num_pins; + for (const auto& type : types) { + if (is_empty_type(&type)) { + continue; + } + + if (type.num_pins > max_pins) { + max_pins = type.num_pins; + } + } + + /* Fc assignment still uses the old function from VPR. + * Should use tileable version so that we have can have full control + */ + std::vector num_tracks = get_num_tracks_per_seg_type(max_chan_width / 2, segment_inf, false); + int* sets_per_seg_type = (int*)vtr::malloc(sizeof(int) * segment_inf.size()); + VTR_ASSERT(num_tracks.size() == segment_inf.size()); + for (size_t iseg = 0; iseg < num_tracks.size(); ++iseg) { + sets_per_seg_type[iseg] = num_tracks[iseg]; + } + + bool Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_in; + Fc_in = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, + e_fc_type::IN, UNI_DIRECTIONAL, &Fc_clipped, false); + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + + Fc_clipped = false; + /* [0..num_types-1][0..num_pins-1] */ + std::vector> Fc_out; + Fc_out = alloc_and_load_actual_fc(types, max_pins, segment_inf, sets_per_seg_type, (const t_chan_width*)&chan_width, + e_fc_type::OUT, UNI_DIRECTIONAL, &Fc_clipped, false); + + if (Fc_clipped) { + *Warnings |= RR_GRAPH_WARN_FC_CLIPPED; + } + + /************************************************************************ + * Build the connections tile by tile: + * We classify rr_nodes into a general switch block (GSB) data structure + * where we create edges to each rr_nodes in the GSB with respect to + * Fc_in and Fc_out, switch block patterns + * In addition, we will also handle direct-connections: + * Add edges that bridge OPINs and IPINs to the rr_graph + ***********************************************************************/ + /* Create edges for a tileable rr_graph */ + build_rr_graph_edges(device_ctx.rr_graph, + device_ctx.rr_graph_builder, + rr_node_driver_switches, + grids, vib_grid, 0, + device_chan_width, + segment_inf, segment_inf_x, segment_inf_y, + Fc_in, Fc_out, + sb_type, Fs, sb_subtype, subFs, + perimeter_cb, + opin2all_sides, concat_wire, + wire_opposite_side, + delayless_rr_switch); + + /************************************************************************ + * Build direction connection lists + * TODO: use tile direct builder + ***********************************************************************/ + /* Create data structure of direct-connections */ + t_clb_to_clb_directs* clb_to_clb_directs = NULL; + if (!directs.empty()) { + clb_to_clb_directs = alloc_and_load_clb_to_clb_directs(directs, delayless_switch); + } + std::vector clb2clb_directs; + for (size_t idirect = 0; idirect < directs.size(); ++idirect) { + /* Sanity checks on rr switch id */ + VTR_ASSERT(true == device_ctx.rr_graph.valid_switch(RRSwitchId(clb_to_clb_directs[idirect].switch_index))); + clb2clb_directs.push_back(clb_to_clb_directs[idirect]); + } + + build_rr_graph_direct_connections(device_ctx.rr_graph, device_ctx.rr_graph_builder, device_ctx.grid, 0, + directs, clb2clb_directs); + + /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, + * based on their fanin in the rr graph. This routine also adjusts the rr nodes to point to these new rr switches */ + device_ctx.rr_graph_builder.init_fan_in(); + alloc_and_load_rr_switch_inf(device_ctx.rr_graph_builder, device_ctx.switch_fanin_remap, device_ctx.all_sw_inf, R_minW_nmos, R_minW_pmos, wire_to_arch_ipin_switch, wire_to_rr_ipin_switch); + + /* Save the channel widths for the newly constructed graph */ + device_ctx.chan_width = chan_width; + + /* Save the track ids for tileable routing resource graph */ + device_ctx.rr_node_track_ids = rr_node_track_ids; + + /* Build incoming edges */ + device_ctx.rr_graph_builder.partition_edges(); + device_ctx.rr_graph_builder.build_in_edges(); + + /************************************************************************ + * Allocate external data structures + * a. cost_index + * b. RC tree + ***********************************************************************/ + rr_graph_externals(segment_inf, segment_inf_x, segment_inf_y, + *wire_to_rr_ipin_switch, base_cost_type); + + /************************************************************************ + * Sanitizer for the rr_graph, check connectivities of rr_nodes + ***********************************************************************/ + /* Essential check for rr_graph, build look-up and */ + if (false == device_ctx.rr_graph_builder.validate()) { + /* Error out if built-in validator of rr_graph fails */ + vpr_throw(VPR_ERROR_ROUTE, + __FILE__, + __LINE__, + "Fundamental errors occurred when validating rr_graph object!\n"); + } + + /* No clock network support yet; Does not support flatten rr_graph yet */ + + check_rr_graph(device_ctx.rr_graph, types, device_ctx.rr_indexed_data, grids, vib_grid, device_ctx.chan_width, GRAPH_UNIDIR, false); + + + /************************************************************************ + * Free all temp stucts + ***********************************************************************/ + free(sets_per_seg_type); + + if (nullptr != clb_to_clb_directs) { + free(clb_to_clb_directs); + } +} diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h new file mode 100644 index 00000000000..2dd4d78b75e --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_builder.h @@ -0,0 +1,39 @@ +#ifndef TILEABLE_RR_GRAPH_BUILDER_H +#define TILEABLE_RR_GRAPH_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "physical_types.h" +#include "device_grid.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +void build_tileable_unidir_rr_graph(const std::vector& types, + const DeviceGrid& grids, + const t_chan_width& chan_width, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const std::vector& segment_inf, + const int& delayless_switch, + const int& wire_to_arch_ipin_switch, + const float R_minW_nmos, + const float R_minW_pmos, + const enum e_base_cost_type& base_cost_type, + const std::vector& directs, + int* wire_to_rr_ipin_switch, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + int* Warnings); + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp new file mode 100644 index 00000000000..d242a0b9bf1 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp @@ -0,0 +1,593 @@ +/************************************************************************ + * This file contains functions that are used to build edges + * between nodes of a tileable routing resource graph + ***********************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +#include "vpr_utils.h" + +#include "rr_graph_builder_utils.h" +#include "tileable_rr_graph_gsb.h" +#include "tileable_rr_graph_edge_builder.h" + +/************************************************************************ + * Build the edges for all the SOURCE and SINKs nodes: + * 1. create edges between SOURCE and OPINs + ***********************************************************************/ +void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + size_t& num_edges_to_create) { + size_t edge_count = 0; + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non OPIN nodes */ + if (OPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short src_node_class_num = get_grid_pin_class_index(grids, layer, xlow, ylow, + rr_graph.node_pin_num(node)); + /* Create edges between SOURCE and OPINs */ + t_physical_tile_loc tile_loc(xlow, ylow, layer); + RRNodeId src_node = rr_graph.node_lookup().find_node(layer, + xlow - grids.get_width_offset(tile_loc), + ylow - grids.get_height_offset(tile_loc), + SOURCE, src_node_class_num); + VTR_ASSERT(true == rr_graph.valid_node(src_node)); + + /* add edges to the src_node */ + rr_graph_builder.create_edge(src_node, node, rr_node_driver_switches[node], false); + edge_count++; + } + /* Allocate edges for all the source nodes */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; +} + +/************************************************************************ + * Build the edges for all the SINKs nodes: + * 1. create edges between IPINs and SINKs + ***********************************************************************/ +void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + size_t& num_edges_to_create) { + size_t edge_count = 0; + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass all the non IPIN nodes */ + if (IPIN != rr_graph.node_type(node)) { + continue; + } + /* Now, we have an OPIN node, we get the source node index */ + short xlow = rr_graph.node_xlow(node); + short ylow = rr_graph.node_ylow(node); + short sink_node_class_num = get_grid_pin_class_index(grids, layer, xlow, ylow, + rr_graph.node_pin_num(node)); + /* 1. create edges between IPINs and SINKs */ + t_physical_tile_loc tile_loc(xlow, ylow, 0); + const RRNodeId& sink_node = rr_graph.node_lookup().find_node(layer, + xlow - grids.get_width_offset(tile_loc), + ylow - grids.get_height_offset(tile_loc), + SINK, sink_node_class_num, TOTAL_2D_SIDES[0]); + VTR_ASSERT(true == rr_graph.valid_node(sink_node)); + + /* add edges to connect the IPIN node to SINK nodes */ + rr_graph_builder.create_edge(node, sink_node, rr_node_driver_switches[sink_node], false); + edge_count++; + } + /* Allocate edges for all the source nodes */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; +} + +/************************************************************************ + * Build the edges of each rr_node tile by tile: + * We classify rr_nodes into a general switch block (GSB) data structure + * where we create edges to each rr_nodes in the GSB with respect to + * Fc_in and Fc_out, switch block patterns + * For each GSB: + * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) + * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) + * 3. create edges between OPINs and IPINs (direct-connections) + ***********************************************************************/ +void build_rr_graph_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch) { + + if (!vib_grid.is_empty()) { + build_rr_graph_vib_edges(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + grids, + vib_grid, + layer, + device_chan_width, + segment_inf, + segment_inf_x, + segment_inf_y, + perimeter_cb, + delayless_switch); + } + else { + build_rr_graph_regular_edges(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + grids, + layer, + device_chan_width, + segment_inf, + segment_inf_x, + segment_inf_y, + Fc_in, + Fc_out, + sb_type, + Fs, + sb_subtype, + subFs, + perimeter_cb, + opin2all_sides, + concat_wire, + wire_opposite_side); + } + /* Create map from medium mux name to index */ + // std::vector>>> medium_mux_name2medium_index; + + // if (!vib_grid.is_empty()) { + // medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); + // for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { + // medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); + + // for (size_t ix = 0; ix < vib_grid.width(); ix++) { + // medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); + + // for (size_t iy = 0; iy < vib_grid.height(); iy++) { + // std::map mux_name_map; + + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { + // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); + // } + // medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; + // } + // } + // } + + // } + + + // size_t num_edges_to_create = 0; + // /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + // build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + // build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + + // vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + + // /* Go Switch Block by Switch Block */ + // for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + // for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + // //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + // vtr::Point gsb_coord(ix, iy); + + // /* adapt the bend_conn */ + // t_bend_track2track_map sb_bend_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_bend_conn = build_bend_track_to_track_map(grids, rr_graph_builder, rr_graph, + // device_chan_width, segment_inf, + // layer, gsb_coord, delayless_switch, rr_node_driver_switches); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + // if (!vib_grid.is_empty()) { + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord, medium_mux_name2medium_index); + // build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + + // rr_graph_builder.build_edges(true); + // } + // else { + // /* adapt the track_to_ipin_lookup for the GSB nodes */ + // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + // track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + // /* adapt the opin_to_track_map for the GSB nodes */ + // t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + // opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + // /* adapt the switch_block_conn for the GSB nodes */ + // t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + // sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + // segment_inf); + + // /* Build edges for a GSB */ + // build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + // sb_bend_conn, track2ipin_map, opin2track_map, + // sb_conn, rr_node_driver_switches, num_edges_to_create); + // /* Finish this GSB, go to the next*/ + // rr_graph_builder.build_edges(true); + // } + // } + // } + + // /* Process boundary */ + // if (!vib_grid.is_empty()) { + // size_t ix, iy; + // // process top boundary + // iy = gsb_range.y() + 1; // == grids.height() - 1 + // for (ix = 0; ix < gsb_range.x() + 1; ++ix) { + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // //rr_graph_builder.build_edges(true); + + // } + + // // process right boundary + // ix = gsb_range.x() + 1; + // for (iy = 0; iy < gsb_range.y() + 1; ++iy) { + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // //rr_graph_builder.build_edges(true); + + // } + + // // process right-top corner + // ix = gsb_range.x() + 1; + // iy = gsb_range.y() + 1; + + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + // rr_graph_builder.build_edges(true); + // } +} + +/************************************************************************ + * Build direct edges for Grids * + ***********************************************************************/ +void build_rr_graph_direct_connections(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { + continue; + } + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { + continue; + } + vtr::Point from_grid_coordinate(ix, iy); + build_direct_connections_for_one_gsb(rr_graph, + rr_graph_builder, + grids, layer, + from_grid_coordinate, + directs, clb_to_clb_directs); + } + } +} + +void build_rr_graph_vib_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const bool& perimeter_cb, + const RRSwitchId& delayless_switch) { + /* Create map from medium mux name to index */ + // std::vector>>> medium_mux_name2medium_index; + // medium_mux_name2medium_index.resize(vib_grid.get_num_layers()); + // for (size_t i_layer = 0; i_layer < vib_grid.get_num_layers(); i_layer++) { + // medium_mux_name2medium_index[i_layer].resize(vib_grid.width()); + + // for (size_t ix = 0; ix < vib_grid.width(); ix++) { + // medium_mux_name2medium_index[i_layer][ix].resize(vib_grid.height()); + + // for (size_t iy = 0; iy < vib_grid.height(); iy++) { + // std::map mux_name_map; + + // for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) { + // mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux); + // } + // medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map; + // } + // } + // } + + size_t num_edges_to_create = 0; + /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + + vtr::Point gsb_range(grids.width() - 2, grids.height() - 2); + + /* Go Switch Block by Switch Block */ + for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + vtr::Point gsb_coord(ix, iy); + + /* adapt the bend_conn */ + t_bend_track2track_map sb_bend_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_bend_conn = build_bend_track_to_track_map(grids, rr_graph_builder, rr_graph, + segment_inf, + layer, gsb_coord, delayless_switch, rr_node_driver_switches); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, gsb_coord); + build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + + rr_graph_builder.build_edges(true); + + // else { + // /* adapt the track_to_ipin_lookup for the GSB nodes */ + // t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + // track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + // /* adapt the opin_to_track_map for the GSB nodes */ + // t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + // opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + // /* adapt the switch_block_conn for the GSB nodes */ + // t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + // sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + // sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + // segment_inf); + + // /* Build edges for a GSB */ + // build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + // sb_bend_conn, track2ipin_map, opin2track_map, + // sb_conn, rr_node_driver_switches, num_edges_to_create); + // /* Finish this GSB, go to the next*/ + // rr_graph_builder.build_edges(true); + // } + } + } + + /* Process boundary */ + + size_t ix, iy; + // process top boundary + iy = gsb_range.y() + 1; // == grids.height() - 1 + for (ix = 0; ix < gsb_range.x() + 1; ++ix) { + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix, iy - 1); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + num_edges_to_create += edge_count; + //rr_graph_builder.build_edges(true); + + } + + // process right boundary + ix = gsb_range.x() + 1; + for (iy = 0; iy < gsb_range.y() + 1; ++iy) { + vtr::Point actual_coord(ix, iy); + vtr::Point gsb_coord(ix - 1, iy); + + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); + + + t_vib_map vib_map; + vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord); + //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + num_edges_to_create += edge_count; + //rr_graph_builder.build_edges(true); + + } + + // process right-top corner + // ix = gsb_range.x() + 1; + // iy = gsb_range.y() + 1; + + // vtr::Point actual_coord(ix, iy); + // vtr::Point gsb_coord(ix - 1, iy - 1); + + // /* Create a GSB object */ + // const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + // device_chan_width, segment_inf_x, segment_inf_y, + // layer, gsb_coord, perimeter_cb); + + + // t_vib_map vib_map; + // vib_map = build_vib_map(rr_graph, grids, vib_grid, rr_gsb, segment_inf, layer, gsb_coord, actual_coord, medium_mux_name2medium_index); + // //build_edges_for_one_tileable_vib(rr_graph_builder, vib_map, sb_bend_conn, rr_node_driver_switches, num_edges_to_create); + // size_t edge_count = 0; + // for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + // for (auto to_node : iter->second) { + // rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + // edge_count++; + // } + // } + // num_edges_to_create += edge_count; + rr_graph_builder.build_edges(true); + +} + +void build_rr_graph_regular_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side) { + size_t num_edges_to_create = 0; + /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ + build_rr_graph_edges_for_source_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + build_rr_graph_edges_for_sink_nodes(rr_graph, rr_graph_builder, rr_node_driver_switches, grids, layer, num_edges_to_create); + + vtr::Point gsb_range(grids.width() - 1, grids.height() - 1); + + /* Go Switch Block by Switch Block */ + for (size_t ix = 0; ix <= gsb_range.x(); ++ix) { + for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { + //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); + + vtr::Point gsb_coord(ix, iy); + /* Create a GSB object */ + const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph, + device_chan_width, segment_inf_x, segment_inf_y, + layer, gsb_coord, perimeter_cb); + + /* adapt the track_to_ipin_lookup for the GSB nodes */ + t_track2pin_map track2ipin_map; /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ + track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in); + + /* adapt the opin_to_track_map for the GSB nodes */ + t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */ + opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides); + + /* adapt the switch_block_conn for the GSB nodes */ + t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, concat_wire, wire_opposite_side, + segment_inf); + + /* Build edges for a GSB */ + /* Build edges for a GSB */ + build_edges_for_one_tileable_rr_gsb(rr_graph_builder, rr_gsb, + track2ipin_map, opin2track_map, + sb_conn, rr_node_driver_switches, num_edges_to_create); + /* Finish this GSB, go to the next*/ + rr_graph_builder.build_edges(true); + } + } +} diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h new file mode 100644 index 00000000000..a697c689be5 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.h @@ -0,0 +1,100 @@ +#ifndef TILEABLE_RR_GRAPH_EDGE_BUILDER_H +#define TILEABLE_RR_GRAPH_EDGE_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +/* Headers from vtrutil library */ +#include "vtr_ndmatrix.h" +#include "vtr_geometry.h" + +#include "physical_types.h" +#include "device_grid.h" +#include "rr_graph_obj.h" +#include "rr_graph_type.h" +#include "rr_graph_view.h" +#include "rr_graph.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +void build_rr_graph_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side, + const RRSwitchId& delayless_switch); + +void build_rr_graph_direct_connections(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const std::vector& directs, + const std::vector& clb_to_clb_directs); + +void build_rr_graph_edges_for_source_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + size_t& num_edges_to_create); + +void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + size_t& num_edges_to_create); + +void build_rr_graph_vib_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const bool& perimeter_cb, + const RRSwitchId& delayless_switch); + +void build_rr_graph_regular_edges(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& device_chan_width, + const std::vector& segment_inf, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const std::vector>& Fc_in, + const std::vector>& Fc_out, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& perimeter_cb, + const bool& opin2all_sides, + const bool& concat_wire, + const bool& wire_opposite_side); + +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp new file mode 100644 index 00000000000..a0e8494718a --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -0,0 +1,2149 @@ +/************************************************************************ + * This file contains a builder for track-to-track connections inside a + * tileable General Switch Block (GSB). + ***********************************************************************/ +#include +#include +#include + +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" + +/* Headers from openfpgautil library */ +#include "openfpga_side_manager.h" + +#include "vpr_utils.h" +#include "rr_graph_view_util.h" +#include "openfpga_rr_graph_utils.h" +#include "rr_graph_builder_utils.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_gsb.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" +#include "vtr_geometry.h" + +/************************************************************************ + * Internal data structures + ***********************************************************************/ +typedef std::vector> t_track_group; + +/************************************************************************ + * A enumeration to list the status of a track inside a GSB + * 1. start; 2. end; 3. passing + * This is used to group tracks which ease the building of + * track-to-track mapping matrix + ***********************************************************************/ +enum e_track_status { + TRACK_START, + TRACK_END, + TRACK_PASS, + NUM_TRACK_STATUS /* just a place holder to get the number of status */ +}; + +/************************************************************************ + * Check if a track starts from this GSB or not + * (xlow, ylow) should be same as the GSB side coordinate + * + * Check if a track ends at this GSB or not + * (xhigh, yhigh) should be same as the GSB side coordinate + ***********************************************************************/ +static enum e_track_status determine_track_status_of_gsb(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& gsb_side, + const size_t& track_id) { + enum e_track_status track_status = TRACK_PASS; + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + /* Get the coordinate of where the track starts */ + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* INC_DIRECTION start_track: (xlow, ylow) should be same as the GSB side coordinate */ + /* DEC_DIRECTION start_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + if ((track_start.x() == side_coordinate.x()) + && (track_start.y() == side_coordinate.y()) + && (OUT_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id))) { + /* Double check: start track should be an OUTPUT PORT of the GSB */ + track_status = TRACK_START; + } + + /* Get the coordinate of where the track ends */ + vtr::Point track_end = get_track_rr_node_end_coordinate(rr_graph, track_node); + + /* INC_DIRECTION end_track: (xhigh, yhigh) should be same as the GSB side coordinate */ + /* DEC_DIRECTION end_track: (xlow, ylow) should be same as the GSB side coordinate */ + if ((track_end.x() == side_coordinate.x()) + && (track_end.y() == side_coordinate.y()) + && (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, track_id))) { + /* Double check: end track should be an INPUT PORT of the GSB */ + track_status = TRACK_END; + } + + return track_status; +} + +/************************************************************************ + * Check if the GSB is in the Connection Block (CB) population list of the segment + * SB population of a L4 wire: 1 0 0 1 + * + * +----+ +----+ +----+ +----+ + * | CB |--->| CB |--->| CB |--->| CB | + * +----+ +----+ +----+ +----+ + * Engage CB connection Yes No No Yes + * + * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track + * Use the offset to check if the tracks should engage in this GSB connection + ***********************************************************************/ +static bool is_gsb_in_track_cb_population(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + RRNodeId track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].cb.size()); + + /* Get the SB population */ + bool in_cb_population = false; + if (true == segment_inf[size_t(seg_id)].cb[offset]) { + in_cb_population = true; + } + + return in_cb_population; +} + +/************************************************************************ + * Check if the GSB is in the Switch Block (SB) population list of the segment + * SB population of a L3 wire: 1 0 0 1 + * + * +----+ +----+ +----+ +----+ + * | SB |--->| SB |--->| SB |--->| SB | + * +----+ +----+ +----+ +----+ + * Engage SB connection Yes No No Yes + * + * We will find the offset between gsb_side_coordinate and (xlow,ylow) of the track + * Use the offset to check if the tracks should engage in this GSB connection + ***********************************************************************/ +static bool is_gsb_in_track_sb_population(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const e_side& gsb_side, + const int& track_id, + const std::vector& segment_inf) { + /* Get the rr_node */ + const RRNodeId& track_node = rr_gsb.get_chan_node(gsb_side, track_id); + /* Get the coordinates */ + vtr::Point side_coordinate = rr_gsb.get_side_block_coordinate(gsb_side); + + vtr::Point track_start = get_track_rr_node_start_coordinate(rr_graph, track_node); + + /* Get the offset */ + size_t offset = std::abs((int)side_coordinate.x() - (int)track_start.x()) + + std::abs((int)side_coordinate.y() - (int)track_start.y()); + + /* Get segment id */ + RRSegmentId seg_id = rr_gsb.get_chan_node_segment(gsb_side, track_id); + /* validate offset */ + VTR_ASSERT(offset < segment_inf[size_t(seg_id)].sb.size()); + + /* Get the SB population */ + bool in_sb_population = false; + if (true == segment_inf[size_t(seg_id)].sb[offset]) { + in_sb_population = true; + } + + return in_sb_population; +} + +/************************************************************************ + * Create a list of track_id based on the to_track and num_to_tracks + * We consider the following list [to_track, to_track + Fs/3 - 1] + * if the [to_track + Fs/3 - 1] exceeds the num_to_tracks, we start over from 0! + ***********************************************************************/ +static std::vector get_to_track_list(const int& Fs, const int& to_track, const int& num_to_tracks) { + std::vector to_tracks; + + for (int i = 0; i < Fs; i = i + 3) { + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ + int to_track_i = to_track + i; + /* make sure the track id is still in range */ + if (to_track_i > num_to_tracks - 1) { + to_track_i = to_track_i % num_to_tracks; + } + /* Ensure we are in the range */ + VTR_ASSERT(to_track_i < num_to_tracks); + /* from track must be connected */ + to_tracks.push_back(to_track_i); + } + return to_tracks; +} + +/************************************************************************ + * This function aims to return the track indices that drive the from_track + * in a Switch Block + * The track_ids to return will depend on different topologies of SB + * SUBSET, UNIVERSAL, and WILTON. + ***********************************************************************/ +static std::vector get_switch_block_to_track_id(const e_switch_block_type& switch_block_type, + const int& Fs, + const e_side& from_side, + const int& from_track, + const e_side& to_side, + const int& num_to_tracks) { + /* This routine returns the track number to which the from_track should + * connect. It supports any Fs % 3 == 0, switch blocks. + */ + std::vector to_tracks; + + /* TODO: currently, for Fs > 3, I always search the next from_track until Fs is satisfied + * The optimal track selection should be done in a more scientific way!!! + */ + VTR_ASSERT(0 == Fs % 3); + + /* Adapt from_track to fit in the range of num_to_tracks */ + size_t actual_from_track = from_track % num_to_tracks; + + switch (switch_block_type) { + case SUBSET: /* NB: Global routing uses SUBSET too */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + /* Finish, we return */ + return to_tracks; + case UNIVERSAL: + if ((from_side == LEFT) + || (from_side == RIGHT)) { + /* For the prev_side, to_track is from_track + * For the next_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ + SideManager side_manager(from_side); + if ((to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_counterclockwise())) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_clockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + + if ((from_side == TOP) + || (from_side == BOTTOM)) { + /* For the next_side, to_track is from_track + * For the prev_side, to_track is num_to_tracks - 1 - from_track + * For the opposite_side, to_track is always from_track + */ + SideManager side_manager(from_side); + if ((to_side == side_manager.get_opposite()) + || (to_side == side_manager.get_rotate_clockwise())) { + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == side_manager.get_rotate_counterclockwise()) { + to_tracks = get_to_track_list(Fs, num_to_tracks - 1 - actual_from_track, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == UNIVERSAL case. */ + case WILTON: + /* See S. Wilton Phd thesis, U of T, 1996 p. 103 for details on following. */ + if (from_side == LEFT) { + if (to_side == RIGHT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } + } else if (from_side == RIGHT) { + if (to_side == LEFT) { /* CHANX to CHANX */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == TOP) { /* from CHANX to CHANY */ + to_tracks = get_to_track_list(Fs, (num_to_tracks + actual_from_track - 1) % num_to_tracks, num_to_tracks); + } else if (to_side == BOTTOM) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == BOTTOM) { + if (to_side == TOP) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, actual_from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (2 * num_to_tracks - 2 - actual_from_track) % num_to_tracks, num_to_tracks); + } + } else if (from_side == TOP) { + if (to_side == BOTTOM) { /* CHANY to CHANY */ + to_tracks = get_to_track_list(Fs, from_track, num_to_tracks); + } else if (to_side == LEFT) { /* from CHANY to CHANX */ + to_tracks = get_to_track_list(Fs, (num_to_tracks - actual_from_track) % num_to_tracks, num_to_tracks); + } else if (to_side == RIGHT) { + to_tracks = get_to_track_list(Fs, (actual_from_track + 1) % num_to_tracks, num_to_tracks); + } + } + /* Finish, we return */ + return to_tracks; + /* End switch_block_type == WILTON case. */ + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid switch block pattern !\n"); + exit(1); + } + + return to_tracks; +} + +/************************************************************************ + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * For a group of from_track nodes and to_track nodes + * For each side of from_tracks, we call a routine to get the list of to_tracks + * Then, we fill the track2track_map + ***********************************************************************/ +static void build_gsb_one_group_track_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const bool& wire_opposite_side, + const t_track_group& from_tracks, /* [0..gsb_side][track_indices] */ + const t_track_group& to_tracks, /* [0..gsb_side][track_indices] */ + t_track2track_map& track2track_map) { + for (size_t side = 0; side < from_tracks.size(); ++side) { + SideManager side_manager(side); + e_side from_side = side_manager.get_side(); + /* Find the other sides where the start tracks will locate */ + std::vector to_track_sides; + /* 0. opposite side */ + to_track_sides.push_back(side_manager.get_opposite()); + /* 1. prev side */ + /* Previous side definition: TOP => LEFT; RIGHT=>TOP; BOTTOM=>RIGHT; LEFT=>BOTTOM */ + to_track_sides.push_back(side_manager.get_rotate_counterclockwise()); + /* 2. next side */ + /* Next side definition: TOP => RIGHT; RIGHT=>BOTTOM; BOTTOM=>LEFT; LEFT=>TOP */ + to_track_sides.push_back(side_manager.get_rotate_clockwise()); + + for (size_t inode = 0; inode < from_tracks[side].size(); ++inode) { + for (size_t to_side_id = 0; to_side_id < to_track_sides.size(); ++to_side_id) { + enum e_side to_side = to_track_sides[to_side_id]; + SideManager to_side_manager(to_side); + size_t to_side_index = to_side_manager.to_size_t(); + /* Bypass those to_sides have no nodes */ + if (0 == to_tracks[to_side_index].size()) { + continue; + } + /* Bypass those from_side is same as to_side */ + if (from_side == to_side) { + continue; + } + /* Bypass those from_side is opposite to to_side if required */ + if (!wire_opposite_side + && (to_side_manager.get_opposite() == from_side)) { + continue; + } + /* Get other track_ids depending on the switch block pattern */ + /* Find the track ids that will start at the other sides */ + std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, + to_side, + to_tracks[to_side_index].size()); + /* Update the track2track_map: */ + for (size_t to_track_id = 0; to_track_id < to_track_ids.size(); ++to_track_id) { + size_t from_side_index = side_manager.to_size_t(); + size_t from_track_index = from_tracks[side][inode]; + /* Check the id is still in the range !*/ + VTR_ASSERT(to_track_ids[to_track_id] < to_tracks[to_side_index].size()); + size_t to_track_index = to_tracks[to_side_index][to_track_ids[to_track_id]]; + //printf("from_track(size=%lu): %lu , to_track_ids[%lu]:%lu, to_track_index: %lu in a group of %lu tracks\n", + // from_tracks[side].size(), inode, to_track_id, to_track_ids[to_track_id], + // to_track_index, to_tracks[to_side_index].size()); + const RRNodeId& to_track_node = rr_gsb.get_chan_node(to_side, to_track_index); + VTR_ASSERT(true == rr_graph.valid_node(to_track_node)); + + /* from_track should be IN_PORT */ + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(from_side, from_track_index)); + /* to_track should be OUT_PORT */ + VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(to_side, to_track_index)); + + //VTR_LOG("Consider a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); + + /* Check if the to_track_node is already in the list ! */ + std::vector::iterator it = std::find(track2track_map[from_side_index][from_track_index].begin(), + track2track_map[from_side_index][from_track_index].end(), + to_track_node); + if (it != track2track_map[from_side_index][from_track_index].end()) { + continue; /* the node_id is already in the list, go for the next */ + } + /* Clear, we should add to the list */ + track2track_map[from_side_index][from_track_index].push_back(to_track_node); + //VTR_LOG("Built a connection from pass tracks %d on side %s to track node %ld on side %s\n", from_track_index, SIDE_STRING[from_side], size_t(to_track_node), SIDE_STRING[to_side]); + } + } + } + } +} + +/************************************************************************ + * Build the track_to_track_map[from_side][0..chan_width-1][to_side][track_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * The track_indices is the indices of tracks that the node at from_side and [0..chan_width-1] will drive + * IMPORTANT: the track_indices are the indicies in the GSB context, but not the rr_graph!!! + * We separate the connections into two groups: + * Group 1: the routing tracks start from this GSB + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * Group 2: the routing tracks do not start from this GSB (bypassing wires) + * We will apply switch block patterns (SUBSET, UNIVERSAL, WILTON) + * but we will check the Switch Block (SB) population of these + * routing segments, and determine which requires connections + * + * CHANY CHANY CHANY CHANY + * [0] [1] [2] [3] + * start yes no yes no + * end +-------------------------+ start Group 1 Group 2 + * no CHANX[0] | TOP | CHANX[0] yes TOP/BOTTOM TOP/BOTTOM + * | | CHANY[0,2] CHANY[1,3] + * yes CHANX[1] | | CHANX[1] no + * | LEFT RIGHT | + * no CHANX[2] | | CHANX[2] yes + * | | + * yes CHANX[3] | BOTTOM | CHANX[3] no + * +-------------------------+ + * CHANY CHANY CHANY CHANY + * [0] [1] [2] [3] + * start yes no yes no + * + * The mapping is done in the following steps: (For each side of the GSB) + * 1. Build a list of tracks that will start from this side + * if a track starts, its xlow/ylow is the same as the x,y of this gsb + * 2. Build a list of tracks on the other sides belonging to Group 1. + * Take the example of RIGHT side, we will collect + * a. tracks that will end at the LEFT side + * b. tracks that will start at the TOP side + * c. tracks that will start at the BOTTOM side + * 3. Apply switch block patterns to Group 1 (SUBSET, UNIVERSAL, WILTON) + * 4. Build a list of tracks on the other sides belonging to Group 1. + * Take the example of RIGHT side, we will collect + * a. tracks that will bypass at the TOP side + * b. tracks that will bypass at the BOTTOM side + * 5. Apply switch block patterns to Group 2 (SUBSET, UNIVERSAL, WILTON) + ***********************************************************************/ +t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& concat_wire, + const bool& wire_opposite_side, + const std::vector& segment_inf) { + t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ + + /* Categorize tracks into 3 groups: + * (1) tracks will start here + * (2) tracks will end here + * (2) tracks will just pass through the SB */ + t_track_group start_tracks; /* [0..gsb_side][track_indices] */ + t_track_group end_tracks; /* [0..gsb_side][track_indices] */ + t_track_group pass_tracks; /* [0..gsb_side][track_indices] */ + + /* resize to the number of sides */ + start_tracks.resize(rr_gsb.get_num_sides()); + end_tracks.resize(rr_gsb.get_num_sides()); + pass_tracks.resize(rr_gsb.get_num_sides()); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + e_side gsb_side = side_manager.get_side(); + /* Build a list of tracks that will start from this side */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* We need to check Switch block population of this track + * The track node will not be considered if there supposed to be no SB at this position + */ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, gsb_side, inode, segment_inf)) { + continue; /* skip this node and go to the next */ + } + /* check if this track will start from here */ + enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, gsb_side, inode); + + switch (track_status) { + case TRACK_START: + /* update starting track list */ + start_tracks[side].push_back(inode); + break; + case TRACK_END: + /* Update end track list */ + end_tracks[side].push_back(inode); + break; + case TRACK_PASS: + /* Update passing track list */ + /* Note that the pass_track should be IN_PORT only !!! */ + if (IN_PORT == rr_gsb.get_chan_node_direction(gsb_side, inode)) { + pass_tracks[side].push_back(inode); + } + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid track status!\n"); + exit(1); + } + } + } + + /* Allocate track2track map */ + track2track_map.resize(rr_gsb.get_num_sides()); + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + /* allocate track2track_map[gsb_side] */ + track2track_map[side].resize(rr_gsb.get_chan_width(gsb_side)); + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + /* allocate track2track_map[gsb_side][inode] */ + track2track_map[side][inode].clear(); + } + } + + /* For Group 1: we build connections between end_tracks and start_tracks*/ + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, + concat_wire, /* End tracks should always to wired to start tracks */ + end_tracks, start_tracks, + track2track_map); + + /* For Group 2: we build connections between end_tracks and start_tracks*/ + /* Currently, I use the same Switch Block pattern for the passing tracks and end tracks, + * TODO: This can be improved with different patterns! + */ + //for (e_side curr_side : SIDES) { + // VTR_LOG("Number of pass tracks %d on side %s\n", pass_tracks[size_t(curr_side)].size(), SIDE_STRING[curr_side]); + //} + build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, + sb_subtype, subFs, + wire_opposite_side, /* Pass tracks may not be wired to start tracks */ + pass_tracks, start_tracks, + track2track_map); + + return track2track_map; +} + +t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const RRSwitchId& delayless_switch, + vtr::vector& rr_node_driver_switches) { + + std::vector>>> chan_rr_nodes_all_sides; //[side][bend_num][start/end][node] + chan_rr_nodes_all_sides.resize(4); + + int bend_seg_num = 0; + std::vector bend_seg_type; //bend type: 1: U; 2: D + for (size_t iseg = 0; iseg < segment_inf.size(); iseg++) { + if (segment_inf[iseg].isbend) { + bend_seg_num++; + + for (size_t i = 0; i < segment_inf[iseg].bend.size(); i++) { + if (segment_inf[iseg].bend[i] != 0) { + bend_seg_type.push_back(segment_inf[iseg].bend[i]); + break; + } + } + } + } + VTR_ASSERT(bend_seg_num == int(bend_seg_type.size())); + for (size_t side = 0; side < 4; ++side) { + std::vector rr_nodes; + switch (side) { + case TOP: /* TOP = 0 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == grids.height() - 2) { + + break; + } + + chan_rr_nodes_all_sides[0].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[0][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, + CHANY); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t ylow = rr_graph.node_ylow(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_start != 0 && xlow == gsb_coordinate.x() && (ylow == gsb_coordinate.y() + 1)) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[0][bend_start - 1][0].push_back(inode); + } + if (direction == Direction::DEC && bend_end != 0 && xlow == gsb_coordinate.x() && (ylow == gsb_coordinate.y() + 1)) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[0][bend_end - 1][1].push_back(inode); + } + + } + + break; + case RIGHT: /* RIGHT = 1 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == grids.width() - 2) { + + break; + } + + chan_rr_nodes_all_sides[1].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[1][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), + CHANX); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + Direction direction = rr_graph.node_direction(inode); + size_t xlow = rr_graph.node_xlow(inode); + size_t ylow = rr_graph.node_ylow(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_start != 0 && (xlow == gsb_coordinate.x() + 1) && ylow == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[1][bend_start - 1][0].push_back(inode); + } + if (direction == Direction::DEC && bend_end != 0 && (xlow == gsb_coordinate.x() + 1) && ylow == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[1][bend_end - 1][1].push_back(inode); + } + + } + break; + case BOTTOM: /* BOTTOM = 2 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.y() == 0) { + + break; + } + + chan_rr_nodes_all_sides[2].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[2][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + CHANY); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANY); + Direction direction = rr_graph.node_direction(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_end != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[2][bend_end - 1][1].push_back(inode); + } + if (direction == Direction::DEC && bend_start != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[2][bend_start - 1][0].push_back(inode); + } + + } + break; + case LEFT: /* BOTTOM = 2 */ + /* For the bording, we should take special care */ + if (gsb_coordinate.x() == 0) { + + break; + } + + chan_rr_nodes_all_sides[3].resize(bend_seg_num); + for (int i = 0; i < bend_seg_num; i++){ + chan_rr_nodes_all_sides[3][i].resize(2); //start/end track for bend + } + + rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + CHANX); + + for (auto inode : rr_nodes) { + VTR_ASSERT(rr_graph.node_type(inode) == CHANX); + Direction direction = rr_graph.node_direction(inode); + size_t xhigh = rr_graph.node_xhigh(inode); + size_t yhigh = rr_graph.node_yhigh(inode); + int bend_start = rr_graph.node_bend_start(inode); + int bend_end = rr_graph.node_bend_end(inode); + + VTR_ASSERT((bend_start <= bend_seg_num) && (bend_end <= bend_seg_num)); + if (direction == Direction::INC && bend_end != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_start == 0); + chan_rr_nodes_all_sides[3][bend_end - 1][1].push_back(inode); + } + if (direction == Direction::DEC && bend_start != 0 && xhigh == gsb_coordinate.x() && yhigh == gsb_coordinate.y()) { + VTR_ASSERT(bend_end == 0); + chan_rr_nodes_all_sides[3][bend_start - 1][0].push_back(inode); + } + + } + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + + } + } + std::map bend_seg_head2bend_seg_end_map; + for (size_t ibend_seg = 0; ibend_seg < (size_t)bend_seg_num; ibend_seg++) { + int bend_type = bend_seg_type[ibend_seg]; //bend_type 1:U 2:D + VTR_ASSERT(bend_type == 1 || bend_type == 2); + + if (bend_type == 1) { //bend type U + for (size_t side = 0; side < 4; side++){ + size_t to_side = (side + 1) % 4; + if (chan_rr_nodes_all_sides[side].size() > 0) + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { + + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); + bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); + rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; + } + else { + rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); + } + } + else { + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + } + } + } + } + + } + else if (bend_type == 2) { //bend type D + for (size_t side = 0; side < 4; side++){ + size_t to_side = (side + 3) % 4; + if (chan_rr_nodes_all_sides[side].size() > 0) + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[side][ibend_seg][1].size(); inode++) { + + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + VTR_ASSERT(chan_rr_nodes_all_sides[side][ibend_seg][1].size() == chan_rr_nodes_all_sides[to_side][ibend_seg][0].size()); + bend_seg_head2bend_seg_end_map.emplace(std::make_pair(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode])); + rr_node_driver_switches[chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode]] = delayless_switch; + } + else { + rr_graph_builder.set_node_bend_end(chan_rr_nodes_all_sides[side][ibend_seg][1][inode], 0); + } + } + else { + if (chan_rr_nodes_all_sides[to_side].size() > 0) { + for (size_t inode = 0; inode < chan_rr_nodes_all_sides[to_side][ibend_seg][0].size(); inode++) { + rr_graph_builder.set_node_bend_start(chan_rr_nodes_all_sides[to_side][ibend_seg][0][inode], 0); + } + } + } + } + } + + } + + return bend_seg_head2bend_seg_end_map; +} + +/* Build a RRChan Object with the given channel type and coorindators */ +static RRChan build_one_tileable_rr_chan(const size_t& layer, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + const RRGraphView& rr_graph, + const ChanNodeDetails& chan_details) { + std::vector chan_rr_nodes; + + /* Create a rr_chan object and check if it is unique in the graph */ + RRChan rr_chan; + + /* Fill the information */ + rr_chan.set_type(chan_type); + + /* Collect rr_nodes for this channel */ + chan_rr_nodes = find_rr_graph_chan_nodes(rr_graph, + layer, chan_coordinate.x(), chan_coordinate.y(), + chan_type); + + /* Reserve */ + /* rr_chan.reserve_node(size_t(chan_width)); */ + + /* Fill the rr_chan */ + for (size_t itrack = 0; itrack < chan_rr_nodes.size(); ++itrack) { + size_t iseg = chan_details.get_track_segment_id(itrack); + rr_chan.add_node(rr_graph, chan_rr_nodes[itrack], RRSegmentId(iseg)); + } + + return rr_chan; +} + +/*********************************************************************** + * Build a General Switch Block (GSB) + * which includes: + * [I] A Switch Box subckt consists of following ports: + * 1. Channel Y [x][y] inputs + * 2. Channel X [x+1][y] inputs + * 3. Channel Y [x][y-1] outputs + * 4. Channel X [x][y] outputs + * 5. Grid[x][y+1] Right side outputs pins + * 6. Grid[x+1][y+1] Left side output pins + * 7. Grid[x+1][y+1] Bottom side output pins + * 8. Grid[x+1][y] Top side output pins + * 9. Grid[x+1][y] Left side output pins + * 10. Grid[x][y] Right side output pins + * 11. Grid[x][y] Top side output pins + * 12. Grid[x][y+1] Bottom side output pins + * + * -------------- -------------- + * | | CBY | | + * | Grid | ChanY | Grid | + * | [x][y+1] | [x][y+1] | [x+1][y+1] | + * | | | | + * -------------- -------------- + * ---------- + * ChanX & CBX | Switch | ChanX + * [x][y] | Box | [x+1][y] + * | [x][y] | + * ---------- + * -------------- -------------- + * | | | | + * | Grid | ChanY | Grid | + * | [x][y] | [x][y] | [x+1][y] | + * | | | | + * -------------- -------------- + * For channels chanY with INC_DIRECTION on the top side, they should be marked as outputs + * For channels chanY with DEC_DIRECTION on the top side, they should be marked as inputs + * For channels chanY with INC_DIRECTION on the bottom side, they should be marked as inputs + * For channels chanY with DEC_DIRECTION on the bottom side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the left side, they should be marked as inputs + * For channels chanX with DEC_DIRECTION on the left side, they should be marked as outputs + * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs + * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs + * + * [II] A X-direction Connection Block [x][y] + * The connection block shares the same routing channel[x][y] with the Switch Block + * We just need to fill the ipin nodes at TOP and BOTTOM sides + * as well as properly fill the ipin_grid_side information + * [III] A Y-direction Connection Block [x][y+1] + * The connection block shares the same routing channel[x][y+1] with the Switch Block + * We just need to fill the ipin nodes at LEFT and RIGHT sides + * as well as properly fill the ipin_grid_side information + ***********************************************************************/ +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, + const RRGraphView& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const bool& perimeter_cb) { + /* Create an object to return */ + RRGSB rr_gsb; + + /* Check */ + VTR_ASSERT(gsb_coordinate.x() <= grids.width()); + VTR_ASSERT(gsb_coordinate.y() <= grids.height()); + + /* Coordinator initialization */ + rr_gsb.set_coordinate(gsb_coordinate.x(), gsb_coordinate.y()); + + /* Basic information*/ + rr_gsb.init_num_sides(4); /* Fixed number of sides */ + + /* Find all rr_nodes of channels */ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + /* Local variables inside this for loop */ + SideManager side_manager(side); + vtr::Point coordinate = rr_gsb.get_side_block_coordinate(side_manager.get_side()); + RRChan rr_chan; + std::vector> temp_opin_rr_nodes(2); + enum e_side opin_grid_side[2] = {NUM_2D_SIDES, NUM_2D_SIDES}; + enum PORTS chan_dir_to_port_dir_mapping[2] = {OUT_PORT, IN_PORT}; /* 0: INC_DIRECTION => ?; 1: DEC_DIRECTION => ? */ + + /* Build a segment details, where we need the segment ids for building rr_chan + * We do not care starting and ending points here, so set chan_side as NUM_SIDES + */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(device_chan_width.x(), grids.width() - 1, + false, false, segment_inf_x); + ChanNodeDetails chany_details = build_unidir_chan_node_details(device_chan_width.y(), grids.height() - 1, + false, false, segment_inf_y); + + switch (side) { + case TOP: /* TOP = 0 */ + /* For the border, we should take special care. */ + if (gsb_coordinate.y() == grids.height() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x][y+1] RIGHT side outputs pins */ + opin_grid_side[0] = RIGHT; + /* Grid[x+1][y+1] left side outputs pins */ + opin_grid_side[1] = LEFT; + + /* Build the Switch block: opin and opin_grid_side */ + /* Include Grid[x][y+1] RIGHT side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* Include Grid[x+1][y+1] Left side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[1]); + + break; + case RIGHT: /* RIGHT = 1 */ + /* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */ + if (gsb_coordinate.x() == grids.width() - 1) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for top: chany[x][y+1] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = OUT_PORT; /* INC_DIRECTION => OUT_PORT */ + chan_dir_to_port_dir_mapping[1] = IN_PORT; /* DEC_DIRECTION => IN_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x+1][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y+1] Bottom side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x+1][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case BOTTOM: /* BOTTOM = 2*/ + if (!perimeter_cb && gsb_coordinate.y() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for bottom: chany[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANY, rr_graph, chany_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Assign grid side of OPIN */ + /* Grid[x+1][y] LEFT side outputs pins */ + opin_grid_side[0] = LEFT; + /* Grid[x][y] RIGHT side outputs pins */ + opin_grid_side[1] = RIGHT; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x+1][y] Left side output pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Right side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + break; + case LEFT: /* LEFT = 3 */ + if (!perimeter_cb && gsb_coordinate.x() == 0) { + rr_gsb.clear_one_side(side_manager.get_side()); + break; + } + /* Routing channels*/ + /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */ + /* Collect rr_nodes for Tracks for left: chanx[x][y] */ + /* Create a rr_chan object and check if it is unique in the graph */ + rr_chan = build_one_tileable_rr_chan(layer, coordinate, CHANX, rr_graph, chanx_details); + chan_dir_to_port_dir_mapping[0] = IN_PORT; /* INC_DIRECTION => IN_PORT */ + chan_dir_to_port_dir_mapping[1] = OUT_PORT; /* DEC_DIRECTION => OUT_PORT */ + + /* Grid[x][y+1] BOTTOM side outputs pins */ + opin_grid_side[0] = BOTTOM; + /* Grid[x][y] TOP side outputs pins */ + opin_grid_side[1] = TOP; + + /* Build the Switch block: opin and opin_grid_side */ + /* include Grid[x][y+1] Bottom side outputs pins */ + temp_opin_rr_nodes[0] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, + OPIN, opin_grid_side[0]); + /* include Grid[x][y] Top side output pins */ + temp_opin_rr_nodes[1] = find_rr_graph_grid_nodes(rr_graph, grids, + layer, gsb_coordinate.x(), gsb_coordinate.y(), + OPIN, opin_grid_side[1]); + + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } + + /* Organize a vector of port direction */ + if (0 < rr_chan.get_chan_width()) { + std::vector rr_chan_dir; + rr_chan_dir.resize(rr_chan.get_chan_width()); + for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + /* Identify the directionality, record it in rr_node_direction */ + if (Direction::INC == rr_graph.node_direction(rr_chan.get_node(itrack))) { + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[0]; + } else { + VTR_ASSERT(Direction::DEC == rr_graph.node_direction(rr_chan.get_node(itrack))); + rr_chan_dir[itrack] = chan_dir_to_port_dir_mapping[1]; + } + } + /* Fill chan_rr_nodes */ + rr_gsb.add_chan_node(side_manager.get_side(), rr_chan, rr_chan_dir); + } + + /* Fill opin_rr_nodes */ + /* Copy from temp_opin_rr_node to opin_rr_node */ + for (const RRNodeId& inode : temp_opin_rr_nodes[0]) { + /* Grid[x+1][y+1] Bottom side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } + for (const RRNodeId& inode : temp_opin_rr_nodes[1]) { + /* Grid[x+1][y] TOP side outputs pins */ + rr_gsb.add_opin_node(inode, side_manager.get_side()); + } + + /* Clean ipin_rr_nodes */ + /* We do not have any IPIN for a Switch Block */ + rr_gsb.clear_ipin_nodes(side_manager.get_side()); + + /* Clear the temp data */ + temp_opin_rr_nodes[0].clear(); + temp_opin_rr_nodes[1].clear(); + opin_grid_side[0] = NUM_2D_SIDES; + opin_grid_side[1] = NUM_2D_SIDES; + } + + /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * | Grid[x][y+1] | + * | BOTTOM side | + * +-----------------------+ + * | + * v + * +-----------------------+ + * | TOP side | + * | X- Connection Block | + * | BOTTOM side | + * +-----------------------+ + * ^ + * | + * +-----------------------+ + * | TOP side | + * | Grid[x][y] | + * + * - The concept of top/bottom side of connection block in GSB domain: + * + * ---------------+ +---------------------- ... ---------------------+ +---------------- + * Grid[x][y] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y] + * RIGHT side | | LEFT side ... RIGHT side | | LEFT side + * --------------+ +---------------------- ... ---------------------+ +---------------- + * + */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + size_t ix; + size_t iy; + enum e_side chan_side; + std::vector temp_ipin_rr_nodes; + enum e_side ipin_rr_node_grid_side; + + switch (side) { + case TOP: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the bottom side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y() + 1; + ipin_rr_node_grid_side = BOTTOM; + break; + case RIGHT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = BOTTOM; + /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */ + ix = rr_gsb.get_sb_x() + 1; + iy = rr_gsb.get_sb_y(); + ipin_rr_node_grid_side = LEFT; + break; + case BOTTOM: + /* Consider the routing channel that is connected to the left side of the switch block */ + chan_side = LEFT; + /* The input pins of the routing channel come from the top side of Grid[x][y] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y(); + ipin_rr_node_grid_side = TOP; + break; + case LEFT: + /* Consider the routing channel that is connected to the top side of the switch block */ + chan_side = BOTTOM; + /* The input pins of the routing channel come from the right side of Grid[x][y+1] */ + ix = rr_gsb.get_sb_x(); + iy = rr_gsb.get_sb_y(); + ipin_rr_node_grid_side = RIGHT; + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid side index!\n"); + exit(1); + } + + /* If there is no channel at this side, we skip ipin_node annotation */ + if (0 == rr_gsb.get_chan_width(chan_side)) { + continue; + } + /* Collect IPIN rr_nodes*/ + temp_ipin_rr_nodes = find_rr_graph_grid_nodes(rr_graph, grids, + layer, ix, iy, IPIN, ipin_rr_node_grid_side); + /* Fill the ipin nodes of RRGSB */ + for (const RRNodeId& inode : temp_ipin_rr_nodes) { + rr_gsb.add_ipin_node(inode, side_manager.get_side()); + } + /* Clear the temp data */ + temp_ipin_rr_nodes.clear(); + } + + /* Find all MEDIUM rr_nodes */ + std::vector medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y(), MEDIUM); + for (auto medium_rr_node : medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + /* For TOP and RIGHT borders, we need to add extra medium nodes. */ + if (gsb_coordinate.y() == grids.height() - 2) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x(), gsb_coordinate.y() + 1, MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + + if (gsb_coordinate.x() == grids.width() - 2) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y(), MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + + if ((gsb_coordinate.x() == grids.width() - 2) && (gsb_coordinate.y() == grids.height() - 2)) { + std::vector extra_medium_rr_nodes = rr_graph.node_lookup().find_grid_nodes_at_all_sides(layer, gsb_coordinate.x() + 1, gsb_coordinate.y() + 1, MEDIUM); + for (auto medium_rr_node : extra_medium_rr_nodes) { + rr_gsb.add_medium_node(medium_rr_node); + } + } + + return rr_gsb; +} + +/************************************************************************ + * Create edges for each rr_node of a General Switch Blocks (GSB): + * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks) + * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks) + * 3. create edges between OPINs and IPINs (direct-connections) + ***********************************************************************/ +void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { + size_t edge_count = 0; + /* Walk through each sides */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + + /* Find OPINs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); + + for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode].size(); ++to_side) { + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side]) { + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } + + /* Find CHANX or CHANY */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides + * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs + */ + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node], false); + edge_count++; + } + } + } + + /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } + // /* Create edges between bend nodes */ + // for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + // rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + // edge_count++; + // } + num_edges_to_create += edge_count; +} + +void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { + size_t edge_count = 0; + /* Walk through each sides */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side gsb_side = side_manager.get_side(); + + /* Find OPINs */ + for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(gsb_side); ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(gsb_side, inode); + + for (size_t to_side = 0; to_side < opin2track_map[gsb_side][inode].size(); ++to_side) { + /* 1. create edges between OPINs and CHANX|CHANY, using opin2track_map */ + /* add edges to the opin_node */ + for (const RRNodeId& track_node : opin2track_map[gsb_side][inode][to_side]) { + rr_graph_builder.create_edge(opin_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } + + /* Find CHANX or CHANY */ + /* For TRACKs to IPINs, we only care LEFT and TOP sides + * Skip RIGHT and BOTTOM for the ipin2track_map since they should be handled in other GSBs + */ + if ((side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANX)) + || (side_manager.get_side() == rr_gsb.get_cb_chan_side(CHANY))) { + /* 2. create edges between CHANX|CHANY and IPINs, using ipin2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node], false); + edge_count++; + } + } + } + + /* 3. create edges between CHANX|CHANY and CHANX|CHANY, using track2track_map */ + for (size_t inode = 0; inode < rr_gsb.get_chan_width(gsb_side); ++inode) { + const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode); + for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) { + rr_graph_builder.create_edge(chan_node, track_node, rr_node_driver_switches[track_node], false); + edge_count++; + } + } + } + /* Create edges between bend nodes */ + for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + edge_count++; + } + num_edges_to_create += edge_count; +} + +/************************************************************************ + * Build track2ipin_map for an IPIN + * 1. build a list of routing tracks which are allowed for connections + * We will check the Connection Block (CB) population of each routing track. + * By comparing current chan_y - ylow, we can determine if a CB connection + * is required for each routing track + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between IPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +static void build_gsb_one_ipin_track2pin_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& ipin_side, + const size_t& ipin_node_id, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_track2pin_map& track2ipin_map) { + /* Get a list of segment_ids*/ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + std::vector seg_list = rr_gsb.get_chan_segment_ids(chan_side); + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager ipin_side_manager(ipin_side); + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, ipin_node_id); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_cb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + /* Check the actual track list */ + VTR_ASSERT(0 == actual_track_list.size() % 2); + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Make sure step should be at least 2 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + /* rotate the track list by an offset */ + if (0 < actual_offset) { + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } + + /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ + //int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { + /* Update pin2track map */ + size_t chan_side_index = chan_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + /* track_index may exceed the chan_width(), adapt it */ + size_t track_index = actual_track_list[actual_itrack] % chan_width; + + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + + /* track_index may exceed the chan_width(), adapt it */ + track_index = (actual_track_list[actual_itrack] + 1) % chan_width; + + track2ipin_map[chan_side_index][track_index].push_back(ipin_node); + + //track_cnt += 2; + } + + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* + * if (actual_Fc != track_cnt) { + * vpr_printf(TIO_MESSAGE_INFO, + * "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + * ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + * } + */ + } +} + +/************************************************************************ + * Build opin2track_map for an OPIN + * 1. build a list of routing tracks which are allowed for connections + * We will check the Switch Block (SB) population of each routing track. + * By comparing current chan_y - ylow, we can determine if a SB connection + * is required for each routing track + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between OPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +static void build_gsb_one_opin_pin2track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const enum e_side& opin_side, + const size_t& opin_node_id, + const enum e_side& chan_side, + const std::vector& Fc, + const size_t& offset, + const std::vector& segment_inf, + t_pin2track_map& opin2track_map) { + /* Get a list of segment_ids*/ + std::vector seg_list = rr_gsb.get_chan_segment_ids(opin_side); + size_t chan_width = rr_gsb.get_chan_width(chan_side); + SideManager opin_side_manager(opin_side); + SideManager chan_side_manager(chan_side); + + for (size_t iseg = 0; iseg < seg_list.size(); ++iseg) { + /* Get a list of node that have the segment id */ + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(chan_side, seg_list[iseg]); + /* Refine the track_list: keep those will have connection blocks in the GSB */ + std::vector actual_track_list; + for (size_t inode = 0; inode < track_list.size(); ++inode) { + /* Check if tracks allow connection blocks in the GSB*/ + if (false == is_gsb_in_track_sb_population(rr_graph, rr_gsb, chan_side, track_list[inode], segment_inf)) { + continue; /* Bypass condition */ + } + if (TRACK_START != determine_track_status_of_gsb(rr_graph, rr_gsb, chan_side, track_list[inode])) { + continue; /* Bypass condition */ + } + /* Push the node to actual_track_list */ + actual_track_list.push_back(track_list[inode]); + } + + /* Go the next segment if offset is zero or actual_track_list is empty */ + if (0 == actual_track_list.size()) { + continue; + } + + /* Scale Fc */ + int actual_Fc = std::ceil((float)Fc[iseg] * (float)actual_track_list.size() / (float)chan_width); + /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ + actual_Fc = std::max(1, actual_Fc); + /* Compute the step between two connection from this IPIN to tracks: + * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); + /* Track step mush be a multiple of 2!!!*/ + /* Make sure step should be at least 1 */ + track_step = std::max(1, (int)track_step); + /* Adapt offset to the range of actual_track_list */ + size_t actual_offset = offset % actual_track_list.size(); + + /* No need to rotate if offset is zero */ + if (0 < actual_offset) { + /* rotate the track list by an offset */ + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } + + /* Assign tracks */ + int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ + for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { + /* Update pin2track map */ + size_t opin_side_index = opin_side_manager.to_size_t(); + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; + const RRNodeId& track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index); + opin2track_map[opin_side_index][opin_node_id][chan_side_manager.to_size_t()].push_back(track_rr_node_index); + /* update track counter */ + track_cnt++; + /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. + * So I comment it. And we just make sure its track_cnt >= actual_Fc + * if (actual_Fc == track_cnt) { + * break; + * } + */ + } + + /* Ensure the number of tracks is similar to Fc */ + /* Give a warning if Fc is < track_cnt */ + /* + * if (actual_Fc != track_cnt) { + * vpr_printf(TIO_MESSAGE_INFO, + * "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + * opin_node_id, track_cnt, actual_Fc); + * } + */ + } +} + +/************************************************************************ + * Build the track_to_ipin_map[gsb_side][0..chan_width-1][ipin_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build ipin_to_track_map[gsb_side][0..num_ipin_nodes-1][track_indices] + * For each IPIN, we ensure at least one connection to the tracks. + * Then, we assign IPINs to tracks evenly while satisfying the actual_Fc + * 2. Convert the ipin_to_track_map to track_to_ipin_map + ***********************************************************************/ +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_in) { + t_track2pin_map track2ipin_map; + /* Resize the matrix */ + track2ipin_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the track-to-IPIN for each connection block */ + size_t offset_size = 0; + std::vector offset; + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* resize offset to the maximum chan_side*/ + offset_size = std::max(offset_size, chan_side_manager.to_size_t() + 1); + } + /* Initial offset */ + offset.resize(offset_size); + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side ipin_side = side_manager.get_side(); + /* Get the chan_side */ + enum e_side chan_side = rr_gsb.get_cb_chan_side(ipin_side); + SideManager chan_side_manager(chan_side); + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t chan_width = rr_gsb.get_chan_width(chan_side); + track2ipin_map[chan_side_manager.to_size_t()].resize(chan_width); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(ipin_side); ++inode) { + const RRNodeId& ipin_node = rr_gsb.get_ipin_node(ipin_side, inode); + t_physical_tile_loc ipin_node_phy_tile_loc(rr_graph.node_xlow(ipin_node), rr_graph.node_ylow(ipin_node), 0); + /* Skip EMPTY type */ + if (true == is_empty_type(grids.get_physical_type(ipin_node_phy_tile_loc))) { + continue; + } + + int grid_type_index = grids.get_physical_type(ipin_node_phy_tile_loc)->index; + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector ipin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int ipin_Fc = Fc_in[grid_type_index][rr_graph.node_pin_num(ipin_node)][iseg]; + ipin_Fc_out.push_back(ipin_Fc); + if (0 != ipin_Fc) { + skip_conn2track = false; + continue; + } + } + + if (true == skip_conn2track) { + continue; + } + + //VTR_ASSERT(ipin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + build_gsb_one_ipin_track2pin_map(rr_graph, rr_gsb, ipin_side, inode, ipin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[chan_side_manager.to_size_t()], + segment_inf, track2ipin_map); + /* update offset */ + offset[chan_side_manager.to_size_t()] += 2; + //printf("offset[%lu]=%lu\n", chan_side_manager.to_size_t(), offset[chan_side_manager.to_size_t()]); + } + } + + return track2ipin_map; +} + +/************************************************************************ + * Build the opin_to_track_map[gsb_side][0..num_opin_nodes-1][track_indices] + * based on the existing routing resources in the General Switch Block (GSB) + * This function supports both X-directional and Y-directional tracks + * The mapping is done in the following steps: + * 1. Build a list of routing tracks whose starting points locate at this GSB + * (xlow - gsb_x == 0) + * 2. Divide the routing tracks by segment types, so that we can balance + * the connections between OPINs and different types of routing tracks. + * 3. Scale the Fc of each pin to the actual number of routing tracks + * actual_Fc = (int) Fc * num_tracks / chan_width + ***********************************************************************/ +t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_out, + const bool& opin2all_sides) { + t_pin2track_map opin2track_map; + /* Resize the matrix */ + opin2track_map.resize(rr_gsb.get_num_sides()); + + /* offset counter: it aims to balance the OPIN-to-track for each switch block */ + std::vector offset; + /* Get the chan_side: which is the same as the opin side */ + offset.resize(rr_gsb.get_num_sides()); + /* Initial offset */ + offset.assign(offset.size(), 0); + + /* Walk through each side */ + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + enum e_side opin_side = side_manager.get_side(); + /* Get the chan_side */ + /* This track2pin mapping is for Connection Blocks, so we only care two sides! */ + /* Get channel width and resize the matrix */ + size_t num_opin_nodes = rr_gsb.get_num_opin_nodes(opin_side); + opin2track_map[side].resize(num_opin_nodes); + /* Find the ipin/opin nodes */ + for (size_t inode = 0; inode < num_opin_nodes; ++inode) { + const RRNodeId& opin_node = rr_gsb.get_opin_node(opin_side, inode); + t_physical_tile_loc opin_node_phy_tile_loc(rr_graph.node_xlow(opin_node), rr_graph.node_ylow(opin_node), 0); + /* Skip EMPTY type */ + if (true == is_empty_type(grids.get_physical_type(opin_node_phy_tile_loc))) { + continue; + } + int grid_type_index = grids.get_physical_type(opin_node_phy_tile_loc)->index; + + /* Get Fc of the ipin */ + /* skip Fc = 0 or unintialized, those pins are in the */ + bool skip_conn2track = true; + std::vector opin_Fc_out; + for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) { + int opin_Fc = Fc_out[grid_type_index][rr_graph.node_pin_num(opin_node)][iseg]; + opin_Fc_out.push_back(opin_Fc); + if (0 != opin_Fc) { + skip_conn2track = false; + continue; + } + } + if (rr_gsb.get_sb_x() == grids.width() - 1 || rr_gsb.get_sb_y() == grids.height() - 1) { + skip_conn2track = true; + } + + if (true == skip_conn2track) { + continue; + } + VTR_ASSERT(opin_Fc_out.size() == segment_inf.size()); + + /* Build track2ipin_map for this IPIN */ + opin2track_map[side][inode].resize(rr_gsb.get_num_sides()); + if (opin2all_sides) { + for (size_t track_side = 0; track_side < rr_gsb.get_num_sides(); ++track_side) { + SideManager track_side_mgr(track_side); + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, track_side_mgr.get_side(), opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } + } else { + build_gsb_one_opin_pin2track_map(rr_graph, rr_gsb, opin_side, inode, opin_side, opin_Fc_out, + /* Give an offset for the first track that this ipin will connect to */ + offset[side_manager.to_size_t()], + segment_inf, opin2track_map); + } + /* update offset: aim to rotate starting tracks by 1*/ + offset[side_manager.to_size_t()] += 1; + } + + /* Check: + * 1. We want to ensure that each OPIN will drive at least one track + * 2. We want to ensure that each track will be driven by at least 1 OPIN */ + } + + return opin2track_map; +} + +/************************************************************************ + * Add all direct clb-pin-to-clb-pin edges to given opin + ***********************************************************************/ +void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& from_grid_coordinate, + const std::vector& directs, + const std::vector& clb_to_clb_directs) { + VTR_ASSERT(directs.size() == clb_to_clb_directs.size()); + + t_physical_tile_type_ptr grid_type = grids.get_physical_type(t_physical_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer)); + + /* Iterate through all direct connections */ + for (size_t i = 0; i < directs.size(); ++i) { + /* Bypass unmatched direct clb-to-clb connections */ + if (grid_type != clb_to_clb_directs[i].from_clb_type) { + continue; + } + + /* This opin is specified to connect directly to an ipin, + * now compute which ipin to connect to + */ + vtr::Point to_grid_coordinate(from_grid_coordinate.x() + directs[i].x_offset, + from_grid_coordinate.y() + directs[i].y_offset); + + /* Bypass unmatched direct clb-to-clb connections */ + t_physical_tile_type_ptr to_grid_type = grids.get_physical_type(t_physical_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer)); + /* Check if to_grid if the same grid */ + if (to_grid_type != clb_to_clb_directs[i].to_clb_type) { + continue; + } + + bool swap; + int max_index, min_index; + /* Compute index of opin with regards to given pins */ + if (clb_to_clb_directs[i].from_clb_pin_start_index + > clb_to_clb_directs[i].from_clb_pin_end_index) { + swap = true; + max_index = clb_to_clb_directs[i].from_clb_pin_start_index; + min_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } else { + swap = false; + min_index = clb_to_clb_directs[i].from_clb_pin_start_index; + max_index = clb_to_clb_directs[i].from_clb_pin_end_index; + } + + /* get every opin in the range */ + for (int opin = min_index; opin <= max_index; ++opin) { + int offset = opin - min_index; + + if ((to_grid_coordinate.x() < grids.width() - 1) + && (to_grid_coordinate.y() < grids.height() - 1)) { + int ipin = OPEN; + if (clb_to_clb_directs[i].to_clb_pin_start_index + > clb_to_clb_directs[i].to_clb_pin_end_index) { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index - offset; + } + } else { + if (true == swap) { + ipin = clb_to_clb_directs[i].to_clb_pin_end_index - offset; + } else { + ipin = clb_to_clb_directs[i].to_clb_pin_start_index + offset; + } + } + + /* Get the pin index in the rr_graph */ + t_physical_tile_loc from_tile_loc(from_grid_coordinate.x(), from_grid_coordinate.y(), layer); + int from_grid_width_ofs = grids.get_width_offset(from_tile_loc); + int from_grid_height_ofs = grids.get_height_offset(from_tile_loc); + t_physical_tile_loc to_tile_loc(to_grid_coordinate.x(), to_grid_coordinate.y(), layer); + int to_grid_width_ofs = grids.get_width_offset(to_tile_loc); + int to_grid_height_ofs = grids.get_height_offset(to_tile_loc); + + /* Find the side of grid pins, the pin location should be unique! + * Pin location is required by searching a node in rr_graph + */ + std::vector opin_grid_side = find_grid_pin_sides(grids, layer, from_grid_coordinate.x(), from_grid_coordinate.y(), opin); + VTR_ASSERT(1 == opin_grid_side.size()); + + std::vector ipin_grid_side = find_grid_pin_sides(grids, layer, to_grid_coordinate.x(), to_grid_coordinate.y(), ipin); + VTR_ASSERT(1 == ipin_grid_side.size()); + + RRNodeId opin_node_id = rr_graph.node_lookup().find_node(layer, + from_grid_coordinate.x() - from_grid_width_ofs, + from_grid_coordinate.y() - from_grid_height_ofs, + OPIN, opin, opin_grid_side[0]); + RRNodeId ipin_node_id = rr_graph.node_lookup().find_node(layer, + to_grid_coordinate.x() - to_grid_width_ofs, + to_grid_coordinate.y() - to_grid_height_ofs, + IPIN, ipin, ipin_grid_side[0]); + + /* add edges to the opin_node */ + VTR_ASSERT(opin_node_id && ipin_node_id); + rr_graph_builder.create_edge(opin_node_id, ipin_node_id, RRSwitchId(clb_to_clb_directs[i].switch_index), false); + } + } + } + /* Build actual edges */ + rr_graph_builder.build_edges(true); +} + +/* Vib edge builder */ +t_vib_map build_vib_map(const RRGraphView& rr_graph, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const RRGSB& rr_gsb, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const vtr::Point& actual_coordinate) { + VTR_ASSERT(rr_gsb.get_x() == gsb_coordinate.x() && rr_gsb.get_y() == gsb_coordinate.y()); + + t_vib_map vib_map; + + const VibInf* vib = vib_grid.get_vib(layer, actual_coordinate.x(), actual_coordinate.y()); + auto phy_type = grids.get_physical_type({(int)actual_coordinate.x(), (int)actual_coordinate.y(), (int)layer}); + VTR_ASSERT(vib->get_pbtype_name() == phy_type->name); + const std::vector first_stages = vib->get_first_stages(); + for (size_t i_first_stage = 0; i_first_stage < first_stages.size(); i_first_stage++) { + std::vector froms = first_stages[i_first_stage].froms; + RRNodeId to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, i_first_stage); + VTR_ASSERT(to_node.is_valid()); + VTR_ASSERT(rr_gsb.is_medium_node(to_node)); + for (auto from : froms) { + RRNodeId from_node; + if (from.from_type == PB) { + + if (from.type_name != vib->get_pbtype_name()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type name!\n"); + exit(1); + } + + for (e_side side : TOTAL_2D_SIDES) { + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + if (from_node.is_valid()) + break; + } + if (!from_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", from.type_name.c_str(), from.phy_pin_index); + continue; + } + if (!rr_gsb.is_opin_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Opin node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + else if (from.from_type == SEGMENT) { + char from_dir = from.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[from.type_index]; + VTR_ASSERT(segment.name == from.type_name); + t_seg_group seg_group; + for (auto seg : vib->get_seg_groups()) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); + e_side side; + if (from_dir == 'W') side = RIGHT; + else if (from_dir == 'E') side = LEFT; + else if (from_dir == 'N') side = BOTTOM; + else if (from_dir == 'S') side = TOP; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //INC + seg_id = from.seg_index * 2; + } + else { //DEC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = from.seg_index * 2 + 1; + } + from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + if (!rr_gsb.is_chan_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wire node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + + } + + + } + else if (from.from_type == MUX) { + size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + if (!rr_gsb.is_medium_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(from_node.is_valid()); + auto iter = vib_map.begin(); + for (; iter != vib_map.end(); ++iter) { + if (iter->first == from_node) { + vib_map[from_node].push_back(to_node); + } + } + if (iter == vib_map.end()) { + std::vector to_nodes; + to_nodes.push_back(to_node); + vib_map.emplace(std::make_pair(from_node, to_nodes)); + } + + + } + } + /* Second stages*/ + const std::vector second_stages = vib->get_second_stages(); + for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) { + std::vector froms = second_stages[i_second_stage].froms; + std::vector tos = second_stages[i_second_stage].to; + + std::vector to_nodes; + for (auto to : tos) { + RRNodeId to_node; + if (to.from_type == PB) { + + if (to.type_name != vib->get_pbtype_name()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong to type name!\n"); + exit(1); + } + + for (e_side side : TOTAL_2D_SIDES) { + to_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), IPIN, to.phy_pin_index, side); + if (to_node.is_valid()) + break; + } + if (!to_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", to.type_name.c_str(), to.phy_pin_index); + continue; + } + if (!rr_gsb.is_ipin_node(to_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + else if (to.from_type == SEGMENT) { + char to_dir = to.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[to.type_index]; + VTR_ASSERT(segment.name == to.type_name); + t_seg_group seg_group; + for (auto seg : vib->get_seg_groups()) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(to.seg_index < seg_group.track_num * segment.length); + e_side side; + if (to_dir == 'W') side = LEFT; + else if (to_dir == 'E') side = RIGHT; + else if (to_dir == 'N') side = TOP; + else if (to_dir == 'S') side = BOTTOM; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + //enum e_track_status track_status = determine_track_status_of_gsb + VTR_ASSERT((int)track_list.size() >= (to.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //DEC + seg_id = to.seg_index * 2 + 1; + } + else { //INC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = to.seg_index * 2; + } + enum e_track_status track_status = determine_track_status_of_gsb(rr_graph, rr_gsb, side, track_list[seg_id]); + VTR_ASSERT(track_status == TRACK_START); + to_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(OUT_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + if (!rr_gsb.is_chan_node(to_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", to_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + + + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(to_node.is_valid()); + to_nodes.push_back(to_node); + } + + + + std::vector from_nodes; + for (auto from : froms) { + RRNodeId from_node; + if (from.from_type == PB) { + + if (from.type_name != vib->get_pbtype_name()) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type name!\n"); + exit(1); + } + + for (e_side side : TOTAL_2D_SIDES) { + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), OPIN, from.phy_pin_index, side); + if (from_node.is_valid()) + break; + } + if (!from_node.is_valid()) { + VTR_LOGF_WARN(__FILE__, __LINE__, + "Can not find from node %s:%d!\n", from.type_name.c_str(), from.phy_pin_index); + continue; + } + if (!rr_gsb.is_opin_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + else if (from.from_type == SEGMENT) { + char from_dir = from.seg_dir; + //int from_index = from.seg_index; + t_segment_inf segment = segment_inf[from.type_index]; + VTR_ASSERT(segment.name == from.type_name); + t_seg_group seg_group; + for (auto seg : vib->get_seg_groups()) { + if (seg.name == segment.name) { + seg_group = seg; + break; + } + } + VTR_ASSERT(from.seg_index < seg_group.track_num * segment.length); + e_side side; + if (from_dir == 'W') side = RIGHT; + else if (from_dir == 'E') side = LEFT; + else if (from_dir == 'N') side = BOTTOM; + else if (from_dir == 'S') side = TOP; + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong segment from direction!\n"); + exit(1); + } + + std::vector track_list = rr_gsb.get_chan_node_ids_by_segment_ids(side, RRSegmentId(segment.seg_index)); + if (track_list.size() == 0) continue; + else { + VTR_ASSERT((int)track_list.size() >= (from.seg_index + 1) * 2); + size_t seg_id; + if (side == LEFT || side == BOTTOM) { //INC + seg_id = from.seg_index * 2; + } + else { //DEC + VTR_ASSERT(side == RIGHT || side == TOP); + seg_id = from.seg_index * 2 + 1; + } + from_node = rr_gsb.get_chan_node(side, track_list[seg_id]); + VTR_ASSERT(IN_PORT == rr_gsb.get_chan_node_direction(side, track_list[seg_id])); + if (!rr_gsb.is_chan_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + + + } + else if (from.from_type == MUX) { + size_t from_mux_index = vib->medium_mux_index_by_name(from.type_name); + from_node = rr_graph.node_lookup().find_node(layer, actual_coordinate.x(), actual_coordinate.y(), MEDIUM, from_mux_index); + if (!rr_gsb.is_medium_node(from_node)) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Medium node %d is not in the GSB (%d, %d)\n", from_node, rr_gsb.get_x(), rr_gsb.get_y()); + exit(1); + } + } + else { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Wrong from type!\n"); + exit(1); + } + VTR_ASSERT(from_node.is_valid()); + from_nodes.push_back(from_node); + } + + if (to_nodes.size() > 0 && from_nodes.size() > 0) { + for (auto from_node : from_nodes) { + auto iter = vib_map.begin(); + for (; iter != vib_map.end(); ++iter) { + if (iter->first == from_node) { + for (auto to_node : to_nodes) { + vib_map[from_node].push_back(to_node); + } + + } + } + if (iter == vib_map.end()) { + vib_map.emplace(std::make_pair(from_node, to_nodes)); + } + } + } + } + return vib_map; +} + +void build_edges_for_one_tileable_vib(RRGraphBuilder& rr_graph_builder, + const t_vib_map& vib_map, + const t_bend_track2track_map& sb_bend_conn, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create) { + + size_t edge_count = 0; + for (auto iter = vib_map.begin(); iter != vib_map.end(); ++iter) { + for (auto to_node : iter->second) { + rr_graph_builder.create_edge(iter->first, to_node, rr_node_driver_switches[to_node], false); + edge_count++; + } + } + for (auto iter = sb_bend_conn.begin(); iter != sb_bend_conn.end(); ++iter) { + rr_graph_builder.create_edge(iter->first, iter->second, rr_node_driver_switches[iter->second], false); + edge_count++; + } + num_edges_to_create += edge_count; +} diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h new file mode 100644 index 00000000000..5e7ca853700 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h @@ -0,0 +1,116 @@ +#ifndef TILEABLE_RR_GRAPH_GSB_H +#define TILEABLE_RR_GRAPH_GSB_H +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include + +#include "vtr_vector.h" +#include "vtr_geometry.h" + +#include "physical_types.h" +#include "device_grid.h" + +#include "rr_gsb.h" +#include "rr_graph_obj.h" +#include "rr_graph.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +/************************************************************************ + * Data stuctures related to the functions + ***********************************************************************/ +typedef std::map t_bend_track2track_map; +typedef std::map> t_vib_map; +typedef std::vector>> t_track2track_map; +typedef std::vector>> t_track2pin_map; +typedef std::vector>>> t_pin2track_map; + +/************************************************************************ + * Functions + ***********************************************************************/ +t_track2track_map build_gsb_track_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const e_switch_block_type& sb_type, + const int& Fs, + const e_switch_block_type& sb_subtype, + const int& subFs, + const bool& concat_wire, + const bool& wire_opposite_side, + const std::vector& segment_inf); + +t_bend_track2track_map build_bend_track_to_track_map(const DeviceGrid& grids, + RRGraphBuilder& rr_graph_builder, + const RRGraphView& rr_graph, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const RRSwitchId& delayless_switch, + vtr::vector& rr_node_driver_switches); + +RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids, + const RRGraphView& rr_graph, + const vtr::Point& device_chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const bool& perimeter_cb); + +void build_edges_for_one_tileable_rr_gsb(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges); + +void build_edges_for_one_tileable_rr_gsb_vib(RRGraphBuilder& rr_graph_builder, + const RRGSB& rr_gsb, + const t_bend_track2track_map& sb_bend_conn, + const t_track2pin_map& track2ipin_map, + const t_pin2track_map& opin2track_map, + const t_track2track_map& track2track_map, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges); + +t_track2pin_map build_gsb_track_to_ipin_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_in); + +t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph, + const RRGSB& rr_gsb, + const DeviceGrid& grids, + const std::vector& segment_inf, + const std::vector>& Fc_out, + const bool& opin2all_sides); + +void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + const DeviceGrid& grids, + const size_t& layer, + const vtr::Point& from_grid_coordinate, + const std::vector& directs, + const std::vector& clb_to_clb_directs); + +t_vib_map build_vib_map(const RRGraphView& rr_graph, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const RRGSB& rr_gsb, + const std::vector& segment_inf, + const size_t& layer, + const vtr::Point& gsb_coordinate, + const vtr::Point& actual_coordinate); + +void build_edges_for_one_tileable_vib(RRGraphBuilder& rr_graph_builder, + const t_vib_map& vib_map, + const t_bend_track2track_map& sb_bend_conn, + const vtr::vector& rr_node_driver_switches, + size_t& num_edges_to_create); +#endif diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp new file mode 100644 index 00000000000..5d9727aac44 --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -0,0 +1,1371 @@ +/************************************************************************ + * This file contains functions that are used to allocate nodes + * for the tileable routing resource graph builder + ***********************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_geometry.h" + +/* Headers from openfpgautil library */ +#include "openfpga_side_manager.h" + +#include "vpr_types.h" +#include "vpr_utils.h" + +#include "rr_node.h" + +#include "rr_graph_builder_utils.h" +#include "rr_graph_builder.h" +#include "tileable_chan_details_builder.h" +#include "tileable_rr_graph_node_builder.h" +#include "rr_rc_data.h" +#include "physical_types_util.h" + +/************************************************************************ + * Find the number output pins by considering all the grid + ***********************************************************************/ +static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, + const size_t& layer, + const t_rr_type& node_type, + const bool& perimeter_cb) { + size_t num_grid_rr_nodes = 0; + + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + t_physical_tile_loc tile_loc(ix, iy, layer); + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { + continue; + } + + /* Skip height > 1 or width > 1 tiles (mostly heterogeneous blocks) */ + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { + continue; + } + + std::vector io_side = {TOP, RIGHT, BOTTOM, LEFT}; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids.get_physical_type(tile_loc))) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + vtr::Point grid_coordinate(ix, iy); + io_side = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); + } + + switch (node_type) { + case OPIN: + /* get the number of OPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, DRIVER, io_side); + break; + case IPIN: + /* get the number of IPINs */ + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, RECEIVER, io_side); + break; + case SOURCE: + /* SOURCE: number of classes whose type is DRIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, DRIVER); + break; + case SINK: + /* SINK: number of classes whose type is RECEIVER */ + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, RECEIVER); + break; + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid routing resource node!\n"); + exit(1); + } + } + } + + return num_grid_rr_nodes; +} + +static size_t estimate_num_medium_rr_nodes(const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer) { + size_t num_grid_rr_nodes = 0; + + VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); + for (size_t ix = 0; ix < grids.width(); ++ix) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + + const VibInf* vib = vib_grid.get_vib(layer, ix, iy); + if (!vib) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "VIB at (%d, %d) is EMPTY!\n", ix, iy); + exit(1); + continue; + } + + size_t count = 0; + for (size_t i_first_stage = 0; i_first_stage < vib->get_first_stages().size(); i_first_stage++) { + auto first_stage = vib->get_first_stages()[i_first_stage]; + if (first_stage.froms.size() == 0) { + VTR_LOGF_ERROR(__FILE__, __LINE__, + "VIB first stage '%s' at (%d, %d) has no from!\n", first_stage.mux_name.c_str(), ix, iy); + exit(1); + } + count++; + } + + VTR_ASSERT(count == vib->get_first_stages().size()); + num_grid_rr_nodes += count; + } + } + + return num_grid_rr_nodes; +} + +/************************************************************************ + * For X-direction Channel: CHANX + * We pair each x-direction routing channel to the grid below it + * as they share the same coordinate + * + * As such, the range of CHANX coordinate starts from x = 1, y = 0 + * which is the grid (I/O) at the left bottom of the fabric + * + * As such, the range of CHANX coordinate ends to x = width - 2, y = height - 2 + * which is the grid at the top right of the core fabric + * Note that the I/O ring is + * + * TOP SIDE OF FPGA + * + * +-------------+ +-------------+ +---------------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][height-1] | + * +-------------+ +-------------+ +---------------------+ + * + * +-------------+ +-------------+ +---------------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][0] | | [2][0] | | [width-2][height-2] | + * +-------------+ +-------------+ +---------------------+ + * + * +-------------+ +-------------+ +---------------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][height-2] | + * +-------------+ +-------------+ +---------------------+ + * + * ... ... ... + * + * +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][1] | | [2][1] | | [width-2][1] | + * +-------------+ +-------------+ +--------------+ + * + * LEFT +-------------+ +-------------+ +--------------+ RIGHT + * SIDE | Grid | | Grid | ... | Grid | SIDE + * GRID | [1][1] | | [2][1] | | [width-2][1] | GRID + * +-------------+ +-------------+ +--------------+ + * + * +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | ... | X-Channel | + * | [1][0] | | [2][0] | | [width-2][0] | + * +-------------+ +-------------+ +--------------+ + * + * +-------------+ +-------------+ +--------------+ + * | Grid | | Grid | ... | Grid | + * | [1][0] | | [2][0] | | [width-2][0] | + * +-------------+ +-------------+ +--------------+ + * + * BOTTOM SIDE OF FPGA + * + * The figure above describe how the X-direction routing channels are + * organized in a homogeneous FPGA fabric + * Note that we talk about general-purpose uni-directional routing architecture here + * It means that a routing track may span across multiple grids + * However, the hard limits are as follows + * All the routing tracks will start at the most LEFT routing channel + * All the routing tracks will end at the most RIGHT routing channel + * + * Things will become more complicated in terms of track starting and end + * in the context of heterogeneous FPGAs + * We may have a grid which span multiple column and rows, as exemplified in the figure below + * In such case, + * all the routing tracks [x-1][y] at the left side of the grid [x][y] are forced to end + * all the routing tracks [x+2][y] at the right side of the grid [x][y] are forced to start + * And there are no routing tracks inside the grid[x][y] + * It means that X-channel [x][y] & [x+1][y] will no exist + * + * +------------+ +-------------+ +-------------+ +--------------+ + * | X-Channel | | X-Channel | | X-Channel | | X-Channel | + * | [x-1][y+2] | | [x][y+2] | | [x+1][y+2] | | [x+2][y+2] | + * +------------+ +-------------+ +-------------+ +--------------+ + * + * +------------+ +-----------------------------------+ +--------------+ + * | Grid | | | | Grid | + * | [x-1][y+1] | | | | [x+2][y+1] | + * +------------+ | | +--------------+ + * | | + * +------------+ | | +--------------+ + * | X-channel | | Grid | | X-Channel | + * | [x-1][y] | | [x][y] - [x+1][y+1] | | [x+2][y] | + * +------------+ | | +--------------+ + * | | + * +------------+ | | +--------------+ + * | Grid | | | | Grid | + * | [x-1][y] | | | | [x+2][y] | + * +------------+ +-----------------------------------+ +--------------+ + * + * + * + ***********************************************************************/ +static size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids, + const size_t& layer, + const size_t& chan_width, + const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + size_t num_chanx_rr_nodes = 0; + /* Default x-channel boundary box */ + size_t start_x = 1; + size_t end_x = grids.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grids.width(); + } + size_t max_seg_length = grids.width() - 2; + if (perimeter_cb) { + max_seg_length = grids.width(); + } + + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + for (size_t ix = start_x; ix < end_x; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { + continue; + } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { + force_start = true; + } + if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { + force_end = true; + } + if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { + force_end = true; + } + + /* Evaluate if the routing channel locates in the middle of a grid */ + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chanx_rr_nodes += chanx_details.get_num_ending_tracks(Direction::DEC); + } + } + + return num_chanx_rr_nodes; +} + +/************************************************************************ + * Estimate the number of CHANY rr_nodes for Y-direction routing channels + * The technical rationale is very similar to the X-direction routing channel + * Refer to the detailed explanation there + ***********************************************************************/ +static size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids, + const size_t& layer, + const size_t& chan_width, + const std::vector& segment_infs, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + size_t num_chany_rr_nodes = 0; + /* Default x-channel boundary box */ + size_t start_y = 1; + size_t end_y = grids.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grids.height(); + } + size_t max_seg_length = grids.height() - 2; + if (perimeter_cb) { + max_seg_length = grids.height(); + } + + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + for (size_t iy = start_y; iy < end_y; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { + continue; + } + + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { + force_start = true; + } + if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { + force_end = true; + } + if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, max_seg_length, force_start, force_end, segment_infs); + /* When an INC_DIRECTION CHANX starts, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_starting_tracks(Direction::INC); + /* When an DEC_DIRECTION CHANX ends, we need a new rr_node */ + num_chany_rr_nodes += chany_details.get_num_ending_tracks(Direction::DEC); + } + } + + return num_chany_rr_nodes; +} + +/************************************************************************ + * Estimate the number of nodes by each type in a routing resource graph + ***********************************************************************/ +static std::vector estimate_num_rr_nodes(const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + + /* Reset the OPIN, IPIN, SOURCE, SINK counter to be zero */ + std::vector num_rr_nodes_per_type(NUM_RR_TYPES, 0); + + /** + * 1 Find number of rr nodes related to grids + */ + if (!vib_grid.is_empty()) + num_rr_nodes_per_type[MEDIUM] = estimate_num_medium_rr_nodes(grids, vib_grid, layer); + else + num_rr_nodes_per_type[MEDIUM] = 0; + + num_rr_nodes_per_type[OPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, OPIN, perimeter_cb); + num_rr_nodes_per_type[IPIN] = estimate_num_grid_rr_nodes_by_type(grids, layer, IPIN, perimeter_cb); + num_rr_nodes_per_type[SOURCE] = estimate_num_grid_rr_nodes_by_type(grids, layer, SOURCE, perimeter_cb); + num_rr_nodes_per_type[SINK] = estimate_num_grid_rr_nodes_by_type(grids, layer, SINK, perimeter_cb); + + + /** + * 2. Assign the segments for each routing channel, + * To be specific, for each routing track, we assign a routing segment. + * The assignment is subject to users' specifications, such as + * a. length of each type of segment + * b. frequency of each type of segment. + * c. routing channel width + * + * SPECIAL for fringes: + * All segments will start and ends with no exception + * + * IMPORTANT: we should be aware that channel width maybe different + * in X-direction and Y-direction channels!!! + * So we will load segment details for different channels + */ + num_rr_nodes_per_type[CHANX] = estimate_num_chanx_rr_nodes(grids, layer, + chan_width.x(), + segment_inf_x, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + num_rr_nodes_per_type[CHANY] = estimate_num_chany_rr_nodes(grids, layer, + chan_width.y(), + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + return num_rr_nodes_per_type; +} + +/************************************************************************ + * Allocate rr_nodes to a rr_graph object + * This function just allocate the memory and ensure its efficiency + * It will NOT fill detailed information for each node!!! + * + * Note: ensure that there are NO nodes in the rr_graph + ***********************************************************************/ +void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + VTR_ASSERT(0 == rr_graph_builder.rr_nodes().size()); + + std::vector num_rr_nodes_per_type = estimate_num_rr_nodes(grids, + vib_grid, + layer, + chan_width, + segment_inf_x, + segment_inf_y, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + /* Reserve the number of node to be memory efficient */ + size_t num_nodes = 0; + for (const size_t& num_node_per_type : num_rr_nodes_per_type) { + num_nodes += num_node_per_type; + } + + rr_graph_builder.reserve_nodes(num_nodes); + + rr_node_driver_switches.resize(num_nodes); +} + +/************************************************************************ + * Configure OPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const DeviceGrid& grids, + const std::vector& wanted_sides, + const RRSwitchId& delayless_switch) { + /* Walk through the width height of each grid, + * get pins and configure the rr_nodes + */ + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { + /* Walk through sides */ + for (e_side side : wanted_sides) { + SideManager side_manager(side); + /* Find OPINs */ + /* Configure pins by pins */ + std::vector opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), + width, height); + for (const int& pin_num : opin_list) { + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, OPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(OPIN_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = delayless_switch; + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + + } /* End of loading OPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ +} + +/************************************************************************ + * Configure IPIN rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const DeviceGrid& grids, + const std::vector& wanted_sides, + const RRSwitchId& wire_to_ipin_switch) { + /* Walk through the width and height of each grid, + * get pins and configure the rr_nodes + */ + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(t_physical_tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer)); + for (int width = 0; width < phy_tile_type->width; ++width) { + for (int height = 0; height < phy_tile_type->height; ++height) { + /* Walk through sides */ + for (e_side side : wanted_sides) { + SideManager side_manager(side); + /* Find IPINs */ + /* Configure pins by pins */ + std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); + for (const int& pin_num : ipin_list) { + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, IPIN, pin_num, side); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x() + width, + grid_coordinate.y() + height, + grid_coordinate.x() + width, + grid_coordinate.y() + height); + rr_graph_builder.add_node_side(node, side_manager.get_side()); + rr_graph_builder.set_node_pin_num(node, pin_num); + + rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); + + /* cost index is a FIXED value for OPIN */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(IPIN_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = wire_to_ipin_switch; + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + + } /* End of loading IPIN rr_nodes */ + } /* End of side enumeration */ + } /* End of height enumeration */ + } /* End of width enumeration */ +} + +/************************************************************************ + * Configure SOURCE rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const DeviceGrid& grids, + const RRSwitchId& delayless_switch) { + /* Set a SOURCE rr_node for each DRIVER class */ + t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (DRIVER != phy_tile_type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SOURCE, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + phy_tile_type->width - 1, + grid_coordinate.y() + phy_tile_type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + rr_graph_builder.set_node_layer(node, (int)layer); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, phy_tile_type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SOURCE */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SOURCE_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = delayless_switch; + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + + } /* End of class enumeration */ +} + +/************************************************************************ + * Configure SINK rr_nodes for this grid + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, ptc_num (pin_num), + * + * Note: this function should be applied ONLY to grid with 0 width offset and 0 height offset!!! + ***********************************************************************/ +static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const DeviceGrid& grids, + const RRSwitchId& delayless_switch) { + /* Set a SINK rr_node for each RECEIVER class */ + t_physical_tile_loc tile_loc(grid_coordinate.x(), grid_coordinate.y(), layer); + t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); + for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if (RECEIVER != phy_tile_type->class_inf[iclass].type) { + continue; + } + + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), SINK, iclass); + + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x() + phy_tile_type->width - 1, + grid_coordinate.y() + phy_tile_type->height - 1); + rr_graph_builder.set_node_class_num(node, iclass); + rr_graph_builder.set_node_layer(node, layer); + + rr_graph_builder.set_node_capacity(node, 1); + + /* The capacity should be the number of pins in this class*/ + rr_graph_builder.set_node_capacity(node, phy_tile_type->class_inf[iclass].num_pins); + + /* cost index is a FIXED value for SINK */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(SINK_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = delayless_switch; + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + + } /* End of class enumeration */ +} + +static void load_one_grid_medium_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& grid_coordinate, + const VibDeviceGrid& vib_grid) { + + const VibInf* vib = vib_grid.get_vib(layer, grid_coordinate.x(), grid_coordinate.y()); + size_t num_medium_nodes = vib->get_first_stages().size(); + for (size_t i_medium = 0; i_medium < num_medium_nodes; i_medium++) { + /* Create a new node and fill information */ + RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x(), grid_coordinate.y(), MEDIUM, i_medium, TOTAL_2D_SIDES[0]); + /* node bounding box */ + rr_graph_builder.set_node_coordinates(node, grid_coordinate.x(), + grid_coordinate.y(), + grid_coordinate.x(), + grid_coordinate.y()); + //rr_graph_builder.add_node_side(node, SIDES[0]); + rr_graph_builder.set_node_medium_num(node, i_medium); + + rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); + + /* cost index is a FIXED value for MEDIUM */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(MEDIUM_COST_INDEX)); + + /* Switch info */ + rr_node_driver_switches[node] = RRSwitchId(vib->get_switch_idx()); + + /* RC data */ + rr_graph_builder.set_node_rc_index(node, NodeRCIndex(find_create_rr_rc_data(0., 0., rr_rc_data))); + } + +} + +/************************************************************************ + * Create all the rr_nodes for grids + ***********************************************************************/ +static void load_grid_nodes_basic_info(RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::vector& rr_rc_data, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch, + const bool& perimeter_cb) { + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + t_physical_tile_loc tile_loc(ix, iy, layer); + /* Skip EMPTY tiles */ + if (true == is_empty_type(grids.get_physical_type(tile_loc))) { + continue; + } + + /* We only build rr_nodes for grids with width_offset = 0 and height_offset = 0 */ + if ((0 < grids.get_width_offset(tile_loc)) + || (0 < grids.get_height_offset(tile_loc))) { + continue; + } + + vtr::Point grid_coordinate(ix, iy); + std::vector wanted_sides{TOP, RIGHT, BOTTOM, LEFT}; + + /* If this is the block on borders, we consider IO side */ + if (true == is_io_type(grids.get_physical_type(tile_loc))) { + vtr::Point io_device_size(grids.width() - 1, grids.height() - 1); + wanted_sides = determine_io_grid_pin_side(io_device_size, grid_coordinate, perimeter_cb); + } + + for (e_side side : wanted_sides) { + for (int width_offset = 0; width_offset < grids.get_physical_type(tile_loc)->width; ++width_offset) { + int x_tile = ix + width_offset; + for (int height_offset = 0; height_offset < grids.get_physical_type(tile_loc)->height; ++height_offset) { + int y_tile = iy + height_offset; + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, OPIN, grids.get_physical_type(tile_loc)->num_pins, side); + rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, IPIN, grids.get_physical_type(tile_loc)->num_pins, side); + } + } + } + + /* Configure source rr_nodes for this grid */ + load_one_grid_source_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + grids, + delayless_switch); + + /* Configure sink rr_nodes for this grid */ + load_one_grid_sink_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + grids, + delayless_switch); + + /* Configure opin rr_nodes for this grid */ + load_one_grid_opin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + grids, + wanted_sides, + delayless_switch); + + /* Configure ipin rr_nodes for this grid */ + load_one_grid_ipin_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + grids, + wanted_sides, + wire_to_ipin_switch); + } + } + + if (!vib_grid.is_empty()) { + /* Create medium nodes */ + VTR_ASSERT(grids.width() == vib_grid.width() && grids.height() == vib_grid.height()); + for (size_t iy = 0; iy < grids.height(); ++iy) { + for (size_t ix = 0; ix < grids.width(); ++ix) { + + t_physical_tile_loc tile_loc(ix, iy, layer); + VTR_ASSERT(vib_grid.vib_pbtype_name(layer, ix, iy) == grids.get_physical_type(tile_loc)->name); + vtr::Point grid_coordinate(ix, iy); + + rr_graph_builder.node_lookup().reserve_nodes(layer, ix, iy, MEDIUM, vib_grid.num_medium_nodes(layer, ix, iy), TOTAL_2D_SIDES[0]); + + load_one_grid_medium_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + layer, grid_coordinate, + vib_grid); + + } + } + } + + + //Copy the SOURCE/SINK nodes to all offset positions for blocks with width > 1 and/or height > 1 + // This ensures that look-ups on non-root locations will still find the correct SOURCE/SINK + for (size_t x = 0; x < grids.width(); x++) { + for (size_t y = 0; y < grids.height(); y++) { + t_physical_tile_loc tile_loc(x, y, 0); + int width_offset = grids.get_width_offset(tile_loc); + int height_offset = grids.get_height_offset(tile_loc); + if (width_offset != 0 || height_offset != 0) { + int root_x = x - width_offset; + int root_y = y - height_offset; + + rr_graph_builder.node_lookup().mirror_nodes(0, + vtr::Point(root_x, root_y), + vtr::Point(x, y), + SOURCE, + TOTAL_2D_SIDES[0]); + rr_graph_builder.node_lookup().mirror_nodes(0, + vtr::Point(root_x, root_y), + vtr::Point(x, y), + SINK, + TOTAL_2D_SIDES[0]); + } + } + } +} + +/************************************************************************ + * Initialize the basic information of routing track rr_nodes + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + ***********************************************************************/ +static void load_one_chan_rr_nodes_basic_info(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + std::vector& rr_rc_data, + const size_t& layer, + const vtr::Point& chan_coordinate, + const t_rr_type& chan_type, + ChanNodeDetails& chan_details, + const std::vector& segment_infs, + const t_unified_to_parallel_seg_index& seg_index_map, + const int& cost_index_offset) { + /* Check each node_id(potential ptc_num) in the channel : + * If this is a starting point, we set a new rr_node with xlow/ylow, ptc_num + * If this is a ending point, we set xhigh/yhigh and track_ids + * For other nodes, we set changes in track_ids + */ + for (size_t itrack = 0; itrack < chan_details.get_chan_width(); ++itrack) { + /* For INC direction, a starting point requires a new chan rr_node */ + if (((true == chan_details.is_track_start(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + /* For DEC direction, an ending point requires a new chan rr_node */ + || ((true == chan_details.is_track_end(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Create a new chan rr_node */ + RRNodeId node = rr_graph_builder.create_node(layer, chan_coordinate.x(), chan_coordinate.y(), chan_type, itrack); + + rr_graph_builder.set_node_direction(node, chan_details.get_track_direction(itrack)); + rr_graph_builder.add_node_track_num(node, chan_coordinate, itrack); + rr_node_track_ids[node].push_back(itrack); + + rr_graph_builder.set_node_capacity(node, 1); + rr_graph_builder.set_node_layer(node, layer); + + /* assign switch id */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); + rr_node_driver_switches[node] = RRSwitchId(segment_infs[parallel_seg_id].arch_opin_switch); + + /* Update chan_details with node_id */ + chan_details.set_track_node_id(itrack, size_t(node)); + + /* cost index depends on the segment index */ + rr_graph_builder.set_node_cost_index(node, RRIndexedDataId(cost_index_offset + parallel_seg_id)); + + if (chan_details.is_track_start(itrack)) { + rr_graph_builder.set_node_bend_start(node, chan_details.get_track_bend_start(itrack)); + } + if (chan_details.is_track_end(itrack)) { + rr_graph_builder.set_node_bend_end(node, chan_details.get_track_bend_end(itrack)); + } + /* Finish here, go to next */ + } + + /* For INC direction, an ending point requires an update on xhigh and yhigh */ + if (((true == chan_details.is_track_end(itrack)) + && (Direction::INC == chan_details.get_track_direction(itrack))) + || + /* For DEC direction, an starting point requires an update on xlow and ylow */ + ((true == chan_details.is_track_start(itrack)) + && (Direction::DEC == chan_details.get_track_direction(itrack)))) { + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* set xhigh/yhigh and push changes to track_ids */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Do not update track_ids for length-1 wires, they should have only 1 track_id */ + if ((rr_graph.node_xhigh(rr_node_id) > rr_graph.node_xlow(rr_node_id)) + || (rr_graph.node_yhigh(rr_node_id) > rr_graph.node_ylow(rr_node_id))) { + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.add_node_track_num(rr_node_id, chan_coordinate, itrack); + } + /* Finish node RC attributes */ + size_t seg_id = chan_details.get_track_segment_id(itrack); + e_parallel_axis wanted_axis = chan_type == CHANX ? X_AXIS : Y_AXIS; + size_t parallel_seg_id = find_parallel_seg_index(seg_id, seg_index_map, wanted_axis); + float node_R = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Rmetal; + float node_C = rr_graph.node_length(rr_node_id) * segment_infs[parallel_seg_id].Cmetal; + rr_graph_builder.set_node_rc_index(rr_node_id, NodeRCIndex(find_create_rr_rc_data(node_R, node_C, rr_rc_data))); + + if (chan_details.is_track_start(itrack)) { + rr_graph_builder.set_node_bend_start(rr_node_id, chan_details.get_track_bend_start(itrack)); + } + if (chan_details.is_track_end(itrack)) { + rr_graph_builder.set_node_bend_end(rr_node_id, chan_details.get_track_bend_end(itrack)); + } + /* Finish here, go to next */ + } + + /* Finish processing starting and ending tracks */ + if ((true == chan_details.is_track_start(itrack)) + || (true == chan_details.is_track_end(itrack))) { + /* Finish here, go to next */ + continue; + } + + /* For other nodes, we get the node_id and just update track_ids */ + /* Ensure those nodes are neither starting nor ending points */ + VTR_ASSERT((false == chan_details.is_track_start(itrack)) + && (false == chan_details.is_track_end(itrack))); + + /* Get the node_id */ + const RRNodeId& rr_node_id = RRNodeId(chan_details.get_track_node_id(itrack)); + + /* Do a quick check, make sure we do not mistakenly modify other nodes */ + VTR_ASSERT(chan_type == rr_graph.node_type(rr_node_id)); + VTR_ASSERT(chan_details.get_track_direction(itrack) == rr_graph.node_direction(rr_node_id)); + + /* Deposit xhigh and yhigh using the current chan_coordinate + * We will update when this track ends + */ + rr_graph_builder.set_node_coordinates(rr_node_id, rr_graph.node_xlow(rr_node_id), + rr_graph.node_ylow(rr_node_id), + chan_coordinate.x(), + chan_coordinate.y()); + + /* Update track_ids */ + rr_node_track_ids[rr_node_id].push_back(itrack); + rr_graph_builder.add_node_track_num(rr_node_id, chan_coordinate, itrack); + /* Finish here, go to next */ + } +} + +/************************************************************************ + * Initialize the basic information of X-channel rr_nodes: + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + * grid_info : pb_graph_pin + ***********************************************************************/ +static void load_chanx_rr_nodes_basic_info(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + std::vector& rr_rc_data, + const DeviceGrid& grids, + const size_t& layer, + const size_t& chan_width, + const std::vector& segment_infs, + const t_unified_to_parallel_seg_index& segment_index_map, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + size_t start_x = 1; + size_t end_x = grids.width() - 1; + if (perimeter_cb) { + start_x = 0; + end_x = grids.width(); + } + size_t max_seg_length = grids.width() - 2; + if (perimeter_cb) { + max_seg_length = grids.width(); + } + + /* For X-direction Channel: CHANX */ + for (size_t iy = 0; iy < grids.height() - 1; ++iy) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t ix = start_x; ix < end_x; ++ix) { + vtr::Point chanx_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channels are not allowed */ + if ((false == through_channel) + && (false == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb))) { + continue; + } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chanx_exist(chanx_coord)) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the RIGHT side a heterogeneous block + * - the routing channel touch the LEFT side of FPGA + */ + if (true == is_chanx_right_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { + force_start = true; + } + if (shrink_boundary && device_grid_annotation.is_chanx_start(chanx_coord)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the LEFT side a heterogeneous block + * - the routing channel touch the RIGHT side of FPGA + */ + if (true == is_chanx_left_to_multi_height_grid(grids, layer, chanx_coord, perimeter_cb, through_channel)) { + force_end = true; + } + if (shrink_boundary && device_grid_annotation.is_chanx_end(chanx_coord)) { + force_end = true; + } + + ChanNodeDetails chanx_details = build_unidir_chan_node_details(chan_width, max_seg_length, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chanx */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ + ChanNodeDetails chanx_details_tt = build_unidir_chan_node_details(chan_width, max_seg_length, + false, false, segment_infs); + chanx_details_tt.set_track_node_ids(track_node_ids); + + /* TODO: + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + */ + if (true == is_chanx_exist(grids, layer, chanx_coord, perimeter_cb, through_channel)) { + /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */ + /* For INC_DIRECTION, we use clockwise rotation + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ + chanx_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ + chanx_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chanx_details_tt.get_track_node_ids(); + chanx_details.set_track_node_ids(track_node_ids); + } + + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + rr_rc_data, + layer, chanx_coord, CHANX, + chanx_details, + segment_infs, + segment_index_map, + CHANX_COST_INDEX_START); + /* Get a copy of node_ids */ + track_node_ids = chanx_details.get_track_node_ids(); + } + } +} + +/************************************************************************ + * Initialize the basic information of Y-channel rr_nodes: + * coordinates: xlow, ylow, xhigh, yhigh, + * features: capacity, track_ids, ptc_num, direction + ***********************************************************************/ +static void load_chany_rr_nodes_basic_info(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + std::vector& rr_rc_data, + const DeviceGrid& grids, + const size_t& layer, + const size_t& chan_width, + const std::vector& segment_infs, + const size_t& num_segment_x, + const t_unified_to_parallel_seg_index& seg_index_map, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + /* Default y-channel boundary box */ + size_t start_y = 1; + size_t end_y = grids.height() - 1; + if (perimeter_cb) { + start_y = 0; + end_y = grids.height(); + } + size_t max_seg_length = grids.height() - 2; + if (perimeter_cb) { + max_seg_length = grids.height(); + } + + /* For Y-direction Channel: CHANY */ + for (size_t ix = 0; ix < grids.width() - 1; ++ix) { + /* Keep a vector of node_ids for the channels, because we will rotate them when walking through ix */ + std::vector track_node_ids; + + for (size_t iy = start_y; iy < end_y; ++iy) { + vtr::Point chany_coord(ix, iy); + + /* Bypass if the routing channel does not exist when through channel are not allowed */ + if ((false == through_channel) + && (false == is_chany_exist(grids, layer, chany_coord, perimeter_cb))) { + continue; + } + /* Bypass if the routing channel does not exist when a shrink boundary is considered */ + if (shrink_boundary && !device_grid_annotation.is_chany_exist(chany_coord)) { + continue; + } + + bool force_start = false; + bool force_end = false; + + /* All the tracks have to start when + * - the routing channel touch the TOP side a heterogeneous block + * - the routing channel touch the BOTTOM side of FPGA + */ + if (true == is_chany_top_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { + force_start = true; + } + if (shrink_boundary && device_grid_annotation.is_chany_start(chany_coord)) { + force_start = true; + } + + /* All the tracks have to end when + * - the routing channel touch the BOTTOM side a heterogeneous block + * - the routing channel touch the TOP side of FPGA + */ + if (true == is_chany_bottom_to_multi_width_grid(grids, layer, chany_coord, perimeter_cb, through_channel)) { + force_end = true; + } + if (shrink_boundary && device_grid_annotation.is_chany_end(chany_coord)) { + force_end = true; + } + + ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, max_seg_length, + force_start, force_end, segment_infs); + /* Force node_ids from the previous chany + * This will not be applied when the routing channel is cut off (force to start) + */ + if (0 < track_node_ids.size()) { + /* Rotate should be done based on a typical case of routing tracks. + * Tracks on the borders are not regularly started and ended, + * which causes the node_rotation malfunction + */ + ChanNodeDetails chany_details_tt = build_unidir_chan_node_details(chan_width, max_seg_length, + false, false, segment_infs); + + chany_details_tt.set_track_node_ids(track_node_ids); + + /* TODO: + * Do NOT rotate the tracks when the routing channel + * locates inside a multi-height and multi-width grid + * Let the routing channel passing through the grid (if through channel is allowed!) + * An example: + * + * +------------------------------ + * | | + * | Grid | + * track0 ----->+-----------------------------+----> track0 + * | | + * we should rotate only once at the bottom side of a grid + */ + if (true == is_chany_exist(grids, layer, chany_coord, perimeter_cb, through_channel)) { + /* Rotate the chany_details by an offset of 1*/ + /* For INC_DIRECTION, we use clockwise rotation + * node_id A ----> -----> node_id D + * node_id B ----> / ----> node_id A + * node_id C ----> / ----> node_id B + * node_id D ----> ----> node_id C + */ + chany_details_tt.rotate_track_node_id(1, Direction::INC, true); + /* For DEC_DIRECTION, we use clockwise rotation + * node_id A <----- <----- node_id B + * node_id B <----- \ <----- node_id C + * node_id C <----- \ <----- node_id D + * node_id D <----- <----- node_id A + */ + chany_details_tt.rotate_track_node_id(1, Direction::DEC, false); + } + + track_node_ids = chany_details_tt.get_track_node_ids(); + chany_details.set_track_node_ids(track_node_ids); + } + /* Configure CHANX in this channel */ + load_one_chan_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + rr_rc_data, + layer, chany_coord, CHANY, + chany_details, + segment_infs, + seg_index_map, + CHANX_COST_INDEX_START + num_segment_x); + /* Get a copy of node_ids */ + track_node_ids = chany_details.get_track_node_ids(); + } + } +} + +/************************************************************************ + * Reverse the track_ids of CHANX and CHANY nodes in DEC_DIRECTION + * This is required as the track ids are allocated in the sequence + * of incrementing x and y + * However, DEC direction routing tracks should have a reversed sequence in + * track ids + ***********************************************************************/ +static void reverse_dec_chan_rr_node_track_ids(const RRGraphView& rr_graph, + std::map>& rr_node_track_ids) { + // this should call rr_graph_builder to do the job + for (const RRNodeId& node : rr_graph.nodes()) { + /* Bypass condition: only focus on CHANX and CHANY in DEC_DIRECTION */ + if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) { + continue; + } + /* Reach here, we must have a node of CHANX or CHANY */ + if (Direction::DEC != rr_graph.node_direction(node)) { + continue; + } + std::reverse(rr_node_track_ids[node].begin(), + rr_node_track_ids[node].end()); + } +} + +/************************************************************************ + * Create all the rr_nodes covering both grids and routing channels + ***********************************************************************/ +void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + std::vector& rr_rc_data, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel) { + /* Allocates and loads all the structures needed for fast lookups of the * + * index of an rr_node. rr_node_indices is a matrix containing the index * + * of the *first* rr_node at a given (i,j) location. */ + + /* Alloc the lookup table + * .. warning: It is mandatory. There are bugs in resize() when called incrementally in RRSpatialLookup. + * When comment the following block out, you will see errors */ + for (t_rr_type rr_type : RR_TYPES) { + if (rr_type == CHANX) { + rr_graph_builder.node_lookup().resize_nodes(layer, grids.height(), grids.width(), rr_type, NUM_2D_SIDES); + } else { + rr_graph_builder.node_lookup().resize_nodes(layer, grids.width(), grids.height(), rr_type, NUM_2D_SIDES); + } + } + + load_grid_nodes_basic_info(rr_graph_builder, + rr_node_driver_switches, + rr_rc_data, + grids, vib_grid, layer, + wire_to_ipin_switch, + delayless_switch, perimeter_cb); + + load_chanx_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + rr_rc_data, + grids, layer, + chan_width.x(), + segment_inf_x, + segment_index_map, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + load_chany_rr_nodes_basic_info(rr_graph, + rr_graph_builder, + rr_node_driver_switches, + rr_node_track_ids, + rr_rc_data, + grids, layer, + chan_width.y(), + segment_inf_y, + segment_inf_x.size(), + segment_index_map, + device_grid_annotation, + shrink_boundary, + perimeter_cb, + through_channel); + + reverse_dec_chan_rr_node_track_ids(rr_graph, + rr_node_track_ids); + + /* Update node look-up for CHANX and CHANY nodes */ + for (const RRNodeId& rr_node_id : rr_graph.nodes()) { + if (CHANX == rr_graph.node_type(rr_node_id) || CHANY == rr_graph.node_type(rr_node_id)) { + rr_graph_builder.add_track_node_to_lookup(rr_node_id); + } + } +} diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h new file mode 100644 index 00000000000..0dd69ac2aff --- /dev/null +++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.h @@ -0,0 +1,57 @@ +#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H +#define TILEABLE_RR_GRAPH_NODE_BUILDER_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +/* Headers from vtrutil library */ +#include "vtr_geometry.h" + +/* Headers from readarch library */ +#include "physical_types.h" + +/* Headers from vpr library */ +#include "device_grid.h" +#include "device_grid_annotation.h" +#include "rr_node_types.h" +#include "rr_graph_type.h" +#include "rr_graph_view.h" +#include "rr_graph_builder.h" + +/******************************************************************** + * Function declaration + *******************************************************************/ + +void alloc_tileable_rr_graph_nodes(RRGraphBuilder& rr_graph_builder, + vtr::vector& driver_switches, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel); + +void create_tileable_rr_graph_nodes(const RRGraphView& rr_graph, + RRGraphBuilder& rr_graph_builder, + vtr::vector& rr_node_driver_switches, + std::map>& rr_node_track_ids, + std::vector& rr_rc_data, + const DeviceGrid& grids, + const VibDeviceGrid& vib_grid, + const size_t& layer, + const vtr::Point& chan_width, + const std::vector& segment_inf_x, + const std::vector& segment_inf_y, + const t_unified_to_parallel_seg_index& segment_index_map, + const RRSwitchId& wire_to_ipin_switch, + const RRSwitchId& delayless_switch, + const DeviceGridAnnotation& device_grid_annotation, + const bool& shrink_boundary, + const bool& perimeter_cb, + const bool& through_channel); + +#endif diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 853725c5bb9..f960f5c8668 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -40,8 +40,6 @@ static AtomPinId find_atom_pin_for_pb_route_id(ClusterBlockId clb, int pb_route_ static bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::regex& blif_model_regex); static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::regex& blif_model_regex); -static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); -static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); /******************** Subroutine definitions *********************************/ @@ -1125,7 +1123,7 @@ static void load_pb_graph_pin_lookup_from_index_rec(t_pb_graph_pin** pb_graph_pi } /* Create a lookup that returns a pb_graph_pin pointer given the pb_graph_pin index */ -static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { +t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type) { t_pb_graph_pin** pb_graph_pin_lookup_from_type = nullptr; t_pb_graph_node* pb_graph_head = type->pb_graph_head; @@ -1153,7 +1151,7 @@ static t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_ } /* Free pb_graph_pin lookup array */ -static void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { +void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type) { if (pb_graph_pin_lookup_from_type == nullptr) { return; } @@ -1734,6 +1732,27 @@ std::vector get_all_pb_graph_node_primitives(const t_pb_ return primitives; } +bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, + const VibInf* vib, + t_rr_type node_type, + int node_ptc) { + + if (node_type == CHANX || node_type == CHANY) { + return true; + } else if (node_type == MEDIUM) { // This function will check all types of nodes. MEDIUM is added for avoiding errors. + VTR_ASSERT(vib != nullptr); + return (node_ptc < (int)vib->get_first_stages().size()); + } else { + VTR_ASSERT(node_type == IPIN || node_type == OPIN || node_type == SINK || node_type == SOURCE); + if (node_type == IPIN || node_type == OPIN) { + return is_pin_on_tile(physical_tile, node_ptc); + } else { + VTR_ASSERT(node_type == SINK || node_type == SOURCE); + return is_class_on_tile(physical_tile, node_ptc); + } + } +} + bool is_inter_cluster_node(const RRGraphView& rr_graph_view, RRNodeId node_id) { auto node_type = rr_graph_view.node_type(node_id); diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index f2b62cfac1c..aa36ce3f03c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -193,7 +193,9 @@ t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* m /// pb_graph_node. t_pb_graph_pin* get_pb_graph_node_pin_from_pb_graph_node(t_pb_graph_node* pb_graph_node, int ipin); t_pb_graph_pin* get_pb_graph_node_pin_from_block_pin(ClusterBlockId iblock, int ipin); +t_pb_graph_pin** alloc_and_load_pb_graph_pin_lookup_from_index(t_logical_block_type_ptr type); vtr::vector alloc_and_load_pin_id_to_pb_mapping(); +void free_pb_graph_pin_lookup_from_index(t_pb_graph_pin** pb_graph_pin_lookup_from_type); void free_pin_id_to_pb_mapping(vtr::vector& pin_id_to_pb_mapping); std::tuple get_cluster_blk_physical_spec(ClusterBlockId cluster_blk_id); @@ -240,6 +242,11 @@ void print_timing_stats(const std::string& name, std::vector get_all_pb_graph_node_primitives(const t_pb_graph_node* pb_graph_node); +bool is_inter_cluster_node(t_physical_tile_type_ptr physical_tile, + const VibInf* vib, + t_rr_type node_type, + int node_ptc); + bool is_inter_cluster_node(const RRGraphView& rr_graph_view, RRNodeId node_id); @@ -313,6 +320,10 @@ t_arch_switch_inf create_internal_arch_sw(float delay); void add_pb_child_to_list(std::list& pb_list, const t_pb* parent_pb); +// apply route constraints for route flow +class VprConstraints; +void apply_route_constraints(VprConstraints& constraint); + /** * @brief Apply user-defined route constraints to set the 'net_is_ignored_' and 'net_is_global_' flags. * diff --git a/vtr_flow/arch/VIB/vib_test_arch.xml b/vtr_flow/arch/VIB/vib_test_arch.xml new file mode 100644 index 00000000000..eb3ba461032 --- /dev/null +++ b/vtr_flow/arch/VIB/vib_test_arch.xml @@ -0,0 +1,13289 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_topL[7:0].outpad io_topL[7:0].inpad io_topL.clock + + + + + + + + + + + + + + + + + + + io_leftL[7:0].outpad io_leftL[7:0].inpad io_leftL.clock + + + + + + + + + + + + + + + + + + + io_rightL[7:0].outpad io_rightL[7:0].inpad io_rightL.clock + + + + + + + + + + + + + + + + + + + io_bottomL[7:0].outpad io_bottomL[7:0].inpad io_bottomL.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.Ia[5:0] clb.Ib[5:0] clb.Ic[5:0] clb.Id[5:0] clb.Ie[5:0] clb.If[5:0] clb.Ig[5:0] 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l1.S0 l3.S0 l6.S5 l6.S16 clb.o[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 clb.o[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 clb.o[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 clb.o[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 clb.o[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 clb.o[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 clb.q[0] + + + l1.E2 l3.E2 l6.E7 l6.E18 clb.q[1] + + + l1.S2 l3.S2 l6.S7 l6.S18 clb.q[2] + + + l1.W2 l3.W2 l6.W7 l6.W18 clb.q[3] + + + l1.N3 l3.N3 l6.N8 l6.N19 clb.q[4] + + + l1.E3 l3.E3 l6.E8 l6.E19 clb.q[5] + + + l1.S3 l3.S3 l6.S8 l6.S19 clb.q[6] + + + l1.W3 l3.W3 l6.W8 l6.W19 clb.q[7] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + clb.Ia[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + clb.Ib[0] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + clb.Ic[0] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + clb.Id[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + clb.Ie[0] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + clb.If[0] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + clb.Ig[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + clb.Ih[0] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + clb.Ia[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + clb.Ib[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + clb.Ic[1] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + clb.Id[1] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + clb.Ie[1] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + clb.If[1] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + clb.Ig[1] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + clb.Ih[1] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + clb.Ia[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + clb.Ib[2] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + clb.Ic[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + clb.Id[2] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + clb.Ie[2] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + clb.If[2] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + clb.Ig[2] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + clb.Ih[2] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + clb.Ia[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + clb.Ib[3] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + clb.Ic[3] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + clb.Id[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + clb.Ie[3] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + clb.If[3] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + clb.Ig[3] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + clb.Ih[3] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + clb.Ia[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + clb.Ib[4] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + clb.Ic[4] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + clb.Id[4] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + clb.Ie[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + clb.If[4] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + clb.Ig[4] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + clb.Ih[4] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + clb.Ia[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + clb.Ib[5] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + clb.Ic[5] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + clb.Id[5] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + clb.Ie[5] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + clb.If[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + clb.Ig[5] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + clb.Ih[5] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + io_left.inpad[0] io_left.inpad[0] io_left.inpad[1] io_left.inpad[1] io_left.inpad[2] io_left.inpad[2] io_left.inpad[3] io_left.inpad[3] + + + io_left.inpad[4] io_left.inpad[4] io_left.inpad[5] io_left.inpad[5] io_left.inpad[6] io_left.inpad[6] io_left.inpad[7] io_left.inpad[7] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_left.inpad[0] + + + io_left.inpad[1] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_left.inpad[2] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_left.inpad[3] + + + l1.N1 l6.N1 l6.N18 l8.N11 io_left.inpad[4] + + + io_left.inpad[5] + + + l1.S1 l6.S1 l6.S18 l8.S11 io_left.inpad[6] + + + l1.W1 l6.W1 l6.W18 l8.W11 io_left.inpad[7] + + + l1.N2 l6.N2 l6.N19 l8.N12 io_left.inpad[0] + + + io_left.inpad[1] + + + l1.S2 l6.S2 l6.S19 l8.S12 io_left.inpad[2] + + + l1.W2 l6.W2 l6.W19 l8.W12 io_left.inpad[3] + + + l1.N3 l6.N3 l6.N20 l8.N13 io_left.inpad[4] + + + io_left.inpad[5] + + + l1.S3 l6.S3 l6.S20 l8.S13 io_left.inpad[6] + + + l1.W3 l6.W3 l6.W20 l8.W13 io_left.inpad[7] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 io_left.inpad[0] + + + io_left.inpad[1] + + + l2.S3 l6.S8 l8.S1 l12.S2 io_left.inpad[2] + + + l2.W3 l6.W8 l8.W1 l12.W2 io_left.inpad[3] + + + l2.N4 l6.N9 l8.N2 l12.N3 io_left.inpad[4] + + + io_left.inpad[5] + + + l2.S4 l6.S9 l8.S2 l12.S3 io_left.inpad[6] + + + l2.W4 l6.W9 l8.W2 l12.W3 io_left.inpad[7] + + + l2.N5 l6.N10 l8.N3 l12.N4 io_left.inpad[0] + + + io_left.inpad[1] + + + l2.S5 l6.S10 l8.S3 l12.S4 io_left.inpad[2] + + + l2.W5 l6.W10 l8.W3 l12.W4 io_left.inpad[3] + + + l3.N0 l6.N11 l8.N4 l12.N5 io_left.inpad[4] + + + io_left.inpad[5] + + + l3.S0 l6.S11 l8.S4 l12.S5 io_left.inpad[6] + + + l3.W0 l6.W11 l8.W4 l12.W5 io_left.inpad[7] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 io_left.inpad[0] + + + io_left.inpad[1] + + + l3.S5 l6.S16 l8.S9 l12.S10 io_left.inpad[2] + + + l3.W5 l6.W16 l8.W9 l12.W10 io_left.inpad[3] + + + l1.N0 l3.N0 l6.N5 l6.N16 io_left.inpad[0] + + + io_left.inpad[1] + + + l1.S0 l3.S0 l6.S5 l6.S16 io_left.inpad[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 io_left.inpad[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 io_left.inpad[4] + + + io_left.inpad[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 io_left.inpad[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 io_left.inpad[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 io_left.inpad[0] + + + io_left.inpad[1] + + + l1.S2 l3.S2 l6.S7 l6.S18 io_left.inpad[2] + + + l1.W2 l3.W2 l6.W7 l6.W18 io_left.inpad[3] + + + l1.N3 l3.N3 l6.N8 l6.N19 io_left.inpad[4] + + + io_left.inpad[5] + + + l1.S3 l3.S3 l6.S8 l6.S19 io_left.inpad[6] + + + l1.W3 l3.W3 l6.W8 l6.W19 io_left.inpad[7] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + io_left.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + io_left.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + io_left.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + io_left.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + io_left.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + io_left.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + io_left.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + io_left.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + io_left.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + io_left.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + io_left.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + io_left.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + io_left.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + io_left.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + io_left.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + io_left.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + io_left.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + io_left.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + io_left.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + io_left.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + io_left.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + io_left.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + io_left.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + io_left.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + io_left.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_left.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + io_left.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + io_left.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_left.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + io_left.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + io_left.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + io_left.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + io_left.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + io_left.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + io_left.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + io_left.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + io_left.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + io_left.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + io_left.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + io_left.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + io_left.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + io_left.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + io_left.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + io_left.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + io_left.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + io_left.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + io_left.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + io_left.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + + + + + + + + + + + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + io_right.inpad[0] io_right.inpad[0] io_right.inpad[1] io_right.inpad[1] io_right.inpad[2] io_right.inpad[2] io_right.inpad[3] io_right.inpad[3] + + + io_right.inpad[4] io_right.inpad[4] io_right.inpad[5] io_right.inpad[5] io_right.inpad[6] io_right.inpad[6] io_right.inpad[7] io_right.inpad[7] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_right.inpad[0] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_right.inpad[1] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_right.inpad[2] + + + io_right.inpad[3] + + + l1.N1 l6.N1 l6.N18 l8.N11 io_right.inpad[4] + + + l1.E1 l6.E1 l6.E18 l8.E11 io_right.inpad[5] + + + l1.S1 l6.S1 l6.S18 l8.S11 io_right.inpad[6] + + + io_right.inpad[7] + + + l1.N2 l6.N2 l6.N19 l8.N12 io_right.inpad[0] + + + l1.E2 l6.E2 l6.E19 l8.E12 io_right.inpad[1] + + + l1.S2 l6.S2 l6.S19 l8.S12 io_right.inpad[2] + + + io_right.inpad[3] + + + l1.N3 l6.N3 l6.N20 l8.N13 io_right.inpad[4] + + + l1.E3 l6.E3 l6.E20 l8.E13 io_right.inpad[5] + + + l1.S3 l6.S3 l6.S20 l8.S13 io_right.inpad[6] + + + io_right.inpad[7] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 io_right.inpad[0] + + + l2.E3 l6.E8 l8.E1 l12.E2 io_right.inpad[1] + + + l2.S3 l6.S8 l8.S1 l12.S2 io_right.inpad[2] + + + io_right.inpad[3] + + + l2.N4 l6.N9 l8.N2 l12.N3 io_right.inpad[4] + + + l2.E4 l6.E9 l8.E2 l12.E3 io_right.inpad[5] + + + l2.S4 l6.S9 l8.S2 l12.S3 io_right.inpad[6] + + + io_right.inpad[7] + + + l2.N5 l6.N10 l8.N3 l12.N4 io_right.inpad[0] + + + l2.E5 l6.E10 l8.E3 l12.E4 io_right.inpad[1] + + + l2.S5 l6.S10 l8.S3 l12.S4 io_right.inpad[2] + + + io_right.inpad[3] + + + l3.N0 l6.N11 l8.N4 l12.N5 io_right.inpad[4] + + + l3.E0 l6.E11 l8.E4 l12.E5 io_right.inpad[5] + + + l3.S0 l6.S11 l8.S4 l12.S5 io_right.inpad[6] + + + io_right.inpad[7] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 io_right.inpad[0] + + + l3.E5 l6.E16 l8.E9 l12.E10 io_right.inpad[1] + + + l3.S5 l6.S16 l8.S9 l12.S10 io_right.inpad[2] + + + io_right.inpad[3] + + + l1.N0 l3.N0 l6.N5 l6.N16 io_right.inpad[0] + + + l1.E0 l3.E0 l6.E5 l6.E16 io_right.inpad[1] + + + l1.S0 l3.S0 l6.S5 l6.S16 io_right.inpad[2] + + + io_right.inpad[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 io_right.inpad[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 io_right.inpad[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 io_right.inpad[6] + + + io_right.inpad[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 io_right.inpad[0] + + + l1.E2 l3.E2 l6.E7 l6.E18 io_right.inpad[1] + + + l1.S2 l3.S2 l6.S7 l6.S18 io_right.inpad[2] + + + io_right.inpad[3] + + + l1.N3 l3.N3 l6.N8 l6.N19 io_right.inpad[4] + + + l1.E3 l3.E3 l6.E8 l6.E19 io_right.inpad[5] + + + l1.S3 l3.S3 l6.S8 l6.S19 io_right.inpad[6] + + + io_right.inpad[7] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + omux-3 + + + + + io_right.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + io_right.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + io_right.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + io_right.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + io_right.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + io_right.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + io_right.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + io_right.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + io_right.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + io_right.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + io_right.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + io_right.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + io_right.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + io_right.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + io_right.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + io_right.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + io_right.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + io_right.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + io_right.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + io_right.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + io_right.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + io_right.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + io_right.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + io_right.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + io_right.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_right.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + io_right.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + io_right.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_right.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + io_right.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + io_right.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + io_right.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + io_right.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + io_right.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + io_right.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + io_right.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + io_right.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + io_right.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + io_right.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + io_right.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + io_right.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + io_right.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + io_right.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + io_right.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + io_right.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + io_right.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + io_right.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + io_right.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + io_top.inpad[0] io_top.inpad[0] io_top.inpad[1] io_top.inpad[1] io_top.inpad[2] io_top.inpad[2] io_top.inpad[3] io_top.inpad[3] + + + io_top.inpad[4] io_top.inpad[4] io_top.inpad[5] io_top.inpad[5] io_top.inpad[6] io_top.inpad[6] io_top.inpad[7] io_top.inpad[7] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 io_top.inpad[0] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_top.inpad[1] + + + io_top.inpad[2] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_top.inpad[3] + + + l1.N1 l6.N1 l6.N18 l8.N11 io_top.inpad[4] + + + l1.E1 l6.E1 l6.E18 l8.E11 io_top.inpad[5] + + + io_top.inpad[6] + + + l1.W1 l6.W1 l6.W18 l8.W11 io_top.inpad[7] + + + l1.N2 l6.N2 l6.N19 l8.N12 io_top.inpad[0] + + + l1.E2 l6.E2 l6.E19 l8.E12 io_top.inpad[1] + + + io_top.inpad[2] + + + l1.W2 l6.W2 l6.W19 l8.W12 io_top.inpad[3] + + + l1.N3 l6.N3 l6.N20 l8.N13 io_top.inpad[4] + + + l1.E3 l6.E3 l6.E20 l8.E13 io_top.inpad[5] + + + io_top.inpad[6] + + + l1.W3 l6.W3 l6.W20 l8.W13 io_top.inpad[7] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 io_top.inpad[0] + + + l2.E3 l6.E8 l8.E1 l12.E2 io_top.inpad[1] + + + io_top.inpad[2] + + + l2.W3 l6.W8 l8.W1 l12.W2 io_top.inpad[3] + + + l2.N4 l6.N9 l8.N2 l12.N3 io_top.inpad[4] + + + l2.E4 l6.E9 l8.E2 l12.E3 io_top.inpad[5] + + + io_top.inpad[6] + + + l2.W4 l6.W9 l8.W2 l12.W3 io_top.inpad[7] + + + l2.N5 l6.N10 l8.N3 l12.N4 io_top.inpad[0] + + + l2.E5 l6.E10 l8.E3 l12.E4 io_top.inpad[1] + + + io_top.inpad[2] + + + l2.W5 l6.W10 l8.W3 l12.W4 io_top.inpad[3] + + + l3.N0 l6.N11 l8.N4 l12.N5 io_top.inpad[4] + + + l3.E0 l6.E11 l8.E4 l12.E5 io_top.inpad[5] + + + io_top.inpad[6] + + + l3.W0 l6.W11 l8.W4 l12.W5 io_top.inpad[7] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 io_top.inpad[0] + + + l3.E5 l6.E16 l8.E9 l12.E10 io_top.inpad[1] + + + io_top.inpad[2] + + + l3.W5 l6.W16 l8.W9 l12.W10 io_top.inpad[3] + + + l1.N0 l3.N0 l6.N5 l6.N16 io_top.inpad[0] + + + l1.E0 l3.E0 l6.E5 l6.E16 io_top.inpad[1] + + + io_top.inpad[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 io_top.inpad[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 io_top.inpad[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 io_top.inpad[5] + + + io_top.inpad[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 io_top.inpad[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 io_top.inpad[0] + + + l1.E2 l3.E2 l6.E7 l6.E18 io_top.inpad[1] + + + io_top.inpad[2] + + + l1.W2 l3.W2 l6.W7 l6.W18 io_top.inpad[3] + + + l1.N3 l3.N3 l6.N8 l6.N19 io_top.inpad[4] + + + l1.E3 l3.E3 l6.E8 l6.E19 io_top.inpad[5] + + + io_top.inpad[6] + + + l1.W3 l3.W3 l6.W8 l6.W19 io_top.inpad[7] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + io_top.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + io_top.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + io_top.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + io_top.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + io_top.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + io_top.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + io_top.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + io_top.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + io_top.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + io_top.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + io_top.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + io_top.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + io_top.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + io_top.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + io_top.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + io_top.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + io_top.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + io_top.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + io_top.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + io_top.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + io_top.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + io_top.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + io_top.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + io_top.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + io_top.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_top.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + io_top.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + io_top.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_top.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + io_top.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + io_top.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + io_top.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + io_top.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + io_top.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + io_top.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + io_top.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + io_top.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + io_top.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + io_top.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + io_top.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + io_top.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + io_top.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + io_top.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + io_top.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + io_top.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + io_top.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + io_top.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + io_top.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] io_bottom.inpad[0] io_bottom.inpad[1] io_bottom.inpad[1] io_bottom.inpad[2] io_bottom.inpad[2] io_bottom.inpad[3] io_bottom.inpad[3] + + + io_bottom.inpad[4] io_bottom.inpad[4] io_bottom.inpad[5] io_bottom.inpad[5] io_bottom.inpad[6] io_bottom.inpad[6] io_bottom.inpad[7] io_bottom.inpad[7] + + + io_bottom.inpad[0] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 io_bottom.inpad[1] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 io_bottom.inpad[2] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l1.E1 l6.E1 l6.E18 l8.E11 io_bottom.inpad[5] + + + l1.S1 l6.S1 l6.S18 l8.S11 io_bottom.inpad[6] + + + l1.W1 l6.W1 l6.W18 l8.W11 io_bottom.inpad[7] + + + io_bottom.inpad[0] + + + l1.E2 l6.E2 l6.E19 l8.E12 io_bottom.inpad[1] + + + l1.S2 l6.S2 l6.S19 l8.S12 io_bottom.inpad[2] + + + l1.W2 l6.W2 l6.W19 l8.W12 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l1.E3 l6.E3 l6.E20 l8.E13 io_bottom.inpad[5] + + + l1.S3 l6.S3 l6.S20 l8.S13 io_bottom.inpad[6] + + + l1.W3 l6.W3 l6.W20 l8.W13 io_bottom.inpad[7] + + + omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + io_bottom.inpad[0] + + + l2.E3 l6.E8 l8.E1 l12.E2 io_bottom.inpad[1] + + + l2.S3 l6.S8 l8.S1 l12.S2 io_bottom.inpad[2] + + + l2.W3 l6.W8 l8.W1 l12.W2 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l2.E4 l6.E9 l8.E2 l12.E3 io_bottom.inpad[5] + + + l2.S4 l6.S9 l8.S2 l12.S3 io_bottom.inpad[6] + + + l2.W4 l6.W9 l8.W2 l12.W3 io_bottom.inpad[7] + + + io_bottom.inpad[0] + + + l2.E5 l6.E10 l8.E3 l12.E4 io_bottom.inpad[1] + + + l2.S5 l6.S10 l8.S3 l12.S4 io_bottom.inpad[2] + + + l2.W5 l6.W10 l8.W3 l12.W4 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l3.E0 l6.E11 l8.E4 l12.E5 io_bottom.inpad[5] + + + l3.S0 l6.S11 l8.S4 l12.S5 io_bottom.inpad[6] + + + l3.W0 l6.W11 l8.W4 l12.W5 io_bottom.inpad[7] + + + omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + io_bottom.inpad[0] + + + l3.E5 l6.E16 l8.E9 l12.E10 io_bottom.inpad[1] + + + l3.S5 l6.S16 l8.S9 l12.S10 io_bottom.inpad[2] + + + l3.W5 l6.W16 l8.W9 l12.W10 io_bottom.inpad[3] + + + io_bottom.inpad[0] + + + l1.E0 l3.E0 l6.E5 l6.E16 io_bottom.inpad[1] + + + l1.S0 l3.S0 l6.S5 l6.S16 io_bottom.inpad[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 io_bottom.inpad[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 io_bottom.inpad[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 io_bottom.inpad[7] + + + io_bottom.inpad[0] + + + l1.E2 l3.E2 l6.E7 l6.E18 io_bottom.inpad[1] + + + l1.S2 l3.S2 l6.S7 l6.S18 io_bottom.inpad[2] + + + l1.W2 l3.W2 l6.W7 l6.W18 io_bottom.inpad[3] + + + io_bottom.inpad[4] + + + l1.E3 l3.E3 l6.E8 l6.E19 io_bottom.inpad[5] + + + l1.S3 l3.S3 l6.S8 l6.S19 io_bottom.inpad[6] + + + l1.W3 l3.W3 l6.W8 l6.W19 io_bottom.inpad[7] + + + omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + io_bottom.outpad[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + io_bottom.outpad[1] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + io_bottom.outpad[2] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + io_bottom.outpad[3] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + io_bottom.outpad[4] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + io_bottom.outpad[5] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + io_bottom.outpad[6] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + io_bottom.outpad[7] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + io_bottom.outpad[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + io_bottom.outpad[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + io_bottom.outpad[2] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + io_bottom.outpad[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + io_bottom.outpad[4] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + io_bottom.outpad[5] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + io_bottom.outpad[6] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + io_bottom.outpad[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + io_bottom.outpad[0] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + io_bottom.outpad[1] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + io_bottom.outpad[2] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + io_bottom.outpad[3] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + io_bottom.outpad[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + io_bottom.outpad[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + io_bottom.outpad[6] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + io_bottom.outpad[7] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + io_bottom.outpad[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + io_bottom.outpad[1] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + io_bottom.outpad[2] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + io_bottom.outpad[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + io_bottom.outpad[4] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + io_bottom.outpad[5] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + io_bottom.outpad[6] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + io_bottom.outpad[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + io_bottom.outpad[0] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + io_bottom.outpad[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + io_bottom.outpad[2] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + io_bottom.outpad[3] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + io_bottom.outpad[4] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + io_bottom.outpad[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + io_bottom.outpad[6] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + io_bottom.outpad[7] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + io_bottom.outpad[0] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + io_bottom.outpad[1] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + io_bottom.outpad[2] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + io_bottom.outpad[3] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + io_bottom.outpad[4] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + io_bottom.outpad[5] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + io_bottom.outpad[6] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + io_bottom.outpad[7] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 + + + l1.N1 l6.N1 l6.N18 l8.N11 + + + l1.E1 l6.E1 l6.E18 l8.E11 + + + l1.S1 l6.S1 l6.S18 l8.S11 + + + l1.W1 l6.W1 l6.W18 l8.W11 + + + l1.N2 l6.N2 l6.N19 l8.N12 + + + l1.E2 l6.E2 l6.E19 l8.E12 + + + l1.S2 l6.S2 l6.S19 l8.S12 + + + l1.W2 l6.W2 l6.W19 l8.W12 + + + l1.N3 l6.N3 l6.N20 l8.N13 + + + l1.E3 l6.E3 l6.E20 l8.E13 + + + l1.S3 l6.S3 l6.S20 l8.S13 + + + l1.W3 l6.W3 l6.W20 l8.W13 + + + l1.N4 l6.N4 l6.N21 l8.N14 + + + l1.E4 l6.E4 l6.E21 l8.E14 + + + l1.S4 l6.S4 l6.S21 l8.S14 + + + l1.W4 l6.W4 l6.W21 l8.W14 + + + l2.N0 l6.N5 l6.N22 l8.N15 + + + l2.E0 l6.E5 l6.E22 l8.E15 + + + l2.S0 l6.S5 l6.S22 l8.S15 + + + l2.W0 l6.W5 l6.W22 l8.W15 + + + l2.N1 l6.N6 l6.N23 l12.N0 + + + l2.E1 l6.E6 l6.E23 l12.E0 + + + l2.S1 l6.S6 l6.S23 l12.S0 + + + l2.W1 l6.W6 l6.W23 l12.W0 + + + l2.N2 l6.N7 l8.N0 l12.N1 + + + l2.E2 l6.E7 l8.E0 l12.E1 + + + l2.S2 l6.S7 l8.S0 l12.S1 + + + l2.W2 l6.W7 l8.W0 l12.W1 + + + l2.N3 l6.N8 l8.N1 l12.N2 + + + l2.E3 l6.E8 l8.E1 l12.E2 + + + l2.S3 l6.S8 l8.S1 l12.S2 + + + l2.W3 l6.W8 l8.W1 l12.W2 + + + l2.N4 l6.N9 l8.N2 l12.N3 + + + l2.E4 l6.E9 l8.E2 l12.E3 + + + l2.S4 l6.S9 l8.S2 l12.S3 + + + l2.W4 l6.W9 l8.W2 l12.W3 + + + l2.N5 l6.N10 l8.N3 l12.N4 + + + l2.E5 l6.E10 l8.E3 l12.E4 + + + l2.S5 l6.S10 l8.S3 l12.S4 + + + l2.W5 l6.W10 l8.W3 l12.W4 + + + l3.N0 l6.N11 l8.N4 l12.N5 + + + l3.E0 l6.E11 l8.E4 l12.E5 + + + l3.S0 l6.S11 l8.S4 l12.S5 + + + l3.W0 l6.W11 l8.W4 l12.W5 + + + l3.N1 l6.N12 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mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] + + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] + + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] + + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] + + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] mult_36.out[61] mult_36.out[69] + + + mult_36.out[54] mult_36.out[70] mult_36.out[62] mult_36.out[55] mult_36.out[71] mult_36.out[63] mult_36.out[56] mult_36.out[64] mult_36.out[57] mult_36.out[65] + + + mult_36.out[58] mult_36.out[66] mult_36.out[59] mult_36.out[67] mult_36.out[60] mult_36.out[68] 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l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[54] mult_36.out[70] + + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[55] mult_36.out[71] + + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[56] + + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[57] + + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[58] + + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[59] + + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[60] + + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[61] + + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[62] + + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[63] + + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[64] + + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[65] + + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[66] + + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[67] + + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[68] + + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[69] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[54] mult_36.out[70] + + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[55] mult_36.out[71] + + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[56] + + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[57] + + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[54] mult_36.out[70] + + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[55] mult_36.out[71] + + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[56] + + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[57] + + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[58] + + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[59] + + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[60] + + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[61] + + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[62] + + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[63] + + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[64] + + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[65] + + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[66] + + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[67] + + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[68] + + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[69] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + mult_36.a[27] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + mult_36.a[33] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + mult_36.b[30] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + mult_36.a[27] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + mult_36.a[33] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + mult_36.b[30] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + mult_36.a[27] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + mult_36.a[33] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + mult_36.a[28] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + mult_36.a[34] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + mult_36.b[31] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + mult_36.a[28] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + mult_36.a[34] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + mult_36.b[31] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + mult_36.a[28] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + mult_36.a[34] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + mult_36.a[29] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + mult_36.a[35] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + mult_36.b[32] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + mult_36.a[29] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + mult_36.a[35] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + mult_36.b[32] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + mult_36.a[29] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + mult_36.a[35] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + mult_36.a[30] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + mult_36.b[27] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + mult_36.b[33] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + mult_36.a[30] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + mult_36.b[27] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + mult_36.b[33] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + mult_36.a[30] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + mult_36.b[27] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + mult_36.a[31] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + mult_36.b[28] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + mult_36.b[34] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + mult_36.a[31] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + mult_36.b[28] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + mult_36.b[34] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + mult_36.a[31] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + mult_36.b[28] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + mult_36.a[32] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + mult_36.b[29] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + mult_36.b[35] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + mult_36.a[32] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + mult_36.b[29] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + mult_36.b[35] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + mult_36.a[32] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + mult_36.b[29] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + mult_36.out[36] mult_36.out[52] mult_36.out[44] mult_36.out[37] mult_36.out[53] mult_36.out[45] mult_36.out[38] mult_36.out[46] mult_36.out[39] mult_36.out[47] + + + mult_36.out[40] mult_36.out[48] mult_36.out[41] mult_36.out[49] mult_36.out[42] mult_36.out[50] mult_36.out[43] mult_36.out[51] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[36] mult_36.out[52] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[37] mult_36.out[53] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[38] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[39] + + + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[40] + + + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[41] + + + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[42] + + + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[43] + + + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[44] + + + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[45] + + + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[46] + + + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[47] + + + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[48] + + + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[49] + + + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[50] + + + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[51] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[36] mult_36.out[52] + + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[37] mult_36.out[53] + + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[38] + + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[39] + + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[40] + + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[41] + + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[42] + + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[43] + + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[44] + + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[45] + + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[46] + + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[47] + + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[48] + + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[49] + + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[50] + + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[51] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[36] mult_36.out[52] + + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[37] mult_36.out[53] + + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[38] + + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[39] + + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[36] mult_36.out[52] + + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[37] mult_36.out[53] + + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[38] + + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[39] + + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[40] + + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[41] + + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[42] + + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[43] + + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[44] + + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[45] + + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[46] + + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[47] + + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[48] + + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[49] + + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[50] + + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[51] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + mult_36.a[18] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + mult_36.a[24] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + mult_36.b[21] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + mult_36.a[18] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + mult_36.a[24] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + mult_36.b[21] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + mult_36.a[18] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + mult_36.a[24] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + mult_36.a[19] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + mult_36.a[25] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + mult_36.b[22] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + mult_36.a[19] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + mult_36.a[25] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + mult_36.b[22] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + mult_36.a[19] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + mult_36.a[25] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + mult_36.a[20] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + mult_36.a[26] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + mult_36.b[23] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + mult_36.a[20] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + mult_36.a[26] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + mult_36.b[23] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + mult_36.a[20] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + mult_36.a[26] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + mult_36.a[21] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + mult_36.b[18] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + mult_36.b[24] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + mult_36.a[21] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + mult_36.b[18] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + mult_36.b[24] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + mult_36.a[21] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + mult_36.b[18] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + mult_36.a[22] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + mult_36.b[19] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + mult_36.b[25] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + mult_36.a[22] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + mult_36.b[19] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + mult_36.b[25] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + mult_36.a[22] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + mult_36.b[19] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + mult_36.a[23] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + mult_36.b[20] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + mult_36.b[26] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + mult_36.a[23] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + mult_36.b[20] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + mult_36.b[26] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + mult_36.a[23] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + mult_36.b[20] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + mult_36.out[18] mult_36.out[34] mult_36.out[26] mult_36.out[19] mult_36.out[35] mult_36.out[27] mult_36.out[20] mult_36.out[28] mult_36.out[21] mult_36.out[29] + + + mult_36.out[22] mult_36.out[30] mult_36.out[23] mult_36.out[31] mult_36.out[24] mult_36.out[32] mult_36.out[25] mult_36.out[33] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[18] mult_36.out[34] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[19] mult_36.out[35] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[20] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[21] + + + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[22] + + + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[23] + + + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[24] + + + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[25] + + + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[26] + + + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[27] + + + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[28] + + + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[29] + + + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[30] + + + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[31] + + + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[32] + + + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[33] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[18] mult_36.out[34] + + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[19] mult_36.out[35] + + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[20] + + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[21] + + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[22] + + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[23] + + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[24] + + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[25] + + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[26] + + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[27] + + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[28] + + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[29] + + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[30] + + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[31] + + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[32] + + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[33] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[18] mult_36.out[34] + + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[19] mult_36.out[35] + + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[20] + + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[21] + + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[18] mult_36.out[34] + + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[19] mult_36.out[35] + + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[20] + + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[21] + + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[22] + + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[23] + + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[24] + + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[25] + + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[26] + + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[27] + + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[28] + + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[29] + + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[30] + + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[31] + + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[32] + + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[33] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + mult_36.a[9] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + mult_36.a[15] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + mult_36.b[12] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + mult_36.a[9] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + mult_36.a[15] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + mult_36.b[12] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + mult_36.a[9] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + mult_36.a[15] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + mult_36.a[10] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + mult_36.a[16] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + mult_36.b[13] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + mult_36.a[10] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + mult_36.a[16] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + mult_36.b[13] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + mult_36.a[10] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + mult_36.a[16] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + mult_36.a[11] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + mult_36.a[17] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + mult_36.b[14] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + mult_36.a[11] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + mult_36.a[17] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + mult_36.b[14] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + mult_36.a[11] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + mult_36.a[17] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + mult_36.a[12] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + mult_36.b[9] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + mult_36.b[15] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + mult_36.a[12] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + mult_36.b[9] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + mult_36.b[15] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + mult_36.a[12] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + mult_36.b[9] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + mult_36.a[13] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + mult_36.b[10] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + mult_36.b[16] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + mult_36.a[13] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + mult_36.b[10] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + mult_36.b[16] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + mult_36.a[13] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + mult_36.b[10] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + mult_36.a[14] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + mult_36.b[11] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + mult_36.b[17] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + mult_36.a[14] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + mult_36.b[11] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + mult_36.b[17] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + mult_36.a[14] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + mult_36.b[11] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + mult_36.out[0] mult_36.out[16] mult_36.out[8] mult_36.out[1] mult_36.out[17] mult_36.out[9] mult_36.out[2] mult_36.out[10] mult_36.out[3] mult_36.out[11] + + + mult_36.out[4] mult_36.out[12] mult_36.out[5] mult_36.out[13] mult_36.out[6] mult_36.out[14] mult_36.out[7] mult_36.out[15] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 mult_36.out[0] mult_36.out[16] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 mult_36.out[1] mult_36.out[17] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 mult_36.out[2] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 mult_36.out[3] + + + l1.N1 l6.N1 l6.N18 l8.N11 mult_36.out[4] + + + l1.E1 l6.E1 l6.E18 l8.E11 mult_36.out[5] + + + l1.S1 l6.S1 l6.S18 l8.S11 mult_36.out[6] + + + l1.W1 l6.W1 l6.W18 l8.W11 mult_36.out[7] + + + l1.N2 l6.N2 l6.N19 l8.N12 mult_36.out[8] + + + l1.E2 l6.E2 l6.E19 l8.E12 mult_36.out[9] + + + l1.S2 l6.S2 l6.S19 l8.S12 mult_36.out[10] + + + l1.W2 l6.W2 l6.W19 l8.W12 mult_36.out[11] + + + l1.N3 l6.N3 l6.N20 l8.N13 mult_36.out[12] + + + l1.E3 l6.E3 l6.E20 l8.E13 mult_36.out[13] + + + l1.S3 l6.S3 l6.S20 l8.S13 mult_36.out[14] + + + l1.W3 l6.W3 l6.W20 l8.W13 mult_36.out[15] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 mult_36.out[0] mult_36.out[16] + + + l2.E3 l6.E8 l8.E1 l12.E2 mult_36.out[1] mult_36.out[17] + + + l2.S3 l6.S8 l8.S1 l12.S2 mult_36.out[2] + + + l2.W3 l6.W8 l8.W1 l12.W2 mult_36.out[3] + + + l2.N4 l6.N9 l8.N2 l12.N3 mult_36.out[4] + + + l2.E4 l6.E9 l8.E2 l12.E3 mult_36.out[5] + + + l2.S4 l6.S9 l8.S2 l12.S3 mult_36.out[6] + + + l2.W4 l6.W9 l8.W2 l12.W3 mult_36.out[7] + + + l2.N5 l6.N10 l8.N3 l12.N4 mult_36.out[8] + + + l2.E5 l6.E10 l8.E3 l12.E4 mult_36.out[9] + + + l2.S5 l6.S10 l8.S3 l12.S4 mult_36.out[10] + + + l2.W5 l6.W10 l8.W3 l12.W4 mult_36.out[11] + + + l3.N0 l6.N11 l8.N4 l12.N5 mult_36.out[12] + + + l3.E0 l6.E11 l8.E4 l12.E5 mult_36.out[13] + + + l3.S0 l6.S11 l8.S4 l12.S5 mult_36.out[14] + + + l3.W0 l6.W11 l8.W4 l12.W5 mult_36.out[15] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 mult_36.out[0] mult_36.out[16] + + + l3.E5 l6.E16 l8.E9 l12.E10 mult_36.out[1] mult_36.out[17] + + + l3.S5 l6.S16 l8.S9 l12.S10 mult_36.out[2] + + + l3.W5 l6.W16 l8.W9 l12.W10 mult_36.out[3] + + + l1.N0 l3.N0 l6.N5 l6.N16 mult_36.out[0] mult_36.out[16] + + + l1.E0 l3.E0 l6.E5 l6.E16 mult_36.out[1] mult_36.out[17] + + + l1.S0 l3.S0 l6.S5 l6.S16 mult_36.out[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 mult_36.out[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 mult_36.out[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 mult_36.out[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 mult_36.out[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 mult_36.out[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 mult_36.out[8] + + + l1.E2 l3.E2 l6.E7 l6.E18 mult_36.out[9] + + + l1.S2 l3.S2 l6.S7 l6.S18 mult_36.out[10] + + + l1.W2 l3.W2 l6.W7 l6.W18 mult_36.out[11] + + + l1.N3 l3.N3 l6.N8 l6.N19 mult_36.out[12] + + + l1.E3 l3.E3 l6.E8 l6.E19 mult_36.out[13] + + + l1.S3 l3.S3 l6.S8 l6.S19 mult_36.out[14] + + + l1.W3 l3.W3 l6.W8 l6.W19 mult_36.out[15] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + mult_36.a[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + mult_36.a[6] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + mult_36.b[3] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + mult_36.a[0] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + mult_36.a[6] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + mult_36.b[3] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + mult_36.a[0] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + mult_36.a[6] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + mult_36.a[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + mult_36.a[7] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + mult_36.b[4] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + mult_36.a[1] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + mult_36.a[7] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + mult_36.b[4] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + mult_36.a[1] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + mult_36.a[7] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + mult_36.a[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + mult_36.a[8] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + mult_36.b[5] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + mult_36.a[2] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + mult_36.a[8] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + mult_36.b[5] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + mult_36.a[2] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + mult_36.a[8] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + mult_36.a[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + mult_36.b[0] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + mult_36.b[6] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + mult_36.a[3] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + mult_36.b[0] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + mult_36.b[6] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + mult_36.a[3] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + mult_36.b[0] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + mult_36.a[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + mult_36.b[1] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + mult_36.b[7] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + mult_36.a[4] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + mult_36.b[1] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + mult_36.b[7] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + mult_36.a[4] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + mult_36.b[1] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + mult_36.a[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + mult_36.b[2] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + mult_36.b[8] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + mult_36.a[5] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + mult_36.b[2] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + mult_36.b[8] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + mult_36.a[5] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + mult_36.b[2] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + memory.out[54] memory.out[62] memory.out[55] memory.out[63] memory.out[56] memory.out[54] memory.out[57] memory.out[55] + + + memory.out[58] memory.out[56] memory.out[59] memory.out[57] memory.out[60] memory.out[58] memory.out[61] memory.out[59] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[54] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[55] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[56] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[57] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[58] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[59] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[60] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[61] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[62] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[63] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[54] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[55] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[56] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[57] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[58] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[59] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[54] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[55] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[56] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[57] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[58] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[59] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[60] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[61] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[62] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[63] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[54] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[55] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[56] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[57] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[58] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[59] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[54] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[55] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[56] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[57] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[54] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[55] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[56] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[57] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[58] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[59] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[60] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[61] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[62] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[63] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[54] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[55] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[56] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[57] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[58] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[59] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.we1[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[54] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[60] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.data[50] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[56] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[62] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.data[52] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[58] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.we2[0] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[55] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[61] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.data[51] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[57] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[63] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.data[53] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[59] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.data[50] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[56] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[62] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.data[52] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[58] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.we1[0] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[54] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[60] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.data[51] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[57] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[63] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.data[53] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[59] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.we2[0] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[55] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[61] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.data[52] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[58] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.we1[0] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[54] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[60] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.data[50] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[56] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[62] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.data[53] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[59] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.we2[0] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[55] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[61] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.data[51] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[57] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[63] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + memory.out[44] memory.out[52] memory.out[45] memory.out[53] memory.out[46] memory.out[44] memory.out[47] memory.out[45] + + + memory.out[48] memory.out[46] memory.out[49] memory.out[47] memory.out[50] memory.out[48] memory.out[51] memory.out[49] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[44] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[45] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[46] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[47] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[48] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[49] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[50] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[51] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[52] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[53] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[44] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[45] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[46] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[47] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[48] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[49] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[44] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[45] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[46] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[47] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[48] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[49] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[50] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[51] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[52] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[53] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[44] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[45] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[46] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[47] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[48] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[49] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[44] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[45] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[46] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[47] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[44] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[45] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[46] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[47] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[48] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[49] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[50] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[51] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[52] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[53] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[44] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[45] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[46] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[47] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[48] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[49] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.addr1[12] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[40] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[46] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[14] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[42] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[48] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[13] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[44] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[13] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[41] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[47] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[12] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[43] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[49] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[14] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[45] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[14] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[42] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[48] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[13] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[44] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[12] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[40] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[46] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[12] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[43] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[49] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[14] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[45] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[13] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[41] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[47] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[13] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[44] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[12] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[40] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[46] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[14] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[42] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[48] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[14] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[45] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[13] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[41] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[47] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[12] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[43] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[49] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + memory.out[33] memory.out[41] memory.out[34] memory.out[42] memory.out[35] memory.out[43] memory.out[36] memory.out[33] + + + memory.out[37] memory.out[34] memory.out[38] memory.out[35] memory.out[39] memory.out[36] memory.out[40] memory.out[37] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[33] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[34] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[35] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[36] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[37] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[38] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[39] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[40] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[41] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[42] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[43] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[33] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[34] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[35] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[36] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[37] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[33] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[34] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[35] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[36] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[37] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[38] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[39] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[40] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[41] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[42] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[43] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[33] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[34] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[35] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[36] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[37] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[33] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[34] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[35] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[36] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[33] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[34] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[35] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[36] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[37] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[38] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[39] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[40] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[41] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[42] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[43] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[33] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[34] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[35] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[36] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[37] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.addr1[9] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[30] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[36] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[11] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[32] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[38] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[10] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[34] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[10] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[31] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[37] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[9] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[33] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[39] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[11] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[35] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[11] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[32] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[38] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[10] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[34] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[9] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[30] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[36] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[9] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[33] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[39] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[11] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[35] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[10] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[31] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[37] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[10] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[34] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[9] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[30] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[36] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[11] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[32] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[38] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[11] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[35] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[10] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[31] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[37] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[9] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[33] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[39] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + memory.out[22] memory.out[30] memory.out[23] memory.out[31] memory.out[24] memory.out[32] memory.out[25] memory.out[22] + + + memory.out[26] memory.out[23] memory.out[27] memory.out[24] memory.out[28] memory.out[25] memory.out[29] memory.out[26] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[22] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[23] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[24] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[25] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[26] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[27] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[28] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[29] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[30] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[31] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[32] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[22] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[23] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[24] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[25] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[26] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[22] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[23] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[24] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[25] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[26] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[27] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[28] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[29] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[30] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[31] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[32] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[22] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[23] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[24] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[25] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[26] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[22] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[23] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[24] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[25] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[22] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[23] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[24] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[25] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[26] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[27] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[28] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[29] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[30] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[31] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[32] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[22] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[23] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[24] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[25] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[26] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.addr1[6] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[20] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[26] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[8] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[22] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[28] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[7] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[24] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[7] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[21] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[27] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[6] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[23] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[29] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[8] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[25] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[8] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[22] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[28] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[7] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[24] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[6] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[20] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[26] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[6] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[23] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[29] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[8] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[25] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[7] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[21] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[27] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[7] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[24] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[6] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[20] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[26] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[8] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[22] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[28] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[8] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[25] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[7] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[21] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[27] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[6] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[23] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[29] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + memory.out[11] memory.out[19] memory.out[12] memory.out[20] memory.out[13] memory.out[21] memory.out[14] memory.out[11] + + + memory.out[15] memory.out[12] memory.out[16] memory.out[13] memory.out[17] memory.out[14] memory.out[18] memory.out[15] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[11] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[12] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[13] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[14] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[15] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[16] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[17] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[18] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[19] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[20] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[21] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[11] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[12] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[13] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[14] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[15] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[11] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[12] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[13] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[14] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[15] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[16] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[17] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[18] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[19] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[20] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[21] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[11] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[12] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[13] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[14] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[15] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[11] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[12] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[13] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[14] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[11] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[12] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[13] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[14] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[15] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[16] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[17] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[18] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[19] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[20] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[21] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[11] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[12] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[13] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[14] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[15] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.addr1[3] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[10] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[16] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[5] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[12] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[18] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[4] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[14] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[4] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[11] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[17] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[3] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[13] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[19] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[5] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[15] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[5] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[12] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[18] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[4] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[14] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[3] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[10] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[16] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[3] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[13] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[19] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[5] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[15] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[4] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[11] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[17] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[4] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[14] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[3] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[10] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[16] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[5] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[12] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[18] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[5] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[15] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[4] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[11] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[17] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[3] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[13] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[19] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + memory.out[0] memory.out[8] memory.out[1] memory.out[9] memory.out[2] memory.out[10] memory.out[3] memory.out[0] + + + memory.out[4] memory.out[1] memory.out[5] memory.out[2] memory.out[6] memory.out[3] memory.out[7] memory.out[4] + + + l1.N0 l6.N0 l6.N17 l8.N10 l12.N11 memory.out[0] + + + l1.E0 l6.E0 l6.E17 l8.E10 l12.E11 memory.out[1] + + + l1.S0 l6.S0 l6.S17 l8.S10 l12.S11 memory.out[2] + + + l1.W0 l6.W0 l6.W17 l8.W10 l12.W11 memory.out[3] + + + l1.N1 l6.N1 l6.N18 l8.N11 memory.out[4] + + + l1.E1 l6.E1 l6.E18 l8.E11 memory.out[5] + + + l1.S1 l6.S1 l6.S18 l8.S11 memory.out[6] + + + l1.W1 l6.W1 l6.W18 l8.W11 memory.out[7] + + + l1.N2 l6.N2 l6.N19 l8.N12 memory.out[8] + + + l1.E2 l6.E2 l6.E19 l8.E12 memory.out[9] + + + l1.S2 l6.S2 l6.S19 l8.S12 memory.out[10] + + + l1.W2 l6.W2 l6.W19 l8.W12 memory.out[0] + + + l1.N3 l6.N3 l6.N20 l8.N13 memory.out[1] + + + l1.E3 l6.E3 l6.E20 l8.E13 memory.out[2] + + + l1.S3 l6.S3 l6.S20 l8.S13 memory.out[3] + + + l1.W3 l6.W3 l6.W20 l8.W13 memory.out[4] + + + l1.N4 l6.N4 l6.N21 l8.N14 omux-0 + + + l1.E4 l6.E4 l6.E21 l8.E14 omux-1 + + + l1.S4 l6.S4 l6.S21 l8.S14 omux-2 + + + l1.W4 l6.W4 l6.W21 l8.W14 omux-3 + + + l2.N0 l6.N5 l6.N22 l8.N15 omux-4 + + + l2.E0 l6.E5 l6.E22 l8.E15 omux-5 + + + l2.S0 l6.S5 l6.S22 l8.S15 omux-6 + + + l2.W0 l6.W5 l6.W22 l8.W15 omux-7 + + + l2.N1 l6.N6 l6.N23 l12.N0 omux-8 + + + l2.E1 l6.E6 l6.E23 l12.E0 omux-9 + + + l2.S1 l6.S6 l6.S23 l12.S0 omux-10 + + + l2.W1 l6.W6 l6.W23 l12.W0 omux-11 + + + l2.N2 l6.N7 l8.N0 l12.N1 omux-12 + + + l2.E2 l6.E7 l8.E0 l12.E1 omux-13 + + + l2.S2 l6.S7 l8.S0 l12.S1 omux-14 + + + l2.W2 l6.W7 l8.W0 l12.W1 omux-15 + + + l2.N3 l6.N8 l8.N1 l12.N2 memory.out[0] + + + l2.E3 l6.E8 l8.E1 l12.E2 memory.out[1] + + + l2.S3 l6.S8 l8.S1 l12.S2 memory.out[2] + + + l2.W3 l6.W8 l8.W1 l12.W2 memory.out[3] + + + l2.N4 l6.N9 l8.N2 l12.N3 memory.out[4] + + + l2.E4 l6.E9 l8.E2 l12.E3 memory.out[5] + + + l2.S4 l6.S9 l8.S2 l12.S3 memory.out[6] + + + l2.W4 l6.W9 l8.W2 l12.W3 memory.out[7] + + + l2.N5 l6.N10 l8.N3 l12.N4 memory.out[8] + + + l2.E5 l6.E10 l8.E3 l12.E4 memory.out[9] + + + l2.S5 l6.S10 l8.S3 l12.S4 memory.out[10] + + + l2.W5 l6.W10 l8.W3 l12.W4 memory.out[0] + + + l3.N0 l6.N11 l8.N4 l12.N5 memory.out[1] + + + l3.E0 l6.E11 l8.E4 l12.E5 memory.out[2] + + + l3.S0 l6.S11 l8.S4 l12.S5 memory.out[3] + + + l3.W0 l6.W11 l8.W4 l12.W5 memory.out[4] + + + l3.N1 l6.N12 l8.N5 l12.N6 omux-0 + + + l3.E1 l6.E12 l8.E5 l12.E6 omux-1 + + + l3.S1 l6.S12 l8.S5 l12.S6 omux-2 + + + l3.W1 l6.W12 l8.W5 l12.W6 omux-3 + + + l3.N2 l6.N13 l8.N6 l12.N7 omux-4 + + + l3.E2 l6.E13 l8.E6 l12.E7 omux-5 + + + l3.S2 l6.S13 l8.S6 l12.S7 omux-6 + + + l3.W2 l6.W13 l8.W6 l12.W7 omux-7 + + + l3.N3 l6.N14 l8.N7 l12.N8 omux-8 + + + l3.E3 l6.E14 l8.E7 l12.E8 omux-9 + + + l3.S3 l6.S14 l8.S7 l12.S8 omux-10 + + + l3.W3 l6.W14 l8.W7 l12.W8 omux-11 + + + l3.N4 l6.N15 l8.N8 l12.N9 omux-12 + + + l3.E4 l6.E15 l8.E8 l12.E9 omux-13 + + + l3.S4 l6.S15 l8.S8 l12.S9 omux-14 + + + l3.W4 l6.W15 l8.W8 l12.W9 omux-15 + + + l3.N5 l6.N16 l8.N9 l12.N10 memory.out[0] + + + l3.E5 l6.E16 l8.E9 l12.E10 memory.out[1] + + + l3.S5 l6.S16 l8.S9 l12.S10 memory.out[2] + + + l3.W5 l6.W16 l8.W9 l12.W10 memory.out[3] + + + l1.N0 l3.N0 l6.N5 l6.N16 memory.out[0] + + + l1.E0 l3.E0 l6.E5 l6.E16 memory.out[1] + + + l1.S0 l3.S0 l6.S5 l6.S16 memory.out[2] + + + l1.W0 l3.W0 l6.W5 l6.W16 memory.out[3] + + + l1.N1 l3.N1 l6.N6 l6.N17 memory.out[4] + + + l1.E1 l3.E1 l6.E6 l6.E17 memory.out[5] + + + l1.S1 l3.S1 l6.S6 l6.S17 memory.out[6] + + + l1.W1 l3.W1 l6.W6 l6.W17 memory.out[7] + + + l1.N2 l3.N2 l6.N7 l6.N18 memory.out[8] + + + l1.E2 l3.E2 l6.E7 l6.E18 memory.out[9] + + + l1.S2 l3.S2 l6.S7 l6.S18 memory.out[10] + + + l1.W2 l3.W2 l6.W7 l6.W18 memory.out[0] + + + l1.N3 l3.N3 l6.N8 l6.N19 memory.out[1] + + + l1.E3 l3.E3 l6.E8 l6.E19 memory.out[2] + + + l1.S3 l3.S3 l6.S8 l6.S19 memory.out[3] + + + l1.W3 l3.W3 l6.W8 l6.W19 memory.out[4] + + + l1.N4 l3.N4 l6.N9 l6.N20 omux-0 + + + l1.E4 l3.E4 l6.E9 l6.E20 omux-1 + + + l1.S4 l3.S4 l6.S9 l6.S20 omux-2 + + + l1.W4 l3.W4 l6.W9 l6.W20 omux-3 + + + + + memory.addr1[0] + mux-0 mux-1 mux-2 mux-3 mux-4 mux-5 + + + memory.data[0] + mux-8 mux-9 mux-10 mux-11 mux-12 mux-13 + + + memory.data[6] + mux-16 mux-17 mux-18 mux-19 mux-20 mux-21 + + + memory.addr1[2] + mux-24 mux-25 mux-26 mux-27 mux-28 mux-29 + + + memory.data[2] + mux-32 mux-33 mux-34 mux-35 mux-36 mux-37 + + + memory.data[8] + mux-40 mux-41 mux-42 mux-43 mux-44 mux-45 + + + memory.addr2[1] + mux-48 mux-49 mux-50 mux-51 mux-52 mux-53 + + + memory.data[4] + mux-56 mux-57 mux-58 mux-59 mux-60 mux-61 + + + memory.addr1[1] + mux-64 mux-65 mux-66 mux-67 mux-_0 mux-_1 + + + memory.data[1] + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 + + + memory.data[7] + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 + + + memory.addr2[0] + mux-1 mux-2 mux-3 mux-4 mux-5 mux-6 + + + memory.data[3] + mux-9 mux-10 mux-11 mux-12 mux-13 mux-14 + + + memory.data[9] + mux-17 mux-18 mux-19 mux-20 mux-21 mux-22 + + + memory.addr2[2] + mux-25 mux-26 mux-27 mux-28 mux-29 mux-30 + + + memory.data[5] + mux-33 mux-34 mux-35 mux-36 mux-37 mux-38 + + + memory.addr1[2] + mux-41 mux-42 mux-43 mux-44 mux-45 mux-46 + + + memory.data[2] + mux-49 mux-50 mux-51 mux-52 mux-53 mux-54 + + + memory.data[8] + mux-57 mux-58 mux-59 mux-60 mux-61 mux-62 + + + memory.addr2[1] + mux-65 mux-66 mux-67 mux-_0 mux-_1 mux-_2 + + + memory.data[4] + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 + + + memory.addr1[0] + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 + + + memory.data[0] + mux-2 mux-3 mux-4 mux-5 mux-6 mux-7 + + + memory.data[6] + mux-10 mux-11 mux-12 mux-13 mux-14 mux-15 + + + memory.addr2[0] + mux-18 mux-19 mux-20 mux-21 mux-22 mux-23 + + + memory.data[3] + mux-26 mux-27 mux-28 mux-29 mux-30 mux-31 + + + memory.data[9] + mux-34 mux-35 mux-36 mux-37 mux-38 mux-39 + + + memory.addr2[2] + mux-42 mux-43 mux-44 mux-45 mux-46 mux-47 + + + memory.data[5] + mux-50 mux-51 mux-52 mux-53 mux-54 mux-55 + + + memory.addr1[1] + mux-58 mux-59 mux-60 mux-61 mux-62 mux-63 + + + memory.data[1] + mux-66 mux-67 mux-_0 mux-_1 mux-_2 mux-_3 + + + memory.data[7] + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 + + + memory.addr2[1] + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 + + + memory.data[4] + mux-3 mux-4 mux-5 mux-6 mux-7 mux-0 + + + memory.addr1[0] + mux-11 mux-12 mux-13 mux-14 mux-15 mux-8 + + + memory.data[0] + mux-19 mux-20 mux-21 mux-22 mux-23 mux-16 + + + memory.data[6] + mux-27 mux-28 mux-29 mux-30 mux-31 mux-24 + + + memory.addr1[2] + mux-35 mux-36 mux-37 mux-38 mux-39 mux-32 + + + memory.data[2] + mux-43 mux-44 mux-45 mux-46 mux-47 mux-40 + + + memory.data[8] + mux-51 mux-52 mux-53 mux-54 mux-55 mux-48 + + + memory.addr2[2] + mux-59 mux-60 mux-61 mux-62 mux-63 mux-56 + + + memory.data[5] + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 mux-64 + + + memory.addr1[1] + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 + + + memory.data[1] + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 + + + memory.data[7] + mux-4 mux-5 mux-6 mux-7 mux-0 mux-1 + + + memory.addr2[0] + mux-12 mux-13 mux-14 mux-15 mux-8 mux-9 + + + memory.data[3] + mux-20 mux-21 mux-22 mux-23 mux-16 mux-17 + + + memory.data[9] + mux-28 mux-29 mux-30 mux-31 mux-24 mux-25 + + + l1.N0 + mux-0 mux-1 mux-2 mux-3 mux-4 omux-0 + + + l1.N1 + mux-8 mux-9 mux-10 mux-11 mux-12 omux-1 + + + l1.N2 + mux-16 mux-17 mux-18 mux-19 mux-20 omux-2 + + + l1.N3 + mux-24 mux-25 mux-26 mux-27 mux-28 omux-3 + + + l1.N4 + mux-32 mux-33 mux-34 mux-35 mux-36 omux-4 + + + l2.N0 + mux-40 mux-41 mux-42 mux-43 mux-44 omux-5 + + + l2.N2 + mux-48 mux-49 mux-50 mux-51 mux-52 omux-6 + + + l2.N4 + mux-56 mux-57 mux-58 mux-59 mux-60 omux-7 + + + l3.N0 + mux-64 mux-65 mux-66 mux-67 mux-_0 omux-8 + + + l3.N3 + mux-_4 mux-_5 mux-_6 mux-_7 mux-_8 omux-9 + + + l6.N0 + mux-_12 mux-_13 mux-_14 mux-_15 mux-_16 omux-10 + + + l6.N6 + mux-1 mux-2 mux-3 mux-4 mux-5 omux-11 + + + l6.N12 + mux-9 mux-10 mux-11 mux-12 mux-13 omux-12 + + + l6.N18 + mux-17 mux-18 mux-19 mux-20 mux-21 omux-13 + + + l8.N0 + mux-25 mux-26 mux-27 mux-28 mux-29 omux-14 + + + l8.N8 + mux-33 mux-34 mux-35 mux-36 mux-37 omux-15 + + + l12.N0 + mux-41 mux-42 mux-43 mux-44 mux-45 omux-0 + + + l1.E0 + mux-49 mux-50 mux-51 mux-52 mux-53 omux-1 + + + l1.E1 + mux-57 mux-58 mux-59 mux-60 mux-61 omux-2 + + + l1.E2 + mux-65 mux-66 mux-67 mux-_0 mux-_1 omux-3 + + + l1.E3 + mux-_5 mux-_6 mux-_7 mux-_8 mux-_9 omux-4 + + + l1.E4 + mux-_13 mux-_14 mux-_15 mux-_16 mux-_17 omux-5 + + + l2.E0 + mux-2 mux-3 mux-4 mux-5 mux-6 omux-6 + + + l2.E2 + mux-10 mux-11 mux-12 mux-13 mux-14 omux-7 + + + l2.E4 + mux-18 mux-19 mux-20 mux-21 mux-22 omux-8 + + + l3.E0 + mux-26 mux-27 mux-28 mux-29 mux-30 omux-9 + + + l3.E3 + mux-34 mux-35 mux-36 mux-37 mux-38 omux-10 + + + l6.E0 + mux-42 mux-43 mux-44 mux-45 mux-46 omux-11 + + + l6.E6 + mux-50 mux-51 mux-52 mux-53 mux-54 omux-12 + + + l6.E12 + mux-58 mux-59 mux-60 mux-61 mux-62 omux-13 + + + l6.E18 + mux-66 mux-67 mux-_0 mux-_1 mux-_2 omux-14 + + + l8.E0 + mux-_6 mux-_7 mux-_8 mux-_9 mux-_10 omux-15 + + + l8.E8 + mux-_14 mux-_15 mux-_16 mux-_17 mux-_18 omux-0 + + + l12.E0 + mux-3 mux-4 mux-5 mux-6 mux-7 omux-1 + + + l1.S0 + mux-11 mux-12 mux-13 mux-14 mux-15 omux-2 + + + l1.S1 + mux-19 mux-20 mux-21 mux-22 mux-23 omux-3 + + + l1.S2 + mux-27 mux-28 mux-29 mux-30 mux-31 omux-4 + + + l1.S3 + mux-35 mux-36 mux-37 mux-38 mux-39 omux-5 + + + l1.S4 + mux-43 mux-44 mux-45 mux-46 mux-47 omux-6 + + + l2.S0 + mux-51 mux-52 mux-53 mux-54 mux-55 omux-7 + + + l2.S2 + mux-59 mux-60 mux-61 mux-62 mux-63 omux-8 + + + l2.S4 + mux-67 mux-_0 mux-_1 mux-_2 mux-_3 omux-9 + + + l3.S0 + mux-_7 mux-_8 mux-_9 mux-_10 mux-_11 omux-10 + + + l3.S3 + mux-_15 mux-_16 mux-_17 mux-_18 mux-_19 omux-11 + + + l6.S0 + mux-4 mux-5 mux-6 mux-7 mux-0 omux-12 + + + l6.S6 + mux-12 mux-13 mux-14 mux-15 mux-8 omux-13 + + + l6.S12 + mux-20 mux-21 mux-22 mux-23 mux-16 omux-14 + + + l6.S18 + mux-28 mux-29 mux-30 mux-31 mux-24 omux-15 + + + l8.S0 + mux-36 mux-37 mux-38 mux-39 mux-32 omux-0 + + + l8.S8 + mux-44 mux-45 mux-46 mux-47 mux-40 omux-1 + + + l12.S0 + mux-52 mux-53 mux-54 mux-55 mux-48 omux-2 + + + l1.W0 + mux-60 mux-61 mux-62 mux-63 mux-56 omux-3 + + + l1.W1 + mux-_0 mux-_1 mux-_2 mux-_3 mux-64 omux-4 + + + l1.W2 + mux-_8 mux-_9 mux-_10 mux-_11 mux-_4 omux-5 + + + l1.W3 + mux-_16 mux-_17 mux-_18 mux-_19 mux-_12 omux-6 + + + l1.W4 + mux-5 mux-6 mux-7 mux-0 mux-1 omux-7 + + + l2.W0 + mux-13 mux-14 mux-15 mux-8 mux-9 omux-8 + + + l2.W2 + mux-21 mux-22 mux-23 mux-16 mux-17 omux-9 + + + l2.W4 + mux-29 mux-30 mux-31 mux-24 mux-25 omux-10 + + + l3.W0 + mux-37 mux-38 mux-39 mux-32 mux-33 omux-11 + + + l3.W3 + mux-45 mux-46 mux-47 mux-40 mux-41 omux-12 + + + l6.W0 + mux-53 mux-54 mux-55 mux-48 mux-49 omux-13 + + + l6.W6 + mux-61 mux-62 mux-63 mux-56 mux-57 omux-14 + + + l6.W12 + mux-_1 mux-_2 mux-_3 mux-64 mux-65 omux-15 + + + l6.W18 + mux-_9 mux-_10 mux-_11 mux-_4 mux-_5 omux-0 + + + l8.W0 + mux-_17 mux-_18 mux-_19 mux-_12 mux-_13 omux-1 + + + l8.W8 + mux-6 mux-7 mux-0 mux-1 mux-2 omux-2 + + + l12.W0 + mux-14 mux-15 mux-8 mux-9 mux-10 omux-3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml new file mode 100644 index 00000000000..6e97691e42d --- /dev/null +++ b/vtr_flow/arch/timing/k4_N4_tileable_90nm.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml b/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml new file mode 100644 index 00000000000..33eab099c51 --- /dev/null +++ b/vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + 2.253000e-10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml b/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml new file mode 100644 index 00000000000..6b027fe6a21 --- /dev/null +++ b/vtr_flow/arch/timing/k4_frac_N4_fracff_localClkGen_40nm.xml @@ -0,0 +1,635 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif new file mode 100644 index 00000000000..884a1ede974 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Divide.blif @@ -0,0 +1,2290 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model Divide +.inputs clk reset start A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] A[20] A[21] A[22] A[23] A[24] A[25] A[26] A[27] A[28] A[29] A[30] A[31] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] B[8] B[9] B[10] B[11] B[12] B[13] B[14] B[15] B[16] B[17] B[18] B[19] B[20] B[21] B[22] B[23] B[24] B[25] B[26] B[27] B[28] B[29] B[30] B[31] +.outputs D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] R[8] R[9] R[10] R[11] R[12] R[13] R[14] R[15] R[16] R[17] R[18] R[19] R[20] R[21] R[22] R[23] R[24] R[25] R[26] R[27] R[28] R[29] R[30] R[31] ok err +.names $false +.names $true +1 +.names $undef +.names start active denom[30] B[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1342 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[29] B[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1344 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[28] B[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1346 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[27] B[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1348 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[26] B[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1350 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[25] B[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1352 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[24] B[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1354 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[23] B[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1356 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[22] B[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1358 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[21] B[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1360 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[20] B[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1362 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[19] B[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1364 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[18] B[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1366 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[17] B[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1368 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[16] B[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1370 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[15] B[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1372 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[14] B[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1374 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[13] B[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1376 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[12] B[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1378 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[11] B[11] $abc$1738$auto$rtlil.cc:2693:MuxGate$1380 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[10] B[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1382 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[9] B[9] $abc$1738$auto$rtlil.cc:2693:MuxGate$1384 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[8] B[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1386 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[7] B[7] $abc$1738$auto$rtlil.cc:2693:MuxGate$1388 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[6] B[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1390 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[5] B[5] $abc$1738$auto$rtlil.cc:2693:MuxGate$1392 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[4] B[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1394 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[3] B[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1396 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[2] B[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1398 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[1] B[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1400 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active denom[0] B[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1402 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active D[30] D[29] A[30] $abc$1738$auto$rtlil.cc:2693:MuxGate$1404 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[29] D[28] A[29] $abc$1738$auto$rtlil.cc:2693:MuxGate$1406 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[28] D[27] A[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1408 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[27] D[26] A[27] $abc$1738$auto$rtlil.cc:2693:MuxGate$1410 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[26] D[25] A[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1412 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[25] D[24] A[25] $abc$1738$auto$rtlil.cc:2693:MuxGate$1414 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[24] D[23] A[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1416 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[23] D[22] A[23] $abc$1738$auto$rtlil.cc:2693:MuxGate$1418 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[22] D[21] A[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1420 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[21] D[20] A[21] $abc$1738$auto$rtlil.cc:2693:MuxGate$1422 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[20] D[19] A[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[19] D[18] A[19] $abc$1738$auto$rtlil.cc:2693:MuxGate$1426 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[18] D[17] A[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1428 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[17] D[16] A[17] $abc$1738$auto$rtlil.cc:2693:MuxGate$1430 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[16] D[15] A[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1432 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[15] D[14] A[15] $abc$1738$auto$rtlil.cc:2693:MuxGate$1434 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[14] D[13] A[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1436 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[13] D[12] A[13] $abc$1738$auto$rtlil.cc:2693:MuxGate$1438 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[12] D[11] A[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1440 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[11] D[10] A[11] $abc$1738$auto$rtlil.cc:2693:MuxGate$1442 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[10] D[9] A[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1444 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[9] D[8] A[9] $abc$1738$auto$rtlil.cc:2693:MuxGate$1446 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[8] D[7] A[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1448 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[7] D[6] A[7] $abc$1738$auto$rtlil.cc:2693:MuxGate$1450 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[6] D[5] A[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1452 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[5] D[4] A[5] $abc$1738$auto$rtlil.cc:2693:MuxGate$1454 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[4] D[3] A[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1456 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[3] D[2] A[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1458 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[2] D[1] A[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1460 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[1] D[0] A[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1462 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names start active D[0] $abc$1738$new_n335 A[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1464 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names R[29] denom[30] denom[31] R[30] $abc$1738$new_n336 $abc$1738$new_n335 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names denom[28] R[27] R[28] denom[29] $abc$1738$new_n337 $abc$1738$new_n336 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[26] R[25] R[26] denom[27] $abc$1738$new_n338 $abc$1738$new_n337 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[24] R[23] R[24] denom[25] $abc$1738$new_n339 $abc$1738$new_n338 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[22] R[21] R[22] denom[23] $abc$1738$new_n340 $abc$1738$new_n339 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[20] R[19] R[20] denom[21] $abc$1738$new_n341 $abc$1738$new_n340 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[18] R[17] R[18] denom[19] $abc$1738$new_n342 $abc$1738$new_n341 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[16] R[15] R[16] denom[17] $abc$1738$new_n343 $abc$1738$new_n342 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[14] R[13] R[14] denom[15] $abc$1738$new_n344 $abc$1738$new_n343 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[12] R[11] R[12] denom[13] $abc$1738$new_n345 $abc$1738$new_n344 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[10] R[9] R[10] denom[11] $abc$1738$new_n346 $abc$1738$new_n345 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[8] R[7] R[8] denom[9] $abc$1738$new_n347 $abc$1738$new_n346 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[6] R[5] R[6] denom[7] $abc$1738$new_n348 $abc$1738$new_n347 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[4] R[3] R[4] denom[5] $abc$1738$new_n349 $abc$1738$new_n348 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[2] R[1] R[2] denom[3] $abc$1738$new_n350 $abc$1738$new_n349 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names denom[0] D[31] R[0] denom[1] $abc$1738$new_n350 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names cycle[3] $abc$1738$new_n352 start active $abc$1738$auto$rtlil.cc:2693:MuxGate$1466 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names start cycle[0] cycle[1] cycle[2] $abc$1738$new_n352 +1000 1 +.names cycle[2] active start cycle[0] cycle[1] $abc$1738$auto$rtlil.cc:2693:MuxGate$1468 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names cycle[1] active start cycle[0] $abc$1738$auto$rtlil.cc:2693:MuxGate$1470 +0010 1 +0011 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names start cycle[0] active $abc$1738$auto$rtlil.cc:2693:MuxGate$1472 +010 1 +011 1 +100 1 +101 1 +110 1 +.names start R[30] active $abc$1738$new_n357 $abc$1738$new_n358 $abc$1738$auto$rtlil.cc:2693:MuxGate$1474 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names R[29] denom[31] R[30] $abc$1738$new_n357 +000 1 +010 1 +011 1 +.names denom[30] $abc$1738$new_n336 R[29] R[30] denom[31] $abc$1738$new_n358 +00000 1 +00010 1 +00011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10110 1 +10111 1 +11010 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n362 $abc$1738$new_n360 R[28] $abc$1738$auto$rtlil.cc:2693:MuxGate$1476 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[28] denom[29] R[27] denom[28] $abc$1738$new_n337 $abc$1738$new_n360 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names active start $abc$1738$new_n361 +11 1 +.names R[29] start $abc$1738$new_n362 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n368 $abc$1738$new_n367 R[26] $abc$1738$auto$rtlil.cc:2693:MuxGate$1480 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[26] denom[27] R[25] denom[26] $abc$1738$new_n338 $abc$1738$new_n367 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[27] start $abc$1738$new_n368 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n374 $abc$1738$new_n373 R[24] $abc$1738$auto$rtlil.cc:2693:MuxGate$1484 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[24] denom[25] R[23] denom[24] $abc$1738$new_n339 $abc$1738$new_n373 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[25] start $abc$1738$new_n374 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n380 $abc$1738$new_n379 R[22] $abc$1738$auto$rtlil.cc:2693:MuxGate$1488 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[22] denom[23] R[21] denom[22] $abc$1738$new_n340 $abc$1738$new_n379 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[23] start $abc$1738$new_n380 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n386 $abc$1738$new_n385 R[20] $abc$1738$auto$rtlil.cc:2693:MuxGate$1492 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[20] denom[21] R[19] denom[20] $abc$1738$new_n341 $abc$1738$new_n385 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[21] start $abc$1738$new_n386 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n392 $abc$1738$new_n391 R[18] $abc$1738$auto$rtlil.cc:2693:MuxGate$1496 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[18] denom[19] R[17] denom[18] $abc$1738$new_n342 $abc$1738$new_n391 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[19] start $abc$1738$new_n392 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n398 $abc$1738$new_n397 R[16] $abc$1738$auto$rtlil.cc:2693:MuxGate$1500 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[16] denom[17] R[15] denom[16] $abc$1738$new_n343 $abc$1738$new_n397 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[17] start $abc$1738$new_n398 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n404 $abc$1738$new_n403 R[14] $abc$1738$auto$rtlil.cc:2693:MuxGate$1504 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[14] denom[15] R[13] denom[14] $abc$1738$new_n344 $abc$1738$new_n403 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[15] start $abc$1738$new_n404 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n410 $abc$1738$new_n409 R[12] $abc$1738$auto$rtlil.cc:2693:MuxGate$1508 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[12] denom[13] R[11] denom[12] $abc$1738$new_n345 $abc$1738$new_n409 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[13] start $abc$1738$new_n410 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n416 $abc$1738$new_n415 R[10] $abc$1738$auto$rtlil.cc:2693:MuxGate$1512 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[10] denom[11] R[9] denom[10] $abc$1738$new_n346 $abc$1738$new_n415 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[11] start $abc$1738$new_n416 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n422 $abc$1738$new_n421 R[8] $abc$1738$auto$rtlil.cc:2693:MuxGate$1516 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[8] denom[9] R[7] denom[8] $abc$1738$new_n347 $abc$1738$new_n421 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[9] start $abc$1738$new_n422 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n428 $abc$1738$new_n427 R[6] $abc$1738$auto$rtlil.cc:2693:MuxGate$1520 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[6] denom[7] R[5] denom[6] $abc$1738$new_n348 $abc$1738$new_n427 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[7] start $abc$1738$new_n428 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n434 $abc$1738$new_n433 R[4] $abc$1738$auto$rtlil.cc:2693:MuxGate$1524 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[4] denom[5] R[3] denom[4] $abc$1738$new_n349 $abc$1738$new_n433 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[5] start $abc$1738$new_n434 +10 1 +.names $abc$1738$new_n361 $abc$1738$new_n335 $abc$1738$new_n440 $abc$1738$new_n439 R[2] $abc$1738$auto$rtlil.cc:2693:MuxGate$1528 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names R[2] denom[3] R[1] denom[2] $abc$1738$new_n350 $abc$1738$new_n439 +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names R[3] start $abc$1738$new_n440 +10 1 +.names $abc$1738$new_n361 D[31] denom[0] $abc$1738$new_n335 $abc$1738$new_n448 $abc$1738$auto$rtlil.cc:2693:MuxGate$1534 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names R[0] start $abc$1738$new_n448 +10 1 +.names start R[31] active R[30] $abc$1738$new_n450 $abc$1738$auto$rtlil.cc:2693:MuxGate$1536 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names denom[31] R[29] denom[30] $abc$1738$new_n336 $abc$1738$new_n450 +0001 1 +0010 1 +0011 1 +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names start active denom[31] B[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1538 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names start active D[31] D[30] A[31] $abc$1738$auto$rtlil.cc:2693:MuxGate$1540 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names cycle[4] $abc$1738$new_n352 cycle[3] start active $abc$1738$auto$rtlil.cc:2693:MuxGate$1542 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names active start $abc$1738$new_n352 cycle[4] cycle[3] $abc$1738$auto$rtlil.cc:2693:MuxGate$1544 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$1738$new_n462 $abc$1738$new_n460 $abc$1738$new_n458 $abc$1738$new_n456 err +1111 1 +.names $abc$1738$new_n457 B[31] B[0] B[1] B[2] $abc$1738$new_n456 +10000 1 +.names B[3] B[4] B[5] B[6] $abc$1738$new_n457 +0000 1 +.names $abc$1738$new_n459 B[11] B[12] B[13] B[14] $abc$1738$new_n458 +10000 1 +.names B[7] B[8] B[9] B[10] $abc$1738$new_n459 +0000 1 +.names $abc$1738$new_n461 B[19] B[20] B[21] B[22] $abc$1738$new_n460 +10000 1 +.names B[15] B[16] B[17] B[18] $abc$1738$new_n461 +0000 1 +.names $abc$1738$new_n463 B[27] B[28] B[29] B[30] $abc$1738$new_n462 +10000 1 +.names B[23] B[24] B[25] B[26] $abc$1738$new_n463 +0000 1 +.names active ok +0 1 +.names start $abc$1738$new_n337 denom[28] R[28] $abc$1738$new_n465 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[27] start $abc$1738$new_n465 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1478 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n338 denom[26] R[26] $abc$1738$new_n467 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[25] start $abc$1738$new_n467 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1482 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n339 denom[24] R[24] $abc$1738$new_n469 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[23] start $abc$1738$new_n469 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1486 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n340 denom[22] R[22] $abc$1738$new_n471 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[21] start $abc$1738$new_n471 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1490 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n341 denom[20] R[20] $abc$1738$new_n473 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[19] start $abc$1738$new_n473 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1494 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n342 denom[18] R[18] $abc$1738$new_n475 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[17] start $abc$1738$new_n475 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1498 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n343 denom[16] R[16] $abc$1738$new_n477 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[15] start $abc$1738$new_n477 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1502 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n344 denom[14] R[14] $abc$1738$new_n479 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[13] start $abc$1738$new_n479 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1506 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n345 denom[12] R[12] $abc$1738$new_n481 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[11] start $abc$1738$new_n481 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1510 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n346 denom[10] R[10] $abc$1738$new_n483 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[9] start $abc$1738$new_n483 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1514 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n347 denom[8] R[8] $abc$1738$new_n485 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[7] start $abc$1738$new_n485 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1518 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n348 denom[6] R[6] $abc$1738$new_n487 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[5] start $abc$1738$new_n487 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1522 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n349 denom[4] R[4] $abc$1738$new_n489 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[3] start $abc$1738$new_n489 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1526 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start $abc$1738$new_n350 denom[2] R[2] $abc$1738$new_n491 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names active R[1] start $abc$1738$new_n491 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1530 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names start denom[1] denom[0] D[31] R[1] $abc$1738$new_n493 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names active R[0] start $abc$1738$new_n493 $abc$1738$new_n335 $abc$1738$auto$rtlil.cc:2693:MuxGate$1532 +00010 1 +00011 1 +01010 1 +01011 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1534 Q=R[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1532 Q=R[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1530 Q=R[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1528 Q=R[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1526 Q=R[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1524 Q=R[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1522 Q=R[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1520 Q=R[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1518 Q=R[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1516 Q=R[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1514 Q=R[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1512 Q=R[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1510 Q=R[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1508 Q=R[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1506 Q=R[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1504 Q=R[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1502 Q=R[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1500 Q=R[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1498 Q=R[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1496 Q=R[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1494 Q=R[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1492 Q=R[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1490 Q=R[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1488 Q=R[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1486 Q=R[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1484 Q=R[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1482 Q=R[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1480 Q=R[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1478 Q=R[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1476 Q=R[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1474 Q=R[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1536 Q=R[31] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1544 Q=active R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1472 Q=cycle[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1470 Q=cycle[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1468 Q=cycle[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1466 Q=cycle[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1542 Q=cycle[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1464 Q=D[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1462 Q=D[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1460 Q=D[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1458 Q=D[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1456 Q=D[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1454 Q=D[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1452 Q=D[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1450 Q=D[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1448 Q=D[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1446 Q=D[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1444 Q=D[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1442 Q=D[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1440 Q=D[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1438 Q=D[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1436 Q=D[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1434 Q=D[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1432 Q=D[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1430 Q=D[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1428 Q=D[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1426 Q=D[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1424 Q=D[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1422 Q=D[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1420 Q=D[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1418 Q=D[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1416 Q=D[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1414 Q=D[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1412 Q=D[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1410 Q=D[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1408 Q=D[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1406 Q=D[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1404 Q=D[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1540 Q=D[31] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1402 Q=denom[0] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1400 Q=denom[1] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1398 Q=denom[2] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1396 Q=denom[3] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1394 Q=denom[4] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1392 Q=denom[5] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1390 Q=denom[6] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1388 Q=denom[7] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1386 Q=denom[8] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1384 Q=denom[9] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1382 Q=denom[10] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1380 Q=denom[11] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1378 Q=denom[12] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1376 Q=denom[13] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1374 Q=denom[14] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1372 Q=denom[15] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1370 Q=denom[16] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1368 Q=denom[17] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1366 Q=denom[18] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1364 Q=denom[19] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1362 Q=denom[20] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1360 Q=denom[21] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1358 Q=denom[22] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1356 Q=denom[23] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1354 Q=denom[24] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1352 Q=denom[25] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1350 Q=denom[26] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1348 Q=denom[27] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1346 Q=denom[28] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1344 Q=denom[29] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1342 Q=denom[30] R=reset +.subckt dffr C=clk D=$abc$1738$auto$rtlil.cc:2693:MuxGate$1538 Q=denom[31] R=reset +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif new file mode 100644 index 00000000000..dec03bfebde --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/GrayCounter.blif @@ -0,0 +1,51 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model GrayCounter +.inputs clk +.outputs cnt_gray[0] cnt_gray[1] cnt_gray[2] cnt_gray[3] +.names $false +.names $true +1 +.names $undef +.names cnt[2] cnt[1] cnt_gray[1] +01 1 +10 1 +.names cnt_gray[3] cnt[2] cnt_gray[2] +01 1 +10 1 +.names cnt[1] cnt[0] cnt_gray[0] +01 1 +10 1 +.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[2] +011 1 +100 1 +101 1 +110 1 +.names cnt_gray[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$401.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[0] $auto$alumacc.cc:485:replace_alu$401.X[0] +0 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.X[0] Q=cnt[0] +.subckt dff C=clk D=cnt_gray[0] Q=cnt[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[2] Q=cnt[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$401.Y[3] Q=cnt_gray[3] +.names cnt[1] $auto$alumacc.cc:485:replace_alu$401.X[1] +1 1 +.names cnt[2] $auto$alumacc.cc:485:replace_alu$401.X[2] +1 1 +.names cnt_gray[3] $auto$alumacc.cc:485:replace_alu$401.X[3] +1 1 +.names $auto$alumacc.cc:485:replace_alu$401.X[0] $auto$alumacc.cc:485:replace_alu$401.Y[0] +1 1 +.names cnt_gray[0] $auto$alumacc.cc:485:replace_alu$401.Y[1] +1 1 +.names cnt_gray[3] cnt[3] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif new file mode 100644 index 00000000000..429f2a124a8 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LCDmodule.blif @@ -0,0 +1,389 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model LCDmodule +.inputs clk RxD +.outputs LCD_RS LCD_RW LCD_E LCD_DataBus[0] LCD_DataBus[1] LCD_DataBus[2] LCD_DataBus[3] LCD_DataBus[4] LCD_DataBus[5] LCD_DataBus[6] LCD_DataBus[7] +.names $false +.names $true +1 +.names $undef +.names count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1481 +01 1 +10 1 +.names count[0] $0\LCD_E[0:0] deserialer.RxD_data_ready $abc$1754$auto$rtlil.cc:2693:MuxGate$1483 +001 1 +010 1 +011 1 +.names count[2] count[0] count[1] $0\LCD_E[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1485 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$1754$new_n83 LCD_RS LCD_DataBus[6] $abc$1754$auto$rtlil.cc:2693:MuxGate$1487 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[3] $abc$1754$new_n84 $abc$1754$new_n83 +11 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$1754$new_n84 +1110 1 +.names $abc$1754$new_n83 LCD_DataBus[6] LCD_DataBus[5] $abc$1754$auto$rtlil.cc:2693:MuxGate$1489 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[5] LCD_DataBus[4] $abc$1754$auto$rtlil.cc:2693:MuxGate$1491 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[4] LCD_DataBus[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1493 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[3] LCD_DataBus[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1495 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[2] LCD_DataBus[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1497 +001 1 +011 1 +110 1 +111 1 +.names $abc$1754$new_n83 LCD_DataBus[1] LCD_DataBus[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1499 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1503 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n92 +0000 1 +.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$1754$new_n92 $abc$1754$auto$rtlil.cc:2693:MuxGate$1507 +010 1 +011 1 +100 1 +.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] $abc$1754$auto$rtlil.cc:2693:MuxGate$1509 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$1754$new_n96 $abc$1754$new_n84 deserialer.RxD_bit $abc$1754$new_n92 $abc$1754$new_n95 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[1] deserialer.RxD_state[0] deserialer.RxD_state[2] $abc$1754$new_n96 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$1754$new_n95 deserialer.RxD_state[0] $abc$1754$new_n92 deserialer.RxD_state[3] $abc$1754$auto$rtlil.cc:2693:MuxGate$1511 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1513 +001 1 +011 1 +110 1 +111 1 +.names count[2] count[0] count[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1515 +011 1 +100 1 +101 1 +110 1 +.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1517 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1521 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$1754$auto$rtlil.cc:2693:MuxGate$1523 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.OversamplingCnt[2] $abc$1754$new_n92 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$1754$auto$rtlil.cc:2693:MuxGate$1527 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$1754$new_n83 deserialer.RxD_bit LCD_RS $abc$1754$auto$rtlil.cc:2693:MuxGate$1529 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$1754$new_n95 $abc$1754$auto$rtlil.cc:2693:MuxGate$1533 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$1754$new_n95 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$1754$auto$rtlil.cc:2693:MuxGate$1535 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1754$new_n108 $abc$1754$new_n84 $abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] +11 1 +.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$1754$new_n108 +11000 1 +.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[1] +00 1 +11 1 +.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[5] +00 1 +11 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $abc$1754$new_n114 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $auto$alumacc.cc:485:replace_alu$595.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[9] +01 1 +10 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$1754$new_n114 $abc$1754$new_n119 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$1754$new_n119 $auto$alumacc.cc:485:replace_alu$595.CO[11] +1111 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.X[0] +0 1 +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1521 Q=deserialer.RxD_bit +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1485 Q=deserialer.Filter_cnt[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1523 Q=deserialer.Filter_cnt[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1483 Q=count[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1481 Q=count[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1515 Q=count[2] +.subckt dff C=clk D=$0\LCD_E[0:0] Q=LCD_E +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1513 Q=deserialer.RxD_sync[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1517 Q=deserialer.RxD_sync[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1511 Q=deserialer.RxD_state[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1509 Q=deserialer.RxD_state[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1535 Q=deserialer.RxD_state[3] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1533 Q=deserialer.RxD_state[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.X[0] Q=deserialer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[1] Q=deserialer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[2] Q=deserialer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[3] Q=deserialer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[4] Q=deserialer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[5] Q=deserialer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[6] Q=deserialer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[7] Q=deserialer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[8] Q=deserialer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[9] Q=deserialer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[10] Q=deserialer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.Y[11] Q=deserialer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$595.CO[11] Q=deserialer.OversamplingTick +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1507 Q=deserialer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1503 Q=deserialer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1527 Q=deserialer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1499 Q=LCD_DataBus[0] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1497 Q=LCD_DataBus[1] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1495 Q=LCD_DataBus[2] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1493 Q=LCD_DataBus[3] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1491 Q=LCD_DataBus[4] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1489 Q=LCD_DataBus[5] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1487 Q=LCD_DataBus[6] +.subckt dff C=clk D=$abc$1754$auto$rtlil.cc:2693:MuxGate$1529 Q=LCD_RS +.subckt dff C=clk D=$abc$1754$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready +.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$595.X[3] +1 1 +.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$595.X[5] +1 1 +.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$595.X[6] +1 1 +.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$595.X[8] +1 1 +.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$595.X[9] +1 1 +.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$595.X[10] +1 1 +.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$595.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$595.X[12] +1 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$595.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$595.CO[12] +1 1 +.names $false LCD_DataBus[7] +1 1 +.names $false LCD_RW +1 1 +.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] +1 1 +.names $auto$alumacc.cc:485:replace_alu$595.X[0] $auto$alumacc.cc:485:replace_alu$595.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$595.CO[11] $auto$alumacc.cc:485:replace_alu$595.Y[12] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif new file mode 100644 index 00000000000..7228a4d4759 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/LED_BCD8x7seg.blif @@ -0,0 +1,918 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model LED_BCD8x7seg +.inputs clk +.outputs segA segB segC segD segE segF segG segDP seg_cathode[0] seg_cathode[1] seg_cathode[2] seg_cathode[3] seg_cathode[4] seg_cathode[5] seg_cathode[6] seg_cathode[7] +.names $false +.names $true +1 +.names $undef +.names BCD.BCD_digits[2] BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1679 +011 1 +100 1 +101 1 +110 1 +.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n131 $abc$1987$new_n130 +111 1 +.names cnt[22] cnt[21] cnt[20] cnt[19] $abc$1987$new_n132 $abc$1987$new_n131 +11111 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 seg_cathode[7] $abc$1987$new_n132 +11110 1 +.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $abc$1987$new_n133 +11111 1 +.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $abc$1987$new_n134 +11111 1 +.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $abc$1987$new_n135 +11111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[7] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[1] $abc$1987$new_n130 $abc$1987$new_n138 $abc$1987$auto$rtlil.cc:2693:MuxGate$1683 +010 1 +100 1 +.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n138 +100 1 +.names BCD.BCD_digits[0] cnt[23] $abc$1987$new_n131 $abc$1987$auto$rtlil.cc:2693:MuxGate$1687 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[6] BCD.BCD_digits[4] BCD.BCD_digits[5] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1691 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n138 $abc$1987$new_n130 $abc$1987$new_n141 +11 1 +.names BCD.BCD_digits[5] BCD.BCD_digits[4] $abc$1987$new_n141 BCD.BCD_digits[6] BCD.BCD_digits[7] $abc$1987$auto$rtlil.cc:2693:MuxGate$1695 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1699 +01 1 +10 1 +.names BCD.BCD_digits[10] BCD.BCD_digits[8] BCD.BCD_digits[9] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1703 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[23] BCD.BCD_digits[0] $abc$1987$new_n146 $abc$1987$new_n138 $abc$1987$new_n131 $abc$1987$new_n145 +11111 1 +.names BCD.BCD_digits[7] BCD.BCD_digits[4] BCD.BCD_digits[5] BCD.BCD_digits[6] $abc$1987$new_n146 +1100 1 +.names BCD.BCD_digits[9] BCD.BCD_digits[8] $abc$1987$new_n145 BCD.BCD_digits[10] BCD.BCD_digits[11] $abc$1987$auto$rtlil.cc:2693:MuxGate$1707 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1711 +01 1 +10 1 +.names BCD.BCD_digits[14] BCD.BCD_digits[13] $abc$1987$new_n150 $abc$1987$auto$rtlil.cc:2693:MuxGate$1715 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$new_n150 +11 1 +.names $abc$1987$new_n152 $abc$1987$new_n145 $abc$1987$new_n151 +11 1 +.names BCD.BCD_digits[11] BCD.BCD_digits[8] BCD.BCD_digits[9] BCD.BCD_digits[10] $abc$1987$new_n152 +1100 1 +.names $abc$1987$new_n150 BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[15] $abc$1987$auto$rtlil.cc:2693:MuxGate$1719 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1723 +01 1 +10 1 +.names BCD.BCD_digits[18] BCD.BCD_digits[16] BCD.BCD_digits[17] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1727 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n157 $abc$1987$new_n151 $abc$1987$new_n156 +11 1 +.names BCD.BCD_digits[15] BCD.BCD_digits[12] BCD.BCD_digits[13] BCD.BCD_digits[14] $abc$1987$new_n157 +1100 1 +.names BCD.BCD_digits[17] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$new_n159 $abc$1987$auto$rtlil.cc:2693:MuxGate$1731 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BCD.BCD_digits[19] BCD.BCD_digits[18] $abc$1987$new_n159 +10 1 +.names BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1735 +01 1 +10 1 +.names BCD.BCD_digits[22] BCD.BCD_digits[20] BCD.BCD_digits[21] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1739 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$1987$new_n157 $abc$1987$new_n163 $abc$1987$new_n151 $abc$1987$new_n162 +111 1 +.names BCD.BCD_digits[16] $abc$1987$new_n159 BCD.BCD_digits[17] $abc$1987$new_n163 +110 1 +.names BCD.BCD_digits[21] BCD.BCD_digits[20] $abc$1987$new_n162 BCD.BCD_digits[22] BCD.BCD_digits[23] $abc$1987$auto$rtlil.cc:2693:MuxGate$1743 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1747 +01 1 +10 1 +.names BCD.BCD_digits[26] BCD.BCD_digits[25] $abc$1987$new_n167 $abc$1987$auto$rtlil.cc:2693:MuxGate$1751 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$new_n167 +11 1 +.names $abc$1987$new_n169 $abc$1987$new_n157 $abc$1987$new_n152 $abc$1987$new_n163 $abc$1987$new_n145 $abc$1987$new_n168 +11111 1 +.names BCD.BCD_digits[23] BCD.BCD_digits[20] BCD.BCD_digits[21] BCD.BCD_digits[22] $abc$1987$new_n169 +1100 1 +.names $abc$1987$new_n167 BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[27] $abc$1987$auto$rtlil.cc:2693:MuxGate$1755 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1759 +01 1 +10 1 +.names BCD.BCD_digits[30] BCD.BCD_digits[29] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1763 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$new_n173 +111 1 +.names BCD.BCD_digits[27] BCD.BCD_digits[24] BCD.BCD_digits[25] BCD.BCD_digits[26] $abc$1987$new_n174 +1100 1 +.names $abc$1987$new_n173 BCD.BCD_digits[29] BCD.BCD_digits[30] BCD.BCD_digits[31] $abc$1987$auto$rtlil.cc:2693:MuxGate$1767 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names BCD.BCD_digits[28] $abc$1987$new_n174 $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1771 +011 1 +100 1 +101 1 +110 1 +.names BCD.BCD_digits[31] BCD.BCD_digits[29] BCD.BCD_digits[30] $abc$1987$new_n173 $abc$1987$auto$rtlil.cc:2693:MuxGate$1775 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names BCD.BCD_digits[27] BCD.BCD_digits[25] BCD.BCD_digits[26] BCD.BCD_digits[24] $abc$1987$new_n168 $abc$1987$auto$rtlil.cc:2693:MuxGate$1779 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[23] BCD.BCD_digits[21] BCD.BCD_digits[22] BCD.BCD_digits[20] $abc$1987$new_n162 $abc$1987$auto$rtlil.cc:2693:MuxGate$1783 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[19] BCD.BCD_digits[17] BCD.BCD_digits[18] BCD.BCD_digits[16] $abc$1987$new_n156 $abc$1987$auto$rtlil.cc:2693:MuxGate$1787 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[15] BCD.BCD_digits[13] BCD.BCD_digits[14] BCD.BCD_digits[12] $abc$1987$new_n151 $abc$1987$auto$rtlil.cc:2693:MuxGate$1791 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[11] BCD.BCD_digits[9] BCD.BCD_digits[10] BCD.BCD_digits[8] $abc$1987$new_n145 $abc$1987$auto$rtlil.cc:2693:MuxGate$1795 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[7] BCD.BCD_digits[5] BCD.BCD_digits[6] BCD.BCD_digits[4] $abc$1987$new_n141 $abc$1987$auto$rtlil.cc:2693:MuxGate$1799 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names BCD.BCD_digits[3] BCD.BCD_digits[1] BCD.BCD_digits[2] $abc$1987$new_n130 $abc$1987$auto$rtlil.cc:2693:MuxGate$1803 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] cnt[17] cnt[18] seg_cathode[1] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[2] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[3] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[18] cnt[17] cnt[16] seg_cathode[4] +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names cnt[18] cnt[16] cnt[17] seg_cathode[5] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[17] cnt[18] cnt[16] seg_cathode[6] +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names cnt[17] cnt[16] cnt[18] seg_cathode[0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segG +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names cnt[18] $abc$1987$new_n194 $abc$1987$new_n196 $abc$1987$new_n193 +010 1 +011 1 +101 1 +111 1 +.names cnt[17] cnt[16] $abc$1987$new_n195 BCD.BCD_digits[10] BCD.BCD_digits[14] $abc$1987$new_n194 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names seg_cathode[1] BCD.BCD_digits[2] BCD.BCD_digits[6] $abc$1987$new_n195 +000 1 +010 1 +100 1 +101 1 +.names $abc$1987$new_n197 cnt[16] cnt[17] BCD.BCD_digits[26] BCD.BCD_digits[30] $abc$1987$new_n196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names cnt[16] cnt[18] cnt[17] BCD.BCD_digits[18] BCD.BCD_digits[22] $abc$1987$new_n197 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names cnt[18] $abc$1987$new_n199 $abc$1987$new_n201 $abc$1987$new_n202 $abc$1987$new_n198 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names cnt[17] cnt[16] $abc$1987$new_n200 BCD.BCD_digits[31] BCD.BCD_digits[27] $abc$1987$new_n199 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names seg_cathode[5] BCD.BCD_digits[19] BCD.BCD_digits[23] $abc$1987$new_n200 +000 1 +010 1 +100 1 +101 1 +.names seg_cathode[3] BCD.BCD_digits[15] cnt[17] BCD.BCD_digits[11] $abc$1987$new_n201 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] cnt[17] cnt[18] BCD.BCD_digits[3] BCD.BCD_digits[7] $abc$1987$new_n202 +00010 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names cnt[17] $abc$1987$new_n204 $abc$1987$new_n206 $abc$1987$new_n203 +001 1 +011 1 +110 1 +111 1 +.names cnt[18] cnt[16] $abc$1987$new_n205 BCD.BCD_digits[25] BCD.BCD_digits[29] $abc$1987$new_n204 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names cnt[16] BCD.BCD_digits[9] BCD.BCD_digits[13] $abc$1987$new_n205 +000 1 +001 1 +100 1 +110 1 +.names cnt[18] cnt[16] $abc$1987$new_n207 BCD.BCD_digits[17] BCD.BCD_digits[21] $abc$1987$new_n206 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names cnt[16] BCD.BCD_digits[1] BCD.BCD_digits[5] $abc$1987$new_n207 +000 1 +001 1 +100 1 +110 1 +.names cnt[18] $abc$1987$new_n209 $abc$1987$new_n211 $abc$1987$new_n208 +001 1 +011 1 +110 1 +111 1 +.names seg_cathode[7] $abc$1987$new_n210 BCD.BCD_digits[24] cnt[17] BCD.BCD_digits[28] $abc$1987$new_n209 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names cnt[16] cnt[17] BCD.BCD_digits[16] BCD.BCD_digits[20] $abc$1987$new_n210 +0010 1 +0011 1 +1001 1 +1011 1 +.names seg_cathode[3] $abc$1987$new_n212 BCD.BCD_digits[8] cnt[17] BCD.BCD_digits[12] $abc$1987$new_n211 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names cnt[16] cnt[17] BCD.BCD_digits[0] BCD.BCD_digits[4] $abc$1987$new_n212 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n208 segF +0110 1 +0111 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $abc$1987$new_n208 $abc$1987$new_n203 $abc$1987$new_n193 $abc$1987$new_n198 segE +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$1987$new_n203 $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n208 segD +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segC +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n203 $abc$1987$new_n208 $abc$1987$new_n193 segB +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$1987$new_n198 $abc$1987$new_n193 $abc$1987$new_n203 $abc$1987$new_n208 segA +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[1] +01 1 +10 1 +.names cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[2] +011 1 +100 1 +101 1 +110 1 +.names cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] $auto$alumacc.cc:485:replace_alu$473.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[5] +01 1 +10 1 +.names cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[6] +011 1 +100 1 +101 1 +110 1 +.names cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[8] cnt[7] cnt[6] cnt[5] $abc$1987$new_n135 $auto$alumacc.cc:485:replace_alu$473.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[9] +01 1 +10 1 +.names cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[10] +011 1 +100 1 +101 1 +110 1 +.names cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[12] cnt[11] cnt[10] cnt[9] $abc$1987$new_n134 $auto$alumacc.cc:485:replace_alu$473.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[13] +01 1 +10 1 +.names cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[14] +011 1 +100 1 +101 1 +110 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $auto$alumacc.cc:485:replace_alu$473.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[16] +01 1 +10 1 +.names cnt[15] cnt[14] cnt[13] $abc$1987$new_n133 $abc$1987$new_n235 +1111 1 +.names cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[17] +011 1 +100 1 +101 1 +110 1 +.names cnt[18] cnt[17] cnt[16] $abc$1987$new_n235 $auto$alumacc.cc:485:replace_alu$473.Y[18] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[19] $abc$1987$new_n132 $auto$alumacc.cc:485:replace_alu$473.Y[19] +01 1 +10 1 +.names cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[20] +01 1 +10 1 +.names cnt[19] $abc$1987$new_n132 $abc$1987$new_n240 +11 1 +.names cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[21] +011 1 +100 1 +101 1 +110 1 +.names cnt[22] cnt[21] cnt[20] $abc$1987$new_n240 $auto$alumacc.cc:485:replace_alu$473.Y[22] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names cnt[23] $abc$1987$new_n131 $auto$alumacc.cc:485:replace_alu$473.Y[23] +01 1 +10 1 +.names cnt[0] $auto$alumacc.cc:485:replace_alu$473.X[0] +0 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.X[0] Q=cnt[0] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[1] Q=cnt[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[2] Q=cnt[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[3] Q=cnt[3] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[4] Q=cnt[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[5] Q=cnt[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[6] Q=cnt[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[7] Q=cnt[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[8] Q=cnt[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[9] Q=cnt[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[10] Q=cnt[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[11] Q=cnt[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[12] Q=cnt[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[13] Q=cnt[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[14] Q=cnt[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[15] Q=cnt[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[16] Q=cnt[16] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[17] Q=cnt[17] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[18] Q=cnt[18] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[19] Q=cnt[19] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[20] Q=cnt[20] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[21] Q=cnt[21] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[22] Q=cnt[22] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$473.Y[23] Q=cnt[23] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1771 Q=BCD.BCD_digits[28] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1767 Q=BCD.BCD_digits[29] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1763 Q=BCD.BCD_digits[30] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1775 Q=BCD.BCD_digits[31] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1759 Q=BCD.BCD_digits[24] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1755 Q=BCD.BCD_digits[25] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1751 Q=BCD.BCD_digits[26] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1779 Q=BCD.BCD_digits[27] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1747 Q=BCD.BCD_digits[20] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1743 Q=BCD.BCD_digits[21] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1739 Q=BCD.BCD_digits[22] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1783 Q=BCD.BCD_digits[23] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1735 Q=BCD.BCD_digits[16] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1731 Q=BCD.BCD_digits[17] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1727 Q=BCD.BCD_digits[18] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1787 Q=BCD.BCD_digits[19] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1723 Q=BCD.BCD_digits[12] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1719 Q=BCD.BCD_digits[13] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1715 Q=BCD.BCD_digits[14] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1791 Q=BCD.BCD_digits[15] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1711 Q=BCD.BCD_digits[8] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1707 Q=BCD.BCD_digits[9] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1703 Q=BCD.BCD_digits[10] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1795 Q=BCD.BCD_digits[11] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1699 Q=BCD.BCD_digits[4] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1695 Q=BCD.BCD_digits[5] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1691 Q=BCD.BCD_digits[6] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1799 Q=BCD.BCD_digits[7] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1687 Q=BCD.BCD_digits[0] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1683 Q=BCD.BCD_digits[1] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1679 Q=BCD.BCD_digits[2] +.subckt dff C=clk D=$abc$1987$auto$rtlil.cc:2693:MuxGate$1803 Q=BCD.BCD_digits[3] +.names cnt[1] $auto$alumacc.cc:485:replace_alu$473.X[1] +1 1 +.names cnt[2] $auto$alumacc.cc:485:replace_alu$473.X[2] +1 1 +.names cnt[3] $auto$alumacc.cc:485:replace_alu$473.X[3] +1 1 +.names cnt[4] $auto$alumacc.cc:485:replace_alu$473.X[4] +1 1 +.names cnt[5] $auto$alumacc.cc:485:replace_alu$473.X[5] +1 1 +.names cnt[6] $auto$alumacc.cc:485:replace_alu$473.X[6] +1 1 +.names cnt[7] $auto$alumacc.cc:485:replace_alu$473.X[7] +1 1 +.names cnt[8] $auto$alumacc.cc:485:replace_alu$473.X[8] +1 1 +.names cnt[9] $auto$alumacc.cc:485:replace_alu$473.X[9] +1 1 +.names cnt[10] $auto$alumacc.cc:485:replace_alu$473.X[10] +1 1 +.names cnt[11] $auto$alumacc.cc:485:replace_alu$473.X[11] +1 1 +.names cnt[12] $auto$alumacc.cc:485:replace_alu$473.X[12] +1 1 +.names cnt[13] $auto$alumacc.cc:485:replace_alu$473.X[13] +1 1 +.names cnt[14] $auto$alumacc.cc:485:replace_alu$473.X[14] +1 1 +.names cnt[15] $auto$alumacc.cc:485:replace_alu$473.X[15] +1 1 +.names cnt[16] $auto$alumacc.cc:485:replace_alu$473.X[16] +1 1 +.names cnt[17] $auto$alumacc.cc:485:replace_alu$473.X[17] +1 1 +.names cnt[18] $auto$alumacc.cc:485:replace_alu$473.X[18] +1 1 +.names cnt[19] $auto$alumacc.cc:485:replace_alu$473.X[19] +1 1 +.names cnt[20] $auto$alumacc.cc:485:replace_alu$473.X[20] +1 1 +.names cnt[21] $auto$alumacc.cc:485:replace_alu$473.X[21] +1 1 +.names cnt[22] $auto$alumacc.cc:485:replace_alu$473.X[22] +1 1 +.names cnt[23] $auto$alumacc.cc:485:replace_alu$473.X[23] +1 1 +.names $auto$alumacc.cc:485:replace_alu$473.X[0] $auto$alumacc.cc:485:replace_alu$473.Y[0] +1 1 +.names $false segDP +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif new file mode 100644 index 00000000000..15b3654b812 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/Murax.blif @@ -0,0 +1,19659 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model Murax +.inputs io_asyncReset io_mainClk io_jtag_tms io_jtag_tdi io_jtag_tck io_gpioA_read[0] io_gpioA_read[1] io_gpioA_read[2] io_gpioA_read[3] io_gpioA_read[4] io_gpioA_read[5] io_gpioA_read[6] io_gpioA_read[7] io_gpioA_read[8] io_gpioA_read[9] io_gpioA_read[10] io_gpioA_read[11] io_gpioA_read[12] io_gpioA_read[13] io_gpioA_read[14] io_gpioA_read[15] io_gpioA_read[16] io_gpioA_read[17] io_gpioA_read[18] io_gpioA_read[19] io_gpioA_read[20] io_gpioA_read[21] io_gpioA_read[22] io_gpioA_read[23] io_gpioA_read[24] io_gpioA_read[25] io_gpioA_read[26] io_gpioA_read[27] io_gpioA_read[28] io_gpioA_read[29] io_gpioA_read[30] io_gpioA_read[31] io_uart_rxd +.outputs io_jtag_tdo io_gpioA_write[0] io_gpioA_write[1] io_gpioA_write[2] io_gpioA_write[3] io_gpioA_write[4] io_gpioA_write[5] io_gpioA_write[6] io_gpioA_write[7] io_gpioA_write[8] io_gpioA_write[9] io_gpioA_write[10] io_gpioA_write[11] io_gpioA_write[12] io_gpioA_write[13] io_gpioA_write[14] io_gpioA_write[15] io_gpioA_write[16] io_gpioA_write[17] io_gpioA_write[18] io_gpioA_write[19] io_gpioA_write[20] io_gpioA_write[21] io_gpioA_write[22] io_gpioA_write[23] io_gpioA_write[24] io_gpioA_write[25] io_gpioA_write[26] io_gpioA_write[27] io_gpioA_write[28] io_gpioA_write[29] io_gpioA_write[30] io_gpioA_write[31] io_gpioA_writeEnable[0] io_gpioA_writeEnable[1] io_gpioA_writeEnable[2] io_gpioA_writeEnable[3] io_gpioA_writeEnable[4] io_gpioA_writeEnable[5] io_gpioA_writeEnable[6] io_gpioA_writeEnable[7] io_gpioA_writeEnable[8] io_gpioA_writeEnable[9] io_gpioA_writeEnable[10] io_gpioA_writeEnable[11] io_gpioA_writeEnable[12] io_gpioA_writeEnable[13] io_gpioA_writeEnable[14] io_gpioA_writeEnable[15] io_gpioA_writeEnable[16] io_gpioA_writeEnable[17] io_gpioA_writeEnable[18] io_gpioA_writeEnable[19] io_gpioA_writeEnable[20] io_gpioA_writeEnable[21] io_gpioA_writeEnable[22] io_gpioA_writeEnable[23] io_gpioA_writeEnable[24] io_gpioA_writeEnable[25] io_gpioA_writeEnable[26] io_gpioA_writeEnable[27] io_gpioA_writeEnable[28] io_gpioA_writeEnable[29] io_gpioA_writeEnable[30] io_gpioA_writeEnable[31] io_uart_txd +.names $false +.names $true +1 +.names $undef +.names $abc$18544$new_n2708 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.timerBBridge_ticksEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2713 $abc$18544$new_n2709 $abc$18544$new_n2708 +11 1 +.names $abc$18544$new_n2712 apb3Router_1._zz_selIndex_1 $abc$18544$new_n2709 +11 1 +.names apb3Router_1.io_input_PADDR[17] io_apb_decoder.io_input_PSEL $abc$18544$new_n2711 apb3Router_1.io_input_PADDR[18] apb3Router_1.io_input_PADDR[19] apb3Router_1._zz_selIndex_1 +11100 1 +.names apb3Router_1.io_input_PADDR[12] apb3Router_1.io_input_PADDR[13] apb3Router_1.io_input_PADDR[14] apb3Router_1.io_input_PADDR[15] apb3Router_1.io_input_PADDR[16] $abc$18544$new_n2711 +00000 1 +.names apb3Router_1.io_input_PENABLE apb3Router_1.io_input_PWRITE $abc$18544$new_n2712 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2713 +11100 1 +.names apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n2714 +0000 1 +.names $abc$18544$new_n2716 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.timerABridge_ticksEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14554 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2717 $abc$18544$new_n2709 $abc$18544$new_n2716 +11 1 +.names apb3Router_1.io_input_PADDR[6] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2717 +11000 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[14] system_timer.system_timer_timerB_io_limit_driver[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14556 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2722 $abc$18544$new_n2720 $abc$18544$new_n2719 +11 1 +.names apb3Router_1._zz_selIndex_1 $abc$18544$new_n2712 $abc$18544$new_n2720 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2722 +11100 1 +.names apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n2723 +1000 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[13] system_timer.system_timer_timerB_io_limit_driver[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14558 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[12] system_timer.system_timer_timerB_io_limit_driver[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14560 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer.system_timer_timerB_io_limit_driver[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14562 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l379 system_timer.system_timer_timerB_io_limit_driver[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer.system_timer_timerB_io_limit_driver[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14566 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[8] system_timer.system_timer_timerB_io_limit_driver[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14568 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[7] system_timer.system_timer_timerB_io_limit_driver[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14570 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[6] system_timer.system_timer_timerB_io_limit_driver[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[5] system_timer.system_timer_timerB_io_limit_driver[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[4] system_timer.system_timer_timerB_io_limit_driver[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[3] system_timer.system_timer_timerB_io_limit_driver[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[2] system_timer.system_timer_timerB_io_limit_driver[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.system_timer_timerB_io_limit_driver[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.system_timer_timerB_io_limit_driver[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[14] system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14586 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2740 $abc$18544$new_n2720 $abc$18544$new_n2739 +11 1 +.names apb3Router_1.io_input_PADDR[6] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2740 +11000 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[13] system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14588 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[12] system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l379 system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14594 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14596 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[8] system_timer.system_timer_timerA_io_limit_driver[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14598 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[7] system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14600 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[6] system_timer.system_timer_timerA_io_limit_driver[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14602 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[5] system_timer.system_timer_timerA_io_limit_driver[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14604 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[4] system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14606 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[3] system_timer.system_timer_timerA_io_limit_driver[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14608 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[2] system_timer.system_timer_timerA_io_limit_driver[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14610 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.system_timer_timerA_io_limit_driver[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14612 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14614 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[14] system_timer._zz_io_limit[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14616 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2757 $abc$18544$new_n2720 $abc$18544$new_n2756 +11 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2757 +10000 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[13] system_timer._zz_io_limit[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14618 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[12] system_timer._zz_io_limit[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14620 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_3 system_timer._zz_io_limit[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14622 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l379 system_timer._zz_io_limit[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14624 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_2 system_timer._zz_io_limit[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14626 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[8] system_timer._zz_io_limit[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14628 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[7] system_timer._zz_io_limit[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14630 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[6] system_timer._zz_io_limit[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14632 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[5] system_timer._zz_io_limit[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14634 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[4] system_timer._zz_io_limit[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14636 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[3] system_timer._zz_io_limit[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14638 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[2] system_timer._zz_io_limit[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14640 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer._zz_io_limit[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14642 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 system_uartCtrl.when_BusSlaveFactory_l347 system_timer._zz_io_limit[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14644 +001 1 +011 1 +110 1 +111 1 +.names system_timer.timerA.counter[14] system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14646 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] system_timer.timerA.counter[12] $abc$18544$new_n2774 $abc$18544$new_n2773 +11111 1 +.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$new_n2774 +11 1 +.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$new_n2775 +11 1 +.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$new_n2776 +11 1 +.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$new_n2777 +11 1 +.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$new_n2778 +11 1 +.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$new_n2779 +11 1 +.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$new_n2780 +11 1 +.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$new_n2781 +11 1 +.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$new_n2782 +11 1 +.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n2783 +00 1 +.names system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerABridge_ticksEnable[1] $abc$18544$new_n2784 +000 1 +001 1 +010 1 +.names $abc$18544$new_n2789 $abc$18544$new_n2787 $abc$18544$new_n2790 system_timer.prescaler_1.counter[14] system_timer._zz_io_limit[14] $abc$18544$new_n2786 +11100 1 +11111 1 +.names $abc$18544$new_n2788 system_timer.prescaler_1.counter[4] system_timer._zz_io_limit[4] system_timer.prescaler_1.counter[12] system_timer._zz_io_limit[12] $abc$18544$new_n2787 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_timer._zz_io_limit[3] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[6] system_timer._zz_io_limit[6] $abc$18544$new_n2788 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[7] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[13] system_timer._zz_io_limit[13] $abc$18544$new_n2789 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[0] system_timer.prescaler_1.counter[0] system_timer.prescaler_1.counter[10] system_timer._zz_io_limit[10] $abc$18544$new_n2790 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer._zz_io_limit[8] system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[9] system_timer._zz_io_limit[9] $abc$18544$new_n2792 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n2801 $abc$18544$new_n2800 $abc$18544$new_n2799 $abc$18544$new_n2797 $abc$18544$new_n2796 +1111 1 +.names system_timer.timerA.counter[6] system_timer.system_timer_timerA_io_limit_driver[6] system_timer.timerA.counter[10] system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$new_n2798 $abc$18544$new_n2797 +00000 1 +00110 1 +11000 1 +11110 1 +.names system_timer.timerA.counter[12] system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$new_n2798 +01 1 +10 1 +.names system_timer.timerA.counter[1] system_timer.system_timer_timerA_io_limit_driver[1] system_timer.timerA.counter[11] system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$new_n2799 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[2] system_timer.system_timer_timerA_io_limit_driver[2] system_timer.timerA.counter[7] system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2800 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[5] system_timer.system_timer_timerA_io_limit_driver[5] system_timer.timerA.counter[13] system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$new_n2801 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[8] system_timer.system_timer_timerA_io_limit_driver[8] system_timer.timerA.counter[9] system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2803 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerA.counter[13] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$14648 +01 1 +10 1 +.names system_timer.timerA.counter[12] system_timer.timerA.counter[9] system_timer.timerA.counter[10] system_timer.timerA.counter[11] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14650 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.timerA.counter[11] system_timer.timerA.counter[9] system_timer.timerA.counter[10] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14652 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerA.counter[10] system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14654 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerA.counter[9] $abc$18544$new_n2774 $abc$18544$auto$rtlil.cc:2693:MuxGate$14656 +01 1 +10 1 +.names system_timer.timerA.counter[8] $abc$18544$new_n2775 $abc$18544$auto$rtlil.cc:2693:MuxGate$14658 +01 1 +10 1 +.names system_timer.timerA.counter[7] $abc$18544$new_n2776 $abc$18544$auto$rtlil.cc:2693:MuxGate$14660 +01 1 +10 1 +.names system_timer.timerA.counter[6] $abc$18544$new_n2777 $abc$18544$auto$rtlil.cc:2693:MuxGate$14662 +01 1 +10 1 +.names system_timer.timerA.counter[5] $abc$18544$new_n2778 $abc$18544$auto$rtlil.cc:2693:MuxGate$14664 +01 1 +10 1 +.names system_timer.timerA.counter[4] $abc$18544$new_n2779 $abc$18544$auto$rtlil.cc:2693:MuxGate$14666 +01 1 +10 1 +.names system_timer.timerA.counter[3] $abc$18544$new_n2780 $abc$18544$auto$rtlil.cc:2693:MuxGate$14668 +01 1 +10 1 +.names system_timer.timerA.counter[2] $abc$18544$new_n2781 $abc$18544$auto$rtlil.cc:2693:MuxGate$14670 +01 1 +10 1 +.names system_timer.timerA.counter[1] $abc$18544$new_n2782 $abc$18544$auto$rtlil.cc:2693:MuxGate$14672 +01 1 +10 1 +.names system_timer.timerA.counter[0] $abc$18544$new_n2783 $abc$18544$auto$rtlil.cc:2693:MuxGate$14674 +01 1 +10 1 +.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347 system_timer.interruptCtrl_1.io_masks[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14676 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2822 $abc$18544$new_n2709 $abc$18544$new_n2821 +11 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n2822 +11000 1 +.names system_timer.timerB.counter[14] system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14678 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] system_timer.timerB.counter[12] $abc$18544$new_n2825 $abc$18544$new_n2824 +11111 1 +.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$new_n2825 +11 1 +.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$new_n2826 +11 1 +.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$new_n2827 +11 1 +.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$new_n2828 +11 1 +.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$new_n2829 +11 1 +.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$new_n2830 +11 1 +.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$new_n2831 +11 1 +.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$new_n2832 +11 1 +.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$new_n2833 +11 1 +.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n2834 +00 1 +.names system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n5026 system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n2835 +000 1 +001 1 +010 1 +.names $abc$18544$new_n2842 $abc$18544$new_n2841 $abc$18544$new_n2840 $abc$18544$new_n2838 $abc$18544$new_n2837 +1111 1 +.names system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerB.counter[10] system_timer.system_timer_timerB_io_limit_driver[10] $abc$18544$new_n2839 $abc$18544$new_n2838 +00000 1 +00110 1 +11000 1 +11110 1 +.names system_timer.timerB.counter[12] system_timer.system_timer_timerB_io_limit_driver[12] $abc$18544$new_n2839 +01 1 +10 1 +.names system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerB.counter[11] system_timer.system_timer_timerB_io_limit_driver[11] $abc$18544$new_n2840 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] $abc$18544$new_n2841 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerB.counter[13] system_timer.system_timer_timerB_io_limit_driver[13] $abc$18544$new_n2842 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] $abc$18544$new_n2845 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_timer.timerB.counter[13] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$14680 +01 1 +10 1 +.names system_timer.timerB.counter[12] system_timer.timerB.counter[9] system_timer.timerB.counter[10] system_timer.timerB.counter[11] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14682 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.timerB.counter[11] system_timer.timerB.counter[9] system_timer.timerB.counter[10] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14684 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerB.counter[10] system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14686 +011 1 +100 1 +101 1 +110 1 +.names system_timer.timerB.counter[9] $abc$18544$new_n2825 $abc$18544$auto$rtlil.cc:2693:MuxGate$14688 +01 1 +10 1 +.names system_timer.timerB.counter[8] $abc$18544$new_n2826 $abc$18544$auto$rtlil.cc:2693:MuxGate$14690 +01 1 +10 1 +.names system_timer.timerB.counter[7] $abc$18544$new_n2827 $abc$18544$auto$rtlil.cc:2693:MuxGate$14692 +01 1 +10 1 +.names system_timer.timerB.counter[6] $abc$18544$new_n2828 $abc$18544$auto$rtlil.cc:2693:MuxGate$14694 +01 1 +10 1 +.names system_timer.timerB.counter[5] $abc$18544$new_n2829 $abc$18544$auto$rtlil.cc:2693:MuxGate$14696 +01 1 +10 1 +.names system_timer.timerB.counter[4] $abc$18544$new_n2830 $abc$18544$auto$rtlil.cc:2693:MuxGate$14698 +01 1 +10 1 +.names system_timer.timerB.counter[3] $abc$18544$new_n2831 $abc$18544$auto$rtlil.cc:2693:MuxGate$14700 +01 1 +10 1 +.names system_timer.timerB.counter[2] $abc$18544$new_n2832 $abc$18544$auto$rtlil.cc:2693:MuxGate$14702 +01 1 +10 1 +.names system_timer.timerB.counter[1] $abc$18544$new_n2833 $abc$18544$auto$rtlil.cc:2693:MuxGate$14704 +01 1 +10 1 +.names system_timer.timerB.counter[0] $abc$18544$new_n2834 $abc$18544$auto$rtlil.cc:2693:MuxGate$14706 +01 1 +10 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.jtag_readArea_full_shifter[33] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14708 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n2863 jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2862 +1110 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n2863 +1100 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n2864 +1110 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.jtag_readArea_full_shifter[32] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14710 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.jtag_readArea_full_shifter[31] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14712 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.jtag_readArea_full_shifter[30] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14714 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.jtag_readArea_full_shifter[29] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14716 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.jtag_readArea_full_shifter[28] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14718 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.jtag_readArea_full_shifter[27] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14720 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.jtag_readArea_full_shifter[26] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14722 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.jtag_readArea_full_shifter[25] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14724 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.jtag_readArea_full_shifter[24] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14726 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.jtag_readArea_full_shifter[23] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14728 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.jtag_readArea_full_shifter[22] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14730 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.jtag_readArea_full_shifter[21] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14732 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.jtag_readArea_full_shifter[20] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14734 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.jtag_readArea_full_shifter[19] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14736 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.jtag_readArea_full_shifter[18] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.jtag_readArea_full_shifter[17] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14740 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.jtag_readArea_full_shifter[16] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14742 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.jtag_readArea_full_shifter[15] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14744 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.jtag_readArea_full_shifter[14] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14746 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.jtag_readArea_full_shifter[13] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14748 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.jtag_readArea_full_shifter[12] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14750 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.jtag_readArea_full_shifter[11] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14752 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.jtag_readArea_full_shifter[10] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14754 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.jtag_readArea_full_shifter[9] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14756 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.jtag_readArea_full_shifter[8] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14758 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.jtag_readArea_full_shifter[7] jtagBridge_1.system_rsp_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14760 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.jtag_readArea_full_shifter[6] jtagBridge_1.system_rsp_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14762 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.jtag_readArea_full_shifter[5] jtagBridge_1.system_rsp_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14764 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.jtag_readArea_full_shifter[4] jtagBridge_1.system_rsp_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14766 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[2] jtagBridge_1.jtag_readArea_full_shifter[3] jtagBridge_1.system_rsp_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14768 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.system_rsp_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$14770 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[5] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14772 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 $abc$18544$new_n2897 +11 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.break_counter[1] $abc$18544$new_n2898 +111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] system_uartCtrl.uartCtrl_1.rx.break_counter[0] $abc$18544$new_n2900 system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.io_readBreak +1110 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2900 +0000 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 $abc$18544$auto$rtlil.cc:2693:MuxGate$14774 +0011 1 +1000 1 +1001 1 +1010 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] $abc$18544$new_n2897 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14776 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[2] $abc$18544$new_n2898 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14778 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[1] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14780 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[0] system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$14782 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[30] $abc$18544$new_n2907 jtagBridge_1.io_remote_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14784 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] $abc$18544$new_n2907 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[14] $abc$18544$new_n2908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2910 system_cpu._zz_lastStageRegFileWrite_payload_address[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2909 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2911 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2910 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] $abc$18544$new_n2911 +000 1 +010 1 +100 1 +101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ENABLE system_cpu.lastStageIsFiring $abc$18544$new_n2912 +11 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] $abc$18544$new_n2913 +000 1 +010 1 +100 1 +101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2914 +10 1 +.names system_cpu.decode_to_execute_DO_EBREAK system_cpu.execute_arbitration_isValid $abc$18544$new_n2915 +11 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[29] $abc$18544$new_n2917 jtagBridge_1.io_remote_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14786 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] $abc$18544$new_n2917 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[28] $abc$18544$new_n2919 jtagBridge_1.io_remote_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14788 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] $abc$18544$new_n2919 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[27] $abc$18544$new_n2921 jtagBridge_1.io_remote_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14790 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] $abc$18544$new_n2921 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[26] $abc$18544$new_n2923 jtagBridge_1.io_remote_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14792 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] $abc$18544$new_n2923 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[25] $abc$18544$new_n2925 jtagBridge_1.io_remote_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14794 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] $abc$18544$new_n2925 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[24] $abc$18544$new_n2927 jtagBridge_1.io_remote_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14796 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] $abc$18544$new_n2927 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[23] $abc$18544$new_n2929 jtagBridge_1.io_remote_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14798 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] $abc$18544$new_n2929 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[22] $abc$18544$new_n2931 jtagBridge_1.io_remote_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14800 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] $abc$18544$new_n2931 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[21] $abc$18544$new_n2933 jtagBridge_1.io_remote_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14802 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] $abc$18544$new_n2933 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[20] $abc$18544$new_n2935 jtagBridge_1.io_remote_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14804 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] $abc$18544$new_n2935 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[19] $abc$18544$new_n2937 jtagBridge_1.io_remote_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14806 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] $abc$18544$new_n2937 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[18] $abc$18544$new_n2939 jtagBridge_1.io_remote_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14808 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] $abc$18544$new_n2939 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[17] $abc$18544$new_n2941 jtagBridge_1.io_remote_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14810 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] $abc$18544$new_n2941 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[16] $abc$18544$new_n2943 jtagBridge_1.io_remote_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14812 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] $abc$18544$new_n2943 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[15] $abc$18544$new_n2945 jtagBridge_1.io_remote_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14814 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2946 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] $abc$18544$new_n2912 $abc$18544$new_n2945 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2913 system_cpu._zz_lastStageRegFileWrite_payload_address[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] $abc$18544$new_n2946 +001 1 +010 1 +011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[14] $abc$18544$new_n2948 jtagBridge_1.io_remote_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14816 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2949 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] $abc$18544$new_n2912 $abc$18544$new_n2948 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2949 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[13] $abc$18544$new_n2951 jtagBridge_1.io_remote_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14818 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2952 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] $abc$18544$new_n2912 $abc$18544$new_n2951 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2952 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[12] $abc$18544$new_n2954 jtagBridge_1.io_remote_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14820 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2955 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] $abc$18544$new_n2912 $abc$18544$new_n2954 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2955 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[11] $abc$18544$new_n2957 jtagBridge_1.io_remote_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14822 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2958 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] $abc$18544$new_n2912 $abc$18544$new_n2957 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2958 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[10] $abc$18544$new_n2960 jtagBridge_1.io_remote_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14824 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2961 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] $abc$18544$new_n2912 $abc$18544$new_n2960 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2961 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[9] $abc$18544$new_n2963 jtagBridge_1.io_remote_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14826 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2964 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] $abc$18544$new_n2912 $abc$18544$new_n2963 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2964 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[8] $abc$18544$new_n2966 jtagBridge_1.io_remote_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14828 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2909 $abc$18544$new_n2967 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] $abc$18544$new_n2912 $abc$18544$new_n2966 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu._zz_lastStageRegFileWrite_payload_address[12] $abc$18544$new_n2967 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[7] $abc$18544$new_n2969 jtagBridge_1.io_remote_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14830 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2910 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] $abc$18544$new_n2969 +000 1 +010 1 +110 1 +111 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[6] $abc$18544$new_n2971 jtagBridge_1.io_remote_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14832 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2972 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] $abc$18544$new_n2971 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] $abc$18544$new_n2972 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[5] $abc$18544$new_n2974 jtagBridge_1.io_remote_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14834 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2975 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] $abc$18544$new_n2974 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2976 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] $abc$18544$new_n2975 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] $abc$18544$new_n2976 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[4] $abc$18544$new_n2978 system_cpu.DebugPlugin_busReadDataReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14836 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2979 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] $abc$18544$new_n2978 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2980 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] $abc$18544$new_n2979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] $abc$18544$new_n2980 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[3] $abc$18544$new_n2982 system_cpu.DebugPlugin_busReadDataReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14838 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2983 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] $abc$18544$new_n2914 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] $abc$18544$new_n2982 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] $abc$18544$new_n2983 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[2] $abc$18544$new_n2985 system_cpu.DebugPlugin_busReadDataReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14840 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2912 $abc$18544$new_n2986 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] $abc$18544$new_n2985 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n2987 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] $abc$18544$new_n2986 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] $abc$18544$new_n2987 +000 1 +010 1 +100 1 +101 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14842 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2989 +11 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2990 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n2991 +1000 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2989 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14844 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2994 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14846 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2994 +1100 1 +.names $abc$18544$new_n2997 $abc$18544$new_n2998 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$14848 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2997 +11 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2998 +10 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2999 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14850 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n2998 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14852 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3003 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14854 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2990 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] $abc$18544$new_n3003 +1000 1 +.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$14914 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$18544$new_n2991 $abc$18544$new_n3008 $abc$18544$new_n3009 $abc$18544$new_n3005 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3007 system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3006 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3007 +000 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n3008 +10000 1 +10001 1 +10010 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n2999 $abc$18544$new_n3009 +11 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] $abc$18544$new_n3010 +100 1 +.names $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] $abc$18544$new_n2991 $abc$18544$new_n3009 $abc$18544$auto$rtlil.cc:2693:MuxGate$14916 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14918 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n3014 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3013 +100 1 +101 1 +111 1 +.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3926 $abc$18544$new_n3017 $abc$18544$new_n3014 +000 1 +001 1 +010 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] $abc$18544$new_n3016 +1100 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] $abc$18544$new_n3017 +100 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14920 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14922 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14924 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire +000 1 +001 1 +010 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3022 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$14926 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$new_n3029 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$new_n3030 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3031 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3030 $abc$18544$auto$rtlil.cc:2693:MuxGate$14928 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3031 $abc$18544$auto$rtlil.cc:2693:MuxGate$14930 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14932 +01 1 +10 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3042 apb3Router_1._zz_selIndex $abc$18544$new_n3036 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 +1110 1 +.names $abc$18544$new_n3037 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3036 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3037 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3038 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3041 $abc$18544$new_n3040 apb3Router_1._zz_selIndex +11 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[17] apb3Router_1.io_input_PADDR[18] apb3Router_1.io_input_PADDR[19] $abc$18544$new_n3040 +1000 1 +.names apb3Router_1.io_input_PADDR[16] apb3Router_1.io_input_PADDR[12] apb3Router_1.io_input_PADDR[13] apb3Router_1.io_input_PADDR[14] apb3Router_1.io_input_PADDR[15] $abc$18544$new_n3041 +10000 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3042 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$14934 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$new_n3044 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$new_n3045 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$new_n3046 +11 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3045 $abc$18544$auto$rtlil.cc:2693:MuxGate$14936 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3046 $abc$18544$auto$rtlil.cc:2693:MuxGate$14938 +01 1 +10 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14940 +01 1 +10 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14942 +001 1 +011 1 +110 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$new_n3051 +10 1 +.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3042 apb3Router_1._zz_selIndex system_apbBridge.pipelinedMemoryBusStage_rsp_valid $abc$18544$new_n3052 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names apb3Router_1.io_input_PENABLE apb3Router_1.io_input_PWRITE system_apbBridge.pipelinedMemoryBusStage_rsp_valid +10 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14944 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$14946 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$14948 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5038 $abc$18544$new_n3052 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire +000 1 +001 1 +010 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$14950 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$new_n3064 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$new_n3065 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$new_n3066 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n3065 $abc$18544$auto$rtlil.cc:2693:MuxGate$14952 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] $abc$18544$new_n3066 $abc$18544$auto$rtlil.cc:2693:MuxGate$14954 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire $abc$18544$auto$rtlil.cc:2693:MuxGate$14956 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 +10 1 +.names $abc$18544$new_n3072 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n3071 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n3072 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n3073 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$14958 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$new_n3075 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$new_n3076 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$new_n3077 +11 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n3076 $abc$18544$auto$rtlil.cc:2693:MuxGate$14960 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3077 $abc$18544$auto$rtlil.cc:2693:MuxGate$14962 +01 1 +10 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$14964 +01 1 +10 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[30] io_gpioA_write[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14966 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3040 $abc$18544$new_n2723 $abc$18544$new_n2711 $abc$18544$new_n2712 $abc$18544$new_n3082 +1111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[29] io_gpioA_write[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14968 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[28] io_gpioA_write[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14970 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[27] io_gpioA_write[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14972 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[26] io_gpioA_write[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14974 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[25] io_gpioA_write[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14976 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[24] io_gpioA_write[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14978 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[23] io_gpioA_write[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14980 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[22] io_gpioA_write[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14982 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[21] io_gpioA_write[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14984 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[20] io_gpioA_write[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14986 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[19] io_gpioA_write[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14988 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[18] io_gpioA_write[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14990 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[17] io_gpioA_write[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14992 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[16] io_gpioA_write[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14994 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[15] io_gpioA_write[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14996 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[14] io_gpioA_write[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14998 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[13] io_gpioA_write[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15000 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[12] io_gpioA_write[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15002 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_3 io_gpioA_write[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15004 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l379 io_gpioA_write[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15006 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_2 io_gpioA_write[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15008 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[8] io_gpioA_write[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15010 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[7] io_gpioA_write[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15012 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[6] io_gpioA_write[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15014 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[5] io_gpioA_write[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15016 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[4] io_gpioA_write[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15018 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[3] io_gpioA_write[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15020 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[2] io_gpioA_write[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15022 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347_1 io_gpioA_write[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15024 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 system_uartCtrl.when_BusSlaveFactory_l347 io_gpioA_write[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15026 +001 1 +011 1 +110 1 +111 1 +.names systemDebugger_1.dispatcher_counter[1] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$15028 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names systemDebugger_1.dispatcher_counter[0] jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$15030 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[65] systemDebugger_1._zz_io_mem_cmd_payload_address[66] $abc$18544$auto$rtlil.cc:2693:MuxGate$15098 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[65] $abc$18544$auto$rtlil.cc:2693:MuxGate$15100 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[63] systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$15102 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[62] systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$auto$rtlil.cc:2693:MuxGate$15104 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[61] systemDebugger_1._zz_io_mem_cmd_payload_address[62] $abc$18544$auto$rtlil.cc:2693:MuxGate$15106 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[60] systemDebugger_1._zz_io_mem_cmd_payload_address[61] $abc$18544$auto$rtlil.cc:2693:MuxGate$15108 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[59] systemDebugger_1._zz_io_mem_cmd_payload_address[60] $abc$18544$auto$rtlil.cc:2693:MuxGate$15110 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[59] $abc$18544$auto$rtlil.cc:2693:MuxGate$15112 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285_1 system_cpu.when_DebugPlugin_l288_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15114 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284_1 system_cpu.when_DebugPlugin_l285_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15116 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[55] system_cpu.when_DebugPlugin_l284_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15118 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[54] systemDebugger_1._zz_io_mem_cmd_payload_address[55] $abc$18544$auto$rtlil.cc:2693:MuxGate$15120 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[53] systemDebugger_1._zz_io_mem_cmd_payload_address[54] $abc$18544$auto$rtlil.cc:2693:MuxGate$15122 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[52] systemDebugger_1._zz_io_mem_cmd_payload_address[53] $abc$18544$auto$rtlil.cc:2693:MuxGate$15124 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[51] systemDebugger_1._zz_io_mem_cmd_payload_address[52] $abc$18544$auto$rtlil.cc:2693:MuxGate$15126 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[51] $abc$18544$auto$rtlil.cc:2693:MuxGate$15128 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l285 system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$15130 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded system_cpu.when_DebugPlugin_l284 system_cpu.when_DebugPlugin_l285 $abc$18544$auto$rtlil.cc:2693:MuxGate$15132 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[47] system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$15134 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[46] systemDebugger_1._zz_io_mem_cmd_payload_address[47] $abc$18544$auto$rtlil.cc:2693:MuxGate$15136 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[45] systemDebugger_1._zz_io_mem_cmd_payload_address[46] $abc$18544$auto$rtlil.cc:2693:MuxGate$15138 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[44] systemDebugger_1._zz_io_mem_cmd_payload_address[45] $abc$18544$auto$rtlil.cc:2693:MuxGate$15140 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[43] systemDebugger_1._zz_io_mem_cmd_payload_address[44] $abc$18544$auto$rtlil.cc:2693:MuxGate$15142 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[42] systemDebugger_1._zz_io_mem_cmd_payload_address[43] $abc$18544$auto$rtlil.cc:2693:MuxGate$15144 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[41] systemDebugger_1._zz_io_mem_cmd_payload_address[42] $abc$18544$auto$rtlil.cc:2693:MuxGate$15146 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[40] systemDebugger_1._zz_io_mem_cmd_payload_address[41] $abc$18544$auto$rtlil.cc:2693:MuxGate$15148 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[39] systemDebugger_1._zz_io_mem_cmd_payload_address[40] $abc$18544$auto$rtlil.cc:2693:MuxGate$15150 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[38] systemDebugger_1._zz_io_mem_cmd_payload_address[39] $abc$18544$auto$rtlil.cc:2693:MuxGate$15152 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[37] systemDebugger_1._zz_io_mem_cmd_payload_address[38] $abc$18544$auto$rtlil.cc:2693:MuxGate$15154 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[36] systemDebugger_1._zz_io_mem_cmd_payload_address[37] $abc$18544$auto$rtlil.cc:2693:MuxGate$15156 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[35] systemDebugger_1._zz_io_mem_cmd_payload_address[36] $abc$18544$auto$rtlil.cc:2693:MuxGate$15158 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[34] systemDebugger_1._zz_io_mem_cmd_payload_address[35] $abc$18544$auto$rtlil.cc:2693:MuxGate$15160 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[33] systemDebugger_1._zz_io_mem_cmd_payload_address[34] $abc$18544$auto$rtlil.cc:2693:MuxGate$15162 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[32] systemDebugger_1._zz_io_mem_cmd_payload_address[33] $abc$18544$auto$rtlil.cc:2693:MuxGate$15164 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[31] systemDebugger_1._zz_io_mem_cmd_payload_address[32] $abc$18544$auto$rtlil.cc:2693:MuxGate$15166 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[30] systemDebugger_1._zz_io_mem_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$15168 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[29] systemDebugger_1._zz_io_mem_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15170 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[28] systemDebugger_1._zz_io_mem_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15172 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[27] systemDebugger_1._zz_io_mem_cmd_payload_address[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15174 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[26] systemDebugger_1._zz_io_mem_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15176 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[25] systemDebugger_1._zz_io_mem_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15178 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[24] systemDebugger_1._zz_io_mem_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15180 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[23] systemDebugger_1._zz_io_mem_cmd_payload_address[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15182 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[22] systemDebugger_1._zz_io_mem_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15184 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[21] systemDebugger_1._zz_io_mem_cmd_payload_address[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15186 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[20] systemDebugger_1._zz_io_mem_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15188 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[19] systemDebugger_1._zz_io_mem_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15190 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[18] systemDebugger_1._zz_io_mem_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15192 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[17] systemDebugger_1._zz_io_mem_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15194 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[16] systemDebugger_1._zz_io_mem_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15196 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[15] systemDebugger_1._zz_io_mem_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15198 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[14] systemDebugger_1._zz_io_mem_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15200 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[13] systemDebugger_1._zz_io_mem_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15202 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[12] systemDebugger_1._zz_io_mem_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15204 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[11] systemDebugger_1._zz_io_mem_cmd_payload_address[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15206 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[10] systemDebugger_1._zz_io_mem_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15208 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[9] systemDebugger_1._zz_io_mem_cmd_payload_address[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15210 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[8] systemDebugger_1._zz_io_mem_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15212 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[7] systemDebugger_1._zz_io_mem_cmd_payload_address[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15214 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15216 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15218 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15220 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15222 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[2] systemDebugger_1._zz_io_mem_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15224 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[6] systemDebugger_1.dispatcher_header[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15230 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15232 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15234 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[3] systemDebugger_1.dispatcher_header[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15236 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15238 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[1] systemDebugger_1.dispatcher_header[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15240 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15242 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[2] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15296 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] $abc$18544$new_n3187 +1000 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[1] jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15298 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1._zz_jtag_tap_isBypass[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15300 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[31] jtagBridge_1.jtag_idcodeArea_shifter[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15302 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n3191 +11000 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[30] jtagBridge_1.jtag_idcodeArea_shifter[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15304 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[29] jtagBridge_1.jtag_idcodeArea_shifter[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15306 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[28] jtagBridge_1.jtag_idcodeArea_shifter[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15308 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[27] jtagBridge_1.jtag_idcodeArea_shifter[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15310 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[26] jtagBridge_1.jtag_idcodeArea_shifter[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15312 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[25] jtagBridge_1.jtag_idcodeArea_shifter[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15314 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[24] jtagBridge_1.jtag_idcodeArea_shifter[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15316 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[23] jtagBridge_1.jtag_idcodeArea_shifter[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15318 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[22] jtagBridge_1.jtag_idcodeArea_shifter[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15320 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[21] jtagBridge_1.jtag_idcodeArea_shifter[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15322 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[20] jtagBridge_1.jtag_idcodeArea_shifter[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15324 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[19] jtagBridge_1.jtag_idcodeArea_shifter[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15326 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[18] jtagBridge_1.jtag_idcodeArea_shifter[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15328 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[17] jtagBridge_1.jtag_idcodeArea_shifter[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15330 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[16] jtagBridge_1.jtag_idcodeArea_shifter[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15332 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[15] jtagBridge_1.jtag_idcodeArea_shifter[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15334 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[14] jtagBridge_1.jtag_idcodeArea_shifter[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15336 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[13] jtagBridge_1.jtag_idcodeArea_shifter[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15338 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[12] jtagBridge_1.jtag_idcodeArea_shifter[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15340 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[11] jtagBridge_1.jtag_idcodeArea_shifter[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15342 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[10] jtagBridge_1.jtag_idcodeArea_shifter[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15344 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[9] jtagBridge_1.jtag_idcodeArea_shifter[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15346 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[8] jtagBridge_1.jtag_idcodeArea_shifter[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15348 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[7] jtagBridge_1.jtag_idcodeArea_shifter[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15350 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[6] jtagBridge_1.jtag_idcodeArea_shifter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15352 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[5] jtagBridge_1.jtag_idcodeArea_shifter[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15354 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[4] jtagBridge_1.jtag_idcodeArea_shifter[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15356 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[3] jtagBridge_1.jtag_idcodeArea_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15358 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[2] jtagBridge_1.jtag_idcodeArea_shifter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15360 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 jtagBridge_1.jtag_idcodeArea_shifter[1] jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$auto$rtlil.cc:2693:MuxGate$15362 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[30] jtagBridge_1.system_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15364 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[29] jtagBridge_1.system_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15366 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[28] jtagBridge_1.system_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15368 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[27] jtagBridge_1.system_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15370 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[26] jtagBridge_1.system_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15372 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[25] jtagBridge_1.system_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15374 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[24] jtagBridge_1.system_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15376 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[23] jtagBridge_1.system_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15378 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[22] jtagBridge_1.system_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15380 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[21] jtagBridge_1.system_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15382 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[20] jtagBridge_1.system_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15384 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[19] jtagBridge_1.system_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15386 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[18] jtagBridge_1.system_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15388 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[17] jtagBridge_1.system_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15390 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[16] jtagBridge_1.system_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15392 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[15] jtagBridge_1.system_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15394 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[14] jtagBridge_1.system_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15396 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[13] jtagBridge_1.system_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15398 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[12] jtagBridge_1.system_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15400 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[11] jtagBridge_1.system_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15402 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[10] jtagBridge_1.system_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15404 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[9] jtagBridge_1.system_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15406 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[8] jtagBridge_1.system_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15408 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[7] jtagBridge_1.system_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15410 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[6] jtagBridge_1.system_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15412 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[5] jtagBridge_1.system_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15414 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[4] system_cpu.DebugPlugin_busReadDataReg[4] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15416 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[3] system_cpu.DebugPlugin_busReadDataReg[3] system_cpu.DebugPlugin_haltedByBreak $abc$18544$auto$rtlil.cc:2693:MuxGate$15418 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[2] system_cpu.DebugPlugin_busReadDataReg[2] system_cpu.DebugPlugin_isPipBusy $abc$18544$auto$rtlil.cc:2693:MuxGate$15420 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[1] system_cpu.DebugPlugin_busReadDataReg[1] system_cpu.DebugPlugin_haltIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15422 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names jtagBridge_1.io_remote_rsp_fire system_cpu._zz_when_DebugPlugin_l257 jtagBridge_1.system_rsp_payload_data[0] system_cpu.DebugPlugin_busReadDataReg[0] system_cpu.DebugPlugin_resetIt $abc$18544$auto$rtlil.cc:2693:MuxGate$15424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15620 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3258 $abc$18544$new_n3255 $abc$18544$new_n3254 +11 1 +.names $abc$18544$new_n2915 $abc$18544$new_n3256 $abc$18544$new_n3255 +00 1 +.names system_cpu.execute_to_memory_MEMORY_ENABLE system_cpu.memory_arbitration_isValid system_cpu.execute_to_memory_MEMORY_STORE $abc$18544$new_n3257 system_mainBusArbiter.rspTarget $abc$18544$new_n3256 +11000 1 +11010 1 +11011 1 +.names system_ram._zz_io_bus_rsp_valid system_apbBridge.io_pipelinedMemoryBus_rsp_valid system_mainBusArbiter.rspPending system_mainBusDecoder_logic_rspNoHit $abc$18544$new_n3257 +0000 1 +0001 1 +0010 1 +.names system_cpu.execute_arbitration_isValid $abc$18544$new_n3259 system_cpu._zz_execute_SHIFT_CTRL[0] system_cpu._zz_execute_SHIFT_CTRL[1] $abc$18544$new_n3258 +1001 1 +1010 1 +1011 1 +.names system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3259 +00000 1 +.names $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3260 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] $abc$18544$new_n3261 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3261 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15622 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3254 $abc$18544$new_n3264 system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15624 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.execute_LightShifterPlugin_amplitudeReg[1] $abc$18544$new_n3264 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$18544$new_n3254 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[0] system_cpu.decode_to_execute_SRC2[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15626 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15752 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3267 +100 1 +110 1 +111 1 +.names $abc$18544$new_n3269 system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3268 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3308 $abc$18544$new_n3270 $abc$18544$new_n3317 $abc$18544$new_n3269 +101 1 +110 1 +111 1 +.names $abc$18544$new_n5050 $abc$18544$new_n3307 $abc$18544$new_n5041 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$new_n3270 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3273 system_cpu.execute_to_memory_INSTRUCTION[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3272 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n3274 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.execute_to_memory_INSTRUCTION[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3273 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n3275 system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.execute_to_memory_INSTRUCTION[7] $abc$18544$new_n3274 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.memory_arbitration_isValid $abc$18544$new_n3275 +11 1 +.names system_cpu._zz_lastStageRegFileWrite_valid system_cpu.lastStageIsFiring system_cpu.HazardSimplePlugin_writeBackWrites_valid +11 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n3288 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$18544$new_n3297 $abc$18544$new_n3292 $abc$18544$new_n3294 $abc$18544$new_n3295 $abc$18544$new_n3291 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3293 system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3292 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n3293 +00 1 +11 1 +.names $abc$18544$new_n3275 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.execute_to_memory_INSTRUCTION[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.execute_to_memory_INSTRUCTION[11] $abc$18544$new_n3294 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n3296 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu.execute_to_memory_INSTRUCTION[10] $abc$18544$new_n3295 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.execute_to_memory_INSTRUCTION[9] $abc$18544$new_n3296 +00 1 +11 1 +.names system_cpu.HazardSimplePlugin_writeBackBuffer_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n3297 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n3299 +100 1 +111 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] $abc$18544$new_n3300 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n3304 +1100 1 +1111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n3306 +10 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n3307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3315 $abc$18544$new_n3309 system_cpu.lastStageIsFiring system_cpu._zz_writeBack_ENV_CTRL $abc$18544$new_n3308 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3313 $abc$18544$new_n3255 $abc$18544$new_n3258 $abc$18544$new_n3310 $abc$18544$new_n3309 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3312 $abc$18544$new_n3311 $abc$18544$new_n3310 +11 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[1] system_cpu.execute_LightShifterPlugin_amplitudeReg[2] system_cpu.decode_to_execute_SRC2[1] system_cpu.decode_to_execute_SRC2[2] $abc$18544$new_n3311 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n3312 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names system_cpu.execute_arbitration_isValid system_cpu.decode_to_execute_IS_CSR $abc$18544$new_n3314 system_cpu.decode_to_execute_MEMORY_ENABLE system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3313 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11100 1 +11101 1 +11110 1 +.names system_cpu.lastStageIsFiring system_cpu.memory_arbitration_isValid $abc$18544$new_n3314 +00 1 +.names $abc$18544$new_n3316 system_cpu._zz_memory_ENV_CTRL system_cpu.memory_arbitration_isValid system_cpu._zz_execute_ENV_CTRL system_cpu.execute_arbitration_isValid $abc$18544$new_n3315 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu.CsrPlugin_interrupt_valid system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_stepIt $abc$18544$new_n3317 $abc$18544$new_n3316 +1000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_valid system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3317 +000 1 +001 1 +011 1 +.names $abc$18544$new_n3320 $abc$18544$new_n3319 $abc$18544$new_n3318 +10 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$18544$new_n3257 system_mainBusArbiter.rspTarget $abc$18544$new_n3319 +001 1 +010 1 +011 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] $abc$18544$new_n3320 +000 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15754 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15756 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[27] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15758 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[26] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15760 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[25] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15762 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[24] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15764 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[23] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15766 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[22] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15768 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[21] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15770 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[20] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15772 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15774 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[18] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15776 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15778 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15780 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15782 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15784 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[13] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15786 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[12] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15788 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[11] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15790 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[10] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15792 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[9] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15794 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[8] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15796 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[7] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15798 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[6] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15800 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[5] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15802 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[4] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15804 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[3] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15806 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15808 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[62] $abc$18544$new_n3350 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15928 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] $abc$18544$new_n3350 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[30] system_ram._zz_ram_port0[30] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] $abc$18544$new_n3352 +000 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[61] $abc$18544$new_n3354 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] $abc$18544$new_n3354 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[29] system_ram._zz_ram_port0[29] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[60] $abc$18544$new_n3357 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15932 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] $abc$18544$new_n3357 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[28] system_ram._zz_ram_port0[28] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[59] $abc$18544$new_n3360 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15934 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] $abc$18544$new_n3360 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[27] system_ram._zz_ram_port0[27] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 system_cpu.when_DebugPlugin_l288_1 $abc$18544$new_n3363 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15936 +00100 1 +00101 1 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system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] $abc$18544$new_n3366 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[25] system_ram._zz_ram_port0[25] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[46] $abc$18544$new_n3369 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy 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system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] $abc$18544$new_n3372 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[13] system_ram._zz_ram_port0[13] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[44] $abc$18544$new_n3375 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$auto$rtlil.cc:2693:MuxGate$15944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] $abc$18544$new_n3375 +000 1 +001 1 +100 1 +110 1 +.names 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system_cpu._zz_execute_SrcPlugin_addSub_2[3] $abc$18544$new_n3423 $abc$18544$new_n3655 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3654 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$18544$new_n3425 system_cpu._zz_execute_SrcPlugin_addSub_2[2] $abc$18544$new_n3424 $abc$18544$new_n3655 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n3258 system_cpu.decode_to_execute_IS_CSR system_cpu.execute_arbitration_isValid $abc$18544$new_n3657 $abc$18544$new_n3656 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names $abc$18544$new_n3658 system_cpu.execute_CsrPlugin_csr_772 system_cpu.CsrPlugin_mie_MSIE system_cpu.execute_CsrPlugin_csr_768 system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n3657 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names system_cpu.execute_CsrPlugin_csr_834 system_cpu.CsrPlugin_mcause_exceptionCode[3] system_cpu.CsrPlugin_mip_MSIP system_cpu.execute_CsrPlugin_csr_836 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$abc$18544$new_n3666 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$18544$new_n3470 system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3651 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n3667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n3255 $abc$18544$new_n3669 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] $abc$18544$new_n3258 $abc$18544$new_n3673 $abc$18544$auto$rtlil.cc:2693:MuxGate$16030 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names $abc$18544$new_n3666 $abc$18544$new_n3473 $abc$18544$new_n3466 $abc$18544$new_n3670 $abc$18544$new_n3672 $abc$18544$new_n3669 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3671 system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n3670 +010 1 +011 1 +101 1 +111 1 +.names system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] system_cpu.decode_to_execute_SRC_USE_SUB_LESS system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] $abc$18544$new_n3671 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n3672 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$18544$new_n3470 system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3674 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] system_cpu._zz_execute_SrcPlugin_addSub_2[2] $abc$18544$new_n3673 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] system_cpu._zz_execute_SrcPlugin_addSub_2[0] $abc$18544$new_n3674 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n3255 $abc$18544$new_n3676 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] $abc$18544$new_n3686 $abc$18544$new_n3258 $abc$18544$auto$rtlil.cc:2693:MuxGate$16032 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3258 system_cpu.decode_to_execute_IS_CSR system_cpu.execute_arbitration_isValid $abc$18544$new_n3677 system_cpu.execute_CsrPlugin_csr_834 $abc$18544$new_n3676 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01101 1 +01111 1 +.names $abc$18544$new_n3467 $abc$18544$new_n3683 $abc$18544$new_n3685 $abc$18544$new_n3678 $abc$18544$new_n3681 $abc$18544$new_n3677 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3680 $abc$18544$new_n3682 $abc$18544$new_n3679 system_cpu._zz_execute_SrcPlugin_addSub_2[31] $abc$18544$new_n3678 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$18544$new_n3410 $abc$18544$new_n3464 system_cpu._zz_execute_SrcPlugin_addSub_2[29] $abc$18544$new_n3463 $abc$18544$new_n3462 $abc$18544$new_n3679 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names system_cpu.decode_to_execute_SRC_USE_SUB_LESS $abc$18544$new_n3681 $abc$18544$new_n3680 +01 1 +10 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[31] system_cpu.decode_to_execute_SRC2[31] $abc$18544$new_n3681 +00 1 +11 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[30] system_cpu.decode_to_execute_SRC_USE_SUB_LESS system_cpu.decode_to_execute_SRC2[30] $abc$18544$new_n3682 +101 1 +110 1 +.names $abc$18544$new_n3473 system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3684 $abc$18544$new_n3683 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[0] system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n3684 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1100 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[31] system_cpu.decode_to_execute_SRC_LESS_UNSIGNED system_cpu.decode_to_execute_SRC2[31] $abc$18544$new_n3685 +000 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3470 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n3686 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[30] $abc$18544$new_n3724 $abc$18544$new_n3688 $abc$18544$new_n3721 $abc$18544$auto$rtlil.cc:2693:MuxGate$16034 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[29] $abc$18544$new_n3689 $abc$18544$new_n3688 +111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[27] $abc$18544$new_n3690 $abc$18544$new_n3689 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[23] system_cpu.IBusSimplePlugin_cmd_payload_pc[24] system_cpu.IBusSimplePlugin_cmd_payload_pc[25] system_cpu.IBusSimplePlugin_cmd_payload_pc[26] $abc$18544$new_n3691 $abc$18544$new_n3690 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_cpu.IBusSimplePlugin_cmd_payload_pc[20] system_cpu.IBusSimplePlugin_cmd_payload_pc[21] system_cpu.IBusSimplePlugin_cmd_payload_pc[22] $abc$18544$new_n3692 $abc$18544$new_n3691 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[18] $abc$18544$new_n3693 $abc$18544$new_n3692 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] $abc$18544$new_n3694 $abc$18544$new_n3693 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[13] $abc$18544$new_n3695 $abc$18544$new_n3694 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[12] $abc$18544$new_n3696 $abc$18544$new_n3695 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[11] $abc$18544$new_n3697 $abc$18544$new_n3696 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[10] $abc$18544$new_n3698 $abc$18544$new_n3697 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[9] $abc$18544$new_n3699 $abc$18544$new_n3698 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[8] $abc$18544$new_n3700 $abc$18544$new_n3699 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[7] $abc$18544$new_n3701 $abc$18544$new_n3700 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[6] $abc$18544$new_n3702 $abc$18544$new_n3701 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[5] $abc$18544$new_n3703 $abc$18544$new_n3702 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[4] $abc$18544$new_n3704 $abc$18544$new_n3703 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[3] $abc$18544$new_n3705 $abc$18544$new_n3704 +11 1 +.names system_cpu.IBusSimplePlugin_fetchPc_inc system_cpu.IBusSimplePlugin_cmd_payload_pc[2] $abc$18544$new_n3705 +11 1 +.names system_cpu.IBusSimplePlugin_fetchPc_booted $abc$18544$new_n3707 $abc$18544$new_n3706 +10 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3708 $abc$18544$new_n3707 +10 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3709 $abc$18544$new_n3710 system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3708 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_pending_value[1] system_cpu.IBusSimplePlugin_pending_value[0] system_cpu.IBusSimplePlugin_pending_value[2] $abc$18544$new_n3709 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3720 $abc$18544$new_n3711 io_apb_decoder.io_input_PSEL $abc$18544$new_n3710 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3719 $abc$18544$new_n3718 $abc$18544$new_n3716 $abc$18544$new_n3717 $abc$18544$new_n3712 $abc$18544$new_n3711 +11100 1 +.names $abc$18544$new_n3713 system_mainBusArbiter.io_dBus_cmd_payload_address[31] $abc$18544$new_n3715 system_mainBusArbiter.io_dBus_cmd_payload_address[21] system_mainBusArbiter.io_dBus_cmd_payload_address[22] $abc$18544$new_n3712 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[31] $abc$18544$new_n3714 system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3713 +1100 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[22] system_cpu.IBusSimplePlugin_cmd_payload_pc[23] system_cpu.IBusSimplePlugin_cmd_payload_pc[26] system_cpu.IBusSimplePlugin_cmd_payload_pc[27] $abc$18544$new_n3714 +0000 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_address[23] system_mainBusArbiter.io_dBus_cmd_payload_address[26] system_mainBusArbiter.io_dBus_cmd_payload_address[27] $abc$18544$new_n3715 +1000 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[24] system_cpu.IBusSimplePlugin_cmd_payload_pc[25] system_mainBusArbiter.io_dBus_cmd_payload_address[24] system_mainBusArbiter.io_dBus_cmd_payload_address[25] $abc$18544$new_n3716 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_mainBusArbiter.io_dBus_cmd_payload_address[29] $abc$18544$new_n3717 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[20] system_mainBusArbiter.io_dBus_cmd_payload_address[20] $abc$18544$new_n3718 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_mainBusArbiter.io_dBus_cmd_payload_address[28] system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$new_n3719 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names system_mainBusArbiter.rspPending $abc$18544$new_n3257 $abc$18544$new_n3720 +11 1 +.names $abc$18544$new_n3722 system_cpu.memory_arbitration_isValid system_cpu.execute_to_memory_BRANCH_DO $abc$18544$new_n3721 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3723 system_cpu.lastStageIsFiring system_cpu._zz_writeBack_ENV_CTRL $abc$18544$new_n3722 +000 1 +001 1 +010 1 +.names system_cpu.CsrPlugin_interrupt_valid system_cpu.CsrPlugin_pipelineLiberator_done system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_stepIt $abc$18544$new_n3723 +1100 1 +.names $abc$18544$new_n3721 system_cpu.BranchPlugin_jumpInterface_payload[30] $abc$18544$new_n3722 system_cpu.CsrPlugin_mepc[30] $abc$18544$new_n3725 $abc$18544$new_n3724 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu._zz_writeBack_ENV_CTRL system_cpu.lastStageIsFiring system_cpu._zz_lastStageRegFileWrite_payload_address[28] system_cpu._zz_lastStageRegFileWrite_payload_address[29] $abc$18544$new_n3725 +1111 1 +.names $abc$18544$new_n3706 $abc$18544$new_n3721 system_cpu.IBusSimplePlugin_cmd_payload_pc[29] $abc$18544$new_n3727 $abc$18544$new_n3728 $abc$18544$auto$rtlil.cc:2693:MuxGate$16036 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_cmd_payload_pc[28] $abc$18544$new_n3689 $abc$18544$new_n3727 +011 1 +100 1 +101 1 +110 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[29] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[29] $abc$18544$new_n3728 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[28] $abc$18544$new_n3689 $abc$18544$new_n3730 $abc$18544$auto$rtlil.cc:2693:MuxGate$16038 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[28] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[28] $abc$18544$new_n3730 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[27] $abc$18544$new_n3690 $abc$18544$new_n3732 $abc$18544$auto$rtlil.cc:2693:MuxGate$16040 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[27] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[27] $abc$18544$new_n3732 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[26] $abc$18544$new_n3734 $abc$18544$new_n3737 $abc$18544$auto$rtlil.cc:2693:MuxGate$16042 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[25] $abc$18544$new_n3735 $abc$18544$new_n3734 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[24] $abc$18544$new_n3736 $abc$18544$new_n3735 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[23] $abc$18544$new_n3691 $abc$18544$new_n3736 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[26] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[26] $abc$18544$new_n3737 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[25] $abc$18544$new_n3735 $abc$18544$new_n3739 $abc$18544$auto$rtlil.cc:2693:MuxGate$16044 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[25] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[25] $abc$18544$new_n3739 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[24] $abc$18544$new_n3736 $abc$18544$new_n3741 $abc$18544$auto$rtlil.cc:2693:MuxGate$16046 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[24] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[24] $abc$18544$new_n3741 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[23] $abc$18544$new_n3691 $abc$18544$new_n3743 $abc$18544$auto$rtlil.cc:2693:MuxGate$16048 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[23] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[23] $abc$18544$new_n3743 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[22] $abc$18544$new_n3745 $abc$18544$new_n3748 $abc$18544$auto$rtlil.cc:2693:MuxGate$16050 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3746 $abc$18544$new_n3745 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[20] $abc$18544$new_n3747 $abc$18544$new_n3746 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[19] $abc$18544$new_n3692 $abc$18544$new_n3747 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[22] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[22] $abc$18544$new_n3748 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[21] $abc$18544$new_n3746 $abc$18544$new_n3750 $abc$18544$auto$rtlil.cc:2693:MuxGate$16052 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[21] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[21] $abc$18544$new_n3750 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[20] $abc$18544$new_n3747 $abc$18544$new_n3752 $abc$18544$auto$rtlil.cc:2693:MuxGate$16054 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[20] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[20] $abc$18544$new_n3752 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[19] $abc$18544$new_n3692 $abc$18544$new_n3754 $abc$18544$auto$rtlil.cc:2693:MuxGate$16056 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[19] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[19] $abc$18544$new_n3754 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[18] $abc$18544$new_n3693 $abc$18544$new_n3756 $abc$18544$auto$rtlil.cc:2693:MuxGate$16058 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[18] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[18] $abc$18544$new_n3756 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[17] $abc$18544$new_n3758 $abc$18544$new_n3761 $abc$18544$auto$rtlil.cc:2693:MuxGate$16060 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[16] $abc$18544$new_n3759 $abc$18544$new_n3758 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[15] $abc$18544$new_n3760 $abc$18544$new_n3759 +11 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[14] $abc$18544$new_n3694 $abc$18544$new_n3760 +11 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[17] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[17] $abc$18544$new_n3761 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[16] $abc$18544$new_n3759 $abc$18544$new_n3763 $abc$18544$auto$rtlil.cc:2693:MuxGate$16062 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[16] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[16] $abc$18544$new_n3763 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[15] $abc$18544$new_n3760 $abc$18544$new_n3765 $abc$18544$auto$rtlil.cc:2693:MuxGate$16064 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[15] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[15] $abc$18544$new_n3765 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[14] $abc$18544$new_n3694 $abc$18544$new_n3767 $abc$18544$auto$rtlil.cc:2693:MuxGate$16066 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[14] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[14] $abc$18544$new_n3767 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[13] $abc$18544$new_n3695 $abc$18544$new_n3769 $abc$18544$auto$rtlil.cc:2693:MuxGate$16068 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[13] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[13] $abc$18544$new_n3769 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[12] $abc$18544$new_n3696 $abc$18544$new_n3771 $abc$18544$auto$rtlil.cc:2693:MuxGate$16070 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[12] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[12] $abc$18544$new_n3771 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[11] $abc$18544$new_n3697 $abc$18544$new_n3773 $abc$18544$auto$rtlil.cc:2693:MuxGate$16072 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[11] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[11] $abc$18544$new_n3773 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[10] $abc$18544$new_n3698 $abc$18544$new_n3775 $abc$18544$auto$rtlil.cc:2693:MuxGate$16074 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[10] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[10] $abc$18544$new_n3775 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[9] $abc$18544$new_n3699 $abc$18544$new_n3777 $abc$18544$auto$rtlil.cc:2693:MuxGate$16076 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[9] $abc$18544$new_n3777 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[8] $abc$18544$new_n3700 $abc$18544$new_n3779 $abc$18544$auto$rtlil.cc:2693:MuxGate$16078 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[8] $abc$18544$new_n3779 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[7] $abc$18544$new_n3701 $abc$18544$new_n3781 $abc$18544$auto$rtlil.cc:2693:MuxGate$16080 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[7] $abc$18544$new_n3781 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[6] $abc$18544$new_n3702 $abc$18544$new_n3783 $abc$18544$auto$rtlil.cc:2693:MuxGate$16082 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[6] $abc$18544$new_n3783 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[5] $abc$18544$new_n3703 $abc$18544$new_n3785 $abc$18544$auto$rtlil.cc:2693:MuxGate$16084 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[5] $abc$18544$new_n3785 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[4] $abc$18544$new_n3704 $abc$18544$new_n3787 $abc$18544$auto$rtlil.cc:2693:MuxGate$16086 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[4] $abc$18544$new_n3787 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[3] $abc$18544$new_n3705 $abc$18544$new_n3789 $abc$18544$auto$rtlil.cc:2693:MuxGate$16088 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[3] $abc$18544$new_n3789 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3791 $abc$18544$auto$rtlil.cc:2693:MuxGate$16090 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$new_n3722 $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[2] $abc$18544$new_n3791 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.CsrPlugin_mepc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16092 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.CsrPlugin_mepc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16094 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.CsrPlugin_mepc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16096 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.CsrPlugin_mepc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16098 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.CsrPlugin_mepc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16100 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.CsrPlugin_mepc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16102 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.CsrPlugin_mepc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16104 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.CsrPlugin_mepc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16106 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.CsrPlugin_mepc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16108 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.CsrPlugin_mepc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16110 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.CsrPlugin_mepc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16112 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.CsrPlugin_mepc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16114 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.CsrPlugin_mepc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16116 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.CsrPlugin_mepc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16118 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.CsrPlugin_mepc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16120 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.CsrPlugin_mepc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16122 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.CsrPlugin_mepc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16124 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.CsrPlugin_mepc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16126 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.CsrPlugin_mepc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16128 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.CsrPlugin_mepc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16130 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.CsrPlugin_mepc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16132 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.CsrPlugin_mepc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16134 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.CsrPlugin_mepc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16136 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.CsrPlugin_mepc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16138 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.CsrPlugin_mepc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16140 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.CsrPlugin_mepc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16142 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.CsrPlugin_mepc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16144 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.CsrPlugin_mepc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16146 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.CsrPlugin_mepc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16148 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n3822 system_cpu.DebugPlugin_busReadDataReg[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16152 +0001 1 +0011 1 +1000 1 +1001 1 +.names $abc$18544$new_n2912 $abc$18544$new_n3823 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] $abc$18544$new_n3822 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n3824 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] $abc$18544$new_n3823 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] $abc$18544$new_n3824 +000 1 +010 1 +100 1 +101 1 +.names jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16156 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$18544$new_n3827 $abc$18544$new_n2864 $abc$18544$new_n3826 +00 1 +.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] $abc$18544$new_n3827 +1000 1 +.names jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[3] $abc$18544$new_n3828 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names jtagBridge_1.jtag_tap_instructionShift[2] $abc$18544$new_n3826 jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3828 $abc$18544$auto$rtlil.cc:2693:MuxGate$16160 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names jtagBridge_1.jtag_tap_instructionShift[1] $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_tdoIr $abc$18544$auto$rtlil.cc:2693:MuxGate$16164 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16166 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3269 $abc$18544$new_n3833 $abc$18544$new_n3832 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n3834 $abc$18544$new_n3833 +111 1 +.names systemDebugger_1.dispatcher_dataLoaded $abc$18544$new_n3835 systemDebugger_1.dispatcher_header[0] systemDebugger_1.dispatcher_header[1] $abc$18544$new_n3834 +1100 1 +.names $abc$18544$new_n3836 systemDebugger_1.dispatcher_header[4] systemDebugger_1.dispatcher_header[5] systemDebugger_1.dispatcher_header[7] systemDebugger_1.dispatcher_header[6] $abc$18544$new_n3835 +10000 1 +.names systemDebugger_1.dispatcher_header[2] systemDebugger_1.dispatcher_header[3] $abc$18544$new_n3836 +00 1 +.names systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n3838 $abc$18544$new_n3837 +11 1 +.names systemDebugger_1._zz_io_mem_cmd_payload_address[3] systemDebugger_1._zz_io_mem_cmd_payload_address[4] systemDebugger_1._zz_io_mem_cmd_payload_address[5] systemDebugger_1._zz_io_mem_cmd_payload_address[6] systemDebugger_1._zz_io_mem_cmd_payload_address[7] $abc$18544$new_n3838 +00000 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[0] $abc$18544$new_n3832 system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16168 +010 1 +100 1 +101 1 +111 1 +.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 resetCtrl_mainClkResetUnbuffered +00 1 +01 1 +10 1 +.names resetCtrl_systemClkResetCounter[4] $abc$18544$new_n3842 $abc$18544$new_n3841 +11 1 +.names resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] resetCtrl_systemClkResetCounter[3] $abc$18544$new_n3842 +1111 1 +.names $abc$18544$new_n3842 resetCtrl_systemClkResetCounter[4] resetCtrl_systemClkResetCounter[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16228 +010 1 +011 1 +100 1 +101 1 +111 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[3] resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] resetCtrl_systemClkResetCounter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16230 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[2] resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16232 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names resetCtrl_mainClkResetUnbuffered resetCtrl_systemClkResetCounter[0] resetCtrl_systemClkResetCounter[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16234 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +.names resetCtrl_systemClkResetCounter[0] resetCtrl_mainClkResetUnbuffered $abc$18544$auto$rtlil.cc:2693:MuxGate$16236 +00 1 +01 1 +10 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16238 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$18544$new_n3320 $abc$18544$new_n3850 $abc$18544$new_n3849 +111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3318 $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3850 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3852 $abc$18544$new_n3851 +10 1 +.names $abc$18544$new_n3314 $abc$18544$new_n2915 $abc$18544$new_n3852 +11 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16240 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16242 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16244 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16246 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16248 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[24] system_ram._zz_ram_port0[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16250 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[23] system_ram._zz_ram_port0[23] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16252 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[22] system_ram._zz_ram_port0[22] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16254 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[21] system_ram._zz_ram_port0[21] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16256 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[20] system_ram._zz_ram_port0[20] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16258 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[19] system_ram._zz_ram_port0[19] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16260 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[18] system_ram._zz_ram_port0[18] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16262 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[17] system_ram._zz_ram_port0[17] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16264 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[16] system_ram._zz_ram_port0[16] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16266 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[15] system_ram._zz_ram_port0[15] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16268 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16270 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16272 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16274 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16276 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16278 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16280 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16282 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16284 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16286 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16288 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16290 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16292 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16294 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[30] io_gpioA_writeEnable[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16324 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3893 $abc$18544$new_n3040 $abc$18544$new_n2711 $abc$18544$new_n2712 $abc$18544$new_n3892 +1111 1 +.names apb3Router_1.io_input_PADDR[3] apb3Router_1.io_input_PADDR[1] apb3Router_1.io_input_PADDR[2] apb3Router_1.io_input_PADDR[0] $abc$18544$new_n3893 +1000 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[29] io_gpioA_writeEnable[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16326 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[28] io_gpioA_writeEnable[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16328 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[27] io_gpioA_writeEnable[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16330 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[26] io_gpioA_writeEnable[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16332 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[25] io_gpioA_writeEnable[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16334 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[24] io_gpioA_writeEnable[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16336 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[23] io_gpioA_writeEnable[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16338 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[22] io_gpioA_writeEnable[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16340 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[21] io_gpioA_writeEnable[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16342 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[20] io_gpioA_writeEnable[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16344 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[19] io_gpioA_writeEnable[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16346 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[18] io_gpioA_writeEnable[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16348 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[17] io_gpioA_writeEnable[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16350 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[16] io_gpioA_writeEnable[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16352 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[15] io_gpioA_writeEnable[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16354 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[14] io_gpioA_writeEnable[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16356 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[13] io_gpioA_writeEnable[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16358 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[12] io_gpioA_writeEnable[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16360 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_3 io_gpioA_writeEnable[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16362 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l379 io_gpioA_writeEnable[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16364 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_2 io_gpioA_writeEnable[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16366 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[8] io_gpioA_writeEnable[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16368 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[7] io_gpioA_writeEnable[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16370 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[6] io_gpioA_writeEnable[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16372 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[5] io_gpioA_writeEnable[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16374 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[4] io_gpioA_writeEnable[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16376 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[3] io_gpioA_writeEnable[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16378 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[2] io_gpioA_writeEnable[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16380 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347_1 io_gpioA_writeEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16382 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3892 system_uartCtrl.when_BusSlaveFactory_l347 io_gpioA_writeEnable[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16384 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3926 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$new_n3928 $abc$18544$auto$rtlil.cc:2693:MuxGate$16512 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3016 $abc$18544$new_n3927 $abc$18544$new_n3926 +11 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n3017 $abc$18544$new_n3927 +00000 1 +00010 1 +00100 1 +01000 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +11101 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$new_n3928 +100 1 +.names $abc$18544$new_n3926 $abc$18544$new_n3022 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16514 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[2] system_cpu.CsrPlugin_mcause_exceptionCode[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16516 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3720 $abc$18544$new_n3932 $abc$18544$new_n3934 $abc$18544$auto$rtlil.cc:2693:MuxGate$16518 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3933 $abc$18544$new_n3711 io_apb_decoder.io_input_PSEL $abc$18544$new_n3932 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3720 system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3709 $abc$18544$new_n3933 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names system_mainBusArbiter.io_dBus_cmd_payload_wr system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3934 +11 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3710 $abc$18544$new_n3936 $abc$18544$auto$rtlil.cc:2693:MuxGate$16520 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.execute_arbitration_isValid $abc$18544$new_n3255 $abc$18544$new_n3851 $abc$18544$new_n3936 +1111 1 +.names $abc$18544$new_n3711 $abc$18544$new_n3933 system_mainBusDecoder_logic_rspSourceId io_apb_decoder.io_input_PSEL $abc$18544$auto$rtlil.cc:2693:MuxGate$16522 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3926 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16532 +010 1 +011 1 +101 1 +.names $abc$18544$auto$rtlil.cc:2582:Mux$3924 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3005 $abc$18544$auto$rtlil.cc:2693:MuxGate$16534 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3005 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 $abc$18544$auto$rtlil.cc:2582:Mux$3924 +1100 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$new_n3941 +11010 1 +11100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[6] $abc$18544$new_n3943 system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$auto$rtlil.cc:2693:MuxGate$16536 +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.rx.break_counter[3] system_uartCtrl.uartCtrl_1.rx.break_counter[4] system_uartCtrl.uartCtrl_1.rx.break_counter[5] $abc$18544$new_n2897 $abc$18544$new_n3943 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16538 +010 1 +011 1 +101 1 +111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16540 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n2997 $abc$18544$new_n2989 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] $abc$18544$new_n2999 $abc$18544$auto$rtlil.cc:2693:MuxGate$16542 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$18544$new_n3051 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16544 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5038 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n3052 $abc$18544$auto$rtlil.cc:2693:MuxGate$16546 +000 1 +001 1 +010 1 +011 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3064 $abc$18544$auto$rtlil.cc:2693:MuxGate$16548 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3075 $abc$18544$auto$rtlil.cc:2693:MuxGate$16550 +011 1 +100 1 +101 1 +110 1 +.names $abc$18544$new_n3013 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n5035 $abc$18544$new_n3014 $abc$18544$new_n3022 $abc$18544$auto$rtlil.cc:2693:MuxGate$16554 +000 1 +001 1 +010 1 +011 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n3029 $abc$18544$auto$rtlil.cc:2693:MuxGate$16556 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n3044 $abc$18544$auto$rtlil.cc:2693:MuxGate$16558 +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.bridge_misc_readOverflowError system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid $abc$18544$new_n3071 $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16560 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3958 apb3Router_1._zz_selIndex $abc$18544$new_n3957 +111 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 $abc$18544$new_n3958 +11 1 +.names system_uartCtrl.bridge_misc_readError $abc$18544$new_n3957 $abc$18544$new_n2991 $abc$18544$new_n3960 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$auto$rtlil.cc:2693:MuxGate$16562 +00100 1 +00101 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$18544$new_n3941 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n3960 +000 1 +001 1 +011 1 +.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347_1 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2712 $abc$18544$new_n3963 apb3Router_1._zz_selIndex $abc$18544$new_n3962 +111 1 +.names $abc$18544$new_n2723 apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3963 +10 1 +.names $abc$18544$new_n3962 system_uartCtrl.when_BusSlaveFactory_l347 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16566 +001 1 +011 1 +110 1 +111 1 +.names system_timer.timerB.io_clear $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n2835 $abc$18544$auto$rtlil.cc:2693:MuxGate$16568 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n2709 system_timer.timerBBridge_clearsEnable $abc$18544$new_n3967 $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.timerB.io_clear +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3968 system_timer.timerB.inhibitFull $abc$18544$new_n3967 +10 1 +.names $abc$18544$new_n5032 $abc$18544$new_n2835 $abc$18544$new_n3968 +10 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n3893 apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3969 +11100 1 +.names system_timer.timerA.io_clear $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n2784 $abc$18544$auto$rtlil.cc:2693:MuxGate$16570 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names system_timer.timerABridge_clearsEnable $abc$18544$new_n3972 $abc$18544$new_n2709 $abc$18544$new_n3974 system_timer.timerA.io_clear +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3973 system_timer.timerA.inhibitFull $abc$18544$new_n3972 +10 1 +.names $abc$18544$new_n5029 $abc$18544$new_n2784 $abc$18544$new_n3973 +10 1 +.names $abc$18544$new_n3975 $abc$18544$new_n2723 $abc$18544$new_n3893 $abc$18544$new_n3974 +101 1 +110 1 +111 1 +.names apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[4] apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n3975 +1000 1 +.names $abc$18544$new_n2821 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2708 apb3Router_1.io_input_PWDATA[16] system_timer.timerBBridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2708 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerBBridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2716 apb3Router_1.io_input_PWDATA[16] system_timer.timerABridge_clearsEnable $abc$18544$auto$rtlil.cc:2693:MuxGate$16578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2716 system_uartCtrl.when_BusSlaveFactory_l347_1 system_timer.timerABridge_ticksEnable[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2719 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerB_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2739 apb3Router_1.io_input_PWDATA[15] system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n2756 apb3Router_1.io_input_PWDATA[15] system_timer._zz_io_limit[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16586 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3932 system_mainBusArbiter.rspTarget system_mainBusArbiter.io_dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16588 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3892 apb3Router_1.io_input_PWDATA[31] io_gpioA_writeEnable[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3082 apb3Router_1.io_input_PWDATA[31] io_gpioA_write[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3850 $abc$18544$new_n3318 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_mainBusArbiter.rspTarget $abc$18544$new_n3257 $abc$18544$auto$rtlil.cc:2693:MuxGate$16594 +00100 1 +01100 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] system_ram._zz_ram_port0[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3849 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16596 +001 1 +011 1 +110 1 +111 1 +.names resetCtrl_systemClkResetCounter[5] $abc$18544$new_n3841 $abc$18544$auto$rtlil.cc:2693:MuxGate$16598 +01 1 +10 1 +11 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] system_cpu.IBusSimplePlugin_injector_port_state[2] $abc$18544$new_n3832 $abc$18544$auto$rtlil.cc:2693:MuxGate$16600 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3254 $abc$18544$new_n3310 system_cpu.execute_LightShifterPlugin_isActive $abc$18544$auto$rtlil.cc:2693:MuxGate$16602 +1001 1 +1011 1 +1100 1 +1101 1 +.names system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16604 +111 1 +.names $abc$18544$new_n3316 $abc$18544$new_n3851 $abc$18544$new_n3256 system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16606 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3316 $abc$18544$new_n3309 system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 $abc$18544$auto$rtlil.cc:2693:MuxGate$16608 +1101 1 +1110 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3657 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3998 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] system_cpu.CsrPlugin_mie_MSIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16610 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_772 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$new_n3998 +11111 1 +.names $abc$18544$new_n3998 $abc$18544$new_n4000 system_cpu.CsrPlugin_mie_MTIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16612 +001 1 +011 1 +110 1 +111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3628 $abc$18544$new_n4000 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3998 $abc$18544$new_n4002 system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16614 +001 1 +011 1 +110 1 +111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n3599 $abc$18544$new_n4002 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_injector_decodeInput_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3318 $abc$18544$auto$rtlil.cc:2693:MuxGate$16616 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n4005 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid $abc$18544$new_n3850 $abc$18544$auto$rtlil.cc:2693:MuxGate$16618 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3932 system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4005 +10 1 +.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$18544$new_n3851 $abc$18544$new_n3708 $abc$18544$auto$rtlil.cc:2693:MuxGate$16620 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_fetchPc_booted $abc$18544$new_n3708 $abc$18544$new_n3722 $abc$18544$new_n4008 system_cpu.DebugPlugin_haltIt $abc$18544$new_n4007 +11110 1 +.names $abc$18544$new_n3852 $abc$18544$new_n4009 system_cpu.DebugPlugin_stepIt $abc$18544$new_n4008 +000 1 +010 1 +011 1 +.names system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid system_cpu.IBusSimplePlugin_injector_decodeInput_valid $abc$18544$new_n4009 +000 1 +.names $abc$18544$new_n4007 system_cpu.IBusSimplePlugin_fetchPc_inc $abc$18544$new_n3707 $abc$18544$auto$rtlil.cc:2693:MuxGate$16622 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n3722 $abc$18544$new_n3309 system_cpu.execute_arbitration_isValid $abc$18544$new_n3851 $abc$18544$auto$rtlil.cc:2693:MuxGate$16624 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3851 $abc$18544$new_n3268 $abc$18544$new_n3317 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16626 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$18544$new_n3255 $abc$18544$new_n4016 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] $abc$18544$new_n4014 $abc$18544$new_n3666 $abc$18544$auto$rtlil.cc:2693:MuxGate$16640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$18544$new_n3466 $abc$18544$new_n3473 $abc$18544$new_n3678 $abc$18544$new_n4015 $abc$18544$new_n4014 +1000 1 +1001 1 +1101 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[31] system_cpu.decode_to_execute_SRC2[31] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n4015 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$18544$new_n3258 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu._zz_execute_SHIFT_CTRL[0] $abc$18544$new_n3471 $abc$18544$new_n3480 $abc$18544$new_n4016 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n4018 system_cpu.execute_LightShifterPlugin_amplitudeReg[4] system_cpu.execute_LightShifterPlugin_isActive $abc$18544$new_n3254 system_cpu.decode_to_execute_SRC2[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16692 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names $abc$18544$new_n3260 system_cpu.execute_LightShifterPlugin_isActive system_cpu.execute_LightShifterPlugin_amplitudeReg[3] system_cpu.decode_to_execute_SRC2[3] $abc$18544$new_n4018 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_cpu.CsrPlugin_mstatus_MIE system_cpu.CsrPlugin_interrupt_code[3] $abc$18544$new_n4020 system_cpu.CsrPlugin_mip_MEIP system_cpu.CsrPlugin_mie_MEIE $abc$18544$auto$rtlil.cc:2693:MuxGate$16696 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4021 system_cpu.CsrPlugin_mie_MTIE system_cpu.CsrPlugin_mip_MTIP $abc$18544$new_n4020 +100 1 +101 1 +110 1 +.names system_cpu.CsrPlugin_mip_MSIP system_cpu.CsrPlugin_mie_MSIE system_cpu.CsrPlugin_mie_MEIE system_cpu.CsrPlugin_mip_MEIP $abc$18544$new_n4021 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n4021 system_cpu.CsrPlugin_interrupt_code[2] $abc$18544$new_n4020 $abc$18544$auto$rtlil.cc:2693:MuxGate$16700 +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3352 $abc$18544$new_n3269 systemDebugger_1._zz_io_mem_cmd_payload_address[63] $abc$18544$new_n4024 system_cpu._zz_decode_SRC2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16702 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] $abc$18544$new_n4024 +000 1 +001 1 +100 1 +110 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l288_1 system_cpu.DebugPlugin_disableEbreak system_cpu.when_DebugPlugin_l288 $abc$18544$auto$rtlil.cc:2693:MuxGate$16704 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3838 systemDebugger_1._zz_io_mem_cmd_payload_address[2] $abc$18544$new_n4026 +1110 1 +.names system_cpu.DebugPlugin_debugUsed $abc$18544$new_n3834 $abc$18544$auto$rtlil.cc:2693:MuxGate$16706 +01 1 +10 1 +11 1 +.names $abc$18544$new_n4026 systemDebugger_1._zz_io_mem_cmd_payload_address[36] system_cpu.DebugPlugin_stepIt $abc$18544$auto$rtlil.cc:2693:MuxGate$16708 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l284_1 system_cpu.DebugPlugin_resetIt system_cpu.when_DebugPlugin_l284 $abc$18544$auto$rtlil.cc:2693:MuxGate$16710 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PENABLE $abc$18544$new_n3933 $abc$18544$new_n3711 $abc$18544$auto$rtlil.cc:2693:MuxGate$16712 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names systemDebugger_1.dispatcher_counter[2] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16724 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names systemDebugger_1.dispatcher_counter[0] systemDebugger_1.dispatcher_counter[1] $abc$18544$new_n4032 +11 1 +.names $abc$18544$new_n4034 $abc$18544$new_n4036 systemDebugger_1.dispatcher_headerLoaded $abc$18544$auto$rtlil.cc:2693:MuxGate$16726 +000 1 +001 1 +011 1 +.names systemDebugger_1.dispatcher_dataLoaded systemDebugger_1.dispatcher_headerLoaded $abc$18544$new_n3833 $abc$18544$new_n4035 $abc$18544$new_n4034 +1100 1 +1101 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_port_state[2] system_cpu.IBusSimplePlugin_injector_port_state[0] system_cpu.IBusSimplePlugin_injector_port_state[1] $abc$18544$new_n4035 +100 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$new_n4032 systemDebugger_1.dispatcher_counter[2] $abc$18544$new_n4036 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4034 systemDebugger_1.dispatcher_dataLoaded jtagBridge_1.flowCCByToggle_1.io_output_valid jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16728 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1.dispatcher_header[7] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16730 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_output_valid systemDebugger_1.dispatcher_headerLoaded systemDebugger_1._zz_io_mem_cmd_payload_address[66] jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16732 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names jtagBridge_1.flowCCByToggle_1.io_input_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16734 +010 1 +011 1 +101 1 +111 1 +.names jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] jtagBridge_1.flowCCByToggle_1.inputArea_data_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16736 +001 1 +011 1 +100 1 +101 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] $abc$18544$new_n2864 jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] +11000 1 +.names jtagBridge_1.flowCCByToggle_1.inputArea_target jtagBridge_1.flowCCByToggle_1.io_input_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16738 +01 1 +10 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_hit jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid +01 1 +10 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment $abc$18544$auto$rtlil.cc:2693:MuxGate$16740 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid jtagBridge_1.flowCCByToggle_1.inputArea_data_last jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last $abc$18544$auto$rtlil.cc:2693:MuxGate$16742 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.io_remote_rsp_fire jtagBridge_1.io_remote_rsp_payload_data[31] jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16744 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3187 jtagBridge_1.jtag_tap_instructionShift[3] jtagBridge_1._zz_jtag_tap_isBypass[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16746 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3191 io_jtag_tdi jtagBridge_1.jtag_idcodeArea_shifter[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16748 +001 1 +011 1 +110 1 +111 1 +.names jtagBridge_1.system_rsp_valid jtagBridge_1.flowCCByToggle_1.io_output_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$16750 +10 1 +.names system_timer.timerA.counter[15] system_timer.timerA.counter[13] system_timer.timerA.counter[14] $abc$18544$new_n2773 $abc$18544$auto$rtlil.cc:2693:MuxGate$16752 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.timerB.counter[15] system_timer.timerB.counter[13] system_timer.timerB.counter[14] $abc$18544$new_n2824 $abc$18544$auto$rtlil.cc:2693:MuxGate$16754 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3721 $abc$18544$new_n3706 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] $abc$18544$new_n4054 $abc$18544$new_n4055 $abc$18544$auto$rtlil.cc:2693:MuxGate$16758 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[29] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] $abc$18544$new_n3689 $abc$18544$new_n4054 +1111 1 +.names $abc$18544$new_n3722 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$new_n3725 system_cpu.CsrPlugin_mepc[31] $abc$18544$new_n4055 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3723 system_cpu.CsrPlugin_interrupt_code[3] system_cpu.CsrPlugin_mcause_exceptionCode[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16760 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3267 system_cpu.IBusSimplePlugin_cmd_payload_pc[31] system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16762 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3723 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.CsrPlugin_mepc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16768 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.lastStageIsFiring $abc$18544$new_n2915 $abc$18544$new_n4060 system_cpu.DebugPlugin_busReadDataReg[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16772 +0001 1 +0011 1 +1000 1 +1001 1 +.names $abc$18544$new_n2912 $abc$18544$new_n4061 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] $abc$18544$new_n4060 +000 1 +010 1 +110 1 +111 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$18544$new_n4062 system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] $abc$18544$new_n4061 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] $abc$18544$new_n4062 +000 1 +010 1 +100 1 +101 1 +.names $abc$18544$new_n2915 system_cpu.lastStageIsFiring system_cpu.decode_to_execute_PC[31] $abc$18544$new_n4064 jtagBridge_1.io_remote_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16774 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n2908 system_cpu._zz_lastStageRegFileWrite_payload_address[13] system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] $abc$18544$new_n2912 system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] $abc$18544$new_n4064 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names io_jtag_tdi $abc$18544$new_n3826 $abc$18544$new_n3828 jtagBridge_1.jtag_tap_instructionShift[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16778 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$18544$new_n2862 jtagBridge_1.jtag_readArea_full_shifter[1] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_readArea_full_shifter[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16782 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n2862 $abc$18544$new_n2864 jtagBridge_1.jtag_readArea_full_shifter[33] io_jtag_tdi jtagBridge_1.system_rsp_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16784 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$14856 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$14858 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$14860 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$14862 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$14864 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$14866 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$14868 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$14870 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$14872 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$14874 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$14876 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$14878 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$14880 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$14882 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$14884 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$14886 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$14888 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$14890 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$14892 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$14894 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$14896 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$14898 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$14900 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$14902 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$14904 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$14906 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$14908 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$14910 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$14912 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[0] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$auto$rtlil.cc:2693:MuxGate$15034 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[30] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15036 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[29] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15038 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[28] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15040 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[27] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15042 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[26] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15044 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[25] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15046 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[24] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15048 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[23] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15050 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[22] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15052 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[21] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15054 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[20] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15056 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[19] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15058 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[18] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15060 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[17] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15062 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[16] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15064 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[15] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15066 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[14] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15068 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[13] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15070 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15072 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_3 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15074 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l379 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15076 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_2 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15078 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[8] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15080 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15082 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15084 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15086 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15088 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15090 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15092 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15094 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_uartCtrl.when_BusSlaveFactory_l347 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15096 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4130 system_cpu._zz_execute_SrcPlugin_addSub_2[30] system_cpu._zz_RegFilePlugin_regFile_port0[30] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15244 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4130 +11110 1 +.names $abc$18544$new_n4132 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4131 +100 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4132 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4134 system_cpu._zz_execute_SrcPlugin_addSub_2[29] system_cpu._zz_RegFilePlugin_regFile_port0[29] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15246 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4134 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4136 system_cpu._zz_execute_SrcPlugin_addSub_2[28] system_cpu._zz_RegFilePlugin_regFile_port0[28] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15248 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4136 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4138 system_cpu._zz_execute_SrcPlugin_addSub_2[27] system_cpu._zz_RegFilePlugin_regFile_port0[27] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15250 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4138 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4140 system_cpu._zz_execute_SrcPlugin_addSub_2[26] system_cpu._zz_RegFilePlugin_regFile_port0[26] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15252 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4142 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4144 system_cpu._zz_execute_SrcPlugin_addSub_2[24] system_cpu._zz_RegFilePlugin_regFile_port0[24] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15256 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4144 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4146 system_cpu._zz_execute_SrcPlugin_addSub_2[23] system_cpu._zz_RegFilePlugin_regFile_port0[23] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15258 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4146 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4148 system_cpu._zz_execute_SrcPlugin_addSub_2[22] system_cpu._zz_RegFilePlugin_regFile_port0[22] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15260 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4148 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4150 system_cpu._zz_execute_SrcPlugin_addSub_2[21] system_cpu._zz_RegFilePlugin_regFile_port0[21] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15262 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4156 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4158 system_cpu._zz_execute_SrcPlugin_addSub_2[17] system_cpu._zz_RegFilePlugin_regFile_port0[17] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15270 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4158 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4160 system_cpu._zz_execute_SrcPlugin_addSub_2[16] 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system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4164 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4166 system_cpu._zz_execute_SrcPlugin_addSub_2[13] system_cpu._zz_RegFilePlugin_regFile_port0[13] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$15278 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4166 +11110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4168 system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu._zz_RegFilePlugin_regFile_port0[12] $abc$18544$new_n4131 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$abc$18544$new_n4170 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4171 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4173 system_cpu._zz_execute_SrcPlugin_addSub_2[3] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15286 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4173 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4175 system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15290 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4175 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 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$abc$18544$auto$rtlil.cc:2693:MuxGate$15426 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu._zz_decode_SRC2 $abc$18544$new_n4179 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4180 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4182 system_cpu.decode_to_execute_SRC2[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15428 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu._zz_decode_SRC2 $abc$18544$new_n4182 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4184 system_cpu.decode_to_execute_SRC2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15430 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[28] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu._zz_decode_SRC2 $abc$18544$new_n4184 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4186 system_cpu.decode_to_execute_SRC2[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15432 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[27] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu._zz_decode_SRC2 $abc$18544$new_n4186 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4188 system_cpu.decode_to_execute_SRC2[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15434 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu._zz_decode_SRC2 $abc$18544$new_n4188 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4190 system_cpu.decode_to_execute_SRC2[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15436 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu._zz_decode_SRC2 $abc$18544$new_n4190 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4192 system_cpu.decode_to_execute_SRC2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15438 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu._zz_decode_SRC2 $abc$18544$new_n4192 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4194 system_cpu.decode_to_execute_SRC2[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15440 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[23] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu._zz_decode_SRC2 $abc$18544$new_n4194 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4196 system_cpu.decode_to_execute_SRC2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15442 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu._zz_decode_SRC2 $abc$18544$new_n4196 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4198 system_cpu.decode_to_execute_SRC2[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15444 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4180 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port1[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu._zz_decode_SRC2 $abc$18544$new_n4198 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4200 system_cpu.decode_to_execute_SRC2[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15446 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu._zz_decode_SRC2 $abc$18544$new_n4200 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4202 system_cpu.decode_to_execute_SRC2[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15448 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[19] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu._zz_decode_SRC2 $abc$18544$new_n4202 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4204 system_cpu.decode_to_execute_SRC2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15450 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[18] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu._zz_decode_SRC2 $abc$18544$new_n4204 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4206 system_cpu.decode_to_execute_SRC2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15452 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4180 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port1[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu._zz_decode_SRC2 $abc$18544$new_n4206 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4208 system_cpu.decode_to_execute_SRC2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15454 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu._zz_decode_SRC2 $abc$18544$new_n4208 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4210 system_cpu.decode_to_execute_SRC2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15456 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu._zz_decode_SRC2 $abc$18544$new_n4210 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4212 system_cpu.decode_to_execute_SRC2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15458 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[14] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu._zz_decode_SRC2 $abc$18544$new_n4212 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4214 system_cpu.decode_to_execute_SRC2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15460 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu._zz_decode_SRC2 $abc$18544$new_n4214 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4216 system_cpu.decode_to_execute_SRC2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15462 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[12] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu._zz_decode_SRC2 $abc$18544$new_n4216 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4218 system_cpu.decode_to_execute_SRC2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15464 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[11] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu._zz_decode_SRC2 $abc$18544$new_n4218 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4220 system_cpu.decode_to_execute_SRC2[10] system_cpu._zz_RegFilePlugin_regFile_port1[10] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15466 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4180 $abc$18544$new_n4220 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4222 system_cpu.decode_to_execute_SRC2[9] system_cpu._zz_RegFilePlugin_regFile_port1[9] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$18544$new_n4180 $abc$18544$new_n4222 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4224 system_cpu.decode_to_execute_SRC2[8] system_cpu._zz_RegFilePlugin_regFile_port1[8] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15470 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$new_n4180 $abc$18544$new_n4224 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4226 system_cpu.decode_to_execute_SRC2[7] system_cpu._zz_RegFilePlugin_regFile_port1[7] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4180 $abc$18544$new_n4226 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4228 system_cpu.decode_to_execute_SRC2[6] system_cpu._zz_RegFilePlugin_regFile_port1[6] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4180 $abc$18544$new_n4228 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4230 system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_RegFilePlugin_regFile_port1[5] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$18544$new_n4180 $abc$18544$new_n4230 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_SRC2[4] $abc$18544$new_n4234 $abc$18544$new_n4232 $abc$18544$auto$rtlil.cc:2693:MuxGate$15478 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4232 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4233 +1000 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$18544$new_n4235 $abc$18544$new_n4234 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 $abc$18544$new_n4235 +00 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4237 system_cpu.decode_to_execute_SRC2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15480 +001 1 +011 1 +100 1 +101 1 +.names $abc$18544$new_n4238 system_cpu._zz_RegFilePlugin_regFile_port1[3] $abc$18544$new_n4180 $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4237 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4238 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4240 system_cpu.decode_to_execute_SRC2[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15482 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n4241 system_cpu._zz_RegFilePlugin_regFile_port1[2] $abc$18544$new_n4180 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$new_n4233 $abc$18544$new_n4240 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4241 +11 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4243 system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_RegFilePlugin_regFile_port1[1] $abc$18544$new_n4180 $abc$18544$auto$rtlil.cc:2693:MuxGate$15484 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4235 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$18544$new_n4233 $abc$18544$new_n4243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4245 system_cpu.decode_to_execute_SRC2[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$new_n4235 $abc$18544$auto$rtlil.cc:2693:MuxGate$15486 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $abc$18544$new_n4180 $abc$18544$new_n4233 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$18544$new_n4245 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[30] system_cpu.decode_to_execute_RS1[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15488 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[29] system_cpu.decode_to_execute_RS1[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15490 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[28] system_cpu.decode_to_execute_RS1[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15492 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[27] system_cpu.decode_to_execute_RS1[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15494 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[26] system_cpu.decode_to_execute_RS1[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15496 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[25] system_cpu.decode_to_execute_RS1[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15498 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[24] system_cpu.decode_to_execute_RS1[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15500 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[23] system_cpu.decode_to_execute_RS1[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15502 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[22] system_cpu.decode_to_execute_RS1[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15504 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[21] system_cpu.decode_to_execute_RS1[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15506 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[20] system_cpu.decode_to_execute_RS1[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15508 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[19] system_cpu.decode_to_execute_RS1[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15510 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[18] system_cpu.decode_to_execute_RS1[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15512 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[17] system_cpu.decode_to_execute_RS1[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15514 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[16] system_cpu.decode_to_execute_RS1[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15516 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[15] system_cpu.decode_to_execute_RS1[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15518 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[14] system_cpu.decode_to_execute_RS1[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15520 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[13] system_cpu.decode_to_execute_RS1[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15522 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[12] system_cpu.decode_to_execute_RS1[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15524 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[11] system_cpu.decode_to_execute_RS1[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15526 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[10] system_cpu.decode_to_execute_RS1[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15528 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[9] system_cpu.decode_to_execute_RS1[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15530 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[8] system_cpu.decode_to_execute_RS1[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15532 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15534 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15536 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15538 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[4] system_cpu.decode_to_execute_RS1[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15540 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[3] system_cpu.decode_to_execute_RS1[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15542 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[2] system_cpu.decode_to_execute_RS1[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15544 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[1] system_cpu.decode_to_execute_RS1[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15546 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[0] system_cpu.decode_to_execute_RS1[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15548 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[30] system_cpu.decode_to_execute_RS2[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15550 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[29] system_cpu.decode_to_execute_RS2[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15552 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[28] system_cpu.decode_to_execute_RS2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15554 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[27] system_cpu.decode_to_execute_RS2[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15556 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[26] system_cpu.decode_to_execute_RS2[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15558 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[25] system_cpu.decode_to_execute_RS2[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15560 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[24] system_cpu.decode_to_execute_RS2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15562 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[23] system_cpu.decode_to_execute_RS2[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15564 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[22] system_cpu.decode_to_execute_RS2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15566 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[21] system_cpu.decode_to_execute_RS2[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15568 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[20] system_cpu.decode_to_execute_RS2[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15570 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[19] system_cpu.decode_to_execute_RS2[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15572 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[18] system_cpu.decode_to_execute_RS2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15574 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[17] system_cpu.decode_to_execute_RS2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15576 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[16] system_cpu.decode_to_execute_RS2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15578 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[15] system_cpu.decode_to_execute_RS2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15580 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[14] system_cpu.decode_to_execute_RS2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15582 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[13] system_cpu.decode_to_execute_RS2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15584 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[12] system_cpu.decode_to_execute_RS2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15586 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[11] system_cpu.decode_to_execute_RS2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15588 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[10] system_cpu.decode_to_execute_RS2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15590 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[9] system_cpu.decode_to_execute_RS2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15592 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[8] system_cpu.decode_to_execute_RS2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15594 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[7] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15596 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[6] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15598 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[5] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15600 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[4] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15602 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[3] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15604 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[2] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15606 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[1] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15608 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[0] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15610 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_BRANCH_CTRL[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15612 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4310 system_cpu._zz_execute_SHIFT_CTRL[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15614 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$18544$new_n4310 +11000 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ALU_CTRL[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15616 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ALU_BITWISE_CTRL[0] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$auto$rtlil.cc:2693:MuxGate$15618 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[29] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15630 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[28] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15632 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[14] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15660 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[13] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15662 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[12] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15664 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[11] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15666 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[10] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15668 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15670 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15672 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_INSTRUCTION[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15674 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15690 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15692 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15694 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15696 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15698 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15700 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15702 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15704 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15706 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15708 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15710 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15712 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15714 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15716 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15718 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15720 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15722 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$15724 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15726 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15728 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15730 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$15732 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15734 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15736 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4348 system_cpu.BranchPlugin_jumpInterface_payload[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15810 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n4400 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4349 $abc$18544$new_n4348 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4399 $abc$18544$new_n4398 $abc$18544$new_n4397 $abc$18544$new_n4350 $abc$18544$new_n4349 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4396 $abc$18544$new_n4395 $abc$18544$new_n4394 $abc$18544$new_n4351 $abc$18544$new_n4350 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4393 $abc$18544$new_n4392 $abc$18544$new_n4391 $abc$18544$new_n4352 $abc$18544$new_n4351 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$18544$new_n4390 $abc$18544$new_n4388 $abc$18544$new_n4389 $abc$18544$new_n4387 $abc$18544$new_n4353 $abc$18544$new_n4352 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4386 $abc$18544$new_n4384 $abc$18544$new_n4385 $abc$18544$new_n4383 $abc$18544$new_n4354 $abc$18544$new_n4353 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4382 $abc$18544$new_n4380 $abc$18544$new_n4381 $abc$18544$new_n4379 $abc$18544$new_n4355 $abc$18544$new_n4354 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4378 $abc$18544$new_n4376 $abc$18544$new_n4377 $abc$18544$new_n4375 $abc$18544$new_n4356 $abc$18544$new_n4355 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$18544$new_n4373 $abc$18544$new_n4374 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] $abc$18544$new_n4372 $abc$18544$new_n4357 $abc$18544$new_n4356 +00011 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4371 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$new_n4370 $abc$18544$new_n4358 $abc$18544$new_n4357 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4365 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$new_n4359 system_cpu.decode_to_execute_PC[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$new_n4358 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$18544$new_n4365 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$new_n4360 system_cpu.decode_to_execute_PC[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$new_n4359 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$18544$new_n4365 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$new_n4361 system_cpu.decode_to_execute_PC[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$new_n4360 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4369 $abc$18544$new_n4362 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n4361 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4368 $abc$18544$new_n4363 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n4362 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4366 $abc$18544$new_n4364 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$new_n4363 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[2] system_cpu.decode_to_execute_PC[2] $abc$18544$new_n4364 +000 1 +010 1 +100 1 +101 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] $abc$18544$new_n4365 +11 1 +.names $abc$18544$new_n4365 system_cpu.decode_to_execute_RS1[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] 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+01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] $abc$18544$new_n4370 $abc$18544$new_n4434 system_cpu.BranchPlugin_jumpInterface_payload[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15852 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n4371 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4358 $abc$18544$new_n4434 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] $abc$18544$new_n4371 $abc$18544$new_n4358 system_cpu.BranchPlugin_jumpInterface_payload[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15854 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4359 $abc$18544$new_n4437 system_cpu.BranchPlugin_jumpInterface_payload[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15856 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[7] system_cpu.decode_to_execute_RS1[7] $abc$18544$new_n4437 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4360 $abc$18544$new_n4439 system_cpu.BranchPlugin_jumpInterface_payload[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15858 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[6] system_cpu.decode_to_execute_RS1[6] $abc$18544$new_n4439 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4361 $abc$18544$new_n4441 system_cpu.BranchPlugin_jumpInterface_payload[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15860 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[5] system_cpu.decode_to_execute_RS1[5] $abc$18544$new_n4441 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4443 system_cpu.BranchPlugin_jumpInterface_payload[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15862 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4369 $abc$18544$new_n4362 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n4443 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4445 system_cpu.BranchPlugin_jumpInterface_payload[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15864 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4368 $abc$18544$new_n4363 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n4445 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4447 system_cpu.BranchPlugin_jumpInterface_payload[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15866 +010 1 +011 1 +101 1 +111 1 +.names system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$new_n4366 $abc$18544$new_n4364 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$18544$new_n4447 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] system_cpu.decode_to_execute_PC[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$15870 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] system_cpu.decode_to_execute_PC[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$15872 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] system_cpu.decode_to_execute_PC[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$15874 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] system_cpu.decode_to_execute_PC[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$15876 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] system_cpu.decode_to_execute_PC[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$15878 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] system_cpu.decode_to_execute_PC[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$15880 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] system_cpu.decode_to_execute_PC[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$15882 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] system_cpu.decode_to_execute_PC[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$15884 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] system_cpu.decode_to_execute_PC[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$15886 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] system_cpu.decode_to_execute_PC[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$15888 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] system_cpu.decode_to_execute_PC[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$15890 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] system_cpu.decode_to_execute_PC[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$15892 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] system_cpu.decode_to_execute_PC[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$15894 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] system_cpu.decode_to_execute_PC[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$15896 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] system_cpu.decode_to_execute_PC[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$15898 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] system_cpu.decode_to_execute_PC[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$15900 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] system_cpu.decode_to_execute_PC[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$15902 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] system_cpu.decode_to_execute_PC[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$15904 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] system_cpu.decode_to_execute_PC[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$15906 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] system_cpu.decode_to_execute_PC[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$15908 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] system_cpu.decode_to_execute_PC[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$15910 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] system_cpu.decode_to_execute_PC[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$15912 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] system_cpu.decode_to_execute_PC[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$15914 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] system_cpu.decode_to_execute_PC[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$15916 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] system_cpu.decode_to_execute_PC[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$15918 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] system_cpu.decode_to_execute_PC[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$15920 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] system_cpu.decode_to_execute_PC[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$15922 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] system_cpu.decode_to_execute_PC[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$15924 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] system_cpu.decode_to_execute_PC[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$15926 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$15970 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[19] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16192 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4480 apb3Router_1.io_input_PADDR[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16194 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[18] system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$new_n4480 +000 1 +001 1 +100 1 +110 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[17] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16196 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16198 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4484 apb3Router_1.io_input_PADDR[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16200 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[15] system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$new_n4484 +000 1 +001 1 +100 1 +110 1 +.names io_apb_decoder.io_input_PSEL system_mainBusArbiter.io_dBus_cmd_valid apb3Router_1.io_input_PADDR[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16202 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n4487 apb3Router_1.io_input_PADDR[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16204 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[13] system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$new_n4487 +000 1 +001 1 +100 1 +110 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[12] system_mainBusArbiter.io_dBus_cmd_payload_address[12] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] apb3Router_1.io_input_PADDR[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16206 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[7] system_mainBusArbiter.io_dBus_cmd_payload_address[7] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] apb3Router_1.io_input_PADDR[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16216 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[6] system_mainBusArbiter.io_dBus_cmd_payload_address[6] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] apb3Router_1.io_input_PADDR[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16218 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[5] system_mainBusArbiter.io_dBus_cmd_payload_address[5] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] apb3Router_1.io_input_PADDR[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16220 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[4] system_mainBusArbiter.io_dBus_cmd_payload_address[4] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] apb3Router_1.io_input_PADDR[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16222 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[3] system_mainBusArbiter.io_dBus_cmd_payload_address[3] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] apb3Router_1.io_input_PADDR[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16224 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[2] system_mainBusArbiter.io_dBus_cmd_payload_address[2] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] +010 1 +011 1 +101 1 +111 1 +.names io_apb_decoder.io_input_PSEL system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] apb3Router_1.io_input_PADDR[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16226 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu._zz_RegFilePlugin_regFile_port0[10] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16302 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu._zz_RegFilePlugin_regFile_port0[9] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16306 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_RegFilePlugin_regFile_port0[8] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16310 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu._zz_RegFilePlugin_regFile_port0[7] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16314 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu._zz_RegFilePlugin_regFile_port0[6] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16318 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu._zz_RegFilePlugin_regFile_port0[5] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16322 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[0] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16386 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4511 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16388 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4510 +00 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[30] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[14] $abc$18544$new_n4511 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4513 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16390 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[29] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[13] $abc$18544$new_n4513 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4515 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16392 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[28] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[12] $abc$18544$new_n4515 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4517 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[27] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[11] $abc$18544$new_n4517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4519 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[26] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[10] $abc$18544$new_n4519 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4521 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16398 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[25] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[9] $abc$18544$new_n4521 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4523 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$new_n4510 $abc$18544$auto$rtlil.cc:2693:MuxGate$16400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[24] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.decode_to_execute_RS2[8] $abc$18544$new_n4523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] system_cpu.decode_to_execute_RS2[23] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16402 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] system_cpu.decode_to_execute_RS2[22] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16404 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] system_cpu.decode_to_execute_RS2[21] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16406 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] system_cpu.decode_to_execute_RS2[20] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16408 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] system_cpu.decode_to_execute_RS2[19] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16410 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] system_cpu.decode_to_execute_RS2[18] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16412 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] system_cpu.decode_to_execute_RS2[17] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16414 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.switch_Misc_l241_1 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] system_cpu.decode_to_execute_RS2[16] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16416 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16418 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16420 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16422 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16424 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16426 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16428 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16430 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4510 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16432 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16434 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] system_cpu._zz_dBus_cmd_payload_data[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16436 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] system_cpu._zz_dBus_cmd_payload_data[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16438 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] system_cpu._zz_dBus_cmd_payload_data[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16440 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] system_cpu._zz_dBus_cmd_payload_data[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16442 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] system_cpu._zz_dBus_cmd_payload_data[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16444 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] system_cpu._zz_dBus_cmd_payload_data[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16446 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] system_cpu._zz_dBus_cmd_payload_data[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16448 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3408 system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$auto$rtlil.cc:2693:MuxGate$16450 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3476 system_mainBusArbiter.io_dBus_cmd_payload_address[29] $abc$18544$auto$rtlil.cc:2693:MuxGate$16452 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[28] $abc$18544$new_n3485 system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$auto$rtlil.cc:2693:MuxGate$16454 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3490 system_mainBusArbiter.io_dBus_cmd_payload_address[27] $abc$18544$auto$rtlil.cc:2693:MuxGate$16456 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3497 system_mainBusArbiter.io_dBus_cmd_payload_address[26] $abc$18544$auto$rtlil.cc:2693:MuxGate$16458 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3503 system_mainBusArbiter.io_dBus_cmd_payload_address[25] $abc$18544$auto$rtlil.cc:2693:MuxGate$16460 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[24] $abc$18544$new_n3511 system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$auto$rtlil.cc:2693:MuxGate$16462 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3515 system_mainBusArbiter.io_dBus_cmd_payload_address[23] $abc$18544$auto$rtlil.cc:2693:MuxGate$16464 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[22] $abc$18544$new_n3523 system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$auto$rtlil.cc:2693:MuxGate$16466 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3527 system_mainBusArbiter.io_dBus_cmd_payload_address[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16468 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3534 system_mainBusArbiter.io_dBus_cmd_payload_address[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16470 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3540 system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16472 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3547 system_mainBusArbiter.io_dBus_cmd_payload_address[18] $abc$18544$auto$rtlil.cc:2693:MuxGate$16474 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3553 system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$auto$rtlil.cc:2693:MuxGate$16476 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3560 system_mainBusArbiter.io_dBus_cmd_payload_address[16] $abc$18544$auto$rtlil.cc:2693:MuxGate$16478 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3568 system_mainBusArbiter.io_dBus_cmd_payload_address[15] $abc$18544$auto$rtlil.cc:2693:MuxGate$16480 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3574 system_mainBusArbiter.io_dBus_cmd_payload_address[14] $abc$18544$auto$rtlil.cc:2693:MuxGate$16482 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3582 system_mainBusArbiter.io_dBus_cmd_payload_address[13] $abc$18544$auto$rtlil.cc:2693:MuxGate$16484 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[12] $abc$18544$new_n3589 system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$auto$rtlil.cc:2693:MuxGate$16486 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3596 system_mainBusArbiter.io_dBus_cmd_payload_address[11] $abc$18544$auto$rtlil.cc:2693:MuxGate$16488 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[10] $abc$18544$new_n3606 system_cpu._zz_execute_SrcPlugin_addSub_2[10] $abc$18544$auto$rtlil.cc:2693:MuxGate$16490 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3612 system_mainBusArbiter.io_dBus_cmd_payload_address[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16492 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[8] $abc$18544$new_n3619 system_cpu._zz_execute_SrcPlugin_addSub_2[8] $abc$18544$auto$rtlil.cc:2693:MuxGate$16494 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3625 system_mainBusArbiter.io_dBus_cmd_payload_address[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16496 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3637 system_mainBusArbiter.io_dBus_cmd_payload_address[6] $abc$18544$auto$rtlil.cc:2693:MuxGate$16498 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3642 system_mainBusArbiter.io_dBus_cmd_payload_address[5] $abc$18544$auto$rtlil.cc:2693:MuxGate$16500 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3649 system_mainBusArbiter.io_dBus_cmd_payload_address[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16502 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3654 system_mainBusArbiter.io_dBus_cmd_payload_address[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16504 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3664 system_mainBusArbiter.io_dBus_cmd_payload_address[2] $abc$18544$auto$rtlil.cc:2693:MuxGate$16506 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3670 system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16508 +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu._zz_execute_SrcPlugin_addSub_2[0] system_cpu.decode_to_execute_SRC2[0] system_cpu.decode_to_execute_SRC2_FORCE_ZERO system_mainBusArbiter.io_dBus_cmd_payload_address[0] $abc$18544$auto$rtlil.cc:2693:MuxGate$16510 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_cpu.switch_Misc_l241_1 $abc$18544$auto$rtlil.cc:2693:MuxGate$16524 +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n4581 system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$new_n4510 system_cpu._zz_dBus_cmd_payload_data[7] $abc$18544$auto$rtlil.cc:2693:MuxGate$16526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.switch_Misc_l241_1 system_cpu.decode_to_execute_RS2[31] system_cpu.decode_to_execute_RS2[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] $abc$18544$new_n4581 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names system_mainBusArbiter.io_dBus_cmd_valid $abc$18544$new_n3678 system_mainBusArbiter.io_dBus_cmd_payload_address[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16528 +000 1 +001 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_wr system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16530 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_834 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$new_n4585 $abc$18544$auto$rtlil.cc:2693:MuxGate$16628 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4586 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4585 +11000 1 +.names $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4586 +1000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$18544$new_n4587 +1100 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_772 $abc$18544$new_n4590 $abc$18544$new_n4589 $abc$18544$auto$rtlil.cc:2693:MuxGate$16630 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n4587 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$18544$new_n4589 +11000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4590 +0000 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4592 system_cpu.execute_CsrPlugin_csr_836 $abc$18544$auto$rtlil.cc:2693:MuxGate$16632 +001 1 +011 1 +110 1 +111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$18544$new_n4589 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$18544$new_n4592 +11000 1 +.names $abc$18544$new_n3309 system_cpu.execute_CsrPlugin_csr_768 $abc$18544$new_n4586 $abc$18544$new_n4590 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$18544$auto$rtlil.cc:2693:MuxGate$16634 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_BRANCH_DO system_cpu._zz_execute_BRANCH_CTRL[1] system_cpu._zz_execute_BRANCH_CTRL[0] $abc$18544$new_n4595 $abc$18544$auto$rtlil.cc:2693:MuxGate$16638 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.switch_Misc_l241_1 $abc$18544$new_n4596 $abc$18544$new_n4597 $abc$18544$new_n4595 +00000 1 +00010 1 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +10101 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n3685 $abc$18544$new_n3678 $abc$18544$new_n3681 $abc$18544$new_n4596 +100 1 +101 1 +110 1 +.names $abc$18544$new_n4613 $abc$18544$new_n4611 $abc$18544$new_n4604 $abc$18544$new_n4598 $abc$18544$new_n4597 +1111 1 +.names $abc$18544$new_n4601 $abc$18544$new_n4599 $abc$18544$new_n4603 system_cpu.decode_to_execute_SRC2[17] system_cpu._zz_execute_SrcPlugin_addSub_2[17] $abc$18544$new_n4598 +11100 1 +11111 1 +.names $abc$18544$new_n4600 system_cpu.decode_to_execute_SRC2[23] system_cpu._zz_execute_SrcPlugin_addSub_2[23] system_cpu.decode_to_execute_SRC2[24] system_cpu._zz_execute_SrcPlugin_addSub_2[24] $abc$18544$new_n4599 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[16] system_cpu._zz_execute_SrcPlugin_addSub_2[16] system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n4600 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4602 $abc$18544$new_n3681 system_cpu.decode_to_execute_SRC2[0] system_cpu._zz_execute_SrcPlugin_addSub_2[0] $abc$18544$new_n4601 +1100 1 +1111 1 +.names system_cpu.decode_to_execute_SRC2[2] system_cpu._zz_execute_SrcPlugin_addSub_2[2] system_cpu.decode_to_execute_SRC2[30] system_cpu._zz_execute_SrcPlugin_addSub_2[30] $abc$18544$new_n4602 +0000 1 +0011 1 +1100 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[9] system_cpu.decode_to_execute_SRC2[9] system_cpu.decode_to_execute_SRC2[13] system_cpu._zz_execute_SrcPlugin_addSub_2[13] $abc$18544$new_n4603 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4607 $abc$18544$new_n4605 $abc$18544$new_n4609 system_cpu.decode_to_execute_SRC2[20] system_cpu._zz_execute_SrcPlugin_addSub_2[20] $abc$18544$new_n4604 +11100 1 +11111 1 +.names $abc$18544$new_n4606 system_cpu._zz_execute_SrcPlugin_addSub_2[5] system_cpu.decode_to_execute_SRC2[5] system_cpu._zz_execute_SrcPlugin_addSub_2[6] system_cpu.decode_to_execute_SRC2[6] $abc$18544$new_n4605 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[18] system_cpu._zz_execute_SrcPlugin_addSub_2[18] system_cpu.decode_to_execute_SRC2[26] system_cpu._zz_execute_SrcPlugin_addSub_2[26] $abc$18544$new_n4606 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4608 system_cpu._zz_execute_SrcPlugin_addSub_2[4] system_cpu.decode_to_execute_SRC2[4] system_cpu.decode_to_execute_SRC2[1] system_cpu._zz_execute_SrcPlugin_addSub_2[1] $abc$18544$new_n4607 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[3] system_cpu._zz_execute_SrcPlugin_addSub_2[3] system_cpu.decode_to_execute_SRC2[19] system_cpu._zz_execute_SrcPlugin_addSub_2[19] $abc$18544$new_n4608 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4610 system_cpu._zz_execute_SrcPlugin_addSub_2[7] system_cpu.decode_to_execute_SRC2[7] system_cpu.decode_to_execute_SRC2[22] system_cpu._zz_execute_SrcPlugin_addSub_2[22] $abc$18544$new_n4609 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[8] system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu.decode_to_execute_SRC2[11] $abc$18544$new_n4610 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4612 system_cpu.decode_to_execute_SRC2[21] system_cpu._zz_execute_SrcPlugin_addSub_2[21] system_cpu.decode_to_execute_SRC2[27] system_cpu._zz_execute_SrcPlugin_addSub_2[27] $abc$18544$new_n4611 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu.decode_to_execute_SRC2[15] system_cpu._zz_execute_SrcPlugin_addSub_2[15] $abc$18544$new_n4612 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n4614 system_cpu._zz_execute_SrcPlugin_addSub_2[10] system_cpu.decode_to_execute_SRC2[10] system_cpu.decode_to_execute_SRC2[14] system_cpu._zz_execute_SrcPlugin_addSub_2[14] $abc$18544$new_n4613 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_SRC2[25] system_cpu._zz_execute_SrcPlugin_addSub_2[25] system_cpu.decode_to_execute_SRC2[29] system_cpu._zz_execute_SrcPlugin_addSub_2[29] $abc$18544$new_n4614 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$18544$new_n3670 $abc$18544$auto$rtlil.cc:2693:MuxGate$16642 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4617 system_cpu.decode_to_execute_DO_EBREAK $abc$18544$auto$rtlil.cc:2693:MuxGate$16644 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4618 system_cpu.DebugPlugin_debugUsed system_cpu.DebugPlugin_haltIt system_cpu.DebugPlugin_disableEbreak system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$18544$new_n4617 +11000 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$new_n4618 +111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$18544$new_n4619 +00 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4621 system_cpu.decode_to_execute_SRC2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16646 +001 1 +011 1 +100 1 +101 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 $abc$18544$new_n4180 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu._zz_decode_SRC2 $abc$18544$new_n4621 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$18544$new_n4623 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n3309 $abc$18544$auto$rtlil.cc:2693:MuxGate$16648 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n4624 $abc$18544$new_n4310 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4623 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4625 $abc$18544$new_n4624 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4625 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port1[31] system_cpu.decode_to_execute_RS2[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16650 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_RegFilePlugin_regFile_port0[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16652 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4629 system_cpu._zz_execute_BRANCH_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16654 +001 1 +011 1 +100 1 +101 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4629 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SHIFT_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4310 $abc$18544$auto$rtlil.cc:2693:MuxGate$16656 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu._zz_execute_ALU_BITWISE_CTRL[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16658 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4633 system_cpu.decode_to_execute_SRC_LESS_UNSIGNED system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$auto$rtlil.cc:2693:MuxGate$16660 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4633 +10 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ALU_CTRL[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4635 $abc$18544$auto$rtlil.cc:2693:MuxGate$16662 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$18544$new_n4635 +000 1 +010 1 +011 1 +.names $abc$18544$new_n3256 system_cpu._zz_memory_ENV_CTRL system_cpu._zz_execute_ENV_CTRL $abc$18544$auto$rtlil.cc:2693:MuxGate$16664 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_ENV_CTRL $abc$18544$new_n4618 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$18544$auto$rtlil.cc:2693:MuxGate$16666 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_IS_CSR system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4619 $abc$18544$auto$rtlil.cc:2693:MuxGate$16668 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names system_cpu.dBus_cmd_payload_wr $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16670 +10 1 +.names $abc$18544$new_n3309 system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.dBus_cmd_payload_wr $abc$18544$auto$rtlil.cc:2693:MuxGate$16672 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3256 system_cpu.execute_to_memory_REGFILE_WRITE_VALID system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$auto$rtlil.cc:2693:MuxGate$16674 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4643 system_cpu.decode_to_execute_REGFILE_WRITE_VALID $abc$18544$new_n4644 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$18544$auto$rtlil.cc:2693:MuxGate$16678 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$18544$new_n4619 $abc$18544$new_n4643 +00100 1 +00101 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$18544$new_n4644 +0000 1 +.names system_cpu.decode_to_execute_MEMORY_ENABLE $abc$18544$new_n3256 $abc$18544$auto$rtlil.cc:2693:MuxGate$16680 +01 1 +10 1 +11 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_MEMORY_ENABLE system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$18544$auto$rtlil.cc:2693:MuxGate$16682 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$18544$new_n4624 $abc$18544$new_n3309 system_cpu.decode_to_execute_SRC_USE_SUB_LESS $abc$18544$auto$rtlil.cc:2693:MuxGate$16684 +001 1 +010 1 +011 1 +.names $abc$18544$new_n3309 system_cpu.decode_to_execute_CSR_WRITE_OPCODE $abc$18544$new_n4649 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16686 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n4649 +1000 1 +.names $abc$18544$new_n3309 system_cpu._zz_decode_SRC2 system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$auto$rtlil.cc:2693:MuxGate$16690 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PWDATA[31] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16714 +001 1 +011 1 +110 1 +111 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PADDR[1] system_mainBusArbiter.io_dBus_cmd_valid system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$auto$rtlil.cc:2693:MuxGate$16718 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names io_apb_decoder.io_input_PSEL $abc$18544$new_n3934 apb3Router_1.io_input_PWRITE $abc$18544$auto$rtlil.cc:2693:MuxGate$16722 +010 1 +011 1 +101 1 +111 1 +.names $abc$18544$new_n3256 $abc$18544$new_n4656 $abc$18544$new_n4655 system_cpu.BranchPlugin_jumpInterface_payload[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16756 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4401 $abc$18544$new_n4400 $abc$18544$new_n4349 $abc$18544$new_n4655 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 $abc$18544$new_n4365 system_cpu.decode_to_execute_PC[31] system_cpu.decode_to_execute_RS1[31] $abc$18544$new_n4656 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16764 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] system_cpu.decode_to_execute_PC[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16766 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3309 system_cpu._zz_execute_SrcPlugin_addSub_2[11] system_cpu._zz_RegFilePlugin_regFile_port0[11] $abc$18544$new_n4131 $abc$18544$auto$rtlil.cc:2693:MuxGate$16788 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4661 system_cpu._zz_execute_SrcPlugin_addSub_2[4] $abc$18544$new_n4131 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$auto$rtlil.cc:2693:MuxGate$16792 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu._zz_RegFilePlugin_regFile_port0[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$18544$new_n4661 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3309 $abc$18544$new_n4663 system_cpu._zz_execute_SrcPlugin_addSub_2[31] $abc$18544$new_n4131 system_cpu._zz_RegFilePlugin_regFile_port0[31] $abc$18544$auto$rtlil.cc:2693:MuxGate$16794 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_decode_SRC2 system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n4663 +1110 1 +.names system_timer.interruptCtrl_1.pendings[0] system_timer.interruptCtrl_1.io_masks[0] system_timer.interruptCtrl_1.pendings[1] system_timer.interruptCtrl_1.io_masks[1] system_cpu.timerInterrupt +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_idcodeArea_ctrl_capture +1100 1 +.names apb3Router_1.selIndex[0] apb3Router_1.selIndex[1] $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +10 1 +.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +01 1 +10 1 +11 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_836 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$auto$opt_dff.cc:253:combine_resets$3598 +11111 1 +.names $abc$18544$new_n4670 $abc$18544$new_n3711 system_mainBusDecoder_logic_noHit +00 1 +.names $abc$18544$new_n4675 $abc$18544$new_n3716 $abc$18544$new_n4672 $abc$18544$new_n4671 $abc$18544$new_n3712 $abc$18544$new_n4670 +11110 1 +.names $abc$18544$new_n3718 $abc$18544$new_n3717 $abc$18544$new_n4671 +11 1 +.names $abc$18544$new_n4674 $abc$18544$new_n4673 $abc$18544$new_n4487 $abc$18544$new_n4484 $abc$18544$new_n4480 $abc$18544$new_n4672 +11111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[14] system_cpu.IBusSimplePlugin_cmd_payload_pc[17] system_mainBusArbiter.io_dBus_cmd_payload_address[14] system_mainBusArbiter.io_dBus_cmd_payload_address[17] $abc$18544$new_n4673 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[16] system_cpu.IBusSimplePlugin_cmd_payload_pc[19] system_mainBusArbiter.io_dBus_cmd_payload_address[16] system_mainBusArbiter.io_dBus_cmd_payload_address[19] $abc$18544$new_n4674 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[28] system_cpu.IBusSimplePlugin_cmd_payload_pc[30] system_mainBusArbiter.io_dBus_cmd_payload_address[28] system_mainBusArbiter.io_dBus_cmd_payload_address[30] $abc$18544$new_n4675 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.when_JtagTap_l120 +0000 1 +.names $abc$18544$new_n4678 system_uartCtrl.uartCtrl_1.clockDivider_counter[19] system_uartCtrl.uartCtrl_1.clockDivider_tick +10 1 +.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] $abc$18544$new_n4678 +10 1 +.names $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4679 +10 1 +.names $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4680 +10 1 +.names $abc$18544$new_n4685 $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[13] system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4681 +1100 1 +.names $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4682 +10 1 +.names $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[8] system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4683 +10000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$new_n4684 +00000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4685 +0000 1 +.names system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] +011 1 +101 1 +110 1 +111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_writeIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.uartCtrl_1.io_readBreak system_cpu.externalInterrupt +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$18544$new_n5026 $abc$18544$new_n2756 system_timer.prescaler_1.when_Prescaler_l17 +01 1 +10 1 +11 1 +.names $abc$18544$new_n3834 systemDebugger_1.io_mem_cmd_payload_wr $abc$18544$new_n3837 $abc$18544$new_n4035 toplevel_system_cpu_debug_bus_cmd_fire +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n3317 $abc$18544$new_n4009 $abc$18544$new_n3314 system_cpu.execute_arbitration_isValid $abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n4670 $abc$18544$new_n3933 system_ram.io_bus_cmd_fire +11 1 +.names system_ram.io_bus_cmd_fire $abc$18544$new_n3934 $abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] +10 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire $abc$18544$new_n4694 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_size[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +11001 1 +11010 1 +11011 1 +.names system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4694 +000 1 +.names $abc$18544$new_n4696 system_ram.io_bus_cmd_fire $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +11 1 +.names $abc$18544$new_n3934 system_mainBusArbiter.io_dBus_cmd_payload_address[1] system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_size[1] system_mainBusArbiter.io_dBus_cmd_payload_size[0] $abc$18544$new_n4696 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$new_n4694 $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +1100 1 +.names $abc$18544$new_n3934 system_ram.io_bus_cmd_fire system_mainBusArbiter.io_dBus_cmd_payload_address[0] system_mainBusArbiter.io_dBus_cmd_payload_address[1] $abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +1100 1 +.names system_uartCtrl.bridge_misc_doBreak $abc$18544$new_n3928 $abc$18544$new_n4700 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] +000 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n4701 system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n4700 +10010 1 +10011 1 +11000 1 +11010 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] $abc$18544$new_n4702 $abc$18544$new_n4704 $abc$18544$new_n4701 +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4703 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] $abc$18544$new_n4702 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] $abc$18544$new_n4703 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4705 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] $abc$18544$new_n4704 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] $abc$18544$new_n4705 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names system_uartCtrl.uartCtrl_1.rx.stateMachine_parity system_uartCtrl.uartCtrl_1.rx.sampler_value $abc$18544$new_n2991 $abc$18544$new_n3010 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[0] +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[1] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$18544$new_n2991 system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] $abc$18544$new_n2997 system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3916[2] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names system_uartCtrl.bridge_misc_breakDetected system_uartCtrl.when_BusSlaveFactory_l347_2 $abc$18544$new_n3957 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] +00010 1 +00110 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n3957 system_uartCtrl.when_BusSlaveFactory_l347_3 system_uartCtrl.bridge_misc_doBreak system_uartCtrl.when_BusSlaveFactory_l379 $abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4713 $abc$18544$new_n4723 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 apb3Router_1._zz_io_input_PRDATA[0] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4714 $abc$18544$new_n4722 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] $abc$18544$new_n4713 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4715 $abc$18544$new_n4718 system_timer._zz_io_limit[0] $abc$18544$new_n2757 $abc$18544$new_n4714 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4716 $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[0] $abc$18544$new_n4715 +100 1 +101 1 +110 1 +.names system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n2740 system_timer.timerA.counter[0] $abc$18544$new_n4717 $abc$18544$new_n4716 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3893 $abc$18544$new_n3975 $abc$18544$new_n4717 +11 1 +.names $abc$18544$new_n4720 $abc$18544$new_n4719 $abc$18544$new_n3969 system_timer.timerB.counter[0] $abc$18544$new_n4718 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$18544$new_n2722 $abc$18544$new_n3969 system_timer.system_timer_timerB_io_limit_driver[0] system_timer.timerBBridge_ticksEnable[0] $abc$18544$new_n2713 $abc$18544$new_n4719 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_timer.interruptCtrl_1.io_masks[0] $abc$18544$new_n2822 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n4720 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names apb3Router_1.io_input_PADDR[4] $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[5] apb3Router_1.io_input_PADDR[6] apb3Router_1.io_input_PADDR[7] $abc$18544$new_n4721 +11000 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[0] $abc$18544$new_n2723 io_gpioA_write[0] $abc$18544$new_n4722 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n2714 apb3Router_1.io_input_PADDR[4] system_uartCtrl.bridge_misc_readError system_uartCtrl.bridge_read_streamBreaked_payload[0] $abc$18544$new_n4723 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4725 $abc$18544$new_n4734 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[1] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4726 $abc$18544$new_n4733 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3958 system_uartCtrl.bridge_misc_readOverflowError $abc$18544$new_n4725 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4727 $abc$18544$new_n4732 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n2822 $abc$18544$new_n4726 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4730 $abc$18544$new_n4728 $abc$18544$new_n2757 system_timer._zz_io_limit[1] $abc$18544$new_n4727 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4729 $abc$18544$new_n2722 $abc$18544$new_n2713 $abc$18544$new_n3969 $abc$18544$new_n4728 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[1] system_timer.system_timer_timerB_io_limit_driver[1] system_timer.timerBBridge_ticksEnable[1] $abc$18544$new_n4729 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n2717 system_timer.timerABridge_ticksEnable[1] system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 system_timer.interruptCtrl_1.io_masks[1] $abc$18544$new_n4730 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4717 system_timer.timerA.counter[1] $abc$18544$new_n2740 system_timer.system_timer_timerA_io_limit_driver[1] $abc$18544$new_n4732 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[1] $abc$18544$new_n3042 $abc$18544$new_n3963 system_uartCtrl.bridge_interruptCtrl_readIntEnable $abc$18544$new_n4733 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[1] $abc$18544$new_n2723 io_gpioA_write[1] $abc$18544$new_n4734 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4736 system_uartCtrl.bridge_read_streamBreaked_payload[2] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[2] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4740 $abc$18544$new_n4739 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4738 $abc$18544$new_n4736 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n4717 $abc$18544$new_n3969 $abc$18544$new_n2722 $abc$18544$new_n4737 +000 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[2] system_timer.system_timer_timerB_io_limit_driver[2] system_timer.timerA.counter[2] $abc$18544$new_n4738 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[2] $abc$18544$new_n2740 system_timer._zz_io_limit[2] $abc$18544$new_n2757 $abc$18544$new_n4739 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4741 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] $abc$18544$new_n2714 $abc$18544$new_n4740 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[2] $abc$18544$new_n2723 io_gpioA_write[2] $abc$18544$new_n4741 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3042 $abc$18544$new_n4742 +11 1 +.names $abc$18544$new_n4744 system_uartCtrl.bridge_read_streamBreaked_payload[3] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[3] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n4747 $abc$18544$new_n4746 $abc$18544$new_n4737 $abc$18544$new_n4745 $abc$18544$new_n4744 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerA.counter[3] $abc$18544$new_n4745 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[3] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[3] $abc$18544$new_n4746 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n4748 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] $abc$18544$new_n4747 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[3] $abc$18544$new_n2723 io_gpioA_write[3] $abc$18544$new_n4748 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4750 system_uartCtrl.bridge_read_streamBreaked_payload[4] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[4] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4753 $abc$18544$new_n4752 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4751 $abc$18544$new_n4750 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] system_timer.timerA.counter[4] $abc$18544$new_n4751 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n2740 system_timer._zz_io_limit[4] $abc$18544$new_n2757 $abc$18544$new_n4752 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4754 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] $abc$18544$new_n2714 $abc$18544$new_n4753 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[4] $abc$18544$new_n2723 io_gpioA_write[4] $abc$18544$new_n4754 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4756 system_uartCtrl.bridge_read_streamBreaked_payload[5] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[5] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4759 $abc$18544$new_n4758 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4757 $abc$18544$new_n4756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[5] system_timer.system_timer_timerB_io_limit_driver[5] system_timer.timerA.counter[5] $abc$18544$new_n4757 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[5] $abc$18544$new_n2740 system_timer._zz_io_limit[5] $abc$18544$new_n2757 $abc$18544$new_n4758 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4760 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] $abc$18544$new_n2714 $abc$18544$new_n4759 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[5] $abc$18544$new_n2723 io_gpioA_write[5] $abc$18544$new_n4760 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4762 system_uartCtrl.bridge_read_streamBreaked_payload[6] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[6] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4765 $abc$18544$new_n4764 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4763 $abc$18544$new_n4762 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[6] system_timer.system_timer_timerB_io_limit_driver[6] system_timer.timerA.counter[6] $abc$18544$new_n4763 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[6] $abc$18544$new_n2740 system_timer._zz_io_limit[6] $abc$18544$new_n2757 $abc$18544$new_n4764 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4766 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] $abc$18544$new_n2714 $abc$18544$new_n4765 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[6] $abc$18544$new_n2723 io_gpioA_write[6] $abc$18544$new_n4766 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4768 system_uartCtrl.bridge_read_streamBreaked_payload[7] $abc$18544$new_n4742 apb3Router_1._zz_io_input_PRDATA[7] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$18544$new_n4771 $abc$18544$new_n4770 apb3Router_1.selIndex[1] $abc$18544$new_n4737 $abc$18544$new_n4769 $abc$18544$new_n4768 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[7] system_timer.system_timer_timerB_io_limit_driver[7] system_timer.timerA.counter[7] $abc$18544$new_n4769 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[7] $abc$18544$new_n2740 system_timer._zz_io_limit[7] $abc$18544$new_n2757 $abc$18544$new_n4770 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4772 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] $abc$18544$new_n2714 $abc$18544$new_n4771 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[7] $abc$18544$new_n2723 io_gpioA_write[7] $abc$18544$new_n4772 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names apb3Router_1.selIndex[1] apb3Router_1.selIndex[0] $abc$18544$new_n4774 $abc$18544$new_n4777 $abc$18544$new_n4779 apb3Router_1._zz_io_input_PRDATA[8] +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$new_n4776 $abc$18544$new_n4737 $abc$18544$new_n4775 $abc$18544$new_n4774 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[8] system_timer.system_timer_timerB_io_limit_driver[8] system_timer.timerA.counter[8] $abc$18544$new_n4775 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[8] $abc$18544$new_n2740 system_timer._zz_io_limit[8] $abc$18544$new_n2757 $abc$18544$new_n4776 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4778 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] $abc$18544$new_n4777 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[8] $abc$18544$new_n2723 io_gpioA_write[8] $abc$18544$new_n4778 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n3958 system_uartCtrl.bridge_interruptCtrl_writeIntEnable $abc$18544$new_n3963 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid $abc$18544$new_n4779 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4781 $abc$18544$new_n4787 $abc$18544$new_n4737 $abc$18544$new_n4786 apb3Router_1._zz_io_input_PRDATA[9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4782 $abc$18544$new_n4784 $abc$18544$new_n3958 $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP system_uartCtrl.bridge_misc_breakDetected $abc$18544$new_n4781 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names system_uartCtrl.bridge_interruptCtrl_readIntEnable system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4783 system_uartCtrl.uartCtrl_1.io_readBreak $abc$18544$new_n4782 +1110 1 +.names $abc$18544$flatten\apb3Router_1.$procmux$3225_CMP $abc$18544$new_n3963 $abc$18544$new_n4783 +11 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4785 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] $abc$18544$new_n2714 $abc$18544$new_n4784 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[9] $abc$18544$new_n2723 io_gpioA_write[9] $abc$18544$new_n4785 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[9] system_timer.system_timer_timerB_io_limit_driver[9] system_timer.timerA.counter[9] $abc$18544$new_n4786 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[9] $abc$18544$new_n2740 system_timer._zz_io_limit[9] $abc$18544$new_n2757 $abc$18544$new_n4787 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4789 $abc$18544$new_n4792 $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid apb3Router_1._zz_io_input_PRDATA[15] +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names apb3Router_1.selIndex[1] $abc$18544$new_n4791 $abc$18544$new_n4737 $abc$18544$new_n4790 $abc$18544$new_n4789 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerA.counter[15] $abc$18544$new_n4790 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[15] $abc$18544$new_n2740 system_timer._zz_io_limit[15] $abc$18544$new_n2757 $abc$18544$new_n4791 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4793 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] $abc$18544$new_n2714 $abc$18544$new_n4792 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[15] $abc$18544$new_n2723 io_gpioA_write[15] $abc$18544$new_n4793 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4795 $abc$18544$new_n4798 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[16] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4797 $abc$18544$new_n4796 $abc$18544$new_n4742 system_uartCtrl.uartCtrl_1.io_readBreak system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid $abc$18544$new_n4795 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4796 +101 1 +110 1 +.names apb3Router_1.selIndex[1] system_timer.timerBBridge_clearsEnable $abc$18544$new_n2713 system_timer.timerABridge_clearsEnable $abc$18544$new_n2717 $abc$18544$new_n4797 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[16] $abc$18544$new_n2723 io_gpioA_write[16] $abc$18544$new_n4798 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4800 $abc$18544$new_n4801 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[17] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4783 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4800 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[17] $abc$18544$new_n2723 io_gpioA_write[17] $abc$18544$new_n4801 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4805 $abc$18544$new_n4783 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4803 apb3Router_1._zz_io_input_PRDATA[18] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4804 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] $abc$18544$new_n4803 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[18] $abc$18544$new_n2723 io_gpioA_write[18] $abc$18544$new_n4804 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n3038 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4805 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4810 $abc$18544$new_n4809 $abc$18544$new_n4807 apb3Router_1._zz_io_input_PRDATA[19] +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4808 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] $abc$18544$new_n2714 $abc$18544$new_n4807 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[19] $abc$18544$new_n2723 io_gpioA_write[19] $abc$18544$new_n4808 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n3038 $abc$18544$new_n4809 +00000 1 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4810 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4812 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4814 apb3Router_1._zz_io_input_PRDATA[20] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] $abc$18544$new_n4813 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] $abc$18544$new_n4812 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4809 $abc$18544$new_n4813 +00001 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names $abc$18544$new_n4815 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] $abc$18544$new_n4814 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[20] $abc$18544$new_n2723 io_gpioA_write[20] $abc$18544$new_n4815 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] $abc$18544$new_n4817 apb3Router_1._zz_io_input_PRDATA[24] +0001 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4818 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] $abc$18544$new_n2714 $abc$18544$new_n4817 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[24] $abc$18544$new_n2723 io_gpioA_write[24] $abc$18544$new_n4818 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4820 $abc$18544$new_n4821 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] $abc$18544$new_n2714 apb3Router_1._zz_io_input_PRDATA[25] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] $abc$18544$new_n4820 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[25] $abc$18544$new_n2723 io_gpioA_write[25] $abc$18544$new_n4821 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] $abc$18544$new_n4825 $abc$18544$new_n4823 apb3Router_1._zz_io_input_PRDATA[26] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4824 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] $abc$18544$new_n2714 $abc$18544$new_n4823 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[26] $abc$18544$new_n2723 io_gpioA_write[26] $abc$18544$new_n4824 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3073 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] $abc$18544$new_n4825 +000 1 +010 1 +011 1 +.names $abc$18544$new_n4783 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n4827 $abc$18544$new_n4828 apb3Router_1._zz_io_input_PRDATA[27] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] $abc$18544$new_n4825 $abc$18544$new_n4827 +001 1 +100 1 +101 1 +111 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4829 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[27] $abc$18544$new_n2714 $abc$18544$new_n4828 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[27] $abc$18544$new_n2723 io_gpioA_write[27] $abc$18544$new_n4829 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4783 $abc$18544$new_n4831 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4832 apb3Router_1._zz_io_input_PRDATA[28] +0000 1 +0100 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] $abc$18544$new_n4827 $abc$18544$new_n4831 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$18544$new_n4833 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[28] $abc$18544$new_n4832 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[28] $abc$18544$new_n2723 io_gpioA_write[28] $abc$18544$new_n4833 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[0] system_ram._zz_ram_port0[0] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[0] +001 1 +011 1 +110 1 +111 1 +.names system_mainBusDecoder_logic_rspSourceId system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[1] system_ram._zz_ram_port0[1] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[1] +001 1 +011 1 +110 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[8] system_mainBusArbiter.io_dBus_cmd_payload_address[8] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[9] system_mainBusArbiter.io_dBus_cmd_payload_address[9] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[10] system_mainBusArbiter.io_dBus_cmd_payload_address[10] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] +010 1 +011 1 +101 1 +111 1 +.names system_mainBusArbiter.io_dBus_cmd_valid system_cpu.IBusSimplePlugin_cmd_payload_pc[11] system_mainBusArbiter.io_dBus_cmd_payload_address[11] system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] +010 1 +011 1 +101 1 +111 1 +.names jtagBridge_1.jtag_tap_fsm_state[3] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[0] +00000 1 +00001 1 +00100 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11111 1 +.names jtagBridge_1.jtag_tap_fsm_state[0] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[1] +00001 1 +00011 1 +00101 1 +00111 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +11010 1 +11110 1 +.names jtagBridge_1.jtag_tap_fsm_state[1] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[0] jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[2] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10100 1 +10101 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names jtagBridge_1.jtag_tap_fsm_state[0] io_jtag_tms jtagBridge_1.jtag_tap_fsm_state[3] jtagBridge_1.jtag_tap_fsm_state[1] jtagBridge_1.jtag_tap_fsm_state[2] jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[3] +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names system_cpu._zz_5 system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu._zz_1 +01 1 +10 1 +11 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[0] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[1] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[2] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[3] +10 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_address[4] +10 1 +.names system_cpu._zz_5 $abc$18544$new_n3822 system_cpu.lastStageRegFileWrite_payload_data[0] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n4060 system_cpu.lastStageRegFileWrite_payload_data[1] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2985 system_cpu.lastStageRegFileWrite_payload_data[2] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2982 system_cpu.lastStageRegFileWrite_payload_data[3] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2978 system_cpu.lastStageRegFileWrite_payload_data[4] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2974 system_cpu.lastStageRegFileWrite_payload_data[5] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2971 system_cpu.lastStageRegFileWrite_payload_data[6] +00 1 +.names system_cpu._zz_5 $abc$18544$new_n2969 system_cpu.lastStageRegFileWrite_payload_data[7] +00 1 +.names $abc$18544$new_n2966 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[8] +10 1 +.names $abc$18544$new_n2963 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[9] +10 1 +.names $abc$18544$new_n2960 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[10] +10 1 +.names $abc$18544$new_n2957 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[11] +10 1 +.names $abc$18544$new_n2954 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[12] +10 1 +.names $abc$18544$new_n2951 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[13] +10 1 +.names $abc$18544$new_n2948 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[14] +10 1 +.names $abc$18544$new_n2945 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[15] +10 1 +.names $abc$18544$new_n2943 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[16] +10 1 +.names $abc$18544$new_n2941 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[17] +10 1 +.names $abc$18544$new_n2939 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[18] +10 1 +.names $abc$18544$new_n2937 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[19] +10 1 +.names $abc$18544$new_n2935 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[20] +10 1 +.names $abc$18544$new_n2933 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[21] +10 1 +.names $abc$18544$new_n2931 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[22] +10 1 +.names $abc$18544$new_n2929 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[23] +10 1 +.names $abc$18544$new_n2927 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[24] +10 1 +.names $abc$18544$new_n2925 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[25] +10 1 +.names $abc$18544$new_n2923 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[26] +10 1 +.names $abc$18544$new_n2921 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[27] +10 1 +.names $abc$18544$new_n2919 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[28] +10 1 +.names $abc$18544$new_n2917 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[29] +10 1 +.names $abc$18544$new_n2907 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[30] +10 1 +.names $abc$18544$new_n4064 system_cpu._zz_5 system_cpu.lastStageRegFileWrite_payload_data[31] +10 1 +.names system_cpu.memory_arbitration_isValid $abc$18544$new_n3722 $abc$18544$new_n3256 $abc$18544$flatten\system_cpu.$0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$18544$new_n4884 system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] $abc$18544$new_n4885 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names system_cpu.decode_to_execute_CSR_WRITE_OPCODE system_cpu.decode_to_execute_IS_CSR system_cpu.execute_CsrPlugin_csr_768 system_cpu.execute_arbitration_isValid $abc$18544$new_n3309 $abc$18544$new_n4884 +11111 1 +.names $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MPIE system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n3723 $abc$18544$new_n4885 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n4884 $abc$18544$new_n4000 $abc$18544$new_n4887 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$18544$new_n3723 $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MIE system_cpu.CsrPlugin_mstatus_MPIE $abc$18544$new_n4887 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$18544$new_n4889 $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MPP[0] $abc$18544$new_n3723 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][0] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4884 $abc$18544$new_n4002 $abc$18544$new_n4890 $abc$18544$new_n4889 +110 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[12] system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] system_cpu.CsrPlugin_mstatus_MPP[1] system_cpu.execute_CsrPlugin_csr_768 $abc$18544$new_n4890 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n4889 $abc$18544$new_n3725 system_cpu.CsrPlugin_mstatus_MPP[1] $abc$18544$new_n3723 $abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.IBusSimplePlugin_pending_value[0] $abc$18544$new_n4893 $abc$18544$new_n4005 system_cpu.IBusSimplePlugin_pending_next[0] +001 1 +010 1 +100 1 +111 1 +.names $abc$18544$new_n3319 $abc$18544$new_n3850 $abc$18544$new_n3320 $abc$18544$new_n4893 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3851 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] $abc$18544$new_n3319 system_cpu.IBusSimplePlugin_pending_next[0] $abc$18544$new_n3320 $abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_cpu.IBusSimplePlugin_pending_value[1] $abc$18544$new_n4897 $abc$18544$new_n4896 system_cpu.IBusSimplePlugin_pending_next[1] +001 1 +010 1 +100 1 +111 1 +.names $abc$18544$new_n4005 system_cpu.IBusSimplePlugin_pending_value[0] $abc$18544$new_n4893 $abc$18544$new_n4896 +101 1 +110 1 +.names $abc$18544$new_n4893 system_cpu.IBusSimplePlugin_pending_value[0] $abc$18544$new_n4897 +10 1 +.names $abc$18544$new_n3851 system_cpu.IBusSimplePlugin_pending_next[1] $abc$18544$new_n4899 $abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] +010 1 +011 1 +100 1 +110 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] $abc$18544$new_n3319 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$18544$new_n4899 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +.names system_cpu.IBusSimplePlugin_pending_value[1] system_cpu.IBusSimplePlugin_pending_value[2] $abc$18544$new_n4897 $abc$18544$new_n4896 system_cpu.IBusSimplePlugin_pending_next[2] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$18544$new_n3851 system_cpu.IBusSimplePlugin_pending_next[2] $abc$18544$new_n4902 $abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] +010 1 +011 1 +101 1 +111 1 +.names system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$18544$new_n3319 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] $abc$18544$new_n4902 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu.CsrPlugin_mstatus_MIE $abc$18544$new_n3723 $abc$18544$new_n4020 $abc$18544$flatten\system_cpu.$0\CsrPlugin_interrupt_valid[0:0] +100 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] system_cpu.decode_INSTRUCTION_ANTICIPATED[15] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[15] systemDebugger_1._zz_io_mem_cmd_payload_address[47] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][15] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] system_cpu.decode_INSTRUCTION_ANTICIPATED[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[16] system_cpu.when_DebugPlugin_l284 $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][16] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] system_cpu.decode_INSTRUCTION_ANTICIPATED[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[17] system_cpu.when_DebugPlugin_l285 $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][17] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] system_cpu.decode_INSTRUCTION_ANTICIPATED[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[18] system_cpu.when_DebugPlugin_l288 $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][18] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] system_cpu.decode_INSTRUCTION_ANTICIPATED[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[19] systemDebugger_1._zz_io_mem_cmd_payload_address[51] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][19] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] system_cpu.decode_INSTRUCTION_ANTICIPATED[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[20] systemDebugger_1._zz_io_mem_cmd_payload_address[52] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][20] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] system_cpu.decode_INSTRUCTION_ANTICIPATED[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[21] systemDebugger_1._zz_io_mem_cmd_payload_address[53] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][21] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] system_cpu.decode_INSTRUCTION_ANTICIPATED[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[22] systemDebugger_1._zz_io_mem_cmd_payload_address[54] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][22] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] system_cpu.decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[23] systemDebugger_1._zz_io_mem_cmd_payload_address[55] $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][23] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n3268 system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] system_cpu.decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$18544$new_n3352 system_cpu.decode_INSTRUCTION_ANTICIPATED[24] system_cpu.when_DebugPlugin_l284_1 $abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][24] +001 1 +011 1 +110 1 +111 1 +.names $abc$18544$new_n4925 $abc$18544$new_n4008 $abc$18544$new_n3317 $abc$18544$new_n3852 $abc$18544$flatten\system_cpu.$0\DebugPlugin_haltIt[0:0] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l285_1 system_cpu.DebugPlugin_haltIt system_cpu.when_DebugPlugin_l285 $abc$18544$new_n4925 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$18544$new_n3852 system_cpu.DebugPlugin_haltedByBreak $abc$18544$new_n4026 system_cpu.when_DebugPlugin_l285_1 $abc$18544$flatten\system_cpu.$0\DebugPlugin_haltedByBreak[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$auto$rtlil.cc:2582:Mux$3954[0] +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] $abc$18544$new_n4929 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] $abc$18544$new_n3016 $abc$18544$auto$rtlil.cc:2582:Mux$3954[1] +0011 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] $abc$18544$new_n4929 +110 1 +.names system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] $abc$18544$new_n4929 system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] $abc$18544$new_n3016 $abc$18544$auto$rtlil.cc:2582:Mux$3954[2] +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names io_apb_decoder.io_input_PSEL apb3Router_1.io_input_PENABLE $abc$18544$flatten\system_apbBridge.$0\state[0:0] +10 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4937 $abc$18544$new_n4940 $abc$18544$new_n4737 $abc$18544$new_n4939 $abc$18544$auto$rtlil.cc:2582:Mux$3626[10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4938 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[10] $abc$18544$new_n4937 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[10] $abc$18544$new_n2723 io_gpioA_write[10] $abc$18544$new_n4938 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[10] system_timer.system_timer_timerB_io_limit_driver[10] system_timer.timerA.counter[10] $abc$18544$new_n4939 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[10] $abc$18544$new_n2740 system_timer._zz_io_limit[10] $abc$18544$new_n2757 $abc$18544$new_n4940 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4942 $abc$18544$new_n4945 $abc$18544$new_n4737 $abc$18544$new_n4944 $abc$18544$auto$rtlil.cc:2582:Mux$3626[11] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4943 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[11] $abc$18544$new_n4942 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[11] $abc$18544$new_n2723 io_gpioA_write[11] $abc$18544$new_n4943 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[11] system_timer.system_timer_timerB_io_limit_driver[11] system_timer.timerA.counter[11] $abc$18544$new_n4944 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[11] $abc$18544$new_n2740 system_timer._zz_io_limit[11] $abc$18544$new_n2757 $abc$18544$new_n4945 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4947 $abc$18544$new_n4950 $abc$18544$new_n4737 $abc$18544$new_n4949 $abc$18544$auto$rtlil.cc:2582:Mux$3626[12] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$18544$new_n4948 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[12] $abc$18544$new_n4947 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[12] $abc$18544$new_n2723 io_gpioA_write[12] $abc$18544$new_n4948 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[12] system_timer.system_timer_timerB_io_limit_driver[12] system_timer.timerA.counter[12] $abc$18544$new_n4949 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[12] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[12] $abc$18544$new_n4950 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n4952 $abc$18544$new_n4955 $abc$18544$new_n4737 $abc$18544$new_n4954 $abc$18544$auto$rtlil.cc:2582:Mux$3626[13] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$18544$new_n4953 $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[13] $abc$18544$new_n4952 +0000 1 +0001 1 +0010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[13] $abc$18544$new_n2723 io_gpioA_write[13] $abc$18544$new_n4953 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[13] system_timer.system_timer_timerB_io_limit_driver[13] system_timer.timerA.counter[13] $abc$18544$new_n4954 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 system_timer.system_timer_timerA_io_limit_driver[13] $abc$18544$new_n2740 $abc$18544$new_n2757 system_timer._zz_io_limit[13] $abc$18544$new_n4955 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$auto$opt_dff.cc:253:combine_resets$4426 $abc$18544$new_n4957 $abc$18544$new_n4960 $abc$18544$new_n4737 $abc$18544$new_n4959 $abc$18544$auto$rtlil.cc:2582:Mux$3626[14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$18544$new_n4958 $abc$18544$new_n2714 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[14] $abc$18544$new_n4957 +000 1 +001 1 +010 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[14] $abc$18544$new_n2723 io_gpioA_write[14] $abc$18544$new_n4958 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n3969 $abc$18544$new_n2722 system_timer.timerB.counter[14] system_timer.system_timer_timerB_io_limit_driver[14] system_timer.timerA.counter[14] $abc$18544$new_n4959 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$new_n2740 system_timer._zz_io_limit[14] $abc$18544$new_n2757 $abc$18544$new_n4960 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$18544$new_n4962 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[21] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[21] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[21] $abc$18544$new_n2723 io_gpioA_write[21] $abc$18544$new_n4962 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4964 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[22] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[22] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[22] $abc$18544$new_n2723 io_gpioA_write[22] $abc$18544$new_n4964 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4966 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[23] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[23] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[23] $abc$18544$new_n2723 io_gpioA_write[23] $abc$18544$new_n4966 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4968 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[29] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[29] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[29] $abc$18544$new_n2723 io_gpioA_write[29] $abc$18544$new_n4968 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4970 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[30] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[30] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[30] $abc$18544$new_n2723 io_gpioA_write[30] $abc$18544$new_n4970 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$18544$new_n4972 system_gpioACtrl.io_gpio_read_buffercc.buffers_1[31] $abc$18544$new_n2714 apb3Router_1.io_outputs_0_PRDATA[31] +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$18544$new_n3893 io_gpioA_writeEnable[31] io_gpioA_write[31] $abc$18544$new_n2723 $abc$18544$new_n4972 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][1] +00 1 +11 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_tick system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][2] +0000 1 +1001 1 +1010 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[3] system_uartCtrl.uartCtrl_1.clockDivider_tick system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][3] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[4] system_uartCtrl.uartCtrl_1.clockDivider_counter[0] system_uartCtrl.uartCtrl_1.clockDivider_counter[2] system_uartCtrl.uartCtrl_1.clockDivider_counter[1] system_uartCtrl.uartCtrl_1.clockDivider_counter[3] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] +0010 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[7] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4981 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] +00 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[8] $abc$18544$new_n4684 system_uartCtrl.uartCtrl_1.clockDivider_counter[6] system_uartCtrl.uartCtrl_1.clockDivider_counter[5] system_uartCtrl.uartCtrl_1.clockDivider_counter[7] $abc$18544$new_n4981 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[9] $abc$18544$new_n4683 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] +0010 1 +1000 1 +1001 1 +1011 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n4987 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] +00 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] $abc$18544$new_n4987 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[14] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] +010 1 +100 1 +.names $abc$18544$new_n4682 system_uartCtrl.uartCtrl_1.clockDivider_counter[12] system_uartCtrl.uartCtrl_1.clockDivider_counter[10] system_uartCtrl.uartCtrl_1.clockDivider_counter[11] system_uartCtrl.uartCtrl_1.clockDivider_counter[13] $abc$18544$new_n4989 +10000 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[15] $abc$18544$new_n4989 system_uartCtrl.uartCtrl_1.clockDivider_counter[14] system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[16] $abc$18544$new_n4681 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[17] $abc$18544$new_n4680 system_uartCtrl.uartCtrl_1.clockDivider_tick $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] +010 1 +100 1 +.names $abc$18544$new_n4679 system_uartCtrl.uartCtrl_1.clockDivider_counter[18] system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] +010 1 +011 1 +101 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[19] $abc$18544$new_n4678 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] +10 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg $abc$18544$new_n3016 system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] +010 1 +100 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] +011 1 +100 1 +101 1 +110 1 +.names system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] system_uartCtrl.uartCtrl_1.clockDivider_tickReg system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_uartCtrl.uartCtrl_1.tx.stateMachine_parity $abc$18544$new_n3016 $abc$18544$new_n4700 $abc$18544$new_n3928 $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names system_uartCtrl.uartCtrl_1.rx.sampler_tick $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] $abc$18544$new_n3006 system_uartCtrl.uartCtrl_1.rx.sampler_tick system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$18544$new_n3972 system_timer.interruptCtrl_1.pendings[0] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$18544$new_n3967 system_timer.interruptCtrl_1.pendings[1] $abc$18544$new_n4721 $abc$18544$new_n2709 system_uartCtrl.when_BusSlaveFactory_l347_1 $abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[1] +01 1 +10 1 +.names system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[2] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[5] +01 1 +10 1 +.names system_timer.prescaler_1.counter[4] system_timer.prescaler_1.counter[3] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[1] system_timer.prescaler_1.counter[0] $abc$18544$new_n5009 +11111 1 +.names system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[6] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $auto$alumacc.cc:485:replace_alu$4095.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[9] +01 1 +10 1 +.names system_timer.prescaler_1.counter[8] system_timer.prescaler_1.counter[7] system_timer.prescaler_1.counter[6] system_timer.prescaler_1.counter[5] $abc$18544$new_n5009 $abc$18544$new_n5014 +11111 1 +.names system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[10] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $auto$alumacc.cc:485:replace_alu$4095.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[13] +01 1 +10 1 +.names system_timer.prescaler_1.counter[12] system_timer.prescaler_1.counter[11] system_timer.prescaler_1.counter[10] system_timer.prescaler_1.counter[9] $abc$18544$new_n5014 $abc$18544$new_n5019 +11111 1 +.names system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[14] +011 1 +100 1 +101 1 +110 1 +.names system_timer.prescaler_1.counter[15] system_timer.prescaler_1.counter[14] system_timer.prescaler_1.counter[13] $abc$18544$new_n5019 $auto$alumacc.cc:485:replace_alu$4095.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names system_timer.prescaler_1.counter[0] $auto$alumacc.cc:485:replace_alu$4095.X[0] +0 1 +.names system_uartCtrl.uartCtrl_1.clockDivider_counter[0] $abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] +0 1 +.names $abc$18544$new_n2792 system_timer.prescaler_1.counter[15] system_timer._zz_io_limit[15] system_timer.prescaler_1.counter[1] system_timer._zz_io_limit[1] $abc$18544$new_n5024 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5024 system_timer._zz_io_limit[2] system_timer.prescaler_1.counter[2] system_timer.prescaler_1.counter[5] system_timer._zz_io_limit[5] $abc$18544$new_n5025 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2786 $abc$18544$new_n5025 system_timer.prescaler_1.counter[11] system_timer._zz_io_limit[11] $abc$18544$new_n5026 +1100 1 +1111 1 +.names $abc$18544$new_n2803 system_timer.timerA.counter[15] system_timer.system_timer_timerA_io_limit_driver[15] system_timer.timerA.counter[0] system_timer.system_timer_timerA_io_limit_driver[0] $abc$18544$new_n5027 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5027 system_timer.timerA.counter[3] system_timer.system_timer_timerA_io_limit_driver[3] system_timer.timerA.counter[4] system_timer.system_timer_timerA_io_limit_driver[4] $abc$18544$new_n5028 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2796 $abc$18544$new_n5028 system_timer.timerA.counter[14] system_timer.system_timer_timerA_io_limit_driver[14] $abc$18544$new_n5029 +1100 1 +1111 1 +.names $abc$18544$new_n2845 system_timer.timerB.counter[15] system_timer.system_timer_timerB_io_limit_driver[15] system_timer.timerB.counter[0] system_timer.system_timer_timerB_io_limit_driver[0] $abc$18544$new_n5030 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5030 system_timer.timerB.counter[3] system_timer.system_timer_timerB_io_limit_driver[3] system_timer.timerB.counter[4] system_timer.system_timer_timerB_io_limit_driver[4] $abc$18544$new_n5031 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n2837 $abc$18544$new_n5031 system_timer.timerB.counter[14] system_timer.system_timer_timerB_io_limit_driver[14] $abc$18544$new_n5032 +1100 1 +1111 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5033 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n5033 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5034 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5034 system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5035 +100 1 +111 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] $abc$18544$new_n5036 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$18544$new_n5036 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] $abc$18544$new_n5037 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5037 system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] $abc$18544$new_n5038 +100 1 +111 1 +.names $abc$18544$new_n3288 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5039 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n5039 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5040 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n5040 $abc$18544$new_n5047 $abc$18544$new_n5044 $abc$18544$new_n3272 $abc$18544$new_n5041 +1000 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_valid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$18544$new_n5042 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5042 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$18544$new_n5043 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5043 system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$18544$new_n5044 +100 1 +111 1 +.names system_cpu.execute_arbitration_isValid system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5045 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu.decode_to_execute_REGFILE_WRITE_VALID system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5046 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5045 $abc$18544$new_n5046 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$18544$new_n5047 +1100 1 +1111 1 +.names $abc$18544$new_n3300 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$18544$new_n5048 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$18544$new_n5048 $abc$18544$new_n3299 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$18544$new_n5052 $abc$18544$new_n5049 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$18544$new_n3306 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$18544$new_n5049 $abc$18544$new_n3291 $abc$18544$new_n5050 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$18544$new_n3304 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$18544$new_n5051 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$18544$new_n5051 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$18544$new_n5052 +10000 1 +10011 1 +11100 1 +11111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[28] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[28] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5053 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n3465 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5053 $abc$18544$new_n3485 $abc$18544$new_n5054 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n5054 $abc$18544$new_n3486 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] $abc$18544$new_n3255 $abc$18544$auto$rtlil.cc:2693:MuxGate$15976 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names system_cpu._zz_execute_SrcPlugin_addSub_2[12] $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2[12] system_cpu._zz_execute_ALU_BITWISE_CTRL[1] system_cpu._zz_execute_ALU_BITWISE_CTRL[0] $abc$18544$new_n5056 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$18544$new_n3466 $abc$18544$new_n3473 system_cpu.decode_to_execute_SRC2_FORCE_ZERO $abc$18544$new_n5056 $abc$18544$new_n3589 $abc$18544$new_n5057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$18544$new_n3255 $abc$18544$new_n3592 system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] $abc$18544$new_n5057 $abc$18544$new_n3590 $abc$18544$auto$rtlil.cc:2693:MuxGate$16008 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names jtagBridge_1._zz_jtag_tap_isBypass[1] jtagBridge_1._zz_jtag_tap_isBypass[2] jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_idcodeArea_ctrl_tdo $abc$18544$new_n5059 +00001 1 +00011 1 +00101 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$18544$new_n5059 jtagBridge_1._zz_jtag_tap_isBypass[0] jtagBridge_1._zz_jtag_tap_isBypass[3] jtagBridge_1._zz_jtag_tap_isBypass[2] $abc$18544$new_n5060 +1100 1 +1111 1 +.names $abc$18544$new_n2864 $abc$18544$new_n3827 $abc$18544$new_n5060 jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment jtagBridge_1.jtag_tap_tdoUnbufferd +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14840 Q=system_cpu.DebugPlugin_busReadDataReg[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14838 Q=system_cpu.DebugPlugin_busReadDataReg[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14836 Q=system_cpu.DebugPlugin_busReadDataReg[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14834 Q=jtagBridge_1.io_remote_rsp_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14832 Q=jtagBridge_1.io_remote_rsp_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14830 Q=jtagBridge_1.io_remote_rsp_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14828 Q=jtagBridge_1.io_remote_rsp_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14826 Q=jtagBridge_1.io_remote_rsp_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14824 Q=jtagBridge_1.io_remote_rsp_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14822 Q=jtagBridge_1.io_remote_rsp_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14820 Q=jtagBridge_1.io_remote_rsp_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14818 Q=jtagBridge_1.io_remote_rsp_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14816 Q=jtagBridge_1.io_remote_rsp_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14814 Q=jtagBridge_1.io_remote_rsp_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14812 Q=jtagBridge_1.io_remote_rsp_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14810 Q=jtagBridge_1.io_remote_rsp_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14808 Q=jtagBridge_1.io_remote_rsp_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14806 Q=jtagBridge_1.io_remote_rsp_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14804 Q=jtagBridge_1.io_remote_rsp_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14802 Q=jtagBridge_1.io_remote_rsp_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14800 Q=jtagBridge_1.io_remote_rsp_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14798 Q=jtagBridge_1.io_remote_rsp_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14796 Q=jtagBridge_1.io_remote_rsp_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14794 Q=jtagBridge_1.io_remote_rsp_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14792 Q=jtagBridge_1.io_remote_rsp_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14790 Q=jtagBridge_1.io_remote_rsp_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14788 Q=jtagBridge_1.io_remote_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14786 Q=jtagBridge_1.io_remote_rsp_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14784 Q=jtagBridge_1.io_remote_rsp_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16774 Q=jtagBridge_1.io_remote_rsp_payload_data[31] +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\sampler_value[0:0] Q=system_uartCtrl.uartCtrl_1.rx.sampler_value S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tickReg Q=system_uartCtrl.uartCtrl_1.rx.sampler_tick R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16538 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_2 S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14782 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14780 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14778 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14776 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14774 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14772 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16536 Q=system_uartCtrl.uartCtrl_1.rx.break_counter[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3924 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=io_uart_rxd Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16564 Q=system_uartCtrl.bridge_interruptCtrl_readIntEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16566 Q=system_uartCtrl.bridge_interruptCtrl_writeIntEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16568 Q=system_timer.timerB.inhibitFull R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=system_uartCtrl.uartCtrl_1.io_readBreak Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_readBreak_regNext +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14770 Q=jtagBridge_1.jtag_readArea_ctrl_tdo +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14768 Q=jtagBridge_1.jtag_readArea_full_shifter[2] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14766 Q=jtagBridge_1.jtag_readArea_full_shifter[3] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14764 Q=jtagBridge_1.jtag_readArea_full_shifter[4] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14762 Q=jtagBridge_1.jtag_readArea_full_shifter[5] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14760 Q=jtagBridge_1.jtag_readArea_full_shifter[6] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14758 Q=jtagBridge_1.jtag_readArea_full_shifter[7] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14756 Q=jtagBridge_1.jtag_readArea_full_shifter[8] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14754 Q=jtagBridge_1.jtag_readArea_full_shifter[9] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14752 Q=jtagBridge_1.jtag_readArea_full_shifter[10] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14750 Q=jtagBridge_1.jtag_readArea_full_shifter[11] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14748 Q=jtagBridge_1.jtag_readArea_full_shifter[12] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14746 Q=jtagBridge_1.jtag_readArea_full_shifter[13] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14744 Q=jtagBridge_1.jtag_readArea_full_shifter[14] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14742 Q=jtagBridge_1.jtag_readArea_full_shifter[15] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14740 Q=jtagBridge_1.jtag_readArea_full_shifter[16] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14738 Q=jtagBridge_1.jtag_readArea_full_shifter[17] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14736 Q=jtagBridge_1.jtag_readArea_full_shifter[18] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14734 Q=jtagBridge_1.jtag_readArea_full_shifter[19] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14732 Q=jtagBridge_1.jtag_readArea_full_shifter[20] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14730 Q=jtagBridge_1.jtag_readArea_full_shifter[21] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14728 Q=jtagBridge_1.jtag_readArea_full_shifter[22] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14726 Q=jtagBridge_1.jtag_readArea_full_shifter[23] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14724 Q=jtagBridge_1.jtag_readArea_full_shifter[24] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14722 Q=jtagBridge_1.jtag_readArea_full_shifter[25] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14720 Q=jtagBridge_1.jtag_readArea_full_shifter[26] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14718 Q=jtagBridge_1.jtag_readArea_full_shifter[27] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14716 Q=jtagBridge_1.jtag_readArea_full_shifter[28] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14714 Q=jtagBridge_1.jtag_readArea_full_shifter[29] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14712 Q=jtagBridge_1.jtag_readArea_full_shifter[30] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14710 Q=jtagBridge_1.jtag_readArea_full_shifter[31] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14708 Q=jtagBridge_1.jtag_readArea_full_shifter[32] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16784 Q=jtagBridge_1.jtag_readArea_full_shifter[33] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16782 Q=jtagBridge_1.jtag_readArea_full_shifter[1] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16562 Q=system_uartCtrl.bridge_misc_readError R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_breakDetected[0:0] Q=system_uartCtrl.bridge_misc_breakDetected R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.$0\bridge_misc_doBreak[0:0] Q=system_uartCtrl.bridge_misc_doBreak R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][0] Q=system_timer.interruptCtrl_1.pendings[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_timer.\interruptCtrl_1.$0\pendings[1:0][1] Q=system_timer.interruptCtrl_1.pendings[1] R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14706 Q=system_timer.timerB.counter[0] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14704 Q=system_timer.timerB.counter[1] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14702 Q=system_timer.timerB.counter[2] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14700 Q=system_timer.timerB.counter[3] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14698 Q=system_timer.timerB.counter[4] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14696 Q=system_timer.timerB.counter[5] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14694 Q=system_timer.timerB.counter[6] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14692 Q=system_timer.timerB.counter[7] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14690 Q=system_timer.timerB.counter[8] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14688 Q=system_timer.timerB.counter[9] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14686 Q=system_timer.timerB.counter[10] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14684 Q=system_timer.timerB.counter[11] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14682 Q=system_timer.timerB.counter[12] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14680 Q=system_timer.timerB.counter[13] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14678 Q=system_timer.timerB.counter[14] R=system_timer.timerB.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16754 Q=system_timer.timerB.counter[15] R=system_timer.timerB.io_clear +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16570 Q=system_timer.timerA.inhibitFull R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.X[0] Q=system_timer.prescaler_1.counter[0] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[1] Q=system_timer.prescaler_1.counter[1] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[2] Q=system_timer.prescaler_1.counter[2] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[3] Q=system_timer.prescaler_1.counter[3] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[4] Q=system_timer.prescaler_1.counter[4] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[5] Q=system_timer.prescaler_1.counter[5] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[6] Q=system_timer.prescaler_1.counter[6] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[7] Q=system_timer.prescaler_1.counter[7] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[8] Q=system_timer.prescaler_1.counter[8] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[9] Q=system_timer.prescaler_1.counter[9] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[10] Q=system_timer.prescaler_1.counter[10] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[11] Q=system_timer.prescaler_1.counter[11] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[12] Q=system_timer.prescaler_1.counter[12] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[13] Q=system_timer.prescaler_1.counter[13] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[14] Q=system_timer.prescaler_1.counter[14] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt sdffr C=io_mainClk D=$auto$alumacc.cc:485:replace_alu$4095.Y[15] Q=system_timer.prescaler_1.counter[15] R=system_timer.prescaler_1.when_Prescaler_l17 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14676 Q=system_timer.interruptCtrl_1.io_masks[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16572 Q=system_timer.interruptCtrl_1.io_masks[1] R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14674 Q=system_timer.timerA.counter[0] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14672 Q=system_timer.timerA.counter[1] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14670 Q=system_timer.timerA.counter[2] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14668 Q=system_timer.timerA.counter[3] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14666 Q=system_timer.timerA.counter[4] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14664 Q=system_timer.timerA.counter[5] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14662 Q=system_timer.timerA.counter[6] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14660 Q=system_timer.timerA.counter[7] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14658 Q=system_timer.timerA.counter[8] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14656 Q=system_timer.timerA.counter[9] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14654 Q=system_timer.timerA.counter[10] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14652 Q=system_timer.timerA.counter[11] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14650 Q=system_timer.timerA.counter[12] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14648 Q=system_timer.timerA.counter[13] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14646 Q=system_timer.timerA.counter[14] R=system_timer.timerA.io_clear +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16752 Q=system_timer.timerA.counter[15] R=system_timer.timerA.io_clear +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16700 Q=system_cpu.CsrPlugin_interrupt_code[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][15] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][16] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][17] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][18] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][19] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][20] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][21] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][22] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][23] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\_zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31:0][24] Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14644 Q=system_timer._zz_io_limit[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14642 Q=system_timer._zz_io_limit[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14640 Q=system_timer._zz_io_limit[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14638 Q=system_timer._zz_io_limit[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14636 Q=system_timer._zz_io_limit[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14634 Q=system_timer._zz_io_limit[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14632 Q=system_timer._zz_io_limit[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14630 Q=system_timer._zz_io_limit[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14628 Q=system_timer._zz_io_limit[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14626 Q=system_timer._zz_io_limit[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14624 Q=system_timer._zz_io_limit[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14622 Q=system_timer._zz_io_limit[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14620 Q=system_timer._zz_io_limit[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14618 Q=system_timer._zz_io_limit[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14616 Q=system_timer._zz_io_limit[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16586 Q=system_timer._zz_io_limit[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14614 Q=system_timer.system_timer_timerA_io_limit_driver[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14612 Q=system_timer.system_timer_timerA_io_limit_driver[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14610 Q=system_timer.system_timer_timerA_io_limit_driver[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14608 Q=system_timer.system_timer_timerA_io_limit_driver[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14606 Q=system_timer.system_timer_timerA_io_limit_driver[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14604 Q=system_timer.system_timer_timerA_io_limit_driver[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14602 Q=system_timer.system_timer_timerA_io_limit_driver[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14600 Q=system_timer.system_timer_timerA_io_limit_driver[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14598 Q=system_timer.system_timer_timerA_io_limit_driver[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14596 Q=system_timer.system_timer_timerA_io_limit_driver[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14594 Q=system_timer.system_timer_timerA_io_limit_driver[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14592 Q=system_timer.system_timer_timerA_io_limit_driver[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14590 Q=system_timer.system_timer_timerA_io_limit_driver[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14588 Q=system_timer.system_timer_timerA_io_limit_driver[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14586 Q=system_timer.system_timer_timerA_io_limit_driver[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16584 Q=system_timer.system_timer_timerA_io_limit_driver[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14584 Q=system_timer.system_timer_timerB_io_limit_driver[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14582 Q=system_timer.system_timer_timerB_io_limit_driver[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14580 Q=system_timer.system_timer_timerB_io_limit_driver[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14578 Q=system_timer.system_timer_timerB_io_limit_driver[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14576 Q=system_timer.system_timer_timerB_io_limit_driver[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14574 Q=system_timer.system_timer_timerB_io_limit_driver[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14572 Q=system_timer.system_timer_timerB_io_limit_driver[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14570 Q=system_timer.system_timer_timerB_io_limit_driver[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14568 Q=system_timer.system_timer_timerB_io_limit_driver[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14566 Q=system_timer.system_timer_timerB_io_limit_driver[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14564 Q=system_timer.system_timer_timerB_io_limit_driver[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14562 Q=system_timer.system_timer_timerB_io_limit_driver[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14560 Q=system_timer.system_timer_timerB_io_limit_driver[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14558 Q=system_timer.system_timer_timerB_io_limit_driver[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14556 Q=system_timer.system_timer_timerB_io_limit_driver[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16582 Q=system_timer.system_timer_timerB_io_limit_driver[15] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14554 Q=system_timer.timerABridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16580 Q=system_timer.timerABridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16578 Q=system_timer.timerABridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14552 Q=system_timer.timerBBridge_ticksEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16576 Q=system_timer.timerBBridge_ticksEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16574 Q=system_timer.timerBBridge_clearsEnable R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex Q=apb3Router_1.selIndex[0] +.subckt dff C=io_mainClk D=apb3Router_1._zz_selIndex_1 Q=apb3Router_1.selIndex[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16516 Q=system_cpu.CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16760 Q=system_cpu.CsrPlugin_mcause_exceptionCode[3] +.subckt dffr C=io_mainClk D=toplevel_system_cpu_debug_bus_cmd_fire Q=jtagBridge_1.io_remote_rsp_fire R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt_regNext Q=toplevel_system_cpu_debug_resetOut_regNext +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16514 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16512 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16532 Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16530 Q=system_mainBusArbiter.io_dBus_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16510 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16508 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16506 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16504 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16502 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16500 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16498 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16496 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16494 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16492 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16490 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16488 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16486 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16484 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16482 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16480 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16478 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16476 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16474 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16472 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16470 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16468 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16466 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16464 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16462 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16460 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16458 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16456 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16454 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16452 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16450 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16528 Q=system_mainBusArbiter.io_dBus_cmd_payload_address[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16448 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16446 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16444 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16442 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16440 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16438 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16436 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16434 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16432 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16430 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16428 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16426 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16424 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16422 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16420 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16418 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16416 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16414 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16412 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16410 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16408 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16406 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16404 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16402 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16400 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16398 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16396 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16394 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16392 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16390 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16388 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16526 Q=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16386 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16524 Q=system_mainBusArbiter.io_dBus_cmd_payload_size[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16522 Q=system_mainBusDecoder_logic_rspSourceId +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16520 Q=system_mainBusArbiter.io_dBus_cmd_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_mainBusDecoder_logic_noHit Q=system_mainBusDecoder_logic_rspNoHit R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt sdffs C=io_mainClk D=resetCtrl_mainClkResetUnbuffered Q=apb3Router_1.resetCtrl_systemReset S=toplevel_system_cpu_debug_resetOut_regNext +.subckt dff C=io_mainClk D=io_asyncReset_buffercc.buffers_0 Q=io_asyncReset_buffercc.buffers_1 +.subckt dff C=io_mainClk D=io_asyncReset Q=io_asyncReset_buffercc.buffers_0 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16384 Q=io_gpioA_writeEnable[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16382 Q=io_gpioA_writeEnable[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16380 Q=io_gpioA_writeEnable[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16378 Q=io_gpioA_writeEnable[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16376 Q=io_gpioA_writeEnable[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16374 Q=io_gpioA_writeEnable[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16372 Q=io_gpioA_writeEnable[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16370 Q=io_gpioA_writeEnable[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16368 Q=io_gpioA_writeEnable[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16366 Q=io_gpioA_writeEnable[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16364 Q=io_gpioA_writeEnable[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16362 Q=io_gpioA_writeEnable[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16360 Q=io_gpioA_writeEnable[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16358 Q=io_gpioA_writeEnable[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16356 Q=io_gpioA_writeEnable[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16354 Q=io_gpioA_writeEnable[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16352 Q=io_gpioA_writeEnable[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16350 Q=io_gpioA_writeEnable[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16348 Q=io_gpioA_writeEnable[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16346 Q=io_gpioA_writeEnable[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16344 Q=io_gpioA_writeEnable[20] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16342 Q=io_gpioA_writeEnable[21] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16340 Q=io_gpioA_writeEnable[22] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16338 Q=io_gpioA_writeEnable[23] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16336 Q=io_gpioA_writeEnable[24] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16334 Q=io_gpioA_writeEnable[25] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16332 Q=io_gpioA_writeEnable[26] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16330 Q=io_gpioA_writeEnable[27] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16328 Q=io_gpioA_writeEnable[28] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16326 Q=io_gpioA_writeEnable[29] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16324 Q=io_gpioA_writeEnable[30] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16590 Q=io_gpioA_writeEnable[31] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16322 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16318 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16314 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16310 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16306 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16302 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16788 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16294 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16292 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16290 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16288 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16286 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16284 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16282 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16280 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16278 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16276 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16274 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16272 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16270 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16268 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16266 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16264 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16262 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16260 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16258 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16256 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16254 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16252 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16250 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16248 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16246 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16244 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16242 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16240 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16238 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16596 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16236 Q=resetCtrl_systemClkResetCounter[0] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16234 Q=resetCtrl_systemClkResetCounter[1] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16232 Q=resetCtrl_systemClkResetCounter[2] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16230 Q=resetCtrl_systemClkResetCounter[3] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16228 Q=resetCtrl_systemClkResetCounter[4] R=io_asyncReset_buffercc.buffers_1 +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16598 Q=resetCtrl_systemClkResetCounter[5] R=io_asyncReset_buffercc.buffers_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16630 Q=system_cpu.execute_CsrPlugin_csr_772 +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_interrupt_valid[0:0] Q=system_cpu.CsrPlugin_interrupt_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$true Q=system_cpu.IBusSimplePlugin_fetchPc_booted R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\writeBack_arbitration_isValid[0:0] Q=system_cpu.lastStageIsFiring R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16624 Q=system_cpu.memory_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16628 Q=system_cpu.execute_CsrPlugin_csr_834 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16626 Q=system_cpu.execute_arbitration_isValid R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[21] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[21] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[22] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[22] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[23] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[23] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[29] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[29] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[30] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[30] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt sdffr C=io_mainClk D=apb3Router_1.io_outputs_0_PRDATA[31] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[31] R=$abc$18544$auto$opt_dff.cc:253:combine_resets$4426 +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[0] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[0] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[1] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[1] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[2] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[2] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[3] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[3] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[4] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[4] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[5] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[5] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[6] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[6] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[7] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[7] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[8] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[8] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[9] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[9] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[15] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[15] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[16] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[16] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[17] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[17] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[18] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[18] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[19] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[19] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[20] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[20] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[24] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[24] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[25] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[25] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[26] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[26] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[27] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[27] +.subckt dff C=io_mainClk D=apb3Router_1._zz_io_input_PRDATA[28] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16226 Q=apb3Router_1.io_input_PADDR[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16224 Q=apb3Router_1.io_input_PADDR[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16222 Q=apb3Router_1.io_input_PADDR[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16220 Q=apb3Router_1.io_input_PADDR[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16218 Q=apb3Router_1.io_input_PADDR[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16216 Q=apb3Router_1.io_input_PADDR[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16206 Q=apb3Router_1.io_input_PADDR[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16204 Q=apb3Router_1.io_input_PADDR[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16202 Q=apb3Router_1.io_input_PADDR[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16200 Q=apb3Router_1.io_input_PADDR[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16198 Q=apb3Router_1.io_input_PADDR[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16196 Q=apb3Router_1.io_input_PADDR[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16194 Q=apb3Router_1.io_input_PADDR[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16192 Q=apb3Router_1.io_input_PADDR[19] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16168 Q=system_cpu.IBusSimplePlugin_injector_port_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16166 Q=system_cpu.IBusSimplePlugin_injector_port_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16600 Q=system_cpu.IBusSimplePlugin_injector_port_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16602 Q=system_cpu.execute_LightShifterPlugin_isActive R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16604 Q=system_cpu.CsrPlugin_pipelineLiberator_done R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_valid Q=system_cpu.HazardSimplePlugin_writeBackBuffer_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16606 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_1 R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][0] Q=system_cpu.CsrPlugin_mstatus_MPP[0] S=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPP[1:0][1] Q=system_cpu.CsrPlugin_mstatus_MPP[1] S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16616 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_isPipBusy[0:0] Q=system_cpu.DebugPlugin_isPipBusy +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16164 Q=jtagBridge_1.jtag_tap_tdoIr +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16160 Q=jtagBridge_1.jtag_tap_instructionShift[1] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16156 Q=jtagBridge_1.jtag_tap_instructionShift[2] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16778 Q=jtagBridge_1.jtag_tap_instructionShift[3] +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[0] Q=system_cpu.IBusSimplePlugin_pending_value[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[1] Q=system_cpu.IBusSimplePlugin_pending_value[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_cpu.IBusSimplePlugin_pending_next[2] Q=system_cpu.IBusSimplePlugin_pending_value[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16152 Q=system_cpu.DebugPlugin_busReadDataReg[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16772 Q=system_cpu.DebugPlugin_busReadDataReg[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[7] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[8] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[9] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[10] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[11] Q=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[12] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[13] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[14] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[28] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_INSTRUCTION[29] Q=system_cpu._zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16686 Q=system_cpu.decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16148 Q=system_cpu.CsrPlugin_mepc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16146 Q=system_cpu.CsrPlugin_mepc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16144 Q=system_cpu.CsrPlugin_mepc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16142 Q=system_cpu.CsrPlugin_mepc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16140 Q=system_cpu.CsrPlugin_mepc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16138 Q=system_cpu.CsrPlugin_mepc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16136 Q=system_cpu.CsrPlugin_mepc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16134 Q=system_cpu.CsrPlugin_mepc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16132 Q=system_cpu.CsrPlugin_mepc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16130 Q=system_cpu.CsrPlugin_mepc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16128 Q=system_cpu.CsrPlugin_mepc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16126 Q=system_cpu.CsrPlugin_mepc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16124 Q=system_cpu.CsrPlugin_mepc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16122 Q=system_cpu.CsrPlugin_mepc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16120 Q=system_cpu.CsrPlugin_mepc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16118 Q=system_cpu.CsrPlugin_mepc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16116 Q=system_cpu.CsrPlugin_mepc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16114 Q=system_cpu.CsrPlugin_mepc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16112 Q=system_cpu.CsrPlugin_mepc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16110 Q=system_cpu.CsrPlugin_mepc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16108 Q=system_cpu.CsrPlugin_mepc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16106 Q=system_cpu.CsrPlugin_mepc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16104 Q=system_cpu.CsrPlugin_mepc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16102 Q=system_cpu.CsrPlugin_mepc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16100 Q=system_cpu.CsrPlugin_mepc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16098 Q=system_cpu.CsrPlugin_mepc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16096 Q=system_cpu.CsrPlugin_mepc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16094 Q=system_cpu.CsrPlugin_mepc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16092 Q=system_cpu.CsrPlugin_mepc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16768 Q=system_cpu.CsrPlugin_mepc[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16622 Q=system_cpu.IBusSimplePlugin_fetchPc_inc R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16696 Q=system_cpu.CsrPlugin_interrupt_code[3] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16608 Q=system_cpu.CsrPlugin_pipelineLiberator_pcValids_0 R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16610 Q=system_cpu.CsrPlugin_mie_MSIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16090 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16088 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16086 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16084 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16082 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16080 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16078 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16076 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16074 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16072 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16070 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16068 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16066 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16064 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16062 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16060 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16058 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16056 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16054 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[20] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16052 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[21] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16050 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[22] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16048 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[23] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16046 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[24] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16044 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[25] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16042 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[26] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16040 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[27] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16038 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[28] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16036 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[29] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16034 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[30] R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16758 Q=system_cpu.IBusSimplePlugin_cmd_payload_pc[31] S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16634 Q=system_cpu.execute_CsrPlugin_csr_768 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16632 Q=system_cpu.execute_CsrPlugin_csr_836 +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16712 Q=io_apb_decoder.io_input_PSEL R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltIt[0:0] Q=system_cpu.DebugPlugin_haltIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16710 Q=system_cpu.DebugPlugin_resetIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\DebugPlugin_haltedByBreak[0:0] Q=system_cpu.DebugPlugin_haltedByBreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffs C=io_mainClk D=$false Q=system_cpu._zz_5 S=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16614 Q=system_cpu.CsrPlugin_mie_MEIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16612 Q=system_cpu.CsrPlugin_mie_MTIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16708 Q=system_cpu.DebugPlugin_stepIt R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16706 Q=system_cpu.DebugPlugin_debugUsed R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16704 Q=system_cpu.DebugPlugin_disableEbreak R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16638 Q=system_cpu.execute_to_memory_BRANCH_DO +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16032 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16030 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16028 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16026 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16024 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16022 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16020 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16018 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16016 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16014 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16012 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16010 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16008 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16006 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16004 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16002 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16000 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15998 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15996 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15994 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15992 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15990 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15988 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15986 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15984 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15982 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15980 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15978 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15976 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15974 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15972 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16640 Q=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=io_mainClk D=systemDebugger_1._zz_io_mem_cmd_payload_address[2] Q=system_cpu._zz_when_DebugPlugin_l257 +.subckt dff C=io_mainClk D=system_cpu.DebugPlugin_resetIt Q=system_cpu.DebugPlugin_resetIt_regNext +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[0] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[1] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[2] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[3] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[4] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[5] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[6] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[7] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[8] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[9] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[10] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[11] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[12] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[13] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[14] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[15] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[16] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[17] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[18] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[19] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[20] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[20] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[21] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[21] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[22] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[22] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[23] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[23] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[24] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[24] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[25] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[25] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[26] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[26] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[27] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[27] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[28] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[28] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[29] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[29] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[30] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[30] +.subckt dff C=io_mainClk D=_zz_system_mainBusDecoder_logic_masterPipelined_rsp_payload_data[31] Q=system_cpu.memory_to_writeBack_MEMORY_READ_DATA[31] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=system_cpu.memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15970 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16642 Q=system_cpu.execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15964 Q=system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15962 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15960 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15958 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15956 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15954 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15952 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15950 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15948 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15946 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15944 Q=system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15942 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15940 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15938 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15936 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15934 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15932 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15930 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15928 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16702 Q=system_cpu._zz_decode_SRC2 +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[0] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[1] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[2] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[3] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[4] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[5] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[6] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[7] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[8] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[9] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[10] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[11] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[12] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[13] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[14] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[15] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[16] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[17] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[18] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[19] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[20] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[21] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[22] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[23] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[24] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[25] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[26] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[27] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[28] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[29] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[30] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_DATA[31] Q=system_cpu.memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15926 Q=system_cpu.decode_to_execute_PC[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15924 Q=system_cpu.decode_to_execute_PC[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15922 Q=system_cpu.decode_to_execute_PC[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15920 Q=system_cpu.decode_to_execute_PC[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15918 Q=system_cpu.decode_to_execute_PC[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15916 Q=system_cpu.decode_to_execute_PC[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15914 Q=system_cpu.decode_to_execute_PC[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15912 Q=system_cpu.decode_to_execute_PC[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15910 Q=system_cpu.decode_to_execute_PC[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15908 Q=system_cpu.decode_to_execute_PC[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15906 Q=system_cpu.decode_to_execute_PC[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15904 Q=system_cpu.decode_to_execute_PC[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15902 Q=system_cpu.decode_to_execute_PC[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15900 Q=system_cpu.decode_to_execute_PC[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15898 Q=system_cpu.decode_to_execute_PC[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15896 Q=system_cpu.decode_to_execute_PC[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15894 Q=system_cpu.decode_to_execute_PC[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15892 Q=system_cpu.decode_to_execute_PC[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15890 Q=system_cpu.decode_to_execute_PC[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15888 Q=system_cpu.decode_to_execute_PC[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15886 Q=system_cpu.decode_to_execute_PC[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15884 Q=system_cpu.decode_to_execute_PC[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15882 Q=system_cpu.decode_to_execute_PC[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15880 Q=system_cpu.decode_to_execute_PC[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15878 Q=system_cpu.decode_to_execute_PC[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15876 Q=system_cpu.decode_to_execute_PC[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15874 Q=system_cpu.decode_to_execute_PC[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15872 Q=system_cpu.decode_to_execute_PC[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15870 Q=system_cpu.decode_to_execute_PC[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16766 Q=system_cpu.decode_to_execute_PC[31] +.subckt dff C=io_mainClk D=system_cpu.externalInterrupt Q=system_cpu.CsrPlugin_mip_MEIP +.subckt dff C=io_mainClk D=system_cpu.timerInterrupt Q=system_cpu.CsrPlugin_mip_MTIP +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15866 Q=system_cpu.BranchPlugin_jumpInterface_payload[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15864 Q=system_cpu.BranchPlugin_jumpInterface_payload[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15862 Q=system_cpu.BranchPlugin_jumpInterface_payload[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15860 Q=system_cpu.BranchPlugin_jumpInterface_payload[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15858 Q=system_cpu.BranchPlugin_jumpInterface_payload[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15856 Q=system_cpu.BranchPlugin_jumpInterface_payload[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15854 Q=system_cpu.BranchPlugin_jumpInterface_payload[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15852 Q=system_cpu.BranchPlugin_jumpInterface_payload[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15850 Q=system_cpu.BranchPlugin_jumpInterface_payload[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15848 Q=system_cpu.BranchPlugin_jumpInterface_payload[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15846 Q=system_cpu.BranchPlugin_jumpInterface_payload[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15844 Q=system_cpu.BranchPlugin_jumpInterface_payload[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15842 Q=system_cpu.BranchPlugin_jumpInterface_payload[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15840 Q=system_cpu.BranchPlugin_jumpInterface_payload[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15838 Q=system_cpu.BranchPlugin_jumpInterface_payload[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15836 Q=system_cpu.BranchPlugin_jumpInterface_payload[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15834 Q=system_cpu.BranchPlugin_jumpInterface_payload[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15832 Q=system_cpu.BranchPlugin_jumpInterface_payload[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15830 Q=system_cpu.BranchPlugin_jumpInterface_payload[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15828 Q=system_cpu.BranchPlugin_jumpInterface_payload[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15826 Q=system_cpu.BranchPlugin_jumpInterface_payload[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15824 Q=system_cpu.BranchPlugin_jumpInterface_payload[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15822 Q=system_cpu.BranchPlugin_jumpInterface_payload[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15820 Q=system_cpu.BranchPlugin_jumpInterface_payload[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15818 Q=system_cpu.BranchPlugin_jumpInterface_payload[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15816 Q=system_cpu.BranchPlugin_jumpInterface_payload[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15814 Q=system_cpu.BranchPlugin_jumpInterface_payload[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15812 Q=system_cpu.BranchPlugin_jumpInterface_payload[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15810 Q=system_cpu.BranchPlugin_jumpInterface_payload[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16756 Q=system_cpu.BranchPlugin_jumpInterface_payload[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15808 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15806 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15804 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15802 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15800 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15798 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15796 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15794 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15792 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15790 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15788 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15786 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15784 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15782 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15780 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15778 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15776 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15774 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15772 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15770 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15768 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15766 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15764 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15760 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15758 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15756 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15754 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15752 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16762 Q=system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[31] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=io_mainClk D=system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] Q=system_cpu.HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16620 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_input_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16618 Q=system_cpu.IBusSimplePlugin_iBusRsp_stages_1_output_m2sPipe_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15736 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15734 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15732 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15730 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15728 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15726 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15724 Q=system_cpu.switch_Misc_l241_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15722 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15720 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15718 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15716 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15714 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15712 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15710 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15708 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15706 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15704 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15702 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15700 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15698 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15696 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15694 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15692 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15690 Q=system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16690 Q=system_cpu._zz_execute_BranchPlugin_branch_src2 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15674 Q=system_cpu.execute_to_memory_INSTRUCTION[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15672 Q=system_cpu.execute_to_memory_INSTRUCTION[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15670 Q=system_cpu.execute_to_memory_INSTRUCTION[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15668 Q=system_cpu.execute_to_memory_INSTRUCTION[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15666 Q=system_cpu.execute_to_memory_INSTRUCTION[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15664 Q=system_cpu.execute_to_memory_INSTRUCTION[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15662 Q=system_cpu.execute_to_memory_INSTRUCTION[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15660 Q=system_cpu.execute_to_memory_INSTRUCTION[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15632 Q=system_cpu.execute_to_memory_INSTRUCTION[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15630 Q=system_cpu.execute_to_memory_INSTRUCTION[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15626 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15624 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15622 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15620 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16692 Q=system_cpu.execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16682 Q=system_cpu.decode_to_execute_MEMORY_ENABLE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16678 Q=system_cpu.decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16680 Q=system_cpu.execute_to_memory_MEMORY_ENABLE +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_REGFILE_WRITE_VALID Q=system_cpu._zz_lastStageRegFileWrite_valid +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MPIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MPIE R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_cpu.$0\CsrPlugin_mstatus_MIE[0:0] Q=system_cpu.CsrPlugin_mstatus_MIE R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16684 Q=system_cpu.decode_to_execute_SRC_USE_SUB_LESS +.subckt dff C=io_mainClk D=system_cpu.execute_to_memory_MEMORY_ENABLE Q=system_cpu.memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16674 Q=system_cpu.execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16670 Q=system_cpu.execute_to_memory_MEMORY_STORE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16668 Q=system_cpu.decode_to_execute_IS_CSR +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16666 Q=system_cpu._zz_execute_ENV_CTRL +.subckt dff C=io_mainClk D=system_cpu._zz_memory_ENV_CTRL Q=system_cpu._zz_writeBack_ENV_CTRL +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16672 Q=system_cpu.dBus_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15618 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16658 Q=system_cpu._zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15616 Q=system_cpu._zz_execute_ALU_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16662 Q=system_cpu._zz_execute_ALU_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15614 Q=system_cpu._zz_execute_SHIFT_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16656 Q=system_cpu._zz_execute_SHIFT_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15612 Q=system_cpu._zz_execute_BRANCH_CTRL[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16654 Q=system_cpu._zz_execute_BRANCH_CTRL[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15610 Q=system_cpu._zz_dBus_cmd_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15608 Q=system_cpu._zz_dBus_cmd_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15606 Q=system_cpu._zz_dBus_cmd_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15604 Q=system_cpu._zz_dBus_cmd_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15602 Q=system_cpu._zz_dBus_cmd_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15600 Q=system_cpu._zz_dBus_cmd_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15598 Q=system_cpu._zz_dBus_cmd_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15596 Q=system_cpu._zz_dBus_cmd_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15594 Q=system_cpu.decode_to_execute_RS2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15592 Q=system_cpu.decode_to_execute_RS2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15590 Q=system_cpu.decode_to_execute_RS2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15588 Q=system_cpu.decode_to_execute_RS2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15586 Q=system_cpu.decode_to_execute_RS2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15584 Q=system_cpu.decode_to_execute_RS2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15582 Q=system_cpu.decode_to_execute_RS2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15580 Q=system_cpu.decode_to_execute_RS2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15578 Q=system_cpu.decode_to_execute_RS2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15576 Q=system_cpu.decode_to_execute_RS2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15574 Q=system_cpu.decode_to_execute_RS2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15572 Q=system_cpu.decode_to_execute_RS2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15570 Q=system_cpu.decode_to_execute_RS2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15568 Q=system_cpu.decode_to_execute_RS2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15566 Q=system_cpu.decode_to_execute_RS2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15564 Q=system_cpu.decode_to_execute_RS2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15562 Q=system_cpu.decode_to_execute_RS2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15560 Q=system_cpu.decode_to_execute_RS2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15558 Q=system_cpu.decode_to_execute_RS2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15556 Q=system_cpu.decode_to_execute_RS2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15554 Q=system_cpu.decode_to_execute_RS2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15552 Q=system_cpu.decode_to_execute_RS2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15550 Q=system_cpu.decode_to_execute_RS2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16650 Q=system_cpu.decode_to_execute_RS2[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15548 Q=system_cpu.decode_to_execute_RS1[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15546 Q=system_cpu.decode_to_execute_RS1[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15544 Q=system_cpu.decode_to_execute_RS1[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15542 Q=system_cpu.decode_to_execute_RS1[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15540 Q=system_cpu.decode_to_execute_RS1[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15538 Q=system_cpu.decode_to_execute_RS1[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15536 Q=system_cpu.decode_to_execute_RS1[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15534 Q=system_cpu.decode_to_execute_RS1[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15532 Q=system_cpu.decode_to_execute_RS1[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15530 Q=system_cpu.decode_to_execute_RS1[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15528 Q=system_cpu.decode_to_execute_RS1[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15526 Q=system_cpu.decode_to_execute_RS1[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15524 Q=system_cpu.decode_to_execute_RS1[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15522 Q=system_cpu.decode_to_execute_RS1[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15520 Q=system_cpu.decode_to_execute_RS1[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15518 Q=system_cpu.decode_to_execute_RS1[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15516 Q=system_cpu.decode_to_execute_RS1[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15514 Q=system_cpu.decode_to_execute_RS1[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15512 Q=system_cpu.decode_to_execute_RS1[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15510 Q=system_cpu.decode_to_execute_RS1[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15508 Q=system_cpu.decode_to_execute_RS1[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15506 Q=system_cpu.decode_to_execute_RS1[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15504 Q=system_cpu.decode_to_execute_RS1[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15502 Q=system_cpu.decode_to_execute_RS1[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15500 Q=system_cpu.decode_to_execute_RS1[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15498 Q=system_cpu.decode_to_execute_RS1[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15496 Q=system_cpu.decode_to_execute_RS1[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15494 Q=system_cpu.decode_to_execute_RS1[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15492 Q=system_cpu.decode_to_execute_RS1[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15490 Q=system_cpu.decode_to_execute_RS1[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15488 Q=system_cpu.decode_to_execute_RS1[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16652 Q=system_cpu.decode_to_execute_RS1[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16664 Q=system_cpu._zz_memory_ENV_CTRL +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16660 Q=system_cpu.decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16648 Q=system_cpu.decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15486 Q=system_cpu.decode_to_execute_SRC2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15484 Q=system_cpu.decode_to_execute_SRC2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15482 Q=system_cpu.decode_to_execute_SRC2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15480 Q=system_cpu.decode_to_execute_SRC2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15478 Q=system_cpu.decode_to_execute_SRC2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15476 Q=system_cpu.decode_to_execute_SRC2[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15474 Q=system_cpu.decode_to_execute_SRC2[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15472 Q=system_cpu.decode_to_execute_SRC2[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15470 Q=system_cpu.decode_to_execute_SRC2[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15468 Q=system_cpu.decode_to_execute_SRC2[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15466 Q=system_cpu.decode_to_execute_SRC2[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15464 Q=system_cpu.decode_to_execute_SRC2[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15462 Q=system_cpu.decode_to_execute_SRC2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15460 Q=system_cpu.decode_to_execute_SRC2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15458 Q=system_cpu.decode_to_execute_SRC2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15456 Q=system_cpu.decode_to_execute_SRC2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15454 Q=system_cpu.decode_to_execute_SRC2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15452 Q=system_cpu.decode_to_execute_SRC2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15450 Q=system_cpu.decode_to_execute_SRC2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15448 Q=system_cpu.decode_to_execute_SRC2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15446 Q=system_cpu.decode_to_execute_SRC2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15444 Q=system_cpu.decode_to_execute_SRC2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15442 Q=system_cpu.decode_to_execute_SRC2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15440 Q=system_cpu.decode_to_execute_SRC2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15438 Q=system_cpu.decode_to_execute_SRC2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15436 Q=system_cpu.decode_to_execute_SRC2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15434 Q=system_cpu.decode_to_execute_SRC2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15432 Q=system_cpu.decode_to_execute_SRC2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15430 Q=system_cpu.decode_to_execute_SRC2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15428 Q=system_cpu.decode_to_execute_SRC2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15426 Q=system_cpu.decode_to_execute_SRC2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16646 Q=system_cpu.decode_to_execute_SRC2[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16644 Q=system_cpu.decode_to_execute_DO_EBREAK +.subckt dffr C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.outputArea_flow_valid Q=jtagBridge_1.flowCCByToggle_1.io_output_valid R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 Q=jtagBridge_1.flowCCByToggle_1.outputArea_hit +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15424 Q=jtagBridge_1.system_rsp_payload_data[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15422 Q=jtagBridge_1.system_rsp_payload_data[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15420 Q=jtagBridge_1.system_rsp_payload_data[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15418 Q=jtagBridge_1.system_rsp_payload_data[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15416 Q=jtagBridge_1.system_rsp_payload_data[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15414 Q=jtagBridge_1.system_rsp_payload_data[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15412 Q=jtagBridge_1.system_rsp_payload_data[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15410 Q=jtagBridge_1.system_rsp_payload_data[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15408 Q=jtagBridge_1.system_rsp_payload_data[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15406 Q=jtagBridge_1.system_rsp_payload_data[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15404 Q=jtagBridge_1.system_rsp_payload_data[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15402 Q=jtagBridge_1.system_rsp_payload_data[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15400 Q=jtagBridge_1.system_rsp_payload_data[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15398 Q=jtagBridge_1.system_rsp_payload_data[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15396 Q=jtagBridge_1.system_rsp_payload_data[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15394 Q=jtagBridge_1.system_rsp_payload_data[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15392 Q=jtagBridge_1.system_rsp_payload_data[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15390 Q=jtagBridge_1.system_rsp_payload_data[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15388 Q=jtagBridge_1.system_rsp_payload_data[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15386 Q=jtagBridge_1.system_rsp_payload_data[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15384 Q=jtagBridge_1.system_rsp_payload_data[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15382 Q=jtagBridge_1.system_rsp_payload_data[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15380 Q=jtagBridge_1.system_rsp_payload_data[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15378 Q=jtagBridge_1.system_rsp_payload_data[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15376 Q=jtagBridge_1.system_rsp_payload_data[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15374 Q=jtagBridge_1.system_rsp_payload_data[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15372 Q=jtagBridge_1.system_rsp_payload_data[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15370 Q=jtagBridge_1.system_rsp_payload_data[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15368 Q=jtagBridge_1.system_rsp_payload_data[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15366 Q=jtagBridge_1.system_rsp_payload_data[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15364 Q=jtagBridge_1.system_rsp_payload_data[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16744 Q=jtagBridge_1.system_rsp_payload_data[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16742 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_last +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16740 Q=jtagBridge_1.flowCCByToggle_1.outputArea_flow_m2sPipe_payload_fragment +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16738 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16736 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_last +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_1 +.subckt dff C=io_jtag_tck D=$abc$18544$flatten\jtagBridge_1.$0\jtag_writeArea_valid[0:0] Q=jtagBridge_1.flowCCByToggle_1.io_input_valid +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15362 Q=jtagBridge_1.jtag_idcodeArea_ctrl_tdo S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15360 Q=jtagBridge_1.jtag_idcodeArea_shifter[1] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15358 Q=jtagBridge_1.jtag_idcodeArea_shifter[2] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15356 Q=jtagBridge_1.jtag_idcodeArea_shifter[3] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15354 Q=jtagBridge_1.jtag_idcodeArea_shifter[4] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15352 Q=jtagBridge_1.jtag_idcodeArea_shifter[5] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15350 Q=jtagBridge_1.jtag_idcodeArea_shifter[6] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15348 Q=jtagBridge_1.jtag_idcodeArea_shifter[7] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15346 Q=jtagBridge_1.jtag_idcodeArea_shifter[8] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15344 Q=jtagBridge_1.jtag_idcodeArea_shifter[9] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15342 Q=jtagBridge_1.jtag_idcodeArea_shifter[10] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15340 Q=jtagBridge_1.jtag_idcodeArea_shifter[11] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15338 Q=jtagBridge_1.jtag_idcodeArea_shifter[12] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15336 Q=jtagBridge_1.jtag_idcodeArea_shifter[13] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15334 Q=jtagBridge_1.jtag_idcodeArea_shifter[14] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15332 Q=jtagBridge_1.jtag_idcodeArea_shifter[15] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15330 Q=jtagBridge_1.jtag_idcodeArea_shifter[16] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15328 Q=jtagBridge_1.jtag_idcodeArea_shifter[17] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15326 Q=jtagBridge_1.jtag_idcodeArea_shifter[18] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15324 Q=jtagBridge_1.jtag_idcodeArea_shifter[19] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15322 Q=jtagBridge_1.jtag_idcodeArea_shifter[20] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15320 Q=jtagBridge_1.jtag_idcodeArea_shifter[21] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15318 Q=jtagBridge_1.jtag_idcodeArea_shifter[22] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15316 Q=jtagBridge_1.jtag_idcodeArea_shifter[23] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15314 Q=jtagBridge_1.jtag_idcodeArea_shifter[24] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15312 Q=jtagBridge_1.jtag_idcodeArea_shifter[25] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15310 Q=jtagBridge_1.jtag_idcodeArea_shifter[26] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15308 Q=jtagBridge_1.jtag_idcodeArea_shifter[27] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15306 Q=jtagBridge_1.jtag_idcodeArea_shifter[28] S=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15304 Q=jtagBridge_1.jtag_idcodeArea_shifter[29] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15302 Q=jtagBridge_1.jtag_idcodeArea_shifter[30] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16748 Q=jtagBridge_1.jtag_idcodeArea_shifter[31] R=jtagBridge_1.jtag_idcodeArea_ctrl_capture +.subckt dff C=io_jtag_tck D=io_jtag_tdi Q=jtagBridge_1.flowCCByToggle_1.io_input_payload_fragment +.subckt sdffs C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15300 Q=jtagBridge_1._zz_jtag_tap_isBypass[0] S=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15298 Q=jtagBridge_1._zz_jtag_tap_isBypass[1] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15296 Q=jtagBridge_1._zz_jtag_tap_isBypass[2] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffr C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16746 Q=jtagBridge_1._zz_jtag_tap_isBypass[3] R=jtagBridge_1.when_JtagTap_l120 +.subckt sdffrn C=io_mainClk D=system_cpu.CsrPlugin_csrMapping_writeDataSignal[3] Q=system_cpu.CsrPlugin_mip_MSIP RN=$abc$18544$auto$opt_dff.cc:253:combine_resets$3598 +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[0] Q=jtagBridge_1.jtag_tap_fsm_state[0] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[1] Q=jtagBridge_1.jtag_tap_fsm_state[1] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[2] Q=jtagBridge_1.jtag_tap_fsm_state[2] +.subckt dff C=io_jtag_tck D=jtagBridge_1._zz_jtag_tap_fsm_stateNext_16[3] Q=jtagBridge_1.jtag_tap_fsm_state[3] +.subckt dffn C=io_jtag_tck D=jtagBridge_1.jtag_tap_tdoUnbufferd Q=io_jtag_tdo +.subckt sdffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16750 Q=jtagBridge_1.system_rsp_valid S=jtagBridge_1.io_remote_rsp_fire +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15294 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15290 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15286 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16792 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15282 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15280 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15278 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15276 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15274 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15272 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15270 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15268 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15266 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15264 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15262 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15260 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15258 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15256 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15254 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15252 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15250 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15248 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15246 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15244 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16794 Q=system_cpu._zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16518 Q=system_mainBusArbiter.rspPending R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=jtagBridge_1.flowCCByToggle_1.inputArea_target Q=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.buffers_0 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15242 Q=systemDebugger_1.dispatcher_header[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15240 Q=systemDebugger_1.dispatcher_header[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15238 Q=systemDebugger_1.dispatcher_header[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15236 Q=systemDebugger_1.dispatcher_header[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15234 Q=systemDebugger_1.dispatcher_header[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15232 Q=systemDebugger_1.dispatcher_header[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15230 Q=systemDebugger_1.dispatcher_header[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16730 Q=systemDebugger_1.dispatcher_header[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15224 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15222 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15220 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15218 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15216 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15214 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15212 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15210 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15208 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15206 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15204 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15202 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15200 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15198 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15196 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15194 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15192 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15190 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15188 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15186 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15184 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15182 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15180 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15178 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15176 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15174 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15172 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15170 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15168 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15166 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15164 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[32] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15162 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[33] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15160 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[34] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15158 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[35] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15156 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[36] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15154 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[37] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15152 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[38] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15150 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[39] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15148 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[40] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15146 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[41] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15144 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[42] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15142 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[43] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15140 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[44] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15138 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[45] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15136 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[46] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15134 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[47] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15132 Q=system_cpu.when_DebugPlugin_l284 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15130 Q=system_cpu.when_DebugPlugin_l285 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15128 Q=system_cpu.when_DebugPlugin_l288 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15126 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[51] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15124 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[52] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15122 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[53] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15120 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[54] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15118 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[55] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15116 Q=system_cpu.when_DebugPlugin_l284_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15114 Q=system_cpu.when_DebugPlugin_l285_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15112 Q=system_cpu.when_DebugPlugin_l288_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15110 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[59] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15108 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[60] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15106 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[61] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15104 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[62] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15102 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[63] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15100 Q=systemDebugger_1.io_mem_cmd_payload_wr +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15098 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[65] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16732 Q=systemDebugger_1._zz_io_mem_cmd_payload_address[66] +.subckt dff C=io_jtag_tck D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16734 Q=jtagBridge_1.flowCCByToggle_1.inputArea_data_fragment +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16728 Q=systemDebugger_1.dispatcher_dataLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16726 Q=systemDebugger_1.dispatcher_headerLoaded R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16588 Q=system_mainBusArbiter.rspTarget R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_ram.$0\_zz_io_bus_rsp_valid[0:0] Q=system_ram._zz_io_bus_rsp_valid R=apb3Router_1.resetCtrl_systemReset +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[10] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[10] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[11] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[11] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[12] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[12] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[13] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[13] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt sdffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3626[14] Q=system_apbBridge.io_pipelinedMemoryBus_rsp_payload_data[14] R=$abc$18544$flatten\apb3Router_1.$procmux$3225_CMP +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15096 Q=system_uartCtrl.when_BusSlaveFactory_l347 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15094 Q=system_uartCtrl.when_BusSlaveFactory_l347_1 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15092 Q=apb3Router_1.io_input_PWDATA[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15090 Q=apb3Router_1.io_input_PWDATA[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15088 Q=apb3Router_1.io_input_PWDATA[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15086 Q=apb3Router_1.io_input_PWDATA[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15084 Q=apb3Router_1.io_input_PWDATA[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15082 Q=apb3Router_1.io_input_PWDATA[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15080 Q=apb3Router_1.io_input_PWDATA[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15078 Q=system_uartCtrl.when_BusSlaveFactory_l347_2 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15076 Q=system_uartCtrl.when_BusSlaveFactory_l379 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15074 Q=system_uartCtrl.when_BusSlaveFactory_l347_3 +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15072 Q=apb3Router_1.io_input_PWDATA[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15070 Q=apb3Router_1.io_input_PWDATA[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15068 Q=apb3Router_1.io_input_PWDATA[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15066 Q=apb3Router_1.io_input_PWDATA[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15064 Q=apb3Router_1.io_input_PWDATA[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15062 Q=apb3Router_1.io_input_PWDATA[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15060 Q=apb3Router_1.io_input_PWDATA[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15058 Q=apb3Router_1.io_input_PWDATA[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15056 Q=apb3Router_1.io_input_PWDATA[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15054 Q=apb3Router_1.io_input_PWDATA[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15052 Q=apb3Router_1.io_input_PWDATA[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15050 Q=apb3Router_1.io_input_PWDATA[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15048 Q=apb3Router_1.io_input_PWDATA[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15046 Q=apb3Router_1.io_input_PWDATA[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15044 Q=apb3Router_1.io_input_PWDATA[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15042 Q=apb3Router_1.io_input_PWDATA[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15040 Q=apb3Router_1.io_input_PWDATA[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15038 Q=apb3Router_1.io_input_PWDATA[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15036 Q=apb3Router_1.io_input_PWDATA[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16714 Q=apb3Router_1.io_input_PWDATA[31] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16722 Q=apb3Router_1.io_input_PWRITE +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15034 Q=apb3Router_1.io_input_PADDR[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16718 Q=apb3Router_1.io_input_PADDR[1] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15030 Q=systemDebugger_1.dispatcher_counter[0] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15028 Q=systemDebugger_1.dispatcher_counter[1] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16724 Q=systemDebugger_1.dispatcher_counter[2] R=jtagBridge_1.flowCCByToggle_1.inputArea_target_buffercc.resetCtrl_mainClkReset +.subckt dffr C=io_mainClk D=system_apbBridge.pipelinedMemoryBusStage_rsp_valid Q=system_apbBridge.io_pipelinedMemoryBus_rsp_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_apbBridge.$0\state[0:0] Q=apb3Router_1.io_input_PENABLE R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[0] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[1] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[2] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[3] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[4] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[5] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[6] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[7] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[8] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[9] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[10] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[11] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[12] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[13] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[14] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[15] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[16] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[17] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[18] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[19] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[20] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[21] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[22] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[23] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[24] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[25] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[26] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[27] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[28] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[29] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[30] +.subckt dff C=io_mainClk D=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_1[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16594 Q=system_cpu.IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15026 Q=io_gpioA_write[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15024 Q=io_gpioA_write[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15022 Q=io_gpioA_write[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15020 Q=io_gpioA_write[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15018 Q=io_gpioA_write[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15016 Q=io_gpioA_write[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15014 Q=io_gpioA_write[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15012 Q=io_gpioA_write[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15010 Q=io_gpioA_write[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15008 Q=io_gpioA_write[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15006 Q=io_gpioA_write[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15004 Q=io_gpioA_write[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15002 Q=io_gpioA_write[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$15000 Q=io_gpioA_write[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14998 Q=io_gpioA_write[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14996 Q=io_gpioA_write[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14994 Q=io_gpioA_write[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14992 Q=io_gpioA_write[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14990 Q=io_gpioA_write[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14988 Q=io_gpioA_write[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14986 Q=io_gpioA_write[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14984 Q=io_gpioA_write[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14982 Q=io_gpioA_write[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14980 Q=io_gpioA_write[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14978 Q=io_gpioA_write[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14976 Q=io_gpioA_write[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14974 Q=io_gpioA_write[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14972 Q=io_gpioA_write[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14970 Q=io_gpioA_write[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14968 Q=io_gpioA_write[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14966 Q=io_gpioA_write[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16592 Q=io_gpioA_write[31] +.subckt dff C=io_mainClk D=io_gpioA_read[0] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[0] +.subckt dff C=io_mainClk D=io_gpioA_read[1] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[1] +.subckt dff C=io_mainClk D=io_gpioA_read[2] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[2] +.subckt dff C=io_mainClk D=io_gpioA_read[3] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[3] +.subckt dff C=io_mainClk D=io_gpioA_read[4] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[4] +.subckt dff C=io_mainClk D=io_gpioA_read[5] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[5] +.subckt dff C=io_mainClk D=io_gpioA_read[6] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[6] +.subckt dff C=io_mainClk D=io_gpioA_read[7] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[7] +.subckt dff C=io_mainClk D=io_gpioA_read[8] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[8] +.subckt dff C=io_mainClk D=io_gpioA_read[9] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[9] +.subckt dff C=io_mainClk D=io_gpioA_read[10] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[10] +.subckt dff C=io_mainClk D=io_gpioA_read[11] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[11] +.subckt dff C=io_mainClk D=io_gpioA_read[12] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[12] +.subckt dff C=io_mainClk D=io_gpioA_read[13] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[13] +.subckt dff C=io_mainClk D=io_gpioA_read[14] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[14] +.subckt dff C=io_mainClk D=io_gpioA_read[15] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[15] +.subckt dff C=io_mainClk D=io_gpioA_read[16] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[16] +.subckt dff C=io_mainClk D=io_gpioA_read[17] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[17] +.subckt dff C=io_mainClk D=io_gpioA_read[18] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[18] +.subckt dff C=io_mainClk D=io_gpioA_read[19] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[19] +.subckt dff C=io_mainClk D=io_gpioA_read[20] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[20] +.subckt dff C=io_mainClk D=io_gpioA_read[21] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[21] +.subckt dff C=io_mainClk D=io_gpioA_read[22] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[22] +.subckt dff C=io_mainClk D=io_gpioA_read[23] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[23] +.subckt dff C=io_mainClk D=io_gpioA_read[24] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[24] +.subckt dff C=io_mainClk D=io_gpioA_read[25] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[25] +.subckt dff C=io_mainClk D=io_gpioA_read[26] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[26] +.subckt dff C=io_mainClk D=io_gpioA_read[27] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[27] +.subckt dff C=io_mainClk D=io_gpioA_read[28] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[28] +.subckt dff C=io_mainClk D=io_gpioA_read[29] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[29] +.subckt dff C=io_mainClk D=io_gpioA_read[30] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[30] +.subckt dff C=io_mainClk D=io_gpioA_read[31] Q=system_gpioACtrl.io_gpio_read_buffercc.buffers_0[31] +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14964 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14962 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14960 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14958 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16550 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14956 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14954 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14952 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14950 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16548 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16546 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14948 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14946 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14944 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14942 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16544 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16560 Q=system_uartCtrl.bridge_misc_readOverflowError R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14940 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14938 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14936 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14934 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16558 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14932 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14930 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14928 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14926 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16556 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16554 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.io_pop_valid R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14924 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14922 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14920 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14918 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16552 Q=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_sync_popReg[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][0] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][1] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][2] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][3] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[3] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][4] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[4] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][5] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[5] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][6] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[6] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][7] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[7] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][8] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[8] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][9] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[9] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][10] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[10] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][11] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[11] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][12] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[12] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][13] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[13] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][14] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[14] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][15] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[15] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][16] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[16] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][17] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[17] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][18] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[18] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.$0\clockDivider_counter[19:0][19] Q=system_uartCtrl.uartCtrl_1.clockDivider_counter[19] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.clockDivider_tick Q=system_uartCtrl.uartCtrl_1.clockDivider_tickReg R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[0] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[1] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_valueNext[2] Q=system_uartCtrl.uartCtrl_1.tx.clockDivider_counter_value[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14916 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[0] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14914 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[1] R=apb3Router_1.resetCtrl_systemReset +.subckt dffr C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16534 Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2] R=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[0] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[1] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3954[2] Q=system_uartCtrl.uartCtrl_1.tx.tickCounter_value[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.tx.stateMachine_parity +.subckt dffs C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\tx.$0\_zz_io_txd[0:0] Q=io_uart_txd S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14912 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14910 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14908 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14906 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14904 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14902 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14900 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14898 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14896 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14894 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14892 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14890 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14888 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14886 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14884 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14882 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14880 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14878 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14876 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14874 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14872 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14870 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14868 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14866 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14864 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14862 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14860 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14858 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14856 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16764 Q=system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dffr C=io_mainClk D=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_0 Q=system_uartCtrl.uartCtrl_1.rx.io_rxd_buffercc.buffers_1 R=apb3Router_1.resetCtrl_systemReset +.subckt dffs C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16540 Q=system_uartCtrl.uartCtrl_1.rx.sampler_samples_1 S=apb3Router_1.resetCtrl_systemReset +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14854 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14852 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14850 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14848 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14846 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14844 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$14842 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2693:MuxGate$16542 Q=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\stateMachine_parity[0:0] Q=system_uartCtrl.uartCtrl_1.rx.stateMachine_parity +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[0] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[0] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[1] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[1] +.subckt dff C=io_mainClk D=$abc$18544$auto$rtlil.cc:2582:Mux$3916[2] Q=system_uartCtrl.uartCtrl_1.rx.bitCounter_value[2] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][0] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[0] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][1] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[1] +.subckt dff C=io_mainClk D=$abc$18544$flatten\system_uartCtrl.\uartCtrl_1.\rx.$0\bitTimer_counter[2:0][2] Q=system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port1[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port1[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port1[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port1[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port1[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port1[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port1[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port1[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port1[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port1[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port1[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port1[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port1[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port1[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port1[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port1[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port1[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port1[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port1[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port1[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port1[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port1[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port1[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port1[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port1[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port1[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port1[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port1[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port1[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port1[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port1[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4542[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4542[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4542[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4542[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=system_cpu.lastStageRegFileWrite_payload_data[0] data_i[34]=system_cpu.lastStageRegFileWrite_payload_data[1] data_i[33]=system_cpu.lastStageRegFileWrite_payload_data[2] data_i[32]=system_cpu.lastStageRegFileWrite_payload_data[3] data_i[31]=system_cpu.lastStageRegFileWrite_payload_data[4] data_i[30]=system_cpu.lastStageRegFileWrite_payload_data[5] data_i[29]=system_cpu.lastStageRegFileWrite_payload_data[6] data_i[28]=system_cpu.lastStageRegFileWrite_payload_data[7] data_i[27]=system_cpu.lastStageRegFileWrite_payload_data[8] data_i[26]=system_cpu.lastStageRegFileWrite_payload_data[9] data_i[25]=system_cpu.lastStageRegFileWrite_payload_data[10] data_i[24]=system_cpu.lastStageRegFileWrite_payload_data[11] data_i[23]=system_cpu.lastStageRegFileWrite_payload_data[12] data_i[22]=system_cpu.lastStageRegFileWrite_payload_data[13] data_i[21]=system_cpu.lastStageRegFileWrite_payload_data[14] data_i[20]=system_cpu.lastStageRegFileWrite_payload_data[15] data_i[19]=system_cpu.lastStageRegFileWrite_payload_data[16] data_i[18]=system_cpu.lastStageRegFileWrite_payload_data[17] data_i[17]=system_cpu.lastStageRegFileWrite_payload_data[18] data_i[16]=system_cpu.lastStageRegFileWrite_payload_data[19] data_i[15]=system_cpu.lastStageRegFileWrite_payload_data[20] data_i[14]=system_cpu.lastStageRegFileWrite_payload_data[21] data_i[13]=system_cpu.lastStageRegFileWrite_payload_data[22] data_i[12]=system_cpu.lastStageRegFileWrite_payload_data[23] data_i[11]=system_cpu.lastStageRegFileWrite_payload_data[24] data_i[10]=system_cpu.lastStageRegFileWrite_payload_data[25] data_i[9]=system_cpu.lastStageRegFileWrite_payload_data[26] data_i[8]=system_cpu.lastStageRegFileWrite_payload_data[27] data_i[7]=system_cpu.lastStageRegFileWrite_payload_data[28] data_i[6]=system_cpu.lastStageRegFileWrite_payload_data[29] data_i[5]=system_cpu.lastStageRegFileWrite_payload_data[30] data_i[4]=system_cpu.lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=system_cpu._zz_RegFilePlugin_regFile_port0[0] q_o[34]=system_cpu._zz_RegFilePlugin_regFile_port0[1] q_o[33]=system_cpu._zz_RegFilePlugin_regFile_port0[2] q_o[32]=system_cpu._zz_RegFilePlugin_regFile_port0[3] q_o[31]=system_cpu._zz_RegFilePlugin_regFile_port0[4] q_o[30]=system_cpu._zz_RegFilePlugin_regFile_port0[5] q_o[29]=system_cpu._zz_RegFilePlugin_regFile_port0[6] q_o[28]=system_cpu._zz_RegFilePlugin_regFile_port0[7] q_o[27]=system_cpu._zz_RegFilePlugin_regFile_port0[8] q_o[26]=system_cpu._zz_RegFilePlugin_regFile_port0[9] q_o[25]=system_cpu._zz_RegFilePlugin_regFile_port0[10] q_o[24]=system_cpu._zz_RegFilePlugin_regFile_port0[11] q_o[23]=system_cpu._zz_RegFilePlugin_regFile_port0[12] q_o[22]=system_cpu._zz_RegFilePlugin_regFile_port0[13] q_o[21]=system_cpu._zz_RegFilePlugin_regFile_port0[14] q_o[20]=system_cpu._zz_RegFilePlugin_regFile_port0[15] q_o[19]=system_cpu._zz_RegFilePlugin_regFile_port0[16] q_o[18]=system_cpu._zz_RegFilePlugin_regFile_port0[17] q_o[17]=system_cpu._zz_RegFilePlugin_regFile_port0[18] q_o[16]=system_cpu._zz_RegFilePlugin_regFile_port0[19] q_o[15]=system_cpu._zz_RegFilePlugin_regFile_port0[20] q_o[14]=system_cpu._zz_RegFilePlugin_regFile_port0[21] q_o[13]=system_cpu._zz_RegFilePlugin_regFile_port0[22] q_o[12]=system_cpu._zz_RegFilePlugin_regFile_port0[23] q_o[11]=system_cpu._zz_RegFilePlugin_regFile_port0[24] q_o[10]=system_cpu._zz_RegFilePlugin_regFile_port0[25] q_o[9]=system_cpu._zz_RegFilePlugin_regFile_port0[26] q_o[8]=system_cpu._zz_RegFilePlugin_regFile_port0[27] q_o[7]=system_cpu._zz_RegFilePlugin_regFile_port0[28] q_o[6]=system_cpu._zz_RegFilePlugin_regFile_port0[29] q_o[5]=system_cpu._zz_RegFilePlugin_regFile_port0[30] q_o[4]=system_cpu._zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4543[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4543[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4543[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4543[35] raddr_i[7]=system_cpu.decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=system_cpu.decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=system_cpu.decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=system_cpu.decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=system_cpu.decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=$true waddr_i[7]=system_cpu.lastStageRegFileWrite_payload_address[0] waddr_i[6]=system_cpu.lastStageRegFileWrite_payload_address[1] waddr_i[5]=system_cpu.lastStageRegFileWrite_payload_address[2] waddr_i[4]=system_cpu.lastStageRegFileWrite_payload_address[3] waddr_i[3]=system_cpu.lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_cpu._zz_1 +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[0] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[1] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[2] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[3] q_o[3]=system_ram._zz_ram_port0[0] q_o[2]=system_ram._zz_ram_port0[1] q_o[1]=system_ram._zz_ram_port0[2] q_o[0]=system_ram._zz_ram_port0[3] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[4] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[5] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[6] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[7] q_o[3]=system_ram._zz_ram_port0[4] q_o[2]=system_ram._zz_ram_port0[5] q_o[1]=system_ram._zz_ram_port0[6] q_o[0]=system_ram._zz_ram_port0[7] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol0$./benchmark/Murax.v:1635$158_EN[7:0]$171[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[8] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[9] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[10] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[11] q_o[3]=system_ram._zz_ram_port0[8] q_o[2]=system_ram._zz_ram_port0[9] q_o[1]=system_ram._zz_ram_port0[10] q_o[0]=system_ram._zz_ram_port0[11] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[12] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[13] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[14] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[15] q_o[3]=system_ram._zz_ram_port0[12] q_o[2]=system_ram._zz_ram_port0[13] q_o[1]=system_ram._zz_ram_port0[14] q_o[0]=system_ram._zz_ram_port0[15] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol1$./benchmark/Murax.v:1638$159_EN[7:0]$174[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[16] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[17] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[18] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[19] q_o[3]=system_ram._zz_ram_port0[16] q_o[2]=system_ram._zz_ram_port0[17] q_o[1]=system_ram._zz_ram_port0[18] q_o[0]=system_ram._zz_ram_port0[19] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[20] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[21] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[22] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[23] q_o[3]=system_ram._zz_ram_port0[20] q_o[2]=system_ram._zz_ram_port0[21] q_o[1]=system_ram._zz_ram_port0[22] q_o[0]=system_ram._zz_ram_port0[23] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol2$./benchmark/Murax.v:1641$160_EN[7:0]$177[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[24] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[25] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[26] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[27] q_o[3]=system_ram._zz_ram_port0[24] q_o[2]=system_ram._zz_ram_port0[25] q_o[1]=system_ram._zz_ram_port0[26] q_o[0]=system_ram._zz_ram_port0[27] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[28] data_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[29] data_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[30] data_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_data[31] q_o[3]=system_ram._zz_ram_port0[28] q_o[2]=system_ram._zz_ram_port0[29] q_o[1]=system_ram._zz_ram_port0[30] q_o[0]=system_ram._zz_ram_port0[31] raddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] raddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] raddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] raddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] raddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] raddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] raddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] raddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] raddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] raddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] raddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] rclk_i=io_mainClk ren_ni=system_ram.io_bus_cmd_fire waddr_i[10]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[2] waddr_i[9]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[3] waddr_i[8]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[4] waddr_i[7]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[5] waddr_i[6]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[6] waddr_i[5]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[7] waddr_i[4]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[8] waddr_i[3]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[9] waddr_i[2]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[10] waddr_i[1]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[11] waddr_i[0]=system_apbBridge.io_pipelinedMemoryBus_cmd_payload_address[12] wclk_i=io_mainClk wen_ni=$abc$18544$flatten\system_ram.$0$memwr$\ram_symbol3$./benchmark/Murax.v:1644$161_EN[7:0]$180[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.when_BusSlaveFactory_l347 data_i[7]=system_uartCtrl.when_BusSlaveFactory_l347_1 data_i[6]=apb3Router_1.io_input_PWDATA[2] data_i[5]=apb3Router_1.io_input_PWDATA[3] data_i[4]=apb3Router_1.io_input_PWDATA[4] data_i[3]=apb3Router_1.io_input_PWDATA[5] data_i[2]=apb3Router_1.io_input_PWDATA[6] data_i[1]=apb3Router_1.io_input_PWDATA[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] q_o[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] q_o[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] q_o[5]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] q_o[4]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] q_o[3]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] q_o[2]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] q_o[1]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4558[8] raddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_1 +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[0] data_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[1] data_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[2] data_i[5]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[3] data_i[4]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[4] data_i[3]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[5] data_i[2]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[6] data_i[1]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.io_push_payload[7] data_i[0]=$undef q_o[8]=system_uartCtrl.bridge_read_streamBreaked_payload[0] q_o[7]=system_uartCtrl.bridge_read_streamBreaked_payload[1] q_o[6]=system_uartCtrl.bridge_read_streamBreaked_payload[2] q_o[5]=system_uartCtrl.bridge_read_streamBreaked_payload[3] q_o[4]=system_uartCtrl.bridge_read_streamBreaked_payload[4] q_o[3]=system_uartCtrl.bridge_read_streamBreaked_payload[5] q_o[2]=system_uartCtrl.bridge_read_streamBreaked_payload[6] q_o[1]=system_uartCtrl.bridge_read_streamBreaked_payload[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4560[8] raddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] raddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] raddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] raddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] raddr_i[5]=$false raddr_i[4]=$false raddr_i[3]=$false raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=io_mainClk ren_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_fire waddr_i[9]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[0] waddr_i[8]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[1] waddr_i[7]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[2] waddr_i[6]=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_push[3] waddr_i[5]=$false waddr_i[4]=$false waddr_i[3]=$false waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=io_mainClk wen_ni=system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy._zz_1 +.names system_timer.prescaler_1.counter[1] $auto$alumacc.cc:485:replace_alu$4095.X[1] +1 1 +.names system_timer.prescaler_1.counter[2] $auto$alumacc.cc:485:replace_alu$4095.X[2] +1 1 +.names system_timer.prescaler_1.counter[3] $auto$alumacc.cc:485:replace_alu$4095.X[3] +1 1 +.names system_timer.prescaler_1.counter[4] $auto$alumacc.cc:485:replace_alu$4095.X[4] +1 1 +.names system_timer.prescaler_1.counter[5] $auto$alumacc.cc:485:replace_alu$4095.X[5] +1 1 +.names system_timer.prescaler_1.counter[6] $auto$alumacc.cc:485:replace_alu$4095.X[6] +1 1 +.names system_timer.prescaler_1.counter[7] $auto$alumacc.cc:485:replace_alu$4095.X[7] +1 1 +.names system_timer.prescaler_1.counter[8] $auto$alumacc.cc:485:replace_alu$4095.X[8] +1 1 +.names system_timer.prescaler_1.counter[9] $auto$alumacc.cc:485:replace_alu$4095.X[9] +1 1 +.names system_timer.prescaler_1.counter[10] $auto$alumacc.cc:485:replace_alu$4095.X[10] +1 1 +.names system_timer.prescaler_1.counter[11] $auto$alumacc.cc:485:replace_alu$4095.X[11] +1 1 +.names system_timer.prescaler_1.counter[12] $auto$alumacc.cc:485:replace_alu$4095.X[12] +1 1 +.names system_timer.prescaler_1.counter[13] $auto$alumacc.cc:485:replace_alu$4095.X[13] +1 1 +.names system_timer.prescaler_1.counter[14] $auto$alumacc.cc:485:replace_alu$4095.X[14] +1 1 +.names system_timer.prescaler_1.counter[15] $auto$alumacc.cc:485:replace_alu$4095.X[15] +1 1 +.names $auto$alumacc.cc:485:replace_alu$4095.X[0] $auto$alumacc.cc:485:replace_alu$4095.Y[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$4542[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$4542[1] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$4542[2] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$4542[3] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$4542[4] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$4542[5] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$4542[6] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$4542[7] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$4542[8] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$4542[9] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$4542[10] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$4542[11] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$4542[12] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$4542[13] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$4542[14] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$4542[15] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$4542[16] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$4542[17] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$4542[18] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$4542[19] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$4542[20] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$4542[21] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$4542[22] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$4542[23] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$4542[24] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$4542[25] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$4542[26] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$4542[27] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$4542[28] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$4542[29] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$4542[30] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$4542[31] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$4543[0] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$4543[1] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$4543[2] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$4543[3] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$4543[4] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$4543[5] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$4543[6] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$4543[7] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$4543[8] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$4543[9] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$4543[10] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$4543[11] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$4543[12] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$4543[13] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$4543[14] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$4543[15] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$4543[16] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$4543[17] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$4543[18] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$4543[19] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$4543[20] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$4543[21] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$4543[22] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$4543[23] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$4543[24] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$4543[25] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$4543[26] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$4543[27] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$4543[28] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$4543[29] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$4543[30] +1 1 +.names system_cpu._zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$4543[31] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[0] $auto$memory_bram.cc:844:replace_memory$4558[0] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[1] $auto$memory_bram.cc:844:replace_memory$4558[1] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[2] $auto$memory_bram.cc:844:replace_memory$4558[2] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[3] $auto$memory_bram.cc:844:replace_memory$4558[3] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[4] $auto$memory_bram.cc:844:replace_memory$4558[4] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[5] $auto$memory_bram.cc:844:replace_memory$4558[5] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[6] $auto$memory_bram.cc:844:replace_memory$4558[6] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy._zz_logic_ram_port1[7] $auto$memory_bram.cc:844:replace_memory$4558[7] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[0] $auto$memory_bram.cc:844:replace_memory$4560[0] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[1] $auto$memory_bram.cc:844:replace_memory$4560[1] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[2] $auto$memory_bram.cc:844:replace_memory$4560[2] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[3] $auto$memory_bram.cc:844:replace_memory$4560[3] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[4] $auto$memory_bram.cc:844:replace_memory$4560[4] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[5] $auto$memory_bram.cc:844:replace_memory$4560[5] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[6] $auto$memory_bram.cc:844:replace_memory$4560[6] +1 1 +.names system_uartCtrl.bridge_read_streamBreaked_payload[7] $auto$memory_bram.cc:844:replace_memory$4560[7] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347 apb3Router_1.io_input_PWDATA[0] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_1 apb3Router_1.io_input_PWDATA[1] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_2 apb3Router_1.io_input_PWDATA[9] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l379 apb3Router_1.io_input_PWDATA[10] +1 1 +.names system_uartCtrl.when_BusSlaveFactory_l347_3 apb3Router_1.io_input_PWDATA[11] +1 1 +.names jtagBridge_1.jtag_idcodeArea_ctrl_tdo jtagBridge_1.jtag_idcodeArea_shifter[0] +1 1 +.names jtagBridge_1.jtag_readArea_ctrl_tdo jtagBridge_1.jtag_readArea_full_shifter[0] +1 1 +.names jtagBridge_1.jtag_tap_tdoIr jtagBridge_1.jtag_tap_instructionShift[0] +1 1 +.names system_cpu.when_DebugPlugin_l284 systemDebugger_1._zz_io_mem_cmd_payload_address[48] +1 1 +.names system_cpu.when_DebugPlugin_l285 systemDebugger_1._zz_io_mem_cmd_payload_address[49] +1 1 +.names system_cpu.when_DebugPlugin_l288 systemDebugger_1._zz_io_mem_cmd_payload_address[50] +1 1 +.names system_cpu.when_DebugPlugin_l284_1 systemDebugger_1._zz_io_mem_cmd_payload_address[56] +1 1 +.names system_cpu.when_DebugPlugin_l285_1 systemDebugger_1._zz_io_mem_cmd_payload_address[57] +1 1 +.names system_cpu.when_DebugPlugin_l288_1 systemDebugger_1._zz_io_mem_cmd_payload_address[58] +1 1 +.names systemDebugger_1.io_mem_cmd_payload_wr systemDebugger_1._zz_io_mem_cmd_payload_address[64] +1 1 +.names $false system_cpu.BranchPlugin_jumpInterface_payload[0] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[13] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[14] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[15] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[16] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[17] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[18] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[19] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[20] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[21] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[22] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[23] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[24] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[25] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[26] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[27] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[28] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[29] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[30] +1 1 +.names $undef system_cpu.CsrPlugin_csrMapping_writeDataSignal[31] +1 1 +.names $true system_cpu.CsrPlugin_interrupt_code[0] +1 1 +.names $true system_cpu.CsrPlugin_interrupt_code[1] +1 1 +.names $true system_cpu.CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true system_cpu.CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false system_cpu.CsrPlugin_mepc[0] +1 1 +.names $false system_cpu.CsrPlugin_mepc[1] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[5] system_cpu.DebugPlugin_busReadDataReg[5] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[6] system_cpu.DebugPlugin_busReadDataReg[6] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[7] system_cpu.DebugPlugin_busReadDataReg[7] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[8] system_cpu.DebugPlugin_busReadDataReg[8] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[9] system_cpu.DebugPlugin_busReadDataReg[9] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[10] system_cpu.DebugPlugin_busReadDataReg[10] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[11] system_cpu.DebugPlugin_busReadDataReg[11] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[12] system_cpu.DebugPlugin_busReadDataReg[12] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[13] system_cpu.DebugPlugin_busReadDataReg[13] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[14] system_cpu.DebugPlugin_busReadDataReg[14] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[15] system_cpu.DebugPlugin_busReadDataReg[15] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[16] system_cpu.DebugPlugin_busReadDataReg[16] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[17] system_cpu.DebugPlugin_busReadDataReg[17] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[18] system_cpu.DebugPlugin_busReadDataReg[18] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[19] system_cpu.DebugPlugin_busReadDataReg[19] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[20] system_cpu.DebugPlugin_busReadDataReg[20] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[21] system_cpu.DebugPlugin_busReadDataReg[21] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[22] system_cpu.DebugPlugin_busReadDataReg[22] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[23] system_cpu.DebugPlugin_busReadDataReg[23] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[24] system_cpu.DebugPlugin_busReadDataReg[24] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[25] system_cpu.DebugPlugin_busReadDataReg[25] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[26] system_cpu.DebugPlugin_busReadDataReg[26] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[27] system_cpu.DebugPlugin_busReadDataReg[27] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[28] system_cpu.DebugPlugin_busReadDataReg[28] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[29] system_cpu.DebugPlugin_busReadDataReg[29] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[30] system_cpu.DebugPlugin_busReadDataReg[30] +1 1 +.names jtagBridge_1.io_remote_rsp_payload_data[31] system_cpu.DebugPlugin_busReadDataReg[31] +1 1 +.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_cmd_payload_pc[1] +1 1 +.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_iBusRsp_output_payload_pc[1] +1 1 +.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false system_cpu.IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names system_cpu._zz_decode_SRC_LESS_UNSIGNED_4 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_45 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names system_cpu._zz__zz_decode_SRC_LESS_UNSIGNED_13 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names system_cpu._zz_decode_SRC2 system_cpu.IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names system_cpu.switch_Misc_l241_1 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[4] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[5] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[6] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[7] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[8] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names system_cpu._zz__zz_execute_BranchPlugin_branch_src2[9] system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names system_cpu._zz_execute_BranchPlugin_branch_src2 system_cpu._zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[0] system_cpu._zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[1] system_cpu._zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[2] system_cpu._zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[3] system_cpu._zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names system_cpu.HazardSimplePlugin_writeBackWrites_payload_address[4] system_cpu._zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[30] +1 1 +.names $undef system_cpu._zz_lastStageRegFileWrite_payload_address[31] +1 1 +.names $false system_cpu.decode_to_execute_PC[0] +1 1 +.names $false system_cpu.decode_to_execute_PC[1] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[0] system_cpu.decode_to_execute_RS2[0] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[1] system_cpu.decode_to_execute_RS2[1] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[2] system_cpu.decode_to_execute_RS2[2] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[3] system_cpu.decode_to_execute_RS2[3] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[4] system_cpu.decode_to_execute_RS2[4] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[5] system_cpu.decode_to_execute_RS2[5] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[6] system_cpu.decode_to_execute_RS2[6] +1 1 +.names system_cpu._zz_dBus_cmd_payload_data[7] system_cpu.decode_to_execute_RS2[7] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[0] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[1] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[2] +1 1 +.names system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.bridge_write_streamUnbuffered_queueWithOccupancy.logic_ptr_pop[3] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[0] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[0] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[1] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[1] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[2] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[2] +1 1 +.names system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_pop_addressGen_payload[3] system_uartCtrl.system_uartCtrl_uartCtrl_1_io_read_queueWithOccupancy.logic_ptr_pop[3] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif new file mode 100644 index 00000000000..07d5fccecba --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PWM.blif @@ -0,0 +1,574 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model PWM +.inputs clk RxD +.outputs PWM_out +.names $false +.names $true +1 +.names $undef +.names deserializer.RxD_data_ready RxD_data_reg[6] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1591 +010 1 +011 1 +101 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[5] RxD_data_reg[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1593 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[4] RxD_data_reg[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1595 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[3] RxD_data_reg[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1597 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[2] RxD_data_reg[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1599 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[1] RxD_data_reg[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1601 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[0] RxD_data_reg[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1603 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingTick deserializer.Filter_cnt[0] deserializer.Filter_cnt[1] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1605 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[7] deserializer.RxD_data[6] $abc$1877$auto$rtlil.cc:2693:MuxGate$1607 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$new_n113 +11 1 +.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick deserializer.OversamplingCnt[2] $abc$1877$new_n114 +1110 1 +.names $abc$1877$new_n113 deserializer.RxD_data[6] deserializer.RxD_data[5] $abc$1877$auto$rtlil.cc:2693:MuxGate$1609 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[5] deserializer.RxD_data[4] $abc$1877$auto$rtlil.cc:2693:MuxGate$1611 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[4] deserializer.RxD_data[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1613 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[3] deserializer.RxD_data[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1615 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[2] deserializer.RxD_data[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1617 +001 1 +011 1 +110 1 +111 1 +.names $abc$1877$new_n113 deserializer.RxD_data[1] deserializer.RxD_data[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1619 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingCnt[1] deserializer.OversamplingCnt[0] deserializer.OversamplingTick $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1623 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n122 +100 1 +.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n123 +00 1 +.names deserializer.OversamplingTick deserializer.OversamplingCnt[0] $abc$1877$new_n122 $abc$1877$auto$rtlil.cc:2693:MuxGate$1627 +010 1 +011 1 +100 1 +.names deserializer.RxD_state[1] deserializer.RxD_state[3] deserializer.RxD_state[0] $abc$1877$new_n126 deserializer.RxD_state[2] $abc$1877$auto$rtlil.cc:2693:MuxGate$1629 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$1877$new_n127 $abc$1877$new_n114 deserializer.RxD_state[3] $abc$1877$new_n126 +100 1 +110 1 +111 1 +.names $abc$1877$new_n123 deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n114 deserializer.RxD_bit $abc$1877$new_n127 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$1877$new_n126 deserializer.RxD_state[0] $abc$1877$new_n122 deserializer.RxD_state[3] $abc$1877$auto$rtlil.cc:2693:MuxGate$1631 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names deserializer.OversamplingTick RxD deserializer.RxD_sync[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1633 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_data_ready deserializer.RxD_data[7] RxD_data_reg[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1635 +001 1 +011 1 +110 1 +111 1 +.names deserializer.OversamplingTick deserializer.RxD_sync[0] deserializer.RxD_sync[1] $abc$1877$auto$rtlil.cc:2693:MuxGate$1637 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_bit deserializer.Filter_cnt[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1641 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserializer.Filter_cnt[1] deserializer.RxD_sync[1] deserializer.OversamplingTick deserializer.Filter_cnt[0] $abc$1877$auto$rtlil.cc:2693:MuxGate$1643 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserializer.OversamplingCnt[2] $abc$1877$new_n122 deserializer.OversamplingCnt[0] deserializer.OversamplingCnt[1] deserializer.OversamplingTick $abc$1877$auto$rtlil.cc:2693:MuxGate$1647 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$1877$new_n113 deserializer.RxD_bit deserializer.RxD_data[7] $abc$1877$auto$rtlil.cc:2693:MuxGate$1649 +001 1 +011 1 +110 1 +111 1 +.names deserializer.RxD_state[3] deserializer.RxD_state[2] $abc$1877$new_n137 $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1653 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserializer.RxD_state[0] deserializer.RxD_state[1] $abc$1877$new_n137 +11 1 +.names $abc$1877$new_n139 deserializer.RxD_state[3] $abc$1877$new_n114 $abc$1877$auto$rtlil.cc:2693:MuxGate$1655 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$1877$new_n127 deserializer.RxD_state[3] deserializer.RxD_state[0] deserializer.RxD_state[2] deserializer.RxD_state[1] $abc$1877$new_n139 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserializer.RxD_bit $abc$1877$new_n114 deserializer.RxD_state[1] $abc$1877$new_n123 deserializer.RxD_state[0] $abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] +11110 1 +.names PWM_accumulator[1] RxD_data_reg[1] PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.Y[1] +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[2] +000 1 +011 1 +101 1 +110 1 +.names RxD_data_reg[0] PWM_accumulator[0] PWM_accumulator[1] RxD_data_reg[1] $abc$1877$new_n143 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names PWM_accumulator[3] RxD_data_reg[3] PWM_accumulator[2] RxD_data_reg[2] $abc$1877$new_n143 $auto$alumacc.cc:485:replace_alu$579.Y[3] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[4] +000 1 +011 1 +101 1 +110 1 +.names PWM_accumulator[2] RxD_data_reg[2] PWM_accumulator[3] RxD_data_reg[3] $abc$1877$new_n143 $abc$1877$new_n146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names PWM_accumulator[5] RxD_data_reg[5] PWM_accumulator[4] RxD_data_reg[4] $abc$1877$new_n146 $auto$alumacc.cc:485:replace_alu$579.Y[5] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[6] +000 1 +011 1 +101 1 +110 1 +.names PWM_accumulator[4] RxD_data_reg[4] PWM_accumulator[5] RxD_data_reg[5] $abc$1877$new_n146 $abc$1877$new_n149 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names PWM_accumulator[7] RxD_data_reg[7] PWM_accumulator[6] RxD_data_reg[6] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.Y[7] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PWM_accumulator[0] RxD_data_reg[0] $auto$alumacc.cc:485:replace_alu$579.X[0] +01 1 +10 1 +.names deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[1] +00 1 +11 1 +.names deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $auto$alumacc.cc:485:replace_alu$591.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[5] +00 1 +11 1 +.names deserializer.tickgen.Acc[8] deserializer.tickgen.Acc[7] deserializer.tickgen.Acc[6] deserializer.tickgen.Acc[4] deserializer.tickgen.Acc[5] $abc$1877$new_n157 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $auto$alumacc.cc:485:replace_alu$591.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[9] +01 1 +10 1 +.names deserializer.tickgen.Acc[12] deserializer.tickgen.Acc[11] deserializer.tickgen.Acc[10] deserializer.tickgen.Acc[9] $abc$1877$new_n157 $abc$1877$new_n162 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PWM_accumulator[6] RxD_data_reg[6] PWM_accumulator[7] RxD_data_reg[7] $abc$1877$new_n149 $auto$alumacc.cc:485:replace_alu$579.CO[7] +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserializer.tickgen.Acc[15] deserializer.tickgen.Acc[14] deserializer.tickgen.Acc[13] $abc$1877$new_n162 $auto$alumacc.cc:485:replace_alu$591.CO[11] +1111 1 +.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.X[0] +0 1 +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1641 Q=deserializer.RxD_bit +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1605 Q=deserializer.Filter_cnt[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1643 Q=deserializer.Filter_cnt[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1603 Q=RxD_data_reg[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1601 Q=RxD_data_reg[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1599 Q=RxD_data_reg[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1597 Q=RxD_data_reg[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1595 Q=RxD_data_reg[4] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1593 Q=RxD_data_reg[5] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1591 Q=RxD_data_reg[6] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1635 Q=RxD_data_reg[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.X[0] Q=PWM_accumulator[0] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[1] Q=PWM_accumulator[1] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[2] Q=PWM_accumulator[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[3] Q=PWM_accumulator[3] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[4] Q=PWM_accumulator[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[5] Q=PWM_accumulator[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[6] Q=PWM_accumulator[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.Y[7] Q=PWM_accumulator[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$579.CO[7] Q=PWM_out +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1633 Q=deserializer.RxD_sync[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1637 Q=deserializer.RxD_sync[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1631 Q=deserializer.RxD_state[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1629 Q=deserializer.RxD_state[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1655 Q=deserializer.RxD_state[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1653 Q=deserializer.RxD_state[2] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.X[0] Q=deserializer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[1] Q=deserializer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[2] Q=deserializer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[3] Q=deserializer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[4] Q=deserializer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[5] Q=deserializer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[6] Q=deserializer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[7] Q=deserializer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[8] Q=deserializer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[9] Q=deserializer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[10] Q=deserializer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.Y[11] Q=deserializer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$591.CO[11] Q=deserializer.OversamplingTick +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1627 Q=deserializer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1623 Q=deserializer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1647 Q=deserializer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1619 Q=deserializer.RxD_data[0] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1617 Q=deserializer.RxD_data[1] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1615 Q=deserializer.RxD_data[2] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1613 Q=deserializer.RxD_data[3] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1611 Q=deserializer.RxD_data[4] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1609 Q=deserializer.RxD_data[5] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1607 Q=deserializer.RxD_data[6] +.subckt dff C=clk D=$abc$1877$auto$rtlil.cc:2693:MuxGate$1649 Q=deserializer.RxD_data[7] +.subckt dff C=clk D=$abc$1877$flatten\deserializer.$0\RxD_data_ready[0:0] Q=deserializer.RxD_data_ready +.names deserializer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$591.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$591.CO[12] +1 1 +.names $auto$alumacc.cc:485:replace_alu$591.X[0] $auto$alumacc.cc:485:replace_alu$591.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$591.CO[11] $auto$alumacc.cc:485:replace_alu$591.Y[12] +1 1 +.names deserializer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$591.X[3] +1 1 +.names deserializer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$591.X[5] +1 1 +.names deserializer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$591.X[6] +1 1 +.names deserializer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$591.X[8] +1 1 +.names deserializer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$591.X[9] +1 1 +.names deserializer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$591.X[10] +1 1 +.names deserializer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$591.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$591.X[12] +1 1 +.names PWM_out PWM_accumulator[8] +1 1 +.names deserializer.OversamplingTick deserializer.tickgen.Acc[16] +1 1 +.names $auto$alumacc.cc:485:replace_alu$579.X[0] $auto$alumacc.cc:485:replace_alu$579.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$579.CO[7] $auto$alumacc.cc:485:replace_alu$579.Y[8] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$579.X[8] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$579.CO[8] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif new file mode 100644 index 00000000000..dad3d8629d9 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/PushButton_Debouncer.blif @@ -0,0 +1,204 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model PushButton_Debouncer +.inputs clk PB +.outputs PB_state PB_down PB_up +.names $false +.names $true +1 +.names $undef +.names $abc$913$new_n43 PB_sync_1 PB_state $abc$913$auto$rtlil.cc:2693:MuxGate$832 +001 1 +011 1 +110 1 +111 1 +.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $abc$913$new_n43 +1111 1 +.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $abc$913$new_n44 +11111 1 +.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $abc$913$new_n45 +11111 1 +.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $abc$913$new_n46 +11111 1 +.names PB_sync_1 PB_state PB_idle +00 1 +11 1 +.names PB_sync_1 $abc$913$new_n43 PB_state PB_down +110 1 +.names $abc$913$new_n43 PB_state PB_sync_1 PB_up +110 1 +.names PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[1] +01 1 +10 1 +.names PB_cnt[2] PB_cnt[1] PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.Y[2] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[3] PB_cnt[1] PB_cnt[0] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[4] PB_cnt[1] PB_cnt[0] PB_cnt[3] PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[5] +01 1 +10 1 +.names PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[6] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[8] PB_cnt[7] PB_cnt[6] PB_cnt[5] $abc$913$new_n46 $auto$alumacc.cc:485:replace_alu$424.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[9] +01 1 +10 1 +.names PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[10] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB_cnt[12] PB_cnt[11] PB_cnt[10] PB_cnt[9] $abc$913$new_n45 $auto$alumacc.cc:485:replace_alu$424.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[13] +01 1 +10 1 +.names PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[14] +011 1 +100 1 +101 1 +110 1 +.names PB_cnt[15] PB_cnt[14] PB_cnt[13] $abc$913$new_n44 $auto$alumacc.cc:485:replace_alu$424.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PB $0\PB_sync_0[0:0] +0 1 +.names PB_cnt[0] $auto$alumacc.cc:485:replace_alu$424.X[0] +0 1 +.subckt dff C=clk D=$abc$913$auto$rtlil.cc:2693:MuxGate$832 Q=PB_state +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.X[0] Q=PB_cnt[0] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[1] Q=PB_cnt[1] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[2] Q=PB_cnt[2] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[3] Q=PB_cnt[3] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[4] Q=PB_cnt[4] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[5] Q=PB_cnt[5] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[6] Q=PB_cnt[6] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[7] Q=PB_cnt[7] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[8] Q=PB_cnt[8] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[9] Q=PB_cnt[9] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[10] Q=PB_cnt[10] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[11] Q=PB_cnt[11] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[12] Q=PB_cnt[12] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[13] Q=PB_cnt[13] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[14] Q=PB_cnt[14] R=PB_idle +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$424.Y[15] Q=PB_cnt[15] R=PB_idle +.subckt dff C=clk D=PB_sync_0 Q=PB_sync_1 +.subckt dff C=clk D=$0\PB_sync_0[0:0] Q=PB_sync_0 +.names $auto$alumacc.cc:485:replace_alu$424.X[0] $auto$alumacc.cc:485:replace_alu$424.Y[0] +1 1 +.names PB_cnt[1] $auto$alumacc.cc:485:replace_alu$424.X[1] +1 1 +.names PB_cnt[2] $auto$alumacc.cc:485:replace_alu$424.X[2] +1 1 +.names PB_cnt[3] $auto$alumacc.cc:485:replace_alu$424.X[3] +1 1 +.names PB_cnt[4] $auto$alumacc.cc:485:replace_alu$424.X[4] +1 1 +.names PB_cnt[5] $auto$alumacc.cc:485:replace_alu$424.X[5] +1 1 +.names PB_cnt[6] $auto$alumacc.cc:485:replace_alu$424.X[6] +1 1 +.names PB_cnt[7] $auto$alumacc.cc:485:replace_alu$424.X[7] +1 1 +.names PB_cnt[8] $auto$alumacc.cc:485:replace_alu$424.X[8] +1 1 +.names PB_cnt[9] $auto$alumacc.cc:485:replace_alu$424.X[9] +1 1 +.names PB_cnt[10] $auto$alumacc.cc:485:replace_alu$424.X[10] +1 1 +.names PB_cnt[11] $auto$alumacc.cc:485:replace_alu$424.X[11] +1 1 +.names PB_cnt[12] $auto$alumacc.cc:485:replace_alu$424.X[12] +1 1 +.names PB_cnt[13] $auto$alumacc.cc:485:replace_alu$424.X[13] +1 1 +.names PB_cnt[14] $auto$alumacc.cc:485:replace_alu$424.X[14] +1 1 +.names PB_cnt[15] $auto$alumacc.cc:485:replace_alu$424.X[15] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif new file mode 100644 index 00000000000..8cf4e1f6f4d --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/RCServo.blif @@ -0,0 +1,735 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model RCServo +.inputs clk RxD +.outputs RCServo_pulse +.names $false +.names $true +1 +.names $undef +.names deserialer.RxD_data_ready RxD_data_reg[5] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1953 +010 1 +011 1 +101 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[4] RxD_data_reg[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1955 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[3] RxD_data_reg[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1957 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[2] RxD_data_reg[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1959 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[1] RxD_data_reg[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1961 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[0] RxD_data_reg[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1963 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.Filter_cnt[0] deserialer.Filter_cnt[1] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1965 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[7] deserialer.RxD_data[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$1967 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[3] $abc$2311$new_n153 $abc$2311$new_n152 +11 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick deserialer.OversamplingCnt[2] $abc$2311$new_n153 +1110 1 +.names $abc$2311$new_n152 deserialer.RxD_data[6] deserialer.RxD_data[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$1969 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[5] deserialer.RxD_data[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$1971 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[4] deserialer.RxD_data[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1973 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[3] deserialer.RxD_data[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1975 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[2] deserialer.RxD_data[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$1977 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n152 deserialer.RxD_data[1] deserialer.RxD_data[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$1979 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingCnt[1] deserialer.OversamplingCnt[0] deserialer.OversamplingTick $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1983 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n161 +0000 1 +.names deserialer.OversamplingTick deserialer.OversamplingCnt[0] $abc$2311$new_n161 $abc$2311$auto$rtlil.cc:2693:MuxGate$1987 +010 1 +011 1 +100 1 +.names deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$1989 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$2311$new_n165 $abc$2311$new_n161 deserialer.RxD_bit $abc$2311$new_n164 +000 1 +001 1 +010 1 +.names $abc$2311$new_n153 deserialer.RxD_state[0] deserialer.RxD_state[1] deserialer.RxD_state[2] deserialer.RxD_state[3] $abc$2311$new_n165 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names $abc$2311$new_n164 deserialer.RxD_state[0] $abc$2311$new_n161 deserialer.RxD_state[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$1991 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names PulseCount[10] PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1993 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[8] $abc$2311$new_n169 $abc$2311$new_n168 +11 1 +.names PulseCount[4] PulseCount[5] PulseCount[6] PulseCount[7] $abc$2311$new_n170 $abc$2311$new_n169 +11111 1 +.names PulseCount[0] PulseCount[1] PulseCount[2] PulseCount[3] ClkTick $abc$2311$new_n170 +11111 1 +.names PulseCount[9] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$1995 +01 1 +10 1 +.names PulseCount[8] $abc$2311$new_n169 $abc$2311$auto$rtlil.cc:2693:MuxGate$1997 +01 1 +10 1 +.names PulseCount[7] PulseCount[4] PulseCount[5] PulseCount[6] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$1999 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PulseCount[6] PulseCount[4] PulseCount[5] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2001 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PulseCount[5] PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2003 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[4] $abc$2311$new_n170 $abc$2311$auto$rtlil.cc:2693:MuxGate$2005 +01 1 +10 1 +.names PulseCount[3] PulseCount[0] PulseCount[1] PulseCount[2] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2007 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names PulseCount[2] PulseCount[0] PulseCount[1] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2009 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names PulseCount[1] PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2011 +011 1 +100 1 +101 1 +110 1 +.names PulseCount[0] ClkTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2013 +01 1 +10 1 +.names $abc$2311$new_n182 RxD_data_reg[6] RCServo_position[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2015 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n183 PulseCount[2] PulseCount[3] PulseCount[4] PulseCount[5] $abc$2311$new_n182 +10000 1 +.names $abc$2311$new_n184 PulseCount[0] PulseCount[1] PulseCount[6] PulseCount[7] $abc$2311$new_n183 +10000 1 +.names PulseCount[11] PulseCount[8] PulseCount[9] PulseCount[10] $abc$2311$new_n184 +0000 1 +.names $abc$2311$new_n182 RxD_data_reg[5] RCServo_position[5] $abc$2311$auto$rtlil.cc:2693:MuxGate$2017 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[4] RCServo_position[4] $abc$2311$auto$rtlil.cc:2693:MuxGate$2019 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[3] RCServo_position[3] $abc$2311$auto$rtlil.cc:2693:MuxGate$2021 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[2] RCServo_position[2] $abc$2311$auto$rtlil.cc:2693:MuxGate$2023 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[1] RCServo_position[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2025 +001 1 +011 1 +110 1 +111 1 +.names $abc$2311$new_n182 RxD_data_reg[0] RCServo_position[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2027 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick RxD deserialer.RxD_sync[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2029 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[7] RxD_data_reg[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2031 +001 1 +011 1 +110 1 +111 1 +.names PulseCount[11] PulseCount[9] PulseCount[10] $abc$2311$new_n168 $abc$2311$auto$rtlil.cc:2693:MuxGate$2033 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$2311$new_n182 RxD_data_reg[7] RCServo_position[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2035 +001 1 +011 1 +110 1 +111 1 +.names deserialer.OversamplingTick deserialer.RxD_sync[0] deserialer.RxD_sync[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2037 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_bit deserialer.Filter_cnt[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2041 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.Filter_cnt[1] deserialer.RxD_sync[1] deserialer.OversamplingTick deserialer.Filter_cnt[0] $abc$2311$auto$rtlil.cc:2693:MuxGate$2043 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names deserialer.OversamplingCnt[2] $abc$2311$new_n161 deserialer.OversamplingCnt[0] deserialer.OversamplingCnt[1] deserialer.OversamplingTick $abc$2311$auto$rtlil.cc:2693:MuxGate$2047 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$2311$new_n152 deserialer.RxD_bit deserialer.RxD_data[7] $abc$2311$auto$rtlil.cc:2693:MuxGate$2049 +001 1 +011 1 +110 1 +111 1 +.names deserialer.RxD_state[2] deserialer.RxD_state[3] deserialer.RxD_state[0] deserialer.RxD_state[1] $abc$2311$new_n164 $abc$2311$auto$rtlil.cc:2693:MuxGate$2053 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_state[3] deserialer.RxD_state[0] $abc$2311$new_n164 deserialer.RxD_state[2] deserialer.RxD_state[1] $abc$2311$auto$rtlil.cc:2693:MuxGate$2055 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names deserialer.RxD_data_ready deserialer.RxD_data[6] RxD_data_reg[6] $abc$2311$auto$rtlil.cc:2693:MuxGate$2057 +001 1 +011 1 +110 1 +111 1 +.names ClkCount[5] $abc$2311$new_n204 ClkCount[4] ClkCount[3] $0\ClkTick[0:0] +1100 1 +.names ClkCount[6] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n204 +1000 1 +.names $abc$2311$new_n206 $abc$2311$new_n153 $abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] +11 1 +.names deserialer.RxD_bit deserialer.RxD_state[1] deserialer.RxD_state[3] deserialer.RxD_state[2] deserialer.RxD_state[0] $abc$2311$new_n206 +11000 1 +.names PulseCount[2] RCServo_position[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n210 $abc$2311$new_n209 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names PulseCount[0] RCServo_position[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n210 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$2311$new_n212 RCServo_position[4] PulseCount[4] RCServo_position[5] PulseCount[5] $abc$2311$new_n211 +10000 1 +10011 1 +11100 1 +11111 1 +.names PulseCount[6] RCServo_position[6] RCServo_position[7] PulseCount[7] $abc$2311$new_n212 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$2311$new_n214 $abc$2311$new_n212 $abc$2311$new_n215 PulseCount[5] RCServo_position[5] $abc$2311$new_n213 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names RCServo_position[6] RCServo_position[7] PulseCount[6] PulseCount[7] $abc$2311$new_n214 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names RCServo_position[5] PulseCount[5] RCServo_position[4] PulseCount[4] $abc$2311$new_n215 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names RCServo_position[2] PulseCount[2] RCServo_position[3] PulseCount[3] $abc$2311$new_n217 +0000 1 +0011 1 +1100 1 +1111 1 +.names RCServo_position[0] PulseCount[0] RCServo_position[1] PulseCount[1] $abc$2311$new_n218 +0000 1 +0011 1 +1100 1 +1111 1 +.names ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[1] +01 1 +10 1 +.names ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[2] +011 1 +100 1 +101 1 +110 1 +.names ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[5] +01 1 +10 1 +.names ClkCount[4] ClkCount[3] ClkCount[2] ClkCount[1] ClkCount[0] $abc$2311$new_n224 +11111 1 +.names ClkCount[6] ClkCount[5] $abc$2311$new_n224 $auto$alumacc.cc:485:replace_alu$613.Y[6] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[1] +00 1 +11 1 +.names deserialer.tickgen.Acc[6] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.Y[2] +000 1 +101 1 +110 1 +111 1 +.names deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[3] +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $auto$alumacc.cc:485:replace_alu$628.Y[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[5] +00 1 +11 1 +.names deserialer.tickgen.Acc[8] deserialer.tickgen.Acc[7] deserialer.tickgen.Acc[5] deserialer.tickgen.Acc[4] deserialer.tickgen.Acc[6] $abc$2311$new_n231 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[6] +010 1 +100 1 +101 1 +111 1 +.names deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1110 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $auto$alumacc.cc:485:replace_alu$628.Y[8] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[9] +01 1 +10 1 +.names deserialer.tickgen.Acc[12] deserialer.tickgen.Acc[11] deserialer.tickgen.Acc[10] deserialer.tickgen.Acc[9] $abc$2311$new_n231 $abc$2311$new_n236 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[10] +011 1 +100 1 +101 1 +110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names deserialer.tickgen.Acc[15] deserialer.tickgen.Acc[14] deserialer.tickgen.Acc[13] $abc$2311$new_n236 $auto$alumacc.cc:485:replace_alu$628.CO[11] +1111 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.X[0] +0 1 +.names ClkCount[0] $auto$alumacc.cc:485:replace_alu$613.X[0] +0 1 +.names $abc$2311$new_n211 $abc$2311$new_n213 $abc$2311$new_n209 $abc$2311$new_n218 $abc$2311$new_n217 $abc$2311$new_n242 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names PulseCount[9] PulseCount[11] PulseCount[10] PulseCount[8] $abc$2311$new_n242 $0\RCServo_pulse[0:0] +00000 1 +00001 1 +00010 1 +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.X[0] Q=deserialer.tickgen.Acc[4] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[1] Q=deserialer.tickgen.Acc[5] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[2] Q=deserialer.tickgen.Acc[6] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[3] Q=deserialer.tickgen.Acc[7] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[4] Q=deserialer.tickgen.Acc[8] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[5] Q=deserialer.tickgen.Acc[9] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[6] Q=deserialer.tickgen.Acc[10] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[7] Q=deserialer.tickgen.Acc[11] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[8] Q=deserialer.tickgen.Acc[12] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[9] Q=deserialer.tickgen.Acc[13] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[10] Q=deserialer.tickgen.Acc[14] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.Y[11] Q=deserialer.tickgen.Acc[15] +.subckt dff C=clk D=$auto$alumacc.cc:485:replace_alu$628.CO[11] Q=deserialer.OversamplingTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1987 Q=deserialer.OversamplingCnt[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1983 Q=deserialer.OversamplingCnt[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2047 Q=deserialer.OversamplingCnt[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1979 Q=deserialer.RxD_data[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1977 Q=deserialer.RxD_data[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1975 Q=deserialer.RxD_data[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1973 Q=deserialer.RxD_data[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1971 Q=deserialer.RxD_data[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1969 Q=deserialer.RxD_data[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1967 Q=deserialer.RxD_data[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2049 Q=deserialer.RxD_data[7] +.subckt dff C=clk D=$abc$2311$flatten\deserialer.$0\RxD_data_ready[0:0] Q=deserialer.RxD_data_ready +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.X[0] Q=ClkCount[0] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[1] Q=ClkCount[1] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[2] Q=ClkCount[2] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[3] Q=ClkCount[3] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[4] Q=ClkCount[4] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[5] Q=ClkCount[5] R=ClkTick +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$613.Y[6] Q=ClkCount[6] R=ClkTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2041 Q=deserialer.RxD_bit +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1965 Q=deserialer.Filter_cnt[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2043 Q=deserialer.Filter_cnt[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1963 Q=RxD_data_reg[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1961 Q=RxD_data_reg[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1959 Q=RxD_data_reg[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1957 Q=RxD_data_reg[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1955 Q=RxD_data_reg[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1953 Q=RxD_data_reg[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2057 Q=RxD_data_reg[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2031 Q=RxD_data_reg[7] +.subckt dff C=clk D=$0\RCServo_pulse[0:0] Q=RCServo_pulse +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2029 Q=deserialer.RxD_sync[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2037 Q=deserialer.RxD_sync[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2027 Q=RCServo_position[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2025 Q=RCServo_position[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2023 Q=RCServo_position[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2021 Q=RCServo_position[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2019 Q=RCServo_position[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2017 Q=RCServo_position[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2015 Q=RCServo_position[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2035 Q=RCServo_position[7] +.subckt dff C=clk D=$0\ClkTick[0:0] Q=ClkTick +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2013 Q=PulseCount[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2011 Q=PulseCount[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2009 Q=PulseCount[2] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2007 Q=PulseCount[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2005 Q=PulseCount[4] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2003 Q=PulseCount[5] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2001 Q=PulseCount[6] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1999 Q=PulseCount[7] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1997 Q=PulseCount[8] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1995 Q=PulseCount[9] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1993 Q=PulseCount[10] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2033 Q=PulseCount[11] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1991 Q=deserialer.RxD_state[0] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$1989 Q=deserialer.RxD_state[1] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2055 Q=deserialer.RxD_state[3] +.subckt dff C=clk D=$abc$2311$auto$rtlil.cc:2693:MuxGate$2053 Q=deserialer.RxD_state[2] +.names $auto$alumacc.cc:485:replace_alu$628.X[0] $auto$alumacc.cc:485:replace_alu$628.Y[0] +1 1 +.names $auto$alumacc.cc:485:replace_alu$628.CO[11] $auto$alumacc.cc:485:replace_alu$628.Y[12] +1 1 +.names deserialer.tickgen.Acc[7] $auto$alumacc.cc:485:replace_alu$628.X[3] +1 1 +.names deserialer.tickgen.Acc[9] $auto$alumacc.cc:485:replace_alu$628.X[5] +1 1 +.names deserialer.tickgen.Acc[10] $auto$alumacc.cc:485:replace_alu$628.X[6] +1 1 +.names deserialer.tickgen.Acc[12] $auto$alumacc.cc:485:replace_alu$628.X[8] +1 1 +.names deserialer.tickgen.Acc[13] $auto$alumacc.cc:485:replace_alu$628.X[9] +1 1 +.names deserialer.tickgen.Acc[14] $auto$alumacc.cc:485:replace_alu$628.X[10] +1 1 +.names deserialer.tickgen.Acc[15] $auto$alumacc.cc:485:replace_alu$628.X[11] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$628.X[12] +1 1 +.names deserialer.tickgen.Acc[4] $auto$alumacc.cc:485:replace_alu$628.CO[0] +1 1 +.names $false $auto$alumacc.cc:485:replace_alu$628.CO[12] +1 1 +.names $auto$alumacc.cc:485:replace_alu$613.X[0] $auto$alumacc.cc:485:replace_alu$613.Y[0] +1 1 +.names ClkCount[1] $auto$alumacc.cc:485:replace_alu$613.X[1] +1 1 +.names ClkCount[2] $auto$alumacc.cc:485:replace_alu$613.X[2] +1 1 +.names ClkCount[3] $auto$alumacc.cc:485:replace_alu$613.X[3] +1 1 +.names ClkCount[4] $auto$alumacc.cc:485:replace_alu$613.X[4] +1 1 +.names ClkCount[5] $auto$alumacc.cc:485:replace_alu$613.X[5] +1 1 +.names ClkCount[6] $auto$alumacc.cc:485:replace_alu$613.X[6] +1 1 +.names deserialer.OversamplingTick deserialer.tickgen.Acc[16] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif new file mode 100644 index 00000000000..909b5033223 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/TaskAck_CrossDomain.blif @@ -0,0 +1,53 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model TaskAck_CrossDomain +.inputs clkA TaskStart_clkA clkB TaskDone_clkB +.outputs TaskBusy_clkA TaskDone_clkA TaskStart_clkB TaskBusy_clkB +.names $false +.names $true +1 +.names $undef +.names $abc$605$new_n19 FlagToggle_clkA FlagToggle_clkB $abc$605$auto$rtlil.cc:2693:MuxGate$526 +001 1 +011 1 +110 1 +111 1 +.names TaskDone_clkB SyncA_clkB[2] SyncA_clkB[1] Busyhold_clkB $abc$605$new_n19 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names SyncA_clkB[2] SyncA_clkB[1] TaskStart_clkB +01 1 +10 1 +.names SyncB_clkA[2] SyncB_clkA[1] TaskDone_clkA +01 1 +10 1 +.names SyncB_clkA[2] FlagToggle_clkA TaskBusy_clkA +01 1 +10 1 +.names TaskStart_clkA FlagToggle_clkA SyncB_clkA[2] $0\FlagToggle_clkA[0:0] +010 1 +011 1 +100 1 +110 1 +.names Busyhold_clkB TaskStart_clkB TaskBusy_clkB +01 1 +10 1 +11 1 +.names TaskDone_clkB TaskStart_clkB Busyhold_clkB $0\Busyhold_clkB[0:0] +001 1 +010 1 +011 1 +.subckt dff C=clkB D=$abc$605$auto$rtlil.cc:2693:MuxGate$526 Q=FlagToggle_clkB +.subckt dff C=clkA D=FlagToggle_clkB Q=SyncB_clkA[0] +.subckt dff C=clkA D=SyncB_clkA[0] Q=SyncB_clkA[1] +.subckt dff C=clkA D=SyncB_clkA[1] Q=SyncB_clkA[2] +.subckt dff C=clkB D=$0\Busyhold_clkB[0:0] Q=Busyhold_clkB +.subckt dff C=clkB D=FlagToggle_clkA Q=SyncA_clkB[0] +.subckt dff C=clkB D=SyncA_clkB[0] Q=SyncA_clkB[1] +.subckt dff C=clkB D=SyncA_clkB[1] Q=SyncA_clkB[2] +.subckt dff C=clkA D=$0\FlagToggle_clkA[0:0] Q=FlagToggle_clkA +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif new file mode 100644 index 00000000000..d81a68f31e7 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv.blif @@ -0,0 +1,10133 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset +.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] +.names $false +.names $true +1 +.names $undef +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 +111 1 +.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 +111 1 +.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 +000 1 +001 1 +010 1 +.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 +11 1 +.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 +1100 1 +1111 1 +.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 +10000 1 +10011 1 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 +00 1 +11 1 +.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 +1100 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid +11 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 +11 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 +1100 1 +1111 1 +.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 +10 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 +11 1 +.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 +1001 1 +1010 1 +1011 1 +.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 +00000 1 +.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 +00001 1 +00010 1 +00011 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 +10 1 +.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 +11 1 +.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 +1000 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7767 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7769 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7771 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7773 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7775 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7777 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7779 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7781 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7783 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7785 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7787 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7789 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7791 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7793 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7795 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7797 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7861 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 $abc$8788$new_n1445 $abc$8788$new_n1325 execute_LightShifterPlugin_isActive $abc$8788$auto$rtlil.cc:2693:MuxGate$7863 +1001 1 +1011 1 +1100 1 +1101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid CsrPlugin_pipelineLiberator_pcValids_1 $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7865 +1111 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n1488 $abc$8788$auto$rtlil.cc:2693:MuxGate$7867 +1110 1 +.names $abc$8788$new_n1321 CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$new_n1488 +000 1 +010 1 +100 1 +101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n2458 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$auto$rtlil.cc:2693:MuxGate$7869 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1492 CsrPlugin_mie_MSIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7871 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n1491 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1493 $abc$8788$new_n1492 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1494 execute_CsrPlugin_csr_772 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MIE $abc$8788$new_n1493 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] CsrPlugin_mip_MSIP execute_CsrPlugin_csr_836 $abc$8788$new_n1494 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1496 CsrPlugin_mie_MTIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7873 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1497 $abc$8788$new_n1496 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1498 execute_CsrPlugin_csr_836 CsrPlugin_mip_MTIP $abc$8788$new_n1497 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE CsrPlugin_mstatus_MPIE execute_CsrPlugin_csr_768 $abc$8788$new_n1498 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1500 CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7875 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1501 $abc$8788$new_n1500 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1502 execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$8788$new_n1501 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE CsrPlugin_mstatus_MPP[0] execute_CsrPlugin_csr_768 $abc$8788$new_n1502 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_injector_decodeInput_valid IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7877 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1270 $abc$8788$new_n1505 $abc$8788$new_n2461 $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7879 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names iBus_cmd_ready iBus_cmd_valid $abc$8788$new_n1505 +11 1 +.names $abc$8788$new_n1507 $abc$8788$new_n2461 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid iBus_cmd_valid +1100 1 +1110 1 +1111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n1271 IBusSimplePlugin_pending_value[2] IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[0] $abc$8788$new_n1507 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8788$new_n1509 $abc$8788$new_n1505 $abc$8788$auto$rtlil.cc:2693:MuxGate$7881 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_fetchPc_inc $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$new_n1509 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$8788$new_n1271 $abc$8788$new_n1321 $abc$8788$new_n2458 execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7883 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2461 execute_arbitration_isValid $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7885 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive $abc$8788$new_n1513 execute_LightShifterPlugin_amplitudeReg[4] $abc$8788$new_n1445 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7949 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 execute_LightShifterPlugin_isActive $abc$8788$new_n1446 execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$new_n1513 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1517 CsrPlugin_interrupt_code[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7953 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$8788$new_n1517 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$8788$new_n1516 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$new_n1517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1516 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7957 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n1330 $abc$8788$new_n1455 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$auto$rtlil.cc:2693:MuxGate$7961 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7963 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$new_n1522 $abc$8788$new_n1523 iBus_cmd_payload_pc[31] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$new_n1255 $abc$8788$new_n1522 +11111 1 +.names BranchPlugin_jumpInterface_payload[31] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[31] $abc$8788$new_n1523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[31] IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7967 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7969 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[31] CsrPlugin_mepc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7975 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1594 $abc$8788$new_n1590 dBus_cmd_payload_address[30] $abc$8788$new_n1595 $abc$8788$auto$rtlil.cc:2693:MuxGate$7057 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1529 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[30] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 $abc$8788$new_n1529 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1584 $abc$8788$new_n1531 $abc$8788$new_n1530 +00 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1581 $abc$8788$new_n1531 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1533 $abc$8788$new_n1580 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1578 $abc$8788$new_n1532 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1534 $abc$8788$new_n1577 _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1575 $abc$8788$new_n1533 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1535 $abc$8788$new_n1574 _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1572 $abc$8788$new_n1534 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1536 $abc$8788$new_n1569 _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1570 $abc$8788$new_n1535 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1537 $abc$8788$new_n1568 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1565 $abc$8788$new_n1536 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1538 $abc$8788$new_n1564 _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1562 $abc$8788$new_n1537 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1559 $abc$8788$new_n1557 $abc$8788$new_n1561 $abc$8788$new_n1560 $abc$8788$new_n1539 $abc$8788$new_n1538 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1540 $abc$8788$new_n1539 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1554 $abc$8788$new_n1541 $abc$8788$new_n1553 $abc$8788$new_n1540 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1542 $abc$8788$new_n1541 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n1548 _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1549 $abc$8788$new_n1543 $abc$8788$new_n1542 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[3] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1544 $abc$8788$new_n1543 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[3] $abc$8788$new_n1544 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[2] $abc$8788$new_n1545 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[1] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[1] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01100 1 +10100 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[5] $abc$8788$new_n1547 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1548 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1549 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[7] $abc$8788$new_n1550 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[6] $abc$8788$new_n1551 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[9] $abc$8788$new_n1552 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[8] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[8] $abc$8788$new_n1553 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n1554 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[11] $abc$8788$new_n1555 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[10] $abc$8788$new_n1556 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1558 $abc$8788$new_n1557 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[12] $abc$8788$new_n1558 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n1559 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n1560 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] $abc$8788$new_n1561 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n1562 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[15] $abc$8788$new_n1563 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1564 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1565 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[18] $abc$8788$new_n1566 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[17] $abc$8788$new_n1567 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1568 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1569 +10 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n1570 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[19] $abc$8788$new_n1571 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n1572 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[21] $abc$8788$new_n1573 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1574 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n1575 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[23] $abc$8788$new_n1576 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1577 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n1578 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[25] $abc$8788$new_n1579 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1580 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n1581 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[27] $abc$8788$new_n1582 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[26] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[26] $abc$8788$new_n1583 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1584 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[29] $abc$8788$new_n1585 +00 1 +11 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1587 $abc$8788$new_n1586 +11 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 $abc$8788$new_n1587 +00 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1322 $abc$8788$new_n1588 +00 1 +.names _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$8788$new_n1589 +10 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[30] $abc$8788$new_n1323 $abc$8788$new_n1591 $abc$8788$new_n1590 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 +10 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 +10 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 +00 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[15] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[15] $abc$8788$new_n1323 $abc$8788$new_n1692 $abc$8788$new_n1691 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1693 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1692 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[14] _zz_execute_SrcPlugin_addSub_2[14] $abc$8788$new_n1693 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 +10 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1560 $abc$8788$new_n1558 $abc$8788$new_n1699 _zz_execute_SrcPlugin_addSub_2[13] dBus_cmd_payload_address[13] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1707 $abc$8788$new_n1693 $abc$8788$new_n1706 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[12] _zz_execute_SrcPlugin_addSub_2[12] $abc$8788$new_n1707 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1708 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1710 execute_to_memory_REGFILE_WRITE_DATA[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7093 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1711 $abc$8788$new_n1592 $abc$8788$new_n1323 $abc$8788$new_n1715 $abc$8788$new_n1701 $abc$8788$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$8788$new_n1713 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[12] $abc$8788$new_n1714 $abc$8788$new_n1711 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1539 $abc$8788$new_n1561 _zz_execute_SrcPlugin_addSub_2[12] dBus_cmd_payload_address[12] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1323 execute_CsrPlugin_csr_768 $abc$8788$new_n1322 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1713 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1720 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[11] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1540 $abc$8788$new_n1720 +000 1 +100 1 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1721 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1723 $abc$8788$new_n1707 $abc$8788$new_n1722 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[10] _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1723 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1725 execute_to_memory_REGFILE_WRITE_DATA[10] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7097 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1727 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[9] $abc$8788$new_n1731 $abc$8788$new_n1735 $abc$8788$auto$rtlil.cc:2693:MuxGate$7099 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1734 dBus_cmd_payload_address[9] $abc$8788$new_n1595 $abc$8788$new_n1731 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1733 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[9] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1553 $abc$8788$new_n1541 $abc$8788$new_n1554 $abc$8788$new_n1733 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1734 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1736 $abc$8788$new_n1723 $abc$8788$new_n1735 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[8] _zz_execute_SrcPlugin_addSub_2[8] $abc$8788$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[8] $abc$8788$new_n1738 $abc$8788$new_n1741 $abc$8788$auto$rtlil.cc:2693:MuxGate$7101 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1740 dBus_cmd_payload_address[8] $abc$8788$new_n1595 $abc$8788$new_n1738 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1541 $abc$8788$new_n1554 _zz_execute_SrcPlugin_addSub_2[8] dBus_cmd_payload_address[8] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 +000 1 +010 1 +100 1 +101 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 +000 1 +001 1 +010 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 +101 1 +110 1 +.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 +000 1 +010 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] +010 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 +000 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 +1000 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 +00 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 +11000 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7389 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7391 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7393 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7395 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7397 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7399 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7401 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7403 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7405 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7407 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7409 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7411 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7413 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7415 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7417 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7419 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7421 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7423 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7505 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7507 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7509 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7511 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7513 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7515 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7517 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7519 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7521 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7523 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7525 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7527 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7529 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7531 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7533 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7535 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7537 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7539 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7541 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7543 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7545 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7547 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7549 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7551 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7553 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7555 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7557 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7559 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7561 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2004 BranchPlugin_jumpInterface_payload[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7563 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2059 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 $abc$8788$new_n2004 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2057 $abc$8788$new_n2056 $abc$8788$new_n2006 $abc$8788$new_n2005 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2020 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2007 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2006 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2054 $abc$8788$new_n2008 $abc$8788$new_n2007 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2053 $abc$8788$new_n2052 $abc$8788$new_n2051 $abc$8788$new_n2009 $abc$8788$new_n2008 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2049 $abc$8788$new_n2047 $abc$8788$new_n2010 $abc$8788$new_n2009 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2045 $abc$8788$new_n2043 $abc$8788$new_n2011 $abc$8788$new_n2010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2042 $abc$8788$new_n2040 $abc$8788$new_n2041 $abc$8788$new_n2039 $abc$8788$new_n2012 $abc$8788$new_n2011 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2036 $abc$8788$new_n2013 $abc$8788$new_n2012 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2032 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2014 $abc$8788$new_n2013 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$8788$new_n2030 _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$new_n2029 $abc$8788$new_n2015 $abc$8788$new_n2014 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2016 $abc$8788$new_n2015 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2017 $abc$8788$new_n2016 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2017 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2018 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[2] decode_to_execute_PC[2] $abc$8788$new_n2019 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2020 +11 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2[10] _zz__zz_execute_BranchPlugin_branch_src2[0] decode_to_execute_RS1[1] $abc$8788$new_n2021 +10011 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[3] decode_to_execute_PC[3] $abc$8788$new_n2023 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[5] decode_to_execute_PC[5] $abc$8788$new_n2024 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[4] decode_to_execute_PC[4] $abc$8788$new_n2025 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$new_n2026 +000 1 +001 1 +100 1 +110 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[7] decode_to_execute_PC[7] $abc$8788$new_n2027 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[6] decode_to_execute_PC[6] $abc$8788$new_n2028 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[9] decode_to_execute_PC[9] $abc$8788$new_n2029 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[8] decode_to_execute_PC[8] $abc$8788$new_n2030 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[11] decode_to_execute_PC[11] $abc$8788$new_n2031 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[10] decode_to_execute_PC[10] $abc$8788$new_n2032 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_4[10] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$new_n2033 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2034 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[12] decode_to_execute_PC[12] $abc$8788$new_n2035 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2036 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[13] decode_to_execute_PC[13] $abc$8788$new_n2037 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 switch_Misc_l241_1 $abc$8788$new_n2038 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[15] decode_to_execute_PC[15] $abc$8788$new_n2039 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[14] decode_to_execute_PC[14] $abc$8788$new_n2040 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$new_n2041 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2042 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[17] decode_to_execute_PC[17] $abc$8788$new_n2043 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[16] decode_to_execute_PC[16] $abc$8788$new_n2044 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$new_n2045 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$new_n2046 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[19] decode_to_execute_PC[19] $abc$8788$new_n2047 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[18] decode_to_execute_PC[18] $abc$8788$new_n2048 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$new_n2049 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$new_n2050 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[22] decode_to_execute_PC[22] $abc$8788$new_n2051 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[21] decode_to_execute_PC[21] $abc$8788$new_n2052 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[20] decode_to_execute_PC[20] $abc$8788$new_n2053 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[24] decode_to_execute_PC[24] $abc$8788$new_n2054 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[23] decode_to_execute_PC[23] $abc$8788$new_n2055 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[28] decode_to_execute_PC[28] $abc$8788$new_n2056 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[27] decode_to_execute_PC[27] $abc$8788$new_n2057 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[26] decode_to_execute_PC[26] $abc$8788$new_n2058 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[30] decode_to_execute_PC[30] $abc$8788$new_n2059 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[29] decode_to_execute_PC[29] $abc$8788$new_n2060 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 BranchPlugin_jumpInterface_payload[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7565 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2056 $abc$8788$new_n2063 BranchPlugin_jumpInterface_payload[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7567 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2057 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2064 $abc$8788$new_n2063 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2058 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2006 $abc$8788$new_n2064 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2057 $abc$8788$new_n2064 BranchPlugin_jumpInterface_payload[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7569 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2006 BranchPlugin_jumpInterface_payload[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7571 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2007 $abc$8788$new_n2068 BranchPlugin_jumpInterface_payload[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7573 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2068 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2070 BranchPlugin_jumpInterface_payload[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7575 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2054 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2008 $abc$8788$new_n2070 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2008 BranchPlugin_jumpInterface_payload[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7577 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2051 $abc$8788$new_n2073 BranchPlugin_jumpInterface_payload[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7579 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 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$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2087 BranchPlugin_jumpInterface_payload[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7597 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2013 $abc$8788$new_n2036 $abc$8788$new_n2087 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2036 $abc$8788$new_n2013 BranchPlugin_jumpInterface_payload[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7599 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2090 BranchPlugin_jumpInterface_payload[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7601 +00000 1 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_zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2015 $abc$8788$new_n2093 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2030 $abc$8788$new_n2015 BranchPlugin_jumpInterface_payload[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7607 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2096 BranchPlugin_jumpInterface_payload[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7609 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2016 $abc$8788$new_n2096 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2028 $abc$8788$new_n2016 BranchPlugin_jumpInterface_payload[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7611 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2099 BranchPlugin_jumpInterface_payload[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7613 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 $abc$8788$new_n2099 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 BranchPlugin_jumpInterface_payload[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7615 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2102 BranchPlugin_jumpInterface_payload[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7617 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2102 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2104 BranchPlugin_jumpInterface_payload[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7619 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2104 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] decode_INSTRUCTION_ANTICIPATED[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] decode_INSTRUCTION_ANTICIPATED[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] decode_INSTRUCTION_ANTICIPATED[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] decode_INSTRUCTION_ANTICIPATED[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] decode_INSTRUCTION_ANTICIPATED[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] decode_INSTRUCTION_ANTICIPATED[25] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] decode_INSTRUCTION_ANTICIPATED[14] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] decode_INSTRUCTION_ANTICIPATED[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] decode_INSTRUCTION_ANTICIPATED[12] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] decode_INSTRUCTION_ANTICIPATED[11] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] decode_INSTRUCTION_ANTICIPATED[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] decode_INSTRUCTION_ANTICIPATED[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] decode_INSTRUCTION_ANTICIPATED[8] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] decode_INSTRUCTION_ANTICIPATED[7] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] decode_INSTRUCTION_ANTICIPATED[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] decode_INSTRUCTION_ANTICIPATED[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] decode_INSTRUCTION_ANTICIPATED[4] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] decode_INSTRUCTION_ANTICIPATED[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] decode_INSTRUCTION_ANTICIPATED[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2126 _zz_execute_SrcPlugin_addSub_2[30] _zz_RegFilePlugin_regFile_port0[30] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1296 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2125 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2126 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2128 _zz_execute_SrcPlugin_addSub_2[29] _zz_RegFilePlugin_regFile_port0[29] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2128 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2130 _zz_execute_SrcPlugin_addSub_2[28] _zz_RegFilePlugin_regFile_port0[28] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7669 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2130 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2132 _zz_execute_SrcPlugin_addSub_2[27] _zz_RegFilePlugin_regFile_port0[27] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7671 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2132 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2134 _zz_execute_SrcPlugin_addSub_2[26] _zz_RegFilePlugin_regFile_port0[26] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2134 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2136 _zz_execute_SrcPlugin_addSub_2[25] _zz_RegFilePlugin_regFile_port0[25] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7675 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2136 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2138 _zz_execute_SrcPlugin_addSub_2[24] _zz_RegFilePlugin_regFile_port0[24] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7677 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2138 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2140 _zz_execute_SrcPlugin_addSub_2[23] _zz_RegFilePlugin_regFile_port0[23] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2140 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2142 _zz_execute_SrcPlugin_addSub_2[22] _zz_RegFilePlugin_regFile_port0[22] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7681 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2142 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2144 _zz_execute_SrcPlugin_addSub_2[21] _zz_RegFilePlugin_regFile_port0[21] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7683 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2144 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2146 _zz_execute_SrcPlugin_addSub_2[20] _zz_RegFilePlugin_regFile_port0[20] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7685 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2146 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2148 _zz_execute_SrcPlugin_addSub_2[19] _zz_RegFilePlugin_regFile_port0[19] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2148 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2150 _zz_execute_SrcPlugin_addSub_2[18] _zz_RegFilePlugin_regFile_port0[18] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2150 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2152 _zz_execute_SrcPlugin_addSub_2[17] _zz_RegFilePlugin_regFile_port0[17] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2152 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2154 _zz_execute_SrcPlugin_addSub_2[16] _zz_RegFilePlugin_regFile_port0[16] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7693 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2154 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2156 _zz_execute_SrcPlugin_addSub_2[15] _zz_RegFilePlugin_regFile_port0[15] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2156 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2158 _zz_execute_SrcPlugin_addSub_2[14] _zz_RegFilePlugin_regFile_port0[14] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7697 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2158 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2160 _zz_execute_SrcPlugin_addSub_2[13] _zz_RegFilePlugin_regFile_port0[13] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7699 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2160 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2162 _zz_execute_SrcPlugin_addSub_2[12] _zz_RegFilePlugin_regFile_port0[12] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7701 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2162 +11110 1 +.names $abc$8788$new_n2164 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7703 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2165 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2164 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz_RegFilePlugin_regFile_port0[2] $abc$8788$new_n2165 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2167 _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7707 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz_RegFilePlugin_regFile_port0[3] $abc$8788$new_n2167 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2168 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n2170 _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7711 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz_RegFilePlugin_regFile_port0[1] $abc$8788$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2172 _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7715 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz_RegFilePlugin_regFile_port0[0] $abc$8788$new_n2172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[10] _zz_RegFilePlugin_regFile_port0[10] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7719 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[9] _zz_RegFilePlugin_regFile_port0[9] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7723 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[8] _zz_RegFilePlugin_regFile_port0[8] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7727 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[7] _zz_RegFilePlugin_regFile_port0[7] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7731 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[6] _zz_RegFilePlugin_regFile_port0[6] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7735 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[5] _zz_RegFilePlugin_regFile_port0[5] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7739 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[30] decode_to_execute_PC[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7803 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[29] decode_to_execute_PC[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7805 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[28] decode_to_execute_PC[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7807 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[27] decode_to_execute_PC[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7809 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[26] decode_to_execute_PC[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7811 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[25] decode_to_execute_PC[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7813 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[24] decode_to_execute_PC[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7815 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[23] decode_to_execute_PC[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7817 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[22] decode_to_execute_PC[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7819 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[21] decode_to_execute_PC[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7821 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[20] decode_to_execute_PC[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7823 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[19] decode_to_execute_PC[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7825 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[18] decode_to_execute_PC[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7827 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[17] decode_to_execute_PC[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7829 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[16] decode_to_execute_PC[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7831 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[15] decode_to_execute_PC[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7833 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[14] decode_to_execute_PC[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7835 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[13] decode_to_execute_PC[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7837 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[12] decode_to_execute_PC[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7839 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[11] decode_to_execute_PC[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7841 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[10] decode_to_execute_PC[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7843 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[9] decode_to_execute_PC[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7845 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[8] decode_to_execute_PC[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7847 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[7] decode_to_execute_PC[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7849 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[6] decode_to_execute_PC[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7851 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[5] decode_to_execute_PC[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7853 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[4] decode_to_execute_PC[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7855 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[3] decode_to_execute_PC[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7857 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[2] decode_to_execute_PC[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7859 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_834 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2209 $abc$8788$auto$rtlil.cc:2693:MuxGate$7887 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2210 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2209 +11000 1 +.names $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2210 +1000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n2211 +1100 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_772 $abc$8788$new_n2214 $abc$8788$new_n2213 $abc$8788$auto$rtlil.cc:2693:MuxGate$7889 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2213 +11000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2214 +0000 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2216 execute_CsrPlugin_csr_836 $abc$8788$auto$rtlil.cc:2693:MuxGate$7891 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2213 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2216 +11000 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_768 $abc$8788$new_n2210 $abc$8788$new_n2214 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7893 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$8788$new_n2245 _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2246 $abc$8788$new_n2219 $abc$8788$new_n2242 $abc$8788$auto$rtlil.cc:2693:MuxGate$7897 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2220 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n2219 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[13] switch_Misc_l241_1 $abc$8788$new_n2221 $abc$8788$new_n2220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2236 $abc$8788$new_n2222 _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] $abc$8788$new_n2221 +1100 1 +1111 1 +.names $abc$8788$new_n2233 $abc$8788$new_n2223 $abc$8788$new_n2235 _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] $abc$8788$new_n2222 +11100 1 +11111 1 +.names $abc$8788$new_n2229 $abc$8788$new_n2224 $abc$8788$new_n2231 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n2223 +11100 1 +11111 1 +.names $abc$8788$new_n2228 $abc$8788$new_n2225 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n2227 $abc$8788$new_n2224 +11000 1 +11110 1 +.names $abc$8788$new_n2226 $abc$8788$new_n1797 _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] $abc$8788$new_n2225 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n2226 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] $abc$8788$new_n2227 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] $abc$8788$new_n2228 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2230 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] $abc$8788$new_n2229 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n2230 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n2232 $abc$8788$new_n2231 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n2232 +01 1 +10 1 +.names $abc$8788$new_n2234 _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] $abc$8788$new_n2233 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n2234 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] $abc$8788$new_n2235 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2239 $abc$8788$new_n2237 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] $abc$8788$new_n2236 +1100 1 +1111 1 +.names $abc$8788$new_n2238 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n2237 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 +01 1 +10 1 +.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 +000 1 +.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 +10 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 +00 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 +001 1 +011 1 +100 1 +101 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 +10 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 +0000 1 +.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 +01 1 +10 1 +11 1 +.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 +10000 1 +.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 +1110 1 +.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid +1110 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] decode_INSTRUCTION_ANTICIPATED[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] decode_INSTRUCTION_ANTICIPATED[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] decode_INSTRUCTION_ANTICIPATED[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1272 $0\CsrPlugin_interrupt_valid[0:0] +10 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2334 $abc$8788$new_n2335 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] +000 1 +001 1 +100 1 +110 1 +.names IBusSimplePlugin_pending_value[0] $abc$8788$new_n1454 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2334 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2335 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2339 $abc$8788$new_n2338 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1454 IBusSimplePlugin_pending_value[0] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2337 +0001 1 +0010 1 +0011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2338 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2339 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2341 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2339 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2341 +010 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[0] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][0] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2345 $abc$8788$new_n1500 $abc$8788$new_n2344 $abc$8788$new_n2343 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2344 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] switch_Misc_l241_1 dBus_cmd_payload_size[0] CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$8788$new_n2345 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1496 $abc$8788$new_n2348 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$8788$new_n1272 $abc$8788$new_n1274 CsrPlugin_mstatus_MIE CsrPlugin_mstatus_MPIE $abc$8788$new_n2348 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1492 $abc$8788$new_n2350 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1274 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$8788$new_n1272 $abc$8788$new_n2350 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names memory_arbitration_isValid $abc$8788$new_n1271 $abc$8788$new_n1321 $0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2353 memory_to_writeBack_REGFILE_WRITE_DATA[0] lastStageRegFileWrite_payload_data[0] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2354 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[16] $abc$8788$new_n2353 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[8] memory_to_writeBack_MEMORY_READ_DATA[0] $abc$8788$new_n2354 +000 1 +010 1 +100 1 +101 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsFiring $abc$8788$new_n2355 +11 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2357 memory_to_writeBack_REGFILE_WRITE_DATA[1] lastStageRegFileWrite_payload_data[1] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2358 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[17] $abc$8788$new_n2357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[9] memory_to_writeBack_MEMORY_READ_DATA[1] $abc$8788$new_n2358 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2360 memory_to_writeBack_REGFILE_WRITE_DATA[2] lastStageRegFileWrite_payload_data[2] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2361 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[18] $abc$8788$new_n2360 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[10] memory_to_writeBack_MEMORY_READ_DATA[2] $abc$8788$new_n2361 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2363 memory_to_writeBack_REGFILE_WRITE_DATA[3] lastStageRegFileWrite_payload_data[3] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2364 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[19] $abc$8788$new_n2363 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[11] memory_to_writeBack_MEMORY_READ_DATA[3] $abc$8788$new_n2364 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2366 memory_to_writeBack_REGFILE_WRITE_DATA[4] lastStageRegFileWrite_payload_data[4] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2367 writeBack_MEMORY_READ_DATA[28] writeBack_MEMORY_READ_DATA[20] $abc$8788$new_n2366 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[12] memory_to_writeBack_MEMORY_READ_DATA[4] $abc$8788$new_n2367 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2369 memory_to_writeBack_REGFILE_WRITE_DATA[5] lastStageRegFileWrite_payload_data[5] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2370 writeBack_MEMORY_READ_DATA[29] writeBack_MEMORY_READ_DATA[21] $abc$8788$new_n2369 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[13] memory_to_writeBack_MEMORY_READ_DATA[5] $abc$8788$new_n2370 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2372 memory_to_writeBack_REGFILE_WRITE_DATA[6] lastStageRegFileWrite_payload_data[6] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2373 writeBack_MEMORY_READ_DATA[30] writeBack_MEMORY_READ_DATA[22] $abc$8788$new_n2372 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[14] memory_to_writeBack_MEMORY_READ_DATA[6] $abc$8788$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2375 memory_to_writeBack_REGFILE_WRITE_DATA[7] lastStageRegFileWrite_payload_data[7] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2376 writeBack_MEMORY_READ_DATA[31] writeBack_MEMORY_READ_DATA[23] $abc$8788$new_n2375 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[15] memory_to_writeBack_MEMORY_READ_DATA[7] $abc$8788$new_n2376 +000 1 +010 1 +100 1 +101 1 +.names _zz_5 $abc$8788$new_n2379 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[8] lastStageRegFileWrite_payload_data[8] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2355 _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2375 _zz_lastStageRegFileWrite_payload_address[14] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2378 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[8] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2379 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2380 +10 1 +.names _zz_5 $abc$8788$new_n2382 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[9] lastStageRegFileWrite_payload_data[9] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2386 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[11] lastStageRegFileWrite_payload_data[11] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[11] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2386 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2388 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[12] lastStageRegFileWrite_payload_data[12] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[28] memory_to_writeBack_MEMORY_READ_DATA[12] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2388 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2390 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[13] lastStageRegFileWrite_payload_data[13] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[29] memory_to_writeBack_MEMORY_READ_DATA[13] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2390 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2392 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[14] lastStageRegFileWrite_payload_data[14] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[30] memory_to_writeBack_MEMORY_READ_DATA[14] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2392 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2394 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[15] lastStageRegFileWrite_payload_data[15] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2394 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[31] memory_to_writeBack_MEMORY_READ_DATA[15] $abc$8788$new_n2395 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2397 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[16] lastStageRegFileWrite_payload_data[16] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2397 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2378 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[14] $abc$8788$new_n2398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2400 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[17] lastStageRegFileWrite_payload_data[17] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2400 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2402 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[18] lastStageRegFileWrite_payload_data[18] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2402 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2404 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[19] lastStageRegFileWrite_payload_data[19] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2404 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2406 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[20] lastStageRegFileWrite_payload_data[20] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2406 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2408 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[21] lastStageRegFileWrite_payload_data[21] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2408 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2410 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[22] lastStageRegFileWrite_payload_data[22] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2410 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2412 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[23] lastStageRegFileWrite_payload_data[23] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2412 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2414 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[24] lastStageRegFileWrite_payload_data[24] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2414 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2416 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[25] lastStageRegFileWrite_payload_data[25] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2416 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2418 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[26] lastStageRegFileWrite_payload_data[26] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2418 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2420 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[27] lastStageRegFileWrite_payload_data[27] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2420 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2422 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[28] lastStageRegFileWrite_payload_data[28] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2422 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2424 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[29] lastStageRegFileWrite_payload_data[29] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2424 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2426 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[30] lastStageRegFileWrite_payload_data[30] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[30] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2426 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2428 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[31] lastStageRegFileWrite_payload_data[31] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[31] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2428 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_5 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_5 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_5 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_5 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_5 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_5 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[1] +001 1 +010 1 +100 1 +111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 $abc$8788$new_n2436 +10 1 +.names IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[2] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 IBusSimplePlugin_pending_next[0] +00 1 +11 1 +.names $abc$8788$new_n1283 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] execute_to_memory_INSTRUCTION[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] execute_to_memory_INSTRUCTION[9] $abc$8788$new_n2439 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2439 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] execute_to_memory_INSTRUCTION[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 +1100 1 +1111 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 +10000 1 +10011 1 +11100 1 +11111 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 +00010 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 +1100 1 +1101 1 +1110 1 +.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] +.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] +.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] +.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] +.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] +.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] +.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] +.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] +.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] +.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] +.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] +.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset +.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffs C=clk D=$false Q=_zz_5 S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.names $false BranchPlugin_jumpInterface_payload[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false CsrPlugin_mepc[0] +1 1 +.names $false CsrPlugin_mepc[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] +1 1 +.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] +1 1 +.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] +1 1 +.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] +1 1 +.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] +1 1 +.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] +1 1 +.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] +1 1 +.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] +1 1 +.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] +1 1 +.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] +1 1 +.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] +1 1 +.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] +1 1 +.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] +1 1 +.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] +1 1 +.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] +1 1 +.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] +1 1 +.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] +1 1 +.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] +1 1 +.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] +1 1 +.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] +1 1 +.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] +1 1 +.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] +1 1 +.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] +1 1 +.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] +1 1 +.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] +1 1 +.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] +1 1 +.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] +1 1 +.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] +1 1 +.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] +1 1 +.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] +1 1 +.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] +1 1 +.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] +1 1 +.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] +1 1 +.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] +1 1 +.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] +1 1 +.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] +1 1 +.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] +1 1 +.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] +1 1 +.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] +1 1 +.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] +1 1 +.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] +1 1 +.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] +1 1 +.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] +1 1 +.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] +1 1 +.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] +1 1 +.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] +1 1 +.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] +1 1 +.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] +1 1 +.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] +1 1 +.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] +1 1 +.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] +1 1 +.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] +1 1 +.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] +1 1 +.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] +1 1 +.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] +1 1 +.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[0] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[1] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] +1 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[1] +1 1 +.names $false decode_to_execute_PC[0] +1 1 +.names $false decode_to_execute_PC[1] +1 1 +.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] +1 1 +.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] +1 1 +.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] +1 1 +.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] +1 1 +.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] +1 1 +.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] +1 1 +.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] +1 1 +.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] +1 1 +.names $false iBus_cmd_payload_pc[0] +1 1 +.names $false iBus_cmd_payload_pc[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif new file mode 100644 index 00000000000..2cdcc440f0a --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_full.blif @@ -0,0 +1,34792 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs dBus_cmd_ready dBus_rsp_valid dBus_rsp_payload_last dBus_rsp_payload_data[0] dBus_rsp_payload_data[1] dBus_rsp_payload_data[2] dBus_rsp_payload_data[3] dBus_rsp_payload_data[4] dBus_rsp_payload_data[5] dBus_rsp_payload_data[6] dBus_rsp_payload_data[7] dBus_rsp_payload_data[8] dBus_rsp_payload_data[9] dBus_rsp_payload_data[10] dBus_rsp_payload_data[11] dBus_rsp_payload_data[12] dBus_rsp_payload_data[13] dBus_rsp_payload_data[14] dBus_rsp_payload_data[15] dBus_rsp_payload_data[16] dBus_rsp_payload_data[17] dBus_rsp_payload_data[18] dBus_rsp_payload_data[19] dBus_rsp_payload_data[20] dBus_rsp_payload_data[21] dBus_rsp_payload_data[22] dBus_rsp_payload_data[23] dBus_rsp_payload_data[24] dBus_rsp_payload_data[25] dBus_rsp_payload_data[26] dBus_rsp_payload_data[27] dBus_rsp_payload_data[28] dBus_rsp_payload_data[29] dBus_rsp_payload_data[30] dBus_rsp_payload_data[31] dBus_rsp_payload_error timerInterrupt externalInterrupt softwareInterrupt debug_bus_cmd_valid debug_bus_cmd_payload_wr debug_bus_cmd_payload_address[0] debug_bus_cmd_payload_address[1] debug_bus_cmd_payload_address[2] debug_bus_cmd_payload_address[3] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_data[0] debug_bus_cmd_payload_data[1] debug_bus_cmd_payload_data[2] debug_bus_cmd_payload_data[3] debug_bus_cmd_payload_data[4] debug_bus_cmd_payload_data[5] debug_bus_cmd_payload_data[6] debug_bus_cmd_payload_data[7] debug_bus_cmd_payload_data[8] debug_bus_cmd_payload_data[9] debug_bus_cmd_payload_data[10] debug_bus_cmd_payload_data[11] debug_bus_cmd_payload_data[12] debug_bus_cmd_payload_data[13] debug_bus_cmd_payload_data[14] debug_bus_cmd_payload_data[15] debug_bus_cmd_payload_data[16] debug_bus_cmd_payload_data[17] debug_bus_cmd_payload_data[18] debug_bus_cmd_payload_data[19] debug_bus_cmd_payload_data[20] debug_bus_cmd_payload_data[21] debug_bus_cmd_payload_data[22] debug_bus_cmd_payload_data[23] debug_bus_cmd_payload_data[24] debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[26] debug_bus_cmd_payload_data[27] debug_bus_cmd_payload_data[28] debug_bus_cmd_payload_data[29] debug_bus_cmd_payload_data[30] debug_bus_cmd_payload_data[31] iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_data[0] iBus_rsp_payload_data[1] iBus_rsp_payload_data[2] iBus_rsp_payload_data[3] iBus_rsp_payload_data[4] iBus_rsp_payload_data[5] iBus_rsp_payload_data[6] iBus_rsp_payload_data[7] iBus_rsp_payload_data[8] iBus_rsp_payload_data[9] iBus_rsp_payload_data[10] iBus_rsp_payload_data[11] iBus_rsp_payload_data[12] iBus_rsp_payload_data[13] iBus_rsp_payload_data[14] iBus_rsp_payload_data[15] iBus_rsp_payload_data[16] iBus_rsp_payload_data[17] iBus_rsp_payload_data[18] iBus_rsp_payload_data[19] iBus_rsp_payload_data[20] iBus_rsp_payload_data[21] iBus_rsp_payload_data[22] iBus_rsp_payload_data[23] iBus_rsp_payload_data[24] iBus_rsp_payload_data[25] iBus_rsp_payload_data[26] iBus_rsp_payload_data[27] iBus_rsp_payload_data[28] iBus_rsp_payload_data[29] iBus_rsp_payload_data[30] iBus_rsp_payload_data[31] iBus_rsp_payload_error clk reset debugReset +.outputs dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[3] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_last debug_bus_cmd_ready debug_bus_rsp_data[0] debug_bus_rsp_data[1] debug_bus_rsp_data[2] debug_bus_rsp_data[3] debug_bus_rsp_data[4] debug_bus_rsp_data[5] debug_bus_rsp_data[6] debug_bus_rsp_data[7] debug_bus_rsp_data[8] debug_bus_rsp_data[9] debug_bus_rsp_data[10] debug_bus_rsp_data[11] debug_bus_rsp_data[12] debug_bus_rsp_data[13] debug_bus_rsp_data[14] debug_bus_rsp_data[15] debug_bus_rsp_data[16] debug_bus_rsp_data[17] debug_bus_rsp_data[18] debug_bus_rsp_data[19] debug_bus_rsp_data[20] debug_bus_rsp_data[21] debug_bus_rsp_data[22] debug_bus_rsp_data[23] debug_bus_rsp_data[24] debug_bus_rsp_data[25] debug_bus_rsp_data[26] debug_bus_rsp_data[27] debug_bus_rsp_data[28] debug_bus_rsp_data[29] debug_bus_rsp_data[30] debug_bus_rsp_data[31] debug_resetOut iBus_cmd_valid iBus_cmd_payload_address[0] iBus_cmd_payload_address[1] iBus_cmd_payload_address[2] iBus_cmd_payload_address[3] iBus_cmd_payload_address[4] iBus_cmd_payload_address[5] iBus_cmd_payload_address[6] iBus_cmd_payload_address[7] iBus_cmd_payload_address[8] iBus_cmd_payload_address[9] iBus_cmd_payload_address[10] iBus_cmd_payload_address[11] iBus_cmd_payload_address[12] iBus_cmd_payload_address[13] iBus_cmd_payload_address[14] iBus_cmd_payload_address[15] iBus_cmd_payload_address[16] iBus_cmd_payload_address[17] iBus_cmd_payload_address[18] iBus_cmd_payload_address[19] iBus_cmd_payload_address[20] iBus_cmd_payload_address[21] iBus_cmd_payload_address[22] iBus_cmd_payload_address[23] iBus_cmd_payload_address[24] iBus_cmd_payload_address[25] iBus_cmd_payload_address[26] iBus_cmd_payload_address[27] iBus_cmd_payload_address[28] iBus_cmd_payload_address[29] iBus_cmd_payload_address[30] iBus_cmd_payload_address[31] iBus_cmd_payload_size[0] iBus_cmd_payload_size[1] iBus_cmd_payload_size[2] +.names $false +.names $true +1 +.names $undef +.names $abc$27210$new_n4092 $abc$27210$new_n3940 dBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21747 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n3941 $abc$27210$new_n3940 +10 1 +.names $abc$27210$new_n4089 $abc$27210$new_n3942 $abc$27210$new_n4084 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$new_n3941 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n3943 $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$new_n3942 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n8219 $abc$27210$new_n3988 $abc$27210$new_n8017 $abc$27210$new_n8034 $abc$27210$new_n3943 +1100 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n3950 +01 1 +10 1 +.names $abc$27210$new_n7999 $abc$27210$new_n3963 MmuPlugin_ports_1_cache_2_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_2_superPage $abc$27210$new_n3956 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n3964 MmuPlugin_ports_1_cache_2_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3963 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$new_n3964 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3971 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n3972 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3980 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n3983 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n3985 +00 1 +11 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n3987 +01 1 +10 1 +.names $abc$27210$new_n8203 $abc$27210$new_n8227 $abc$27210$new_n3988 +00 1 +.names $abc$27210$new_n8008 $abc$27210$new_n3997 MmuPlugin_ports_1_cache_3_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n3990 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n3995 MmuPlugin_ports_1_cache_3_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n3994 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n3995 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n3998 MmuPlugin_ports_1_cache_3_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n3997 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$new_n3998 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4000 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4005 +01 1 +10 1 +.names $abc$27210$new_n4015 $abc$27210$new_n4014 MmuPlugin_ports_1_cache_5_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4013 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4014 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n4015 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n4017 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4016 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4017 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4020 +00 1 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4023 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_5_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4027 +10 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n4033 +10 1 +.names $abc$27210$new_n4038 MmuPlugin_ports_1_cache_1_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4037 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4038 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4046 +01 1 +10 1 +.names MmuPlugin_ports_1_cache_1_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4048 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n8219 $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4049 +00000 1 +.names MmuPlugin_ports_1_cache_4_valid MmuPlugin_ports_1_cache_4_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4055 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4085 $abc$27210$new_n4084 +00 1 +.names $abc$27210$new_n4087 $abc$27210$new_n8034 $abc$27210$new_n4086 $abc$27210$new_n4085 +100 1 +.names $abc$27210$new_n8203 $abc$27210$new_n8017 $abc$27210$new_n4086 +00 1 +.names $abc$27210$new_n3988 $abc$27210$new_n8219 $abc$27210$new_n4087 +10 1 +.names $abc$27210$new_n4086 $abc$27210$new_n8034 $abc$27210$new_n8227 $abc$27210$new_n4088 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4087 $abc$27210$new_n4088 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$new_n4089 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n4091 MmuPlugin_satp_mode CsrPlugin_mstatus_MPP[1] CsrPlugin_mstatus_MPP[0] $abc$27210$new_n4090 +11100 1 +11101 1 +11110 1 +.names MmuPlugin_status_mprv DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4091 +11000 1 +.names $abc$27210$new_n4093 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4092 +00 1 +.names $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$new_n4093 +10 1 +.names $abc$27210$new_n4103 $abc$27210$new_n4095 $abc$27210$new_n4094 +11 1 +.names $abc$27210$new_n4096 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4095 +10 1 +.names MmuPlugin_dBusAccess_rsp_payload_error $abc$27210$new_n4102 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$new_n4096 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4098 $abc$27210$new_n4102 dBus_cmd_payload_uncached dataCache_1.stageB_mmuRsp_isPaging MmuPlugin_dBusAccess_rsp_payload_error +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$27210$new_n4099 dBus_rsp_payload_error dBus_cmd_payload_uncached dBus_rsp_valid dBus_cmd_payload_wr $abc$27210$new_n4098 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4100 dataCache_1.stageB_unaligned dataCache_1.stageB_tagsReadRsp_0_error dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4099 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names memory_to_writeBack_IS_DBUS_SHARING $abc$27210$new_n4101 $abc$27210$new_n4100 +00 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsValid $abc$27210$new_n4101 +11 1 +.names $abc$27210$new_n4100 dBus_cmd_payload_wr dataCache_1.stageB_mmuRsp_exception dataCache_1.stageB_mmuRsp_allowWrite dataCache_1.stageB_mmuRsp_allowRead $abc$27210$new_n4102 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dBus_cmd_ready dBus_rsp_valid dataCache_1.stageB_waysHit $abc$27210$new_n4103 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 dBus_cmd_payload_size[2] +0000 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4106 dBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21749 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$new_n4107 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$new_n4106 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n4108 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$new_n4109 $abc$27210$new_n4107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$new_n4108 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$new_n4109 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4111 dBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21751 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n4112 $abc$27210$new_n4090 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$new_n4111 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n4113 $abc$27210$new_n3943 $abc$27210$new_n4084 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$new_n4114 $abc$27210$new_n4112 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$new_n4113 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$new_n4114 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4116 dBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21753 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4117 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n4116 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4120 $abc$27210$new_n4118 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$new_n4117 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$new_n4119 $abc$27210$new_n4118 +1000 1 +1010 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$new_n4119 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$new_n4120 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4122 dBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4123 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4122 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4126 $abc$27210$new_n4124 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$new_n4123 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$new_n4125 $abc$27210$new_n4124 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$new_n4125 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$new_n4126 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4128 dBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21757 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4129 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n4128 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4132 $abc$27210$new_n4130 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$new_n4129 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$new_n4131 $abc$27210$new_n4130 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$new_n4131 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$new_n4132 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4134 dBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4135 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n4134 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4138 $abc$27210$new_n4136 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$new_n4135 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$new_n4137 $abc$27210$new_n4136 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$new_n4137 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$new_n4138 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4140 dBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4141 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4140 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4144 $abc$27210$new_n4142 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$new_n4141 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$new_n4143 $abc$27210$new_n4142 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$new_n4143 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$new_n4144 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4146 dBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4147 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4146 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4150 $abc$27210$new_n4148 $abc$27210$new_n4085 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$new_n4147 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$new_n4149 $abc$27210$new_n4148 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$new_n4149 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$new_n4150 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4152 dBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4157 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n4152 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4090 $abc$27210$new_n4156 $abc$27210$new_n4154 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n4153 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n4155 $abc$27210$new_n4154 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n4155 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_ports_1_cache_3_superPage $abc$27210$new_n4156 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4160 $abc$27210$new_n4158 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$new_n4157 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$new_n4159 $abc$27210$new_n4158 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[9] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$new_n4159 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[9] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$new_n4160 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4162 dBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n4162 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4166 $abc$27210$new_n4164 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$new_n4163 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[8] $abc$27210$new_n4165 $abc$27210$new_n4164 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[8] MmuPlugin_ports_1_cache_5_physicalAddress_0[8] $abc$27210$new_n4165 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[8] MmuPlugin_ports_1_cache_3_physicalAddress_0[8] $abc$27210$new_n4166 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4168 dBus_cmd_payload_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$21769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4169 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4168 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4172 $abc$27210$new_n4170 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[7] $abc$27210$new_n4169 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[7] $abc$27210$new_n4171 $abc$27210$new_n4170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[7] MmuPlugin_ports_1_cache_5_physicalAddress_0[7] $abc$27210$new_n4171 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[7] MmuPlugin_ports_1_cache_3_physicalAddress_0[7] $abc$27210$new_n4172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4174 dBus_cmd_payload_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$21771 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4175 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n4174 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4178 $abc$27210$new_n4176 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[6] $abc$27210$new_n4175 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[6] $abc$27210$new_n4177 $abc$27210$new_n4176 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[6] MmuPlugin_ports_1_cache_5_physicalAddress_0[6] $abc$27210$new_n4177 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[6] MmuPlugin_ports_1_cache_3_physicalAddress_0[6] $abc$27210$new_n4178 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4180 dBus_cmd_payload_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$21773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4181 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n4180 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4184 $abc$27210$new_n4182 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[5] $abc$27210$new_n4181 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[5] $abc$27210$new_n4183 $abc$27210$new_n4182 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[5] MmuPlugin_ports_1_cache_5_physicalAddress_0[5] $abc$27210$new_n4183 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[5] MmuPlugin_ports_1_cache_3_physicalAddress_0[5] $abc$27210$new_n4184 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4186 dBus_cmd_payload_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4187 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n4186 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4190 $abc$27210$new_n4188 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[4] $abc$27210$new_n4187 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[4] $abc$27210$new_n4189 $abc$27210$new_n4188 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[4] MmuPlugin_ports_1_cache_5_physicalAddress_0[4] $abc$27210$new_n4189 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[4] MmuPlugin_ports_1_cache_3_physicalAddress_0[4] $abc$27210$new_n4190 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4192 dBus_cmd_payload_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4193 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4192 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4196 $abc$27210$new_n4194 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[3] $abc$27210$new_n4193 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[3] $abc$27210$new_n4195 $abc$27210$new_n4194 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[3] MmuPlugin_ports_1_cache_5_physicalAddress_0[3] $abc$27210$new_n4195 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[3] MmuPlugin_ports_1_cache_3_physicalAddress_0[3] $abc$27210$new_n4196 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4198 dBus_cmd_payload_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4199 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n4198 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4202 $abc$27210$new_n4200 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[2] $abc$27210$new_n4199 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[2] $abc$27210$new_n4201 $abc$27210$new_n4200 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[2] MmuPlugin_ports_1_cache_5_physicalAddress_0[2] $abc$27210$new_n4201 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[2] MmuPlugin_ports_1_cache_3_physicalAddress_0[2] $abc$27210$new_n4202 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4204 dBus_cmd_payload_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4205 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$new_n4204 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4208 $abc$27210$new_n4206 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[1] $abc$27210$new_n4205 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[1] $abc$27210$new_n4207 $abc$27210$new_n4206 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[1] MmuPlugin_ports_1_cache_5_physicalAddress_0[1] $abc$27210$new_n4207 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[1] MmuPlugin_ports_1_cache_3_physicalAddress_0[1] $abc$27210$new_n4208 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4210 dBus_cmd_payload_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4153 $abc$27210$new_n4211 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4210 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4214 $abc$27210$new_n4212 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_physicalAddress_0[0] $abc$27210$new_n4211 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_physicalAddress_0[0] $abc$27210$new_n4213 $abc$27210$new_n4212 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_physicalAddress_0[0] MmuPlugin_ports_1_cache_5_physicalAddress_0[0] $abc$27210$new_n4213 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_physicalAddress_0[0] MmuPlugin_ports_1_cache_3_physicalAddress_0[0] $abc$27210$new_n4214 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] dBus_cmd_payload_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] dBus_cmd_payload_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] dBus_cmd_payload_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] dBus_cmd_payload_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21791 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] dBus_cmd_payload_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] dBus_cmd_payload_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21795 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] dBus_cmd_payload_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21797 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] dataCache_1.stageB_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21799 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] dataCache_1.stageB_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] dataCache_1.stageB_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] dataCache_1.stageB_mmuRsp_physicalAddress[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21805 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] dataCache_1.stageB_mmuRsp_physicalAddress[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21807 +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.stageB_flusher_counter[5] dataCache_1.stageB_flusher_start $abc$27210$new_n4228 dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4232 $abc$27210$auto$rtlil.cc:2693:MuxGate$21817 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[4] $abc$27210$new_n4229 $abc$27210$new_n4228 +11 1 +.names dataCache_1.stageB_flusher_counter[3] $abc$27210$new_n4230 $abc$27210$new_n4229 +11 1 +.names dataCache_1.stageB_flusher_counter[2] $abc$27210$new_n4231 $abc$27210$new_n4230 +11 1 +.names dataCache_1.stageB_flusher_counter[0] dataCache_1.stageB_flusher_counter[1] $abc$27210$new_n4231 +11 1 +.names execute_RS1[10] $abc$27210$new_n4233 $abc$27210$new_n4232 +11 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4234 $abc$27210$new_n4233 +11 1 +.names decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid $abc$27210$new_n4235 $abc$27210$new_n4234 +110 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[14] _zz__zz_execute_BranchPlugin_branch_src2_2[15] _zz__zz_execute_BranchPlugin_branch_src2_2[16] _zz__zz_execute_BranchPlugin_branch_src2_2[17] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n4235 +00000 1 +.names dataCache_1.stageB_flusher_counter[4] $abc$27210$new_n4237 $abc$27210$new_n4229 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$21819 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[9] $abc$27210$new_n4233 $abc$27210$new_n4237 +11 1 +.names $abc$27210$new_n4239 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_counter[3] dataCache_1.stageB_flusher_start $abc$27210$new_n4230 $abc$27210$auto$rtlil.cc:2693:MuxGate$21821 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +11101 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4229 execute_RS1[8] $abc$27210$new_n4233 $abc$27210$new_n4239 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names dataCache_1.stageB_flusher_counter[2] $abc$27210$new_n4241 $abc$27210$new_n4231 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$21823 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[7] $abc$27210$new_n4233 $abc$27210$new_n4241 +11 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_counter[1] $abc$27210$new_n4243 execute_RS1[6] $abc$27210$new_n4234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21825 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[0] dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4243 +10 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_counter[0] execute_RS1[5] $abc$27210$new_n4234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21827 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names lastStageIsValid $abc$27210$new_n4256 HazardSimplePlugin_writeBackWrites_payload_data[0] DebugPlugin_busReadDataReg[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21833 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n4253 MmuPlugin_dBusAccess_rsp_payload_data[0] DBusCachedPlugin_exceptionBus_payload_badAddr[0] HazardSimplePlugin_writeBackWrites_payload_data[0] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4248 MmuPlugin_dBusAccess_rsp_payload_data[16] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[0] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[24] $abc$27210$new_n4250 $abc$27210$new_n4251 $abc$27210$new_n4248 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[24] dataCache_1.stageB_dataMux[24] MmuPlugin_dBusAccess_rsp_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[0] dataCache_1.stageB_dataMux[0] $abc$27210$new_n4250 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[8] dataCache_1.stageB_dataMux[8] $abc$27210$new_n4251 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[16] dataCache_1.stageB_dataMux[16] MmuPlugin_dBusAccess_rsp_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4254 _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] _zz__zz_decode_RS2_2[0] $abc$27210$new_n4253 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n4254 +00 1 +.names memory_to_writeBack_IS_MUL lastStageIsValid $abc$27210$new_n4255 +11 1 +.names decode_to_execute_DO_EBREAK execute_arbitration_isValid $abc$27210$new_n4256 +11 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4258 $abc$27210$auto$rtlil.cc:2693:MuxGate$21835 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4317 $abc$27210$new_n4259 $abc$27210$new_n4265 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4258 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n4262 DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_arbitration_isValid decode_to_execute_DO_EBREAK dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4259 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_isStuck +01 1 +10 1 +11 1 +.names execute_to_memory_IS_DIV memory_arbitration_isValid memory_DivPlugin_div_done $abc$27210$new_n4261 +110 1 +.names $abc$27210$new_n4263 decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid dataCache_1.stageB_flusher_waitDone $abc$27210$new_n4262 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4264 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4263 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$27210$new_n4264 +11 1 +.names $abc$27210$new_n4266 $abc$27210$new_n4305 $abc$27210$new_n4291 $abc$27210$new_n4316 $abc$27210$new_n4313 $abc$27210$new_n4265 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n8213 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$new_n4266 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4270 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$new_n4272 +01 1 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$new_n4274 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$new_n4275 +10 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$new_n4279 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4280 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid execute_to_memory_BYPASSABLE_MEMORY_STAGE $abc$27210$new_n4292 $abc$27210$new_n4291 +1100 1 +.names $abc$27210$new_n4298 $abc$27210$new_n4300 $abc$27210$new_n4304 $abc$27210$new_n8023 $abc$27210$new_n4303 $abc$27210$new_n4292 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4299 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4298 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4299 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$27210$new_n4302 $abc$27210$new_n4301 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4300 +1100 1 +1111 1 +.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4301 +0000 1 +0011 1 +1100 1 +1111 1 +.names execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4302 +0000 1 +0011 1 +1100 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4303 +11 1 +.names _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4304 +10 1 +.names decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n4306 $abc$27210$new_n4305 +1100 1 +.names $abc$27210$new_n4298 $abc$27210$new_n4307 $abc$27210$new_n4304 $abc$27210$new_n4310 $abc$27210$new_n4303 $abc$27210$new_n4306 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4309 $abc$27210$new_n4308 _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4307 +1100 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4308 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4309 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n4312 $abc$27210$new_n4311 _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n4310 +1100 1 +1111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_4[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] _zz__zz_execute_BranchPlugin_branch_src2_4[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4311 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2_10 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] _zz__zz_execute_BranchPlugin_branch_src2_4[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4312 +0000 1 +0011 1 +1100 1 +1111 1 +.names when_MmuPlugin_l281_1 $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4315 $abc$27210$new_n4313 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4314 +00 1 +.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4315 +000 1 +.names CsrPlugin_interrupt_valid DebugPlugin_haltIt DebugPlugin_stepIt $abc$27210$new_n4316 +100 1 +.names $abc$27210$new_n4318 $abc$27210$new_n4319 IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4317 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n4318 +00 1 +01 1 +11 1 +.names _zz_memory_ENV_CTRL memory_arbitration_isValid _zz_execute_ENV_CTRL execute_arbitration_isValid $abc$27210$new_n4319 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names debug_bus_cmd_payload_address[2] $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] $abc$27210$new_n4320 +1100 1 +.names debug_bus_cmd_payload_wr debug_bus_cmd_valid debug_bus_cmd_payload_address[7] debug_bus_cmd_payload_address[6] debug_bus_cmd_payload_address[3] $abc$27210$new_n4321 +11000 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n4258 $abc$27210$new_n4320 $abc$27210$auto$rtlil.cc:2693:MuxGate$21837 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4324 $abc$27210$new_n4390 MmuPlugin_shared_state_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21839 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4325 $abc$27210$new_n4329 $abc$27210$new_n4315 $abc$27210$new_n4324 +100 1 +110 1 +111 1 +.names MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_state_1[2] $abc$27210$new_n4326 MmuPlugin_shared_state_1[1] $abc$27210$new_n4325 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4326 +110 1 +.names $abc$27210$new_n4328 execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid $abc$27210$new_n4318 $abc$27210$new_n4327 +10000 1 +.names CsrPlugin_exceptionPendings_3 CsrPlugin_exceptionPendings_2 CsrPlugin_exceptionPendings_1 $abc$27210$new_n4328 +000 1 +.names $abc$27210$new_n4090 $abc$27210$new_n8224 execute_to_memory_MEMORY_ENABLE memory_arbitration_isValid $abc$27210$new_n4329 +1111 1 +.names MmuPlugin_ports_1_cache_3_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n4005 $abc$27210$new_n4000 $abc$27210$new_n4333 +0000 1 +1100 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$new_n3950 $abc$27210$new_n4359 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n4362 +0000 1 +0011 1 +1100 1 +1111 1 +.names MmuPlugin_ports_1_cache_2_valid MmuPlugin_ports_1_cache_2_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n4363 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_4_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$new_n4368 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n3987 $abc$27210$new_n3980 $abc$27210$new_n3983 $abc$27210$new_n4369 +000 1 +.names $abc$27210$new_n4371 $abc$27210$new_n4377 MmuPlugin_ports_1_cache_0_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_0_superPage $abc$27210$new_n4370 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n4375 $abc$27210$new_n4372 MmuPlugin_ports_1_cache_0_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n4371 +1100 1 +1111 1 +.names $abc$27210$new_n4373 MmuPlugin_ports_1_cache_0_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4372 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$new_n4374 MmuPlugin_ports_1_cache_0_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n4373 +00000 1 +00010 1 +00011 1 +11000 1 +11010 1 +11011 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n4374 +10 1 +.names $abc$27210$new_n4376 MmuPlugin_ports_1_cache_0_virtualAddress_0[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$new_n4375 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$new_n4376 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n4378 $abc$27210$new_n4377 +00000 1 +00110 1 +11000 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$new_n4378 +10 1 +.names MmuPlugin_ports_1_cache_0_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n4387 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n4390 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_X $abc$27210$new_n4391 +10000 1 +.names $abc$27210$new_n4324 $abc$27210$new_n4393 MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21841 +001 1 +011 1 +100 1 +101 1 +.names MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[1] $abc$27210$new_n4391 $abc$27210$new_n4393 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4395 $abc$27210$new_n4442 $abc$27210$auto$rtlil.cc:2693:MuxGate$21945 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4421 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n4423 $abc$27210$new_n4395 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_6 $abc$27210$new_n4417 $abc$27210$new_n4419 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +11110 1 +.names $abc$27210$new_n4416 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4398 $abc$27210$new_n4397 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 $abc$27210$new_n4398 +00100 1 +00110 1 +00111 1 +11010 1 +.names $abc$27210$new_n4415 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n4400 $abc$27210$new_n4399 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4401 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4402 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4403 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4404 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4405 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 _zz_6 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4406 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n4407 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4409 $abc$27210$new_n4408 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4410 $abc$27210$new_n4409 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4411 $abc$27210$new_n4410 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4411 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4412 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$new_n4413 +1001 1 +1011 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4414 +0010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] _zz_6 $abc$27210$new_n4415 +000 1 +010 1 +100 1 +101 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4416 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4417 +01 1 +10 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4419 +011 1 +100 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4436 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[30] $abc$27210$new_n4421 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 $abc$27210$new_n4422 +00 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4424 $abc$27210$new_n4428 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4423 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n4425 $abc$27210$new_n4266 $abc$27210$new_n4424 +00 1 +.names _zz_10 $abc$27210$new_n4427 $abc$27210$new_n4414 $abc$27210$new_n4425 +000 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] _zz_10 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_PREDICTION_CONTEXT_line_history_2[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4427 +1100 1 +.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4428 +11 1 +.names $abc$27210$new_n4430 $abc$27210$new_n4100 dataCache_1.io_cpu_execute_refilling dataCache_1.loader_valid_regNext MmuPlugin_dBusAccess_rsp_payload_redo +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1110 1 +.names dataCache_1.stageB_mmuRsp_refilling dataCache_1.stageB_waysHit dataCache_1.stageB_dataColisions dBus_cmd_payload_wr dBus_cmd_payload_uncached $abc$27210$new_n4430 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4432 lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n4431 +100 1 +101 1 +110 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 $abc$27210$new_n4432 +00 1 +.names $abc$27210$new_n4316 CsrPlugin_pipelineLiberator_pcValids_2 $abc$27210$new_n4328 CsrPlugin_hadException $abc$27210$new_n4433 +1110 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4431 execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4434 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4424 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n4435 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[30] $abc$27210$new_n4437 CsrPlugin_mepc[30] $abc$27210$new_n4438 $abc$27210$new_n4436 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n4437 +1110 1 +.names _zz_writeBack_ENV_CTRL _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] lastStageIsValid $abc$27210$new_n4438 +1111 1 +.names IBusCachedPlugin_fetchPc_booted $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 $abc$27210$new_n4439 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4258 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n8213 $abc$27210$new_n4441 +10 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4443 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4442 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4444 $abc$27210$new_n4443 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4445 $abc$27210$new_n4444 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4446 $abc$27210$new_n4445 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n4447 $abc$27210$new_n4446 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n4448 $abc$27210$new_n4447 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n4449 $abc$27210$new_n4448 +11111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$new_n4450 $abc$27210$new_n4449 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$new_n4451 $abc$27210$new_n4450 +111 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$new_n4452 $abc$27210$new_n4451 +111 1 +.names IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$new_n4452 +111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] $abc$27210$new_n4454 $abc$27210$new_n4458 $abc$27210$auto$rtlil.cc:2693:MuxGate$21947 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4456 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 $abc$27210$new_n4423 $abc$27210$new_n4454 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_6 $abc$27210$new_n4397 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4455 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4457 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[29] $abc$27210$new_n4456 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[29] $abc$27210$new_n4437 CsrPlugin_mepc[29] $abc$27210$new_n4438 $abc$27210$new_n4457 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4459 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4458 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4444 $abc$27210$new_n4459 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] $abc$27210$new_n4461 $abc$27210$new_n4465 $abc$27210$auto$rtlil.cc:2693:MuxGate$21949 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4463 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[28] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[28] $abc$27210$new_n4461 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[28] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4464 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[28] $abc$27210$new_n4463 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[28] $abc$27210$new_n4438 $abc$27210$new_n4464 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4444 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n4465 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] $abc$27210$new_n4467 $abc$27210$new_n4471 $abc$27210$auto$rtlil.cc:2693:MuxGate$21951 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4469 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[27] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[27] $abc$27210$new_n4467 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[27] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4470 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[27] $abc$27210$new_n4469 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[27] $abc$27210$new_n4438 $abc$27210$new_n4470 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4472 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4471 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4445 $abc$27210$new_n4472 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] $abc$27210$new_n4474 $abc$27210$new_n4478 $abc$27210$auto$rtlil.cc:2693:MuxGate$21953 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4476 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[26] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[26] $abc$27210$new_n4474 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4417 $abc$27210$new_n4397 IBusCachedPlugin_predictionJumpInterface_payload[26] +00 1 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4477 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[26] $abc$27210$new_n4476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[26] $abc$27210$new_n4438 $abc$27210$new_n4477 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4479 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n4478 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4445 $abc$27210$new_n4479 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] $abc$27210$new_n4481 $abc$27210$new_n4485 $abc$27210$auto$rtlil.cc:2693:MuxGate$21955 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4483 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[25] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[25] $abc$27210$new_n4481 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[25] +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10010 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4484 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[25] $abc$27210$new_n4438 $abc$27210$new_n4484 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4486 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4485 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4445 $abc$27210$new_n4486 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] $abc$27210$new_n4488 $abc$27210$new_n4492 $abc$27210$auto$rtlil.cc:2693:MuxGate$21957 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4490 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[24] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[24] $abc$27210$new_n4488 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4416 $abc$27210$new_n4398 IBusCachedPlugin_predictionJumpInterface_payload[24] +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4491 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[24] $abc$27210$new_n4490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[24] $abc$27210$new_n4438 $abc$27210$new_n4491 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4445 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n4492 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] $abc$27210$new_n4494 $abc$27210$new_n4498 $abc$27210$auto$rtlil.cc:2693:MuxGate$21959 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$27210$new_n4496 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[23] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[23] $abc$27210$new_n4494 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[23] +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4497 $abc$27210$new_n4434 $abc$27210$new_n4437 BranchPlugin_branchExceptionPort_payload_badAddr[23] $abc$27210$new_n4496 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names CsrPlugin_mepc[23] $abc$27210$new_n4438 $abc$27210$new_n4497 +11 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4499 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n4498 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 $abc$27210$new_n4499 +011 1 +100 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[22] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[22] $abc$27210$new_n4437 CsrPlugin_mepc[22] $abc$27210$new_n4438 $abc$27210$new_n4504 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n4446 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$new_n4505 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4399 IBusCachedPlugin_predictionJumpInterface_payload[21] +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[21] $abc$27210$new_n4437 CsrPlugin_mepc[21] $abc$27210$new_n4438 $abc$27210$new_n4510 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4512 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$new_n4511 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n4447 $abc$27210$new_n4512 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[20] +00000 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[20] $abc$27210$new_n4437 CsrPlugin_mepc[20] $abc$27210$new_n4438 $abc$27210$new_n4517 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n4415 $abc$27210$new_n4400 IBusCachedPlugin_predictionJumpInterface_payload[19] +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[19] $abc$27210$new_n4437 CsrPlugin_mepc[19] $abc$27210$new_n4438 $abc$27210$new_n4524 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4401 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_predictionJumpInterface_payload[18] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[18] $abc$27210$new_n4437 CsrPlugin_mepc[18] $abc$27210$new_n4438 $abc$27210$new_n4531 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n4447 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$new_n4532 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4402 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_predictionJumpInterface_payload[17] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4437 CsrPlugin_mepc[17] $abc$27210$new_n4438 $abc$27210$new_n4537 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4539 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4538 +1000 1 +1001 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n4448 $abc$27210$new_n4539 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4403 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_predictionJumpInterface_payload[16] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4437 CsrPlugin_mepc[16] $abc$27210$new_n4438 $abc$27210$new_n4544 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n4404 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_predictionJumpInterface_payload[15] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[15] $abc$27210$new_n4437 CsrPlugin_mepc[15] $abc$27210$new_n4438 $abc$27210$new_n4551 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4405 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_predictionJumpInterface_payload[14] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[14] $abc$27210$new_n4437 CsrPlugin_mepc[14] $abc$27210$new_n4438 $abc$27210$new_n4558 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n4448 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n4559 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4406 $abc$27210$new_n4414 _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_predictionJumpInterface_payload[13] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[13] $abc$27210$new_n4437 CsrPlugin_mepc[13] $abc$27210$new_n4438 $abc$27210$new_n4564 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$new_n4566 $abc$27210$new_n4565 +1000 1 +1010 1 +1100 1 +1101 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n4449 $abc$27210$new_n4566 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n4407 $abc$27210$new_n4414 _zz_6 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_predictionJumpInterface_payload[12] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[12] $abc$27210$new_n4437 CsrPlugin_mepc[12] $abc$27210$new_n4438 $abc$27210$new_n4571 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4575 $abc$27210$new_n4578 IBusCachedPlugin_predictionJumpInterface_payload[11] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4576 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[11] $abc$27210$new_n4575 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[11] $abc$27210$new_n4437 CsrPlugin_mepc[11] $abc$27210$new_n4438 $abc$27210$new_n4576 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4408 $abc$27210$new_n4414 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_predictionJumpInterface_payload[11] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$new_n4578 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4581 $abc$27210$new_n4584 IBusCachedPlugin_predictionJumpInterface_payload[10] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4582 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[10] $abc$27210$new_n4581 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[10] $abc$27210$new_n4437 CsrPlugin_mepc[10] $abc$27210$new_n4438 $abc$27210$new_n4582 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[10] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n4449 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$new_n4584 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4587 $abc$27210$new_n4590 IBusCachedPlugin_predictionJumpInterface_payload[9] $abc$27210$new_n4423 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4588 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[9] $abc$27210$new_n4587 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[9] $abc$27210$new_n4437 CsrPlugin_mepc[9] $abc$27210$new_n4438 $abc$27210$new_n4588 +10011 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4409 IBusCachedPlugin_predictionJumpInterface_payload[9] +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$new_n4590 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4593 $abc$27210$new_n4596 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[8] $abc$27210$new_n4595 DBusCachedPlugin_redoBranch_payload[8] $abc$27210$new_n4593 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[8] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names BranchPlugin_branchExceptionPort_payload_badAddr[8] $abc$27210$new_n4437 CsrPlugin_mepc[8] $abc$27210$new_n4438 $abc$27210$new_n4595 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$new_n4450 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$new_n4596 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4599 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4602 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4434 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[7] $abc$27210$new_n4601 DBusCachedPlugin_redoBranch_payload[7] $abc$27210$new_n4599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$new_n4410 IBusCachedPlugin_predictionJumpInterface_payload[7] +000 1 +011 1 +101 1 +110 1 +.names BranchPlugin_branchExceptionPort_payload_badAddr[7] $abc$27210$new_n4437 CsrPlugin_mepc[7] $abc$27210$new_n4438 $abc$27210$new_n4601 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 $abc$27210$new_n4602 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4605 $abc$27210$new_n4608 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4606 IBusCachedPlugin_predictionJumpInterface_payload[6] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[6] $abc$27210$new_n4605 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[6] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[6] $abc$27210$new_n4606 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[6] +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$new_n4451 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$new_n4608 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4611 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4614 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4612 IBusCachedPlugin_predictionJumpInterface_payload[5] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[5] $abc$27210$new_n4611 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[5] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[5] $abc$27210$new_n4612 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$new_n4411 IBusCachedPlugin_predictionJumpInterface_payload[5] +000 1 +011 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4614 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n4617 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4620 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4618 IBusCachedPlugin_predictionJumpInterface_payload[4] $abc$27210$new_n4434 DBusCachedPlugin_redoBranch_payload[4] $abc$27210$new_n4617 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[4] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[4] $abc$27210$new_n4618 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$new_n4412 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_predictionJumpInterface_payload[4] +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$new_n4452 $abc$27210$new_n4620 +01 1 +10 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4623 $abc$27210$new_n4626 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4624 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[3] $abc$27210$new_n4623 +000 1 +001 1 +011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[3] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[3] $abc$27210$new_n4624 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4413 $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] IBusCachedPlugin_predictionJumpInterface_payload[3] +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$new_n4626 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4629 $abc$27210$new_n4632 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4630 $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[2] $abc$27210$new_n4629 +000 1 +001 1 +011 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[2] $abc$27210$new_n4630 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4414 IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_predictionJumpInterface_payload[2] +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_fetchPc_inc IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4632 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[30] DBusCachedPlugin_redoBranch_payload[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22969 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4636 $abc$27210$new_n4093 $abc$27210$new_n4635 +00 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4637 CsrPlugin_exceptionPendings_3 $abc$27210$new_n4636 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4096 $abc$27210$new_n4637 +10 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[29] DBusCachedPlugin_redoBranch_payload[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22971 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[28] DBusCachedPlugin_redoBranch_payload[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22973 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[27] DBusCachedPlugin_redoBranch_payload[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[26] DBusCachedPlugin_redoBranch_payload[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22977 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[25] DBusCachedPlugin_redoBranch_payload[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22979 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[24] DBusCachedPlugin_redoBranch_payload[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22981 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[23] DBusCachedPlugin_redoBranch_payload[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[22] DBusCachedPlugin_redoBranch_payload[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[21] DBusCachedPlugin_redoBranch_payload[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[20] DBusCachedPlugin_redoBranch_payload[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[19] DBusCachedPlugin_redoBranch_payload[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[18] DBusCachedPlugin_redoBranch_payload[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[17] DBusCachedPlugin_redoBranch_payload[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[16] DBusCachedPlugin_redoBranch_payload[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[15] DBusCachedPlugin_redoBranch_payload[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[14] DBusCachedPlugin_redoBranch_payload[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[13] DBusCachedPlugin_redoBranch_payload[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23003 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[12] DBusCachedPlugin_redoBranch_payload[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] DBusCachedPlugin_redoBranch_payload[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] DBusCachedPlugin_redoBranch_payload[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] DBusCachedPlugin_redoBranch_payload[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] DBusCachedPlugin_redoBranch_payload[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] DBusCachedPlugin_redoBranch_payload[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] DBusCachedPlugin_redoBranch_payload[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] DBusCachedPlugin_redoBranch_payload[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] DBusCachedPlugin_redoBranch_payload[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23021 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] DBusCachedPlugin_redoBranch_payload[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23023 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4635 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] DBusCachedPlugin_redoBranch_payload[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23025 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] iBus_cmd_payload_address[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23027 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] iBus_cmd_payload_address[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23029 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] iBus_cmd_payload_address[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23031 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] iBus_cmd_payload_address[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23033 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] iBus_cmd_payload_address[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23035 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] iBus_cmd_payload_address[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23037 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] iBus_cmd_payload_address[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23039 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] iBus_cmd_payload_address[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23041 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] iBus_cmd_payload_address[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23043 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] iBus_cmd_payload_address[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23045 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] iBus_cmd_payload_address[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23047 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] iBus_cmd_payload_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23049 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] iBus_cmd_payload_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23051 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] iBus_cmd_payload_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23053 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] iBus_cmd_payload_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23055 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] iBus_cmd_payload_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23057 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] iBus_cmd_payload_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23059 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] iBus_cmd_payload_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23061 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] iBus_cmd_payload_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23063 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] iBus_cmd_payload_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23065 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] iBus_cmd_payload_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23067 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] iBus_cmd_payload_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23069 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] iBus_cmd_payload_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23071 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] iBus_cmd_payload_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23073 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] iBus_cmd_payload_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23075 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] iBus_cmd_payload_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23077 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.lineLoader_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23079 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.lineLoader_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23081 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.lineLoader_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23083 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] DBusCachedPlugin_exceptionBus_payload_badAddr[30] $abc$27210$new_n4744 $abc$27210$auto$rtlil.cc:2693:MuxGate$23085 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4697 $abc$27210$new_n8208 $abc$27210$new_n4696 +10 1 +.names $abc$27210$new_n4699 $abc$27210$new_n4698 $abc$27210$new_n4697 +10 1 +.names $abc$27210$new_n4637 MmuPlugin_dBusAccess_rsp_payload_redo $abc$27210$new_n4698 +10 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 $abc$27210$new_n4699 +00 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_error IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_iBusRsp_readyForError $abc$27210$new_n8213 $abc$27210$new_n4700 +1111 1 +.names execute_to_memory_BRANCH_DO BranchPlugin_branchExceptionPort_payload_badAddr[1] memory_arbitration_isValid $abc$27210$new_n4701 +111 1 +.names $abc$27210$new_n4710 $abc$27210$new_n4706 $abc$27210$new_n4708 $abc$27210$new_n4715 $abc$27210$new_n4714 $abc$27210$new_n4705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4707 $abc$27210$new_n4706 +1111 1 +.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$new_n4707 +00000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4708 +110 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4709 +00 1 +.names $abc$27210$new_n4711 $abc$27210$new_n4713 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4710 +1110 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4711 +000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4712 +110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4713 +000 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4714 +00 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4715 +10 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4721 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4722 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n4723 +1000 1 +1010 1 +1011 1 +.names $abc$27210$new_n4726 $abc$27210$new_n4729 $abc$27210$new_n4728 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4725 +1110 1 +.names $abc$27210$new_n4727 _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4726 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4727 +10 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4728 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4729 +0000 1 +.names $abc$27210$new_n4709 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n4732 $abc$27210$new_n4733 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4731 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4732 +1000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4733 +1000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n4735 +00000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n4736 +0000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4740 +1110 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4744 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n4746 $abc$27210$auto$rtlil.cc:2693:MuxGate$23087 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4746 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4752 $abc$27210$new_n4698 $abc$27210$new_n4751 +10 1 +.names $abc$27210$new_n4700 $abc$27210$new_n4701 $abc$27210$new_n4752 +10 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4272 $abc$27210$new_n4270 $abc$27210$new_n4761 +10000 1 +11100 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$new_n4763 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$new_n4764 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n4771 $abc$27210$auto$rtlil.cc:2693:MuxGate$23093 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4771 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] $abc$27210$new_n4773 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23095 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4774 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n4773 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[25] BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$new_n4701 $abc$27210$new_n4774 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n4776 $abc$27210$auto$rtlil.cc:2693:MuxGate$23097 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n4776 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n4778 $abc$27210$auto$rtlil.cc:2693:MuxGate$23099 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n4778 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n4783 $abc$27210$auto$rtlil.cc:2693:MuxGate$23103 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n4783 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n4791 $abc$27210$auto$rtlil.cc:2693:MuxGate$23109 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$new_n4791 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] $abc$27210$new_n4793 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23111 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4794 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$new_n4793 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[17] BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$new_n4701 $abc$27210$new_n4794 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] $abc$27210$new_n4796 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23113 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4797 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n4796 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[16] BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$new_n4701 $abc$27210$new_n4797 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n4799 $abc$27210$auto$rtlil.cc:2693:MuxGate$23115 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$new_n4799 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n4801 $abc$27210$auto$rtlil.cc:2693:MuxGate$23117 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4801 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n4803 $abc$27210$auto$rtlil.cc:2693:MuxGate$23119 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4803 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n4812 $abc$27210$auto$rtlil.cc:2693:MuxGate$23125 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$new_n4812 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n4817 $abc$27210$auto$rtlil.cc:2693:MuxGate$23129 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$new_n4817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n4819 $abc$27210$auto$rtlil.cc:2693:MuxGate$23131 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$new_n4819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n4821 $abc$27210$auto$rtlil.cc:2693:MuxGate$23133 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n4823 $abc$27210$auto$rtlil.cc:2693:MuxGate$23135 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n4828 $abc$27210$auto$rtlil.cc:2693:MuxGate$23139 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n4828 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] $abc$27210$new_n4830 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n4697 $abc$27210$auto$rtlil.cc:2693:MuxGate$23141 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4831 $abc$27210$new_n4751 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$new_n4830 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[2] BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n4701 $abc$27210$new_n4831 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] $abc$27210$new_n4833 $abc$27210$auto$rtlil.cc:2693:MuxGate$23143 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4698 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4752 IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n4701 $abc$27210$new_n4833 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] $abc$27210$new_n4835 $abc$27210$auto$rtlil.cc:2693:MuxGate$23145 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4698 DBusCachedPlugin_exceptionBus_payload_badAddr[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$new_n4699 $abc$27210$new_n4835 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] CsrPlugin_mtval[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23207 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] CsrPlugin_mtval[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23209 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] CsrPlugin_mtval[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23211 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] CsrPlugin_mtval[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23213 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] CsrPlugin_mtval[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23215 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] CsrPlugin_mtval[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23217 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] CsrPlugin_mtval[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23219 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] CsrPlugin_mtval[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23221 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] CsrPlugin_mtval[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23223 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] CsrPlugin_mtval[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23225 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] CsrPlugin_mtval[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23227 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] CsrPlugin_mtval[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23229 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] CsrPlugin_mtval[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23231 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] CsrPlugin_mtval[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23233 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] CsrPlugin_mtval[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23235 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] CsrPlugin_mtval[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23237 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] CsrPlugin_mtval[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23239 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] CsrPlugin_mtval[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23241 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] CsrPlugin_mtval[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23243 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] CsrPlugin_mtval[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23245 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] CsrPlugin_mtval[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23247 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] CsrPlugin_mtval[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23249 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] CsrPlugin_mtval[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23251 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] CsrPlugin_mtval[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23253 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] CsrPlugin_mtval[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23255 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] CsrPlugin_mtval[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23257 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] CsrPlugin_mtval[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23259 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] CsrPlugin_mtval[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23261 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] CsrPlugin_mtval[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23263 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] CsrPlugin_mtval[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23265 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] CsrPlugin_mtval[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23267 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4903 _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n4905 $abc$27210$new_n4868 memory_DivPlugin_div_result[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n4869 $abc$27210$new_n4902 $abc$27210$new_n4901 $abc$27210$new_n4900 $abc$27210$new_n4868 +1000 1 +.names $abc$27210$new_n4870 $abc$27210$new_n4899 $abc$27210$new_n4898 $abc$27210$new_n4897 $abc$27210$new_n4869 +1111 1 +.names $abc$27210$new_n4871 $abc$27210$new_n4896 $abc$27210$new_n4895 $abc$27210$new_n4894 $abc$27210$new_n4893 $abc$27210$new_n4870 +10000 1 +.names $abc$27210$new_n4872 $abc$27210$new_n4892 $abc$27210$new_n4891 $abc$27210$new_n4890 $abc$27210$new_n4871 +1111 1 +.names $abc$27210$new_n4873 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n4872 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4874 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n4873 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4875 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4874 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4876 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[14] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$new_n4875 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4877 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n4876 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4878 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[12] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$new_n4877 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4879 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4878 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4880 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[10] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n4879 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4881 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4880 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4882 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n4881 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4883 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4882 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4884 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$new_n4883 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4885 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n4884 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4886 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] _zz_memory_DivPlugin_div_stage_0_outNumerator[4] $abc$27210$new_n4885 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n4889 $abc$27210$new_n4888 $abc$27210$new_n4887 $abc$27210$new_n4886 +1111 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] _zz_memory_DivPlugin_div_stage_0_outNumerator[1] $abc$27210$new_n4887 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] _zz_memory_DivPlugin_div_stage_0_outNumerator[2] $abc$27210$new_n4888 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] _zz_memory_DivPlugin_div_stage_0_outNumerator[3] $abc$27210$new_n4889 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$new_n4890 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$new_n4891 +000 1 +010 1 +100 1 +101 1 +.names execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$new_n4892 +000 1 +010 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[21] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] $abc$27210$new_n4893 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[22] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$new_n4894 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_DivPlugin_div_result_5 execute_to_memory_INSTRUCTION[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[23] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4895 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names 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1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] $abc$27210$new_n4967 $abc$27210$new_n4966 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n4968 $abc$27210$new_n4967 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names 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_zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n4971 $abc$27210$new_n4970 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n4972 $abc$27210$new_n4971 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$new_n4973 $abc$27210$new_n4972 +00001 1 +01000 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$abc$27210$new_n4963 $abc$27210$new_n4984 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] $abc$27210$new_n4986 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23403 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$new_n4963 $abc$27210$new_n4986 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] $abc$27210$new_n4988 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23405 +00100 1 +00101 1 +00110 1 +00111 1 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_zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4964 $abc$27210$new_n4990 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] $abc$27210$new_n4992 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23409 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] $abc$27210$new_n4965 $abc$27210$new_n4992 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4994 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1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n4967 $abc$27210$new_n5000 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5002 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23419 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] $abc$27210$new_n4967 $abc$27210$new_n4959 $abc$27210$new_n5002 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] $abc$27210$new_n5004 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23421 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4968 $abc$27210$new_n5004 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] $abc$27210$new_n5006 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23423 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n4968 $abc$27210$new_n5006 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] $abc$27210$new_n5008 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23425 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n4969 $abc$27210$new_n5008 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5010 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23427 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] $abc$27210$new_n4969 $abc$27210$new_n4959 $abc$27210$new_n5010 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] $abc$27210$new_n5012 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23429 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4970 $abc$27210$new_n5012 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] $abc$27210$new_n5014 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23431 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n4970 $abc$27210$new_n5014 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] $abc$27210$new_n5016 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23433 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4971 $abc$27210$new_n5016 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] $abc$27210$new_n5018 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23435 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n4971 $abc$27210$new_n5018 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] $abc$27210$new_n5020 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23437 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4972 $abc$27210$new_n5020 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] $abc$27210$new_n5022 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23439 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n4972 $abc$27210$new_n5022 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] $abc$27210$new_n5024 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23441 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n4973 $abc$27210$new_n5024 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n5026 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23443 +001 1 +011 1 +100 1 +101 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] $abc$27210$new_n4973 $abc$27210$new_n4959 $abc$27210$new_n5026 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] $abc$27210$new_n5028 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23445 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n4974 $abc$27210$new_n5028 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] $abc$27210$new_n5030 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23447 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n4974 $abc$27210$new_n5030 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] $abc$27210$new_n5032 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23449 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$new_n4975 $abc$27210$new_n5032 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] $abc$27210$new_n5034 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23451 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$new_n5034 +0010 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1110 1 +.names $abc$27210$new_n4261 memory_DivPlugin_div_stage_0_remainderShifted _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23453 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[9] MmuPlugin_shared_dBusRspStaged_payload_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23457 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[8] MmuPlugin_shared_dBusRspStaged_payload_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23459 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[7] MmuPlugin_shared_dBusRspStaged_payload_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23461 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[6] MmuPlugin_shared_dBusRspStaged_payload_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23463 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[5] MmuPlugin_shared_dBusRspStaged_payload_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23465 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[4] MmuPlugin_shared_dBusRspStaged_payload_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23467 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[3] MmuPlugin_shared_dBusRspStaged_payload_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23469 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[2] MmuPlugin_shared_dBusRspStaged_payload_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23471 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[1] MmuPlugin_shared_dBusRspStaged_payload_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23473 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN1[0] MmuPlugin_shared_dBusRspStaged_payload_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23475 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[8] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23477 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[7] MmuPlugin_shared_dBusRspStaged_payload_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23479 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[6] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23481 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[5] MmuPlugin_shared_dBusRspStaged_payload_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23483 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[4] MmuPlugin_shared_dBusRspStaged_payload_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23485 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[3] MmuPlugin_shared_dBusRspStaged_payload_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23487 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[2] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23489 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[1] MmuPlugin_shared_dBusRspStaged_payload_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23491 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[0] MmuPlugin_shared_dBusRspStaged_payload_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23493 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_vpn_1[8] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23495 +01 1 +10 1 +11 1 +.names $abc$27210$new_n4315 $abc$27210$new_n4329 $abc$27210$new_n5056 +11 1 +.names MmuPlugin_shared_vpn_1[7] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23497 +10 1 +.names MmuPlugin_shared_vpn_1[6] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$23499 +10 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_shared_vpn_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23501 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_shared_vpn_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23503 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_shared_vpn_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23505 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_shared_vpn_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23507 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_shared_vpn_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23509 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_shared_vpn_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23511 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_shared_vpn_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23513 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_shared_vpn_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23515 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_shared_vpn_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23517 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_shared_vpn_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23519 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_shared_vpn_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23521 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_shared_vpn_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23523 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] MmuPlugin_shared_vpn_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23525 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] MmuPlugin_shared_vpn_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23527 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_shared_vpn_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23529 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23531 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5075 +1110 1 +.names when_MmuPlugin_l281_1 MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo $abc$27210$new_n4391 $abc$27210$new_n5076 +1100 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23533 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23535 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23537 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23539 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23541 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23543 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23545 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23547 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_5_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23549 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_5_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_5_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23553 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_5_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23555 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_5_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_5_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23559 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_5_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23561 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_5_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23563 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_5_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23567 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23569 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_5_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_5_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23573 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23575 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23577 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23579 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_5_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23581 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_5_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23583 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_5_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23585 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23587 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_5_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23589 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23591 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23593 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_5_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23595 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_5_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23597 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_5_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23599 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_5_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23601 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23603 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5113 +1100 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23605 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23607 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23609 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23611 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23613 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23615 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23617 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23619 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_4_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23621 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_4_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23623 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_4_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23625 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_4_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23627 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_4_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23629 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_4_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23631 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_4_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23633 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_4_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23635 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_4_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23637 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_4_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23639 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23641 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_4_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23643 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_4_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23645 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23647 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_4_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23649 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_4_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23651 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_4_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23653 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_4_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23655 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23657 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23659 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_4_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23661 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_4_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23663 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_4_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23665 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_4_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23667 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_4_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23669 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_4_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23671 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23673 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23675 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5150 +1110 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23677 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23679 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23681 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23685 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_3_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_3_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_3_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23697 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_3_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23699 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_3_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_3_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23703 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_3_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_3_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_3_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_3_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_3_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23715 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_3_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23717 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_3_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23721 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_3_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_3_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_3_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_3_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23733 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23735 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_3_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23739 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_3_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_3_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_3_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23747 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5187 +1100 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23749 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23751 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23753 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23757 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_2_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_2_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_2_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_2_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23771 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_2_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_2_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_2_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_2_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_2_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_2_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_2_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_2_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23791 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_2_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_2_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23795 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_2_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23797 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_2_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23799 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_2_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23805 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23807 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23809 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23811 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23813 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_2_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_2_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23817 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23819 +001 1 +011 1 +110 1 +111 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5224 +1100 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23823 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23825 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23827 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23829 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23831 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23833 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23835 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_1_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23837 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_1_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23839 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_1_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23841 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_1_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23843 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_1_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23845 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_1_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23847 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_1_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23849 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_1_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23851 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_1_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23853 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_1_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23855 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_1_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23857 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23859 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23861 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23863 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_1_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23865 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23867 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_1_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23869 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_1_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23871 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_1_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23873 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_1_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23875 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23877 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_1_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23879 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_1_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23881 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23883 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23885 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_1_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23887 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_1_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23889 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[28] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[0] MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[2] $abc$27210$new_n5261 +1000 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[27] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23893 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[26] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[25] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23897 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[24] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23899 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[23] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23901 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[22] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23903 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[21] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23905 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[20] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[18] MmuPlugin_ports_1_cache_0_physicalAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23909 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_ports_1_cache_0_physicalAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23911 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[16] MmuPlugin_ports_1_cache_0_physicalAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_ports_1_cache_0_physicalAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_ports_1_cache_0_physicalAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_ports_1_cache_0_physicalAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[12] MmuPlugin_ports_1_cache_0_physicalAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_ports_1_cache_0_physicalAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_ports_1_cache_0_physicalAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[8] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[7] MmuPlugin_ports_1_cache_0_virtualAddress_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[6] MmuPlugin_ports_1_cache_0_virtualAddress_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[5] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[4] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[2] MmuPlugin_ports_1_cache_0_virtualAddress_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[1] MmuPlugin_ports_1_cache_0_virtualAddress_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[0] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[8] MmuPlugin_ports_1_cache_0_virtualAddress_0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23945 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[7] MmuPlugin_ports_1_cache_0_virtualAddress_0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23947 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[6] MmuPlugin_ports_1_cache_0_virtualAddress_0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23949 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[5] MmuPlugin_ports_1_cache_0_virtualAddress_0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23951 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[4] MmuPlugin_ports_1_cache_0_virtualAddress_0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23953 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[3] MmuPlugin_ports_1_cache_0_virtualAddress_0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23955 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[2] MmuPlugin_ports_1_cache_0_virtualAddress_0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23957 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[1] MmuPlugin_ports_1_cache_0_virtualAddress_0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23959 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[0] MmuPlugin_ports_1_cache_0_virtualAddress_0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23961 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5299 MmuPlugin_satp_ppn[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23963 +001 1 +011 1 +100 1 +101 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_384 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5298 +1111 1 +.names $abc$27210$new_n5302 switch_Misc_l241_1 $abc$27210$new_n5300 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5299 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5301 execute_CsrPlugin_csr_833 CsrPlugin_mepc[20] $abc$27210$new_n5300 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[20] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[20] $abc$27210$new_n5301 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[20] _zz_execute_BranchPlugin_branch_src2_8 $abc$27210$new_n5302 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5304 MmuPlugin_satp_ppn[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23965 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5307 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5305 $abc$27210$new_n5304 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5306 execute_CsrPlugin_csr_835 CsrPlugin_mtval[19] MmuPlugin_satp_ppn[19] execute_CsrPlugin_csr_384 $abc$27210$new_n5305 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_mxr CsrPlugin_mepc[19] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5306 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[19] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5307 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5309 MmuPlugin_satp_ppn[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23967 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5312 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5310 $abc$27210$new_n5309 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5311 execute_CsrPlugin_csr_835 CsrPlugin_mtval[18] MmuPlugin_satp_ppn[18] execute_CsrPlugin_csr_384 $abc$27210$new_n5310 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_sum CsrPlugin_mepc[18] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5311 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[18] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5312 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5314 MmuPlugin_satp_ppn[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23969 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5317 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5315 $abc$27210$new_n5314 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5316 execute_CsrPlugin_csr_835 CsrPlugin_mtval[17] MmuPlugin_satp_ppn[17] execute_CsrPlugin_csr_384 $abc$27210$new_n5315 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names MmuPlugin_status_mprv CsrPlugin_mepc[17] execute_CsrPlugin_csr_833 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n5316 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10100 1 +11000 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[17] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5317 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5319 MmuPlugin_satp_ppn[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23971 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5322 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5320 $abc$27210$new_n5319 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5321 execute_CsrPlugin_csr_833 CsrPlugin_mepc[16] $abc$27210$new_n5320 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[16] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[16] $abc$27210$new_n5321 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[16] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5322 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5324 MmuPlugin_satp_ppn[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23973 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5327 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5325 $abc$27210$new_n5324 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5326 execute_CsrPlugin_csr_833 CsrPlugin_mepc[15] $abc$27210$new_n5325 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[15] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[15] $abc$27210$new_n5326 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[15] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n5327 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5329 MmuPlugin_satp_ppn[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5332 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5330 $abc$27210$new_n5329 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5331 execute_CsrPlugin_csr_833 CsrPlugin_mepc[14] $abc$27210$new_n5330 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[14] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[14] $abc$27210$new_n5331 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$new_n5332 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5334 MmuPlugin_satp_ppn[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23977 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5337 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5335 $abc$27210$new_n5334 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5336 execute_CsrPlugin_csr_833 CsrPlugin_mepc[13] $abc$27210$new_n5335 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[13] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[13] $abc$27210$new_n5336 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[13] switch_Misc_l241_1 $abc$27210$new_n5337 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5339 MmuPlugin_satp_ppn[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23979 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5342 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5340 $abc$27210$new_n5339 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5341 CsrPlugin_mepc[12] execute_CsrPlugin_csr_833 CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$27210$new_n5340 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[12] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[12] $abc$27210$new_n5341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[12] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5342 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5344 MmuPlugin_satp_ppn[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23981 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5348 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5345 $abc$27210$new_n5344 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5346 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[11] execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPP[0] $abc$27210$new_n5345 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5347 execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$27210$new_n5346 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[11] CsrPlugin_mepc[11] execute_CsrPlugin_csr_833 $abc$27210$new_n5347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_RS1[11] $abc$27210$new_n5349 $abc$27210$new_n5348 +11 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] $abc$27210$new_n5349 +00 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5351 MmuPlugin_satp_ppn[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23983 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5352 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5353 $abc$27210$new_n5351 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[10] $abc$27210$new_n5349 $abc$27210$new_n5352 +11 1 +.names $abc$27210$new_n5354 execute_CsrPlugin_csr_833 CsrPlugin_mepc[10] $abc$27210$new_n5353 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[10] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[10] $abc$27210$new_n5354 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5356 MmuPlugin_satp_ppn[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23985 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5357 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5358 $abc$27210$new_n5356 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[9] $abc$27210$new_n5349 $abc$27210$new_n5357 +11 1 +.names $abc$27210$new_n5359 execute_CsrPlugin_csr_833 CsrPlugin_mepc[9] $abc$27210$new_n5358 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[9] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[9] $abc$27210$new_n5359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5361 MmuPlugin_satp_ppn[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23987 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5362 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5363 $abc$27210$new_n5361 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[8] $abc$27210$new_n5349 $abc$27210$new_n5362 +11 1 +.names $abc$27210$new_n5364 execute_CsrPlugin_csr_833 CsrPlugin_mepc[8] $abc$27210$new_n5363 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[8] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[8] $abc$27210$new_n5364 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5366 MmuPlugin_satp_ppn[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23989 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5370 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5367 $abc$27210$new_n5366 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5368 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[7] execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE $abc$27210$new_n5367 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5369 CsrPlugin_mip_MTIP execute_CsrPlugin_csr_836 execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MPIE $abc$27210$new_n5368 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[7] CsrPlugin_mepc[7] execute_CsrPlugin_csr_833 $abc$27210$new_n5369 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_RS1[7] $abc$27210$new_n5349 $abc$27210$new_n5370 +11 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5372 MmuPlugin_satp_ppn[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23991 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5373 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5374 $abc$27210$new_n5372 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[6] $abc$27210$new_n5349 $abc$27210$new_n5373 +11 1 +.names $abc$27210$new_n5375 execute_CsrPlugin_csr_833 CsrPlugin_mepc[6] $abc$27210$new_n5374 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[6] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[6] $abc$27210$new_n5375 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5377 MmuPlugin_satp_ppn[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23993 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5378 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5379 $abc$27210$new_n5377 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names execute_RS1[5] $abc$27210$new_n5349 $abc$27210$new_n5378 +11 1 +.names $abc$27210$new_n5380 execute_CsrPlugin_csr_833 CsrPlugin_mepc[5] $abc$27210$new_n5379 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[5] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[5] $abc$27210$new_n5380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5382 MmuPlugin_satp_ppn[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23995 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5385 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5383 $abc$27210$new_n5382 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5384 execute_CsrPlugin_csr_833 CsrPlugin_mepc[4] $abc$27210$new_n5383 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[4] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[4] $abc$27210$new_n5384 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[4] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$new_n5385 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5387 MmuPlugin_satp_ppn[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23997 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5392 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5388 $abc$27210$new_n5387 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5391 $abc$27210$new_n5389 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_772 $abc$27210$new_n5388 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n5390 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] execute_CsrPlugin_csr_836 CsrPlugin_mip_MSIP $abc$27210$new_n5389 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[3] CsrPlugin_mstatus_MIE execute_CsrPlugin_csr_768 $abc$27210$new_n5390 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[3] CsrPlugin_mepc[3] execute_CsrPlugin_csr_833 $abc$27210$new_n5391 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[3] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$new_n5392 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5394 MmuPlugin_satp_ppn[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$23999 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5397 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5395 $abc$27210$new_n5394 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$27210$new_n5396 execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[2] execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$27210$new_n5395 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[2] CsrPlugin_mepc[2] execute_CsrPlugin_csr_833 $abc$27210$new_n5396 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[2] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$new_n5397 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5399 MmuPlugin_satp_ppn[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24001 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5402 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5400 $abc$27210$new_n5399 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5401 execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[1] execute_CsrPlugin_csr_833 CsrPlugin_mepc[1] $abc$27210$new_n5400 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[1] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[1] $abc$27210$new_n5401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[1] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$new_n5402 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5404 MmuPlugin_satp_ppn[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24003 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5407 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5405 $abc$27210$new_n5404 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5406 execute_CsrPlugin_csr_835 CsrPlugin_mtval[0] execute_CsrPlugin_csr_833 CsrPlugin_mepc[0] $abc$27210$new_n5405 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[0] CsrPlugin_mcause_exceptionCode[0] execute_CsrPlugin_csr_834 $abc$27210$new_n5406 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[1] _zz_execute_SRC1_CTRL[0] execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n5407 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5409 MmuPlugin_satp_asid[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5412 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5410 $abc$27210$new_n5409 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5411 execute_CsrPlugin_csr_833 CsrPlugin_mepc[29] $abc$27210$new_n5410 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[29] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[7] $abc$27210$new_n5411 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$new_n5412 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5414 MmuPlugin_satp_asid[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5417 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5415 $abc$27210$new_n5414 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5416 execute_CsrPlugin_csr_833 CsrPlugin_mepc[28] $abc$27210$new_n5415 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[28] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[6] $abc$27210$new_n5416 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$new_n5417 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5419 MmuPlugin_satp_asid[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5422 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5420 $abc$27210$new_n5419 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5421 execute_CsrPlugin_csr_833 CsrPlugin_mepc[27] $abc$27210$new_n5420 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[27] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[5] $abc$27210$new_n5421 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[27] _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$new_n5422 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5424 MmuPlugin_satp_asid[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5427 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5425 $abc$27210$new_n5424 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5426 execute_CsrPlugin_csr_833 CsrPlugin_mepc[26] $abc$27210$new_n5425 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[26] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[4] $abc$27210$new_n5426 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[26] _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$new_n5427 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5429 MmuPlugin_satp_asid[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5432 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5430 $abc$27210$new_n5429 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5431 execute_CsrPlugin_csr_833 CsrPlugin_mepc[25] $abc$27210$new_n5430 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[25] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[3] $abc$27210$new_n5431 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[25] _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$new_n5432 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5434 MmuPlugin_satp_asid[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5437 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5435 $abc$27210$new_n5434 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5436 execute_CsrPlugin_csr_833 CsrPlugin_mepc[24] $abc$27210$new_n5435 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[24] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[2] $abc$27210$new_n5436 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[24] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$new_n5437 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5439 MmuPlugin_satp_asid[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5442 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5440 $abc$27210$new_n5439 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5441 execute_CsrPlugin_csr_833 CsrPlugin_mepc[23] $abc$27210$new_n5440 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[23] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[1] $abc$27210$new_n5441 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[23] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$new_n5442 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5444 MmuPlugin_satp_asid[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5447 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5445 $abc$27210$new_n5444 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5446 execute_CsrPlugin_csr_833 CsrPlugin_mepc[22] $abc$27210$new_n5445 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[22] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[0] $abc$27210$new_n5446 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[22] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$new_n5447 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24021 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24023 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24025 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24027 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24029 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24031 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24033 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24035 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24037 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24039 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24041 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24043 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24045 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24047 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24049 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24051 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24053 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24055 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24057 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24059 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24061 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24063 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24065 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24067 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24069 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24071 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24073 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24075 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24077 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[0] _zz_decode_PREDICTION_CONTEXT_line_history_2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24079 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24081 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24083 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24085 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24087 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24089 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24091 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_decode_PREDICTION_CONTEXT_hazard_3[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24093 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24095 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_decode_PREDICTION_CONTEXT_hazard_3[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24097 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_mcause_exceptionCode[0] CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24159 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[30] $abc$27210$new_n5489 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24161 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[30] $abc$27210$new_n5506 $abc$27210$new_n5490 $abc$27210$new_n5489 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n5491 execute_RS1[28] execute_RS1[29] $abc$27210$new_n5490 +100 1 +.names $abc$27210$new_n5492 execute_RS1[25] execute_RS1[26] execute_RS1[27] $abc$27210$new_n5491 +1000 1 +.names $abc$27210$new_n5493 execute_RS1[22] execute_RS1[23] execute_RS1[24] $abc$27210$new_n5492 +1000 1 +.names $abc$27210$new_n5494 execute_RS1[19] execute_RS1[20] execute_RS1[21] $abc$27210$new_n5493 +1000 1 +.names $abc$27210$new_n5495 execute_RS1[18] $abc$27210$new_n5494 +10 1 +.names $abc$27210$new_n5496 execute_RS1[17] $abc$27210$new_n5495 +10 1 +.names $abc$27210$new_n5497 execute_RS1[16] $abc$27210$new_n5496 +10 1 +.names $abc$27210$new_n5498 execute_RS1[15] $abc$27210$new_n5497 +10 1 +.names $abc$27210$new_n5499 execute_RS1[14] $abc$27210$new_n5498 +10 1 +.names $abc$27210$new_n5500 execute_RS1[13] $abc$27210$new_n5499 +10 1 +.names $abc$27210$new_n5501 execute_RS1[12] $abc$27210$new_n5500 +10 1 +.names $abc$27210$new_n5502 execute_RS1[11] $abc$27210$new_n5501 +10 1 +.names $abc$27210$new_n5503 execute_RS1[10] $abc$27210$new_n5502 +10 1 +.names $abc$27210$new_n5504 execute_RS1[7] execute_RS1[8] execute_RS1[9] $abc$27210$new_n5503 +1000 1 +.names $abc$27210$new_n5505 execute_RS1[4] execute_RS1[5] execute_RS1[6] $abc$27210$new_n5504 +1000 1 +.names $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] execute_RS1[2] execute_RS1[3] $abc$27210$new_n5505 +10000 1 +.names decode_to_execute_IS_DIV decode_to_execute_IS_RS1_SIGNED execute_RS1[31] $abc$27210$new_n5506 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[29] $abc$27210$new_n5508 _zz_memory_DivPlugin_div_stage_0_outNumerator[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24163 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[29] $abc$27210$new_n5491 $abc$27210$new_n5506 execute_RS1[28] $abc$27210$new_n5508 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[28] $abc$27210$new_n5510 _zz_memory_DivPlugin_div_stage_0_outNumerator[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24165 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[28] $abc$27210$new_n5506 $abc$27210$new_n5491 $abc$27210$new_n5510 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[27] $abc$27210$new_n5512 _zz_memory_DivPlugin_div_stage_0_outNumerator[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24167 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[27] $abc$27210$new_n5506 $abc$27210$new_n5492 execute_RS1[25] execute_RS1[26] $abc$27210$new_n5512 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[26] $abc$27210$new_n5514 _zz_memory_DivPlugin_div_stage_0_outNumerator[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24169 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[26] $abc$27210$new_n5492 $abc$27210$new_n5506 execute_RS1[25] $abc$27210$new_n5514 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[25] $abc$27210$new_n5516 _zz_memory_DivPlugin_div_stage_0_outNumerator[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24171 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[25] $abc$27210$new_n5506 $abc$27210$new_n5492 $abc$27210$new_n5516 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[24] $abc$27210$new_n5518 _zz_memory_DivPlugin_div_stage_0_outNumerator[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24173 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[24] $abc$27210$new_n5506 $abc$27210$new_n5493 execute_RS1[22] execute_RS1[23] $abc$27210$new_n5518 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[23] $abc$27210$new_n5520 _zz_memory_DivPlugin_div_stage_0_outNumerator[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24175 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[23] $abc$27210$new_n5493 $abc$27210$new_n5506 execute_RS1[22] $abc$27210$new_n5520 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[22] $abc$27210$new_n5522 _zz_memory_DivPlugin_div_stage_0_outNumerator[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24177 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[22] $abc$27210$new_n5506 $abc$27210$new_n5493 $abc$27210$new_n5522 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[21] $abc$27210$new_n5524 _zz_memory_DivPlugin_div_stage_0_outNumerator[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24179 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[21] $abc$27210$new_n5506 $abc$27210$new_n5494 execute_RS1[19] execute_RS1[20] $abc$27210$new_n5524 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$new_n5526 _zz_memory_DivPlugin_div_stage_0_outNumerator[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24181 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[20] $abc$27210$new_n5494 $abc$27210$new_n5506 execute_RS1[19] $abc$27210$new_n5526 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$new_n5528 _zz_memory_DivPlugin_div_stage_0_outNumerator[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24183 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[19] $abc$27210$new_n5506 $abc$27210$new_n5494 $abc$27210$new_n5528 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$new_n5530 _zz_memory_DivPlugin_div_stage_0_outNumerator[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24185 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[18] $abc$27210$new_n5506 $abc$27210$new_n5495 $abc$27210$new_n5530 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[17] $abc$27210$new_n5532 _zz_memory_DivPlugin_div_stage_0_outNumerator[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24187 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[17] $abc$27210$new_n5506 $abc$27210$new_n5496 $abc$27210$new_n5532 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[16] $abc$27210$new_n5534 _zz_memory_DivPlugin_div_stage_0_outNumerator[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24189 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[16] $abc$27210$new_n5506 $abc$27210$new_n5497 $abc$27210$new_n5534 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[15] $abc$27210$new_n5536 _zz_memory_DivPlugin_div_stage_0_outNumerator[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24191 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[15] $abc$27210$new_n5506 $abc$27210$new_n5498 $abc$27210$new_n5536 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[14] _zz_memory_DivPlugin_div_stage_0_outNumerator[15] $abc$27210$new_n5538 $abc$27210$auto$rtlil.cc:2693:MuxGate$24193 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[14] $abc$27210$new_n5506 $abc$27210$new_n5499 $abc$27210$new_n5538 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[13] _zz_memory_DivPlugin_div_stage_0_outNumerator[14] $abc$27210$new_n5540 $abc$27210$auto$rtlil.cc:2693:MuxGate$24195 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[13] $abc$27210$new_n5506 $abc$27210$new_n5500 $abc$27210$new_n5540 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[12] _zz_memory_DivPlugin_div_stage_0_outNumerator[13] $abc$27210$new_n5542 $abc$27210$auto$rtlil.cc:2693:MuxGate$24197 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[12] $abc$27210$new_n5506 $abc$27210$new_n5501 $abc$27210$new_n5542 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[11] _zz_memory_DivPlugin_div_stage_0_outNumerator[12] $abc$27210$new_n5544 $abc$27210$auto$rtlil.cc:2693:MuxGate$24199 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[11] $abc$27210$new_n5506 $abc$27210$new_n5502 $abc$27210$new_n5544 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[10] _zz_memory_DivPlugin_div_stage_0_outNumerator[11] $abc$27210$new_n5546 $abc$27210$auto$rtlil.cc:2693:MuxGate$24201 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[10] $abc$27210$new_n5506 $abc$27210$new_n5503 $abc$27210$new_n5546 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[9] _zz_memory_DivPlugin_div_stage_0_outNumerator[10] $abc$27210$new_n5548 $abc$27210$auto$rtlil.cc:2693:MuxGate$24203 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[9] $abc$27210$new_n5506 $abc$27210$new_n5504 execute_RS1[7] execute_RS1[8] $abc$27210$new_n5548 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[8] _zz_memory_DivPlugin_div_stage_0_outNumerator[9] $abc$27210$new_n5550 $abc$27210$auto$rtlil.cc:2693:MuxGate$24205 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[8] $abc$27210$new_n5504 $abc$27210$new_n5506 execute_RS1[7] $abc$27210$new_n5550 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[7] _zz_memory_DivPlugin_div_stage_0_outNumerator[8] $abc$27210$new_n5552 $abc$27210$auto$rtlil.cc:2693:MuxGate$24207 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[7] $abc$27210$new_n5506 $abc$27210$new_n5504 $abc$27210$new_n5552 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[6] _zz_memory_DivPlugin_div_stage_0_outNumerator[7] $abc$27210$new_n5554 $abc$27210$auto$rtlil.cc:2693:MuxGate$24209 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[6] $abc$27210$new_n5506 $abc$27210$new_n5505 execute_RS1[4] execute_RS1[5] $abc$27210$new_n5554 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[5] _zz_memory_DivPlugin_div_stage_0_outNumerator[6] $abc$27210$new_n5556 $abc$27210$auto$rtlil.cc:2693:MuxGate$24211 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[5] $abc$27210$new_n5505 $abc$27210$new_n5506 execute_RS1[4] $abc$27210$new_n5556 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[4] _zz_memory_DivPlugin_div_stage_0_outNumerator[5] $abc$27210$new_n5558 $abc$27210$auto$rtlil.cc:2693:MuxGate$24213 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[4] $abc$27210$new_n5506 $abc$27210$new_n5505 $abc$27210$new_n5558 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[3] _zz_memory_DivPlugin_div_stage_0_outNumerator[4] $abc$27210$new_n5560 $abc$27210$auto$rtlil.cc:2693:MuxGate$24215 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[3] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] execute_RS1[2] $abc$27210$new_n5560 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[2] _zz_memory_DivPlugin_div_stage_0_outNumerator[3] $abc$27210$new_n5562 $abc$27210$auto$rtlil.cc:2693:MuxGate$24217 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[2] $abc$27210$new_n5506 execute_RS1[0] execute_RS1[1] $abc$27210$new_n5562 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] _zz_memory_DivPlugin_div_stage_0_outNumerator[2] $abc$27210$new_n5564 $abc$27210$auto$rtlil.cc:2693:MuxGate$24219 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_RS1[1] execute_RS1[0] $abc$27210$new_n5506 $abc$27210$new_n5564 +011 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 $abc$27210$new_n4959 _zz_memory_DivPlugin_div_stage_0_outNumerator[1] execute_RS1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24221 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24223 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4698 $abc$27210$new_n4699 memory_to_writeBack_MEMORY_WR $abc$27210$new_n8208 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24237 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4751 $abc$27210$new_n5569 $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24239 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4698 dataCache_1.stageB_unaligned $abc$27210$new_n5569 +10 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24241 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24243 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24245 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24247 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24249 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24251 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24253 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24255 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24257 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24259 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24261 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24263 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24265 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24267 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24269 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24271 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24273 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24275 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24277 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[30] IBusCachedPlugin_cache._zz_banks_0_port1[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24279 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] $abc$27210$new_n5590 +000 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[29] IBusCachedPlugin_cache._zz_banks_0_port1[29] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24281 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[28] IBusCachedPlugin_cache._zz_banks_0_port1[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24283 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[27] IBusCachedPlugin_cache._zz_banks_0_port1[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24285 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[26] IBusCachedPlugin_cache._zz_banks_0_port1[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24287 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[25] IBusCachedPlugin_cache._zz_banks_0_port1[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24289 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[24] IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24291 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[23] IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24293 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[22] IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24295 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[21] IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24297 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[20] IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24299 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[19] IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24301 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[18] IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24303 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[17] IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24305 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[16] IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24307 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[15] IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[14] IBusCachedPlugin_cache._zz_banks_0_port1[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24311 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[13] IBusCachedPlugin_cache._zz_banks_0_port1[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24313 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[12] IBusCachedPlugin_cache._zz_banks_0_port1[12] _zz__zz_decode_IS_CSR_21 $abc$27210$auto$rtlil.cc:2693:MuxGate$24315 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[11] IBusCachedPlugin_cache._zz_banks_0_port1[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24317 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[10] IBusCachedPlugin_cache._zz_banks_0_port1[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24319 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[9] IBusCachedPlugin_cache._zz_banks_0_port1[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24321 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[8] IBusCachedPlugin_cache._zz_banks_0_port1[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24323 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[7] IBusCachedPlugin_cache._zz_banks_0_port1[7] _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24325 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[6] IBusCachedPlugin_cache._zz_banks_0_port1[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24327 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[5] IBusCachedPlugin_cache._zz_banks_0_port1[5] _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24329 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[4] IBusCachedPlugin_cache._zz_banks_0_port1[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24331 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[3] IBusCachedPlugin_cache._zz_banks_0_port1[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24333 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[2] IBusCachedPlugin_cache._zz_banks_0_port1[2] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24335 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[1] IBusCachedPlugin_cache._zz_banks_0_port1[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24337 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[0] IBusCachedPlugin_cache._zz_banks_0_port1[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24339 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[1] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24341 +011 1 +100 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24343 +01 1 +10 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[30] HazardSimplePlugin_writeBackWrites_payload_data[30] debug_bus_rsp_data[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24403 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5646 $abc$27210$new_n4255 $abc$27210$new_n5625 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[30] HazardSimplePlugin_writeBackWrites_payload_data[30] +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5626 $abc$27210$new_n5645 _zz__zz_decode_RS2_2[30] $abc$27210$new_n5625 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[61] $abc$27210$new_n5627 $abc$27210$new_n5626 +010 1 +100 1 +110 1 +111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5627 +000 1 +001 1 +011 1 +101 1 +.names $abc$27210$new_n5644 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] _zz_writeBack_MulPlugin_result_1[59] $abc$27210$new_n5629 $abc$27210$new_n5628 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] _zz_writeBack_MulPlugin_result_1[57] $abc$27210$new_n5630 $abc$27210$new_n5629 +0110 1 +1000 1 +.names $abc$27210$new_n5643 _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] _zz_writeBack_MulPlugin_result_1[55] $abc$27210$new_n5631 $abc$27210$new_n5630 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] _zz_writeBack_MulPlugin_result_1[53] $abc$27210$new_n5632 $abc$27210$new_n5631 +0110 1 +1000 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[51] $abc$27210$new_n5633 $abc$27210$new_n5632 +000 1 +001 1 +011 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] $abc$27210$new_n5634 $abc$27210$new_n5633 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] $abc$27210$new_n5635 $abc$27210$new_n5634 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] $abc$27210$new_n5636 $abc$27210$new_n5635 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] $abc$27210$new_n5637 $abc$27210$new_n5636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] $abc$27210$new_n5638 $abc$27210$new_n5637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] $abc$27210$new_n5639 $abc$27210$new_n5638 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] $abc$27210$new_n5640 $abc$27210$new_n5639 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] $abc$27210$new_n5641 $abc$27210$new_n5640 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 $abc$27210$new_n5641 +000 1 +001 1 +011 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] $abc$27210$new_n5642 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[53] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5643 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[57] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5644 +000 1 +001 1 +010 1 +011 1 +100 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5645 +00 1 +11 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5656 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5646 +1000 1 +1010 1 +1011 1 +.names MmuPlugin_dBusAccess_rsp_payload_data[7] $abc$27210$new_n4254 _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5647 +110 1 +.names $abc$27210$new_n5649 MmuPlugin_dBusAccess_rsp_payload_data[23] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5650 $abc$27210$new_n5651 $abc$27210$new_n5652 $abc$27210$new_n5649 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[31] dataCache_1.stageB_dataMux[31] $abc$27210$new_n5650 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[7] dataCache_1.stageB_dataMux[7] $abc$27210$new_n5651 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[15] dataCache_1.stageB_dataMux[15] $abc$27210$new_n5652 +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[23] dataCache_1.stageB_dataMux[23] MmuPlugin_dBusAccess_rsp_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4101 _zz_lastStageRegFileWrite_payload_address[12] MmuPlugin_dBusAccess_rsp_payload_data[15] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[14] $abc$27210$new_n5654 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5650 $abc$27210$new_n5652 MmuPlugin_dBusAccess_rsp_payload_data[15] +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[30] dataCache_1.stageB_dataMux[30] $abc$27210$new_n5656 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[29] HazardSimplePlugin_writeBackWrites_payload_data[29] debug_bus_rsp_data[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24405 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5660 $abc$27210$new_n5659 _zz__zz_decode_RS2_2[29] HazardSimplePlugin_writeBackWrites_payload_data[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[61] $abc$27210$new_n5627 $abc$27210$new_n5659 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5661 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n5660 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5661 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[29] dataCache_1.stageB_dataMux[29] MmuPlugin_dBusAccess_rsp_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[28] HazardSimplePlugin_writeBackWrites_payload_data[28] debug_bus_rsp_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24407 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5666 $abc$27210$new_n5665 _zz__zz_decode_RS2_2[28] HazardSimplePlugin_writeBackWrites_payload_data[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[60] $abc$27210$new_n5628 $abc$27210$new_n5665 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5667 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$new_n5666 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5667 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[28] dataCache_1.stageB_dataMux[28] MmuPlugin_dBusAccess_rsp_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[27] HazardSimplePlugin_writeBackWrites_payload_data[27] debug_bus_rsp_data[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24409 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5672 $abc$27210$new_n5671 _zz__zz_decode_RS2_2[27] HazardSimplePlugin_writeBackWrites_payload_data[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[59] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] $abc$27210$new_n5644 $abc$27210$new_n5629 $abc$27210$new_n5671 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11010 1 +.names $abc$27210$new_n5673 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$new_n5672 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5673 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[27] dataCache_1.stageB_dataMux[27] MmuPlugin_dBusAccess_rsp_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[26] HazardSimplePlugin_writeBackWrites_payload_data[26] debug_bus_rsp_data[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24411 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5678 $abc$27210$new_n5677 _zz__zz_decode_RS2_2[26] HazardSimplePlugin_writeBackWrites_payload_data[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[58] $abc$27210$new_n5644 $abc$27210$new_n5629 $abc$27210$new_n5677 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5679 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n5678 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5679 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[26] dataCache_1.stageB_dataMux[26] MmuPlugin_dBusAccess_rsp_payload_data[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[25] HazardSimplePlugin_writeBackWrites_payload_data[25] debug_bus_rsp_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24413 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5684 $abc$27210$new_n5683 _zz__zz_decode_RS2_2[25] HazardSimplePlugin_writeBackWrites_payload_data[25] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[57] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5630 $abc$27210$new_n5683 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5685 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[25] $abc$27210$new_n5684 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5685 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[25] dataCache_1.stageB_dataMux[25] MmuPlugin_dBusAccess_rsp_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[24] HazardSimplePlugin_writeBackWrites_payload_data[24] debug_bus_rsp_data[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24415 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5690 $abc$27210$new_n5689 _zz__zz_decode_RS2_2[24] HazardSimplePlugin_writeBackWrites_payload_data[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[56] $abc$27210$new_n5630 $abc$27210$new_n5689 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5691 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n5690 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5691 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[23] HazardSimplePlugin_writeBackWrites_payload_data[23] debug_bus_rsp_data[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24417 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5696 $abc$27210$new_n5694 _zz__zz_decode_RS2_2[23] HazardSimplePlugin_writeBackWrites_payload_data[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[55] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] $abc$27210$new_n5695 $abc$27210$new_n5694 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5643 $abc$27210$new_n5631 $abc$27210$new_n5695 +10 1 +.names $abc$27210$new_n5697 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n5696 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5697 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[22] HazardSimplePlugin_writeBackWrites_payload_data[22] debug_bus_rsp_data[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24419 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5701 $abc$27210$new_n5700 _zz__zz_decode_RS2_2[22] HazardSimplePlugin_writeBackWrites_payload_data[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[54] $abc$27210$new_n5695 $abc$27210$new_n5700 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5702 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$new_n5701 +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5654 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5702 +100 1 +101 1 +110 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[22] dataCache_1.stageB_dataMux[22] MmuPlugin_dBusAccess_rsp_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[21] HazardSimplePlugin_writeBackWrites_payload_data[21] debug_bus_rsp_data[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24421 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5707 $abc$27210$new_n5706 _zz__zz_decode_RS2_2[21] HazardSimplePlugin_writeBackWrites_payload_data[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[53] _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5632 $abc$27210$new_n5706 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$27210$new_n5708 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n5707 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5708 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[21] dataCache_1.stageB_dataMux[21] MmuPlugin_dBusAccess_rsp_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[20] HazardSimplePlugin_writeBackWrites_payload_data[20] debug_bus_rsp_data[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24423 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5713 $abc$27210$new_n5712 _zz__zz_decode_RS2_2[20] HazardSimplePlugin_writeBackWrites_payload_data[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[52] $abc$27210$new_n5632 $abc$27210$new_n5712 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5714 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$new_n5713 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5714 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[20] dataCache_1.stageB_dataMux[20] MmuPlugin_dBusAccess_rsp_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[19] HazardSimplePlugin_writeBackWrites_payload_data[19] debug_bus_rsp_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24425 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5719 $abc$27210$new_n5718 _zz__zz_decode_RS2_2[19] HazardSimplePlugin_writeBackWrites_payload_data[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[51] $abc$27210$new_n5633 $abc$27210$new_n5718 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5720 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$new_n5719 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5720 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[19] dataCache_1.stageB_dataMux[19] MmuPlugin_dBusAccess_rsp_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[18] HazardSimplePlugin_writeBackWrites_payload_data[18] debug_bus_rsp_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24427 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5725 $abc$27210$new_n5724 _zz__zz_decode_RS2_2[18] HazardSimplePlugin_writeBackWrites_payload_data[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[50] _zz_writeBack_MulPlugin_result[50] _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5724 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n5726 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n5725 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5726 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[18] dataCache_1.stageB_dataMux[18] MmuPlugin_dBusAccess_rsp_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[17] HazardSimplePlugin_writeBackWrites_payload_data[17] debug_bus_rsp_data[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24429 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5731 $abc$27210$new_n5730 _zz__zz_decode_RS2_2[17] HazardSimplePlugin_writeBackWrites_payload_data[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[49] _zz_writeBack_MulPlugin_result[49] $abc$27210$new_n5634 $abc$27210$new_n5730 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5732 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n5731 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5732 +1000 1 +1001 1 +1010 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[17] dataCache_1.stageB_dataMux[17] MmuPlugin_dBusAccess_rsp_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[16] HazardSimplePlugin_writeBackWrites_payload_data[16] debug_bus_rsp_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24431 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5737 $abc$27210$new_n5736 _zz__zz_decode_RS2_2[16] HazardSimplePlugin_writeBackWrites_payload_data[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[48] _zz_writeBack_MulPlugin_result[48] _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5736 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n5738 $abc$27210$new_n4255 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n5737 +0001 1 +0010 1 +0011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 MmuPlugin_dBusAccess_rsp_payload_data[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n5738 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[15] HazardSimplePlugin_writeBackWrites_payload_data[15] debug_bus_rsp_data[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24433 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5742 $abc$27210$new_n5741 _zz__zz_decode_RS2_2[15] HazardSimplePlugin_writeBackWrites_payload_data[15] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[47] _zz_writeBack_MulPlugin_result[47] $abc$27210$new_n5635 $abc$27210$new_n5741 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[15] MmuPlugin_dBusAccess_rsp_payload_data[15] $abc$27210$new_n4254 $abc$27210$new_n5742 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[14] HazardSimplePlugin_writeBackWrites_payload_data[14] debug_bus_rsp_data[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24435 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[46] _zz_writeBack_MulPlugin_result[46] _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5745 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 MmuPlugin_dBusAccess_rsp_payload_data[14] +000 1 +010 1 +100 1 +101 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[14] dataCache_1.stageB_dataMux[14] $abc$27210$new_n5749 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[13] HazardSimplePlugin_writeBackWrites_payload_data[13] debug_bus_rsp_data[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24437 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5753 $abc$27210$new_n5752 _zz__zz_decode_RS2_2[13] HazardSimplePlugin_writeBackWrites_payload_data[13] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[45] _zz_writeBack_MulPlugin_result[45] $abc$27210$new_n5636 $abc$27210$new_n5752 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[13] MmuPlugin_dBusAccess_rsp_payload_data[13] $abc$27210$new_n4254 $abc$27210$new_n5753 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[29] dBus_rsp_payload_data[13] dataCache_1.stageB_dataMux[13] MmuPlugin_dBusAccess_rsp_payload_data[13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[12] HazardSimplePlugin_writeBackWrites_payload_data[12] debug_bus_rsp_data[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24439 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[44] _zz_writeBack_MulPlugin_result[44] _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5757 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[28] dBus_rsp_payload_data[12] dataCache_1.stageB_dataMux[12] MmuPlugin_dBusAccess_rsp_payload_data[12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[11] HazardSimplePlugin_writeBackWrites_payload_data[11] debug_bus_rsp_data[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24441 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5764 $abc$27210$new_n5763 _zz__zz_decode_RS2_2[11] HazardSimplePlugin_writeBackWrites_payload_data[11] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[43] _zz_writeBack_MulPlugin_result[43] $abc$27210$new_n5637 $abc$27210$new_n5763 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5647 DBusCachedPlugin_exceptionBus_payload_badAddr[11] MmuPlugin_dBusAccess_rsp_payload_data[11] $abc$27210$new_n4254 $abc$27210$new_n5764 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[27] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[11] +000 1 +010 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[11] dataCache_1.stageB_dataMux[11] $abc$27210$new_n5766 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[10] HazardSimplePlugin_writeBackWrites_payload_data[10] debug_bus_rsp_data[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24443 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[42] _zz_writeBack_MulPlugin_result[42] _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5769 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 MmuPlugin_dBusAccess_rsp_payload_data[10] +000 1 +010 1 +110 1 +111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[10] dataCache_1.stageB_dataMux[10] $abc$27210$new_n5773 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[9] HazardSimplePlugin_writeBackWrites_payload_data[9] debug_bus_rsp_data[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24445 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5776 $abc$27210$new_n5779 _zz__zz_decode_RS2_2[9] HazardSimplePlugin_writeBackWrites_payload_data[9] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5777 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n5776 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n5647 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n5777 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[9] dataCache_1.stageB_dataMux[9] $abc$27210$new_n5778 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[41] _zz_writeBack_MulPlugin_result[41] $abc$27210$new_n5638 $abc$27210$new_n5779 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[8] HazardSimplePlugin_writeBackWrites_payload_data[8] debug_bus_rsp_data[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24447 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5782 $abc$27210$new_n5784 _zz__zz_decode_RS2_2[8] HazardSimplePlugin_writeBackWrites_payload_data[8] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 $abc$27210$new_n5647 $abc$27210$new_n5783 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n5782 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n4254 MmuPlugin_dBusAccess_rsp_payload_data[24] $abc$27210$new_n4251 $abc$27210$new_n5783 +0000 1 +0010 1 +1010 1 +1011 1 +.names _zz_writeBack_MulPlugin_result_1[40] _zz_writeBack_MulPlugin_result[40] _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5784 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[7] HazardSimplePlugin_writeBackWrites_payload_data[7] debug_bus_rsp_data[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24449 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5788 $abc$27210$new_n5787 _zz__zz_decode_RS2_2[7] HazardSimplePlugin_writeBackWrites_payload_data[7] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[39] _zz_writeBack_MulPlugin_result[39] $abc$27210$new_n5639 $abc$27210$new_n5787 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[7] DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n5788 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[6] HazardSimplePlugin_writeBackWrites_payload_data[6] debug_bus_rsp_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24451 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5791 $abc$27210$new_n5795 _zz__zz_decode_RS2_2[6] HazardSimplePlugin_writeBackWrites_payload_data[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n4255 MmuPlugin_dBusAccess_rsp_payload_data[6] DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n5791 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n5793 MmuPlugin_dBusAccess_rsp_payload_data[22] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[6] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5656 $abc$27210$new_n5749 $abc$27210$new_n5794 $abc$27210$new_n5793 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[6] dataCache_1.stageB_dataMux[6] $abc$27210$new_n5794 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[38] _zz_writeBack_MulPlugin_result[38] _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5795 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[5] HazardSimplePlugin_writeBackWrites_payload_data[5] debug_bus_rsp_data[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24453 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n8115 $abc$27210$new_n5798 _zz__zz_decode_RS2_2[5] HazardSimplePlugin_writeBackWrites_payload_data[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result_1[37] _zz_writeBack_MulPlugin_result[37] $abc$27210$new_n5640 $abc$27210$new_n5798 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[4] HazardSimplePlugin_writeBackWrites_payload_data[4] DebugPlugin_busReadDataReg[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24455 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5805 $abc$27210$new_n5808 _zz__zz_decode_RS2_2[4] HazardSimplePlugin_writeBackWrites_payload_data[4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 $abc$27210$new_n5806 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n5805 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[12] MmuPlugin_dBusAccess_rsp_payload_data[20] $abc$27210$new_n5807 $abc$27210$new_n5806 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[4] dataCache_1.stageB_dataMux[4] $abc$27210$new_n5807 +001 1 +011 1 +110 1 +111 1 +.names _zz_writeBack_MulPlugin_result_1[36] _zz_writeBack_MulPlugin_result[36] _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5808 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[3] HazardSimplePlugin_writeBackWrites_payload_data[3] DebugPlugin_busReadDataReg[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24457 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n5811 $abc$27210$new_n5814 _zz__zz_decode_RS2_2[3] HazardSimplePlugin_writeBackWrites_payload_data[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4101 MmuPlugin_dBusAccess_rsp_payload_data[3] DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n5811 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n5813 MmuPlugin_dBusAccess_rsp_payload_data[19] $abc$27210$new_n5766 MmuPlugin_dBusAccess_rsp_payload_data[3] +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[27] dBus_rsp_payload_data[3] dataCache_1.stageB_dataMux[3] $abc$27210$new_n5813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_writeBack_MulPlugin_result_1[35] _zz_writeBack_MulPlugin_result[35] $abc$27210$new_n5641 $abc$27210$new_n5814 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[2] HazardSimplePlugin_writeBackWrites_payload_data[2] DebugPlugin_busReadDataReg[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24459 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n5820 MmuPlugin_dBusAccess_rsp_payload_data[2] DBusCachedPlugin_exceptionBus_payload_badAddr[2] HazardSimplePlugin_writeBackWrites_payload_data[2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n5818 MmuPlugin_dBusAccess_rsp_payload_data[18] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[2] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[26] $abc$27210$new_n5773 $abc$27210$new_n5819 $abc$27210$new_n5818 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[2] dataCache_1.stageB_dataMux[2] $abc$27210$new_n5819 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4254 _zz_writeBack_MulPlugin_result_1[34] _zz_writeBack_MulPlugin_result[34] $abc$27210$new_n5642 _zz__zz_decode_RS2_2[2] $abc$27210$new_n5820 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] $abc$27210$new_n4258 $abc$27210$auto$rtlil.cc:2693:MuxGate$24461 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_valid memory_to_writeBack_IS_DBUS_SHARING $abc$27210$auto$rtlil.cc:2693:MuxGate$24463 +0100 1 +0101 1 +0110 1 +1001 1 +1101 1 +.names memory_to_writeBack_IS_DBUS_SHARING dBus_cmd_payload_wr $abc$27210$new_n4094 MmuPlugin_dBusAccess_rsp_payload_redo MmuPlugin_dBusAccess_rsp_valid +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n5825 $abc$27210$new_n4093 CsrPlugin_pipelineLiberator_pcValids_2 CsrPlugin_pipelineLiberator_pcValids_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24467 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4316 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$new_n5825 +110 1 +.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n5826 +11 1 +.names $abc$27210$new_n5828 $abc$27210$new_n4637 $abc$27210$new_n5827 +10 1 +.names $abc$27210$new_n4431 $abc$27210$new_n4428 $abc$27210$new_n5829 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$27210$new_n5828 +10000 1 +10001 1 +10010 1 +.names $abc$27210$new_n4256 memory_arbitration_isValid lastStageIsValid $abc$27210$new_n5829 +100 1 +.names $abc$27210$new_n4700 $abc$27210$new_n8208 $abc$27210$new_n5830 +00 1 +.names $abc$27210$new_n5825 DBusCachedPlugin_mmuBus_cmd_0_isStuck CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24469 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5825 $abc$27210$new_n4259 CsrPlugin_pipelineLiberator_pcValids_0 $abc$27210$auto$rtlil.cc:2693:MuxGate$24471 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5387 CsrPlugin_mie_MSIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24473 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n5834 +1111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5366 CsrPlugin_mie_MTIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24475 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5834 $abc$27210$new_n5344 CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24477 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5838 $abc$27210$new_n4324 MmuPlugin_shared_state_1[2] MmuPlugin_shared_dBusRspStaged_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24479 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] MmuPlugin_shared_state_1[2] $abc$27210$new_n5838 +110 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5840 MmuPlugin_satp_mode $abc$27210$auto$rtlil.cc:2693:MuxGate$24481 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5843 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5841 $abc$27210$new_n5840 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5842 execute_CsrPlugin_csr_384 MmuPlugin_satp_mode execute_CsrPlugin_csr_834 CsrPlugin_mcause_interrupt $abc$27210$new_n5841 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[31] CsrPlugin_mepc[31] execute_CsrPlugin_csr_833 $abc$27210$new_n5842 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] _zz_execute_BranchPlugin_branch_src2 execute_RS1[31] $abc$27210$new_n5843 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4435 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n4441 IBusCachedPlugin_injector_nextPcCalc_valids_0 IBusCachedPlugin_iBusRsp_readyForError $abc$27210$auto$rtlil.cc:2693:MuxGate$24483 +10001 1 +10011 1 +11010 1 +11011 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_injector_nextPcCalc_valids_0 $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$auto$rtlil.cc:2693:MuxGate$24485 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24487 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5830 $abc$27210$new_n5827 $abc$27210$new_n4441 $abc$27210$new_n4258 $abc$27210$new_n4424 $abc$27210$new_n5847 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n5849 IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5847 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24489 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$new_n5850 $abc$27210$new_n5858 $abc$27210$new_n5856 $abc$27210$new_n5855 $abc$27210$new_n5849 +11000 1 +.names $abc$27210$new_n4432 $abc$27210$new_n5852 $abc$27210$new_n5829 $abc$27210$new_n4636 $abc$27210$new_n5851 $abc$27210$new_n5850 +11000 1 +.names CsrPlugin_exceptionPendings_1 $abc$27210$new_n5827 $abc$27210$new_n5851 +11 1 +.names $abc$27210$new_n5853 IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_flushPending lastStageIsValid _zz_writeBack_ENV_CTRL $abc$27210$new_n5852 +10000 1 +10001 1 +10010 1 +.names IBusCachedPlugin_cache._zz_when_InstructionCache_l342 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_fetchPc_booted DebugPlugin_haltIt $abc$27210$new_n5854 $abc$27210$new_n5853 +11100 1 +.names DebugPlugin_stepIt IBusCachedPlugin_cache.io_cpu_decode_isValid IBusCachedPlugin_cache.io_cpu_fetch_isValid $abc$27210$new_n5854 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5827 $abc$27210$new_n5830 CsrPlugin_exceptionPendings_0 $abc$27210$new_n5855 +100 1 +101 1 +111 1 +.names $abc$27210$new_n4431 $abc$27210$new_n5857 $abc$27210$new_n4701 CsrPlugin_exceptionPendings_2 $abc$27210$new_n5856 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4428 $abc$27210$new_n4637 $abc$27210$new_n5857 +00 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$new_n5859 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4266 $abc$27210$new_n5858 +1100 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n5859 +10 1 +.names $abc$27210$new_n5849 IBusCachedPlugin_fetchPc_inc $abc$27210$new_n4435 $abc$27210$new_n4441 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24491 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5862 $abc$27210$new_n5857 $abc$27210$new_n4093 lastStageIsValid $abc$27210$auto$rtlil.cc:2693:MuxGate$24493 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5863 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5862 +10 1 +.names memory_arbitration_isValid $abc$27210$new_n5857 $abc$27210$new_n4431 $abc$27210$new_n4701 $abc$27210$new_n5863 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5863 $abc$27210$new_n4259 execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$auto$rtlil.cc:2693:MuxGate$24495 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5866 $abc$27210$new_n4258 $abc$27210$new_n5826 $abc$27210$new_n4266 $abc$27210$auto$rtlil.cc:2693:MuxGate$24497 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names execute_arbitration_isValid $abc$27210$new_n5827 $abc$27210$new_n4259 $abc$27210$new_n5866 +110 1 +.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[2] $abc$27210$new_n5869 $abc$27210$auto$rtlil.cc:2693:MuxGate$24637 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$27210$new_n5869 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$27210$new_n5868 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$new_n5869 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$27210$new_n5868 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$27210$auto$rtlil.cc:2693:MuxGate$24641 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names CsrPlugin_hadException CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] CsrPlugin_mtval[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24645 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4433 CsrPlugin_mcause_interrupt CsrPlugin_hadException $abc$27210$auto$rtlil.cc:2693:MuxGate$24647 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4261 $abc$27210$new_n4093 _zz_memory_DivPlugin_div_stage_0_outNumerator[31] $abc$27210$new_n5881 memory_DivPlugin_div_stage_0_remainderShifted $abc$27210$auto$rtlil.cc:2693:MuxGate$24655 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5506 $abc$27210$new_n5490 execute_RS1[30] execute_RS1[31] $abc$27210$new_n5881 +0000 1 +0010 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_dBusRspStaged_valid MmuPlugin_shared_dBusRspStaged_payload_redo MmuPlugin_shared_pteBuffer_PPN0[9] MmuPlugin_shared_dBusRspStaged_payload_data[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24659 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names MmuPlugin_shared_vpn_1[9] $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24661 +01 1 +10 1 +11 1 +.names $abc$27210$new_n5056 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_shared_vpn_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24663 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_5_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24665 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24667 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_5_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24669 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24671 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_5_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24673 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_5_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24675 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24677 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5075 MmuPlugin_ports_1_cache_5_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24679 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5075 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_5_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24681 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5898 MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[0] $abc$27210$new_n5895 MmuPlugin_shared_state_1[2] $abc$27210$new_n5894 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5897 $abc$27210$new_n5896 MmuPlugin_shared_dBusRspStaged_payload_data[17] MmuPlugin_shared_dBusRspStaged_payload_data[18] $abc$27210$new_n5895 +1100 1 +.names MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_shared_dBusRspStaged_payload_data[10] MmuPlugin_shared_dBusRspStaged_payload_data[11] MmuPlugin_shared_dBusRspStaged_payload_data[12] $abc$27210$new_n5896 +0000 1 +.names MmuPlugin_shared_dBusRspStaged_payload_data[13] MmuPlugin_shared_dBusRspStaged_payload_data[14] MmuPlugin_shared_dBusRspStaged_payload_data[15] MmuPlugin_shared_dBusRspStaged_payload_data[16] $abc$27210$new_n5897 +0000 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_error MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRsp_pte_W $abc$27210$new_n5898 +11000 1 +11010 1 +11011 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_4_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24685 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_4_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_4_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_4_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5113 MmuPlugin_ports_1_cache_4_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24697 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5113 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_4_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24699 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_3_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24703 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_3_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_3_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_3_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_3_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5150 MmuPlugin_ports_1_cache_3_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24715 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5150 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_3_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24717 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_2_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24721 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_2_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_2_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_2_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_2_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5187 MmuPlugin_ports_1_cache_2_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24733 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5187 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_2_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24735 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_1_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24739 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_1_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_1_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_1_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24747 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24749 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5224 MmuPlugin_ports_1_cache_1_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24751 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5224 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_1_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24753 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_ports_1_cache_0_allowExecute $abc$27210$auto$rtlil.cc:2693:MuxGate$24755 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRsp_pte_W $abc$27210$auto$rtlil.cc:2693:MuxGate$24757 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_ports_1_cache_0_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24759 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[29] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24761 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_dBusRspStaged_payload_data[19] MmuPlugin_ports_1_cache_0_physicalAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_1[9] MmuPlugin_ports_1_cache_0_virtualAddress_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24765 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_shared_vpn_0[9] MmuPlugin_ports_1_cache_0_virtualAddress_0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5261 MmuPlugin_ports_1_cache_0_superPage MmuPlugin_shared_state_1[1] MmuPlugin_shared_state_1[2] MmuPlugin_shared_state_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24769 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5261 $abc$27210$new_n5894 MmuPlugin_ports_1_cache_0_exception $abc$27210$auto$rtlil.cc:2693:MuxGate$24771 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5945 MmuPlugin_satp_ppn[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24773 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5948 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5946 $abc$27210$new_n5945 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5947 execute_CsrPlugin_csr_833 CsrPlugin_mepc[21] $abc$27210$new_n5946 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[21] execute_CsrPlugin_csr_384 MmuPlugin_satp_ppn[21] $abc$27210$new_n5947 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[21] _zz__zz_execute_BranchPlugin_branch_src2_2[0] $abc$27210$new_n5948 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5950 MmuPlugin_satp_asid[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24775 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5953 switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n5951 $abc$27210$new_n5950 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1100 1 +1110 1 +.names $abc$27210$new_n5952 execute_CsrPlugin_csr_833 CsrPlugin_mepc[30] $abc$27210$new_n5951 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_835 CsrPlugin_mtval[30] execute_CsrPlugin_csr_384 MmuPlugin_satp_asid[8] $abc$27210$new_n5952 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_execute_SRC1_CTRL[0] _zz_execute_SRC1_CTRL[1] execute_RS1[30] _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$new_n5953 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz__zz_3_port1[1] _zz_decode_PREDICTION_CONTEXT_line_history_2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24777 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5956 _zz_decode_PREDICTION_CONTEXT_hazard_4 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$24779 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5957 _zz_decode_PREDICTION_CONTEXT_hazard_3[8] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] $abc$27210$new_n5956 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5958 _zz_decode_PREDICTION_CONTEXT_hazard_3[6] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] _zz_decode_PREDICTION_CONTEXT_hazard_3[7] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] $abc$27210$new_n5957 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5959 _zz_decode_PREDICTION_CONTEXT_hazard_3[4] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] _zz_decode_PREDICTION_CONTEXT_hazard_3[5] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] $abc$27210$new_n5958 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n5960 _zz_decode_PREDICTION_CONTEXT_hazard_3[1] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] _zz_decode_PREDICTION_CONTEXT_hazard_3[3] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] $abc$27210$new_n5959 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$new_n5961 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_3[0] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] $abc$27210$new_n5960 +11100 1 +11111 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_3[2] IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] $abc$27210$new_n5961 +00 1 +11 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_decode_PREDICTION_CONTEXT_hazard_3[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24781 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_BRANCH_CTRL[0] $abc$27210$new_n5862 execute_to_memory_PREDICTION_CONTEXT_hazard _zz_memory_BRANCH_CTRL[1] $abc$27210$new_n5964 _zz_2 +11000 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[1] execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid $abc$27210$new_n5964 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_2 _zz_decode_PREDICTION_CONTEXT_hazard_2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24783 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[26] DebugPlugin_disableEbreak debug_bus_cmd_payload_data[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24785 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4321 debug_bus_cmd_payload_address[5] debug_bus_cmd_payload_address[4] debug_bus_cmd_payload_address[2] $abc$27210$new_n5967 +1000 1 +.names debug_bus_cmd_valid DebugPlugin_debugUsed $abc$27210$auto$rtlil.cc:2693:MuxGate$24787 +01 1 +10 1 +11 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[4] DebugPlugin_stepIt $abc$27210$auto$rtlil.cc:2693:MuxGate$24789 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5967 debug_bus_cmd_payload_data[24] DebugPlugin_resetIt debug_bus_cmd_payload_data[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24791 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_refilling $abc$27210$new_n4090 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24807 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_exception $abc$27210$new_n4090 $abc$27210$new_n5973 $abc$27210$new_n8224 $abc$27210$auto$rtlil.cc:2693:MuxGate$24811 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n5976 $abc$27210$new_n5974 $abc$27210$new_n4085 MmuPlugin_ports_1_cache_4_exception $abc$27210$new_n5973 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4084 $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_exception $abc$27210$new_n5975 $abc$27210$new_n5974 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_exception MmuPlugin_ports_1_cache_5_exception $abc$27210$new_n5975 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_exception MmuPlugin_ports_1_cache_3_exception $abc$27210$new_n5976 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n5978 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24815 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n5979 MmuPlugin_ports_1_cache_4_allowWrite $abc$27210$new_n5978 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n5980 $abc$27210$new_n3943 $abc$27210$new_n4088 MmuPlugin_ports_1_cache_1_allowWrite $abc$27210$new_n5981 $abc$27210$new_n5979 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 MmuPlugin_ports_1_cache_2_allowWrite MmuPlugin_ports_1_cache_3_allowWrite $abc$27210$new_n5980 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowWrite MmuPlugin_ports_1_cache_5_allowWrite $abc$27210$new_n5981 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n5983 $abc$27210$new_n4092 dataCache_1.stageB_mmuRsp_allowRead $abc$27210$auto$rtlil.cc:2693:MuxGate$24819 +001 1 +010 1 +011 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 $abc$27210$new_n4085 $abc$27210$new_n8123 $abc$27210$new_n5991 $abc$27210$new_n5983 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_5_allowRead $abc$27210$new_n5989 MmuPlugin_ports_1_cache_5_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5988 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4049 MmuPlugin_ports_1_cache_0_allowRead MmuPlugin_ports_1_cache_0_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5989 +1000 1 +1001 1 +1010 1 +.names MmuPlugin_ports_1_cache_4_allowRead MmuPlugin_ports_1_cache_4_allowExecute MmuPlugin_status_mxr $abc$27210$new_n5991 +000 1 +001 1 +010 1 +.names $abc$27210$new_n4092 $abc$27210$new_n4090 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n5994 dBus_cmd_payload_uncached DebugPlugin_godmode dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24825 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n3940 $abc$27210$new_n8126 $abc$27210$new_n4111 $abc$27210$new_n4106 $abc$27210$new_n5994 +1100 1 +.names $abc$27210$new_n4049 DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] $abc$27210$new_n5998 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4092 $abc$27210$new_n8126 dBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24827 +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.tagsWriteCmd_payload_data_error dataCache_1.loader_counter_willOverflow dataCache_1.loader_error dataCache_1.io_cpu_execute_refilling $abc$27210$auto$rtlil.cc:2693:MuxGate$24841 +1001 1 +1010 1 +1011 1 +.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] dataCache_1.loader_counter_value[2] $abc$27210$new_n6003 dataCache_1.loader_counter_willOverflow +1111 1 +.names dBus_rsp_valid dataCache_1.io_cpu_execute_refilling $abc$27210$new_n6003 +11 1 +.names dataCache_1.loader_error dBus_rsp_valid dBus_rsp_payload_error dataCache_1.tagsWriteCmd_payload_data_error +011 1 +100 1 +101 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dataCache_1.io_cpu_execute_refilling $abc$27210$new_n4095 dBus_cmd_payload_size[2] dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24843 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names dataCache_1.stageB_flusher_counter[6] $abc$27210$new_n6008 $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[7] dataCache_1.stageB_flusher_start $abc$27210$auto$rtlil.cc:2693:MuxGate$24845 +00100 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dataCache_1.stageB_flusher_counter[5] $abc$27210$new_n4228 $abc$27210$new_n6007 +11 1 +.names execute_RS1[11] $abc$27210$new_n4233 $abc$27210$new_n6008 +11 1 +.names dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone dataCache_1.stageB_flusher_counter[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24847 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.memCmdSent dBus_cmd_ready $abc$27210$auto$rtlil.cc:2693:MuxGate$24849 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4095 $abc$27210$new_n6012 $abc$27210$new_n4100 dBus_cmd_valid +100 1 +.names dBus_cmd_payload_wr dBus_cmd_payload_uncached dataCache_1.memCmdSent dataCache_1.stageB_waysHit $abc$27210$new_n6012 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24851 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n6015 IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_ready IBusCachedPlugin_cache.lineLoader_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24853 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names IBusCachedPlugin_cache.lineLoader_wordIndex[2] IBusCachedPlugin_cache.lineLoader_wordIndex[0] iBus_rsp_valid IBusCachedPlugin_cache.lineLoader_wordIndex[1] $abc$27210$new_n6015 +1111 1 +.names IBusCachedPlugin_cache.when_InstructionCache_l351 $abc$27210$new_n5858 IBusCachedPlugin_cache.lineLoader_flushPending $abc$27210$auto$rtlil.cc:2693:MuxGate$24855 +001 1 +010 1 +011 1 +.names IBusCachedPlugin_cache.lineLoader_flushPending IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.when_InstructionCache_l351 +100 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.lineLoader_valid $abc$27210$new_n6015 $abc$27210$auto$rtlil.cc:2693:MuxGate$24857 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5590 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 debug_bus_cmd_payload_data[31] IBusCachedPlugin_cache._zz_banks_0_port1[31] _zz_6 $abc$27210$auto$rtlil.cc:2693:MuxGate$24859 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24861 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] IBusCachedPlugin_cache.decodeStage_hit_tags_0_error $abc$27210$auto$rtlil.cc:2693:MuxGate$24863 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24865 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] $abc$27210$new_n4960 $abc$27210$new_n4261 memory_DivPlugin_accumulator[31] _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24869 +00010 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names memory_DivPlugin_div_done $abc$27210$new_n4904 memory_DivPlugin_div_counter_value[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24871 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4439 $abc$27210$new_n6027 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] $abc$27210$new_n6026 $abc$27210$new_n6029 $abc$27210$auto$rtlil.cc:2693:MuxGate$24875 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$27210$new_n4423 _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 $abc$27210$new_n6026 +10010 1 +10100 1 +10101 1 +10111 1 +11001 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n4441 $abc$27210$new_n6028 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$new_n6027 +1010 1 +1011 1 +1100 1 +1110 1 +.names IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] $abc$27210$new_n4444 $abc$27210$new_n6028 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n6030 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[31] $abc$27210$new_n6029 +0000 1 +0001 1 +0010 1 +.names $abc$27210$new_n4434 BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$new_n4437 $abc$27210$new_n4438 CsrPlugin_mepc[31] $abc$27210$new_n6030 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] CsrPlugin_mcause_exceptionCode[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24879 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names CsrPlugin_hadException $abc$27210$new_n4433 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24881 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24883 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4441 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] iBus_cmd_payload_address[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24887 +001 1 +011 1 +110 1 +111 1 +.names lastStageIsValid $abc$27210$new_n4256 HazardSimplePlugin_writeBackWrites_payload_data[1] DebugPlugin_busReadDataReg[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24891 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n6040 MmuPlugin_dBusAccess_rsp_payload_data[1] _zz_writeBack_DBusCachedPlugin_rspShifted_3 HazardSimplePlugin_writeBackWrites_payload_data[1] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6038 MmuPlugin_dBusAccess_rsp_payload_data[17] _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[0] MmuPlugin_dBusAccess_rsp_payload_data[1] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names DBusCachedPlugin_exceptionBus_payload_badAddr[0] _zz_writeBack_DBusCachedPlugin_rspShifted_3 MmuPlugin_dBusAccess_rsp_payload_data[25] $abc$27210$new_n5778 $abc$27210$new_n6039 $abc$27210$new_n6038 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dBus_cmd_payload_uncached dBus_rsp_payload_data[1] dataCache_1.stageB_dataMux[1] $abc$27210$new_n6039 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4254 _zz__zz_decode_RS2_2[1] $abc$27210$new_n6041 $abc$27210$new_n6040 +000 1 +010 1 +100 1 +101 1 +.names _zz_writeBack_MulPlugin_result_1[33] _zz_writeBack_MulPlugin_result[33] _zz_writeBack_MulPlugin_result_1[32] _zz_writeBack_MulPlugin_result[32] $abc$27210$new_n6041 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$27210$new_n4256 lastStageIsValid _zz_execute_to_memory_PC[31] HazardSimplePlugin_writeBackWrites_payload_data[31] debug_bus_rsp_data[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24893 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 $abc$27210$new_n6045 $abc$27210$new_n6044 _zz__zz_decode_RS2_2[31] HazardSimplePlugin_writeBackWrites_payload_data[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result_1[63] _zz_writeBack_MulPlugin_result_1[62] $abc$27210$new_n5626 $abc$27210$new_n6044 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6046 $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$new_n6045 +001 1 +010 1 +011 1 +.names $abc$27210$new_n5654 $abc$27210$new_n5647 $abc$27210$new_n5650 _zz_lastStageRegFileWrite_payload_address[13] $abc$27210$new_n6046 +1000 1 +1010 1 +1011 1 +.names $abc$27210$new_n4635 execute_to_memory_PC[31] DBusCachedPlugin_redoBranch_payload[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24897 +001 1 +011 1 +110 1 +111 1 +.names when_MmuPlugin_l281_1 $abc$27210$new_n5056 $abc$27210$auto$rtlil.cc:2693:MuxGate$24899 +01 1 +10 1 +11 1 +.names $abc$27210$new_n4696 CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] $abc$27210$new_n4102 $abc$27210$new_n5569 dataCache_1.stageB_mmuRsp_isPaging $abc$27210$auto$rtlil.cc:2693:MuxGate$24903 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] $abc$27210$new_n4696 $abc$27210$auto$rtlil.cc:2693:MuxGate$24905 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[30] dataCache_1._zz_ways_0_data_port0[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21679 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[29] dataCache_1._zz_ways_0_data_port0[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21681 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[28] dataCache_1._zz_ways_0_data_port0[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$21683 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[27] dataCache_1._zz_ways_0_data_port0[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21685 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[26] dataCache_1._zz_ways_0_data_port0[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$21687 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[25] dataCache_1._zz_ways_0_data_port0[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21689 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[24] dataCache_1._zz_ways_0_data_port0[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$21691 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[23] dataCache_1._zz_ways_0_data_port0[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21693 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[22] dataCache_1._zz_ways_0_data_port0[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$21695 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[21] dataCache_1._zz_ways_0_data_port0[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$21697 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[20] dataCache_1._zz_ways_0_data_port0[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$21699 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[19] dataCache_1._zz_ways_0_data_port0[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$21701 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[18] dataCache_1._zz_ways_0_data_port0[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$21703 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[17] dataCache_1._zz_ways_0_data_port0[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$21705 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[16] dataCache_1._zz_ways_0_data_port0[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21707 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[15] dataCache_1._zz_ways_0_data_port0[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21709 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[14] dataCache_1._zz_ways_0_data_port0[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21711 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[13] dataCache_1._zz_ways_0_data_port0[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21713 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[12] dataCache_1._zz_ways_0_data_port0[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21715 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[11] dataCache_1._zz_ways_0_data_port0[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21717 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[10] dataCache_1._zz_ways_0_data_port0[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21719 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[9] dataCache_1._zz_ways_0_data_port0[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21721 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[8] dataCache_1._zz_ways_0_data_port0[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21723 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[7] dataCache_1._zz_ways_0_data_port0[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21725 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[6] dataCache_1._zz_ways_0_data_port0[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21727 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[5] dataCache_1._zz_ways_0_data_port0[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21729 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[4] dataCache_1._zz_ways_0_data_port0[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21731 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[3] dataCache_1._zz_ways_0_data_port0[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21733 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[2] dataCache_1._zz_ways_0_data_port0[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21735 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[1] dataCache_1._zz_ways_0_data_port0[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21737 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[0] dataCache_1._zz_ways_0_data_port0[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21739 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[2] dataCache_1.stageA_mask[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21741 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[1] dataCache_1.stageA_mask[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21743 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[0] dataCache_1.stageA_mask[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21745 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_request_size[0] dataCache_1.stageA_request_size[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21809 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[2] $abc$27210$new_n6087 $abc$27210$auto$rtlil.cc:2693:MuxGate$21811 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6091 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n4327 switch_Misc_l241_1 $abc$27210$new_n6088 $abc$27210$new_n6087 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11010 1 +11011 1 +.names $abc$27210$new_n6089 $abc$27210$new_n4327 $abc$27210$new_n6088 +00 1 +.names $abc$27210$new_n5407 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6090 $abc$27210$new_n6089 +000 1 +101 1 +110 1 +111 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[0] _zz_execute_BranchPlugin_branch_src2_8 _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$new_n6090 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5402 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6093 $abc$27210$new_n6092 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6091 +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n5407 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6092 +010 1 +011 1 +100 1 +110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[1] _zz__zz_execute_BranchPlugin_branch_src2_2[0] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$new_n6093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[1] $abc$27210$new_n6095 $abc$27210$auto$rtlil.cc:2693:MuxGate$21813 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6089 _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6091 $abc$27210$new_n6095 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[0] $abc$27210$new_n6097 $abc$27210$auto$rtlil.cc:2693:MuxGate$21815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6088 $abc$27210$new_n6091 $abc$27210$new_n4327 $abc$27210$new_n6097 +001 1 +010 1 +011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_request_size[0] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$21829 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6100 _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] _zz_writeBack_MulPlugin_result[50] $abc$27210$auto$rtlil.cc:2693:MuxGate$21843 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] $abc$27210$new_n6176 $abc$27210$new_n6177 $abc$27210$new_n6101 $abc$27210$new_n6100 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n6172 $abc$27210$new_n6173 $abc$27210$new_n6174 $abc$27210$new_n6102 $abc$27210$new_n6175 $abc$27210$new_n6101 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6168 $abc$27210$new_n6169 $abc$27210$new_n6170 $abc$27210$new_n6103 $abc$27210$new_n6171 $abc$27210$new_n6102 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6164 $abc$27210$new_n6165 $abc$27210$new_n6166 $abc$27210$new_n6104 $abc$27210$new_n6167 $abc$27210$new_n6103 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6160 $abc$27210$new_n6161 $abc$27210$new_n6162 $abc$27210$new_n6105 $abc$27210$new_n6163 $abc$27210$new_n6104 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6156 $abc$27210$new_n6157 $abc$27210$new_n6158 $abc$27210$new_n6106 $abc$27210$new_n6159 $abc$27210$new_n6105 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6152 $abc$27210$new_n6153 $abc$27210$new_n6154 $abc$27210$new_n6107 $abc$27210$new_n6155 $abc$27210$new_n6106 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6148 $abc$27210$new_n6149 $abc$27210$new_n6150 $abc$27210$new_n6108 $abc$27210$new_n6151 $abc$27210$new_n6107 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6144 $abc$27210$new_n6145 $abc$27210$new_n6146 $abc$27210$new_n6109 $abc$27210$new_n6147 $abc$27210$new_n6108 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6141 $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 $abc$27210$new_n6109 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n6139 $abc$27210$new_n6140 $abc$27210$new_n6138 $abc$27210$new_n6137 $abc$27210$new_n6111 $abc$27210$new_n6110 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6135 $abc$27210$new_n6136 $abc$27210$new_n6134 $abc$27210$new_n6133 $abc$27210$new_n6112 $abc$27210$new_n6111 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6131 $abc$27210$new_n6132 $abc$27210$new_n6130 $abc$27210$new_n6129 $abc$27210$new_n6113 $abc$27210$new_n6112 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6127 $abc$27210$new_n6128 $abc$27210$new_n6126 $abc$27210$new_n6125 $abc$27210$new_n6114 $abc$27210$new_n6113 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6124 _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6115 $abc$27210$new_n6114 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6123 _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6116 $abc$27210$new_n6115 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6122 _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6117 $abc$27210$new_n6116 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6121 _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6118 $abc$27210$new_n6117 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names $abc$27210$new_n6119 _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6118 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +11001 1 +.names _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6119 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[16] _zz_memory_MUL_LOW_4[16] _zz_memory_MUL_LOW_6[16] $abc$27210$new_n6120 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6121 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6122 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6123 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[22] _zz_memory_MUL_LOW_4[22] _zz_memory_MUL_LOW_6[22] $abc$27210$new_n6124 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[23] _zz_memory_MUL_LOW_4[23] _zz_memory_MUL_LOW_6[23] $abc$27210$new_n6125 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[24] _zz_memory_MUL_LOW_4[24] _zz_memory_MUL_LOW_6[24] $abc$27210$new_n6126 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[22] _zz_memory_MUL_LOW_4[22] _zz_memory_MUL_LOW_6[22] $abc$27210$new_n6127 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[23] _zz_memory_MUL_LOW_4[23] _zz_memory_MUL_LOW_6[23] $abc$27210$new_n6128 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[25] _zz_memory_MUL_LOW_4[25] _zz_memory_MUL_LOW_6[25] $abc$27210$new_n6129 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[26] _zz_memory_MUL_LOW_4[26] _zz_memory_MUL_LOW_6[26] $abc$27210$new_n6130 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[24] _zz_memory_MUL_LOW_4[24] _zz_memory_MUL_LOW_6[24] $abc$27210$new_n6131 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[25] _zz_memory_MUL_LOW_4[25] _zz_memory_MUL_LOW_6[25] $abc$27210$new_n6132 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[27] _zz_memory_MUL_LOW_4[27] _zz_memory_MUL_LOW_6[27] $abc$27210$new_n6133 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[28] _zz_memory_MUL_LOW_4[28] _zz_memory_MUL_LOW_6[28] $abc$27210$new_n6134 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[26] _zz_memory_MUL_LOW_4[26] _zz_memory_MUL_LOW_6[26] $abc$27210$new_n6135 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[27] _zz_memory_MUL_LOW_4[27] _zz_memory_MUL_LOW_6[27] $abc$27210$new_n6136 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[29] _zz_memory_MUL_LOW_4[29] _zz_memory_MUL_LOW_6[29] $abc$27210$new_n6137 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[30] _zz_memory_MUL_LOW_4[30] _zz_memory_MUL_LOW_6[30] $abc$27210$new_n6138 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_1[28] _zz_memory_MUL_LOW_4[28] _zz_memory_MUL_LOW_6[28] $abc$27210$new_n6139 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[29] _zz_memory_MUL_LOW_4[29] _zz_memory_MUL_LOW_6[29] $abc$27210$new_n6140 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] $abc$27210$new_n6141 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_memory_MUL_LOW_1[30] _zz_memory_MUL_LOW_4[30] _zz_memory_MUL_LOW_6[30] $abc$27210$new_n6142 +000 1 +001 1 +010 1 +100 1 +.names _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] $abc$27210$new_n6143 +001 1 +010 1 +100 1 +111 1 +.names _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] $abc$27210$new_n6144 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] $abc$27210$new_n6145 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] $abc$27210$new_n6146 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_1[31] _zz_memory_MUL_LOW_4[31] _zz_memory_MUL_LOW_6[31] _zz_memory_MUL_LOW_4[32] _zz_memory_MUL_LOW_6[32] $abc$27210$new_n6147 +01101 1 +01110 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] $abc$27210$new_n6148 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] $abc$27210$new_n6149 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] $abc$27210$new_n6150 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[33] _zz_memory_MUL_LOW_6[33] _zz_memory_MUL_LOW_4[34] _zz_memory_MUL_LOW_6[34] $abc$27210$new_n6151 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] $abc$27210$new_n6152 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] $abc$27210$new_n6153 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] $abc$27210$new_n6154 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[35] _zz_memory_MUL_LOW_6[35] _zz_memory_MUL_LOW_4[36] _zz_memory_MUL_LOW_6[36] $abc$27210$new_n6155 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] $abc$27210$new_n6156 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] $abc$27210$new_n6157 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] $abc$27210$new_n6158 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[37] _zz_memory_MUL_LOW_6[37] _zz_memory_MUL_LOW_4[38] _zz_memory_MUL_LOW_6[38] $abc$27210$new_n6159 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] $abc$27210$new_n6160 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] $abc$27210$new_n6161 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] $abc$27210$new_n6162 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[39] _zz_memory_MUL_LOW_6[39] _zz_memory_MUL_LOW_4[40] _zz_memory_MUL_LOW_6[40] $abc$27210$new_n6163 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] $abc$27210$new_n6164 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] $abc$27210$new_n6165 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] $abc$27210$new_n6166 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[41] _zz_memory_MUL_LOW_6[41] _zz_memory_MUL_LOW_4[42] _zz_memory_MUL_LOW_6[42] $abc$27210$new_n6167 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] $abc$27210$new_n6168 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] $abc$27210$new_n6169 +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] $abc$27210$new_n6170 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[43] _zz_memory_MUL_LOW_6[43] _zz_memory_MUL_LOW_4[44] _zz_memory_MUL_LOW_6[44] $abc$27210$new_n6171 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] $abc$27210$new_n6172 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] $abc$27210$new_n6173 +01 1 +10 1 +.names _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] $abc$27210$new_n6174 +11 1 +.names _zz_memory_MUL_LOW_4[45] _zz_memory_MUL_LOW_6[45] _zz_memory_MUL_LOW_4[46] _zz_memory_MUL_LOW_6[46] $abc$27210$new_n6175 +1101 1 +1110 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6176 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_6[51] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6177 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6179 $abc$27210$new_n6177 _zz_writeBack_MulPlugin_result[49] $abc$27210$auto$rtlil.cc:2693:MuxGate$21845 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_memory_MUL_LOW_4[47] _zz_memory_MUL_LOW_6[47] _zz_memory_MUL_LOW_4[48] _zz_memory_MUL_LOW_6[48] $abc$27210$new_n6101 $abc$27210$new_n6179 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11110 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6181 _zz_writeBack_MulPlugin_result[48] $abc$27210$auto$rtlil.cc:2693:MuxGate$21847 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6172 $abc$27210$new_n6173 $abc$27210$new_n6174 $abc$27210$new_n6102 $abc$27210$new_n6175 $abc$27210$new_n6181 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6183 _zz_writeBack_MulPlugin_result[47] $abc$27210$auto$rtlil.cc:2693:MuxGate$21849 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6174 $abc$27210$new_n6173 $abc$27210$new_n6175 $abc$27210$new_n6102 $abc$27210$new_n6183 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6185 _zz_writeBack_MulPlugin_result[46] $abc$27210$auto$rtlil.cc:2693:MuxGate$21851 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6168 $abc$27210$new_n6170 $abc$27210$new_n6169 $abc$27210$new_n6171 $abc$27210$new_n6103 $abc$27210$new_n6185 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6187 _zz_writeBack_MulPlugin_result[45] $abc$27210$auto$rtlil.cc:2693:MuxGate$21853 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6171 $abc$27210$new_n6170 $abc$27210$new_n6169 $abc$27210$new_n6103 $abc$27210$new_n6187 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6189 _zz_writeBack_MulPlugin_result[44] $abc$27210$auto$rtlil.cc:2693:MuxGate$21855 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6164 $abc$27210$new_n6166 $abc$27210$new_n6165 $abc$27210$new_n6167 $abc$27210$new_n6104 $abc$27210$new_n6189 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6191 _zz_writeBack_MulPlugin_result[43] $abc$27210$auto$rtlil.cc:2693:MuxGate$21857 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6167 $abc$27210$new_n6166 $abc$27210$new_n6165 $abc$27210$new_n6104 $abc$27210$new_n6191 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6193 _zz_writeBack_MulPlugin_result[42] $abc$27210$auto$rtlil.cc:2693:MuxGate$21859 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6160 $abc$27210$new_n6162 $abc$27210$new_n6161 $abc$27210$new_n6163 $abc$27210$new_n6105 $abc$27210$new_n6193 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6195 _zz_writeBack_MulPlugin_result[41] $abc$27210$auto$rtlil.cc:2693:MuxGate$21861 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6163 $abc$27210$new_n6162 $abc$27210$new_n6161 $abc$27210$new_n6105 $abc$27210$new_n6195 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6197 _zz_writeBack_MulPlugin_result[40] $abc$27210$auto$rtlil.cc:2693:MuxGate$21863 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6156 $abc$27210$new_n6158 $abc$27210$new_n6157 $abc$27210$new_n6159 $abc$27210$new_n6106 $abc$27210$new_n6197 +00001 1 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_zz_writeBack_MulPlugin_result[37] $abc$27210$auto$rtlil.cc:2693:MuxGate$21869 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6155 $abc$27210$new_n6154 $abc$27210$new_n6153 $abc$27210$new_n6107 $abc$27210$new_n6203 +0000 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6205 _zz_writeBack_MulPlugin_result[36] $abc$27210$auto$rtlil.cc:2693:MuxGate$21871 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6148 $abc$27210$new_n6150 $abc$27210$new_n6149 $abc$27210$new_n6151 $abc$27210$new_n6108 $abc$27210$new_n6205 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6207 _zz_writeBack_MulPlugin_result[35] $abc$27210$auto$rtlil.cc:2693:MuxGate$21873 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6151 $abc$27210$new_n6150 $abc$27210$new_n6149 $abc$27210$new_n6108 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$abc$27210$auto$rtlil.cc:2693:MuxGate$21879 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 $abc$27210$new_n6213 +000 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6143 $abc$27210$new_n6142 $abc$27210$new_n6110 _zz__zz_decode_RS2_2[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$21881 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6216 _zz__zz_decode_RS2_2[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$21883 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6138 $abc$27210$new_n6137 $abc$27210$new_n6139 $abc$27210$new_n6140 $abc$27210$new_n6111 $abc$27210$new_n6216 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6140 $abc$27210$new_n6139 $abc$27210$new_n6111 _zz__zz_decode_RS2_2[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$21885 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[28] $abc$27210$new_n6219 $abc$27210$auto$rtlil.cc:2693:MuxGate$21887 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6134 $abc$27210$new_n6133 $abc$27210$new_n6135 $abc$27210$new_n6136 $abc$27210$new_n6112 $abc$27210$new_n6219 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6136 $abc$27210$new_n6135 $abc$27210$new_n6112 _zz__zz_decode_RS2_2[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$21889 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[26] $abc$27210$new_n6222 $abc$27210$auto$rtlil.cc:2693:MuxGate$21891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6130 $abc$27210$new_n6129 $abc$27210$new_n6131 $abc$27210$new_n6132 $abc$27210$new_n6113 $abc$27210$new_n6222 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6132 $abc$27210$new_n6131 $abc$27210$new_n6113 _zz__zz_decode_RS2_2[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$21893 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[24] $abc$27210$new_n6225 $abc$27210$auto$rtlil.cc:2693:MuxGate$21895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6126 $abc$27210$new_n6125 $abc$27210$new_n6127 $abc$27210$new_n6128 $abc$27210$new_n6114 $abc$27210$new_n6225 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6128 $abc$27210$new_n6127 $abc$27210$new_n6114 _zz__zz_decode_RS2_2[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$21897 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[22] $abc$27210$new_n6228 $abc$27210$auto$rtlil.cc:2693:MuxGate$21899 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6124 $abc$27210$new_n6115 _zz_memory_MUL_LOW_1[21] _zz_memory_MUL_LOW_4[21] _zz_memory_MUL_LOW_6[21] $abc$27210$new_n6228 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[21] $abc$27210$new_n6230 $abc$27210$auto$rtlil.cc:2693:MuxGate$21901 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6123 $abc$27210$new_n6116 _zz_memory_MUL_LOW_1[20] _zz_memory_MUL_LOW_4[20] _zz_memory_MUL_LOW_6[20] $abc$27210$new_n6230 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[20] $abc$27210$new_n6232 $abc$27210$auto$rtlil.cc:2693:MuxGate$21903 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6122 $abc$27210$new_n6117 _zz_memory_MUL_LOW_1[19] _zz_memory_MUL_LOW_4[19] _zz_memory_MUL_LOW_6[19] $abc$27210$new_n6232 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[19] $abc$27210$new_n6234 $abc$27210$auto$rtlil.cc:2693:MuxGate$21905 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6121 $abc$27210$new_n6118 _zz_memory_MUL_LOW_1[18] _zz_memory_MUL_LOW_4[18] _zz_memory_MUL_LOW_6[18] $abc$27210$new_n6234 +00000 1 +00001 1 +00010 1 +00100 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[18] $abc$27210$new_n6236 $abc$27210$auto$rtlil.cc:2693:MuxGate$21907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6119 _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6236 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +11001 1 +11110 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[17] $abc$27210$new_n6238 $abc$27210$auto$rtlil.cc:2693:MuxGate$21909 +001 1 +011 1 +110 1 +111 1 +.names _zz_memory_MUL_LOW_1[17] _zz_memory_MUL_LOW_4[17] _zz_memory_MUL_LOW_6[17] $abc$27210$new_n6120 $abc$27210$new_n6238 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$27210$new_n4093 _zz_memory_MUL_LOW_1[16] _zz_memory_MUL_LOW_4[16] _zz_memory_MUL_LOW_6[16] _zz__zz_decode_RS2_2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$21911 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[15] _zz_memory_MUL_LOW_1[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$21913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[14] _zz_memory_MUL_LOW_1[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$21915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[13] _zz_memory_MUL_LOW_1[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$21917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[12] _zz_memory_MUL_LOW_1[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$21919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[11] _zz_memory_MUL_LOW_1[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$21921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[10] _zz_memory_MUL_LOW_1[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$21923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[9] _zz_memory_MUL_LOW_1[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$21925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[8] _zz_memory_MUL_LOW_1[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$21927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[7] _zz_memory_MUL_LOW_1[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$21929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[6] _zz_memory_MUL_LOW_1[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$21931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[5] _zz_memory_MUL_LOW_1[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$21933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[4] _zz_memory_MUL_LOW_1[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$21935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[3] _zz_memory_MUL_LOW_1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$21937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[2] _zz_memory_MUL_LOW_1[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$21939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[1] _zz_memory_MUL_LOW_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$21941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz__zz_decode_RS2_2[0] _zz_memory_MUL_LOW_1[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$21943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[63] execute_to_memory_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22005 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[62] execute_to_memory_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22007 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[61] execute_to_memory_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22009 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[60] execute_to_memory_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22011 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[59] execute_to_memory_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22013 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[58] execute_to_memory_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22015 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[57] execute_to_memory_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22017 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[56] execute_to_memory_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22019 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[55] execute_to_memory_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22021 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[54] execute_to_memory_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22023 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[53] execute_to_memory_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22025 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[52] execute_to_memory_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22027 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[51] execute_to_memory_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22029 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[50] execute_to_memory_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22031 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[49] execute_to_memory_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22033 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[48] execute_to_memory_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22035 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[47] execute_to_memory_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22037 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[46] execute_to_memory_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22039 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[45] execute_to_memory_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22041 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[44] execute_to_memory_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22043 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[43] execute_to_memory_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22045 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[42] execute_to_memory_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22047 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[41] execute_to_memory_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22049 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[40] execute_to_memory_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22051 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[39] execute_to_memory_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22053 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[38] execute_to_memory_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22055 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[37] execute_to_memory_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22057 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[36] execute_to_memory_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22059 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[35] execute_to_memory_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22061 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[34] execute_to_memory_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22063 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[33] execute_to_memory_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22065 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_MulPlugin_result_1[32] execute_to_memory_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22067 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[31] execute_MUL_HH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22071 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[30] execute_MUL_HH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22073 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[29] execute_MUL_HH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22075 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[28] execute_MUL_HH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22077 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[27] execute_MUL_HH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22079 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[26] execute_MUL_HH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22081 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[25] execute_MUL_HH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22083 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[24] execute_MUL_HH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22085 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[23] execute_MUL_HH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22087 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[22] execute_MUL_HH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22089 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[21] execute_MUL_HH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22091 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[20] execute_MUL_HH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22093 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[19] execute_MUL_HH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22095 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[18] execute_MUL_HH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22097 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[17] execute_MUL_HH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22099 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[16] execute_MUL_HH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22101 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[15] execute_MUL_HH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22103 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[14] execute_MUL_HH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22105 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[13] execute_MUL_HH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22107 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[12] execute_MUL_HH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22109 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[11] execute_MUL_HH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22111 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[10] execute_MUL_HH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22113 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[9] execute_MUL_HH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22115 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[8] execute_MUL_HH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22117 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[7] execute_MUL_HH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22119 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[6] execute_MUL_HH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22121 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[5] execute_MUL_HH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22123 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[4] execute_MUL_HH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22125 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[3] execute_MUL_HH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22127 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[2] execute_MUL_HH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22129 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[1] execute_MUL_HH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22131 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MUL_HH[0] execute_MUL_HH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22133 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[48] execute_MUL_HL[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22135 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[47] execute_MUL_HL[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22137 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[46] execute_MUL_HL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22139 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[45] execute_MUL_HL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22141 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[44] execute_MUL_HL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22143 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[43] execute_MUL_HL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22145 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[42] execute_MUL_HL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22147 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[41] execute_MUL_HL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22149 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[40] execute_MUL_HL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22151 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[39] execute_MUL_HL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22153 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[38] execute_MUL_HL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22155 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[37] execute_MUL_HL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22157 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[36] execute_MUL_HL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22159 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[35] execute_MUL_HL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22161 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[34] execute_MUL_HL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22163 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[33] execute_MUL_HL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22165 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[32] execute_MUL_HL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22167 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[31] execute_MUL_HL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22169 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[30] execute_MUL_HL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22171 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[29] execute_MUL_HL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22173 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[28] execute_MUL_HL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22175 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[27] execute_MUL_HL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22177 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[26] execute_MUL_HL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22179 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[25] execute_MUL_HL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22181 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[24] execute_MUL_HL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22183 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[23] execute_MUL_HL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22185 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[22] execute_MUL_HL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22187 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[21] execute_MUL_HL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22189 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[20] execute_MUL_HL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22191 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[19] execute_MUL_HL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22193 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[18] execute_MUL_HL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22195 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[17] execute_MUL_HL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22197 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[16] execute_MUL_HL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22199 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[48] execute_MUL_LH[32] $abc$27210$auto$rtlil.cc:2693:MuxGate$22201 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[47] execute_MUL_LH[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$22203 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[46] execute_MUL_LH[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22205 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[45] execute_MUL_LH[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22207 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[44] execute_MUL_LH[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22209 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[43] execute_MUL_LH[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22211 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[42] execute_MUL_LH[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22213 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[41] execute_MUL_LH[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22215 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[40] execute_MUL_LH[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22217 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[39] execute_MUL_LH[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22219 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[38] execute_MUL_LH[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22221 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[37] execute_MUL_LH[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22223 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[36] execute_MUL_LH[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22225 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[35] execute_MUL_LH[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22227 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[34] execute_MUL_LH[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22229 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[33] execute_MUL_LH[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22231 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[32] execute_MUL_LH[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22233 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[31] execute_MUL_LH[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22235 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[30] execute_MUL_LH[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22237 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[29] execute_MUL_LH[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22239 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[28] execute_MUL_LH[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22241 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[27] execute_MUL_LH[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22243 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[26] execute_MUL_LH[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22245 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[25] execute_MUL_LH[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22247 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[24] execute_MUL_LH[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22249 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[23] execute_MUL_LH[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22251 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[22] execute_MUL_LH[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22253 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[21] execute_MUL_LH[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22255 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[20] execute_MUL_LH[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22257 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[19] execute_MUL_LH[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22259 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[18] execute_MUL_LH[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22261 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[17] execute_MUL_LH[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22263 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[16] execute_MUL_LH[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22265 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[30] execute_MUL_LL[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22267 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[29] execute_MUL_LL[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22269 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[28] execute_MUL_LL[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22271 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[27] execute_MUL_LL[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22273 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[26] execute_MUL_LL[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22275 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[25] execute_MUL_LL[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22277 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[24] execute_MUL_LL[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22279 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[23] execute_MUL_LL[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22281 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[22] execute_MUL_LL[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22283 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[21] execute_MUL_LL[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22285 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[20] execute_MUL_LL[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22287 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[19] execute_MUL_LL[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22289 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[18] execute_MUL_LL[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22291 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[17] execute_MUL_LL[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22293 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[16] execute_MUL_LL[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22295 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[15] execute_MUL_LL[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22297 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[14] execute_MUL_LL[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22299 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[13] execute_MUL_LL[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22301 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[12] execute_MUL_LL[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22303 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[11] execute_MUL_LL[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22305 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[10] execute_MUL_LL[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22307 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[9] execute_MUL_LL[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22309 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[8] execute_MUL_LL[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22311 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[7] execute_MUL_LL[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22313 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[6] execute_MUL_LL[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22315 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[5] execute_MUL_LL[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22317 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[4] execute_MUL_LL[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22319 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[3] execute_MUL_LL[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22321 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[2] execute_MUL_LL[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22323 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[1] execute_MUL_LL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22325 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[0] execute_MUL_LL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22327 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[1] $abc$27210$new_n6418 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22329 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6419 $abc$27210$new_n6421 $abc$27210$new_n6418 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6420 $abc$27210$new_n6421 $abc$27210$new_n6419 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6421 $abc$27210$new_n6424 $abc$27210$new_n6420 +010 1 +011 1 +100 1 +110 1 +.names _zz_execute_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[0] $abc$27210$new_n6422 $abc$27210$new_n6421 +110 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5407 $abc$27210$new_n5843 $abc$27210$new_n6422 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n6423 +10 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6422 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6424 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n6426 _zz_execute_to_memory_PC[2] _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] $abc$27210$new_n6425 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] execute_RS2[2] _zz__zz_execute_BranchPlugin_branch_src2_2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$new_n6426 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6428 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6427 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[3] _zz__zz_execute_BranchPlugin_branch_src2_2[2] _zz_execute_to_memory_PC[3] $abc$27210$new_n6428 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n6430 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6429 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names _zz_execute_SRC2_CTRL[0] _zz_execute_SRC2_CTRL[1] execute_RS2[4] _zz__zz_execute_BranchPlugin_branch_src2_2[3] _zz_execute_to_memory_PC[4] $abc$27210$new_n6430 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[2] $abc$27210$new_n6432 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22331 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6433 $abc$27210$new_n6421 $abc$27210$new_n6432 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6434 $abc$27210$new_n6421 $abc$27210$new_n6433 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6435 $abc$27210$new_n6437 $abc$27210$new_n6421 $abc$27210$new_n6434 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6436 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6435 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6436 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6422 $abc$27210$new_n6437 +10 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[3] $abc$27210$new_n6439 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22333 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6440 $abc$27210$new_n6421 $abc$27210$new_n6439 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6441 $abc$27210$new_n6421 $abc$27210$new_n6440 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6424 $abc$27210$new_n6442 $abc$27210$new_n6441 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6436 $abc$27210$new_n6443 $abc$27210$new_n6442 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5392 $abc$27210$new_n5417 $abc$27210$new_n6443 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[4] $abc$27210$new_n6445 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22335 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6446 $abc$27210$new_n6421 $abc$27210$new_n6445 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6421 $abc$27210$new_n6447 $abc$27210$new_n6437 $abc$27210$new_n6093 $abc$27210$new_n6446 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6435 $abc$27210$new_n6448 $abc$27210$new_n6447 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6443 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6448 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[5] $abc$27210$new_n6450 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22337 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6451 $abc$27210$new_n6421 $abc$27210$new_n6450 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6452 $abc$27210$new_n6420 $abc$27210$new_n6451 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6453 $abc$27210$new_n6442 $abc$27210$new_n6452 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6454 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6453 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5378 $abc$27210$new_n5427 $abc$27210$new_n6454 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[6] $abc$27210$new_n6456 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22339 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6457 $abc$27210$new_n6421 $abc$27210$new_n6456 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6458 $abc$27210$new_n6434 $abc$27210$new_n6457 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6459 $abc$27210$new_n6448 $abc$27210$new_n6458 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6454 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6459 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6429 _zz_decode_RS2_3[7] $abc$27210$new_n6461 $abc$27210$new_n6421 $abc$27210$auto$rtlil.cc:2693:MuxGate$22341 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6462 $abc$27210$new_n6421 $abc$27210$new_n6461 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6463 $abc$27210$new_n6441 $abc$27210$new_n6462 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6453 $abc$27210$new_n6464 $abc$27210$new_n6463 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6465 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6464 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6465 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6467 DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22343 +000 1 +001 1 +011 1 +.names $abc$27210$new_n6468 $abc$27210$new_n6427 $abc$27210$new_n6429 $abc$27210$new_n6469 $abc$27210$new_n6473 $abc$27210$new_n6467 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6421 $abc$27210$new_n6429 $abc$27210$new_n6468 +000 1 +001 1 +011 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6470 $abc$27210$new_n6447 $abc$27210$new_n6469 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6459 $abc$27210$new_n6471 $abc$27210$new_n6470 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6465 $abc$27210$new_n6472 $abc$27210$new_n6471 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5362 $abc$27210$new_n5442 $abc$27210$new_n6472 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n6421 $abc$27210$new_n6425 $abc$27210$new_n6437 $abc$27210$new_n6093 $abc$27210$new_n6473 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6475 DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22345 +000 1 +001 1 +011 1 +.names $abc$27210$new_n6468 $abc$27210$new_n6427 $abc$27210$new_n6429 $abc$27210$new_n6476 $abc$27210$new_n6419 $abc$27210$new_n6475 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6452 $abc$27210$new_n6477 $abc$27210$new_n6476 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6464 $abc$27210$new_n6478 $abc$27210$new_n6477 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6472 $abc$27210$new_n5357 $abc$27210$new_n5447 $abc$27210$new_n6478 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 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$abc$27210$auto$rtlil.cc:2693:MuxGate$22373 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6461 $abc$27210$new_n6510 $abc$27210$new_n6555 $abc$27210$new_n6554 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6556 $abc$27210$new_n6534 $abc$27210$new_n6555 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6546 $abc$27210$new_n6557 $abc$27210$new_n6556 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6552 $abc$27210$new_n6558 $abc$27210$new_n6557 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5362 $abc$27210$new_n5442 $abc$27210$new_n6558 +000 1 +001 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[24] $abc$27210$new_n6560 $abc$27210$auto$rtlil.cc:2693:MuxGate$22375 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6561 $abc$27210$new_n6469 $abc$27210$new_n6473 $abc$27210$new_n6560 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6425 $abc$27210$new_n6515 $abc$27210$new_n6539 $abc$27210$new_n6562 $abc$27210$new_n6561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6551 $abc$27210$new_n6563 $abc$27210$new_n6562 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6558 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[25] $abc$27210$new_n6565 $abc$27210$auto$rtlil.cc:2693:MuxGate$22377 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6566 $abc$27210$new_n6476 $abc$27210$new_n6419 $abc$27210$new_n6565 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6425 $abc$27210$new_n6521 $abc$27210$new_n6545 $abc$27210$new_n6567 $abc$27210$new_n6566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6557 $abc$27210$new_n6568 $abc$27210$new_n6567 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6569 $abc$27210$new_n5370 $abc$27210$new_n5437 $abc$27210$new_n6568 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5373 $abc$27210$new_n5432 $abc$27210$new_n6569 +000 1 +001 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[26] $abc$27210$new_n6571 $abc$27210$auto$rtlil.cc:2693:MuxGate$22379 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6572 $abc$27210$new_n6481 $abc$27210$new_n6433 $abc$27210$new_n6571 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6527 $abc$27210$new_n6573 $abc$27210$new_n6572 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6550 $abc$27210$new_n6563 $abc$27210$new_n6574 $abc$27210$new_n6573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6569 $abc$27210$new_n6575 $abc$27210$new_n6574 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5378 $abc$27210$new_n5427 $abc$27210$new_n6575 +000 1 +001 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[27] $abc$27210$new_n6577 $abc$27210$auto$rtlil.cc:2693:MuxGate$22381 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6578 $abc$27210$new_n6487 $abc$27210$new_n6440 $abc$27210$new_n6577 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6579 $abc$27210$new_n6533 $abc$27210$new_n6578 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6556 $abc$27210$new_n6568 $abc$27210$new_n6580 $abc$27210$new_n6579 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6575 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6580 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[28] $abc$27210$new_n6582 $abc$27210$auto$rtlil.cc:2693:MuxGate$22383 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6492 $abc$27210$new_n6538 $abc$27210$new_n6583 $abc$27210$new_n6582 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6562 $abc$27210$new_n6574 $abc$27210$new_n6584 $abc$27210$new_n6583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6585 $abc$27210$new_n5385 $abc$27210$new_n5422 $abc$27210$new_n6584 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n5392 $abc$27210$new_n5417 $abc$27210$new_n6585 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[29] $abc$27210$new_n6587 $abc$27210$auto$rtlil.cc:2693:MuxGate$22385 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6588 $abc$27210$new_n6451 $abc$27210$new_n6498 $abc$27210$new_n6587 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6544 $abc$27210$new_n6589 $abc$27210$new_n6588 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6567 $abc$27210$new_n6580 $abc$27210$new_n6590 $abc$27210$new_n6589 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n6585 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6590 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[30] $abc$27210$new_n6592 $abc$27210$auto$rtlil.cc:2693:MuxGate$22387 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6593 $abc$27210$new_n6457 $abc$27210$new_n6504 $abc$27210$new_n6592 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6549 $abc$27210$new_n6594 $abc$27210$new_n6593 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6595 $abc$27210$new_n6563 $abc$27210$new_n6574 $abc$27210$new_n6594 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6584 $abc$27210$new_n6597 $abc$27210$new_n6596 $abc$27210$new_n6595 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1100 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6596 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n6423 $abc$27210$new_n6090 $abc$27210$new_n5397 $abc$27210$new_n5412 $abc$27210$new_n6597 +0000 1 +0001 1 +1001 1 +1011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_RS2_3[31] $abc$27210$new_n6599 $abc$27210$auto$rtlil.cc:2693:MuxGate$22389 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6429 $abc$27210$new_n6427 $abc$27210$new_n6600 $abc$27210$new_n6462 $abc$27210$new_n6510 $abc$27210$new_n6599 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6427 $abc$27210$new_n6555 $abc$27210$new_n6601 $abc$27210$new_n6600 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n6425 $abc$27210$new_n6093 $abc$27210$new_n6602 $abc$27210$new_n6568 $abc$27210$new_n6580 $abc$27210$new_n6601 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6093 $abc$27210$new_n6590 $abc$27210$new_n6604 $abc$27210$new_n6603 $abc$27210$new_n6602 +0000 1 +0001 1 +0010 1 +0011 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6090 $abc$27210$new_n6423 $abc$27210$new_n5407 $abc$27210$new_n5843 $abc$27210$new_n6603 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n6423 $abc$27210$new_n6090 $abc$27210$new_n5402 $abc$27210$new_n5953 $abc$27210$new_n6604 +0000 1 +0001 1 +1000 1 +1010 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[30] $abc$27210$new_n6606 $abc$27210$auto$rtlil.cc:2693:MuxGate$22391 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n6607 memory_DivPlugin_div_result[30] $abc$27210$new_n6606 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_memory_SHIFT_CTRL[1] _zz_memory_SHIFT_CTRL[0] _zz_decode_RS2_3[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] _zz_decode_RS2_3[30] $abc$27210$new_n6607 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[29] $abc$27210$new_n6609 $abc$27210$auto$rtlil.cc:2693:MuxGate$22393 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6610 memory_DivPlugin_div_result[29] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] execute_to_memory_IS_DIV $abc$27210$new_n6609 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6611 _zz_decode_RS2_3[2] $abc$27210$new_n6610 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] _zz_decode_RS2_3[29] $abc$27210$new_n6611 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$new_n6613 $abc$27210$auto$rtlil.cc:2693:MuxGate$22395 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6614 memory_DivPlugin_div_result[28] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] execute_to_memory_IS_DIV $abc$27210$new_n6613 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6615 _zz_decode_RS2_3[3] $abc$27210$new_n6614 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] _zz_decode_RS2_3[28] $abc$27210$new_n6615 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$new_n6617 $abc$27210$auto$rtlil.cc:2693:MuxGate$22397 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6618 memory_DivPlugin_div_result[27] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] execute_to_memory_IS_DIV $abc$27210$new_n6617 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6619 _zz_decode_RS2_3[4] $abc$27210$new_n6618 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] _zz_decode_RS2_3[27] $abc$27210$new_n6619 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[26] $abc$27210$new_n6621 $abc$27210$auto$rtlil.cc:2693:MuxGate$22399 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6622 memory_DivPlugin_div_result[26] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] execute_to_memory_IS_DIV $abc$27210$new_n6621 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6623 _zz_decode_RS2_3[5] $abc$27210$new_n6622 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] _zz_decode_RS2_3[26] $abc$27210$new_n6623 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[25] $abc$27210$new_n6625 $abc$27210$auto$rtlil.cc:2693:MuxGate$22401 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6626 memory_DivPlugin_div_result[25] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] execute_to_memory_IS_DIV $abc$27210$new_n6625 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6627 _zz_decode_RS2_3[6] $abc$27210$new_n6626 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] _zz_decode_RS2_3[25] $abc$27210$new_n6627 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[24] $abc$27210$new_n6629 $abc$27210$auto$rtlil.cc:2693:MuxGate$22403 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6630 memory_DivPlugin_div_result[24] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] execute_to_memory_IS_DIV $abc$27210$new_n6629 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6631 _zz_decode_RS2_3[7] $abc$27210$new_n6630 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] _zz_decode_RS2_3[24] $abc$27210$new_n6631 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[23] $abc$27210$new_n6633 $abc$27210$auto$rtlil.cc:2693:MuxGate$22405 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6634 memory_DivPlugin_div_result[23] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] execute_to_memory_IS_DIV $abc$27210$new_n6633 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6635 _zz_decode_RS2_3[8] $abc$27210$new_n6634 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] _zz_decode_RS2_3[23] $abc$27210$new_n6635 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$new_n6637 $abc$27210$auto$rtlil.cc:2693:MuxGate$22407 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6638 memory_DivPlugin_div_result[22] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] execute_to_memory_IS_DIV $abc$27210$new_n6637 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6639 _zz_decode_RS2_3[9] $abc$27210$new_n6638 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] _zz_decode_RS2_3[22] $abc$27210$new_n6639 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[21] $abc$27210$new_n6641 $abc$27210$auto$rtlil.cc:2693:MuxGate$22409 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6642 memory_DivPlugin_div_result[21] execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n6641 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6643 _zz_decode_RS2_3[10] $abc$27210$new_n6642 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] _zz_decode_RS2_3[21] $abc$27210$new_n6643 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$new_n6645 $abc$27210$auto$rtlil.cc:2693:MuxGate$22411 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6646 memory_DivPlugin_div_result[20] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] execute_to_memory_IS_DIV $abc$27210$new_n6645 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6647 _zz_decode_RS2_3[11] $abc$27210$new_n6646 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] _zz_decode_RS2_3[20] $abc$27210$new_n6647 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$new_n6649 $abc$27210$auto$rtlil.cc:2693:MuxGate$22413 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6650 memory_DivPlugin_div_result[19] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] execute_to_memory_IS_DIV $abc$27210$new_n6649 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6651 _zz_decode_RS2_3[12] $abc$27210$new_n6650 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] _zz_decode_RS2_3[19] $abc$27210$new_n6651 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[18] $abc$27210$new_n6653 $abc$27210$auto$rtlil.cc:2693:MuxGate$22415 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6654 memory_DivPlugin_div_result[18] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] execute_to_memory_IS_DIV $abc$27210$new_n6653 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6655 _zz_decode_RS2_3[13] $abc$27210$new_n6654 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] _zz_decode_RS2_3[18] $abc$27210$new_n6655 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[17] $abc$27210$new_n6657 $abc$27210$auto$rtlil.cc:2693:MuxGate$22417 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6658 memory_DivPlugin_div_result[17] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] execute_to_memory_IS_DIV $abc$27210$new_n6657 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6659 _zz_decode_RS2_3[14] $abc$27210$new_n6658 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] _zz_decode_RS2_3[17] $abc$27210$new_n6659 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[16] $abc$27210$new_n6661 $abc$27210$auto$rtlil.cc:2693:MuxGate$22419 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6662 memory_DivPlugin_div_result[16] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] execute_to_memory_IS_DIV $abc$27210$new_n6661 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6663 _zz_decode_RS2_3[15] $abc$27210$new_n6662 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] _zz_decode_RS2_3[16] $abc$27210$new_n6663 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[15] $abc$27210$new_n6665 $abc$27210$auto$rtlil.cc:2693:MuxGate$22421 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6666 memory_DivPlugin_div_result[15] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] execute_to_memory_IS_DIV $abc$27210$new_n6665 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6667 _zz_decode_RS2_3[16] $abc$27210$new_n6666 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] _zz_decode_RS2_3[15] $abc$27210$new_n6667 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n6669 $abc$27210$auto$rtlil.cc:2693:MuxGate$22423 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6670 memory_DivPlugin_div_result[14] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] execute_to_memory_IS_DIV $abc$27210$new_n6669 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6671 _zz_decode_RS2_3[17] $abc$27210$new_n6670 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] _zz_decode_RS2_3[14] $abc$27210$new_n6671 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[13] $abc$27210$new_n6673 $abc$27210$auto$rtlil.cc:2693:MuxGate$22425 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6674 memory_DivPlugin_div_result[13] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] execute_to_memory_IS_DIV $abc$27210$new_n6673 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6675 _zz_decode_RS2_3[18] $abc$27210$new_n6674 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] _zz_decode_RS2_3[13] $abc$27210$new_n6675 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$new_n6677 $abc$27210$auto$rtlil.cc:2693:MuxGate$22427 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6678 memory_DivPlugin_div_result[12] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] execute_to_memory_IS_DIV $abc$27210$new_n6677 +00000 1 +00001 1 +00100 1 +00101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6679 _zz_decode_RS2_3[19] $abc$27210$new_n6678 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] _zz_decode_RS2_3[12] $abc$27210$new_n6679 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[11] $abc$27210$new_n6681 $abc$27210$auto$rtlil.cc:2693:MuxGate$22429 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6682 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] memory_DivPlugin_div_result[11] execute_to_memory_IS_DIV $abc$27210$new_n6681 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6683 _zz_decode_RS2_3[20] $abc$27210$new_n6682 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] _zz_decode_RS2_3[11] $abc$27210$new_n6683 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n6685 $abc$27210$auto$rtlil.cc:2693:MuxGate$22431 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6686 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] memory_DivPlugin_div_result[10] execute_to_memory_IS_DIV $abc$27210$new_n6685 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6687 _zz_decode_RS2_3[21] $abc$27210$new_n6686 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] _zz_decode_RS2_3[10] $abc$27210$new_n6687 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$new_n6689 $abc$27210$auto$rtlil.cc:2693:MuxGate$22433 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6690 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] memory_DivPlugin_div_result[9] execute_to_memory_IS_DIV $abc$27210$new_n6689 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6691 _zz_decode_RS2_3[22] $abc$27210$new_n6690 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] _zz_decode_RS2_3[9] $abc$27210$new_n6691 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[8] $abc$27210$new_n6693 $abc$27210$auto$rtlil.cc:2693:MuxGate$22435 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6694 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] memory_DivPlugin_div_result[8] execute_to_memory_IS_DIV $abc$27210$new_n6693 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6695 _zz_decode_RS2_3[23] $abc$27210$new_n6694 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] _zz_decode_RS2_3[8] $abc$27210$new_n6695 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[7] $abc$27210$new_n6697 $abc$27210$auto$rtlil.cc:2693:MuxGate$22437 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6698 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] memory_DivPlugin_div_result[7] execute_to_memory_IS_DIV $abc$27210$new_n6697 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6699 _zz_decode_RS2_3[24] $abc$27210$new_n6698 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] _zz_decode_RS2_3[7] $abc$27210$new_n6699 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[6] $abc$27210$new_n6701 $abc$27210$auto$rtlil.cc:2693:MuxGate$22439 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6702 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] memory_DivPlugin_div_result[6] execute_to_memory_IS_DIV $abc$27210$new_n6701 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6703 _zz_decode_RS2_3[25] $abc$27210$new_n6702 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] _zz_decode_RS2_3[6] $abc$27210$new_n6703 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n6705 $abc$27210$auto$rtlil.cc:2693:MuxGate$22441 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6706 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] memory_DivPlugin_div_result[5] execute_to_memory_IS_DIV $abc$27210$new_n6705 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6707 _zz_decode_RS2_3[26] $abc$27210$new_n6706 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] _zz_decode_RS2_3[5] $abc$27210$new_n6707 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$new_n6709 $abc$27210$auto$rtlil.cc:2693:MuxGate$22443 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6710 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] memory_DivPlugin_div_result[4] execute_to_memory_IS_DIV $abc$27210$new_n6709 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6711 _zz_decode_RS2_3[27] $abc$27210$new_n6710 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] _zz_decode_RS2_3[4] $abc$27210$new_n6711 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[3] $abc$27210$new_n6713 $abc$27210$auto$rtlil.cc:2693:MuxGate$22445 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6714 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] memory_DivPlugin_div_result[3] execute_to_memory_IS_DIV $abc$27210$new_n6713 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6715 _zz_decode_RS2_3[28] $abc$27210$new_n6714 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] _zz_decode_RS2_3[3] $abc$27210$new_n6715 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[2] $abc$27210$new_n6717 $abc$27210$auto$rtlil.cc:2693:MuxGate$22447 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6718 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] memory_DivPlugin_div_result[2] execute_to_memory_IS_DIV $abc$27210$new_n6717 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6719 _zz_decode_RS2_3[29] $abc$27210$new_n6718 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] _zz_decode_RS2_3[2] $abc$27210$new_n6719 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 _zz_writeBack_DBusCachedPlugin_rspShifted_3 $abc$27210$new_n6721 $abc$27210$auto$rtlil.cc:2693:MuxGate$22449 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6722 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] memory_DivPlugin_div_result[1] execute_to_memory_IS_DIV $abc$27210$new_n6721 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6723 _zz_decode_RS2_3[30] $abc$27210$new_n6722 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] _zz_decode_RS2_3[1] $abc$27210$new_n6723 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[0] $abc$27210$new_n6725 $abc$27210$auto$rtlil.cc:2693:MuxGate$22451 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n6726 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] memory_DivPlugin_div_result[0] execute_to_memory_IS_DIV $abc$27210$new_n6725 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n6727 _zz_decode_RS2_3[31] $abc$27210$new_n6726 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] _zz_decode_RS2_3[0] $abc$27210$new_n6727 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8130 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22453 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6799 $abc$27210$new_n5412 $abc$27210$new_n6797 $abc$27210$new_n6733 $abc$27210$new_n6732 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5427 $abc$27210$new_n6795 $abc$27210$new_n5422 $abc$27210$new_n6793 $abc$27210$new_n6734 $abc$27210$new_n6733 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n5432 $abc$27210$new_n6789 $abc$27210$new_n6735 $abc$27210$new_n6734 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5447 $abc$27210$new_n6787 $abc$27210$new_n5442 $abc$27210$new_n6785 $abc$27210$new_n6736 $abc$27210$new_n6735 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n5948 $abc$27210$new_n6781 $abc$27210$new_n6737 $abc$27210$new_n6736 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5312 $abc$27210$new_n6779 $abc$27210$new_n5307 $abc$27210$new_n6777 $abc$27210$new_n6738 $abc$27210$new_n6737 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$27210$new_n5317 $abc$27210$new_n5322 $abc$27210$new_n6775 $abc$27210$new_n6773 $abc$27210$new_n6739 $abc$27210$new_n6738 +00000 1 +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n5327 $abc$27210$new_n6768 $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n6770 $abc$27210$new_n6739 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n5337 $abc$27210$new_n6764 $abc$27210$new_n6741 $abc$27210$new_n6740 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n6760 $abc$27210$new_n5352 $abc$27210$new_n5348 $abc$27210$new_n6742 $abc$27210$new_n6741 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$27210$new_n5362 $abc$27210$new_n6758 $abc$27210$new_n6756 $abc$27210$new_n5357 $abc$27210$new_n6743 $abc$27210$new_n6742 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names $abc$27210$new_n6752 $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n5370 $abc$27210$new_n6744 $abc$27210$new_n6743 +00000 1 +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6750 $abc$27210$new_n5378 $abc$27210$new_n6745 $abc$27210$new_n6744 +00100 1 +00101 1 +01001 1 +01100 1 +01101 1 +01111 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6429 $abc$27210$new_n6745 +01 1 +10 1 +.names $abc$27210$new_n5392 $abc$27210$new_n6749 $abc$27210$new_n5397 $abc$27210$new_n6748 $abc$27210$new_n6747 $abc$27210$new_n6746 +00011 1 +01001 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6428 _zz_execute_SRC2_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6747 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6426 _zz_execute_SRC2_CTRL[1] _zz_execute_to_memory_PC[2] _zz_execute_SRC2_CTRL[0] $abc$27210$new_n6748 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6093 $abc$27210$new_n6090 $abc$27210$new_n5402 $abc$27210$new_n5407 $abc$27210$new_n6749 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6751 $abc$27210$new_n6750 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[4] execute_RS2[5] _zz_execute_to_memory_PC[5] $abc$27210$new_n6751 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6753 $abc$27210$new_n6752 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[6] execute_RS2[7] _zz_execute_to_memory_PC[7] $abc$27210$new_n6753 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6755 $abc$27210$new_n6754 +00 1 +11 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[5] execute_RS2[6] _zz_execute_to_memory_PC[6] $abc$27210$new_n6755 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6757 $abc$27210$new_n6756 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[8] execute_RS2[9] _zz_execute_to_memory_PC[9] $abc$27210$new_n6757 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6759 $abc$27210$new_n6758 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[7] execute_RS2[8] _zz_execute_to_memory_PC[8] $abc$27210$new_n6759 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6761 $abc$27210$new_n6760 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[11] _zz_execute_to_memory_PC[11] $abc$27210$new_n6761 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6763 $abc$27210$new_n6762 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_2[9] execute_RS2[10] _zz_execute_to_memory_PC[10] $abc$27210$new_n6763 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6765 $abc$27210$new_n6764 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[13] _zz_execute_to_memory_PC[13] $abc$27210$new_n6765 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6767 $abc$27210$new_n6766 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[12] _zz_execute_to_memory_PC[12] $abc$27210$new_n6767 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6769 $abc$27210$new_n6768 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[15] _zz_execute_to_memory_PC[15] $abc$27210$new_n6769 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n6770 +000 1 +110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[14] _zz_execute_to_memory_PC[14] $abc$27210$new_n6771 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n6772 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6774 $abc$27210$new_n6773 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[17] _zz_execute_to_memory_PC[17] $abc$27210$new_n6774 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6776 $abc$27210$new_n6775 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[16] _zz_execute_to_memory_PC[16] $abc$27210$new_n6776 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6778 $abc$27210$new_n6777 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[19] _zz_execute_to_memory_PC[19] $abc$27210$new_n6778 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6780 $abc$27210$new_n6779 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[18] _zz_execute_to_memory_PC[18] $abc$27210$new_n6780 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6782 $abc$27210$new_n6781 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[21] _zz_execute_to_memory_PC[21] $abc$27210$new_n6782 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6784 $abc$27210$new_n6783 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[20] _zz_execute_to_memory_PC[20] $abc$27210$new_n6784 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6786 $abc$27210$new_n6785 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[23] _zz_execute_to_memory_PC[23] $abc$27210$new_n6786 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6788 $abc$27210$new_n6787 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[22] _zz_execute_to_memory_PC[22] $abc$27210$new_n6788 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6790 $abc$27210$new_n6789 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[25] _zz_execute_to_memory_PC[25] $abc$27210$new_n6790 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6792 $abc$27210$new_n6791 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[24] _zz_execute_to_memory_PC[24] $abc$27210$new_n6792 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6794 $abc$27210$new_n6793 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n6794 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6796 $abc$27210$new_n6795 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[26] _zz_execute_to_memory_PC[26] $abc$27210$new_n6796 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6798 $abc$27210$new_n6797 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[29] _zz_execute_to_memory_PC[29] $abc$27210$new_n6798 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6800 $abc$27210$new_n6799 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[28] _zz_execute_to_memory_PC[28] $abc$27210$new_n6800 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 execute_RS2[30] _zz_execute_to_memory_PC[30] $abc$27210$new_n6802 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$27210$new_n6803 +10 1 +.names $abc$27210$new_n4264 _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$27210$new_n6805 +000 1 +001 1 +011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[8] MmuPlugin_satp_ppn[18] $abc$27210$new_n6806 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8133 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22455 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6799 $abc$27210$new_n6733 $abc$27210$new_n6812 +010 1 +100 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6798 $abc$27210$new_n5412 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6813 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8136 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22457 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6800 $abc$27210$new_n5417 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6819 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6821 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22459 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6825 $abc$27210$new_n6826 $abc$27210$new_n6805 $abc$27210$new_n6822 $abc$27210$new_n6821 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6824 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6823 $abc$27210$new_n5422 $abc$27210$new_n6822 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5422 $abc$27210$new_n6793 $abc$27210$new_n5427 $abc$27210$new_n6795 $abc$27210$new_n6734 $abc$27210$new_n6823 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6794 $abc$27210$new_n5422 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6824 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n4264 $abc$27210$new_n5420 $abc$27210$new_n6825 +10 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[5] MmuPlugin_satp_ppn[15] $abc$27210$new_n6826 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8139 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22461 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4264 $abc$27210$new_n5425 $abc$27210$new_n6832 +10 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[4] MmuPlugin_satp_ppn[14] $abc$27210$new_n6833 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6835 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22463 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6836 $abc$27210$new_n6840 $abc$27210$new_n4264 $abc$27210$new_n5430 $abc$27210$new_n6835 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6837 $abc$27210$new_n6839 $abc$27210$new_n6836 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5432 $abc$27210$new_n6803 $abc$27210$new_n6789 $abc$27210$new_n6838 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6837 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +10010 1 +10100 1 +.names $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n6735 $abc$27210$new_n6838 +010 1 +100 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6790 $abc$27210$new_n5432 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6839 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[3] MmuPlugin_satp_ppn[13] $abc$27210$new_n6840 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6842 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22465 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6843 $abc$27210$new_n6846 $abc$27210$new_n4264 $abc$27210$new_n5435 $abc$27210$new_n6842 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6844 $abc$27210$new_n6845 $abc$27210$new_n5437 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6843 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5437 $abc$27210$new_n6791 $abc$27210$new_n6735 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6844 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6792 $abc$27210$new_n5437 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6845 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[2] MmuPlugin_satp_ppn[12] $abc$27210$new_n6846 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6848 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22467 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6849 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN1[1] MmuPlugin_satp_ppn[11] $abc$27210$new_n6848 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6850 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5440 $abc$27210$new_n6849 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6852 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6851 $abc$27210$new_n5442 $abc$27210$new_n6850 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5442 $abc$27210$new_n6785 $abc$27210$new_n5447 $abc$27210$new_n6787 $abc$27210$new_n6736 $abc$27210$new_n6851 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6786 $abc$27210$new_n5442 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6852 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6854 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22469 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n8142 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN1[0] MmuPlugin_satp_ppn[10] $abc$27210$new_n6854 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6860 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22471 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6861 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[9] MmuPlugin_satp_ppn[9] $abc$27210$new_n6860 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6862 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5946 $abc$27210$new_n6861 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6864 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6863 $abc$27210$new_n5948 $abc$27210$new_n6862 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5948 $abc$27210$new_n6781 $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n6737 $abc$27210$new_n6863 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6782 $abc$27210$new_n5948 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6864 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6866 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22473 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6867 $abc$27210$new_n6870 $abc$27210$new_n4264 $abc$27210$new_n5300 $abc$27210$new_n6866 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6869 $abc$27210$new_n6803 $abc$27210$new_n6868 $abc$27210$new_n6867 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5302 $abc$27210$new_n6783 $abc$27210$new_n6737 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6868 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6784 $abc$27210$new_n5302 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6869 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[8] MmuPlugin_satp_ppn[8] $abc$27210$new_n6870 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6872 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22475 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6873 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[7] MmuPlugin_satp_ppn[7] $abc$27210$new_n6872 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6874 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5305 $abc$27210$new_n6873 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6876 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6875 $abc$27210$new_n5307 $abc$27210$new_n6874 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5307 $abc$27210$new_n6777 $abc$27210$new_n5312 $abc$27210$new_n6779 $abc$27210$new_n6738 $abc$27210$new_n6875 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6778 $abc$27210$new_n5307 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6876 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6878 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22477 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6879 $abc$27210$new_n6882 $abc$27210$new_n4264 $abc$27210$new_n5310 $abc$27210$new_n6878 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6880 $abc$27210$new_n6881 $abc$27210$new_n6879 +101 1 +110 1 +111 1 +.names $abc$27210$new_n5312 $abc$27210$new_n6803 $abc$27210$new_n6779 $abc$27210$new_n6738 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6880 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10110 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6780 $abc$27210$new_n5312 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6881 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[6] MmuPlugin_satp_ppn[6] $abc$27210$new_n6882 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6884 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22479 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6885 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[5] MmuPlugin_satp_ppn[5] $abc$27210$new_n6884 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6886 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5315 $abc$27210$new_n6885 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6888 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6887 $abc$27210$new_n5317 $abc$27210$new_n6886 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5317 $abc$27210$new_n6773 $abc$27210$new_n5322 $abc$27210$new_n6775 $abc$27210$new_n6739 $abc$27210$new_n6887 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6774 $abc$27210$new_n5317 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6888 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8145 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22481 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6776 $abc$27210$new_n5322 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6894 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6896 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22483 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6897 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[3] MmuPlugin_satp_ppn[3] $abc$27210$new_n6896 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6898 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5325 $abc$27210$new_n6897 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6900 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6899 $abc$27210$new_n5327 $abc$27210$new_n6898 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5327 $abc$27210$new_n6768 $abc$27210$new_n6770 $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n6899 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6769 $abc$27210$new_n5327 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6900 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8149 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22485 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[2] MmuPlugin_satp_ppn[2] $abc$27210$new_n6907 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6909 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22487 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n6910 $abc$27210$new_n5838 $abc$27210$new_n4327 MmuPlugin_shared_pteBuffer_PPN0[1] MmuPlugin_satp_ppn[1] $abc$27210$new_n6909 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6911 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5335 $abc$27210$new_n6910 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$27210$new_n6913 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n6912 $abc$27210$new_n5337 $abc$27210$new_n6911 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n5337 $abc$27210$new_n6764 $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n6741 $abc$27210$new_n6912 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6765 $abc$27210$new_n5337 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6913 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] $abc$27210$new_n6915 $abc$27210$auto$rtlil.cc:2693:MuxGate$22489 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6916 $abc$27210$new_n6919 $abc$27210$new_n4264 $abc$27210$new_n5340 $abc$27210$new_n6915 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6918 $abc$27210$new_n6803 $abc$27210$new_n6917 $abc$27210$new_n6916 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5342 $abc$27210$new_n6766 $abc$27210$new_n6741 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6917 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n6767 $abc$27210$new_n5342 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6918 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN0[0] MmuPlugin_satp_ppn[0] $abc$27210$new_n6919 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] $abc$27210$new_n6921 $abc$27210$auto$rtlil.cc:2693:MuxGate$22491 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6922 $abc$27210$new_n6926 $abc$27210$new_n5345 $abc$27210$new_n4264 $abc$27210$new_n6921 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6925 $abc$27210$new_n6923 $abc$27210$new_n6803 $abc$27210$new_n6922 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n5348 $abc$27210$new_n6760 $abc$27210$new_n6924 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6923 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n5352 $abc$27210$new_n6742 $abc$27210$new_n6924 +000 1 +100 1 +101 1 +110 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5348 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6761 $abc$27210$new_n6925 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11101 1 +11110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[9] MmuPlugin_shared_vpn_1[9] $abc$27210$new_n6926 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] $abc$27210$new_n8152 $abc$27210$auto$rtlil.cc:2693:MuxGate$22493 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6762 $abc$27210$new_n5352 $abc$27210$new_n6742 $abc$27210$new_n6931 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[8] MmuPlugin_shared_vpn_1[8] $abc$27210$new_n6933 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] $abc$27210$new_n6935 $abc$27210$auto$rtlil.cc:2693:MuxGate$22495 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6936 $abc$27210$new_n6940 $abc$27210$new_n5358 $abc$27210$new_n4264 $abc$27210$new_n6935 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6937 $abc$27210$new_n6939 $abc$27210$new_n6936 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$27210$new_n5357 $abc$27210$new_n6756 $abc$27210$new_n6938 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6937 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n6758 $abc$27210$new_n5362 $abc$27210$new_n6743 $abc$27210$new_n6938 +001 1 +100 1 +101 1 +111 1 +.names $abc$27210$new_n5357 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6757 $abc$27210$new_n6939 +0000 1 +0010 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[7] MmuPlugin_shared_vpn_1[7] $abc$27210$new_n6940 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] $abc$27210$new_n8155 $abc$27210$auto$rtlil.cc:2693:MuxGate$22497 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6758 $abc$27210$new_n5362 $abc$27210$new_n6743 $abc$27210$new_n6945 +001 1 +010 1 +100 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[6] MmuPlugin_shared_vpn_1[6] $abc$27210$new_n6947 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] $abc$27210$new_n6949 $abc$27210$auto$rtlil.cc:2693:MuxGate$22499 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6950 $abc$27210$new_n6954 $abc$27210$new_n5367 $abc$27210$new_n4264 $abc$27210$new_n6949 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6951 $abc$27210$new_n6953 $abc$27210$new_n6950 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n5370 $abc$27210$new_n6752 $abc$27210$new_n6952 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6951 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n6744 $abc$27210$new_n6952 +000 1 +001 1 +011 1 +101 1 +.names $abc$27210$new_n5370 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6753 $abc$27210$new_n6953 +0000 1 +0010 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[5] MmuPlugin_shared_vpn_1[5] $abc$27210$new_n6954 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] $abc$27210$new_n8158 $abc$27210$auto$rtlil.cc:2693:MuxGate$22501 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n6754 $abc$27210$new_n5373 $abc$27210$new_n6744 $abc$27210$new_n6959 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[4] MmuPlugin_shared_vpn_1[4] $abc$27210$new_n6961 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] $abc$27210$new_n6963 $abc$27210$auto$rtlil.cc:2693:MuxGate$22503 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6964 $abc$27210$new_n6968 $abc$27210$new_n5379 $abc$27210$new_n4264 $abc$27210$new_n6963 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6967 $abc$27210$new_n6965 $abc$27210$new_n6803 $abc$27210$new_n6964 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n5378 $abc$27210$new_n6750 $abc$27210$new_n6966 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6965 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6745 $abc$27210$new_n6966 +011 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5378 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6751 $abc$27210$new_n6967 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11101 1 +11110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[3] MmuPlugin_shared_vpn_1[3] $abc$27210$new_n6968 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] $abc$27210$new_n8161 $abc$27210$auto$rtlil.cc:2693:MuxGate$22505 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n5385 $abc$27210$new_n6746 $abc$27210$new_n6745 $abc$27210$new_n6973 +000 1 +011 1 +101 1 +110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[2] MmuPlugin_shared_vpn_1[2] $abc$27210$new_n6975 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] $abc$27210$new_n6977 $abc$27210$auto$rtlil.cc:2693:MuxGate$22507 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6978 $abc$27210$new_n6982 $abc$27210$new_n5388 $abc$27210$new_n4264 $abc$27210$new_n6977 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6979 $abc$27210$new_n6981 $abc$27210$new_n6978 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$27210$new_n5392 $abc$27210$new_n6747 $abc$27210$new_n6980 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6979 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n6749 $abc$27210$new_n5397 $abc$27210$new_n6748 $abc$27210$new_n6980 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n5392 $abc$27210$new_n6427 $abc$27210$new_n6981 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[1] MmuPlugin_shared_vpn_1[1] $abc$27210$new_n6982 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] $abc$27210$new_n6984 $abc$27210$auto$rtlil.cc:2693:MuxGate$22509 +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6985 $abc$27210$new_n6988 $abc$27210$new_n5395 $abc$27210$new_n4264 $abc$27210$new_n6984 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6986 $abc$27210$new_n6987 $abc$27210$new_n6985 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$27210$new_n5397 $abc$27210$new_n6749 $abc$27210$new_n6748 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6986 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names $abc$27210$new_n5397 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6425 $abc$27210$new_n6987 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_vpn_0[0] MmuPlugin_shared_vpn_1[0] $abc$27210$new_n6988 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$new_n6990 $abc$27210$auto$rtlil.cc:2693:MuxGate$22511 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6991 $abc$27210$new_n4264 $abc$27210$new_n5400 $abc$27210$new_n6990 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 $abc$27210$new_n6091 $abc$27210$new_n6992 $abc$27210$new_n6991 +1000 1 +1001 1 +1100 1 +1110 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6093 $abc$27210$new_n5402 $abc$27210$new_n6992 +0000 1 +0011 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8163 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22513 +010 1 +011 1 +101 1 +111 1 +.names decode_to_execute_SRC_LESS_UNSIGNED $abc$27210$new_n6999 $abc$27210$new_n5843 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6997 $abc$27210$new_n6996 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +01111 1 +10000 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n6998 $abc$27210$new_n5953 $abc$27210$new_n6802 $abc$27210$new_n6732 $abc$27210$new_n6997 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6999 $abc$27210$new_n5843 $abc$27210$new_n6998 +01 1 +10 1 +.names _zz_execute_SRC2_CTRL[1] _zz_execute_SRC2_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz_execute_to_memory_PC[31] execute_RS2[31] $abc$27210$new_n6999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6090 $abc$27210$new_n5407 $abc$27210$new_n7001 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[30] execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$22515 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[29] execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22517 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[28] execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22519 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[27] execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$22521 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[26] execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$22523 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[25] execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$22525 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[24] execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$22527 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[23] execute_to_memory_MEMORY_STORE_DATA_RF[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22529 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[22] execute_to_memory_MEMORY_STORE_DATA_RF[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22531 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[21] execute_to_memory_MEMORY_STORE_DATA_RF[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22533 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[20] execute_to_memory_MEMORY_STORE_DATA_RF[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22535 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[19] execute_to_memory_MEMORY_STORE_DATA_RF[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22537 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[18] execute_to_memory_MEMORY_STORE_DATA_RF[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22539 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[17] execute_to_memory_MEMORY_STORE_DATA_RF[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22541 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[16] execute_to_memory_MEMORY_STORE_DATA_RF[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22543 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[15] execute_to_memory_MEMORY_STORE_DATA_RF[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22545 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[14] execute_to_memory_MEMORY_STORE_DATA_RF[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22547 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[13] execute_to_memory_MEMORY_STORE_DATA_RF[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22549 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[12] execute_to_memory_MEMORY_STORE_DATA_RF[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[11] execute_to_memory_MEMORY_STORE_DATA_RF[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22553 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[10] execute_to_memory_MEMORY_STORE_DATA_RF[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22555 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[9] execute_to_memory_MEMORY_STORE_DATA_RF[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[8] execute_to_memory_MEMORY_STORE_DATA_RF[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22559 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[7] execute_to_memory_MEMORY_STORE_DATA_RF[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22561 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[6] execute_to_memory_MEMORY_STORE_DATA_RF[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22563 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[5] execute_to_memory_MEMORY_STORE_DATA_RF[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[4] execute_to_memory_MEMORY_STORE_DATA_RF[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22567 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[3] execute_to_memory_MEMORY_STORE_DATA_RF[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22569 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[2] execute_to_memory_MEMORY_STORE_DATA_RF[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[1] execute_to_memory_MEMORY_STORE_DATA_RF[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22573 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[0] execute_to_memory_MEMORY_STORE_DATA_RF[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22575 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[30] $abc$27210$new_n7034 $abc$27210$auto$rtlil.cc:2693:MuxGate$22577 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[30] execute_RS2[6] execute_RS2[14] $abc$27210$new_n7034 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[29] $abc$27210$new_n7036 $abc$27210$auto$rtlil.cc:2693:MuxGate$22579 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[29] execute_RS2[5] execute_RS2[13] $abc$27210$new_n7036 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[28] $abc$27210$new_n7038 $abc$27210$auto$rtlil.cc:2693:MuxGate$22581 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[28] execute_RS2[4] execute_RS2[12] $abc$27210$new_n7038 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[27] $abc$27210$new_n7040 $abc$27210$auto$rtlil.cc:2693:MuxGate$22583 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[27] execute_RS2[3] execute_RS2[11] $abc$27210$new_n7040 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[26] $abc$27210$new_n7042 $abc$27210$auto$rtlil.cc:2693:MuxGate$22585 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[26] execute_RS2[2] execute_RS2[10] $abc$27210$new_n7042 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[25] $abc$27210$new_n7044 $abc$27210$auto$rtlil.cc:2693:MuxGate$22587 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[25] execute_RS2[1] execute_RS2[9] $abc$27210$new_n7044 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[24] $abc$27210$new_n7046 $abc$27210$auto$rtlil.cc:2693:MuxGate$22589 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[24] execute_RS2[0] execute_RS2[8] $abc$27210$new_n7046 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[23] execute_RS2[7] execute_RS2[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$22591 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[22] execute_RS2[6] execute_RS2[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$22593 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[21] execute_RS2[5] execute_RS2[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$22595 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[20] execute_RS2[4] execute_RS2[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$22597 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[19] execute_RS2[3] execute_RS2[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$22599 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[18] execute_RS2[2] execute_RS2[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22601 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[17] execute_RS2[1] execute_RS2[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22603 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck switch_Misc_l241_1 execute_to_memory_MEMORY_STORE_DATA_RF[16] execute_RS2[0] execute_RS2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22605 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[15] execute_RS2[7] execute_RS2[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22607 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n7056 +00 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[14] execute_RS2[6] execute_RS2[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22609 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[13] execute_RS2[5] execute_RS2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22611 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[12] execute_RS2[4] execute_RS2[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22613 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[11] execute_RS2[3] execute_RS2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22615 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[10] execute_RS2[2] execute_RS2[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22617 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[9] execute_RS2[1] execute_RS2[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22619 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7056 execute_to_memory_MEMORY_STORE_DATA_RF[8] execute_RS2[0] execute_RS2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22621 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[7] execute_RS2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22623 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[6] execute_RS2[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22625 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[5] execute_RS2[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22627 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[4] execute_RS2[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22629 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[3] execute_RS2[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22631 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[2] execute_RS2[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22633 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[1] execute_RS2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22635 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[0] execute_RS2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22637 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[30] $abc$27210$new_n7073 $abc$27210$new_n8130 $abc$27210$auto$rtlil.cc:2693:MuxGate$22639 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6606 HazardSimplePlugin_writeBackWrites_payload_data[30] $abc$27210$new_n7075 $abc$27210$new_n7073 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_to_memory_REGFILE_WRITE_VALID execute_to_memory_BYPASSABLE_MEMORY_STAGE memory_arbitration_isValid $abc$27210$new_n8023 $abc$27210$new_n7074 +1111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[30] _zz_RegFilePlugin_regFile_port1[30] $abc$27210$new_n7075 +000 1 +010 1 +100 1 +101 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7080 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsValid $abc$27210$new_n7086 +11 1 +.names decode_to_execute_REGFILE_WRITE_VALID decode_to_execute_BYPASSABLE_EXECUTE_STAGE execute_arbitration_isValid $abc$27210$new_n4310 $abc$27210$new_n7087 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[29] $abc$27210$new_n8133 $abc$27210$new_n7089 $abc$27210$auto$rtlil.cc:2693:MuxGate$22641 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6609 HazardSimplePlugin_writeBackWrites_payload_data[29] $abc$27210$new_n7090 $abc$27210$new_n7089 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[29] _zz_RegFilePlugin_regFile_port1[29] $abc$27210$new_n7090 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[28] $abc$27210$new_n8136 $abc$27210$new_n7092 $abc$27210$auto$rtlil.cc:2693:MuxGate$22643 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6613 HazardSimplePlugin_writeBackWrites_payload_data[28] $abc$27210$new_n7093 $abc$27210$new_n7092 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[28] _zz_RegFilePlugin_regFile_port1[28] $abc$27210$new_n7093 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[27] $abc$27210$new_n6821 $abc$27210$new_n7095 $abc$27210$auto$rtlil.cc:2693:MuxGate$22645 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6617 HazardSimplePlugin_writeBackWrites_payload_data[27] $abc$27210$new_n7096 $abc$27210$new_n7095 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[27] _zz_RegFilePlugin_regFile_port1[27] $abc$27210$new_n7096 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[26] $abc$27210$new_n8139 $abc$27210$new_n7098 $abc$27210$auto$rtlil.cc:2693:MuxGate$22647 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6621 HazardSimplePlugin_writeBackWrites_payload_data[26] $abc$27210$new_n7099 $abc$27210$new_n7098 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[26] _zz_RegFilePlugin_regFile_port1[26] $abc$27210$new_n7099 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[25] $abc$27210$new_n6835 $abc$27210$new_n7101 $abc$27210$auto$rtlil.cc:2693:MuxGate$22649 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6625 HazardSimplePlugin_writeBackWrites_payload_data[25] $abc$27210$new_n7102 $abc$27210$new_n7101 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[25] _zz_RegFilePlugin_regFile_port1[25] $abc$27210$new_n7102 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[24] $abc$27210$new_n6842 $abc$27210$new_n7104 $abc$27210$auto$rtlil.cc:2693:MuxGate$22651 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6629 HazardSimplePlugin_writeBackWrites_payload_data[24] $abc$27210$new_n7105 $abc$27210$new_n7104 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[24] _zz_RegFilePlugin_regFile_port1[24] $abc$27210$new_n7105 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[23] $abc$27210$new_n6848 $abc$27210$new_n7107 $abc$27210$auto$rtlil.cc:2693:MuxGate$22653 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6633 HazardSimplePlugin_writeBackWrites_payload_data[23] $abc$27210$new_n7108 $abc$27210$new_n7107 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[23] _zz_RegFilePlugin_regFile_port1[23] $abc$27210$new_n7108 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[22] $abc$27210$new_n6854 $abc$27210$new_n7110 $abc$27210$auto$rtlil.cc:2693:MuxGate$22655 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6637 HazardSimplePlugin_writeBackWrites_payload_data[22] $abc$27210$new_n7111 $abc$27210$new_n7110 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[22] _zz_RegFilePlugin_regFile_port1[22] $abc$27210$new_n7111 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[21] $abc$27210$new_n6860 $abc$27210$new_n7113 $abc$27210$auto$rtlil.cc:2693:MuxGate$22657 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6641 HazardSimplePlugin_writeBackWrites_payload_data[21] $abc$27210$new_n7114 $abc$27210$new_n7113 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[21] _zz_RegFilePlugin_regFile_port1[21] $abc$27210$new_n7114 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[20] $abc$27210$new_n6866 $abc$27210$new_n7116 $abc$27210$auto$rtlil.cc:2693:MuxGate$22659 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 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+01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[19] _zz_RegFilePlugin_regFile_port1[19] $abc$27210$new_n7120 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[18] $abc$27210$new_n6878 $abc$27210$new_n7122 $abc$27210$auto$rtlil.cc:2693:MuxGate$22663 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6653 HazardSimplePlugin_writeBackWrites_payload_data[18] $abc$27210$new_n7123 $abc$27210$new_n7122 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[18] _zz_RegFilePlugin_regFile_port1[18] $abc$27210$new_n7123 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[17] $abc$27210$new_n6884 $abc$27210$new_n7125 $abc$27210$auto$rtlil.cc:2693:MuxGate$22665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6657 HazardSimplePlugin_writeBackWrites_payload_data[17] $abc$27210$new_n7126 $abc$27210$new_n7125 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[17] _zz_RegFilePlugin_regFile_port1[17] $abc$27210$new_n7126 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[16] $abc$27210$new_n8145 $abc$27210$new_n7128 $abc$27210$auto$rtlil.cc:2693:MuxGate$22667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6661 HazardSimplePlugin_writeBackWrites_payload_data[16] $abc$27210$new_n7129 $abc$27210$new_n7128 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[16] _zz_RegFilePlugin_regFile_port1[16] $abc$27210$new_n7129 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[15] $abc$27210$new_n6896 $abc$27210$new_n7131 $abc$27210$auto$rtlil.cc:2693:MuxGate$22669 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6665 HazardSimplePlugin_writeBackWrites_payload_data[15] $abc$27210$new_n7132 $abc$27210$new_n7131 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[15] _zz_RegFilePlugin_regFile_port1[15] $abc$27210$new_n7132 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[14] $abc$27210$new_n8149 $abc$27210$new_n7134 $abc$27210$auto$rtlil.cc:2693:MuxGate$22671 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6669 HazardSimplePlugin_writeBackWrites_payload_data[14] $abc$27210$new_n7135 $abc$27210$new_n7134 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[14] _zz_RegFilePlugin_regFile_port1[14] $abc$27210$new_n7135 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[13] $abc$27210$new_n6909 $abc$27210$new_n7137 $abc$27210$auto$rtlil.cc:2693:MuxGate$22673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n6673 HazardSimplePlugin_writeBackWrites_payload_data[13] $abc$27210$new_n7138 $abc$27210$new_n7137 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[13] _zz_RegFilePlugin_regFile_port1[13] $abc$27210$new_n7138 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 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$abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[12] $abc$27210$new_n6915 $abc$27210$new_n7242 $abc$27210$auto$rtlil.cc:2693:MuxGate$22737 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6677 HazardSimplePlugin_writeBackWrites_payload_data[12] $abc$27210$new_n7243 $abc$27210$new_n7242 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[12] _zz_RegFilePlugin_regFile_port0[12] $abc$27210$new_n7243 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[11] $abc$27210$new_n6921 $abc$27210$new_n7245 $abc$27210$auto$rtlil.cc:2693:MuxGate$22739 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 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$abc$27210$new_n7186 $abc$27210$new_n6701 HazardSimplePlugin_writeBackWrites_payload_data[6] $abc$27210$new_n7261 $abc$27210$new_n7260 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[6] _zz_RegFilePlugin_regFile_port0[6] $abc$27210$new_n7261 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[5] $abc$27210$new_n6963 $abc$27210$new_n7263 $abc$27210$auto$rtlil.cc:2693:MuxGate$22751 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6705 HazardSimplePlugin_writeBackWrites_payload_data[5] $abc$27210$new_n7264 $abc$27210$new_n7263 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[5] _zz_RegFilePlugin_regFile_port0[5] $abc$27210$new_n7264 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[4] $abc$27210$new_n8161 $abc$27210$new_n7266 $abc$27210$auto$rtlil.cc:2693:MuxGate$22753 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6709 HazardSimplePlugin_writeBackWrites_payload_data[4] $abc$27210$new_n7267 $abc$27210$new_n7266 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[4] _zz_RegFilePlugin_regFile_port0[4] $abc$27210$new_n7267 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7269 execute_RS1[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22755 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n7189 $abc$27210$new_n7185 $abc$27210$new_n6977 $abc$27210$new_n7270 $abc$27210$new_n6713 $abc$27210$new_n7269 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7186 $abc$27210$new_n7181 HazardSimplePlugin_writeBackWrites_payload_data[3] HazardSimplePlugin_writeBackBuffer_payload_data[3] _zz_RegFilePlugin_regFile_port0[3] $abc$27210$new_n7270 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[2] $abc$27210$new_n7272 $abc$27210$new_n6984 $abc$27210$auto$rtlil.cc:2693:MuxGate$22757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7273 $abc$27210$new_n6717 $abc$27210$new_n7272 +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n7186 $abc$27210$new_n7181 HazardSimplePlugin_writeBackWrites_payload_data[2] HazardSimplePlugin_writeBackBuffer_payload_data[2] _zz_RegFilePlugin_regFile_port0[2] $abc$27210$new_n7273 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[1] $abc$27210$new_n6990 $abc$27210$new_n7275 $abc$27210$auto$rtlil.cc:2693:MuxGate$22759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6721 HazardSimplePlugin_writeBackWrites_payload_data[1] $abc$27210$new_n7276 $abc$27210$new_n7275 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[1] _zz_RegFilePlugin_regFile_port0[1] $abc$27210$new_n7276 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[0] $abc$27210$new_n8163 $abc$27210$new_n7278 $abc$27210$auto$rtlil.cc:2693:MuxGate$22761 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n6725 HazardSimplePlugin_writeBackWrites_payload_data[0] $abc$27210$new_n7279 $abc$27210$new_n7278 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[0] _zz_RegFilePlugin_regFile_port0[0] $abc$27210$new_n7279 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_BRANCH_CTRL[0] _zz_execute_BRANCH_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22763 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_BRANCH_CTRL[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22765 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22767 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7284 _zz_execute_SHIFT_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22769 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7285 $abc$27210$new_n4713 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n7284 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n7286 $abc$27210$new_n7285 +111 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n7286 +00 1 +.names $abc$27210$new_n4259 _zz_execute_ALU_BITWISE_CTRL[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$auto$rtlil.cc:2693:MuxGate$22771 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4304 _zz_execute_SRC2_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22773 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7290 _zz_execute_ALU_CTRL[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22775 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7290 +1100 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7292 _zz_execute_SRC1_CTRL[0] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n4303 $abc$27210$new_n7292 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_line_history[0] decode_to_execute_PREDICTION_CONTEXT_line_history[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22779 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_line_history_2[0] decode_to_execute_PREDICTION_CONTEXT_line_history[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22781 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[29] execute_to_memory_INSTRUCTION[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$22785 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[28] execute_to_memory_INSTRUCTION[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$22787 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[14] execute_to_memory_INSTRUCTION[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22815 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[13] execute_to_memory_INSTRUCTION[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22817 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_payload_address[12] execute_to_memory_INSTRUCTION[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$22819 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[4] execute_to_memory_INSTRUCTION[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22821 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[3] execute_to_memory_INSTRUCTION[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$22823 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[2] execute_to_memory_INSTRUCTION[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22825 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[1] execute_to_memory_INSTRUCTION[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22827 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_payload_address[0] execute_to_memory_INSTRUCTION[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22829 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22847 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22849 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22877 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$22879 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[12] _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22881 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22883 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22885 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22887 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22889 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_INSTRUCTION[7] _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$auto$rtlil.cc:2693:MuxGate$22891 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] _zz__zz_execute_BranchPlugin_branch_src2_2[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$22907 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] _zz__zz_execute_BranchPlugin_branch_src2_2[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$22909 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] _zz__zz_execute_BranchPlugin_branch_src2_2[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$22911 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] _zz__zz_execute_BranchPlugin_branch_src2_2[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$22913 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] _zz__zz_execute_BranchPlugin_branch_src2_2[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$22915 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] _zz__zz_execute_BranchPlugin_branch_src2_2[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$22917 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] _zz__zz_execute_BranchPlugin_branch_src2_2[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22919 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] _zz__zz_execute_BranchPlugin_branch_src2_2[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22921 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] _zz__zz_execute_BranchPlugin_branch_src2_2[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22923 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] _zz__zz_execute_BranchPlugin_branch_src2_2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22925 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] _zz_execute_BranchPlugin_branch_src2_8 $abc$27210$auto$rtlil.cc:2693:MuxGate$22927 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] _zz__zz_execute_BranchPlugin_branch_src2_2[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$22929 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] _zz__zz_execute_BranchPlugin_branch_src2_2[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$22931 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] _zz__zz_execute_BranchPlugin_branch_src2_2[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$22933 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] _zz__zz_execute_BranchPlugin_branch_src2_2[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$22935 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$22937 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$22939 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] switch_Misc_l241_1 $abc$27210$auto$rtlil.cc:2693:MuxGate$22941 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$22943 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$22945 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$22947 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$22949 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$22951 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 _zz_execute_BranchPlugin_branch_src2_10 $abc$27210$auto$rtlil.cc:2693:MuxGate$22953 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7410 $abc$27210$new_n7399 $abc$27210$new_n7340 BranchPlugin_branchExceptionPort_payload_badAddr[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$23147 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 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_zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 switch_Misc_l241_1 $abc$27210$new_n7385 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[11] $abc$27210$new_n7386 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n7358 execute_RS1[15] _zz_execute_to_memory_PC[15] $abc$27210$new_n7387 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[14] _zz_execute_to_memory_PC[14] $abc$27210$new_n7388 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[14] $abc$27210$new_n7389 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names _zz_execute_BRANCH_CTRL[1] decode_to_execute_PREDICTION_HAD_BRANCHED2 _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_2[13] $abc$27210$new_n7390 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n7358 execute_RS1[17] _zz_execute_to_memory_PC[17] $abc$27210$new_n7391 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 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_zz_execute_BranchPlugin_branch_src2 $abc$27210$new_n7357 $abc$27210$new_n7399 +10 1 +.names $abc$27210$new_n7358 execute_RS1[22] _zz_execute_to_memory_PC[22] $abc$27210$new_n7400 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[21] _zz_execute_to_memory_PC[21] $abc$27210$new_n7401 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[20] _zz_execute_to_memory_PC[20] $abc$27210$new_n7402 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[25] _zz_execute_to_memory_PC[25] $abc$27210$new_n7403 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[24] _zz_execute_to_memory_PC[24] $abc$27210$new_n7404 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[23] _zz_execute_to_memory_PC[23] $abc$27210$new_n7405 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7399 $abc$27210$new_n7358 execute_RS1[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n7406 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$27210$new_n7358 $abc$27210$new_n7399 execute_RS1[27] _zz_execute_to_memory_PC[27] $abc$27210$new_n7407 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$27210$new_n7358 execute_RS1[28] _zz_execute_to_memory_PC[28] $abc$27210$new_n7408 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[29] _zz_execute_to_memory_PC[29] $abc$27210$new_n7409 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n7358 execute_RS1[30] _zz_execute_to_memory_PC[30] $abc$27210$new_n7410 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7409 $abc$27210$new_n7399 $abc$27210$new_n7341 BranchPlugin_branchExceptionPort_payload_badAddr[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23149 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7408 $abc$27210$new_n7399 $abc$27210$new_n7413 BranchPlugin_branchExceptionPort_payload_badAddr[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23151 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7406 $abc$27210$new_n7342 $abc$27210$new_n7407 $abc$27210$new_n7413 +001 1 +010 1 +011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7342 $abc$27210$new_n7407 $abc$27210$new_n7406 BranchPlugin_branchExceptionPort_payload_badAddr[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23153 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7416 BranchPlugin_branchExceptionPort_payload_badAddr[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23155 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7399 $abc$27210$new_n7343 $abc$27210$new_n7358 _zz_execute_to_memory_PC[26] execute_RS1[26] $abc$27210$new_n7416 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7418 BranchPlugin_branchExceptionPort_payload_badAddr[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23157 +000 1 +001 1 +101 1 +111 1 +.names $abc$27210$new_n7405 $abc$27210$new_n7403 $abc$27210$new_n7404 $abc$27210$new_n7399 $abc$27210$new_n7344 $abc$27210$new_n7418 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7420 BranchPlugin_branchExceptionPort_payload_badAddr[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23159 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7404 $abc$27210$new_n7405 $abc$27210$new_n7399 $abc$27210$new_n7344 $abc$27210$new_n7420 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7405 $abc$27210$new_n7399 $abc$27210$new_n7344 BranchPlugin_branchExceptionPort_payload_badAddr[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23161 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7400 $abc$27210$new_n7399 $abc$27210$new_n7423 BranchPlugin_branchExceptionPort_payload_badAddr[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23163 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7401 $abc$27210$new_n7399 $abc$27210$new_n7424 $abc$27210$new_n7423 +001 1 +100 1 +101 1 +111 1 +.names $abc$27210$new_n7402 $abc$27210$new_n7399 $abc$27210$new_n7345 $abc$27210$new_n7424 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7401 $abc$27210$new_n7399 $abc$27210$new_n7424 BranchPlugin_branchExceptionPort_payload_badAddr[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23165 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7402 $abc$27210$new_n7399 $abc$27210$new_n7345 BranchPlugin_branchExceptionPort_payload_badAddr[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23167 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7397 $abc$27210$new_n7395 $abc$27210$new_n7428 BranchPlugin_branchExceptionPort_payload_badAddr[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23169 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7398 $abc$27210$new_n7396 $abc$27210$new_n7346 $abc$27210$new_n7428 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7398 $abc$27210$new_n7396 $abc$27210$new_n7346 BranchPlugin_branchExceptionPort_payload_badAddr[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23171 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7431 BranchPlugin_branchExceptionPort_payload_badAddr[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23173 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n7393 $abc$27210$new_n7391 $abc$27210$new_n7394 $abc$27210$new_n7392 $abc$27210$new_n7347 $abc$27210$new_n7431 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7394 $abc$27210$new_n7392 $abc$27210$new_n7347 BranchPlugin_branchExceptionPort_payload_badAddr[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$23175 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7389 $abc$27210$new_n7387 $abc$27210$new_n7434 BranchPlugin_branchExceptionPort_payload_badAddr[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23177 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7390 $abc$27210$new_n7388 $abc$27210$new_n7348 $abc$27210$new_n7434 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7390 $abc$27210$new_n7388 $abc$27210$new_n7348 BranchPlugin_branchExceptionPort_payload_badAddr[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23179 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7385 $abc$27210$new_n7383 $abc$27210$new_n7437 BranchPlugin_branchExceptionPort_payload_badAddr[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$23181 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7386 $abc$27210$new_n7384 $abc$27210$new_n7349 $abc$27210$new_n7437 +011 1 +101 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7386 $abc$27210$new_n7384 $abc$27210$new_n7349 BranchPlugin_branchExceptionPort_payload_badAddr[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23183 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7380 $abc$27210$new_n7440 BranchPlugin_branchExceptionPort_payload_badAddr[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23185 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7382 $abc$27210$new_n7381 $abc$27210$new_n7350 $abc$27210$new_n7440 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7382 $abc$27210$new_n7381 $abc$27210$new_n7350 BranchPlugin_branchExceptionPort_payload_badAddr[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$23187 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7375 $abc$27210$new_n7373 $abc$27210$new_n7443 BranchPlugin_branchExceptionPort_payload_badAddr[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23189 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7376 $abc$27210$new_n7374 $abc$27210$new_n7351 $abc$27210$new_n7443 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7376 $abc$27210$new_n7374 $abc$27210$new_n7351 BranchPlugin_branchExceptionPort_payload_badAddr[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$23191 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7446 $abc$27210$new_n7370 $abc$27210$new_n7368 BranchPlugin_branchExceptionPort_payload_badAddr[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$23193 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7372 $abc$27210$new_n7371 $abc$27210$new_n7352 $abc$27210$new_n7446 +001 1 +100 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7372 $abc$27210$new_n7371 $abc$27210$new_n7352 BranchPlugin_branchExceptionPort_payload_badAddr[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23195 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7353 $abc$27210$new_n7367 $abc$27210$new_n7365 BranchPlugin_branchExceptionPort_payload_badAddr[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23197 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7364 $abc$27210$new_n7363 $abc$27210$new_n7354 BranchPlugin_branchExceptionPort_payload_badAddr[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23199 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7451 $abc$27210$new_n7355 BranchPlugin_branchExceptionPort_payload_badAddr[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23201 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7362 $abc$27210$new_n7358 _zz_execute_to_memory_PC[3] execute_RS1[3] $abc$27210$new_n7451 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[2] $abc$27210$new_n7453 $abc$27210$auto$rtlil.cc:2693:MuxGate$23203 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7359 $abc$27210$new_n7356 $abc$27210$new_n7358 _zz_execute_to_memory_PC[2] execute_RS1[2] $abc$27210$new_n7453 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[1] $abc$27210$new_n7455 $abc$27210$auto$rtlil.cc:2693:MuxGate$23205 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7358 $abc$27210$new_n7361 _zz__zz_execute_BranchPlugin_branch_src2_2[0] execute_RS1[1] $abc$27210$new_n7360 $abc$27210$new_n7455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names $abc$27210$new_n7457 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23331 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[30] $abc$27210$new_n7458 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[29] $abc$27210$new_n7457 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names $abc$27210$new_n7459 execute_RS2[28] $abc$27210$new_n7458 +10 1 +.names $abc$27210$new_n7460 execute_RS2[27] $abc$27210$new_n7459 +10 1 +.names $abc$27210$new_n7461 execute_RS2[26] $abc$27210$new_n7460 +10 1 +.names $abc$27210$new_n7462 execute_RS2[25] $abc$27210$new_n7461 +10 1 +.names $abc$27210$new_n7463 execute_RS2[24] $abc$27210$new_n7462 +10 1 +.names $abc$27210$new_n7464 execute_RS2[23] $abc$27210$new_n7463 +10 1 +.names $abc$27210$new_n7465 execute_RS2[22] $abc$27210$new_n7464 +10 1 +.names $abc$27210$new_n7466 execute_RS2[21] $abc$27210$new_n7465 +10 1 +.names $abc$27210$new_n7467 execute_RS2[20] $abc$27210$new_n7466 +10 1 +.names $abc$27210$new_n7468 execute_RS2[19] $abc$27210$new_n7467 +10 1 +.names $abc$27210$new_n7469 execute_RS2[18] $abc$27210$new_n7468 +10 1 +.names $abc$27210$new_n7470 execute_RS2[17] $abc$27210$new_n7469 +10 1 +.names $abc$27210$new_n7471 execute_RS2[15] execute_RS2[16] $abc$27210$new_n7470 +100 1 +.names $abc$27210$new_n7472 execute_RS2[14] $abc$27210$new_n7471 +10 1 +.names $abc$27210$new_n7473 execute_RS2[12] execute_RS2[13] $abc$27210$new_n7472 +100 1 +.names $abc$27210$new_n7474 execute_RS2[9] execute_RS2[10] execute_RS2[11] $abc$27210$new_n7473 +1000 1 +.names $abc$27210$new_n7475 execute_RS2[8] execute_RS2[7] execute_RS2[6] $abc$27210$new_n7474 +1000 1 +.names $abc$27210$new_n7477 $abc$27210$new_n7476 execute_RS2[4] execute_RS2[5] $abc$27210$new_n7475 +1100 1 +.names decode_to_execute_IS_RS1_SIGNED execute_RS2[31] $abc$27210$new_n7476 +11 1 +.names execute_RS2[0] execute_RS2[1] execute_RS2[2] execute_RS2[3] $abc$27210$new_n7477 +0000 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[29] $abc$27210$new_n7476 $abc$27210$new_n7458 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$23333 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[28] $abc$27210$new_n7476 $abc$27210$new_n7459 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23335 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[27] $abc$27210$new_n7476 $abc$27210$new_n7460 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23337 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[26] $abc$27210$new_n7476 $abc$27210$new_n7461 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$23339 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[25] $abc$27210$new_n7476 $abc$27210$new_n7462 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$23341 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[24] $abc$27210$new_n7476 $abc$27210$new_n7463 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$23343 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[23] $abc$27210$new_n7476 $abc$27210$new_n7464 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$23345 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[22] $abc$27210$new_n7476 $abc$27210$new_n7465 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23347 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[21] $abc$27210$new_n7476 $abc$27210$new_n7466 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$23349 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[20] $abc$27210$new_n7476 $abc$27210$new_n7467 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23351 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[19] $abc$27210$new_n7476 $abc$27210$new_n7468 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23353 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[18] $abc$27210$new_n7476 $abc$27210$new_n7469 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$23355 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[17] $abc$27210$new_n7476 $abc$27210$new_n7470 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$23357 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7492 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23359 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[16] $abc$27210$new_n7471 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[15] $abc$27210$new_n7492 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[15] $abc$27210$new_n7476 $abc$27210$new_n7471 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$23361 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[14] $abc$27210$new_n7476 $abc$27210$new_n7472 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$23363 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7496 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$23365 +011 1 +100 1 +101 1 +110 1 +111 1 +.names execute_RS2[13] $abc$27210$new_n7473 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7476 execute_RS2[12] $abc$27210$new_n7496 +00010 1 +00011 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11010 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[12] $abc$27210$new_n7476 $abc$27210$new_n7473 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23367 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] $abc$27210$new_n7499 $abc$27210$auto$rtlil.cc:2693:MuxGate$23369 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[11] $abc$27210$new_n7476 $abc$27210$new_n7474 execute_RS2[9] execute_RS2[10] $abc$27210$new_n7499 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] $abc$27210$new_n7501 $abc$27210$auto$rtlil.cc:2693:MuxGate$23371 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[10] $abc$27210$new_n7474 $abc$27210$new_n7476 execute_RS2[9] $abc$27210$new_n7501 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[9] $abc$27210$new_n7476 $abc$27210$new_n7474 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23373 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] $abc$27210$new_n7504 $abc$27210$auto$rtlil.cc:2693:MuxGate$23375 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[8] $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7476 execute_RS2[7] $abc$27210$new_n7504 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] $abc$27210$new_n7506 $abc$27210$auto$rtlil.cc:2693:MuxGate$23377 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[7] $abc$27210$new_n7476 $abc$27210$new_n7475 execute_RS2[6] $abc$27210$new_n7506 +0010 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[6] $abc$27210$new_n7476 $abc$27210$new_n7475 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$23379 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[5] $abc$27210$new_n7476 $abc$27210$new_n7509 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$23381 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n7477 execute_RS2[4] $abc$27210$new_n7509 +10 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[4] $abc$27210$new_n7476 $abc$27210$new_n7477 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23383 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[3] $abc$27210$new_n7512 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$23385 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$27210$new_n7476 execute_RS2[1] execute_RS2[2] execute_RS2[0] $abc$27210$new_n7512 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] $abc$27210$new_n7514 $abc$27210$auto$rtlil.cc:2693:MuxGate$23387 +001 1 +011 1 +110 1 +111 1 +.names execute_RS2[2] $abc$27210$new_n7476 execute_RS2[0] execute_RS2[1] $abc$27210$new_n7514 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_RS2[1] execute_RS2[0] $abc$27210$new_n7476 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$23389 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] execute_RS2[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$23391 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24099 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24101 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24103 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24105 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24107 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24109 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24111 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24113 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24115 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24117 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24119 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24121 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24123 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24125 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24127 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24129 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24131 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24133 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24135 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[9] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24137 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[8] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24139 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[7] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24141 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[6] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24143 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[5] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24145 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[4] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24147 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[3] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24149 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[2] _zz_execute_to_memory_PC[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24151 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[1] _zz_execute_to_memory_PC[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24153 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_decode_PREDICTION_CONTEXT_hazard_1[0] _zz_execute_to_memory_PC[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24155 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] _zz_execute_to_memory_PC[30] $abc$27210$auto$rtlil.cc:2693:MuxGate$24345 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] _zz_execute_to_memory_PC[29] $abc$27210$auto$rtlil.cc:2693:MuxGate$24347 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] _zz_execute_to_memory_PC[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24349 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] _zz_execute_to_memory_PC[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$24351 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] _zz_execute_to_memory_PC[26] $abc$27210$auto$rtlil.cc:2693:MuxGate$24353 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] _zz_execute_to_memory_PC[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24355 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] _zz_execute_to_memory_PC[24] $abc$27210$auto$rtlil.cc:2693:MuxGate$24357 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] _zz_execute_to_memory_PC[23] $abc$27210$auto$rtlil.cc:2693:MuxGate$24359 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] _zz_execute_to_memory_PC[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$24361 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] _zz_execute_to_memory_PC[21] $abc$27210$auto$rtlil.cc:2693:MuxGate$24363 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] _zz_execute_to_memory_PC[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$24365 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] _zz_execute_to_memory_PC[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$24367 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] _zz_execute_to_memory_PC[18] $abc$27210$auto$rtlil.cc:2693:MuxGate$24369 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] _zz_execute_to_memory_PC[17] $abc$27210$auto$rtlil.cc:2693:MuxGate$24371 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] _zz_execute_to_memory_PC[16] $abc$27210$auto$rtlil.cc:2693:MuxGate$24373 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] _zz_execute_to_memory_PC[15] $abc$27210$auto$rtlil.cc:2693:MuxGate$24375 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] _zz_execute_to_memory_PC[14] $abc$27210$auto$rtlil.cc:2693:MuxGate$24377 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] _zz_execute_to_memory_PC[13] $abc$27210$auto$rtlil.cc:2693:MuxGate$24379 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] _zz_execute_to_memory_PC[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$24381 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] _zz_execute_to_memory_PC[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$24383 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] _zz_execute_to_memory_PC[10] $abc$27210$auto$rtlil.cc:2693:MuxGate$24385 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] _zz_execute_to_memory_PC[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$24387 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] _zz_execute_to_memory_PC[8] $abc$27210$auto$rtlil.cc:2693:MuxGate$24389 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] _zz_execute_to_memory_PC[7] $abc$27210$auto$rtlil.cc:2693:MuxGate$24391 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] _zz_execute_to_memory_PC[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24393 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] _zz_execute_to_memory_PC[5] $abc$27210$auto$rtlil.cc:2693:MuxGate$24395 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] _zz_execute_to_memory_PC[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24397 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] _zz_execute_to_memory_PC[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24399 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] _zz_execute_to_memory_PC[2] $abc$27210$auto$rtlil.cc:2693:MuxGate$24401 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4326 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$24465 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_835 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n7577 $abc$27210$auto$rtlil.cc:2693:MuxGate$24499 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7577 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n7579 $abc$27210$new_n4709 $abc$27210$new_n7578 +1111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n7579 +1000 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_834 $abc$27210$new_n4732 $abc$27210$new_n7578 $abc$27210$auto$rtlil.cc:2693:MuxGate$24501 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7582 execute_CsrPlugin_csr_833 $abc$27210$auto$rtlil.cc:2693:MuxGate$24503 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7582 +11000 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7584 execute_CsrPlugin_csr_772 $abc$27210$auto$rtlil.cc:2693:MuxGate$24505 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7585 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7584 +11000 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] $abc$27210$new_n4736 $abc$27210$new_n4709 $abc$27210$new_n7585 +1111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7587 execute_CsrPlugin_csr_836 $abc$27210$auto$rtlil.cc:2693:MuxGate$24507 +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n7578 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n7587 +11000 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_384 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n7589 $abc$27210$auto$rtlil.cc:2693:MuxGate$24509 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n7590 IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n7589 +1000 1 +.names $abc$27210$new_n4729 $abc$27210$new_n4708 $abc$27210$new_n7590 +11 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_256 $abc$27210$new_n4736 $abc$27210$new_n7590 $abc$27210$auto$rtlil.cc:2693:MuxGate$24511 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 execute_CsrPlugin_csr_768 $abc$27210$new_n4729 $abc$27210$new_n7585 $abc$27210$auto$rtlil.cc:2693:MuxGate$24513 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4093 $abc$27210$new_n6100 _zz_writeBack_MulPlugin_result[65] _zz_memory_MUL_LOW_6[51] _zz_memory_MUL_LOW_4[51] $abc$27210$auto$rtlil.cc:2693:MuxGate$24515 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck decode_to_execute_PREDICTION_HAD_BRANCHED2 $abc$27210$new_n7595 execute_to_memory_BRANCH_DO $abc$27210$new_n7617 $abc$27210$auto$rtlil.cc:2693:MuxGate$24517 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$27210$new_n7596 _zz_execute_BRANCH_CTRL[0] $abc$27210$new_n7595 +000 1 +010 1 +011 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[13] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6996 $abc$27210$new_n7597 $abc$27210$new_n7596 +00000 1 +00010 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n7598 $abc$27210$new_n6090 $abc$27210$new_n5407 $abc$27210$new_n7597 +100 1 +111 1 +.names $abc$27210$new_n7615 $abc$27210$new_n7613 $abc$27210$new_n7608 $abc$27210$new_n7603 $abc$27210$new_n7599 $abc$27210$new_n7598 +11111 1 +.names $abc$27210$new_n7602 $abc$27210$new_n7600 $abc$27210$new_n6093 $abc$27210$new_n5402 $abc$27210$new_n6998 $abc$27210$new_n7599 +11000 1 +11110 1 +.names $abc$27210$new_n7601 $abc$27210$new_n5397 $abc$27210$new_n6425 $abc$27210$new_n5385 $abc$27210$new_n6429 $abc$27210$new_n7600 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$27210$new_n6761 $abc$27210$new_n6751 $abc$27210$new_n5378 $abc$27210$new_n5348 $abc$27210$new_n7601 +0011 1 +0101 1 +1010 1 +1100 1 +.names $abc$27210$new_n6782 $abc$27210$new_n5948 $abc$27210$new_n6794 $abc$27210$new_n5422 $abc$27210$new_n7602 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n7606 $abc$27210$new_n7604 $abc$27210$new_n6755 $abc$27210$new_n5373 $abc$27210$new_n7607 $abc$27210$new_n7603 +11010 1 +11100 1 +.names $abc$27210$new_n7605 $abc$27210$new_n6792 $abc$27210$new_n5437 $abc$27210$new_n6800 $abc$27210$new_n5417 $abc$27210$new_n7604 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6769 $abc$27210$new_n5327 $abc$27210$new_n6776 $abc$27210$new_n5322 $abc$27210$new_n7605 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6757 $abc$27210$new_n6788 $abc$27210$new_n5447 $abc$27210$new_n5357 $abc$27210$new_n7606 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6784 $abc$27210$new_n5302 $abc$27210$new_n7607 +01 1 +10 1 +.names $abc$27210$new_n7612 $abc$27210$new_n7609 $abc$27210$new_n6771 $abc$27210$new_n5332 $abc$27210$new_n7611 $abc$27210$new_n7608 +11000 1 +11110 1 +.names $abc$27210$new_n7610 $abc$27210$new_n6802 $abc$27210$new_n5953 $abc$27210$new_n6767 $abc$27210$new_n5342 $abc$27210$new_n7609 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6774 $abc$27210$new_n6786 $abc$27210$new_n5442 $abc$27210$new_n5317 $abc$27210$new_n7610 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6759 $abc$27210$new_n5362 $abc$27210$new_n7611 +00 1 +11 1 +.names $abc$27210$new_n6753 $abc$27210$new_n6778 $abc$27210$new_n5307 $abc$27210$new_n5370 $abc$27210$new_n7612 +0001 1 +0111 1 +1000 1 +1110 1 +.names $abc$27210$new_n6763 $abc$27210$new_n6765 $abc$27210$new_n5337 $abc$27210$new_n5352 $abc$27210$new_n7614 $abc$27210$new_n7613 +00010 1 +01110 1 +10000 1 +11100 1 +.names $abc$27210$new_n6780 $abc$27210$new_n5312 $abc$27210$new_n7614 +01 1 +10 1 +.names $abc$27210$new_n7616 $abc$27210$new_n6790 $abc$27210$new_n5432 $abc$27210$new_n5392 $abc$27210$new_n6427 $abc$27210$new_n7615 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6796 $abc$27210$new_n5427 $abc$27210$new_n6798 $abc$27210$new_n5412 $abc$27210$new_n7616 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_BRANCH_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_2[0] _zz_execute_BRANCH_CTRL[0] execute_RS1[1] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$27210$new_n7617 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_6[51] execute_MUL_HL[33] $abc$27210$auto$rtlil.cc:2693:MuxGate$24523 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_4[51] execute_MUL_LH[33] $abc$27210$auto$rtlil.cc:2693:MuxGate$24525 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_MUL_LOW_1[31] execute_MUL_LL[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24527 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n6518 _zz_decode_RS2_3[0] $abc$27210$new_n6421 $abc$27210$new_n6429 $abc$27210$auto$rtlil.cc:2693:MuxGate$24529 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4093 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$new_n7623 $abc$27210$auto$rtlil.cc:2693:MuxGate$24531 +000 1 +010 1 +110 1 +111 1 +.names memory_arbitration_isValid $abc$27210$new_n7624 memory_DivPlugin_div_result[31] execute_to_memory_IS_DIV DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n7623 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names memory_arbitration_isValid _zz_memory_SHIFT_CTRL[1] execute_to_memory_IS_DIV $abc$27210$new_n7625 _zz_decode_RS2_3[0] $abc$27210$new_n7624 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_memory_SHIFT_CTRL[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] _zz_decode_RS2_3[31] $abc$27210$new_n7625 +010 1 +011 1 +101 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n8171 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24533 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n5838 MmuPlugin_shared_pteBuffer_PPN1[9] MmuPlugin_satp_ppn[19] $abc$27210$new_n7631 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_data[31] execute_to_memory_MEMORY_STORE_DATA_RF[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24535 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_STORE_DATA_RF[31] $abc$27210$new_n7634 $abc$27210$auto$rtlil.cc:2693:MuxGate$24537 +000 1 +010 1 +110 1 +111 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2_2[11] execute_RS2[31] execute_RS2[7] execute_RS2[15] $abc$27210$new_n7634 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4259 $abc$27210$new_n4425 decode_to_execute_PREDICTION_HAD_BRANCHED2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24539 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n4259 decode_to_execute_DO_EBREAK $abc$27210$new_n7637 IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$24541 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n7638 DebugPlugin_debugUsed DebugPlugin_haltIt DebugPlugin_disableEbreak $abc$27210$new_n7637 +1100 1 +.names $abc$27210$new_n4714 $abc$27210$new_n4303 $abc$27210$new_n7638 +11 1 +.names $abc$27210$new_n4259 decode_to_execute_CSR_WRITE_OPCODE IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n4735 $abc$27210$auto$rtlil.cc:2693:MuxGate$24543 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$27210$new_n4259 decode_to_execute_SRC2_FORCE_ZERO _zz__zz_decode_IS_CSR_85 _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24545 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7087 execute_RS2[31] $abc$27210$new_n8171 $abc$27210$new_n7642 $abc$27210$auto$rtlil.cc:2693:MuxGate$24547 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7074 $abc$27210$new_n8168 $abc$27210$new_n7623 HazardSimplePlugin_writeBackWrites_payload_data[31] $abc$27210$new_n7643 $abc$27210$new_n7642 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8165 HazardSimplePlugin_writeBackBuffer_payload_data[31] _zz_RegFilePlugin_regFile_port1[31] $abc$27210$new_n7643 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7189 execute_RS1[31] $abc$27210$new_n8171 $abc$27210$new_n7645 $abc$27210$auto$rtlil.cc:2693:MuxGate$24549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n7185 $abc$27210$new_n7186 $abc$27210$new_n7623 HazardSimplePlugin_writeBackWrites_payload_data[31] $abc$27210$new_n7646 $abc$27210$new_n7645 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7181 HazardSimplePlugin_writeBackBuffer_payload_data[31] _zz_RegFilePlugin_regFile_port0[31] $abc$27210$new_n7646 +000 1 +010 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24551 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7649 _zz_execute_BRANCH_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24553 +001 1 +011 1 +100 1 +101 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n7649 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$27210$new_n4093 _zz_writeBack_ENV_CTRL _zz_memory_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24555 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$27210$auto$rtlil.cc:2693:MuxGate$24557 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_ENV_CTRL $abc$27210$new_n7638 IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24559 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_CSR $abc$27210$new_n4303 $abc$27210$new_n4714 $abc$27210$auto$rtlil.cc:2693:MuxGate$24561 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24563 +001 1 +011 1 +100 1 +101 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_DIV decode_to_execute_IS_DIV $abc$27210$auto$rtlil.cc:2693:MuxGate$24565 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_DIV IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7657 $abc$27210$auto$rtlil.cc:2693:MuxGate$24567 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7286 $abc$27210$new_n7657 +111 1 +.names $abc$27210$new_n4093 memory_to_writeBack_IS_MUL execute_to_memory_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24569 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_IS_MUL decode_to_execute_IS_MUL $abc$27210$auto$rtlil.cc:2693:MuxGate$24571 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_MUL $abc$27210$new_n4715 $abc$27210$new_n4712 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24573 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_SHIFT_CTRL[1] _zz_execute_SHIFT_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24575 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_execute_SHIFT_CTRL[1] $abc$27210$new_n7285 $abc$27210$new_n4727 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$auto$rtlil.cc:2693:MuxGate$24577 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_21 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24579 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n5859 decode_to_execute_SRC_LESS_UNSIGNED IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 decode_to_execute_IS_SFENCE_VMA2 IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] $abc$27210$new_n7638 $abc$27210$auto$rtlil.cc:2693:MuxGate$24583 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4259 decode_to_execute_MEMORY_MANAGMENT IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$auto$rtlil.cc:2693:MuxGate$24585 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_WR execute_to_memory_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24587 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_WR decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24589 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_41 decode_to_execute_MEMORY_WR $abc$27210$auto$rtlil.cc:2693:MuxGate$24591 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_BYPASSABLE_MEMORY_STAGE decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24593 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7672 decode_to_execute_BYPASSABLE_MEMORY_STAGE $abc$27210$auto$rtlil.cc:2693:MuxGate$24595 +001 1 +011 1 +100 1 +101 1 +.names $abc$27210$new_n7286 _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n7672 +10000 1 +10001 1 +10010 1 +10011 1 +11010 1 +11110 1 +.names $abc$27210$new_n4259 decode_to_execute_BYPASSABLE_EXECUTE_STAGE $abc$27210$new_n7674 $abc$27210$new_n4723 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24597 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n7674 +10000 1 +10010 1 +11000 1 +11001 1 +.names $abc$27210$new_n4093 _zz_lastStageRegFileWrite_valid execute_to_memory_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24599 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$27210$auto$rtlil.cc:2693:MuxGate$24601 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_REGFILE_WRITE_VALID $abc$27210$new_n4707 $abc$27210$new_n7678 $abc$27210$auto$rtlil.cc:2693:MuxGate$24605 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4304 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n4714 $abc$27210$new_n7678 +00100 1 +00101 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4259 _zz__zz_decode_IS_CSR_85 _zz_execute_SRC2_CTRL[1] $abc$27210$new_n4314 _zz__zz_decode_IS_CSR_41 $abc$27210$auto$rtlil.cc:2693:MuxGate$24607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 _zz_execute_ALU_CTRL[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24609 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$27210$new_n4093 memory_to_writeBack_MEMORY_ENABLE execute_to_memory_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24611 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_MEMORY_ENABLE decode_to_execute_MEMORY_ENABLE $abc$27210$auto$rtlil.cc:2693:MuxGate$24613 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 decode_to_execute_MEMORY_ENABLE $abc$27210$new_n4314 IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24615 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$27210$new_n4259 _zz_execute_SrcPlugin_addSub_4 $abc$27210$new_n7685 _zz__zz_decode_IS_CSR_85 $abc$27210$auto$rtlil.cc:2693:MuxGate$24617 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n7685 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4259 $abc$27210$new_n7292 _zz_execute_SRC1_CTRL[1] _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$24619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_line_history[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24621 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PREDICTION_CONTEXT_hazard decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24623 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_line_history_2[1] decode_to_execute_PREDICTION_CONTEXT_line_history[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24625 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_decode_PREDICTION_CONTEXT_hazard_4 decode_to_execute_PREDICTION_CONTEXT_hazard $abc$27210$auto$rtlil.cc:2693:MuxGate$24627 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4259 _zz_6 _zz_execute_BranchPlugin_branch_src2 $abc$27210$auto$rtlil.cc:2693:MuxGate$24633 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck _zz_memory_DivPlugin_div_result_5 $abc$27210$new_n7693 $abc$27210$auto$rtlil.cc:2693:MuxGate$24651 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7702 $abc$27210$new_n7477 $abc$27210$new_n7700 $abc$27210$new_n7694 $abc$27210$new_n7693 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$27210$new_n7697 $abc$27210$new_n7695 $abc$27210$new_n7699 execute_RS2[4] execute_RS2[5] $abc$27210$new_n7694 +11100 1 +.names $abc$27210$new_n7696 execute_RS2[21] execute_RS2[22] execute_RS2[23] execute_RS2[24] $abc$27210$new_n7695 +10000 1 +.names execute_RS2[25] execute_RS2[26] execute_RS2[27] execute_RS2[28] $abc$27210$new_n7696 +0000 1 +.names $abc$27210$new_n7698 execute_RS2[13] execute_RS2[14] execute_RS2[15] execute_RS2[16] $abc$27210$new_n7697 +10000 1 +.names execute_RS2[17] execute_RS2[18] execute_RS2[19] execute_RS2[20] $abc$27210$new_n7698 +0000 1 +.names execute_RS2[29] execute_RS2[30] execute_RS2[6] execute_RS2[7] $abc$27210$new_n7699 +0000 1 +.names $abc$27210$new_n7701 execute_RS2[9] execute_RS2[10] execute_RS2[11] execute_RS2[12] $abc$27210$new_n7700 +10000 1 +.names decode_to_execute_IS_RS1_SIGNED execute_RS2[31] switch_Misc_l241_1 execute_RS2[8] $abc$27210$new_n7701 +1000 1 +.names decode_to_execute_IS_RS1_SIGNED decode_to_execute_IS_DIV execute_RS1[31] execute_RS2[31] switch_Misc_l241_1 $abc$27210$new_n7702 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7704 _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] execute_RS2[31] decode_to_execute_IS_RS1_SIGNED $abc$27210$auto$rtlil.cc:2693:MuxGate$24653 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7458 execute_RS2[29] execute_RS2[30] $abc$27210$new_n7476 $abc$27210$new_n7704 +1001 1 +1110 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] $abc$27210$auto$rtlil.cc:2693:MuxGate$24793 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n7712 +10 1 +.names $abc$27210$new_n3940 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n7714 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7716 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] $abc$27210$new_n4192 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] $abc$27210$new_n4186 $abc$27210$new_n7715 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7717 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] $abc$27210$new_n8126 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n4146 $abc$27210$new_n7716 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4140 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] $abc$27210$new_n4122 $abc$27210$new_n7717 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n7719 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] $abc$27210$new_n4106 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] $abc$27210$new_n4152 $abc$27210$new_n7718 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$27210$new_n4180 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] $abc$27210$new_n4162 $abc$27210$new_n7719 +0000 1 +0011 1 +1100 1 +1111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] $abc$27210$new_n4198 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] $abc$27210$new_n3940 $abc$27210$new_n7721 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] $abc$27210$new_n4093 $abc$27210$new_n4146 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] $abc$27210$new_n7723 +1000 1 +1010 1 +1011 1 +.names dataCache_1.stageA_request_size[1] dataCache_1.stageA_request_size[0] $abc$27210$new_n4093 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24797 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataColisions dataCache_1.stage0_dataColisions_regNextWhen $abc$27210$new_n7728 $abc$27210$new_n7726 $abc$27210$auto$rtlil.cc:2693:MuxGate$24799 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6003 $abc$27210$new_n4095 $abc$27210$new_n7727 $abc$27210$new_n7726 +000 1 +001 1 +010 1 +.names dBus_cmd_payload_wr dataCache_1.stageB_waysHit dBus_cmd_payload_uncached $abc$27210$new_n4100 $abc$27210$new_n7727 +1100 1 +.names $abc$27210$new_n7736 $abc$27210$new_n8181 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] dataCache_1.dataWriteCmd_payload_address[2] $abc$27210$new_n7728 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[1] dataCache_1.stageB_mmuRsp_physicalAddress[3] dataCache_1.dataWriteCmd_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[0] dataCache_1.stageB_mmuRsp_physicalAddress[2] dataCache_1.dataWriteCmd_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7739 $abc$27210$new_n7737 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] dBus_cmd_payload_address[6] $abc$27210$new_n7736 +1100 1 +1111 1 +.names $abc$27210$new_n7738 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] dBus_cmd_payload_address[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] dBus_cmd_payload_address[11] $abc$27210$new_n7737 +10000 1 +10011 1 +11100 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] dBus_cmd_payload_address[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] dBus_cmd_payload_address[10] $abc$27210$new_n7738 +0000 1 +0011 1 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] dBus_cmd_payload_address[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] dBus_cmd_payload_address[9] $abc$27210$new_n7739 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dataCache_1.loader_counter_value[2] dataCache_1.stageB_mmuRsp_physicalAddress[4] dataCache_1.dataWriteCmd_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_dataMux[31] dataCache_1._zz_ways_0_data_port0[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24801 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_tagsReadRsp_0_error dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24803 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dataCache_1.stageB_request_size[1] dataCache_1.stageA_request_size[1] $abc$27210$auto$rtlil.cc:2693:MuxGate$24829 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4093 dBus_cmd_payload_wr dataCache_1.io_cpu_memory_isWrite $abc$27210$auto$rtlil.cc:2693:MuxGate$24831 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7746 dataCache_1.stage0_dataColisions_regNextWhen DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$auto$rtlil.cc:2693:MuxGate$24833 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$27210$new_n7747 dBus_cmd_payload_address[10] dataCache_1.dataReadCmd_payload[8] dBus_cmd_payload_address[11] dataCache_1.dataReadCmd_payload[9] $abc$27210$new_n7746 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7748 dBus_cmd_payload_address[8] dataCache_1.dataReadCmd_payload[6] dBus_cmd_payload_address[9] dataCache_1.dataReadCmd_payload[7] $abc$27210$new_n7747 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8184 dBus_cmd_payload_address[6] dataCache_1.dataReadCmd_payload[4] dBus_cmd_payload_address[7] dataCache_1.dataReadCmd_payload[5] $abc$27210$new_n7748 +10000 1 +10011 1 +11100 1 +11111 1 +.names dataCache_1.dataWriteCmd_payload_address[0] dataCache_1.dataReadCmd_payload[0] $abc$27210$new_n7726 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7751 +0000 1 +1100 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6986 $abc$27210$new_n6988 dataCache_1.dataReadCmd_payload[0] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[1] $abc$27210$new_n6095 $abc$27210$new_n6097 $abc$27210$new_n7755 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 $abc$27210$new_n6091 $abc$27210$new_n4327 $abc$27210$new_n6089 $abc$27210$new_n7756 +00000 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6979 $abc$27210$new_n6982 dataCache_1.dataReadCmd_payload[1] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6965 $abc$27210$new_n6968 dataCache_1.dataReadCmd_payload[3] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6975 $abc$27210$new_n6973 $abc$27210$new_n5385 dataCache_1.dataReadCmd_payload[2] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6951 $abc$27210$new_n6954 dataCache_1.dataReadCmd_payload[5] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6961 $abc$27210$new_n6959 $abc$27210$new_n5373 dataCache_1.dataReadCmd_payload[4] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6937 $abc$27210$new_n6940 dataCache_1.dataReadCmd_payload[7] +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6947 $abc$27210$new_n6945 $abc$27210$new_n5362 dataCache_1.dataReadCmd_payload[6] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6923 $abc$27210$new_n6926 dataCache_1.dataReadCmd_payload[9] +010 1 +011 1 +100 1 +110 1 +.names $abc$27210$new_n4327 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6933 $abc$27210$new_n6931 $abc$27210$new_n5352 dataCache_1.dataReadCmd_payload[8] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_mask[3] $abc$27210$new_n7756 $abc$27210$auto$rtlil.cc:2693:MuxGate$24835 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.stageA_request_size[1] switch_Misc_l241_1 $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24837 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck dataCache_1.io_cpu_memory_isWrite decode_to_execute_MEMORY_WR $abc$27210$new_n4327 $abc$27210$auto$rtlil.cc:2693:MuxGate$24839 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7770 DBusCachedPlugin_mmuBus_cmd_0_isStuck BranchPlugin_branchExceptionPort_payload_badAddr[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24873 +000 1 +001 1 +011 1 +.names $abc$27210$new_n7410 $abc$27210$new_n7771 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n7399 $abc$27210$new_n7340 $abc$27210$new_n7770 +00000 1 +01001 1 +01010 1 +01011 1 +10011 1 +11000 1 +11001 1 +11010 1 +.names $abc$27210$new_n7358 execute_RS1[31] _zz_execute_to_memory_PC[31] $abc$27210$new_n7771 +000 1 +010 1 +100 1 +101 1 +.names $abc$27210$new_n4259 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24885 +001 1 +011 1 +110 1 +111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck execute_to_memory_PC[31] _zz_execute_to_memory_PC[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24895 +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7086 $abc$27210$new_n5857 $abc$27210$new_n4093 HazardSimplePlugin_writeBackWrites_valid +110 1 +.names execute_RS1[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_aHigh[16] +101 1 +110 1 +.names execute_RS2[31] _zz__zz_execute_BranchPlugin_branch_src2_2[11] switch_Misc_l241_1 execute_MulPlugin_bHigh[16] +110 1 +.names $abc$27210$new_n4636 DebugPlugin_godmode CsrPlugin_exception +10 1 +.names $abc$27210$new_n7779 $abc$27210$new_n4266 $0\DebugPlugin_isPipBusy[0:0] +00 1 +01 1 +10 1 +.names execute_arbitration_isValid memory_arbitration_isValid lastStageIsValid IBusCachedPlugin_cache.io_cpu_fetch_isValid IBusCachedPlugin_cache.io_cpu_decode_isValid $abc$27210$new_n7779 +00000 1 +.names iBus_rsp_payload_error IBusCachedPlugin_cache.lineLoader_hadError IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error +01 1 +10 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n6015 IBusCachedPlugin_cache._zz_2 +00 1 +01 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_valid IBusCachedPlugin_cache.lineLoader_cmdSent iBus_cmd_valid +10 1 +.names $abc$27210$new_n7784 decode_to_execute_MEMORY_ENABLE $abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] +10 1 +.names $abc$27210$new_n7785 DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation MmuPlugin_dBusAccess_rsp_payload_redo memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE $abc$27210$new_n7784 +10000 1 +10001 1 +10010 1 +.names decode_to_execute_MEMORY_MANAGMENT execute_arbitration_isValid $abc$27210$new_n4100 dataCache_1.stageB_flusher_start dataCache_1.stageB_flusher_waitDone $abc$27210$new_n7785 +11100 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n4327 dataCache_1.io_cpu_execute_refilling decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid dataCache_1._zz_ways_0_dataReadRspMem +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[3] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[2] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[1] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n7726 $abc$27210$new_n6003 dBus_cmd_payload_mask[0] $abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] +001 1 +010 1 +011 1 +.names $abc$27210$new_n5826 $abc$27210$new_n4424 IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 _zz_decode_PREDICTION_CONTEXT_line_history_1 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_hadError $abc$27210$new_n6015 iBus_rsp_payload_error iBus_rsp_valid $abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$auto$rtlil.cc:2693:MuxGate$24235 +00 1 +11 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24233 +010 1 +100 1 +101 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24231 +010 1 +100 1 +101 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_flushCounter[0] $abc$27210$new_n7796 +11 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24229 +01 1 +10 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7796 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$new_n7798 +110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24227 +011 1 +100 1 +101 1 +110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7798 $abc$27210$auto$rtlil.cc:2693:MuxGate$24225 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid $abc$27210$auto$rtlil.cc:2693:MuxGate$24867 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_flushCounter[3] $abc$27210$new_n7796 $abc$27210$new_n7802 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[2] $abc$27210$new_n7802 IBusCachedPlugin_cache.lineLoader_flushCounter[6] $abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_flushCounter[0] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_flushCounter[1] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_flushCounter[2] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_flushCounter[3] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_flushCounter[4] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_flushCounter[5] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] +001 1 +011 1 +110 1 +111 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_flushCounter[6] IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n5829 DebugPlugin_haltedByBreak debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 $0\DebugPlugin_haltedByBreak[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DebugPlugin_godmode debug_bus_cmd_payload_data[25] $abc$27210$new_n5967 DebugPlugin_isPipBusy DebugPlugin_haltIt $0\DebugPlugin_godmode[0:0] +00001 1 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7814 $abc$27210$new_n5854 $abc$27210$new_n4266 $0\DebugPlugin_haltIt[0:0] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$27210$new_n5829 DebugPlugin_haltIt $abc$27210$new_n5967 debug_bus_cmd_payload_data[25] debug_bus_cmd_payload_data[17] $abc$27210$new_n7814 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +01111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n5404 CsrPlugin_mepc[0] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][0] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_833 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7816 +1111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n5399 CsrPlugin_mepc[1] $abc$27210$new_n4432 $0\CsrPlugin_mepc[31:0][1] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5394 CsrPlugin_mepc[2] DBusCachedPlugin_redoBranch_payload[2] $0\CsrPlugin_mepc[31:0][2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5387 CsrPlugin_mepc[3] DBusCachedPlugin_redoBranch_payload[3] $0\CsrPlugin_mepc[31:0][3] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5382 CsrPlugin_mepc[4] DBusCachedPlugin_redoBranch_payload[4] $0\CsrPlugin_mepc[31:0][4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5377 CsrPlugin_mepc[5] DBusCachedPlugin_redoBranch_payload[5] $0\CsrPlugin_mepc[31:0][5] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5372 CsrPlugin_mepc[6] DBusCachedPlugin_redoBranch_payload[6] $0\CsrPlugin_mepc[31:0][6] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5366 CsrPlugin_mepc[7] DBusCachedPlugin_redoBranch_payload[7] $0\CsrPlugin_mepc[31:0][7] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5361 CsrPlugin_mepc[8] DBusCachedPlugin_redoBranch_payload[8] $0\CsrPlugin_mepc[31:0][8] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5356 CsrPlugin_mepc[9] DBusCachedPlugin_redoBranch_payload[9] $0\CsrPlugin_mepc[31:0][9] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5351 CsrPlugin_mepc[10] DBusCachedPlugin_redoBranch_payload[10] $0\CsrPlugin_mepc[31:0][10] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5344 CsrPlugin_mepc[11] DBusCachedPlugin_redoBranch_payload[11] $0\CsrPlugin_mepc[31:0][11] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5339 CsrPlugin_mepc[12] DBusCachedPlugin_redoBranch_payload[12] $0\CsrPlugin_mepc[31:0][12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5334 CsrPlugin_mepc[13] DBusCachedPlugin_redoBranch_payload[13] $0\CsrPlugin_mepc[31:0][13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5329 CsrPlugin_mepc[14] DBusCachedPlugin_redoBranch_payload[14] $0\CsrPlugin_mepc[31:0][14] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5324 CsrPlugin_mepc[15] DBusCachedPlugin_redoBranch_payload[15] $0\CsrPlugin_mepc[31:0][15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5319 CsrPlugin_mepc[16] DBusCachedPlugin_redoBranch_payload[16] $0\CsrPlugin_mepc[31:0][16] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5314 CsrPlugin_mepc[17] DBusCachedPlugin_redoBranch_payload[17] $0\CsrPlugin_mepc[31:0][17] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5309 CsrPlugin_mepc[18] DBusCachedPlugin_redoBranch_payload[18] $0\CsrPlugin_mepc[31:0][18] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5304 CsrPlugin_mepc[19] DBusCachedPlugin_redoBranch_payload[19] $0\CsrPlugin_mepc[31:0][19] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5299 CsrPlugin_mepc[20] DBusCachedPlugin_redoBranch_payload[20] $0\CsrPlugin_mepc[31:0][20] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5945 CsrPlugin_mepc[21] DBusCachedPlugin_redoBranch_payload[21] $0\CsrPlugin_mepc[31:0][21] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5444 CsrPlugin_mepc[22] DBusCachedPlugin_redoBranch_payload[22] $0\CsrPlugin_mepc[31:0][22] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5439 CsrPlugin_mepc[23] DBusCachedPlugin_redoBranch_payload[23] $0\CsrPlugin_mepc[31:0][23] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5434 CsrPlugin_mepc[24] DBusCachedPlugin_redoBranch_payload[24] $0\CsrPlugin_mepc[31:0][24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5429 CsrPlugin_mepc[25] DBusCachedPlugin_redoBranch_payload[25] $0\CsrPlugin_mepc[31:0][25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5424 CsrPlugin_mepc[26] DBusCachedPlugin_redoBranch_payload[26] $0\CsrPlugin_mepc[31:0][26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5419 CsrPlugin_mepc[27] DBusCachedPlugin_redoBranch_payload[27] $0\CsrPlugin_mepc[31:0][27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5414 CsrPlugin_mepc[28] DBusCachedPlugin_redoBranch_payload[28] $0\CsrPlugin_mepc[31:0][28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5409 CsrPlugin_mepc[29] DBusCachedPlugin_redoBranch_payload[29] $0\CsrPlugin_mepc[31:0][29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5950 CsrPlugin_mepc[30] DBusCachedPlugin_redoBranch_payload[30] $0\CsrPlugin_mepc[31:0][30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7816 $abc$27210$new_n4432 $abc$27210$new_n5840 CsrPlugin_mepc[31] DBusCachedPlugin_redoBranch_payload[31] $0\CsrPlugin_mepc[31:0][31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7849 $abc$27210$new_n5387 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7849 +1111 1 +.names $abc$27210$new_n5856 DBusCachedPlugin_mmuBus_cmd_0_isStuck $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] +10 1 +.names $abc$27210$new_n5851 $abc$27210$new_n4259 DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n5856 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5855 $abc$27210$new_n4258 $abc$27210$new_n5851 $abc$27210$new_n4259 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5855 $abc$27210$new_n4258 $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] +10 1 +.names $abc$27210$new_n5868 $abc$27210$new_n4433 $0\CsrPlugin_interrupt_valid[0:0] +00 1 +.names $abc$27210$new_n7856 $abc$27210$new_n4438 $abc$27210$new_n4432 CsrPlugin_mstatus_MPP[0] $0\CsrPlugin_mstatus_MPP[1:0][0] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n5339 $abc$27210$new_n5344 $abc$27210$new_n7857 $abc$27210$new_n7856 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$27210$new_n4264 $abc$27210$new_n4259 $abc$27210$new_n7857 +1111 1 +.names $abc$27210$new_n7856 $abc$27210$new_n4438 $abc$27210$new_n4432 CsrPlugin_mstatus_MPP[1] $0\CsrPlugin_mstatus_MPP[1:0][1] +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7857 $abc$27210$new_n5366 $abc$27210$new_n7860 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$27210$new_n4432 $abc$27210$new_n4438 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$27210$new_n7860 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$27210$new_n7857 $abc$27210$new_n5387 $abc$27210$new_n7862 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4438 CsrPlugin_mstatus_MPIE $abc$27210$new_n4432 CsrPlugin_mstatus_MIE $abc$27210$new_n7862 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_5_valid $abc$27210$new_n5075 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_5_exception $0\MmuPlugin_ports_1_cache_5_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5298 $abc$27210$new_n5827 $abc$27210$new_n4259 decode_to_execute_IS_SFENCE_VMA2 execute_arbitration_isValid $abc$27210$new_n7864 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_4_valid $abc$27210$new_n5113 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_4_exception $0\MmuPlugin_ports_1_cache_4_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_3_valid $abc$27210$new_n5150 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_3_exception $0\MmuPlugin_ports_1_cache_3_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_2_valid $abc$27210$new_n5187 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_2_exception $0\MmuPlugin_ports_1_cache_2_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_1_valid $abc$27210$new_n5224 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_1_exception $0\MmuPlugin_ports_1_cache_1_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7864 MmuPlugin_ports_1_cache_0_valid $abc$27210$new_n5261 $abc$27210$new_n4431 MmuPlugin_ports_1_cache_0_exception $0\MmuPlugin_ports_1_cache_0_valid[0:0] +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5314 MmuPlugin_status_mprv $0\MmuPlugin_status_mprv[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE $abc$27210$new_n4264 $abc$27210$new_n4259 execute_CsrPlugin_csr_256 execute_CsrPlugin_csr_768 $abc$27210$new_n7871 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5304 MmuPlugin_status_mxr $0\MmuPlugin_status_mxr[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n7871 $abc$27210$new_n5309 MmuPlugin_status_sum $0\MmuPlugin_status_sum[0:0] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[4] DebugPlugin_stepIt debug_bus_rsp_data[4] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[2] DebugPlugin_isPipBusy debug_bus_rsp_data[2] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[1] DebugPlugin_haltIt debug_bus_rsp_data[1] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[0] DebugPlugin_resetIt debug_bus_rsp_data[0] +001 1 +011 1 +110 1 +111 1 +.names _zz_when_DebugPlugin_l257 DebugPlugin_busReadDataReg[3] DebugPlugin_haltedByBreak debug_bus_rsp_data[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4320 IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] debug_bus_cmd_ready +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names memory_DivPlugin_div_counter_value[0] $abc$27210$new_n4261 $abc$27210$new_n4093 memory_DivPlugin_div_counter_valueNext[0] +010 1 +011 1 +101 1 +.names $abc$27210$new_n7882 memory_DivPlugin_div_counter_value[1] DBusCachedPlugin_mmuBus_cmd_0_isStuck $abc$27210$new_n4904 memory_DivPlugin_div_counter_valueNext[1] +0110 1 +0111 1 +1000 1 +1010 1 +.names memory_DivPlugin_div_counter_value[0] $abc$27210$new_n4261 $abc$27210$new_n7882 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[2] +101 1 +110 1 +.names memory_DivPlugin_div_counter_value[1] $abc$27210$new_n7882 $abc$27210$new_n7884 +11 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[3] +1011 1 +1100 1 +1101 1 +1110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[4] memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 memory_DivPlugin_div_counter_valueNext[4] +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_isStuck memory_DivPlugin_div_counter_value[5] $abc$27210$new_n7888 $abc$27210$new_n4904 $abc$27210$new_n7882 memory_DivPlugin_div_counter_valueNext[5] +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names memory_DivPlugin_div_counter_value[4] memory_DivPlugin_div_counter_value[3] memory_DivPlugin_div_counter_value[2] $abc$27210$new_n7884 $abc$27210$new_n7888 +1111 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[0] _zz_14 lastStageRegFileWrite_payload_data[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[1] _zz_14 lastStageRegFileWrite_payload_data[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[2] _zz_14 lastStageRegFileWrite_payload_data[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[3] _zz_14 lastStageRegFileWrite_payload_data[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[4] _zz_14 lastStageRegFileWrite_payload_data[4] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[5] _zz_14 lastStageRegFileWrite_payload_data[5] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[6] _zz_14 lastStageRegFileWrite_payload_data[6] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[7] _zz_14 lastStageRegFileWrite_payload_data[7] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[8] _zz_14 lastStageRegFileWrite_payload_data[8] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[9] _zz_14 lastStageRegFileWrite_payload_data[9] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[10] _zz_14 lastStageRegFileWrite_payload_data[10] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[11] _zz_14 lastStageRegFileWrite_payload_data[11] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[12] _zz_14 lastStageRegFileWrite_payload_data[12] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[13] _zz_14 lastStageRegFileWrite_payload_data[13] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[14] _zz_14 lastStageRegFileWrite_payload_data[14] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[15] _zz_14 lastStageRegFileWrite_payload_data[15] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[16] _zz_14 lastStageRegFileWrite_payload_data[16] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[17] _zz_14 lastStageRegFileWrite_payload_data[17] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[18] _zz_14 lastStageRegFileWrite_payload_data[18] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[19] _zz_14 lastStageRegFileWrite_payload_data[19] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[20] _zz_14 lastStageRegFileWrite_payload_data[20] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[21] _zz_14 lastStageRegFileWrite_payload_data[21] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[22] _zz_14 lastStageRegFileWrite_payload_data[22] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[23] _zz_14 lastStageRegFileWrite_payload_data[23] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[24] _zz_14 lastStageRegFileWrite_payload_data[24] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[25] _zz_14 lastStageRegFileWrite_payload_data[25] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[26] _zz_14 lastStageRegFileWrite_payload_data[26] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[27] _zz_14 lastStageRegFileWrite_payload_data[27] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[28] _zz_14 lastStageRegFileWrite_payload_data[28] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[29] _zz_14 lastStageRegFileWrite_payload_data[29] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[30] _zz_14 lastStageRegFileWrite_payload_data[30] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_data[31] _zz_14 lastStageRegFileWrite_payload_data[31] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_14 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_14 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_14 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_14 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_14 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_14 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_valueNext[0] +01 1 +10 1 +.names MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_valueNext[1] +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names MmuPlugin_ports_1_entryToReplace_value[2] MmuPlugin_ports_1_entryToReplace_value[0] $abc$27210$new_n5076 MmuPlugin_ports_1_entryToReplace_value[1] MmuPlugin_ports_1_entryToReplace_valueNext[2] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] $abc$27210$new_n4455 IBusCachedPlugin_predictionJumpInterface_payload[29] +000 1 +011 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[30] +000 1 +011 1 +101 1 +110 1 +.names _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] $abc$27210$new_n4396 IBusCachedPlugin_predictionJumpInterface_payload[31] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names dataCache_1.loader_counter_willOverflow dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n4095 $abc$27210$new_n4100 dataCache_1._zz_2 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[5] dataCache_1.stageB_flusher_counter[0] dataCache_1.tagsWriteCmd_payload_address[0] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[6] dataCache_1.stageB_flusher_counter[1] dataCache_1.tagsWriteCmd_payload_address[1] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[7] dataCache_1.stageB_flusher_counter[2] dataCache_1.tagsWriteCmd_payload_address[2] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[8] dataCache_1.stageB_flusher_counter[3] dataCache_1.tagsWriteCmd_payload_address[3] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[9] dataCache_1.stageB_flusher_counter[4] dataCache_1.tagsWriteCmd_payload_address[4] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[10] dataCache_1.stageB_flusher_counter[5] dataCache_1.tagsWriteCmd_payload_address[5] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_willOverflow dBus_cmd_payload_address[11] dataCache_1.stageB_flusher_counter[6] dataCache_1.tagsWriteCmd_payload_address[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[0] dBus_cmd_payload_data[0] dataCache_1.dataWriteCmd_payload_data[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[1] dBus_cmd_payload_data[1] dataCache_1.dataWriteCmd_payload_data[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[2] dBus_cmd_payload_data[2] dataCache_1.dataWriteCmd_payload_data[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[3] dBus_cmd_payload_data[3] dataCache_1.dataWriteCmd_payload_data[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[4] dBus_cmd_payload_data[4] dataCache_1.dataWriteCmd_payload_data[4] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[5] dBus_cmd_payload_data[5] dataCache_1.dataWriteCmd_payload_data[5] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[6] dBus_cmd_payload_data[6] dataCache_1.dataWriteCmd_payload_data[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[7] dBus_cmd_payload_data[7] dataCache_1.dataWriteCmd_payload_data[7] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[8] dBus_cmd_payload_data[8] dataCache_1.dataWriteCmd_payload_data[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[9] dBus_cmd_payload_data[9] dataCache_1.dataWriteCmd_payload_data[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[10] dBus_cmd_payload_data[10] dataCache_1.dataWriteCmd_payload_data[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[11] dBus_cmd_payload_data[11] dataCache_1.dataWriteCmd_payload_data[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[12] dBus_cmd_payload_data[12] dataCache_1.dataWriteCmd_payload_data[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[13] dBus_cmd_payload_data[13] dataCache_1.dataWriteCmd_payload_data[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[14] dBus_cmd_payload_data[14] dataCache_1.dataWriteCmd_payload_data[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[15] dBus_cmd_payload_data[15] dataCache_1.dataWriteCmd_payload_data[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[16] dBus_cmd_payload_data[16] dataCache_1.dataWriteCmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[17] dBus_cmd_payload_data[17] dataCache_1.dataWriteCmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[18] dBus_cmd_payload_data[18] dataCache_1.dataWriteCmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[19] dBus_cmd_payload_data[19] dataCache_1.dataWriteCmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[20] dBus_cmd_payload_data[20] dataCache_1.dataWriteCmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[21] dBus_cmd_payload_data[21] dataCache_1.dataWriteCmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[22] dBus_cmd_payload_data[22] dataCache_1.dataWriteCmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[23] dBus_cmd_payload_data[23] dataCache_1.dataWriteCmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[24] dBus_cmd_payload_data[24] dataCache_1.dataWriteCmd_payload_data[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[25] dBus_cmd_payload_data[25] dataCache_1.dataWriteCmd_payload_data[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[26] dBus_cmd_payload_data[26] dataCache_1.dataWriteCmd_payload_data[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[27] dBus_cmd_payload_data[27] dataCache_1.dataWriteCmd_payload_data[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[28] dBus_cmd_payload_data[28] dataCache_1.dataWriteCmd_payload_data[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[29] dBus_cmd_payload_data[29] dataCache_1.dataWriteCmd_payload_data[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[30] dBus_cmd_payload_data[30] dataCache_1.dataWriteCmd_payload_data[30] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n6003 dBus_rsp_payload_data[31] dBus_cmd_payload_data[31] dataCache_1.dataWriteCmd_payload_data[31] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[0] dBus_cmd_payload_size[2] dBus_cmd_payload_address[0] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[1] dBus_cmd_payload_size[2] dBus_cmd_payload_address[1] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[2] dBus_cmd_payload_size[2] dBus_cmd_payload_address[2] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[3] dBus_cmd_payload_size[2] dBus_cmd_payload_address[3] +10 1 +.names dataCache_1.stageB_mmuRsp_physicalAddress[4] dBus_cmd_payload_size[2] dBus_cmd_payload_address[4] +10 1 +.names dataCache_1.stageB_request_size[0] dBus_cmd_payload_size[2] dBus_cmd_payload_size[0] +01 1 +10 1 +11 1 +.names dataCache_1.stageB_request_size[1] dBus_cmd_payload_size[2] dBus_cmd_payload_size[1] +10 1 +.names dataCache_1.stageB_flusher_start $abc$27210$new_n4234 dataCache_1.stageB_flusher_counter[7] $abc$27210$new_n6007 dataCache_1.stageB_flusher_counter[6] $abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[15] IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] decode_INSTRUCTION_ANTICIPATED[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[16] IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] decode_INSTRUCTION_ANTICIPATED[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[17] IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] decode_INSTRUCTION_ANTICIPATED[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[18] IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] decode_INSTRUCTION_ANTICIPATED[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] decode_INSTRUCTION_ANTICIPATED[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] decode_INSTRUCTION_ANTICIPATED[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[21] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] decode_INSTRUCTION_ANTICIPATED[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] decode_INSTRUCTION_ANTICIPATED[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[23] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] decode_INSTRUCTION_ANTICIPATED[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$27210$new_n4258 IBusCachedPlugin_cache._zz_banks_0_port1[24] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] decode_INSTRUCTION_ANTICIPATED[24] +001 1 +011 1 +110 1 +111 1 +.names dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[0] +01 1 +10 1 +.names dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[1] +011 1 +100 1 +101 1 +110 1 +.names dataCache_1.loader_counter_value[2] dataCache_1.loader_counter_value[1] dataCache_1.loader_counter_value[0] $abc$27210$new_n6003 dataCache_1.loader_counter_valueNext[2] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] execute_to_memory_BRANCH_DO memory_arbitration_isValid _zz__zz_3_port[1] +011 1 +100 1 +101 1 +110 1 +.names execute_to_memory_PREDICTION_CONTEXT_line_history[0] _zz__zz_3_port[0] +0 1 +.names $abc$27210$new_n8193 MmuPlugin_ports_1_cache_2_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] MmuPlugin_ports_1_cache_2_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n7999 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8195 MmuPlugin_ports_1_cache_4_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_4_virtualAddress_0[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] $abc$27210$new_n8001 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names $abc$27210$new_n8001 MmuPlugin_ports_1_cache_4_superPage $abc$27210$new_n8002 +10 1 +.names $abc$27210$new_n3971 MmuPlugin_ports_1_cache_4_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_4_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8003 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n3994 MmuPlugin_ports_1_cache_3_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_3_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8006 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8006 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_3_virtualAddress_0[7] MmuPlugin_ports_1_cache_3_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8007 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8007 MmuPlugin_ports_1_cache_3_virtualAddress_0[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] $abc$27210$new_n8008 +100 1 +111 1 +.names $abc$27210$new_n4013 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_5_virtualAddress_0[5] MmuPlugin_ports_1_cache_5_virtualAddress_0[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] $abc$27210$new_n8009 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4016 MmuPlugin_ports_1_cache_5_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_5_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] $abc$27210$new_n8010 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8010 $abc$27210$new_n8009 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] MmuPlugin_ports_1_cache_5_virtualAddress_0[7] MmuPlugin_ports_1_cache_5_superPage $abc$27210$new_n8011 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11100 1 +.names $abc$27210$new_n4037 MmuPlugin_ports_1_cache_1_virtualAddress_0[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_1_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8013 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4369 MmuPlugin_ports_1_cache_4_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_4_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8015 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4368 $abc$27210$new_n4055 $abc$27210$new_n3985 MmuPlugin_ports_1_cache_4_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8016 +11100 1 +11111 1 +.names $abc$27210$new_n8016 $abc$27210$new_n8015 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_4_virtualAddress_1[7] $abc$27210$new_n8002 $abc$27210$new_n8017 +11000 1 +11110 1 +.names execute_to_memory_INSTRUCTION[7] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] execute_to_memory_INSTRUCTION[8] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8021 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8021 execute_to_memory_INSTRUCTION[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] execute_to_memory_INSTRUCTION[10] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8022 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8022 execute_to_memory_INSTRUCTION[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8023 +100 1 +111 1 +.names MmuPlugin_ports_1_cache_3_valid MmuPlugin_ports_1_cache_3_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8025 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_5_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_5_virtualAddress_1[8] $abc$27210$new_n4027 $abc$27210$new_n8029 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_5_valid MmuPlugin_ports_1_cache_5_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_5_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] $abc$27210$new_n8030 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4362 MmuPlugin_ports_1_cache_2_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_2_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8032 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4363 MmuPlugin_ports_1_cache_2_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_2_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8033 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4359 $abc$27210$new_n8032 $abc$27210$new_n8033 $abc$27210$new_n3956 $abc$27210$new_n8034 +1110 1 +.names $abc$27210$new_n4387 MmuPlugin_ports_1_cache_0_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8035 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4504 DBusCachedPlugin_redoBranch_payload[22] IBusCachedPlugin_predictionJumpInterface_payload[22] $abc$27210$new_n4434 $abc$27210$new_n8038 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4505 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] $abc$27210$new_n8038 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4510 DBusCachedPlugin_redoBranch_payload[21] IBusCachedPlugin_predictionJumpInterface_payload[21] $abc$27210$new_n4434 $abc$27210$new_n8040 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4511 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] $abc$27210$new_n8040 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21963 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4517 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[20] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[20] $abc$27210$new_n8042 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8042 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8043 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8043 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] $abc$27210$new_n8044 $abc$27210$auto$rtlil.cc:2693:MuxGate$21965 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4524 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[19] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[19] $abc$27210$new_n8046 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8046 $abc$27210$new_n4447 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8047 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8047 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] $abc$27210$new_n8048 $abc$27210$auto$rtlil.cc:2693:MuxGate$21967 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4531 DBusCachedPlugin_redoBranch_payload[18] IBusCachedPlugin_predictionJumpInterface_payload[18] $abc$27210$new_n4434 $abc$27210$new_n8050 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4532 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] $abc$27210$new_n8050 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4537 DBusCachedPlugin_redoBranch_payload[17] IBusCachedPlugin_predictionJumpInterface_payload[17] $abc$27210$new_n4434 $abc$27210$new_n8052 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4538 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] $abc$27210$new_n8052 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21971 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4544 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[16] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[16] $abc$27210$new_n8054 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8054 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8055 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8055 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] $abc$27210$new_n8056 $abc$27210$auto$rtlil.cc:2693:MuxGate$21973 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4551 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[15] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[15] $abc$27210$new_n8058 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8058 $abc$27210$new_n4448 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8059 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8059 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] $abc$27210$new_n8060 $abc$27210$auto$rtlil.cc:2693:MuxGate$21975 +010 1 +011 1 +101 1 +111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4558 DBusCachedPlugin_redoBranch_payload[14] IBusCachedPlugin_predictionJumpInterface_payload[14] $abc$27210$new_n4434 $abc$27210$new_n8062 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4559 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] $abc$27210$new_n8062 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21977 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4423 $abc$27210$new_n4564 DBusCachedPlugin_redoBranch_payload[13] IBusCachedPlugin_predictionJumpInterface_payload[13] $abc$27210$new_n4434 $abc$27210$new_n8064 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$27210$new_n4439 $abc$27210$new_n4565 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] $abc$27210$new_n8064 $abc$27210$new_n4435 $abc$27210$auto$rtlil.cc:2693:MuxGate$21979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$27210$new_n4571 $abc$27210$new_n4422 DBusCachedPlugin_redoBranch_payload[12] $abc$27210$new_n4423 IBusCachedPlugin_predictionJumpInterface_payload[12] $abc$27210$new_n8066 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8066 $abc$27210$new_n4449 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] $abc$27210$new_n8067 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$27210$new_n4435 $abc$27210$new_n8067 $abc$27210$new_n4441 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$27210$new_n4439 IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] $abc$27210$new_n8068 $abc$27210$auto$rtlil.cc:2693:MuxGate$21981 +010 1 +011 1 +101 1 +111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4728 $abc$27210$new_n4722 $abc$27210$new_n4714 $abc$27210$new_n8071 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$27210$new_n4711 $abc$27210$new_n4721 IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] $abc$27210$new_n4712 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8074 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$27210$new_n8078 IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] $abc$27210$new_n4705 $abc$27210$new_n8074 $abc$27210$new_n8075 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n8077 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n8077 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n8078 +00 1 +01 1 +11 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] _zz__zz_decode_IS_CSR_41 _zz__zz_decode_IS_CSR_21 _zz__zz_decode_IS_CSR_85 $abc$27210$new_n8079 +01100 1 +01101 1 +10001 1 +10011 1 +.names IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] $abc$27210$new_n8079 IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] $abc$27210$new_n8080 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[28] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] $abc$27210$new_n8081 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] $abc$27210$new_n8081 DBusCachedPlugin_exceptionBus_payload_badAddr[28] $abc$27210$auto$rtlil.cc:2693:MuxGate$23089 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[27] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] $abc$27210$new_n8083 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] $abc$27210$new_n8083 DBusCachedPlugin_exceptionBus_payload_badAddr[27] $abc$27210$auto$rtlil.cc:2693:MuxGate$23091 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4279 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] $abc$27210$new_n8086 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4763 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] $abc$27210$new_n8088 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4761 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] $abc$27210$new_n8091 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8091 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] $abc$27210$new_n8092 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[22] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8094 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] $abc$27210$new_n8094 DBusCachedPlugin_exceptionBus_payload_badAddr[22] $abc$27210$auto$rtlil.cc:2693:MuxGate$23101 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[20] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] $abc$27210$new_n8096 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] $abc$27210$new_n8096 DBusCachedPlugin_exceptionBus_payload_badAddr[20] $abc$27210$auto$rtlil.cc:2693:MuxGate$23105 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[19] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] $abc$27210$new_n8098 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] $abc$27210$new_n8098 DBusCachedPlugin_exceptionBus_payload_badAddr[19] $abc$27210$auto$rtlil.cc:2693:MuxGate$23107 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] _zz__zz_decode_IS_CSR_21 $abc$27210$new_n8100 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] $abc$27210$new_n8100 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$auto$rtlil.cc:2693:MuxGate$23121 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[11] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] $abc$27210$new_n8102 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] $abc$27210$new_n8102 DBusCachedPlugin_exceptionBus_payload_badAddr[11] $abc$27210$auto$rtlil.cc:2693:MuxGate$23123 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] $abc$27210$new_n8104 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] $abc$27210$new_n8104 DBusCachedPlugin_exceptionBus_payload_badAddr[9] $abc$27210$auto$rtlil.cc:2693:MuxGate$23127 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[4] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] $abc$27210$new_n8106 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] $abc$27210$new_n8106 DBusCachedPlugin_exceptionBus_payload_badAddr[4] $abc$27210$auto$rtlil.cc:2693:MuxGate$23137 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[14] $abc$27210$new_n5745 MmuPlugin_dBusAccess_rsp_payload_data[14] $abc$27210$new_n8108 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8108 DBusCachedPlugin_exceptionBus_payload_badAddr[14] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[14] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[12] $abc$27210$new_n5757 MmuPlugin_dBusAccess_rsp_payload_data[12] $abc$27210$new_n8110 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8110 DBusCachedPlugin_exceptionBus_payload_badAddr[12] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[12] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4254 _zz__zz_decode_RS2_2[10] $abc$27210$new_n5769 MmuPlugin_dBusAccess_rsp_payload_data[10] $abc$27210$new_n8112 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4255 $abc$27210$new_n4101 $abc$27210$new_n8112 DBusCachedPlugin_exceptionBus_payload_badAddr[10] $abc$27210$new_n5647 HazardSimplePlugin_writeBackWrites_payload_data[10] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 dBus_cmd_payload_uncached MmuPlugin_dBusAccess_rsp_payload_data[21] dBus_rsp_payload_data[5] dataCache_1.stageB_dataMux[5] $abc$27210$new_n8114 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4101 DBusCachedPlugin_exceptionBus_payload_badAddr[0] DBusCachedPlugin_exceptionBus_payload_badAddr[5] $abc$27210$new_n8114 MmuPlugin_dBusAccess_rsp_payload_data[13] $abc$27210$new_n8115 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4701 $abc$27210$new_n4700 BranchPlugin_branchExceptionPort_payload_badAddr[31] _zz_6 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] $abc$27210$new_n8116 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4696 $abc$27210$new_n4698 CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] $abc$27210$new_n8116 DBusCachedPlugin_exceptionBus_payload_badAddr[31] $abc$27210$auto$rtlil.cc:2693:MuxGate$24643 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n4903 execute_to_memory_INSTRUCTION[13] memory_DivPlugin_div_result[31] memory_DivPlugin_div_stage_0_remainderShifted memory_DivPlugin_accumulator[31] $abc$27210$new_n8118 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n4869 $abc$27210$new_n4902 $abc$27210$new_n4901 $abc$27210$new_n4900 $abc$27210$new_n8119 +1000 1 +.names $abc$27210$new_n8118 $abc$27210$new_n8119 $abc$27210$new_n4903 $abc$27210$new_n4905 _zz_memory_DivPlugin_div_result_5 $abc$27210$auto$rtlil.cc:2693:MuxGate$24649 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n4087 MmuPlugin_status_mxr MmuPlugin_ports_1_cache_2_allowRead MmuPlugin_ports_1_cache_3_allowExecute MmuPlugin_ports_1_cache_2_allowExecute $abc$27210$new_n8121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +.names $abc$27210$new_n3943 MmuPlugin_ports_1_cache_1_allowRead $abc$27210$new_n5988 MmuPlugin_ports_1_cache_1_allowExecute MmuPlugin_status_mxr $abc$27210$new_n8122 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names $abc$27210$new_n4088 $abc$27210$new_n8121 $abc$27210$new_n8122 MmuPlugin_ports_1_cache_3_allowRead $abc$27210$new_n4087 $abc$27210$new_n8123 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4088 $abc$27210$new_n4087 $abc$27210$new_n5998 DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] $abc$27210$new_n8124 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n4088 $abc$27210$new_n3943 $abc$27210$new_n4085 $abc$27210$new_n8124 DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] $abc$27210$new_n8125 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n8125 $abc$27210$new_n4090 DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] $abc$27210$new_n4085 $abc$27210$new_n8126 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$27210$new_n6802 $abc$27210$new_n6732 _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6803 $abc$27210$new_n8127 +00000 1 +01100 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6803 $abc$27210$new_n5953 $abc$27210$new_n8127 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n8128 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8128 $abc$27210$new_n4264 $abc$27210$new_n5951 $abc$27210$new_n8129 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8129 $abc$27210$new_n6806 $abc$27210$new_n8130 +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n5412 $abc$27210$new_n6803 $abc$27210$new_n6812 $abc$27210$new_n6797 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8131 +00010 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8131 $abc$27210$new_n4264 $abc$27210$new_n5410 $abc$27210$new_n6813 $abc$27210$new_n8132 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8132 MmuPlugin_shared_pteBuffer_PPN1[7] MmuPlugin_satp_ppn[17] $abc$27210$new_n8133 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5417 $abc$27210$new_n6803 $abc$27210$new_n6799 $abc$27210$new_n6733 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8134 +00000 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8134 $abc$27210$new_n4264 $abc$27210$new_n5415 $abc$27210$new_n6819 $abc$27210$new_n8135 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8135 MmuPlugin_shared_pteBuffer_PPN1[6] MmuPlugin_satp_ppn[16] $abc$27210$new_n8136 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5427 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6796 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8137 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n8137 $abc$27210$new_n6795 $abc$27210$new_n6734 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8138 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01101 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n6833 $abc$27210$new_n6832 $abc$27210$new_n8138 $abc$27210$new_n6805 $abc$27210$new_n8139 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$27210$new_n5447 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6788 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8140 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n8140 $abc$27210$new_n6787 $abc$27210$new_n6736 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8141 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01101 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8141 $abc$27210$new_n6805 $abc$27210$new_n4264 $abc$27210$new_n5445 $abc$27210$new_n8142 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names $abc$27210$new_n5322 $abc$27210$new_n6803 $abc$27210$new_n6775 $abc$27210$new_n6739 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8143 +00000 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8143 $abc$27210$new_n4264 $abc$27210$new_n5320 $abc$27210$new_n6894 $abc$27210$new_n8144 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11000 1 +11010 1 +11110 1 +.names $abc$27210$new_n4327 $abc$27210$new_n5838 $abc$27210$new_n8144 MmuPlugin_shared_pteBuffer_PPN0[4] MmuPlugin_satp_ppn[4] $abc$27210$new_n8145 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$27210$new_n5332 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6771 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8146 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n6772 $abc$27210$new_n6740 $abc$27210$new_n8146 $abc$27210$new_n8147 +00000 1 +00001 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n8147 $abc$27210$new_n4264 $abc$27210$new_n5330 $abc$27210$new_n8148 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8148 $abc$27210$new_n6907 $abc$27210$new_n8149 +000 1 +001 1 +100 1 +110 1 +.names $abc$27210$new_n5352 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6763 $abc$27210$new_n8150 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8150 $abc$27210$new_n6931 $abc$27210$new_n8151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8151 $abc$27210$new_n6933 $abc$27210$new_n4264 $abc$27210$new_n5353 $abc$27210$new_n8152 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5362 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6759 $abc$27210$new_n8153 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8153 $abc$27210$new_n6945 $abc$27210$new_n8154 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8154 $abc$27210$new_n6947 $abc$27210$new_n4264 $abc$27210$new_n5363 $abc$27210$new_n8155 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5373 $abc$27210$new_n6803 _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6755 $abc$27210$new_n8156 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8156 $abc$27210$new_n6959 $abc$27210$new_n8157 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8157 $abc$27210$new_n6961 $abc$27210$new_n4264 $abc$27210$new_n5374 $abc$27210$new_n8158 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n5385 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6429 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8159 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8159 $abc$27210$new_n6973 $abc$27210$new_n8160 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8160 $abc$27210$new_n6975 $abc$27210$new_n4264 $abc$27210$new_n5383 $abc$27210$new_n8161 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$27210$new_n6089 $abc$27210$new_n6996 $abc$27210$new_n7001 $abc$27210$new_n8162 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$27210$new_n4264 $abc$27210$new_n4327 $abc$27210$new_n8162 $abc$27210$new_n5405 $abc$27210$new_n8163 +0010 1 +0011 1 +1000 1 +1010 1 +.names $abc$27210$new_n7080 IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] HazardSimplePlugin_writeBackBuffer_payload_address[1] HazardSimplePlugin_writeBackBuffer_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] $abc$27210$new_n8164 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8164 IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] HazardSimplePlugin_writeBackBuffer_payload_address[3] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8165 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7086 HazardSimplePlugin_writeBackWrites_payload_address[0] IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] $abc$27210$new_n8166 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8166 HazardSimplePlugin_writeBackWrites_payload_address[2] IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] $abc$27210$new_n8167 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8167 HazardSimplePlugin_writeBackWrites_payload_address[4] IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] $abc$27210$new_n8168 +100 1 +111 1 +.names $abc$27210$new_n5843 _zz_execute_ALU_BITWISE_CTRL[1] $abc$27210$new_n6999 _zz_execute_ALU_BITWISE_CTRL[0] $abc$27210$new_n6803 $abc$27210$new_n8169 +00011 1 +00101 1 +00111 1 +01001 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$27210$new_n6805 $abc$27210$new_n6803 decode_to_execute_SRC2_FORCE_ZERO $abc$27210$new_n8169 $abc$27210$new_n6997 $abc$27210$new_n8170 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$27210$new_n4327 $abc$27210$new_n8170 $abc$27210$new_n7631 $abc$27210$new_n4264 $abc$27210$new_n5841 $abc$27210$new_n8171 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$27210$new_n7714 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] $abc$27210$new_n4128 $abc$27210$new_n4174 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] $abc$27210$new_n8172 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8172 $abc$27210$new_n8216 dataCache_1.stageB_waysHit $abc$27210$new_n4094 $abc$27210$new_n4100 $abc$27210$auto$rtlil.cc:2693:MuxGate$24795 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] $abc$27210$new_n4134 $abc$27210$new_n7712 $abc$27210$new_n4111 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] $abc$27210$new_n8175 +00000 1 +00001 1 +00010 1 +11000 1 +11001 1 +11010 1 +.names dataCache_1.dataWriteCmd_payload_address[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] dataCache_1.dataWriteCmd_payload_address[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] $abc$27210$new_n8178 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[2] dBus_cmd_payload_mask[1] dataCache_1.stageA_mask[1] dataCache_1.stageA_mask[2] $abc$27210$new_n8179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names $abc$27210$new_n6003 dBus_cmd_payload_mask[0] dBus_cmd_payload_mask[3] dataCache_1.stageA_mask[3] dataCache_1.stageA_mask[0] $abc$27210$new_n8180 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names $abc$27210$new_n8178 $abc$27210$new_n8179 $abc$27210$new_n8180 $abc$27210$new_n8181 +100 1 +101 1 +110 1 +.names $abc$27210$new_n6003 $abc$27210$new_n6087 dBus_cmd_payload_mask[3] dBus_cmd_payload_mask[2] $abc$27210$new_n7756 $abc$27210$new_n8182 +00000 1 +00001 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$27210$new_n7751 dataCache_1.dataReadCmd_payload[2] dataCache_1.dataWriteCmd_payload_address[2] dataCache_1.dataReadCmd_payload[1] dataCache_1.dataWriteCmd_payload_address[1] $abc$27210$new_n8183 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8183 dataCache_1.dataReadCmd_payload[3] dBus_cmd_payload_address[5] $abc$27210$new_n7755 $abc$27210$new_n8182 $abc$27210$new_n8184 +10000 1 +10001 1 +10010 1 +11100 1 +11101 1 +11110 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_1_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] MmuPlugin_ports_1_cache_1_virtualAddress_0[3] $abc$27210$new_n4033 $abc$27210$new_n8185 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$27210$new_n8185 MmuPlugin_ports_1_cache_1_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] MmuPlugin_ports_1_cache_1_virtualAddress_0[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] $abc$27210$new_n8186 +10000 1 +10011 1 +11100 1 +11111 1 +.names MmuPlugin_ports_1_cache_0_valid DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_0_virtualAddress_1[3] MmuPlugin_ports_1_cache_0_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] $abc$27210$new_n8188 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names MmuPlugin_ports_1_cache_2_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_2_virtualAddress_0[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] $abc$27210$new_n8191 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$27210$new_n8191 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] MmuPlugin_ports_1_cache_2_virtualAddress_0[4] MmuPlugin_ports_1_cache_2_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8192 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8192 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] MmuPlugin_ports_1_cache_2_virtualAddress_0[8] MmuPlugin_ports_1_cache_2_virtualAddress_0[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] $abc$27210$new_n8193 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] MmuPlugin_ports_1_cache_4_virtualAddress_0[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] MmuPlugin_ports_1_cache_4_virtualAddress_0[0] $abc$27210$new_n3972 $abc$27210$new_n8194 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$27210$new_n8003 $abc$27210$new_n8194 MmuPlugin_ports_1_cache_4_virtualAddress_0[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] $abc$27210$new_n8195 +1100 1 +1111 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] MmuPlugin_ports_1_cache_1_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_1_virtualAddress_1[6] $abc$27210$new_n4046 $abc$27210$new_n8196 +00000 1 +00110 1 +11000 1 +11110 1 +.names MmuPlugin_ports_1_cache_1_valid MmuPlugin_ports_1_cache_1_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_1_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8197 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8025 MmuPlugin_ports_1_cache_3_virtualAddress_1[7] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8199 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n8029 MmuPlugin_ports_1_cache_5_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_5_virtualAddress_1[2] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] $abc$27210$new_n8201 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8030 $abc$27210$new_n4023 $abc$27210$new_n4020 MmuPlugin_ports_1_cache_5_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] $abc$27210$new_n8202 +11100 1 +11111 1 +.names $abc$27210$new_n8201 $abc$27210$new_n8202 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] MmuPlugin_ports_1_cache_5_virtualAddress_1[4] $abc$27210$new_n8011 $abc$27210$new_n8203 +11000 1 +11110 1 +.names $abc$27210$new_n4736 $abc$27210$new_n4735 $abc$27210$new_n4706 $abc$27210$new_n4722 $abc$27210$new_n4731 $abc$27210$new_n8204 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$27210$new_n4725 $abc$27210$new_n4266 IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] $abc$27210$new_n8204 $abc$27210$new_n8080 $abc$27210$new_n8206 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$27210$new_n8206 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n8071 _zz__zz_decode_IS_CSR_41 $abc$27210$new_n4740 $abc$27210$new_n8207 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$27210$new_n8207 $abc$27210$new_n8075 $abc$27210$new_n4722 IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] $abc$27210$new_n4723 $abc$27210$new_n8208 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n4280 $abc$27210$new_n4275 $abc$27210$new_n4274 IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] $abc$27210$new_n8209 +00000 1 +00010 1 +00011 1 +.names $abc$27210$new_n8209 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] $abc$27210$new_n8210 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8210 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] $abc$27210$new_n8211 +100 1 +111 1 +.names $abc$27210$new_n4764 IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] $abc$27210$new_n8212 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8211 $abc$27210$new_n8092 $abc$27210$new_n8088 $abc$27210$new_n8086 $abc$27210$new_n8212 $abc$27210$new_n8213 +11111 1 +.names $abc$27210$new_n7721 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] $abc$27210$new_n4204 $abc$27210$new_n4210 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] $abc$27210$new_n8214 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n7723 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] $abc$27210$new_n4116 $abc$27210$new_n4168 dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] $abc$27210$new_n8215 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8175 $abc$27210$new_n7718 $abc$27210$new_n7715 $abc$27210$new_n8215 $abc$27210$new_n8214 $abc$27210$new_n8216 +11111 1 +.names $abc$27210$new_n8197 MmuPlugin_ports_1_cache_1_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_1_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8217 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8196 $abc$27210$new_n4048 $abc$27210$new_n8217 MmuPlugin_ports_1_cache_1_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8218 +11100 1 +11111 1 +.names $abc$27210$new_n8218 MmuPlugin_ports_1_cache_1_superPage $abc$27210$new_n8186 $abc$27210$new_n8013 $abc$27210$new_n8219 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$27210$new_n8188 MmuPlugin_ports_1_cache_0_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] MmuPlugin_ports_1_cache_0_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8220 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8035 MmuPlugin_ports_1_cache_0_virtualAddress_1[6] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] MmuPlugin_ports_1_cache_0_virtualAddress_1[8] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] $abc$27210$new_n8222 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8220 MmuPlugin_ports_1_cache_0_virtualAddress_1[9] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] MmuPlugin_ports_1_cache_0_virtualAddress_1[5] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] $abc$27210$new_n8223 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n4049 $abc$27210$new_n8223 $abc$27210$new_n8222 $abc$27210$new_n4370 $abc$27210$new_n8224 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$27210$new_n4333 MmuPlugin_ports_1_cache_3_virtualAddress_1[3] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] MmuPlugin_ports_1_cache_3_virtualAddress_1[4] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] $abc$27210$new_n8225 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$27210$new_n8199 MmuPlugin_ports_1_cache_3_virtualAddress_1[0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] MmuPlugin_ports_1_cache_3_virtualAddress_1[1] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] $abc$27210$new_n8226 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$27210$new_n8226 $abc$27210$new_n8225 $abc$27210$new_n3990 DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] MmuPlugin_ports_1_cache_3_virtualAddress_1[8] $abc$27210$new_n8227 +11000 1 +11001 1 +11011 1 +.subckt dff C=clk D=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid Q=IBusCachedPlugin_cache._zz_when_InstructionCache_l342 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24235 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[0] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24233 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[1] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24231 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[2] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24229 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[3] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24227 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[4] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24225 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[5] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24867 Q=IBusCachedPlugin_cache.lineLoader_flushCounter[6] R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt sdffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$procmux$1907_Y[7] Q=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid R=IBusCachedPlugin_cache.when_InstructionCache_l351 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24223 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24881 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dffr C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_counter[7:0][7] Q=dataCache_1.stageB_flusher_counter[7] R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24221 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24219 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24217 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24215 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24213 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24211 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24209 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24207 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24205 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24203 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24201 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24199 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24197 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24195 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24193 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24191 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24189 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24187 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24185 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24183 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24181 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24179 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24177 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24175 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24173 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24171 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24169 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24167 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24165 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24163 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24161 Q=_zz_memory_DivPlugin_div_stage_0_outNumerator[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24655 Q=memory_DivPlugin_div_stage_0_remainderShifted +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24641 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24637 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24159 Q=CsrPlugin_mcause_exceptionCode[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24879 Q=CsrPlugin_mcause_exceptionCode[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24903 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[3] +.subckt dffr C=clk D=$0\DebugPlugin_haltIt[0:0] Q=DebugPlugin_haltIt R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24791 Q=DebugPlugin_resetIt R=debugReset +.subckt dffr C=clk D=$0\DebugPlugin_godmode[0:0] Q=DebugPlugin_godmode R=debugReset +.subckt dffr C=clk D=$0\DebugPlugin_haltedByBreak[0:0] Q=DebugPlugin_haltedByBreak R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24789 Q=DebugPlugin_stepIt R=debugReset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24787 Q=DebugPlugin_debugUsed R=debugReset +.subckt dff C=clk D=$0\DebugPlugin_isPipBusy[0:0] Q=DebugPlugin_isPipBusy +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24785 Q=DebugPlugin_disableEbreak R=debugReset +.subckt dff C=clk D=debug_bus_cmd_payload_address[2] Q=_zz_when_DebugPlugin_l257 +.subckt dff C=clk D=DebugPlugin_resetIt Q=debug_resetOut +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24155 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24153 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24151 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24149 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24147 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24145 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24143 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24141 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24139 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24137 Q=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24135 Q=execute_to_memory_PC[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24133 Q=execute_to_memory_PC[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24131 Q=execute_to_memory_PC[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24129 Q=execute_to_memory_PC[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24127 Q=execute_to_memory_PC[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24125 Q=execute_to_memory_PC[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24123 Q=execute_to_memory_PC[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24121 Q=execute_to_memory_PC[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24119 Q=execute_to_memory_PC[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24117 Q=execute_to_memory_PC[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24115 Q=execute_to_memory_PC[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24113 Q=execute_to_memory_PC[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24111 Q=execute_to_memory_PC[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24109 Q=execute_to_memory_PC[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24107 Q=execute_to_memory_PC[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24105 Q=execute_to_memory_PC[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24103 Q=execute_to_memory_PC[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24101 Q=execute_to_memory_PC[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24099 Q=execute_to_memory_PC[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24895 Q=execute_to_memory_PC[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24783 Q=_zz_decode_PREDICTION_CONTEXT_hazard_2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24097 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24095 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24093 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24091 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24089 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24087 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24085 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24083 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24081 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24781 Q=_zz_decode_PREDICTION_CONTEXT_hazard_3[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24779 Q=_zz_decode_PREDICTION_CONTEXT_hazard_4 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24079 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24777 Q=_zz_decode_PREDICTION_CONTEXT_line_history_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24077 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24075 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24073 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24071 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24069 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24067 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24065 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24063 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24061 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24059 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24057 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24055 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24053 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24051 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24049 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24047 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24045 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24043 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24041 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24039 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24037 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24035 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24033 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24031 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24029 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24027 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24025 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24023 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24021 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24883 Q=IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24019 Q=MmuPlugin_satp_asid[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24017 Q=MmuPlugin_satp_asid[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24015 Q=MmuPlugin_satp_asid[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24013 Q=MmuPlugin_satp_asid[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24011 Q=MmuPlugin_satp_asid[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24009 Q=MmuPlugin_satp_asid[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24007 Q=MmuPlugin_satp_asid[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24005 Q=MmuPlugin_satp_asid[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24775 Q=MmuPlugin_satp_asid[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24003 Q=MmuPlugin_satp_ppn[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24001 Q=MmuPlugin_satp_ppn[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23999 Q=MmuPlugin_satp_ppn[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23997 Q=MmuPlugin_satp_ppn[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23995 Q=MmuPlugin_satp_ppn[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23993 Q=MmuPlugin_satp_ppn[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23991 Q=MmuPlugin_satp_ppn[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23989 Q=MmuPlugin_satp_ppn[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23987 Q=MmuPlugin_satp_ppn[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23985 Q=MmuPlugin_satp_ppn[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23983 Q=MmuPlugin_satp_ppn[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23981 Q=MmuPlugin_satp_ppn[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23979 Q=MmuPlugin_satp_ppn[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23977 Q=MmuPlugin_satp_ppn[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23975 Q=MmuPlugin_satp_ppn[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23973 Q=MmuPlugin_satp_ppn[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23971 Q=MmuPlugin_satp_ppn[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23969 Q=MmuPlugin_satp_ppn[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23967 Q=MmuPlugin_satp_ppn[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23965 Q=MmuPlugin_satp_ppn[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23963 Q=MmuPlugin_satp_ppn[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24773 Q=MmuPlugin_satp_ppn[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24771 Q=MmuPlugin_ports_1_cache_0_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24769 Q=MmuPlugin_ports_1_cache_0_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23961 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23959 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23957 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23955 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23953 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23951 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23949 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23947 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23945 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24767 Q=MmuPlugin_ports_1_cache_0_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23943 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23941 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23939 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23937 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23935 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23933 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23931 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23929 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23927 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24765 Q=MmuPlugin_ports_1_cache_0_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23925 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23923 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23921 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23919 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23917 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23915 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23913 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23911 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23909 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24763 Q=MmuPlugin_ports_1_cache_0_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23907 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23905 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23903 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23901 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23899 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23897 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23895 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23893 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23891 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24761 Q=DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24759 Q=MmuPlugin_ports_1_cache_0_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24757 Q=MmuPlugin_ports_1_cache_0_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24755 Q=MmuPlugin_ports_1_cache_0_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24753 Q=MmuPlugin_ports_1_cache_1_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24751 Q=MmuPlugin_ports_1_cache_1_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23889 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23887 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23885 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23883 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23881 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23879 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23877 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23875 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23873 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24749 Q=MmuPlugin_ports_1_cache_1_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23871 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23869 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23867 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23865 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23863 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23861 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23859 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23857 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23855 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24747 Q=MmuPlugin_ports_1_cache_1_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23853 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23851 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23849 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23847 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23845 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23843 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23841 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23839 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23837 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24745 Q=MmuPlugin_ports_1_cache_1_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23835 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23833 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23831 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23829 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23827 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23825 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23823 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23821 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23819 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24743 Q=DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24741 Q=MmuPlugin_ports_1_cache_1_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24739 Q=MmuPlugin_ports_1_cache_1_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24737 Q=MmuPlugin_ports_1_cache_1_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24735 Q=MmuPlugin_ports_1_cache_2_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24733 Q=MmuPlugin_ports_1_cache_2_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23817 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23815 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23813 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23811 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23809 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23807 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23805 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23803 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23801 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24731 Q=MmuPlugin_ports_1_cache_2_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23799 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23797 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23795 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23793 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23791 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23789 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23787 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23785 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23783 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24729 Q=MmuPlugin_ports_1_cache_2_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23781 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23779 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23777 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23775 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23773 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23771 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23769 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23767 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23765 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24727 Q=MmuPlugin_ports_1_cache_2_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23763 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23761 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23759 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23757 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23755 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23753 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23751 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23749 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23747 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24725 Q=DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24723 Q=MmuPlugin_ports_1_cache_2_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24721 Q=MmuPlugin_ports_1_cache_2_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24719 Q=MmuPlugin_ports_1_cache_2_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24717 Q=MmuPlugin_ports_1_cache_3_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24715 Q=MmuPlugin_ports_1_cache_3_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23745 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23743 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23741 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23739 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23737 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23735 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23733 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23731 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23729 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23727 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23725 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23723 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23721 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23719 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23717 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23715 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23713 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24711 Q=MmuPlugin_ports_1_cache_3_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23707 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23705 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23703 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23701 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23699 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23697 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23695 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23693 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24709 Q=MmuPlugin_ports_1_cache_3_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23691 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23689 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23687 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23685 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23683 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23681 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23679 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23677 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23675 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24707 Q=DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24705 Q=MmuPlugin_ports_1_cache_3_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24703 Q=MmuPlugin_ports_1_cache_3_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24701 Q=MmuPlugin_ports_1_cache_3_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24699 Q=MmuPlugin_ports_1_cache_4_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24697 Q=MmuPlugin_ports_1_cache_4_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23673 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23671 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23669 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23667 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23665 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23663 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23661 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23659 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23657 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24695 Q=MmuPlugin_ports_1_cache_4_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23655 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23653 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23651 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23649 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23647 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23645 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23643 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23641 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23639 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24693 Q=MmuPlugin_ports_1_cache_4_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23637 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23635 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23633 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23631 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23629 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23627 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23625 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23623 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23621 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24691 Q=MmuPlugin_ports_1_cache_4_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23619 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23617 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23615 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23613 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23611 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23609 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23607 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23605 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23603 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24689 Q=DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24687 Q=MmuPlugin_ports_1_cache_4_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24685 Q=MmuPlugin_ports_1_cache_4_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24683 Q=MmuPlugin_ports_1_cache_4_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24681 Q=MmuPlugin_ports_1_cache_5_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24679 Q=MmuPlugin_ports_1_cache_5_superPage +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23601 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23599 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23597 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23595 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23593 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23591 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23589 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23587 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23585 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24677 Q=MmuPlugin_ports_1_cache_5_virtualAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23583 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23581 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23579 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23577 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23575 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23573 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23571 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23569 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23567 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24675 Q=MmuPlugin_ports_1_cache_5_virtualAddress_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23565 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23563 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23561 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23559 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23557 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23555 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23553 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23551 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23549 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24673 Q=MmuPlugin_ports_1_cache_5_physicalAddress_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23547 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23545 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23543 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23541 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23539 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23537 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23535 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23533 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23531 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24671 Q=DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24669 Q=MmuPlugin_ports_1_cache_5_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24667 Q=MmuPlugin_ports_1_cache_5_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24665 Q=MmuPlugin_ports_1_cache_5_allowExecute +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23529 Q=MmuPlugin_shared_vpn_0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23527 Q=MmuPlugin_shared_vpn_0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23525 Q=MmuPlugin_shared_vpn_0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23523 Q=MmuPlugin_shared_vpn_0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23521 Q=MmuPlugin_shared_vpn_0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23519 Q=MmuPlugin_shared_vpn_0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23517 Q=MmuPlugin_shared_vpn_0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23515 Q=MmuPlugin_shared_vpn_0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23513 Q=MmuPlugin_shared_vpn_0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24663 Q=MmuPlugin_shared_vpn_0[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23511 Q=MmuPlugin_shared_vpn_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23509 Q=MmuPlugin_shared_vpn_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23507 Q=MmuPlugin_shared_vpn_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23505 Q=MmuPlugin_shared_vpn_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23503 Q=MmuPlugin_shared_vpn_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23501 Q=MmuPlugin_shared_vpn_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23499 Q=MmuPlugin_shared_vpn_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23497 Q=MmuPlugin_shared_vpn_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23495 Q=MmuPlugin_shared_vpn_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24661 Q=MmuPlugin_shared_vpn_1[9] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[0] Q=MmuPlugin_shared_dBusRsp_pte_V +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[1] Q=MmuPlugin_shared_dBusRsp_pte_R +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[2] Q=MmuPlugin_shared_dBusRsp_pte_W +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[3] Q=MmuPlugin_shared_dBusRsp_pte_X +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[6] Q=MmuPlugin_shared_dBusRsp_pte_A +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[7] Q=MmuPlugin_shared_dBusRsp_pte_D +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[10] Q=MmuPlugin_shared_dBusRspStaged_payload_data[10] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[11] Q=MmuPlugin_shared_dBusRspStaged_payload_data[11] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[12] Q=MmuPlugin_shared_dBusRspStaged_payload_data[12] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[13] Q=MmuPlugin_shared_dBusRspStaged_payload_data[13] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[14] Q=MmuPlugin_shared_dBusRspStaged_payload_data[14] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[15] Q=MmuPlugin_shared_dBusRspStaged_payload_data[15] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[16] Q=MmuPlugin_shared_dBusRspStaged_payload_data[16] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[17] Q=MmuPlugin_shared_dBusRspStaged_payload_data[17] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[18] Q=MmuPlugin_shared_dBusRspStaged_payload_data[18] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[19] Q=MmuPlugin_shared_dBusRspStaged_payload_data[19] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[20] Q=MmuPlugin_shared_dBusRspStaged_payload_data[20] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[21] Q=MmuPlugin_shared_dBusRspStaged_payload_data[21] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[22] Q=MmuPlugin_shared_dBusRspStaged_payload_data[22] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[23] Q=MmuPlugin_shared_dBusRspStaged_payload_data[23] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[24] Q=MmuPlugin_shared_dBusRspStaged_payload_data[24] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[25] Q=MmuPlugin_shared_dBusRspStaged_payload_data[25] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[26] Q=MmuPlugin_shared_dBusRspStaged_payload_data[26] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[27] Q=MmuPlugin_shared_dBusRspStaged_payload_data[27] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[28] Q=MmuPlugin_shared_dBusRspStaged_payload_data[28] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_data[29] Q=MmuPlugin_shared_dBusRspStaged_payload_data[29] +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_error Q=MmuPlugin_shared_dBusRspStaged_payload_error +.subckt dff C=clk D=MmuPlugin_dBusAccess_rsp_payload_redo Q=MmuPlugin_shared_dBusRspStaged_payload_redo +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23493 Q=MmuPlugin_shared_pteBuffer_PPN0[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23491 Q=MmuPlugin_shared_pteBuffer_PPN0[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23489 Q=MmuPlugin_shared_pteBuffer_PPN0[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23487 Q=MmuPlugin_shared_pteBuffer_PPN0[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23485 Q=MmuPlugin_shared_pteBuffer_PPN0[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23483 Q=MmuPlugin_shared_pteBuffer_PPN0[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23481 Q=MmuPlugin_shared_pteBuffer_PPN0[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23479 Q=MmuPlugin_shared_pteBuffer_PPN0[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23477 Q=MmuPlugin_shared_pteBuffer_PPN0[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24659 Q=MmuPlugin_shared_pteBuffer_PPN0[9] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[0] Q=HazardSimplePlugin_writeBackBuffer_payload_data[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[1] Q=HazardSimplePlugin_writeBackBuffer_payload_data[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[2] Q=HazardSimplePlugin_writeBackBuffer_payload_data[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[3] Q=HazardSimplePlugin_writeBackBuffer_payload_data[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[4] Q=HazardSimplePlugin_writeBackBuffer_payload_data[4] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[5] Q=HazardSimplePlugin_writeBackBuffer_payload_data[5] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[6] Q=HazardSimplePlugin_writeBackBuffer_payload_data[6] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[7] Q=HazardSimplePlugin_writeBackBuffer_payload_data[7] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[8] Q=HazardSimplePlugin_writeBackBuffer_payload_data[8] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[9] Q=HazardSimplePlugin_writeBackBuffer_payload_data[9] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[10] Q=HazardSimplePlugin_writeBackBuffer_payload_data[10] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[11] Q=HazardSimplePlugin_writeBackBuffer_payload_data[11] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[12] Q=HazardSimplePlugin_writeBackBuffer_payload_data[12] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[13] Q=HazardSimplePlugin_writeBackBuffer_payload_data[13] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[14] Q=HazardSimplePlugin_writeBackBuffer_payload_data[14] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[15] Q=HazardSimplePlugin_writeBackBuffer_payload_data[15] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[16] Q=HazardSimplePlugin_writeBackBuffer_payload_data[16] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[17] Q=HazardSimplePlugin_writeBackBuffer_payload_data[17] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[18] Q=HazardSimplePlugin_writeBackBuffer_payload_data[18] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[19] Q=HazardSimplePlugin_writeBackBuffer_payload_data[19] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[20] Q=HazardSimplePlugin_writeBackBuffer_payload_data[20] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[21] Q=HazardSimplePlugin_writeBackBuffer_payload_data[21] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[22] Q=HazardSimplePlugin_writeBackBuffer_payload_data[22] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[23] Q=HazardSimplePlugin_writeBackBuffer_payload_data[23] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[24] Q=HazardSimplePlugin_writeBackBuffer_payload_data[24] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[25] Q=HazardSimplePlugin_writeBackBuffer_payload_data[25] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[26] Q=HazardSimplePlugin_writeBackBuffer_payload_data[26] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[27] Q=HazardSimplePlugin_writeBackBuffer_payload_data[27] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[28] Q=HazardSimplePlugin_writeBackBuffer_payload_data[28] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[29] Q=HazardSimplePlugin_writeBackBuffer_payload_data[29] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[30] Q=HazardSimplePlugin_writeBackBuffer_payload_data[30] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_data[31] Q=HazardSimplePlugin_writeBackBuffer_payload_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23475 Q=MmuPlugin_shared_pteBuffer_PPN1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23473 Q=MmuPlugin_shared_pteBuffer_PPN1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23471 Q=MmuPlugin_shared_pteBuffer_PPN1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23469 Q=MmuPlugin_shared_pteBuffer_PPN1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23467 Q=MmuPlugin_shared_pteBuffer_PPN1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23465 Q=MmuPlugin_shared_pteBuffer_PPN1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23463 Q=MmuPlugin_shared_pteBuffer_PPN1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23461 Q=MmuPlugin_shared_pteBuffer_PPN1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23459 Q=MmuPlugin_shared_pteBuffer_PPN1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23457 Q=MmuPlugin_shared_pteBuffer_PPN1[9] +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23453 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23451 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23449 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23447 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23445 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23443 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23441 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23439 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23437 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23435 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23433 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23431 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23429 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23427 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23425 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23423 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23421 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23419 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23417 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23415 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23413 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23411 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23409 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23407 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23405 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23403 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23401 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23399 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23397 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23395 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23393 Q=_zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24869 Q=memory_DivPlugin_accumulator[31] RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23391 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23389 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23387 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23385 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23383 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23381 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23379 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23377 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23375 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23373 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23371 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23369 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23367 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23365 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23363 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23361 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23359 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23357 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23355 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23353 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23351 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23349 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23347 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23345 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23343 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23341 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23339 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23337 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23335 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23333 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23331 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24653 Q=_zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator[31] +.subckt sdffrn C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24871 Q=memory_DivPlugin_div_done RN=DBusCachedPlugin_mmuBus_cmd_0_isStuck +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24651 Q=_zz_memory_DivPlugin_div_result_5 +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][0] Q=CsrPlugin_mepc[0] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][1] Q=CsrPlugin_mepc[1] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][2] Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][3] Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][4] Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][5] Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][6] Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][7] Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][8] Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][9] Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][10] Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][11] Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][12] Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][13] Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][14] Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][15] Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][16] Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][17] Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][18] Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][19] Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][20] Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][21] Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][22] Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][23] Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][24] Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][25] Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][26] Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][27] Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][28] Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][29] Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][30] Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$0\CsrPlugin_mepc[31:0][31] Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23329 Q=memory_DivPlugin_div_result[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23327 Q=memory_DivPlugin_div_result[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23325 Q=memory_DivPlugin_div_result[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23323 Q=memory_DivPlugin_div_result[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23321 Q=memory_DivPlugin_div_result[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23319 Q=memory_DivPlugin_div_result[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23317 Q=memory_DivPlugin_div_result[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23315 Q=memory_DivPlugin_div_result[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23313 Q=memory_DivPlugin_div_result[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23311 Q=memory_DivPlugin_div_result[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23309 Q=memory_DivPlugin_div_result[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23307 Q=memory_DivPlugin_div_result[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23305 Q=memory_DivPlugin_div_result[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23303 Q=memory_DivPlugin_div_result[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23301 Q=memory_DivPlugin_div_result[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23299 Q=memory_DivPlugin_div_result[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23297 Q=memory_DivPlugin_div_result[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23295 Q=memory_DivPlugin_div_result[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23293 Q=memory_DivPlugin_div_result[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23291 Q=memory_DivPlugin_div_result[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23289 Q=memory_DivPlugin_div_result[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23287 Q=memory_DivPlugin_div_result[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23285 Q=memory_DivPlugin_div_result[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23283 Q=memory_DivPlugin_div_result[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23281 Q=memory_DivPlugin_div_result[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23279 Q=memory_DivPlugin_div_result[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23277 Q=memory_DivPlugin_div_result[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23275 Q=memory_DivPlugin_div_result[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23273 Q=memory_DivPlugin_div_result[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23271 Q=memory_DivPlugin_div_result[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23269 Q=memory_DivPlugin_div_result[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24649 Q=memory_DivPlugin_div_result[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24647 Q=CsrPlugin_mcause_interrupt +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23267 Q=CsrPlugin_mtval[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23265 Q=CsrPlugin_mtval[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23263 Q=CsrPlugin_mtval[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23261 Q=CsrPlugin_mtval[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23259 Q=CsrPlugin_mtval[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23257 Q=CsrPlugin_mtval[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23255 Q=CsrPlugin_mtval[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23253 Q=CsrPlugin_mtval[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23251 Q=CsrPlugin_mtval[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23249 Q=CsrPlugin_mtval[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23247 Q=CsrPlugin_mtval[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23245 Q=CsrPlugin_mtval[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23243 Q=CsrPlugin_mtval[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23241 Q=CsrPlugin_mtval[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23239 Q=CsrPlugin_mtval[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23237 Q=CsrPlugin_mtval[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23235 Q=CsrPlugin_mtval[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23233 Q=CsrPlugin_mtval[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23231 Q=CsrPlugin_mtval[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23229 Q=CsrPlugin_mtval[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23227 Q=CsrPlugin_mtval[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23225 Q=CsrPlugin_mtval[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23223 Q=CsrPlugin_mtval[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23221 Q=CsrPlugin_mtval[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23219 Q=CsrPlugin_mtval[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23217 Q=CsrPlugin_mtval[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23215 Q=CsrPlugin_mtval[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23213 Q=CsrPlugin_mtval[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23211 Q=CsrPlugin_mtval[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23209 Q=CsrPlugin_mtval[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23207 Q=CsrPlugin_mtval[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24645 Q=CsrPlugin_mtval[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23205 Q=BranchPlugin_branchExceptionPort_payload_badAddr[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23203 Q=BranchPlugin_branchExceptionPort_payload_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23201 Q=BranchPlugin_branchExceptionPort_payload_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23199 Q=BranchPlugin_branchExceptionPort_payload_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23197 Q=BranchPlugin_branchExceptionPort_payload_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23195 Q=BranchPlugin_branchExceptionPort_payload_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23193 Q=BranchPlugin_branchExceptionPort_payload_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23191 Q=BranchPlugin_branchExceptionPort_payload_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23189 Q=BranchPlugin_branchExceptionPort_payload_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23187 Q=BranchPlugin_branchExceptionPort_payload_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23185 Q=BranchPlugin_branchExceptionPort_payload_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23183 Q=BranchPlugin_branchExceptionPort_payload_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23181 Q=BranchPlugin_branchExceptionPort_payload_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23179 Q=BranchPlugin_branchExceptionPort_payload_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23177 Q=BranchPlugin_branchExceptionPort_payload_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23175 Q=BranchPlugin_branchExceptionPort_payload_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23173 Q=BranchPlugin_branchExceptionPort_payload_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23171 Q=BranchPlugin_branchExceptionPort_payload_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23169 Q=BranchPlugin_branchExceptionPort_payload_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23167 Q=BranchPlugin_branchExceptionPort_payload_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23165 Q=BranchPlugin_branchExceptionPort_payload_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23163 Q=BranchPlugin_branchExceptionPort_payload_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23161 Q=BranchPlugin_branchExceptionPort_payload_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23159 Q=BranchPlugin_branchExceptionPort_payload_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23157 Q=BranchPlugin_branchExceptionPort_payload_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23155 Q=BranchPlugin_branchExceptionPort_payload_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23153 Q=BranchPlugin_branchExceptionPort_payload_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23151 Q=BranchPlugin_branchExceptionPort_payload_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23149 Q=BranchPlugin_branchExceptionPort_payload_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23147 Q=BranchPlugin_branchExceptionPort_payload_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24873 Q=BranchPlugin_branchExceptionPort_payload_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23145 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23143 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23141 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23139 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23137 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23135 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23133 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23131 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23129 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23127 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23125 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23123 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23121 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23119 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23117 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23115 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23113 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23111 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23109 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23107 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23105 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23103 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23101 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23099 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23097 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23095 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23093 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23091 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23089 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23087 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23085 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24643 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23083 Q=IBusCachedPlugin_cache.lineLoader_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23081 Q=IBusCachedPlugin_cache.lineLoader_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23079 Q=IBusCachedPlugin_cache.lineLoader_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23077 Q=iBus_cmd_payload_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23075 Q=iBus_cmd_payload_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23073 Q=iBus_cmd_payload_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23071 Q=iBus_cmd_payload_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23069 Q=iBus_cmd_payload_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23067 Q=iBus_cmd_payload_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23065 Q=iBus_cmd_payload_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23063 Q=iBus_cmd_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23061 Q=iBus_cmd_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23059 Q=iBus_cmd_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23057 Q=iBus_cmd_payload_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23055 Q=iBus_cmd_payload_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23053 Q=iBus_cmd_payload_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23051 Q=iBus_cmd_payload_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23049 Q=iBus_cmd_payload_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23047 Q=iBus_cmd_payload_address[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23045 Q=iBus_cmd_payload_address[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23043 Q=iBus_cmd_payload_address[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23041 Q=iBus_cmd_payload_address[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23039 Q=iBus_cmd_payload_address[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23037 Q=iBus_cmd_payload_address[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23035 Q=iBus_cmd_payload_address[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23033 Q=iBus_cmd_payload_address[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23031 Q=iBus_cmd_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23029 Q=iBus_cmd_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23027 Q=iBus_cmd_payload_address[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24887 Q=iBus_cmd_payload_address[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23025 Q=DBusCachedPlugin_redoBranch_payload[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23023 Q=DBusCachedPlugin_redoBranch_payload[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23021 Q=DBusCachedPlugin_redoBranch_payload[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23019 Q=DBusCachedPlugin_redoBranch_payload[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23017 Q=DBusCachedPlugin_redoBranch_payload[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23015 Q=DBusCachedPlugin_redoBranch_payload[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23013 Q=DBusCachedPlugin_redoBranch_payload[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23011 Q=DBusCachedPlugin_redoBranch_payload[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23009 Q=DBusCachedPlugin_redoBranch_payload[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23007 Q=DBusCachedPlugin_redoBranch_payload[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23005 Q=DBusCachedPlugin_redoBranch_payload[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23003 Q=DBusCachedPlugin_redoBranch_payload[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$23001 Q=DBusCachedPlugin_redoBranch_payload[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22999 Q=DBusCachedPlugin_redoBranch_payload[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22997 Q=DBusCachedPlugin_redoBranch_payload[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22995 Q=DBusCachedPlugin_redoBranch_payload[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22993 Q=DBusCachedPlugin_redoBranch_payload[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22991 Q=DBusCachedPlugin_redoBranch_payload[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22989 Q=DBusCachedPlugin_redoBranch_payload[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22987 Q=DBusCachedPlugin_redoBranch_payload[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22985 Q=DBusCachedPlugin_redoBranch_payload[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22983 Q=DBusCachedPlugin_redoBranch_payload[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22981 Q=DBusCachedPlugin_redoBranch_payload[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22979 Q=DBusCachedPlugin_redoBranch_payload[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22977 Q=DBusCachedPlugin_redoBranch_payload[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22975 Q=DBusCachedPlugin_redoBranch_payload[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22973 Q=DBusCachedPlugin_redoBranch_payload[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22971 Q=DBusCachedPlugin_redoBranch_payload[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22969 Q=DBusCachedPlugin_redoBranch_payload[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24897 Q=DBusCachedPlugin_redoBranch_payload[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22953 Q=_zz_execute_BranchPlugin_branch_src2_10 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22951 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22949 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22947 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22945 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22943 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22941 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22939 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22937 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22935 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22933 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22931 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22929 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22927 Q=_zz_execute_BranchPlugin_branch_src2_8 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22925 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22923 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22921 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22919 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22917 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22915 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22913 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22911 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22909 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22907 Q=_zz__zz_execute_BranchPlugin_branch_src2_2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24633 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22891 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22889 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22887 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22885 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22883 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22881 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22879 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22877 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22849 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22847 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22829 Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22827 Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22825 Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22823 Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22821 Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22819 Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22817 Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22815 Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22787 Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22785 Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24627 Q=decode_to_execute_PREDICTION_CONTEXT_hazard +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22781 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24625 Q=decode_to_execute_PREDICTION_CONTEXT_line_history[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24623 Q=execute_to_memory_PREDICTION_CONTEXT_hazard +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22779 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24621 Q=execute_to_memory_PREDICTION_CONTEXT_line_history[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22777 Q=_zz_execute_SRC1_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24619 Q=_zz_execute_SRC1_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24617 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24615 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24613 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24611 Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22775 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24609 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24605 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22773 Q=_zz_execute_SRC2_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24607 Q=_zz_execute_SRC2_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24601 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24599 Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24597 Q=decode_to_execute_BYPASSABLE_EXECUTE_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24595 Q=decode_to_execute_BYPASSABLE_MEMORY_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24593 Q=execute_to_memory_BYPASSABLE_MEMORY_STAGE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24591 Q=decode_to_execute_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24589 Q=execute_to_memory_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24587 Q=memory_to_writeBack_MEMORY_WR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24585 Q=decode_to_execute_MEMORY_MANAGMENT +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24583 Q=decode_to_execute_IS_SFENCE_VMA2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24581 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22771 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24579 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22769 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24577 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22767 Q=_zz_memory_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24575 Q=_zz_memory_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24573 Q=decode_to_execute_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24571 Q=execute_to_memory_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24569 Q=memory_to_writeBack_IS_MUL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24567 Q=decode_to_execute_IS_DIV +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24565 Q=execute_to_memory_IS_DIV +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24563 Q=decode_to_execute_IS_RS1_SIGNED +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24561 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24559 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24557 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24555 Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22765 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24553 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22763 Q=_zz_memory_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24551 Q=_zz_memory_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22761 Q=execute_RS1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22759 Q=execute_RS1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22757 Q=execute_RS1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22755 Q=execute_RS1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22753 Q=execute_RS1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22751 Q=execute_RS1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22749 Q=execute_RS1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22747 Q=execute_RS1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22745 Q=execute_RS1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22743 Q=execute_RS1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22741 Q=execute_RS1[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22739 Q=execute_RS1[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22737 Q=execute_RS1[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22735 Q=execute_RS1[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22733 Q=execute_RS1[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22731 Q=execute_RS1[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22729 Q=execute_RS1[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22727 Q=execute_RS1[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22725 Q=execute_RS1[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22723 Q=execute_RS1[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22721 Q=execute_RS1[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22719 Q=execute_RS1[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22717 Q=execute_RS1[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22715 Q=execute_RS1[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22713 Q=execute_RS1[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22711 Q=execute_RS1[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22709 Q=execute_RS1[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22707 Q=execute_RS1[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22705 Q=execute_RS1[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22703 Q=execute_RS1[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22701 Q=execute_RS1[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24549 Q=execute_RS1[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22699 Q=execute_RS2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22697 Q=execute_RS2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22695 Q=execute_RS2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22693 Q=execute_RS2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22691 Q=execute_RS2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22689 Q=execute_RS2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22687 Q=execute_RS2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22685 Q=execute_RS2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22683 Q=execute_RS2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22681 Q=execute_RS2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22679 Q=execute_RS2[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22677 Q=execute_RS2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22675 Q=execute_RS2[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22673 Q=execute_RS2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22671 Q=execute_RS2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22669 Q=execute_RS2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22667 Q=execute_RS2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22665 Q=execute_RS2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22663 Q=execute_RS2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22661 Q=execute_RS2[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22659 Q=execute_RS2[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22657 Q=execute_RS2[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22655 Q=execute_RS2[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22653 Q=execute_RS2[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22651 Q=execute_RS2[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22649 Q=execute_RS2[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22647 Q=execute_RS2[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22645 Q=execute_RS2[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22643 Q=execute_RS2[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22641 Q=execute_RS2[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22639 Q=execute_RS2[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24547 Q=execute_RS2[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24545 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24543 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24541 Q=decode_to_execute_DO_EBREAK +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24539 Q=decode_to_execute_PREDICTION_HAD_BRANCHED2 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22637 Q=execute_to_memory_MEMORY_STORE_DATA_RF[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22635 Q=execute_to_memory_MEMORY_STORE_DATA_RF[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22633 Q=execute_to_memory_MEMORY_STORE_DATA_RF[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22631 Q=execute_to_memory_MEMORY_STORE_DATA_RF[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22629 Q=execute_to_memory_MEMORY_STORE_DATA_RF[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22627 Q=execute_to_memory_MEMORY_STORE_DATA_RF[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22625 Q=execute_to_memory_MEMORY_STORE_DATA_RF[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22623 Q=execute_to_memory_MEMORY_STORE_DATA_RF[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22621 Q=execute_to_memory_MEMORY_STORE_DATA_RF[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22619 Q=execute_to_memory_MEMORY_STORE_DATA_RF[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22617 Q=execute_to_memory_MEMORY_STORE_DATA_RF[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22615 Q=execute_to_memory_MEMORY_STORE_DATA_RF[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22613 Q=execute_to_memory_MEMORY_STORE_DATA_RF[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22611 Q=execute_to_memory_MEMORY_STORE_DATA_RF[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22609 Q=execute_to_memory_MEMORY_STORE_DATA_RF[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22607 Q=execute_to_memory_MEMORY_STORE_DATA_RF[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22605 Q=execute_to_memory_MEMORY_STORE_DATA_RF[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22603 Q=execute_to_memory_MEMORY_STORE_DATA_RF[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22601 Q=execute_to_memory_MEMORY_STORE_DATA_RF[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22599 Q=execute_to_memory_MEMORY_STORE_DATA_RF[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22597 Q=execute_to_memory_MEMORY_STORE_DATA_RF[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22595 Q=execute_to_memory_MEMORY_STORE_DATA_RF[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22593 Q=execute_to_memory_MEMORY_STORE_DATA_RF[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22591 Q=execute_to_memory_MEMORY_STORE_DATA_RF[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22589 Q=execute_to_memory_MEMORY_STORE_DATA_RF[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22587 Q=execute_to_memory_MEMORY_STORE_DATA_RF[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22585 Q=execute_to_memory_MEMORY_STORE_DATA_RF[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22583 Q=execute_to_memory_MEMORY_STORE_DATA_RF[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22581 Q=execute_to_memory_MEMORY_STORE_DATA_RF[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22579 Q=execute_to_memory_MEMORY_STORE_DATA_RF[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22577 Q=execute_to_memory_MEMORY_STORE_DATA_RF[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24537 Q=execute_to_memory_MEMORY_STORE_DATA_RF[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22575 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22573 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22571 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22569 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22567 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22565 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22563 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22561 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22559 Q=dBus_cmd_payload_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22557 Q=dBus_cmd_payload_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22555 Q=dBus_cmd_payload_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22553 Q=dBus_cmd_payload_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22551 Q=dBus_cmd_payload_data[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22549 Q=dBus_cmd_payload_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22547 Q=dBus_cmd_payload_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22545 Q=dBus_cmd_payload_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22543 Q=dBus_cmd_payload_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22541 Q=dBus_cmd_payload_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22539 Q=dBus_cmd_payload_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22537 Q=dBus_cmd_payload_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22535 Q=dBus_cmd_payload_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22533 Q=dBus_cmd_payload_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22531 Q=dBus_cmd_payload_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22529 Q=dBus_cmd_payload_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22527 Q=dBus_cmd_payload_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22525 Q=dBus_cmd_payload_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22523 Q=dBus_cmd_payload_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22521 Q=dBus_cmd_payload_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22519 Q=dBus_cmd_payload_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22517 Q=dBus_cmd_payload_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22515 Q=dBus_cmd_payload_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24535 Q=dBus_cmd_payload_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22513 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22511 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22509 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22507 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22505 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22503 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22501 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22499 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22497 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22495 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22493 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22491 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22489 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22487 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22485 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22483 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22481 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22479 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22477 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22475 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22473 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22471 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22469 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22467 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22465 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22463 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22461 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22459 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22457 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22455 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22453 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24533 Q=DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22451 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22449 Q=_zz_writeBack_DBusCachedPlugin_rspShifted_3 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22447 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22445 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22443 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22441 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22439 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22437 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22435 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22433 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22431 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22429 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22427 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22425 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22423 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22421 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22419 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22417 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22415 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22413 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22411 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22409 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22407 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22405 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22403 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22401 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22399 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22397 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22395 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22393 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22391 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24531 Q=DBusCachedPlugin_exceptionBus_payload_badAddr[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22389 Q=_zz_decode_RS2_3[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22387 Q=_zz_decode_RS2_3[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22385 Q=_zz_decode_RS2_3[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22383 Q=_zz_decode_RS2_3[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22381 Q=_zz_decode_RS2_3[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22379 Q=_zz_decode_RS2_3[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22377 Q=_zz_decode_RS2_3[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22375 Q=_zz_decode_RS2_3[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22373 Q=_zz_decode_RS2_3[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22371 Q=_zz_decode_RS2_3[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22369 Q=_zz_decode_RS2_3[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22367 Q=_zz_decode_RS2_3[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22365 Q=_zz_decode_RS2_3[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22363 Q=_zz_decode_RS2_3[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22361 Q=_zz_decode_RS2_3[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22359 Q=_zz_decode_RS2_3[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22357 Q=_zz_decode_RS2_3[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22355 Q=_zz_decode_RS2_3[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22353 Q=_zz_decode_RS2_3[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22351 Q=_zz_decode_RS2_3[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22349 Q=_zz_decode_RS2_3[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22347 Q=_zz_decode_RS2_3[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22345 Q=_zz_decode_RS2_3[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22343 Q=_zz_decode_RS2_3[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22341 Q=_zz_decode_RS2_3[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22339 Q=_zz_decode_RS2_3[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22337 Q=_zz_decode_RS2_3[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22335 Q=_zz_decode_RS2_3[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22333 Q=_zz_decode_RS2_3[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22331 Q=_zz_decode_RS2_3[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22329 Q=_zz_decode_RS2_3[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24529 Q=_zz_decode_RS2_3[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22327 Q=_zz_memory_MUL_LOW_1[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22325 Q=_zz_memory_MUL_LOW_1[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22323 Q=_zz_memory_MUL_LOW_1[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22321 Q=_zz_memory_MUL_LOW_1[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22319 Q=_zz_memory_MUL_LOW_1[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22317 Q=_zz_memory_MUL_LOW_1[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22315 Q=_zz_memory_MUL_LOW_1[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22313 Q=_zz_memory_MUL_LOW_1[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22311 Q=_zz_memory_MUL_LOW_1[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22309 Q=_zz_memory_MUL_LOW_1[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22307 Q=_zz_memory_MUL_LOW_1[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22305 Q=_zz_memory_MUL_LOW_1[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22303 Q=_zz_memory_MUL_LOW_1[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22301 Q=_zz_memory_MUL_LOW_1[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22299 Q=_zz_memory_MUL_LOW_1[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22297 Q=_zz_memory_MUL_LOW_1[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22295 Q=_zz_memory_MUL_LOW_1[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22293 Q=_zz_memory_MUL_LOW_1[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22291 Q=_zz_memory_MUL_LOW_1[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22289 Q=_zz_memory_MUL_LOW_1[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22287 Q=_zz_memory_MUL_LOW_1[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22285 Q=_zz_memory_MUL_LOW_1[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22283 Q=_zz_memory_MUL_LOW_1[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22281 Q=_zz_memory_MUL_LOW_1[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22279 Q=_zz_memory_MUL_LOW_1[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22277 Q=_zz_memory_MUL_LOW_1[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22275 Q=_zz_memory_MUL_LOW_1[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22273 Q=_zz_memory_MUL_LOW_1[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22271 Q=_zz_memory_MUL_LOW_1[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22269 Q=_zz_memory_MUL_LOW_1[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22267 Q=_zz_memory_MUL_LOW_1[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24527 Q=_zz_memory_MUL_LOW_1[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22265 Q=_zz_memory_MUL_LOW_4[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22263 Q=_zz_memory_MUL_LOW_4[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22261 Q=_zz_memory_MUL_LOW_4[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22259 Q=_zz_memory_MUL_LOW_4[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22257 Q=_zz_memory_MUL_LOW_4[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22255 Q=_zz_memory_MUL_LOW_4[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22253 Q=_zz_memory_MUL_LOW_4[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22251 Q=_zz_memory_MUL_LOW_4[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22249 Q=_zz_memory_MUL_LOW_4[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22247 Q=_zz_memory_MUL_LOW_4[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22245 Q=_zz_memory_MUL_LOW_4[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22243 Q=_zz_memory_MUL_LOW_4[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22241 Q=_zz_memory_MUL_LOW_4[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22239 Q=_zz_memory_MUL_LOW_4[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22237 Q=_zz_memory_MUL_LOW_4[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22235 Q=_zz_memory_MUL_LOW_4[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22233 Q=_zz_memory_MUL_LOW_4[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22231 Q=_zz_memory_MUL_LOW_4[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22229 Q=_zz_memory_MUL_LOW_4[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22227 Q=_zz_memory_MUL_LOW_4[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22225 Q=_zz_memory_MUL_LOW_4[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22223 Q=_zz_memory_MUL_LOW_4[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22221 Q=_zz_memory_MUL_LOW_4[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22219 Q=_zz_memory_MUL_LOW_4[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22217 Q=_zz_memory_MUL_LOW_4[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22215 Q=_zz_memory_MUL_LOW_4[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22213 Q=_zz_memory_MUL_LOW_4[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22211 Q=_zz_memory_MUL_LOW_4[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22209 Q=_zz_memory_MUL_LOW_4[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22207 Q=_zz_memory_MUL_LOW_4[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22205 Q=_zz_memory_MUL_LOW_4[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22203 Q=_zz_memory_MUL_LOW_4[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22201 Q=_zz_memory_MUL_LOW_4[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24525 Q=_zz_memory_MUL_LOW_4[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22199 Q=_zz_memory_MUL_LOW_6[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22197 Q=_zz_memory_MUL_LOW_6[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22195 Q=_zz_memory_MUL_LOW_6[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22193 Q=_zz_memory_MUL_LOW_6[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22191 Q=_zz_memory_MUL_LOW_6[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22189 Q=_zz_memory_MUL_LOW_6[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22187 Q=_zz_memory_MUL_LOW_6[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22185 Q=_zz_memory_MUL_LOW_6[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22183 Q=_zz_memory_MUL_LOW_6[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22181 Q=_zz_memory_MUL_LOW_6[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22179 Q=_zz_memory_MUL_LOW_6[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22177 Q=_zz_memory_MUL_LOW_6[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22175 Q=_zz_memory_MUL_LOW_6[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22173 Q=_zz_memory_MUL_LOW_6[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22171 Q=_zz_memory_MUL_LOW_6[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22169 Q=_zz_memory_MUL_LOW_6[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22167 Q=_zz_memory_MUL_LOW_6[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22165 Q=_zz_memory_MUL_LOW_6[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22163 Q=_zz_memory_MUL_LOW_6[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22161 Q=_zz_memory_MUL_LOW_6[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22159 Q=_zz_memory_MUL_LOW_6[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22157 Q=_zz_memory_MUL_LOW_6[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22155 Q=_zz_memory_MUL_LOW_6[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22153 Q=_zz_memory_MUL_LOW_6[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22151 Q=_zz_memory_MUL_LOW_6[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22149 Q=_zz_memory_MUL_LOW_6[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22147 Q=_zz_memory_MUL_LOW_6[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22145 Q=_zz_memory_MUL_LOW_6[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22143 Q=_zz_memory_MUL_LOW_6[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22141 Q=_zz_memory_MUL_LOW_6[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22139 Q=_zz_memory_MUL_LOW_6[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22137 Q=_zz_memory_MUL_LOW_6[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22135 Q=_zz_memory_MUL_LOW_6[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24523 Q=_zz_memory_MUL_LOW_6[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22133 Q=execute_to_memory_MUL_HH[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22131 Q=execute_to_memory_MUL_HH[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22129 Q=execute_to_memory_MUL_HH[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22127 Q=execute_to_memory_MUL_HH[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22125 Q=execute_to_memory_MUL_HH[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22123 Q=execute_to_memory_MUL_HH[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22121 Q=execute_to_memory_MUL_HH[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22119 Q=execute_to_memory_MUL_HH[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22117 Q=execute_to_memory_MUL_HH[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22115 Q=execute_to_memory_MUL_HH[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22113 Q=execute_to_memory_MUL_HH[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22111 Q=execute_to_memory_MUL_HH[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22109 Q=execute_to_memory_MUL_HH[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22107 Q=execute_to_memory_MUL_HH[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22105 Q=execute_to_memory_MUL_HH[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22103 Q=execute_to_memory_MUL_HH[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22101 Q=execute_to_memory_MUL_HH[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22099 Q=execute_to_memory_MUL_HH[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22097 Q=execute_to_memory_MUL_HH[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22095 Q=execute_to_memory_MUL_HH[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22093 Q=execute_to_memory_MUL_HH[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22091 Q=execute_to_memory_MUL_HH[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22089 Q=execute_to_memory_MUL_HH[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22087 Q=execute_to_memory_MUL_HH[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22085 Q=execute_to_memory_MUL_HH[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22083 Q=execute_to_memory_MUL_HH[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22081 Q=execute_to_memory_MUL_HH[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22079 Q=execute_to_memory_MUL_HH[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22077 Q=execute_to_memory_MUL_HH[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22075 Q=execute_to_memory_MUL_HH[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22073 Q=execute_to_memory_MUL_HH[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22071 Q=execute_to_memory_MUL_HH[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22067 Q=_zz_writeBack_MulPlugin_result_1[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22065 Q=_zz_writeBack_MulPlugin_result_1[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22063 Q=_zz_writeBack_MulPlugin_result_1[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22061 Q=_zz_writeBack_MulPlugin_result_1[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22059 Q=_zz_writeBack_MulPlugin_result_1[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22057 Q=_zz_writeBack_MulPlugin_result_1[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22055 Q=_zz_writeBack_MulPlugin_result_1[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22053 Q=_zz_writeBack_MulPlugin_result_1[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22051 Q=_zz_writeBack_MulPlugin_result_1[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22049 Q=_zz_writeBack_MulPlugin_result_1[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22047 Q=_zz_writeBack_MulPlugin_result_1[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22045 Q=_zz_writeBack_MulPlugin_result_1[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22043 Q=_zz_writeBack_MulPlugin_result_1[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22041 Q=_zz_writeBack_MulPlugin_result_1[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22039 Q=_zz_writeBack_MulPlugin_result_1[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22037 Q=_zz_writeBack_MulPlugin_result_1[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22035 Q=_zz_writeBack_MulPlugin_result_1[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22033 Q=_zz_writeBack_MulPlugin_result_1[49] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22031 Q=_zz_writeBack_MulPlugin_result_1[50] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22029 Q=_zz_writeBack_MulPlugin_result_1[51] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22027 Q=_zz_writeBack_MulPlugin_result_1[52] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22025 Q=_zz_writeBack_MulPlugin_result_1[53] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22023 Q=_zz_writeBack_MulPlugin_result_1[54] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22021 Q=_zz_writeBack_MulPlugin_result_1[55] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22019 Q=_zz_writeBack_MulPlugin_result_1[56] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22017 Q=_zz_writeBack_MulPlugin_result_1[57] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22015 Q=_zz_writeBack_MulPlugin_result_1[58] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22013 Q=_zz_writeBack_MulPlugin_result_1[59] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22011 Q=_zz_writeBack_MulPlugin_result_1[60] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22009 Q=_zz_writeBack_MulPlugin_result_1[61] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22007 Q=_zz_writeBack_MulPlugin_result_1[62] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22005 Q=_zz_writeBack_MulPlugin_result_1[63] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24517 Q=execute_to_memory_BRANCH_DO +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$22001 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21999 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[3] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21997 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[4] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21995 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[5] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21993 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[6] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21991 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[7] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21989 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[8] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21987 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[9] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21985 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[10] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21983 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[11] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21981 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[12] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21979 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[13] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21977 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[14] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21975 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[15] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21973 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[16] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21971 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[17] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21969 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[18] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21967 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[19] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21965 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[20] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21963 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[21] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21961 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[22] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21959 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[23] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21957 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[24] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21955 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[25] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21953 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[26] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21951 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[27] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21949 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[28] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21947 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[29] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21945 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[30] R=reset +.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24875 Q=IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[31] S=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21943 Q=_zz__zz_decode_RS2_2[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21941 Q=_zz__zz_decode_RS2_2[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21939 Q=_zz__zz_decode_RS2_2[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21937 Q=_zz__zz_decode_RS2_2[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21935 Q=_zz__zz_decode_RS2_2[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21933 Q=_zz__zz_decode_RS2_2[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21931 Q=_zz__zz_decode_RS2_2[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21929 Q=_zz__zz_decode_RS2_2[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21927 Q=_zz__zz_decode_RS2_2[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21925 Q=_zz__zz_decode_RS2_2[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21923 Q=_zz__zz_decode_RS2_2[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21921 Q=_zz__zz_decode_RS2_2[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21919 Q=_zz__zz_decode_RS2_2[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21917 Q=_zz__zz_decode_RS2_2[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21915 Q=_zz__zz_decode_RS2_2[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21913 Q=_zz__zz_decode_RS2_2[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21911 Q=_zz__zz_decode_RS2_2[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21909 Q=_zz__zz_decode_RS2_2[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21907 Q=_zz__zz_decode_RS2_2[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21905 Q=_zz__zz_decode_RS2_2[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21903 Q=_zz__zz_decode_RS2_2[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21901 Q=_zz__zz_decode_RS2_2[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21899 Q=_zz__zz_decode_RS2_2[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21897 Q=_zz__zz_decode_RS2_2[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21895 Q=_zz__zz_decode_RS2_2[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21893 Q=_zz__zz_decode_RS2_2[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21891 Q=_zz__zz_decode_RS2_2[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21889 Q=_zz__zz_decode_RS2_2[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21887 Q=_zz__zz_decode_RS2_2[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21885 Q=_zz__zz_decode_RS2_2[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21883 Q=_zz__zz_decode_RS2_2[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21881 Q=_zz__zz_decode_RS2_2[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21879 Q=_zz_writeBack_MulPlugin_result[32] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21877 Q=_zz_writeBack_MulPlugin_result[33] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21875 Q=_zz_writeBack_MulPlugin_result[34] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21873 Q=_zz_writeBack_MulPlugin_result[35] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21871 Q=_zz_writeBack_MulPlugin_result[36] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21869 Q=_zz_writeBack_MulPlugin_result[37] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21867 Q=_zz_writeBack_MulPlugin_result[38] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21865 Q=_zz_writeBack_MulPlugin_result[39] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21863 Q=_zz_writeBack_MulPlugin_result[40] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21861 Q=_zz_writeBack_MulPlugin_result[41] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21859 Q=_zz_writeBack_MulPlugin_result[42] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21857 Q=_zz_writeBack_MulPlugin_result[43] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21855 Q=_zz_writeBack_MulPlugin_result[44] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21853 Q=_zz_writeBack_MulPlugin_result[45] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21851 Q=_zz_writeBack_MulPlugin_result[46] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21849 Q=_zz_writeBack_MulPlugin_result[47] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21847 Q=_zz_writeBack_MulPlugin_result[48] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21845 Q=_zz_writeBack_MulPlugin_result[49] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21843 Q=_zz_writeBack_MulPlugin_result[50] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24515 Q=_zz_writeBack_MulPlugin_result[65] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24513 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24511 Q=execute_CsrPlugin_csr_256 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24509 Q=execute_CsrPlugin_csr_384 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24507 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24505 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24503 Q=execute_CsrPlugin_csr_833 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24501 Q=execute_CsrPlugin_csr_834 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24499 Q=execute_CsrPlugin_csr_835 +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24497 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24495 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24493 Q=lastStageIsValid R=reset +.subckt dffr C=clk D=$true Q=IBusCachedPlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24491 Q=IBusCachedPlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24489 Q=IBusCachedPlugin_cache.io_cpu_fetch_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24487 Q=IBusCachedPlugin_cache.io_cpu_decode_isValid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24485 Q=IBusCachedPlugin_injector_nextPcCalc_valids_0 R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_sum[0:0] Q=MmuPlugin_status_sum R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_mxr[0:0] Q=MmuPlugin_status_mxr R=reset +.subckt dffr C=clk D=$0\MmuPlugin_status_mprv[0:0] Q=MmuPlugin_status_mprv R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24483 Q=IBusCachedPlugin_iBusRsp_readyForError R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_0_valid[0:0] Q=MmuPlugin_ports_1_cache_0_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_1_valid[0:0] Q=MmuPlugin_ports_1_cache_1_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_2_valid[0:0] Q=MmuPlugin_ports_1_cache_2_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_3_valid[0:0] Q=MmuPlugin_ports_1_cache_3_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_4_valid[0:0] Q=MmuPlugin_ports_1_cache_4_valid R=reset +.subckt dffr C=clk D=$0\MmuPlugin_ports_1_cache_5_valid[0:0] Q=MmuPlugin_ports_1_cache_5_valid R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[0] Q=MmuPlugin_ports_1_entryToReplace_value[0] R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[1] Q=MmuPlugin_ports_1_entryToReplace_value[1] R=reset +.subckt dffr C=clk D=MmuPlugin_ports_1_entryToReplace_valueNext[2] Q=MmuPlugin_ports_1_entryToReplace_value[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24481 Q=MmuPlugin_satp_mode R=reset +.subckt dffr C=clk D=MmuPlugin_dBusAccess_rsp_valid Q=MmuPlugin_shared_dBusRspStaged_valid R=reset +.subckt dffs C=clk D=$false Q=_zz_14 S=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[0] Q=memory_DivPlugin_div_counter_value[0] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[1] Q=memory_DivPlugin_div_counter_value[1] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[2] Q=memory_DivPlugin_div_counter_value[2] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[3] Q=memory_DivPlugin_div_counter_value[3] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[4] Q=memory_DivPlugin_div_counter_value[4] R=reset +.subckt dffr C=clk D=memory_DivPlugin_div_counter_valueNext[5] Q=memory_DivPlugin_div_counter_value[5] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21841 Q=MmuPlugin_shared_state_1[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21839 Q=MmuPlugin_shared_state_1[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24479 Q=MmuPlugin_shared_state_1[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24477 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24475 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode[0:0] Q=CsrPlugin_exceptionPendings_0 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0] Q=CsrPlugin_exceptionPendings_1 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0] Q=CsrPlugin_exceptionPendings_2 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0] Q=CsrPlugin_exceptionPendings_3 R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24473 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24471 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24469 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffr C=clk D=CsrPlugin_exception Q=CsrPlugin_hadException R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24467 Q=CsrPlugin_pipelineLiberator_pcValids_2 R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24465 Q=DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24463 Q=memory_to_writeBack_IS_DBUS_SHARING R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21837 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21835 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24461 Q=IBusCachedPlugin_cache._zz_when_Fetcher_l411[2] R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21833 Q=DebugPlugin_busReadDataReg[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24891 Q=DebugPlugin_busReadDataReg[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21829 Q=dataCache_1.stageA_request_size[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24837 Q=dataCache_1.stageA_request_size[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24839 Q=dataCache_1.io_cpu_memory_isWrite +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24841 Q=dataCache_1.loader_error R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24843 Q=dataCache_1.io_cpu_execute_refilling R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[0] Q=dataCache_1.loader_counter_value[0] R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[1] Q=dataCache_1.loader_counter_value[1] R=reset +.subckt dffr C=clk D=dataCache_1.loader_counter_valueNext[2] Q=dataCache_1.loader_counter_value[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21827 Q=dataCache_1.stageB_flusher_counter[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21825 Q=dataCache_1.stageB_flusher_counter[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21823 Q=dataCache_1.stageB_flusher_counter[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21821 Q=dataCache_1.stageB_flusher_counter[3] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21819 Q=dataCache_1.stageB_flusher_counter[4] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21817 Q=dataCache_1.stageB_flusher_counter[5] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24845 Q=dataCache_1.stageB_flusher_counter[6] R=reset +.subckt dffs C=clk D=$abc$27210$flatten\dataCache_1.$0\stageB_flusher_start[0:0] Q=dataCache_1.stageB_flusher_start S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24847 Q=dataCache_1.stageB_flusher_waitDone R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24849 Q=dataCache_1.memCmdSent R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24797 Q=dataCache_1.stageB_unaligned +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24795 Q=dataCache_1.stageB_waysHit +.subckt dff C=clk D=dataCache_1.io_cpu_execute_refilling Q=dataCache_1.loader_valid_regNext +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21815 Q=dataCache_1.stageA_mask[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21813 Q=dataCache_1.stageA_mask[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21811 Q=dataCache_1.stageA_mask[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24835 Q=dataCache_1.stageA_mask[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24833 Q=dataCache_1.stage0_dataColisions_regNextWhen +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24831 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21809 Q=dataCache_1.stageB_request_size[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24829 Q=dataCache_1.stageB_request_size[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24825 Q=dBus_cmd_payload_uncached +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21807 Q=dataCache_1.stageB_mmuRsp_physicalAddress[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21805 Q=dataCache_1.stageB_mmuRsp_physicalAddress[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21803 Q=dataCache_1.stageB_mmuRsp_physicalAddress[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21801 Q=dataCache_1.stageB_mmuRsp_physicalAddress[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21799 Q=dataCache_1.stageB_mmuRsp_physicalAddress[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21797 Q=dBus_cmd_payload_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21795 Q=dBus_cmd_payload_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21793 Q=dBus_cmd_payload_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21791 Q=dBus_cmd_payload_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21789 Q=dBus_cmd_payload_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21787 Q=dBus_cmd_payload_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21785 Q=dBus_cmd_payload_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21783 Q=dBus_cmd_payload_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21781 Q=dBus_cmd_payload_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21779 Q=dBus_cmd_payload_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21777 Q=dBus_cmd_payload_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21775 Q=dBus_cmd_payload_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21773 Q=dBus_cmd_payload_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21771 Q=dBus_cmd_payload_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21769 Q=dBus_cmd_payload_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21767 Q=dBus_cmd_payload_address[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21765 Q=dBus_cmd_payload_address[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21763 Q=dBus_cmd_payload_address[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21761 Q=dBus_cmd_payload_address[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21759 Q=dBus_cmd_payload_address[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21757 Q=dBus_cmd_payload_address[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21755 Q=dBus_cmd_payload_address[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21753 Q=dBus_cmd_payload_address[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21751 Q=dBus_cmd_payload_address[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21749 Q=dBus_cmd_payload_address[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21747 Q=dBus_cmd_payload_address[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24827 Q=dBus_cmd_payload_address[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24819 Q=dataCache_1.stageB_mmuRsp_allowRead +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24815 Q=dataCache_1.stageB_mmuRsp_allowWrite +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24811 Q=dataCache_1.stageB_mmuRsp_exception +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24807 Q=dataCache_1.stageB_mmuRsp_refilling +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24821 Q=dataCache_1.stageB_mmuRsp_isPaging +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24803 Q=dataCache_1.stageB_tagsReadRsp_0_error +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21745 Q=dBus_cmd_payload_mask[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21743 Q=dBus_cmd_payload_mask[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21741 Q=dBus_cmd_payload_mask[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24793 Q=dBus_cmd_payload_mask[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21739 Q=dataCache_1.stageB_dataMux[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21737 Q=dataCache_1.stageB_dataMux[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21735 Q=dataCache_1.stageB_dataMux[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21733 Q=dataCache_1.stageB_dataMux[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21731 Q=dataCache_1.stageB_dataMux[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21729 Q=dataCache_1.stageB_dataMux[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21727 Q=dataCache_1.stageB_dataMux[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21725 Q=dataCache_1.stageB_dataMux[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21723 Q=dataCache_1.stageB_dataMux[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21721 Q=dataCache_1.stageB_dataMux[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21719 Q=dataCache_1.stageB_dataMux[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21717 Q=dataCache_1.stageB_dataMux[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21715 Q=dataCache_1.stageB_dataMux[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21713 Q=dataCache_1.stageB_dataMux[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21711 Q=dataCache_1.stageB_dataMux[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21709 Q=dataCache_1.stageB_dataMux[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21707 Q=dataCache_1.stageB_dataMux[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21705 Q=dataCache_1.stageB_dataMux[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21703 Q=dataCache_1.stageB_dataMux[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21701 Q=dataCache_1.stageB_dataMux[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21699 Q=dataCache_1.stageB_dataMux[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21697 Q=dataCache_1.stageB_dataMux[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21695 Q=dataCache_1.stageB_dataMux[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21693 Q=dataCache_1.stageB_dataMux[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21691 Q=dataCache_1.stageB_dataMux[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21689 Q=dataCache_1.stageB_dataMux[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21687 Q=dataCache_1.stageB_dataMux[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21685 Q=dataCache_1.stageB_dataMux[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21683 Q=dataCache_1.stageB_dataMux[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21681 Q=dataCache_1.stageB_dataMux[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$21679 Q=dataCache_1.stageB_dataMux[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24801 Q=dataCache_1.stageB_dataMux[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24799 Q=dataCache_1.stageB_dataColisions +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24899 Q=when_MmuPlugin_l281_1 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24459 Q=DebugPlugin_busReadDataReg[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24457 Q=DebugPlugin_busReadDataReg[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24455 Q=DebugPlugin_busReadDataReg[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24453 Q=debug_bus_rsp_data[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24451 Q=debug_bus_rsp_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24449 Q=debug_bus_rsp_data[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24447 Q=debug_bus_rsp_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24445 Q=debug_bus_rsp_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24443 Q=debug_bus_rsp_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24441 Q=debug_bus_rsp_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24439 Q=debug_bus_rsp_data[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24437 Q=debug_bus_rsp_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24435 Q=debug_bus_rsp_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24433 Q=debug_bus_rsp_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24431 Q=debug_bus_rsp_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24429 Q=debug_bus_rsp_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24427 Q=debug_bus_rsp_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24425 Q=debug_bus_rsp_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24423 Q=debug_bus_rsp_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24421 Q=debug_bus_rsp_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24419 Q=debug_bus_rsp_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24417 Q=debug_bus_rsp_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24415 Q=debug_bus_rsp_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24413 Q=debug_bus_rsp_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24411 Q=debug_bus_rsp_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24409 Q=debug_bus_rsp_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24407 Q=debug_bus_rsp_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24405 Q=debug_bus_rsp_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24403 Q=debug_bus_rsp_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24893 Q=debug_bus_rsp_data[31] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24401 Q=_zz_execute_to_memory_PC[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24399 Q=_zz_execute_to_memory_PC[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24397 Q=_zz_execute_to_memory_PC[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24395 Q=_zz_execute_to_memory_PC[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24393 Q=_zz_execute_to_memory_PC[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24391 Q=_zz_execute_to_memory_PC[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24389 Q=_zz_execute_to_memory_PC[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24387 Q=_zz_execute_to_memory_PC[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24385 Q=_zz_execute_to_memory_PC[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24383 Q=_zz_execute_to_memory_PC[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24381 Q=_zz_execute_to_memory_PC[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24379 Q=_zz_execute_to_memory_PC[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24377 Q=_zz_execute_to_memory_PC[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24375 Q=_zz_execute_to_memory_PC[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24373 Q=_zz_execute_to_memory_PC[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24371 Q=_zz_execute_to_memory_PC[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24369 Q=_zz_execute_to_memory_PC[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24367 Q=_zz_execute_to_memory_PC[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24365 Q=_zz_execute_to_memory_PC[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24363 Q=_zz_execute_to_memory_PC[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24361 Q=_zz_execute_to_memory_PC[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24359 Q=_zz_execute_to_memory_PC[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24357 Q=_zz_execute_to_memory_PC[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24355 Q=_zz_execute_to_memory_PC[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24353 Q=_zz_execute_to_memory_PC[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24351 Q=_zz_execute_to_memory_PC[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24349 Q=_zz_execute_to_memory_PC[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24347 Q=_zz_execute_to_memory_PC[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24345 Q=_zz_execute_to_memory_PC[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24885 Q=_zz_execute_to_memory_PC[31] +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24343 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[0] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24341 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[1] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24851 Q=IBusCachedPlugin_cache.lineLoader_wordIndex[2] R=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24853 Q=IBusCachedPlugin_cache.lineLoader_cmdSent R=reset +.subckt dffs C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24855 Q=IBusCachedPlugin_cache.lineLoader_flushPending S=reset +.subckt dffr C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24857 Q=IBusCachedPlugin_cache.lineLoader_valid R=reset +.subckt dffr C=clk D=$abc$27210$flatten\IBusCachedPlugin_cache.$0\lineLoader_hadError[0:0] Q=IBusCachedPlugin_cache.lineLoader_hadError R=reset +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24339 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24337 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24335 Q=_zz__zz_decode_IS_CSR_85 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24333 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24331 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24329 Q=_zz__zz_decode_IS_CSR_41 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24327 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24325 Q=_zz_IBusCachedPlugin_predictionJumpInterface_payload_6 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24323 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24321 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24319 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24317 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24315 Q=_zz__zz_decode_IS_CSR_21 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24313 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24311 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24309 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24307 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24305 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24303 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24301 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24299 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[20] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24297 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[21] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24295 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[22] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24293 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[23] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24291 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[24] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24289 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[25] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24287 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[26] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24285 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[27] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24283 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[28] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24281 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[29] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24279 Q=IBusCachedPlugin_cache._zz_decodeStage_hit_data[30] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24859 Q=_zz_6 +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24277 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24275 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24273 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[2] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24271 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[3] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24269 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[4] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24267 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[5] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24265 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[6] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24263 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[7] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24261 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[8] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24259 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[9] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24257 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[10] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24255 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[11] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24253 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[12] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24251 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[13] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24249 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[14] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24247 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[15] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24245 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[16] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24243 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[17] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24241 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[18] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24861 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_address[19] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24863 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_error +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24865 Q=IBusCachedPlugin_cache.decodeStage_hit_tags_0_valid +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24239 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[0] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24237 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[1] +.subckt dff C=clk D=$abc$27210$auto$rtlil.cc:2693:MuxGate$24905 Q=CsrPlugin_exceptionPortCtrl_exceptionContext_code[2] +.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_HH[0] Y[42]=execute_MUL_HH[1] Y[41]=execute_MUL_HH[2] Y[40]=execute_MUL_HH[3] Y[39]=execute_MUL_HH[4] Y[38]=execute_MUL_HH[5] Y[37]=execute_MUL_HH[6] Y[36]=execute_MUL_HH[7] Y[35]=execute_MUL_HH[8] Y[34]=execute_MUL_HH[9] Y[33]=execute_MUL_HH[10] Y[32]=execute_MUL_HH[11] Y[31]=execute_MUL_HH[12] Y[30]=execute_MUL_HH[13] Y[29]=execute_MUL_HH[14] Y[28]=execute_MUL_HH[15] Y[27]=execute_MUL_HH[16] Y[26]=execute_MUL_HH[17] Y[25]=execute_MUL_HH[18] Y[24]=execute_MUL_HH[19] Y[23]=execute_MUL_HH[20] Y[22]=execute_MUL_HH[21] Y[21]=execute_MUL_HH[22] Y[20]=execute_MUL_HH[23] Y[19]=execute_MUL_HH[24] Y[18]=execute_MUL_HH[25] Y[17]=execute_MUL_HH[26] Y[16]=execute_MUL_HH[27] Y[15]=execute_MUL_HH[28] Y[14]=execute_MUL_HH[29] Y[13]=execute_MUL_HH[30] Y[12]=execute_MUL_HH[31] Y[11]=execute_MUL_HH[32] Y[10]=execute_MUL_HH[33] Y[9]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[9] Y[8]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[8] Y[7]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[7] Y[6]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[6] Y[5]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[5] Y[4]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[4] Y[3]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[3] Y[2]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[2] Y[1]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[1] Y[0]=$techmap6156$mul$./benchmark/VexRiscv.v:2945$248.Y[0] +.subckt mult24x20 A[23]=execute_RS1[16] A[22]=execute_RS1[17] A[21]=execute_RS1[18] A[20]=execute_RS1[19] A[19]=execute_RS1[20] A[18]=execute_RS1[21] A[17]=execute_RS1[22] A[16]=execute_RS1[23] A[15]=execute_RS1[24] A[14]=execute_RS1[25] A[13]=execute_RS1[26] A[12]=execute_RS1[27] A[11]=execute_RS1[28] A[10]=execute_RS1[29] A[9]=execute_RS1[30] A[8]=execute_RS1[31] A[7]=execute_MulPlugin_aHigh[16] A[6]=execute_MulPlugin_aHigh[16] A[5]=execute_MulPlugin_aHigh[16] A[4]=execute_MulPlugin_aHigh[16] A[3]=execute_MulPlugin_aHigh[16] A[2]=execute_MulPlugin_aHigh[16] A[1]=execute_MulPlugin_aHigh[16] A[0]=execute_MulPlugin_aHigh[16] B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_HL[0] Y[42]=execute_MUL_HL[1] Y[41]=execute_MUL_HL[2] Y[40]=execute_MUL_HL[3] Y[39]=execute_MUL_HL[4] Y[38]=execute_MUL_HL[5] Y[37]=execute_MUL_HL[6] Y[36]=execute_MUL_HL[7] Y[35]=execute_MUL_HL[8] Y[34]=execute_MUL_HL[9] Y[33]=execute_MUL_HL[10] Y[32]=execute_MUL_HL[11] Y[31]=execute_MUL_HL[12] Y[30]=execute_MUL_HL[13] Y[29]=execute_MUL_HL[14] Y[28]=execute_MUL_HL[15] Y[27]=execute_MUL_HL[16] Y[26]=execute_MUL_HL[17] Y[25]=execute_MUL_HL[18] Y[24]=execute_MUL_HL[19] Y[23]=execute_MUL_HL[20] Y[22]=execute_MUL_HL[21] Y[21]=execute_MUL_HL[22] Y[20]=execute_MUL_HL[23] Y[19]=execute_MUL_HL[24] Y[18]=execute_MUL_HL[25] Y[17]=execute_MUL_HL[26] Y[16]=execute_MUL_HL[27] Y[15]=execute_MUL_HL[28] Y[14]=execute_MUL_HL[29] Y[13]=execute_MUL_HL[30] Y[12]=execute_MUL_HL[31] Y[11]=execute_MUL_HL[32] Y[10]=execute_MUL_HL[33] Y[9]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[9] Y[8]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[8] Y[7]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[7] Y[6]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[6] Y[5]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[5] Y[4]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[4] Y[3]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[3] Y[2]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[2] Y[1]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[1] Y[0]=$techmap6157$mul$./benchmark/VexRiscv.v:2946$249.Y[0] +.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[16] B[18]=execute_RS2[17] B[17]=execute_RS2[18] B[16]=execute_RS2[19] B[15]=execute_RS2[20] B[14]=execute_RS2[21] B[13]=execute_RS2[22] B[12]=execute_RS2[23] B[11]=execute_RS2[24] B[10]=execute_RS2[25] B[9]=execute_RS2[26] B[8]=execute_RS2[27] B[7]=execute_RS2[28] B[6]=execute_RS2[29] B[5]=execute_RS2[30] B[4]=execute_RS2[31] B[3]=execute_MulPlugin_bHigh[16] B[2]=execute_MulPlugin_bHigh[16] B[1]=execute_MulPlugin_bHigh[16] B[0]=execute_MulPlugin_bHigh[16] Y[43]=execute_MUL_LH[0] Y[42]=execute_MUL_LH[1] Y[41]=execute_MUL_LH[2] Y[40]=execute_MUL_LH[3] Y[39]=execute_MUL_LH[4] Y[38]=execute_MUL_LH[5] Y[37]=execute_MUL_LH[6] Y[36]=execute_MUL_LH[7] Y[35]=execute_MUL_LH[8] Y[34]=execute_MUL_LH[9] Y[33]=execute_MUL_LH[10] Y[32]=execute_MUL_LH[11] Y[31]=execute_MUL_LH[12] Y[30]=execute_MUL_LH[13] Y[29]=execute_MUL_LH[14] Y[28]=execute_MUL_LH[15] Y[27]=execute_MUL_LH[16] Y[26]=execute_MUL_LH[17] Y[25]=execute_MUL_LH[18] Y[24]=execute_MUL_LH[19] Y[23]=execute_MUL_LH[20] Y[22]=execute_MUL_LH[21] Y[21]=execute_MUL_LH[22] Y[20]=execute_MUL_LH[23] Y[19]=execute_MUL_LH[24] Y[18]=execute_MUL_LH[25] Y[17]=execute_MUL_LH[26] Y[16]=execute_MUL_LH[27] Y[15]=execute_MUL_LH[28] Y[14]=execute_MUL_LH[29] Y[13]=execute_MUL_LH[30] Y[12]=execute_MUL_LH[31] Y[11]=execute_MUL_LH[32] Y[10]=execute_MUL_LH[33] Y[9]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[9] Y[8]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[8] Y[7]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[7] Y[6]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[6] Y[5]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[5] Y[4]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[4] Y[3]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[3] Y[2]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[2] Y[1]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[1] Y[0]=$techmap6158$mul$./benchmark/VexRiscv.v:2947$250.Y[0] +.subckt mult24x20 A[23]=execute_RS1[0] A[22]=execute_RS1[1] A[21]=execute_RS1[2] A[20]=execute_RS1[3] A[19]=execute_RS1[4] A[18]=execute_RS1[5] A[17]=execute_RS1[6] A[16]=execute_RS1[7] A[15]=execute_RS1[8] A[14]=execute_RS1[9] A[13]=execute_RS1[10] A[12]=execute_RS1[11] A[11]=execute_RS1[12] A[10]=execute_RS1[13] A[9]=execute_RS1[14] A[8]=execute_RS1[15] A[7]=$false A[6]=$false A[5]=$false A[4]=$false A[3]=$false A[2]=$false A[1]=$false A[0]=$false B[19]=execute_RS2[0] B[18]=execute_RS2[1] B[17]=execute_RS2[2] B[16]=execute_RS2[3] B[15]=execute_RS2[4] B[14]=execute_RS2[5] B[13]=execute_RS2[6] B[12]=execute_RS2[7] B[11]=execute_RS2[8] B[10]=execute_RS2[9] B[9]=execute_RS2[10] B[8]=execute_RS2[11] B[7]=execute_RS2[12] B[6]=execute_RS2[13] B[5]=execute_RS2[14] B[4]=execute_RS2[15] B[3]=$false B[2]=$false B[1]=$false B[0]=$false Y[43]=execute_MUL_LL[0] Y[42]=execute_MUL_LL[1] Y[41]=execute_MUL_LL[2] Y[40]=execute_MUL_LL[3] Y[39]=execute_MUL_LL[4] Y[38]=execute_MUL_LL[5] Y[37]=execute_MUL_LL[6] Y[36]=execute_MUL_LL[7] Y[35]=execute_MUL_LL[8] Y[34]=execute_MUL_LL[9] Y[33]=execute_MUL_LL[10] Y[32]=execute_MUL_LL[11] Y[31]=execute_MUL_LL[12] Y[30]=execute_MUL_LL[13] Y[29]=execute_MUL_LL[14] Y[28]=execute_MUL_LL[15] Y[27]=execute_MUL_LL[16] Y[26]=execute_MUL_LL[17] Y[25]=execute_MUL_LL[18] Y[24]=execute_MUL_LL[19] Y[23]=execute_MUL_LL[20] Y[22]=execute_MUL_LL[21] Y[21]=execute_MUL_LL[22] Y[20]=execute_MUL_LL[23] Y[19]=execute_MUL_LL[24] Y[18]=execute_MUL_LL[25] Y[17]=execute_MUL_LL[26] Y[16]=execute_MUL_LL[27] Y[15]=execute_MUL_LL[28] Y[14]=execute_MUL_LL[29] Y[13]=execute_MUL_LL[30] Y[12]=execute_MUL_LL[31] Y[11]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[11] Y[10]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[10] Y[9]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[9] Y[8]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[8] Y[7]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[7] Y[6]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[6] Y[5]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[5] Y[4]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[4] Y[3]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[3] Y[2]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[2] Y[1]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[1] Y[0]=$techmap6159$mul$./benchmark/VexRiscv.v:2948$251.Y[0] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[0] data_i[7]=iBus_rsp_payload_data[1] data_i[6]=iBus_rsp_payload_data[2] data_i[5]=iBus_rsp_payload_data[3] data_i[4]=iBus_rsp_payload_data[4] data_i[3]=iBus_rsp_payload_data[5] data_i[2]=iBus_rsp_payload_data[6] data_i[1]=iBus_rsp_payload_data[7] data_i[0]=iBus_rsp_payload_data[8] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[0] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[1] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[2] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[3] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[4] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[5] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[6] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[7] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[8] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[9] data_i[7]=iBus_rsp_payload_data[10] data_i[6]=iBus_rsp_payload_data[11] data_i[5]=iBus_rsp_payload_data[12] data_i[4]=iBus_rsp_payload_data[13] data_i[3]=iBus_rsp_payload_data[14] data_i[2]=iBus_rsp_payload_data[15] data_i[1]=iBus_rsp_payload_data[16] data_i[0]=iBus_rsp_payload_data[17] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[9] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[10] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[11] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[12] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[13] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[14] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[15] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[16] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[17] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[18] data_i[7]=iBus_rsp_payload_data[19] data_i[6]=iBus_rsp_payload_data[20] data_i[5]=iBus_rsp_payload_data[21] data_i[4]=iBus_rsp_payload_data[22] data_i[3]=iBus_rsp_payload_data[23] data_i[2]=iBus_rsp_payload_data[24] data_i[1]=iBus_rsp_payload_data[25] data_i[0]=iBus_rsp_payload_data[26] q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[18] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[19] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[20] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[21] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[22] q_o[3]=IBusCachedPlugin_cache._zz_banks_0_port1[23] q_o[2]=IBusCachedPlugin_cache._zz_banks_0_port1[24] q_o[1]=IBusCachedPlugin_cache._zz_banks_0_port1[25] q_o[0]=IBusCachedPlugin_cache._zz_banks_0_port1[26] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=iBus_rsp_payload_data[27] data_i[7]=iBus_rsp_payload_data[28] data_i[6]=iBus_rsp_payload_data[29] data_i[5]=iBus_rsp_payload_data[30] data_i[4]=iBus_rsp_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[8]=IBusCachedPlugin_cache._zz_banks_0_port1[27] q_o[7]=IBusCachedPlugin_cache._zz_banks_0_port1[28] q_o[6]=IBusCachedPlugin_cache._zz_banks_0_port1[29] q_o[5]=IBusCachedPlugin_cache._zz_banks_0_port1[30] q_o[4]=IBusCachedPlugin_cache._zz_banks_0_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6842[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6842[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6842[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6842[35] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[0]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[9]=IBusCachedPlugin_cache.lineLoader_wordIndex[0] waddr_i[8]=IBusCachedPlugin_cache.lineLoader_wordIndex[1] waddr_i[7]=IBusCachedPlugin_cache.lineLoader_wordIndex[2] waddr_i[6]=iBus_cmd_payload_address[5] waddr_i[5]=iBus_cmd_payload_address[6] waddr_i[4]=iBus_cmd_payload_address[7] waddr_i[3]=iBus_cmd_payload_address[8] waddr_i[2]=iBus_cmd_payload_address[9] waddr_i[1]=iBus_cmd_payload_address[10] waddr_i[0]=iBus_cmd_payload_address[11] wclk_i=clk wen_ni=iBus_rsp_valid +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid data_i[34]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_error data_i[33]=iBus_cmd_payload_address[12] data_i[32]=iBus_cmd_payload_address[13] data_i[31]=iBus_cmd_payload_address[14] data_i[30]=iBus_cmd_payload_address[15] data_i[29]=iBus_cmd_payload_address[16] data_i[28]=iBus_cmd_payload_address[17] data_i[27]=iBus_cmd_payload_address[18] data_i[26]=iBus_cmd_payload_address[19] data_i[25]=iBus_cmd_payload_address[20] data_i[24]=iBus_cmd_payload_address[21] data_i[23]=iBus_cmd_payload_address[22] data_i[22]=iBus_cmd_payload_address[23] data_i[21]=iBus_cmd_payload_address[24] data_i[20]=iBus_cmd_payload_address[25] data_i[19]=iBus_cmd_payload_address[26] data_i[18]=iBus_cmd_payload_address[27] data_i[17]=iBus_cmd_payload_address[28] data_i[16]=iBus_cmd_payload_address[29] data_i[15]=iBus_cmd_payload_address[30] data_i[14]=iBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] q_o[34]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] q_o[33]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] q_o[32]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] q_o[31]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] q_o[30]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] q_o[29]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] q_o[28]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] q_o[27]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] q_o[26]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] q_o[25]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] q_o[24]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] q_o[23]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] q_o[22]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] q_o[21]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] q_o[20]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] q_o[19]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] q_o[18]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] q_o[17]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] q_o[16]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] q_o[15]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] q_o[14]=IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6847[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6847[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6847[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6847[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6847[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6847[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6847[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6847[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6847[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6847[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6847[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6847[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6847[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6847[35] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_1 waddr_i[7]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[0] waddr_i[6]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[1] waddr_i[5]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[2] waddr_i[4]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[3] waddr_i[3]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[4] waddr_i[2]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[5] waddr_i[1]=IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=IBusCachedPlugin_cache._zz_2 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6849[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6849[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6849[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6849[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6850[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6850[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6850[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6850[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram2048x4 bwen_ni[3]=$true bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[3]=_zz__zz_3_port[0] data_i[2]=_zz__zz_3_port[1] data_i[1]=$undef data_i[0]=$undef q_o[3]=_zz__zz_3_port1[0] q_o[2]=_zz__zz_3_port1[1] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6853[2] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6853[3] raddr_i[10]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[0] raddr_i[9]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[1] raddr_i[8]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[2] raddr_i[7]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[3] raddr_i[6]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[4] raddr_i[5]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[5] raddr_i[4]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[6] raddr_i[3]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[7] raddr_i[2]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[8] raddr_i[1]=IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem[9] raddr_i[0]=$false rclk_i=clk ren_ni=_zz_decode_PREDICTION_CONTEXT_line_history_1 waddr_i[10]=_zz_decode_PREDICTION_CONTEXT_hazard_1[0] waddr_i[9]=_zz_decode_PREDICTION_CONTEXT_hazard_1[1] waddr_i[8]=_zz_decode_PREDICTION_CONTEXT_hazard_1[2] waddr_i[7]=_zz_decode_PREDICTION_CONTEXT_hazard_1[3] waddr_i[6]=_zz_decode_PREDICTION_CONTEXT_hazard_1[4] waddr_i[5]=_zz_decode_PREDICTION_CONTEXT_hazard_1[5] waddr_i[4]=_zz_decode_PREDICTION_CONTEXT_hazard_1[6] waddr_i[3]=_zz_decode_PREDICTION_CONTEXT_hazard_1[7] waddr_i[2]=_zz_decode_PREDICTION_CONTEXT_hazard_1[8] waddr_i[1]=_zz_decode_PREDICTION_CONTEXT_hazard_1[9] waddr_i[0]=$false wclk_i=clk wen_ni=_zz_2 +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[0] data_i[7]=dataCache_1.dataWriteCmd_payload_data[1] data_i[6]=dataCache_1.dataWriteCmd_payload_data[2] data_i[5]=dataCache_1.dataWriteCmd_payload_data[3] data_i[4]=dataCache_1.dataWriteCmd_payload_data[4] data_i[3]=dataCache_1.dataWriteCmd_payload_data[5] data_i[2]=dataCache_1.dataWriteCmd_payload_data[6] data_i[1]=dataCache_1.dataWriteCmd_payload_data[7] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[0] q_o[7]=dataCache_1._zz_ways_0_data_port0[1] q_o[6]=dataCache_1._zz_ways_0_data_port0[2] q_o[5]=dataCache_1._zz_ways_0_data_port0[3] q_o[4]=dataCache_1._zz_ways_0_data_port0[4] q_o[3]=dataCache_1._zz_ways_0_data_port0[5] q_o[2]=dataCache_1._zz_ways_0_data_port0[6] q_o[1]=dataCache_1._zz_ways_0_data_port0[7] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6855[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol0$./benchmark/VexRiscv.v:6878$1192_EN[7:0]$1214[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[8] data_i[7]=dataCache_1.dataWriteCmd_payload_data[9] data_i[6]=dataCache_1.dataWriteCmd_payload_data[10] data_i[5]=dataCache_1.dataWriteCmd_payload_data[11] data_i[4]=dataCache_1.dataWriteCmd_payload_data[12] data_i[3]=dataCache_1.dataWriteCmd_payload_data[13] data_i[2]=dataCache_1.dataWriteCmd_payload_data[14] data_i[1]=dataCache_1.dataWriteCmd_payload_data[15] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[8] q_o[7]=dataCache_1._zz_ways_0_data_port0[9] q_o[6]=dataCache_1._zz_ways_0_data_port0[10] q_o[5]=dataCache_1._zz_ways_0_data_port0[11] q_o[4]=dataCache_1._zz_ways_0_data_port0[12] q_o[3]=dataCache_1._zz_ways_0_data_port0[13] q_o[2]=dataCache_1._zz_ways_0_data_port0[14] q_o[1]=dataCache_1._zz_ways_0_data_port0[15] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6857[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol1$./benchmark/VexRiscv.v:6881$1193_EN[7:0]$1217[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[16] data_i[7]=dataCache_1.dataWriteCmd_payload_data[17] data_i[6]=dataCache_1.dataWriteCmd_payload_data[18] data_i[5]=dataCache_1.dataWriteCmd_payload_data[19] data_i[4]=dataCache_1.dataWriteCmd_payload_data[20] data_i[3]=dataCache_1.dataWriteCmd_payload_data[21] data_i[2]=dataCache_1.dataWriteCmd_payload_data[22] data_i[1]=dataCache_1.dataWriteCmd_payload_data[23] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[16] q_o[7]=dataCache_1._zz_ways_0_data_port0[17] q_o[6]=dataCache_1._zz_ways_0_data_port0[18] q_o[5]=dataCache_1._zz_ways_0_data_port0[19] q_o[4]=dataCache_1._zz_ways_0_data_port0[20] q_o[3]=dataCache_1._zz_ways_0_data_port0[21] q_o[2]=dataCache_1._zz_ways_0_data_port0[22] q_o[1]=dataCache_1._zz_ways_0_data_port0[23] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6859[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol2$./benchmark/VexRiscv.v:6884$1194_EN[7:0]$1220[7] +.subckt dpram1024x9 bwen_ni[8]=$true bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[8]=dataCache_1.dataWriteCmd_payload_data[24] data_i[7]=dataCache_1.dataWriteCmd_payload_data[25] data_i[6]=dataCache_1.dataWriteCmd_payload_data[26] data_i[5]=dataCache_1.dataWriteCmd_payload_data[27] data_i[4]=dataCache_1.dataWriteCmd_payload_data[28] data_i[3]=dataCache_1.dataWriteCmd_payload_data[29] data_i[2]=dataCache_1.dataWriteCmd_payload_data[30] data_i[1]=dataCache_1.dataWriteCmd_payload_data[31] data_i[0]=$undef q_o[8]=dataCache_1._zz_ways_0_data_port0[24] q_o[7]=dataCache_1._zz_ways_0_data_port0[25] q_o[6]=dataCache_1._zz_ways_0_data_port0[26] q_o[5]=dataCache_1._zz_ways_0_data_port0[27] q_o[4]=dataCache_1._zz_ways_0_data_port0[28] q_o[3]=dataCache_1._zz_ways_0_data_port0[29] q_o[2]=dataCache_1._zz_ways_0_data_port0[30] q_o[1]=dataCache_1._zz_ways_0_data_port0[31] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6861[8] raddr_i[9]=dataCache_1.dataReadCmd_payload[0] raddr_i[8]=dataCache_1.dataReadCmd_payload[1] raddr_i[7]=dataCache_1.dataReadCmd_payload[2] raddr_i[6]=dataCache_1.dataReadCmd_payload[3] raddr_i[5]=dataCache_1.dataReadCmd_payload[4] raddr_i[4]=dataCache_1.dataReadCmd_payload[5] raddr_i[3]=dataCache_1.dataReadCmd_payload[6] raddr_i[2]=dataCache_1.dataReadCmd_payload[7] raddr_i[1]=dataCache_1.dataReadCmd_payload[8] raddr_i[0]=dataCache_1.dataReadCmd_payload[9] rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[9]=dataCache_1.dataWriteCmd_payload_address[0] waddr_i[8]=dataCache_1.dataWriteCmd_payload_address[1] waddr_i[7]=dataCache_1.dataWriteCmd_payload_address[2] waddr_i[6]=dBus_cmd_payload_address[5] waddr_i[5]=dBus_cmd_payload_address[6] waddr_i[4]=dBus_cmd_payload_address[7] waddr_i[3]=dBus_cmd_payload_address[8] waddr_i[2]=dBus_cmd_payload_address[9] waddr_i[1]=dBus_cmd_payload_address[10] waddr_i[0]=dBus_cmd_payload_address[11] wclk_i=clk wen_ni=$abc$27210$flatten\dataCache_1.$0$memwr$\ways_0_data_symbol3$./benchmark/VexRiscv.v:6887$1195_EN[7:0]$1223[7] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=dataCache_1.loader_counter_willOverflow data_i[34]=dataCache_1.tagsWriteCmd_payload_data_error data_i[33]=dBus_cmd_payload_address[12] data_i[32]=dBus_cmd_payload_address[13] data_i[31]=dBus_cmd_payload_address[14] data_i[30]=dBus_cmd_payload_address[15] data_i[29]=dBus_cmd_payload_address[16] data_i[28]=dBus_cmd_payload_address[17] data_i[27]=dBus_cmd_payload_address[18] data_i[26]=dBus_cmd_payload_address[19] data_i[25]=dBus_cmd_payload_address[20] data_i[24]=dBus_cmd_payload_address[21] data_i[23]=dBus_cmd_payload_address[22] data_i[22]=dBus_cmd_payload_address[23] data_i[21]=dBus_cmd_payload_address[24] data_i[20]=dBus_cmd_payload_address[25] data_i[19]=dBus_cmd_payload_address[26] data_i[18]=dBus_cmd_payload_address[27] data_i[17]=dBus_cmd_payload_address[28] data_i[16]=dBus_cmd_payload_address[29] data_i[15]=dBus_cmd_payload_address[30] data_i[14]=dBus_cmd_payload_address[31] data_i[13]=$undef data_i[12]=$undef data_i[11]=$undef data_i[10]=$undef data_i[9]=$undef data_i[8]=$undef data_i[7]=$undef data_i[6]=$undef data_i[5]=$undef data_i[4]=$undef data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[0] q_o[34]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[1] q_o[33]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[2] q_o[32]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[3] q_o[31]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[4] q_o[30]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[5] q_o[29]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[6] q_o[28]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[7] q_o[27]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[8] q_o[26]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[9] q_o[25]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[10] q_o[24]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[11] q_o[23]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[12] q_o[22]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[13] q_o[21]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[14] q_o[20]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[15] q_o[19]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[16] q_o[18]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[17] q_o[17]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[18] q_o[16]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[19] q_o[15]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[20] q_o[14]=dataCache_1._zz_ways_0_tagsReadRsp_valid_1[21] q_o[13]=$auto$memory_bram.cc:844:replace_memory$6863[22] q_o[12]=$auto$memory_bram.cc:844:replace_memory$6863[23] q_o[11]=$auto$memory_bram.cc:844:replace_memory$6863[24] q_o[10]=$auto$memory_bram.cc:844:replace_memory$6863[25] q_o[9]=$auto$memory_bram.cc:844:replace_memory$6863[26] q_o[8]=$auto$memory_bram.cc:844:replace_memory$6863[27] q_o[7]=$auto$memory_bram.cc:844:replace_memory$6863[28] q_o[6]=$auto$memory_bram.cc:844:replace_memory$6863[29] q_o[5]=$auto$memory_bram.cc:844:replace_memory$6863[30] q_o[4]=$auto$memory_bram.cc:844:replace_memory$6863[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$6863[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$6863[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$6863[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$6863[35] raddr_i[7]=dataCache_1.dataReadCmd_payload[3] raddr_i[6]=dataCache_1.dataReadCmd_payload[4] raddr_i[5]=dataCache_1.dataReadCmd_payload[5] raddr_i[4]=dataCache_1.dataReadCmd_payload[6] raddr_i[3]=dataCache_1.dataReadCmd_payload[7] raddr_i[2]=dataCache_1.dataReadCmd_payload[8] raddr_i[1]=dataCache_1.dataReadCmd_payload[9] raddr_i[0]=$false rclk_i=clk ren_ni=dataCache_1._zz_ways_0_dataReadRspMem waddr_i[7]=dataCache_1.tagsWriteCmd_payload_address[0] waddr_i[6]=dataCache_1.tagsWriteCmd_payload_address[1] waddr_i[5]=dataCache_1.tagsWriteCmd_payload_address[2] waddr_i[4]=dataCache_1.tagsWriteCmd_payload_address[3] waddr_i[3]=dataCache_1.tagsWriteCmd_payload_address[4] waddr_i[2]=dataCache_1.tagsWriteCmd_payload_address[5] waddr_i[1]=dataCache_1.tagsWriteCmd_payload_address[6] waddr_i[0]=$false wclk_i=clk wen_ni=dataCache_1._zz_2 +.names $false BranchPlugin_branchExceptionPort_payload_badAddr[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names _zz_writeBack_DBusCachedPlugin_rspShifted_3 DBusCachedPlugin_exceptionBus_payload_badAddr[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_0_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_0_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_1_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_1_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_2_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_2_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_3_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_3_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_4_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_4_physical[21] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[0] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[0] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[1] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[1] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[2] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[2] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[3] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[3] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[4] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[4] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[5] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[5] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[6] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[6] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[7] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[7] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[8] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[8] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[9] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[9] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[10] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[10] +1 1 +.names DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11] DBusCachedPlugin_mmuBus_rsp_ways_5_physical[11] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[12] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[13] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[14] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[15] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[16] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[17] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[18] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[19] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[20] +1 1 +.names $undef DBusCachedPlugin_mmuBus_rsp_ways_5_physical[21] +1 1 +.names $false DBusCachedPlugin_redoBranch_payload[0] +1 1 +.names $false DBusCachedPlugin_redoBranch_payload[1] +1 1 +.names debug_bus_rsp_data[5] DebugPlugin_busReadDataReg[5] +1 1 +.names debug_bus_rsp_data[6] DebugPlugin_busReadDataReg[6] +1 1 +.names debug_bus_rsp_data[7] DebugPlugin_busReadDataReg[7] +1 1 +.names debug_bus_rsp_data[8] DebugPlugin_busReadDataReg[8] +1 1 +.names debug_bus_rsp_data[9] DebugPlugin_busReadDataReg[9] +1 1 +.names debug_bus_rsp_data[10] DebugPlugin_busReadDataReg[10] +1 1 +.names debug_bus_rsp_data[11] DebugPlugin_busReadDataReg[11] +1 1 +.names debug_bus_rsp_data[12] DebugPlugin_busReadDataReg[12] +1 1 +.names debug_bus_rsp_data[13] DebugPlugin_busReadDataReg[13] +1 1 +.names debug_bus_rsp_data[14] DebugPlugin_busReadDataReg[14] +1 1 +.names debug_bus_rsp_data[15] DebugPlugin_busReadDataReg[15] +1 1 +.names debug_bus_rsp_data[16] DebugPlugin_busReadDataReg[16] +1 1 +.names debug_bus_rsp_data[17] DebugPlugin_busReadDataReg[17] +1 1 +.names debug_bus_rsp_data[18] DebugPlugin_busReadDataReg[18] +1 1 +.names debug_bus_rsp_data[19] DebugPlugin_busReadDataReg[19] +1 1 +.names debug_bus_rsp_data[20] DebugPlugin_busReadDataReg[20] +1 1 +.names debug_bus_rsp_data[21] DebugPlugin_busReadDataReg[21] +1 1 +.names debug_bus_rsp_data[22] DebugPlugin_busReadDataReg[22] +1 1 +.names debug_bus_rsp_data[23] DebugPlugin_busReadDataReg[23] +1 1 +.names debug_bus_rsp_data[24] DebugPlugin_busReadDataReg[24] +1 1 +.names debug_bus_rsp_data[25] DebugPlugin_busReadDataReg[25] +1 1 +.names debug_bus_rsp_data[26] DebugPlugin_busReadDataReg[26] +1 1 +.names debug_bus_rsp_data[27] DebugPlugin_busReadDataReg[27] +1 1 +.names debug_bus_rsp_data[28] DebugPlugin_busReadDataReg[28] +1 1 +.names debug_bus_rsp_data[29] DebugPlugin_busReadDataReg[29] +1 1 +.names debug_bus_rsp_data[30] DebugPlugin_busReadDataReg[30] +1 1 +.names debug_bus_rsp_data[31] DebugPlugin_busReadDataReg[31] +1 1 +.names _zz__zz_decode_IS_CSR_85 IBusCachedPlugin_cache._zz_decodeStage_hit_data[2] +1 1 +.names _zz__zz_decode_IS_CSR_41 IBusCachedPlugin_cache._zz_decodeStage_hit_data[5] +1 1 +.names _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[7] +1 1 +.names _zz__zz_decode_IS_CSR_21 IBusCachedPlugin_cache._zz_decodeStage_hit_data[12] +1 1 +.names _zz_6 IBusCachedPlugin_cache._zz_decodeStage_hit_data[31] +1 1 +.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[0] +1 1 +.names $false IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress[1] +1 1 +.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[0] +1 1 +.names $false IBusCachedPlugin_cache.io_cpu_fetch_mmuRsp_physicalAddress[1] +1 1 +.names $false IBusCachedPlugin_cache.lineLoader_address[0] +1 1 +.names $false IBusCachedPlugin_cache.lineLoader_address[1] +1 1 +.names iBus_cmd_payload_address[5] IBusCachedPlugin_cache.lineLoader_address[5] +1 1 +.names iBus_cmd_payload_address[6] IBusCachedPlugin_cache.lineLoader_address[6] +1 1 +.names iBus_cmd_payload_address[7] IBusCachedPlugin_cache.lineLoader_address[7] +1 1 +.names iBus_cmd_payload_address[8] IBusCachedPlugin_cache.lineLoader_address[8] +1 1 +.names iBus_cmd_payload_address[9] IBusCachedPlugin_cache.lineLoader_address[9] +1 1 +.names iBus_cmd_payload_address[10] IBusCachedPlugin_cache.lineLoader_address[10] +1 1 +.names iBus_cmd_payload_address[11] IBusCachedPlugin_cache.lineLoader_address[11] +1 1 +.names iBus_cmd_payload_address[12] IBusCachedPlugin_cache.lineLoader_address[12] +1 1 +.names iBus_cmd_payload_address[13] IBusCachedPlugin_cache.lineLoader_address[13] +1 1 +.names iBus_cmd_payload_address[14] IBusCachedPlugin_cache.lineLoader_address[14] +1 1 +.names iBus_cmd_payload_address[15] IBusCachedPlugin_cache.lineLoader_address[15] +1 1 +.names iBus_cmd_payload_address[16] IBusCachedPlugin_cache.lineLoader_address[16] +1 1 +.names iBus_cmd_payload_address[17] IBusCachedPlugin_cache.lineLoader_address[17] +1 1 +.names iBus_cmd_payload_address[18] IBusCachedPlugin_cache.lineLoader_address[18] +1 1 +.names iBus_cmd_payload_address[19] IBusCachedPlugin_cache.lineLoader_address[19] +1 1 +.names iBus_cmd_payload_address[20] IBusCachedPlugin_cache.lineLoader_address[20] +1 1 +.names iBus_cmd_payload_address[21] IBusCachedPlugin_cache.lineLoader_address[21] +1 1 +.names iBus_cmd_payload_address[22] IBusCachedPlugin_cache.lineLoader_address[22] +1 1 +.names iBus_cmd_payload_address[23] IBusCachedPlugin_cache.lineLoader_address[23] +1 1 +.names iBus_cmd_payload_address[24] IBusCachedPlugin_cache.lineLoader_address[24] +1 1 +.names iBus_cmd_payload_address[25] IBusCachedPlugin_cache.lineLoader_address[25] +1 1 +.names iBus_cmd_payload_address[26] IBusCachedPlugin_cache.lineLoader_address[26] +1 1 +.names iBus_cmd_payload_address[27] IBusCachedPlugin_cache.lineLoader_address[27] +1 1 +.names iBus_cmd_payload_address[28] IBusCachedPlugin_cache.lineLoader_address[28] +1 1 +.names iBus_cmd_payload_address[29] IBusCachedPlugin_cache.lineLoader_address[29] +1 1 +.names iBus_cmd_payload_address[30] IBusCachedPlugin_cache.lineLoader_address[30] +1 1 +.names iBus_cmd_payload_address[31] IBusCachedPlugin_cache.lineLoader_address[31] +1 1 +.names IBusCachedPlugin_cache.lineLoader_write_tag_0_payload_data_valid IBusCachedPlugin_cache.lineLoader_flushCounter[7] +1 1 +.names $false IBusCachedPlugin_predictionJumpInterface_payload[0] +1 1 +.names _zz_10 IBusCachedPlugin_predictionJumpInterface_payload[1] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_V MmuPlugin_shared_dBusRspStaged_payload_data[0] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_R MmuPlugin_shared_dBusRspStaged_payload_data[1] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_W MmuPlugin_shared_dBusRspStaged_payload_data[2] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_X MmuPlugin_shared_dBusRspStaged_payload_data[3] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_A MmuPlugin_shared_dBusRspStaged_payload_data[6] +1 1 +.names MmuPlugin_shared_dBusRsp_pte_D MmuPlugin_shared_dBusRspStaged_payload_data[7] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[0] $auto$memory_bram.cc:844:replace_memory$6842[0] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[1] $auto$memory_bram.cc:844:replace_memory$6842[1] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[2] $auto$memory_bram.cc:844:replace_memory$6842[2] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[3] $auto$memory_bram.cc:844:replace_memory$6842[3] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[4] $auto$memory_bram.cc:844:replace_memory$6842[4] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[5] $auto$memory_bram.cc:844:replace_memory$6842[5] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[6] $auto$memory_bram.cc:844:replace_memory$6842[6] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[7] $auto$memory_bram.cc:844:replace_memory$6842[7] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[8] $auto$memory_bram.cc:844:replace_memory$6842[8] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[9] $auto$memory_bram.cc:844:replace_memory$6842[9] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[10] $auto$memory_bram.cc:844:replace_memory$6842[10] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[11] $auto$memory_bram.cc:844:replace_memory$6842[11] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[12] $auto$memory_bram.cc:844:replace_memory$6842[12] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[13] $auto$memory_bram.cc:844:replace_memory$6842[13] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[14] $auto$memory_bram.cc:844:replace_memory$6842[14] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[15] $auto$memory_bram.cc:844:replace_memory$6842[15] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[16] $auto$memory_bram.cc:844:replace_memory$6842[16] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[17] $auto$memory_bram.cc:844:replace_memory$6842[17] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[18] $auto$memory_bram.cc:844:replace_memory$6842[18] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[19] $auto$memory_bram.cc:844:replace_memory$6842[19] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[20] $auto$memory_bram.cc:844:replace_memory$6842[20] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[21] $auto$memory_bram.cc:844:replace_memory$6842[21] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[22] $auto$memory_bram.cc:844:replace_memory$6842[22] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[23] $auto$memory_bram.cc:844:replace_memory$6842[23] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[24] $auto$memory_bram.cc:844:replace_memory$6842[24] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[25] $auto$memory_bram.cc:844:replace_memory$6842[25] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[26] $auto$memory_bram.cc:844:replace_memory$6842[26] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[27] $auto$memory_bram.cc:844:replace_memory$6842[27] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[28] $auto$memory_bram.cc:844:replace_memory$6842[28] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[29] $auto$memory_bram.cc:844:replace_memory$6842[29] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[30] $auto$memory_bram.cc:844:replace_memory$6842[30] +1 1 +.names IBusCachedPlugin_cache._zz_banks_0_port1[31] $auto$memory_bram.cc:844:replace_memory$6842[31] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[0] $auto$memory_bram.cc:844:replace_memory$6847[0] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[1] $auto$memory_bram.cc:844:replace_memory$6847[1] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[2] $auto$memory_bram.cc:844:replace_memory$6847[2] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[3] $auto$memory_bram.cc:844:replace_memory$6847[3] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[4] $auto$memory_bram.cc:844:replace_memory$6847[4] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[5] $auto$memory_bram.cc:844:replace_memory$6847[5] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[6] $auto$memory_bram.cc:844:replace_memory$6847[6] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[7] $auto$memory_bram.cc:844:replace_memory$6847[7] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[8] $auto$memory_bram.cc:844:replace_memory$6847[8] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[9] $auto$memory_bram.cc:844:replace_memory$6847[9] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[10] $auto$memory_bram.cc:844:replace_memory$6847[10] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[11] $auto$memory_bram.cc:844:replace_memory$6847[11] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[12] $auto$memory_bram.cc:844:replace_memory$6847[12] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[13] $auto$memory_bram.cc:844:replace_memory$6847[13] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[14] $auto$memory_bram.cc:844:replace_memory$6847[14] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[15] $auto$memory_bram.cc:844:replace_memory$6847[15] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[16] $auto$memory_bram.cc:844:replace_memory$6847[16] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[17] $auto$memory_bram.cc:844:replace_memory$6847[17] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[18] $auto$memory_bram.cc:844:replace_memory$6847[18] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[19] $auto$memory_bram.cc:844:replace_memory$6847[19] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[20] $auto$memory_bram.cc:844:replace_memory$6847[20] +1 1 +.names IBusCachedPlugin_cache._zz_fetchStage_read_waysValues_0_tag_valid_2[21] $auto$memory_bram.cc:844:replace_memory$6847[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$6849[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$6849[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$6849[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$6849[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$6849[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$6849[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$6849[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$6849[7] +1 1 +.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$6849[8] +1 1 +.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$6849[9] +1 1 +.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$6849[10] +1 1 +.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$6849[11] +1 1 +.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$6849[12] +1 1 +.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$6849[13] +1 1 +.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$6849[14] +1 1 +.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$6849[15] +1 1 +.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$6849[16] +1 1 +.names _zz_RegFilePlugin_regFile_port1[17] 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_zz_memory_MUL_LOW_4[12] +1 1 +.names $false _zz_memory_MUL_LOW_4[13] +1 1 +.names $false _zz_memory_MUL_LOW_4[14] +1 1 +.names $false _zz_memory_MUL_LOW_4[15] +1 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_4[49] +1 1 +.names _zz_memory_MUL_LOW_4[51] _zz_memory_MUL_LOW_4[50] +1 1 +.names $false _zz_memory_MUL_LOW_6[0] +1 1 +.names $false _zz_memory_MUL_LOW_6[1] +1 1 +.names $false _zz_memory_MUL_LOW_6[2] +1 1 +.names $false _zz_memory_MUL_LOW_6[3] +1 1 +.names $false _zz_memory_MUL_LOW_6[4] +1 1 +.names $false _zz_memory_MUL_LOW_6[5] +1 1 +.names $false _zz_memory_MUL_LOW_6[6] +1 1 +.names $false _zz_memory_MUL_LOW_6[7] +1 1 +.names $false _zz_memory_MUL_LOW_6[8] +1 1 +.names $false _zz_memory_MUL_LOW_6[9] +1 1 +.names $false _zz_memory_MUL_LOW_6[10] +1 1 +.names $false _zz_memory_MUL_LOW_6[11] +1 1 +.names $false _zz_memory_MUL_LOW_6[12] +1 1 +.names $false _zz_memory_MUL_LOW_6[13] +1 1 +.names $false _zz_memory_MUL_LOW_6[14] +1 1 +.names $false _zz_memory_MUL_LOW_6[15] +1 1 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_zz__zz_decode_RS2_2[12] _zz_writeBack_MulPlugin_result[12] +1 1 +.names _zz__zz_decode_RS2_2[13] _zz_writeBack_MulPlugin_result[13] +1 1 +.names _zz__zz_decode_RS2_2[14] _zz_writeBack_MulPlugin_result[14] +1 1 +.names _zz__zz_decode_RS2_2[15] _zz_writeBack_MulPlugin_result[15] +1 1 +.names _zz__zz_decode_RS2_2[16] _zz_writeBack_MulPlugin_result[16] +1 1 +.names _zz__zz_decode_RS2_2[17] _zz_writeBack_MulPlugin_result[17] +1 1 +.names _zz__zz_decode_RS2_2[18] _zz_writeBack_MulPlugin_result[18] +1 1 +.names _zz__zz_decode_RS2_2[19] _zz_writeBack_MulPlugin_result[19] +1 1 +.names _zz__zz_decode_RS2_2[20] _zz_writeBack_MulPlugin_result[20] +1 1 +.names _zz__zz_decode_RS2_2[21] _zz_writeBack_MulPlugin_result[21] +1 1 +.names _zz__zz_decode_RS2_2[22] _zz_writeBack_MulPlugin_result[22] +1 1 +.names _zz__zz_decode_RS2_2[23] _zz_writeBack_MulPlugin_result[23] +1 1 +.names _zz__zz_decode_RS2_2[24] _zz_writeBack_MulPlugin_result[24] +1 1 +.names _zz__zz_decode_RS2_2[25] _zz_writeBack_MulPlugin_result[25] +1 1 +.names _zz__zz_decode_RS2_2[26] _zz_writeBack_MulPlugin_result[26] +1 1 +.names _zz__zz_decode_RS2_2[27] _zz_writeBack_MulPlugin_result[27] +1 1 +.names _zz__zz_decode_RS2_2[28] _zz_writeBack_MulPlugin_result[28] +1 1 +.names _zz__zz_decode_RS2_2[29] _zz_writeBack_MulPlugin_result[29] +1 1 +.names _zz__zz_decode_RS2_2[30] _zz_writeBack_MulPlugin_result[30] +1 1 +.names _zz__zz_decode_RS2_2[31] _zz_writeBack_MulPlugin_result[31] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[51] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[52] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[53] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[54] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[55] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[56] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[57] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[58] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[59] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[60] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[61] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[62] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[63] +1 1 +.names _zz_writeBack_MulPlugin_result[65] _zz_writeBack_MulPlugin_result[64] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[0] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[1] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[2] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[3] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[4] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[5] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[6] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[7] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[8] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[9] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[10] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[11] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[12] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[13] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[14] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[15] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[16] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[17] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[18] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[19] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[20] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[21] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[22] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[23] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[24] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[25] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[26] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[27] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[28] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[29] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[30] +1 1 +.names $false _zz_writeBack_MulPlugin_result_1[31] +1 1 +.names $true dBus_cmd_payload_last +1 1 +.names dBus_cmd_payload_address[5] dataCache_1.dataWriteCmd_payload_address[3] +1 1 +.names dBus_cmd_payload_address[6] dataCache_1.dataWriteCmd_payload_address[4] +1 1 +.names dBus_cmd_payload_address[7] dataCache_1.dataWriteCmd_payload_address[5] +1 1 +.names dBus_cmd_payload_address[8] dataCache_1.dataWriteCmd_payload_address[6] +1 1 +.names dBus_cmd_payload_address[9] dataCache_1.dataWriteCmd_payload_address[7] +1 1 +.names dBus_cmd_payload_address[10] dataCache_1.dataWriteCmd_payload_address[8] +1 1 +.names dBus_cmd_payload_address[11] dataCache_1.dataWriteCmd_payload_address[9] +1 1 +.names dBus_cmd_payload_address[5] dataCache_1.stageB_mmuRsp_physicalAddress[5] +1 1 +.names dBus_cmd_payload_address[6] dataCache_1.stageB_mmuRsp_physicalAddress[6] +1 1 +.names dBus_cmd_payload_address[7] dataCache_1.stageB_mmuRsp_physicalAddress[7] +1 1 +.names dBus_cmd_payload_address[8] dataCache_1.stageB_mmuRsp_physicalAddress[8] +1 1 +.names dBus_cmd_payload_address[9] dataCache_1.stageB_mmuRsp_physicalAddress[9] +1 1 +.names dBus_cmd_payload_address[10] dataCache_1.stageB_mmuRsp_physicalAddress[10] +1 1 +.names dBus_cmd_payload_address[11] dataCache_1.stageB_mmuRsp_physicalAddress[11] +1 1 +.names dBus_cmd_payload_address[12] dataCache_1.stageB_mmuRsp_physicalAddress[12] +1 1 +.names dBus_cmd_payload_address[13] dataCache_1.stageB_mmuRsp_physicalAddress[13] +1 1 +.names dBus_cmd_payload_address[14] dataCache_1.stageB_mmuRsp_physicalAddress[14] +1 1 +.names dBus_cmd_payload_address[15] dataCache_1.stageB_mmuRsp_physicalAddress[15] +1 1 +.names dBus_cmd_payload_address[16] dataCache_1.stageB_mmuRsp_physicalAddress[16] +1 1 +.names dBus_cmd_payload_address[17] dataCache_1.stageB_mmuRsp_physicalAddress[17] +1 1 +.names dBus_cmd_payload_address[18] dataCache_1.stageB_mmuRsp_physicalAddress[18] +1 1 +.names dBus_cmd_payload_address[19] dataCache_1.stageB_mmuRsp_physicalAddress[19] +1 1 +.names dBus_cmd_payload_address[20] dataCache_1.stageB_mmuRsp_physicalAddress[20] +1 1 +.names dBus_cmd_payload_address[21] dataCache_1.stageB_mmuRsp_physicalAddress[21] +1 1 +.names dBus_cmd_payload_address[22] dataCache_1.stageB_mmuRsp_physicalAddress[22] +1 1 +.names dBus_cmd_payload_address[23] dataCache_1.stageB_mmuRsp_physicalAddress[23] +1 1 +.names dBus_cmd_payload_address[24] dataCache_1.stageB_mmuRsp_physicalAddress[24] +1 1 +.names dBus_cmd_payload_address[25] dataCache_1.stageB_mmuRsp_physicalAddress[25] +1 1 +.names dBus_cmd_payload_address[26] dataCache_1.stageB_mmuRsp_physicalAddress[26] +1 1 +.names dBus_cmd_payload_address[27] dataCache_1.stageB_mmuRsp_physicalAddress[27] +1 1 +.names dBus_cmd_payload_address[28] dataCache_1.stageB_mmuRsp_physicalAddress[28] +1 1 +.names dBus_cmd_payload_address[29] dataCache_1.stageB_mmuRsp_physicalAddress[29] +1 1 +.names dBus_cmd_payload_address[30] dataCache_1.stageB_mmuRsp_physicalAddress[30] +1 1 +.names dBus_cmd_payload_address[31] dataCache_1.stageB_mmuRsp_physicalAddress[31] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[25] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[26] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[27] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[28] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[29] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[30] +1 1 +.names $undef decode_INSTRUCTION_ANTICIPATED[31] +1 1 +.names execute_RS1[16] execute_MulPlugin_aHigh[0] +1 1 +.names execute_RS1[17] execute_MulPlugin_aHigh[1] +1 1 +.names execute_RS1[18] execute_MulPlugin_aHigh[2] +1 1 +.names execute_RS1[19] execute_MulPlugin_aHigh[3] +1 1 +.names execute_RS1[20] execute_MulPlugin_aHigh[4] +1 1 +.names execute_RS1[21] execute_MulPlugin_aHigh[5] +1 1 +.names execute_RS1[22] execute_MulPlugin_aHigh[6] +1 1 +.names execute_RS1[23] execute_MulPlugin_aHigh[7] +1 1 +.names execute_RS1[24] execute_MulPlugin_aHigh[8] +1 1 +.names execute_RS1[25] execute_MulPlugin_aHigh[9] +1 1 +.names execute_RS1[26] execute_MulPlugin_aHigh[10] +1 1 +.names execute_RS1[27] execute_MulPlugin_aHigh[11] +1 1 +.names execute_RS1[28] execute_MulPlugin_aHigh[12] +1 1 +.names execute_RS1[29] execute_MulPlugin_aHigh[13] +1 1 +.names execute_RS1[30] execute_MulPlugin_aHigh[14] +1 1 +.names execute_RS1[31] execute_MulPlugin_aHigh[15] +1 1 +.names execute_RS2[16] execute_MulPlugin_bHigh[0] +1 1 +.names execute_RS2[17] execute_MulPlugin_bHigh[1] +1 1 +.names execute_RS2[18] execute_MulPlugin_bHigh[2] +1 1 +.names execute_RS2[19] execute_MulPlugin_bHigh[3] +1 1 +.names execute_RS2[20] execute_MulPlugin_bHigh[4] +1 1 +.names execute_RS2[21] execute_MulPlugin_bHigh[5] +1 1 +.names execute_RS2[22] execute_MulPlugin_bHigh[6] +1 1 +.names execute_RS2[23] execute_MulPlugin_bHigh[7] +1 1 +.names execute_RS2[24] execute_MulPlugin_bHigh[8] +1 1 +.names execute_RS2[25] execute_MulPlugin_bHigh[9] +1 1 +.names execute_RS2[26] execute_MulPlugin_bHigh[10] +1 1 +.names execute_RS2[27] execute_MulPlugin_bHigh[11] +1 1 +.names execute_RS2[28] execute_MulPlugin_bHigh[12] +1 1 +.names execute_RS2[29] execute_MulPlugin_bHigh[13] +1 1 +.names execute_RS2[30] execute_MulPlugin_bHigh[14] +1 1 +.names execute_RS2[31] execute_MulPlugin_bHigh[15] +1 1 +.names $false execute_to_memory_PC[0] +1 1 +.names $false execute_to_memory_PC[1] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[0] execute_to_memory_PC[2] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[1] execute_to_memory_PC[3] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[2] execute_to_memory_PC[4] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[3] execute_to_memory_PC[5] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[4] execute_to_memory_PC[6] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[5] execute_to_memory_PC[7] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[6] execute_to_memory_PC[8] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[7] execute_to_memory_PC[9] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[8] execute_to_memory_PC[10] +1 1 +.names _zz_decode_PREDICTION_CONTEXT_hazard_1[9] execute_to_memory_PC[11] +1 1 +.names $false iBus_cmd_payload_address[0] +1 1 +.names $false iBus_cmd_payload_address[1] +1 1 +.names $false iBus_cmd_payload_address[2] +1 1 +.names $false iBus_cmd_payload_address[3] +1 1 +.names $false iBus_cmd_payload_address[4] +1 1 +.names $true iBus_cmd_payload_size[0] +1 1 +.names $false iBus_cmd_payload_size[1] +1 1 +.names $true iBus_cmd_payload_size[2] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[1] memory_DivPlugin_accumulator[0] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[2] memory_DivPlugin_accumulator[1] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[3] memory_DivPlugin_accumulator[2] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[4] memory_DivPlugin_accumulator[3] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[5] memory_DivPlugin_accumulator[4] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[6] memory_DivPlugin_accumulator[5] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[7] memory_DivPlugin_accumulator[6] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[8] memory_DivPlugin_accumulator[7] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[9] memory_DivPlugin_accumulator[8] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[10] memory_DivPlugin_accumulator[9] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[11] memory_DivPlugin_accumulator[10] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[12] memory_DivPlugin_accumulator[11] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[13] memory_DivPlugin_accumulator[12] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[14] memory_DivPlugin_accumulator[13] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[15] memory_DivPlugin_accumulator[14] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[16] memory_DivPlugin_accumulator[15] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[17] memory_DivPlugin_accumulator[16] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[18] memory_DivPlugin_accumulator[17] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[19] memory_DivPlugin_accumulator[18] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[20] memory_DivPlugin_accumulator[19] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[21] memory_DivPlugin_accumulator[20] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[22] memory_DivPlugin_accumulator[21] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[23] memory_DivPlugin_accumulator[22] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[24] memory_DivPlugin_accumulator[23] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[25] memory_DivPlugin_accumulator[24] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[26] memory_DivPlugin_accumulator[25] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[27] memory_DivPlugin_accumulator[26] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[28] memory_DivPlugin_accumulator[27] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[29] memory_DivPlugin_accumulator[28] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[30] memory_DivPlugin_accumulator[29] +1 1 +.names _zz_memory_DivPlugin_div_stage_0_outRemainder_1[31] memory_DivPlugin_accumulator[30] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif new file mode 100644 index 00000000000..d81a68f31e7 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/VexRiscv_small.blif @@ -0,0 +1,10133 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model VexRiscv +.inputs iBus_cmd_ready iBus_rsp_valid iBus_rsp_payload_error iBus_rsp_payload_inst[0] iBus_rsp_payload_inst[1] iBus_rsp_payload_inst[2] iBus_rsp_payload_inst[3] iBus_rsp_payload_inst[4] iBus_rsp_payload_inst[5] iBus_rsp_payload_inst[6] iBus_rsp_payload_inst[7] iBus_rsp_payload_inst[8] iBus_rsp_payload_inst[9] iBus_rsp_payload_inst[10] iBus_rsp_payload_inst[11] iBus_rsp_payload_inst[12] iBus_rsp_payload_inst[13] iBus_rsp_payload_inst[14] iBus_rsp_payload_inst[15] iBus_rsp_payload_inst[16] iBus_rsp_payload_inst[17] iBus_rsp_payload_inst[18] iBus_rsp_payload_inst[19] iBus_rsp_payload_inst[20] iBus_rsp_payload_inst[21] iBus_rsp_payload_inst[22] iBus_rsp_payload_inst[23] iBus_rsp_payload_inst[24] iBus_rsp_payload_inst[25] iBus_rsp_payload_inst[26] iBus_rsp_payload_inst[27] iBus_rsp_payload_inst[28] iBus_rsp_payload_inst[29] iBus_rsp_payload_inst[30] iBus_rsp_payload_inst[31] timerInterrupt externalInterrupt softwareInterrupt dBus_cmd_ready dBus_rsp_ready dBus_rsp_error dBus_rsp_data[0] dBus_rsp_data[1] dBus_rsp_data[2] dBus_rsp_data[3] dBus_rsp_data[4] dBus_rsp_data[5] dBus_rsp_data[6] dBus_rsp_data[7] dBus_rsp_data[8] dBus_rsp_data[9] dBus_rsp_data[10] dBus_rsp_data[11] dBus_rsp_data[12] dBus_rsp_data[13] dBus_rsp_data[14] dBus_rsp_data[15] dBus_rsp_data[16] dBus_rsp_data[17] dBus_rsp_data[18] dBus_rsp_data[19] dBus_rsp_data[20] dBus_rsp_data[21] dBus_rsp_data[22] dBus_rsp_data[23] dBus_rsp_data[24] dBus_rsp_data[25] dBus_rsp_data[26] dBus_rsp_data[27] dBus_rsp_data[28] dBus_rsp_data[29] dBus_rsp_data[30] dBus_rsp_data[31] clk reset +.outputs iBus_cmd_valid iBus_cmd_payload_pc[0] iBus_cmd_payload_pc[1] iBus_cmd_payload_pc[2] iBus_cmd_payload_pc[3] iBus_cmd_payload_pc[4] iBus_cmd_payload_pc[5] iBus_cmd_payload_pc[6] iBus_cmd_payload_pc[7] iBus_cmd_payload_pc[8] iBus_cmd_payload_pc[9] iBus_cmd_payload_pc[10] iBus_cmd_payload_pc[11] iBus_cmd_payload_pc[12] iBus_cmd_payload_pc[13] iBus_cmd_payload_pc[14] iBus_cmd_payload_pc[15] iBus_cmd_payload_pc[16] iBus_cmd_payload_pc[17] iBus_cmd_payload_pc[18] iBus_cmd_payload_pc[19] iBus_cmd_payload_pc[20] iBus_cmd_payload_pc[21] iBus_cmd_payload_pc[22] iBus_cmd_payload_pc[23] iBus_cmd_payload_pc[24] iBus_cmd_payload_pc[25] iBus_cmd_payload_pc[26] iBus_cmd_payload_pc[27] iBus_cmd_payload_pc[28] iBus_cmd_payload_pc[29] iBus_cmd_payload_pc[30] iBus_cmd_payload_pc[31] dBus_cmd_valid dBus_cmd_payload_wr dBus_cmd_payload_address[0] dBus_cmd_payload_address[1] dBus_cmd_payload_address[2] dBus_cmd_payload_address[3] dBus_cmd_payload_address[4] dBus_cmd_payload_address[5] dBus_cmd_payload_address[6] dBus_cmd_payload_address[7] dBus_cmd_payload_address[8] dBus_cmd_payload_address[9] dBus_cmd_payload_address[10] dBus_cmd_payload_address[11] dBus_cmd_payload_address[12] dBus_cmd_payload_address[13] dBus_cmd_payload_address[14] dBus_cmd_payload_address[15] dBus_cmd_payload_address[16] dBus_cmd_payload_address[17] dBus_cmd_payload_address[18] dBus_cmd_payload_address[19] dBus_cmd_payload_address[20] dBus_cmd_payload_address[21] dBus_cmd_payload_address[22] dBus_cmd_payload_address[23] dBus_cmd_payload_address[24] dBus_cmd_payload_address[25] dBus_cmd_payload_address[26] dBus_cmd_payload_address[27] dBus_cmd_payload_address[28] dBus_cmd_payload_address[29] dBus_cmd_payload_address[30] dBus_cmd_payload_address[31] dBus_cmd_payload_data[0] dBus_cmd_payload_data[1] dBus_cmd_payload_data[2] dBus_cmd_payload_data[3] dBus_cmd_payload_data[4] dBus_cmd_payload_data[5] dBus_cmd_payload_data[6] dBus_cmd_payload_data[7] dBus_cmd_payload_data[8] dBus_cmd_payload_data[9] dBus_cmd_payload_data[10] dBus_cmd_payload_data[11] dBus_cmd_payload_data[12] dBus_cmd_payload_data[13] dBus_cmd_payload_data[14] dBus_cmd_payload_data[15] dBus_cmd_payload_data[16] dBus_cmd_payload_data[17] dBus_cmd_payload_data[18] dBus_cmd_payload_data[19] dBus_cmd_payload_data[20] dBus_cmd_payload_data[21] dBus_cmd_payload_data[22] dBus_cmd_payload_data[23] dBus_cmd_payload_data[24] dBus_cmd_payload_data[25] dBus_cmd_payload_data[26] dBus_cmd_payload_data[27] dBus_cmd_payload_data[28] dBus_cmd_payload_data[29] dBus_cmd_payload_data[30] dBus_cmd_payload_data[31] dBus_cmd_payload_size[0] dBus_cmd_payload_size[1] +.names $false +.names $true +1 +.names $undef +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1273 iBus_cmd_payload_pc[30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$new_n1255 $abc$8788$new_n1254 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$new_n1256 $abc$8788$new_n1255 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$new_n1257 $abc$8788$new_n1256 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1257 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1258 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1259 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1260 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1261 +11 1 +.names IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$new_n1263 $abc$8788$new_n1262 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$new_n1264 $abc$8788$new_n1263 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$new_n1265 $abc$8788$new_n1264 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$new_n1266 $abc$8788$new_n1265 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$new_n1267 $abc$8788$new_n1266 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$new_n1268 $abc$8788$new_n1267 +111 1 +.names IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$new_n1269 $abc$8788$new_n1268 +111 1 +.names IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$new_n1269 +111 1 +.names $abc$8788$new_n1271 memory_arbitration_isValid execute_to_memory_BRANCH_DO $abc$8788$new_n1270 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1272 lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1271 +000 1 +001 1 +010 1 +.names CsrPlugin_interrupt_valid CsrPlugin_pipelineLiberator_done $abc$8788$new_n1272 +11 1 +.names BranchPlugin_jumpInterface_payload[30] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[30] $abc$8788$new_n1273 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz_writeBack_ENV_CTRL lastStageIsFiring _zz_lastStageRegFileWrite_payload_address[28] _zz_lastStageRegFileWrite_payload_address[29] $abc$8788$new_n1274 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[30] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$6999 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n2461 $abc$8788$new_n1270 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1276 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2464 $abc$8788$new_n1296 $abc$8788$new_n1278 +10 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] execute_to_memory_INSTRUCTION[7] $abc$8788$new_n1283 +1100 1 +1111 1 +.names $abc$8788$new_n1286 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n1285 +10000 1 +10011 1 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n1286 +00 1 +11 1 +.names $abc$8788$new_n1289 HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1288 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1290 HazardSimplePlugin_writeBackBuffer_valid HazardSimplePlugin_writeBackBuffer_payload_address[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1289 +1100 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1290 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_lastStageRegFileWrite_valid lastStageIsFiring HazardSimplePlugin_writeBackWrites_valid +11 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1296 +11 1 +.names execute_to_memory_REGFILE_WRITE_VALID memory_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n1304 +1100 1 +1111 1 +.names $abc$8788$new_n1317 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1316 $abc$8788$new_n1315 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1316 +10 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1317 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_arbitration_isValid execute_to_memory_MEMORY_ENABLE dBus_rsp_ready execute_to_memory_MEMORY_STORE $abc$8788$new_n1321 +1100 1 +.names decode_to_execute_IS_CSR execute_arbitration_isValid $abc$8788$new_n1322 +11 1 +.names execute_arbitration_isValid $abc$8788$new_n1324 _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1323 +1001 1 +1010 1 +1011 1 +.names decode_to_execute_SRC2[0] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1324 +00000 1 +.names $abc$8788$new_n1327 $abc$8788$new_n1326 $abc$8788$new_n1325 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[1] decode_to_execute_SRC2[2] $abc$8788$new_n1326 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[4] execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] decode_to_execute_SRC2[4] $abc$8788$new_n1327 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1329 _zz_memory_ENV_CTRL memory_arbitration_isValid lastStageIsFiring _zz_writeBack_ENV_CTRL $abc$8788$new_n1328 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid execute_arbitration_isValid _zz_execute_ENV_CTRL $abc$8788$new_n1329 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n1330 +00001 1 +00010 1 +00011 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$new_n1254 $abc$8788$new_n1332 iBus_cmd_payload_pc[29] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[29] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[29] $abc$8788$new_n1332 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[29] IBusSimplePlugin_fetchPc_pcReg[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7001 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1335 iBus_cmd_payload_pc[28] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[28] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[28] $abc$8788$new_n1335 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[28] IBusSimplePlugin_fetchPc_pcReg[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7003 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$new_n1255 $abc$8788$new_n1338 iBus_cmd_payload_pc[27] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[27] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[27] $abc$8788$new_n1338 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[27] IBusSimplePlugin_fetchPc_pcReg[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7005 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1341 iBus_cmd_payload_pc[26] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[26] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[26] $abc$8788$new_n1341 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[26] IBusSimplePlugin_fetchPc_pcReg[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7007 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$new_n1256 $abc$8788$new_n1344 iBus_cmd_payload_pc[25] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[25] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[25] $abc$8788$new_n1344 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[25] IBusSimplePlugin_fetchPc_pcReg[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7009 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1347 iBus_cmd_payload_pc[24] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[24] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[24] $abc$8788$new_n1347 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[24] IBusSimplePlugin_fetchPc_pcReg[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7011 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$new_n1257 $abc$8788$new_n1350 iBus_cmd_payload_pc[23] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[23] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[23] $abc$8788$new_n1350 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[23] IBusSimplePlugin_fetchPc_pcReg[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7013 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$new_n1258 $abc$8788$new_n1353 iBus_cmd_payload_pc[22] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[22] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[22] $abc$8788$new_n1353 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[22] IBusSimplePlugin_fetchPc_pcReg[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7015 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$new_n1259 $abc$8788$new_n1356 iBus_cmd_payload_pc[21] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[21] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[21] $abc$8788$new_n1356 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[21] IBusSimplePlugin_fetchPc_pcReg[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7017 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$new_n1260 $abc$8788$new_n1359 iBus_cmd_payload_pc[20] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[20] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[20] $abc$8788$new_n1359 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[20] IBusSimplePlugin_fetchPc_pcReg[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7019 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$new_n1261 $abc$8788$new_n1362 iBus_cmd_payload_pc[19] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[19] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[19] $abc$8788$new_n1362 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[19] IBusSimplePlugin_fetchPc_pcReg[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7021 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$new_n1262 $abc$8788$new_n1365 iBus_cmd_payload_pc[18] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[18] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[18] $abc$8788$new_n1365 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[18] IBusSimplePlugin_fetchPc_pcReg[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7023 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1368 iBus_cmd_payload_pc[17] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[17] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[17] $abc$8788$new_n1368 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[17] IBusSimplePlugin_fetchPc_pcReg[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7025 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$new_n1263 $abc$8788$new_n1371 iBus_cmd_payload_pc[16] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[16] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[16] $abc$8788$new_n1371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[16] IBusSimplePlugin_fetchPc_pcReg[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7027 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1374 iBus_cmd_payload_pc[15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[15] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[15] $abc$8788$new_n1374 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[15] IBusSimplePlugin_fetchPc_pcReg[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7029 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$new_n1264 $abc$8788$new_n1377 iBus_cmd_payload_pc[14] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[14] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[14] $abc$8788$new_n1377 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[14] IBusSimplePlugin_fetchPc_pcReg[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7031 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1380 iBus_cmd_payload_pc[13] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[13] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[13] $abc$8788$new_n1380 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[13] IBusSimplePlugin_fetchPc_pcReg[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7033 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$new_n1265 $abc$8788$new_n1383 iBus_cmd_payload_pc[12] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[12] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[12] $abc$8788$new_n1383 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[12] IBusSimplePlugin_fetchPc_pcReg[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7035 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1386 iBus_cmd_payload_pc[11] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[11] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[11] $abc$8788$new_n1386 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[11] IBusSimplePlugin_fetchPc_pcReg[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7037 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$new_n1266 $abc$8788$new_n1389 iBus_cmd_payload_pc[10] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[10] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[10] $abc$8788$new_n1389 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[10] IBusSimplePlugin_fetchPc_pcReg[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7039 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1392 iBus_cmd_payload_pc[9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[9] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[9] $abc$8788$new_n1392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[9] IBusSimplePlugin_fetchPc_pcReg[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7041 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$new_n1267 $abc$8788$new_n1395 iBus_cmd_payload_pc[8] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[8] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[8] $abc$8788$new_n1395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[8] IBusSimplePlugin_fetchPc_pcReg[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7043 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1398 iBus_cmd_payload_pc[7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[7] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[7] $abc$8788$new_n1398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[7] IBusSimplePlugin_fetchPc_pcReg[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7045 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$new_n1268 $abc$8788$new_n1401 iBus_cmd_payload_pc[6] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[6] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[6] $abc$8788$new_n1401 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[6] IBusSimplePlugin_fetchPc_pcReg[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7047 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1404 iBus_cmd_payload_pc[5] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n1271 BranchPlugin_jumpInterface_payload[5] $abc$8788$new_n1274 CsrPlugin_mepc[5] $abc$8788$new_n1404 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[5] IBusSimplePlugin_fetchPc_pcReg[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7049 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$new_n1269 $abc$8788$new_n1407 iBus_cmd_payload_pc[4] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[4] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[4] $abc$8788$new_n1407 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[4] IBusSimplePlugin_fetchPc_pcReg[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7051 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1410 iBus_cmd_payload_pc[3] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names BranchPlugin_jumpInterface_payload[3] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[3] $abc$8788$new_n1410 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[3] IBusSimplePlugin_fetchPc_pcReg[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7053 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_inc IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$new_n1413 iBus_cmd_payload_pc[2] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names BranchPlugin_jumpInterface_payload[2] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[2] $abc$8788$new_n1413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[2] IBusSimplePlugin_fetchPc_pcReg[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7055 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[30] CsrPlugin_mepc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7439 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[29] CsrPlugin_mepc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7441 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[28] CsrPlugin_mepc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7443 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[27] CsrPlugin_mepc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7445 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[26] CsrPlugin_mepc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7447 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[25] CsrPlugin_mepc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7449 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[24] CsrPlugin_mepc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7451 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[23] CsrPlugin_mepc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7453 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[22] CsrPlugin_mepc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7455 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[21] CsrPlugin_mepc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7457 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[20] CsrPlugin_mepc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7459 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[19] CsrPlugin_mepc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7461 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[18] CsrPlugin_mepc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7463 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[17] CsrPlugin_mepc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7465 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[16] CsrPlugin_mepc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7467 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[15] CsrPlugin_mepc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7469 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[14] CsrPlugin_mepc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7471 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[13] CsrPlugin_mepc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7473 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[12] CsrPlugin_mepc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7475 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[11] CsrPlugin_mepc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7477 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[10] CsrPlugin_mepc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7479 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[9] CsrPlugin_mepc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7481 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[8] CsrPlugin_mepc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7483 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[7] CsrPlugin_mepc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7485 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[6] CsrPlugin_mepc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7487 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[5] CsrPlugin_mepc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7489 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[4] CsrPlugin_mepc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7491 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[3] CsrPlugin_mepc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7493 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[2] CsrPlugin_mepc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7495 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1446 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7497 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1321 $abc$8788$new_n1445 +10 1 +.names $abc$8788$new_n1447 $abc$8788$new_n1326 $abc$8788$new_n1446 +11 1 +.names execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[0] decode_to_execute_SRC2[0] $abc$8788$new_n1447 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1449 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[2] decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7499 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$new_n1449 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_isActive execute_LightShifterPlugin_amplitudeReg[1] decode_to_execute_SRC2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7501 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1447 execute_LightShifterPlugin_amplitudeReg[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7503 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7741 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n1454 $abc$8788$new_n1453 +11 1 +.names $abc$8788$new_n1455 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n1454 +1000 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n2461 $abc$8788$new_n1455 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7743 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7745 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7747 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7749 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] iBus_rsp_payload_inst[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7751 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7753 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7755 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7757 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7759 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7761 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7763 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7765 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7767 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7769 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7771 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] iBus_rsp_payload_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7773 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7775 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7777 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7779 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7781 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7783 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] iBus_rsp_payload_inst[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7785 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] iBus_rsp_payload_inst[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7787 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7789 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7791 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7793 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7795 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7797 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[2] CsrPlugin_mcause_exceptionCode[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7861 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 $abc$8788$new_n1445 $abc$8788$new_n1325 execute_LightShifterPlugin_isActive $abc$8788$auto$rtlil.cc:2693:MuxGate$7863 +1001 1 +1011 1 +1100 1 +1101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid CsrPlugin_pipelineLiberator_pcValids_1 $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7865 +1111 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n1488 $abc$8788$auto$rtlil.cc:2693:MuxGate$7867 +1110 1 +.names $abc$8788$new_n1321 CsrPlugin_pipelineLiberator_pcValids_1 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$new_n1488 +000 1 +010 1 +100 1 +101 1 +.names CsrPlugin_interrupt_valid IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n1270 $abc$8788$new_n2458 CsrPlugin_pipelineLiberator_pcValids_0 $abc$8788$auto$rtlil.cc:2693:MuxGate$7869 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1492 CsrPlugin_mie_MSIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7871 +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_772 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n1491 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1493 $abc$8788$new_n1492 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1494 execute_CsrPlugin_csr_772 CsrPlugin_mie_MSIE execute_CsrPlugin_csr_768 CsrPlugin_mstatus_MIE $abc$8788$new_n1493 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[3] CsrPlugin_mip_MSIP execute_CsrPlugin_csr_836 $abc$8788$new_n1494 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1496 CsrPlugin_mie_MTIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7873 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1497 $abc$8788$new_n1496 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1498 execute_CsrPlugin_csr_836 CsrPlugin_mip_MTIP $abc$8788$new_n1497 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MTIE CsrPlugin_mstatus_MPIE execute_CsrPlugin_csr_768 $abc$8788$new_n1498 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1491 $abc$8788$new_n1500 CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7875 +001 1 +011 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] switch_Misc_l241_1 dBus_cmd_payload_size[0] $abc$8788$new_n1501 $abc$8788$new_n1500 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$8788$new_n1502 execute_CsrPlugin_csr_836 CsrPlugin_mip_MEIP $abc$8788$new_n1501 +100 1 +101 1 +110 1 +.names execute_CsrPlugin_csr_772 CsrPlugin_mie_MEIE CsrPlugin_mstatus_MPP[0] execute_CsrPlugin_csr_768 $abc$8788$new_n1502 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_injector_decodeInput_valid IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7877 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1270 $abc$8788$new_n1505 $abc$8788$new_n2461 $abc$8788$new_n1330 $abc$8788$auto$rtlil.cc:2693:MuxGate$7879 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names iBus_cmd_ready iBus_cmd_valid $abc$8788$new_n1505 +11 1 +.names $abc$8788$new_n1507 $abc$8788$new_n2461 $abc$8788$new_n1330 IBusSimplePlugin_iBusRsp_stages_1_input_valid iBus_cmd_valid +1100 1 +1110 1 +1111 1 +.names IBusSimplePlugin_fetchPc_booted $abc$8788$new_n1271 IBusSimplePlugin_pending_value[2] IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[0] $abc$8788$new_n1507 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8788$new_n1509 $abc$8788$new_n1505 $abc$8788$auto$rtlil.cc:2693:MuxGate$7881 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_fetchPc_inc $abc$8788$new_n1270 $abc$8788$new_n2461 IBusSimplePlugin_iBusRsp_stages_1_input_valid $abc$8788$new_n1330 $abc$8788$new_n1509 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names $abc$8788$new_n1271 $abc$8788$new_n1321 $abc$8788$new_n2458 execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$auto$rtlil.cc:2693:MuxGate$7883 +00111 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2461 execute_arbitration_isValid $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7885 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive $abc$8788$new_n1513 execute_LightShifterPlugin_amplitudeReg[4] $abc$8788$new_n1445 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7949 +00100 1 +00101 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 execute_LightShifterPlugin_isActive $abc$8788$new_n1446 execute_LightShifterPlugin_amplitudeReg[3] decode_to_execute_SRC2[3] $abc$8788$new_n1513 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1517 CsrPlugin_interrupt_code[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7953 +001 1 +011 1 +110 1 +111 1 +.names CsrPlugin_mstatus_MIE $abc$8788$new_n1517 CsrPlugin_mip_MTIP CsrPlugin_mie_MTIE $abc$8788$new_n1516 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CsrPlugin_mip_MSIP CsrPlugin_mie_MSIE CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$new_n1517 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1516 CsrPlugin_interrupt_code[3] CsrPlugin_mip_MEIP CsrPlugin_mie_MEIE $abc$8788$auto$rtlil.cc:2693:MuxGate$7957 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n1330 $abc$8788$new_n1455 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$auto$rtlil.cc:2693:MuxGate$7961 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1453 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7963 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$new_n1522 $abc$8788$new_n1523 iBus_cmd_payload_pc[31] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_fetchPc_pcReg[30] $abc$8788$new_n1255 $abc$8788$new_n1522 +11111 1 +.names BranchPlugin_jumpInterface_payload[31] $abc$8788$new_n1271 $abc$8788$new_n1274 CsrPlugin_mepc[31] $abc$8788$new_n1523 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n1276 iBus_cmd_payload_pc[31] IBusSimplePlugin_fetchPc_pcReg[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7967 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 CsrPlugin_interrupt_code[3] CsrPlugin_mcause_exceptionCode[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7969 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1272 IBusSimplePlugin_injector_decodeInput_payload_pc[31] CsrPlugin_mepc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7975 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1594 $abc$8788$new_n1590 dBus_cmd_payload_address[30] $abc$8788$new_n1595 $abc$8788$auto$rtlil.cc:2693:MuxGate$7057 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1529 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[30] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 $abc$8788$new_n1529 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1584 $abc$8788$new_n1531 $abc$8788$new_n1530 +00 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1581 $abc$8788$new_n1531 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1533 $abc$8788$new_n1580 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1578 $abc$8788$new_n1532 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1534 $abc$8788$new_n1577 _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1575 $abc$8788$new_n1533 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1535 $abc$8788$new_n1574 _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1572 $abc$8788$new_n1534 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1536 $abc$8788$new_n1569 _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1570 $abc$8788$new_n1535 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1537 $abc$8788$new_n1568 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1565 $abc$8788$new_n1536 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1538 $abc$8788$new_n1564 _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1562 $abc$8788$new_n1537 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names $abc$8788$new_n1559 $abc$8788$new_n1557 $abc$8788$new_n1561 $abc$8788$new_n1560 $abc$8788$new_n1539 $abc$8788$new_n1538 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1540 $abc$8788$new_n1539 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1554 $abc$8788$new_n1541 $abc$8788$new_n1553 $abc$8788$new_n1540 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1542 $abc$8788$new_n1541 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n1548 _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1549 $abc$8788$new_n1543 $abc$8788$new_n1542 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[3] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1544 $abc$8788$new_n1543 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[3] $abc$8788$new_n1544 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[2] $abc$8788$new_n1545 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[1] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[1] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01100 1 +10100 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[5] $abc$8788$new_n1547 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1548 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[4] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[4] $abc$8788$new_n1549 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[7] $abc$8788$new_n1550 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[6] $abc$8788$new_n1551 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[9] $abc$8788$new_n1552 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[8] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[8] $abc$8788$new_n1553 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n1554 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[11] $abc$8788$new_n1555 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[10] $abc$8788$new_n1556 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1558 $abc$8788$new_n1557 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[12] $abc$8788$new_n1558 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n1559 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n1560 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] $abc$8788$new_n1561 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n1562 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[15] $abc$8788$new_n1563 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1564 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1565 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[18] $abc$8788$new_n1566 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[17] $abc$8788$new_n1567 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1568 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1566 $abc$8788$new_n1569 +10 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n1570 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[19] $abc$8788$new_n1571 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n1572 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[21] $abc$8788$new_n1573 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1574 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n1575 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[23] $abc$8788$new_n1576 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1577 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n1578 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[25] $abc$8788$new_n1579 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1580 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n1581 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[27] $abc$8788$new_n1582 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[26] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[26] $abc$8788$new_n1583 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1584 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[29] $abc$8788$new_n1585 +00 1 +11 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1587 $abc$8788$new_n1586 +11 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 $abc$8788$new_n1587 +00 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1322 $abc$8788$new_n1588 +00 1 +.names _zz_execute_ALU_CTRL[0] _zz_execute_ALU_CTRL[1] $abc$8788$new_n1589 +10 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[30] $abc$8788$new_n1323 $abc$8788$new_n1591 $abc$8788$new_n1590 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1593 execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n1591 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] $abc$8788$new_n1592 +10 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[29] _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1593 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1594 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names _zz_execute_ALU_CTRL[1] _zz_execute_ALU_CTRL[0] $abc$8788$new_n1595 +10 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1598 dBus_cmd_payload_address[29] $abc$8788$new_n1601 $abc$8788$auto$rtlil.cc:2693:MuxGate$7059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1530 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[29] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[29] $abc$8788$new_n1323 $abc$8788$new_n1599 $abc$8788$new_n1598 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1600 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n1599 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[28] _zz_execute_SrcPlugin_addSub_2[28] $abc$8788$new_n1600 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1601 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1605 dBus_cmd_payload_address[28] $abc$8788$new_n1608 $abc$8788$auto$rtlil.cc:2693:MuxGate$7061 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[28] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[28] $abc$8788$new_n1604 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[28] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1532 $abc$8788$new_n1583 _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1604 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[28] $abc$8788$new_n1323 $abc$8788$new_n1606 $abc$8788$new_n1605 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1607 $abc$8788$new_n1593 $abc$8788$new_n1606 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[27] _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1607 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1608 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1611 dBus_cmd_payload_address[27] $abc$8788$new_n1614 $abc$8788$auto$rtlil.cc:2693:MuxGate$7063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[27] $abc$8788$new_n1582 $abc$8788$new_n1583 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1532 dBus_cmd_payload_address[27] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[27] $abc$8788$new_n1323 $abc$8788$new_n1612 $abc$8788$new_n1611 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 $abc$8788$new_n1613 $abc$8788$new_n1600 $abc$8788$new_n1612 +001 1 +011 1 +110 1 +111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[26] _zz_execute_SrcPlugin_addSub_2[26] $abc$8788$new_n1613 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1614 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1618 dBus_cmd_payload_address[26] $abc$8788$new_n1620 $abc$8788$auto$rtlil.cc:2693:MuxGate$7065 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1617 _zz_execute_SrcPlugin_addSub_2[26] dBus_cmd_payload_address[26] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1578 _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 $abc$8788$new_n1533 $abc$8788$new_n1617 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[26] $abc$8788$new_n1323 $abc$8788$new_n1619 $abc$8788$new_n1618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1607 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1619 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1620 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1622 execute_to_memory_REGFILE_WRITE_DATA[25] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7067 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1624 $abc$8788$new_n1626 $abc$8788$new_n1586 dBus_cmd_payload_address[25] $abc$8788$new_n1595 $abc$8788$new_n1622 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1579 $abc$8788$new_n1580 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1533 dBus_cmd_payload_address[25] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1625 $abc$8788$new_n1613 $abc$8788$new_n1624 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[24] _zz_execute_SrcPlugin_addSub_2[24] $abc$8788$new_n1625 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1626 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1631 dBus_cmd_payload_address[24] $abc$8788$new_n1634 $abc$8788$auto$rtlil.cc:2693:MuxGate$7069 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[24] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[24] $abc$8788$new_n1629 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[24] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 $abc$8788$new_n1629 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1577 $abc$8788$new_n1534 $abc$8788$new_n1630 +00 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[24] $abc$8788$new_n1323 $abc$8788$new_n1632 $abc$8788$new_n1631 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1633 execute_to_memory_REGFILE_WRITE_DATA[25] _zz_execute_SrcPlugin_addSub_2[25] $abc$8788$new_n1632 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[23] _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1633 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1634 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1636 execute_to_memory_REGFILE_WRITE_DATA[23] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7071 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1638 $abc$8788$new_n1640 $abc$8788$new_n1586 dBus_cmd_payload_address[23] $abc$8788$new_n1595 $abc$8788$new_n1636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[23] $abc$8788$new_n1576 $abc$8788$new_n1630 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[23] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1639 $abc$8788$new_n1625 $abc$8788$new_n1638 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[22] _zz_execute_SrcPlugin_addSub_2[22] $abc$8788$new_n1639 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1640 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1642 execute_to_memory_REGFILE_WRITE_DATA[22] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7073 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1646 $abc$8788$new_n1648 $abc$8788$new_n1586 dBus_cmd_payload_address[22] $abc$8788$new_n1595 $abc$8788$new_n1642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[22] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[22] $abc$8788$new_n1644 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[22] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 $abc$8788$new_n1644 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1574 $abc$8788$new_n1535 $abc$8788$new_n1645 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1647 $abc$8788$new_n1633 $abc$8788$new_n1646 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[21] _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1647 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1648 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1653 $abc$8788$new_n1650 $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7075 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 dBus_cmd_payload_address[21] $abc$8788$new_n1652 $abc$8788$new_n1650 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] $abc$8788$new_n1573 $abc$8788$new_n1645 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[21] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1652 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1654 $abc$8788$new_n1639 $abc$8788$new_n1653 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[20] _zz_execute_SrcPlugin_addSub_2[20] $abc$8788$new_n1654 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1656 execute_to_memory_REGFILE_WRITE_DATA[20] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7077 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1660 $abc$8788$new_n1662 $abc$8788$new_n1586 dBus_cmd_payload_address[20] $abc$8788$new_n1595 $abc$8788$new_n1656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[20] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[20] $abc$8788$new_n1658 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[20] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 $abc$8788$new_n1658 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1569 $abc$8788$new_n1536 $abc$8788$new_n1659 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1661 $abc$8788$new_n1647 $abc$8788$new_n1660 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[19] _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1661 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1662 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1664 execute_to_memory_REGFILE_WRITE_DATA[19] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7079 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1666 $abc$8788$new_n1586 $abc$8788$new_n1668 $abc$8788$new_n1595 dBus_cmd_payload_address[19] $abc$8788$new_n1664 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names _zz_execute_SrcPlugin_addSub_2[19] $abc$8788$new_n1571 $abc$8788$new_n1659 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[19] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1667 $abc$8788$new_n1654 $abc$8788$new_n1666 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[18] _zz_execute_SrcPlugin_addSub_2[18] $abc$8788$new_n1667 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1668 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11100 1 +11111 1 +.names $abc$8788$new_n1670 execute_to_memory_REGFILE_WRITE_DATA[18] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7081 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1673 $abc$8788$new_n1675 $abc$8788$new_n1586 dBus_cmd_payload_address[18] $abc$8788$new_n1595 $abc$8788$new_n1670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1672 _zz_execute_SrcPlugin_addSub_2[18] dBus_cmd_payload_address[18] +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1565 _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 $abc$8788$new_n1537 $abc$8788$new_n1672 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1674 $abc$8788$new_n1661 $abc$8788$new_n1673 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[17] _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1674 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1675 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1678 dBus_cmd_payload_address[17] $abc$8788$new_n1680 $abc$8788$auto$rtlil.cc:2693:MuxGate$7083 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] $abc$8788$new_n1567 $abc$8788$new_n1568 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1537 dBus_cmd_payload_address[17] +00000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[17] $abc$8788$new_n1323 $abc$8788$new_n1679 $abc$8788$new_n1678 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1667 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1680 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1682 execute_to_memory_REGFILE_WRITE_DATA[16] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7085 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1686 $abc$8788$new_n1688 $abc$8788$new_n1586 dBus_cmd_payload_address[16] $abc$8788$new_n1595 $abc$8788$new_n1682 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names _zz_execute_SrcPlugin_addSub_2[16] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[16] $abc$8788$new_n1684 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[16] +00010 1 +00100 1 +01000 1 +01110 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 $abc$8788$new_n1684 +000 1 +100 1 +101 1 +110 1 +.names $abc$8788$new_n1564 $abc$8788$new_n1538 $abc$8788$new_n1685 +00 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1687 $abc$8788$new_n1674 $abc$8788$new_n1686 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[15] _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1687 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1688 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1586 $abc$8788$new_n1595 $abc$8788$new_n1691 dBus_cmd_payload_address[15] $abc$8788$new_n1694 $abc$8788$auto$rtlil.cc:2693:MuxGate$7087 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[15] $abc$8788$new_n1563 $abc$8788$new_n1685 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[15] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[15] $abc$8788$new_n1323 $abc$8788$new_n1692 $abc$8788$new_n1691 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1693 execute_to_memory_REGFILE_WRITE_DATA[16] _zz_execute_SrcPlugin_addSub_2[16] $abc$8788$new_n1692 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[14] _zz_execute_SrcPlugin_addSub_2[14] $abc$8788$new_n1693 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1694 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1696 execute_to_memory_REGFILE_WRITE_DATA[14] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7089 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1700 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[14] $abc$8788$new_n1702 $abc$8788$new_n1696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[14] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[14] $abc$8788$new_n1698 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[14] +00000 1 +00110 1 +01010 1 +01100 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1557 $abc$8788$new_n1699 $abc$8788$new_n1560 $abc$8788$new_n1698 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1561 $abc$8788$new_n1539 $abc$8788$new_n1699 +10 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1701 $abc$8788$new_n1687 $abc$8788$new_n1700 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[13] _zz_execute_SrcPlugin_addSub_2[13] $abc$8788$new_n1701 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1702 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1704 execute_to_memory_REGFILE_WRITE_DATA[13] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7091 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1706 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[13] $abc$8788$new_n1708 $abc$8788$new_n1704 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1560 $abc$8788$new_n1558 $abc$8788$new_n1699 _zz_execute_SrcPlugin_addSub_2[13] dBus_cmd_payload_address[13] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1707 $abc$8788$new_n1693 $abc$8788$new_n1706 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[12] _zz_execute_SrcPlugin_addSub_2[12] $abc$8788$new_n1707 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1708 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1710 execute_to_memory_REGFILE_WRITE_DATA[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7093 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1711 $abc$8788$new_n1592 $abc$8788$new_n1323 $abc$8788$new_n1715 $abc$8788$new_n1701 $abc$8788$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$8788$new_n1713 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[12] $abc$8788$new_n1714 $abc$8788$new_n1711 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1539 $abc$8788$new_n1561 _zz_execute_SrcPlugin_addSub_2[12] dBus_cmd_payload_address[12] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1323 execute_CsrPlugin_csr_768 $abc$8788$new_n1322 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1713 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1714 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[11] _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1715 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1717 execute_to_memory_REGFILE_WRITE_DATA[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7095 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1722 $abc$8788$new_n1718 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1501 $abc$8788$new_n1717 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[11] $abc$8788$new_n1721 $abc$8788$new_n1718 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[11] $abc$8788$new_n1555 $abc$8788$new_n1720 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[11] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1556 _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1540 $abc$8788$new_n1720 +000 1 +100 1 +101 1 +110 1 +.names _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1721 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1723 $abc$8788$new_n1707 $abc$8788$new_n1722 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[10] _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1723 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1725 execute_to_memory_REGFILE_WRITE_DATA[10] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7097 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1727 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[10] $abc$8788$new_n1729 $abc$8788$new_n1725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[10] $abc$8788$new_n1556 $abc$8788$new_n1540 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[10] +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1728 $abc$8788$new_n1715 $abc$8788$new_n1727 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[9] _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1728 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1729 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[9] $abc$8788$new_n1731 $abc$8788$new_n1735 $abc$8788$auto$rtlil.cc:2693:MuxGate$7099 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1734 dBus_cmd_payload_address[9] $abc$8788$new_n1595 $abc$8788$new_n1731 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[9] $abc$8788$new_n1552 $abc$8788$new_n1733 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[9] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1553 $abc$8788$new_n1541 $abc$8788$new_n1554 $abc$8788$new_n1733 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1734 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1736 $abc$8788$new_n1723 $abc$8788$new_n1735 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[8] _zz_execute_SrcPlugin_addSub_2[8] $abc$8788$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[8] $abc$8788$new_n1738 $abc$8788$new_n1741 $abc$8788$auto$rtlil.cc:2693:MuxGate$7101 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1740 dBus_cmd_payload_address[8] $abc$8788$new_n1595 $abc$8788$new_n1738 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1541 $abc$8788$new_n1554 _zz_execute_SrcPlugin_addSub_2[8] dBus_cmd_payload_address[8] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1740 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1742 $abc$8788$new_n1728 $abc$8788$new_n1741 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[7] _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1744 execute_to_memory_REGFILE_WRITE_DATA[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7103 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1749 $abc$8788$new_n1745 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1497 $abc$8788$new_n1744 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1748 dBus_cmd_payload_address[7] $abc$8788$new_n1595 $abc$8788$new_n1745 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] $abc$8788$new_n1550 $abc$8788$new_n1747 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[7] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1551 _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1542 $abc$8788$new_n1747 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1748 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1750 $abc$8788$new_n1736 $abc$8788$new_n1749 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[6] _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1750 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1752 execute_to_memory_REGFILE_WRITE_DATA[6] $abc$8788$new_n1323 $abc$8788$new_n1755 $abc$8788$auto$rtlil.cc:2693:MuxGate$7105 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1754 dBus_cmd_payload_address[6] $abc$8788$new_n1595 $abc$8788$new_n1752 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] $abc$8788$new_n1551 $abc$8788$new_n1542 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[6] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1754 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1742 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1755 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1757 execute_to_memory_REGFILE_WRITE_DATA[5] $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7107 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8788$new_n1760 $abc$8788$new_n1595 $abc$8788$new_n1586 dBus_cmd_payload_address[5] $abc$8788$new_n1762 $abc$8788$new_n1757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1547 $abc$8788$new_n1759 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[5] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1548 $abc$8788$new_n1543 $abc$8788$new_n1549 $abc$8788$new_n1759 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1445 $abc$8788$new_n1592 $abc$8788$new_n1761 $abc$8788$new_n1750 $abc$8788$new_n1760 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[4] _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n1761 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1762 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1764 execute_to_memory_REGFILE_WRITE_DATA[4] $abc$8788$new_n1323 $abc$8788$new_n1767 $abc$8788$auto$rtlil.cc:2693:MuxGate$7109 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1323 $abc$8788$new_n1766 dBus_cmd_payload_address[4] $abc$8788$new_n1595 $abc$8788$new_n1764 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1543 $abc$8788$new_n1549 _zz_execute_SrcPlugin_addSub_2[4] dBus_cmd_payload_address[4] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1595 _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1766 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1768 execute_to_memory_REGFILE_WRITE_DATA[5] _zz_execute_SrcPlugin_addSub_2[5] $abc$8788$new_n1767 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[3] _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1768 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1770 execute_to_memory_REGFILE_WRITE_DATA[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7111 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n1775 $abc$8788$new_n1771 $abc$8788$new_n1323 $abc$8788$new_n1322 $abc$8788$new_n1493 $abc$8788$new_n1770 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 dBus_cmd_payload_address[3] $abc$8788$new_n1774 $abc$8788$new_n1771 +1010 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n1544 $abc$8788$new_n1773 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[3] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n1546 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1545 $abc$8788$new_n1773 +001 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1774 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1776 $abc$8788$new_n1761 $abc$8788$new_n1775 +1001 1 +1011 1 +1110 1 +1111 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[2] _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1776 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_DATA[2] $abc$8788$new_n1783 $abc$8788$new_n1781 $abc$8788$new_n1778 $abc$8788$auto$rtlil.cc:2693:MuxGate$7113 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1588 $abc$8788$new_n1595 $abc$8788$new_n1323 dBus_cmd_payload_address[2] $abc$8788$new_n1780 $abc$8788$new_n1778 +10010 1 +10011 1 +11001 1 +11011 1 +.names _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$new_n1546 $abc$8788$new_n1545 decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[2] +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1780 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1592 $abc$8788$new_n1782 $abc$8788$new_n1768 $abc$8788$new_n1781 +1000 1 +1010 1 +1100 1 +1101 1 +.names execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[1] _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n1782 +000 1 +010 1 +100 1 +101 1 +.names execute_CsrPlugin_csr_834 CsrPlugin_mcause_exceptionCode[2] $abc$8788$new_n1322 $abc$8788$new_n1323 $abc$8788$new_n1783 +1110 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1785 execute_to_memory_REGFILE_WRITE_DATA[1] $abc$8788$new_n1323 $abc$8788$new_n1790 $abc$8788$auto$rtlil.cc:2693:MuxGate$7115 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[1] $abc$8788$new_n1789 $abc$8788$new_n1785 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$8788$new_n1323 $abc$8788$new_n1322 execute_CsrPlugin_csr_834 $abc$8788$new_n1786 +000 1 +001 1 +010 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1788 _zz_execute_SrcPlugin_addSub_2[1] dBus_cmd_payload_address[1] +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] $abc$8788$new_n1788 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1789 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n1592 execute_LightShifterPlugin_isActive $abc$8788$new_n1776 execute_to_memory_REGFILE_WRITE_DATA[0] _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n1790 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n1803 $abc$8788$new_n1322 $abc$8788$new_n1587 $abc$8788$new_n1792 execute_CsrPlugin_csr_834 $abc$8788$auto$rtlil.cc:2693:MuxGate$7117 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1589 $abc$8788$new_n1799 $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n1792 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n1796 $abc$8788$new_n1798 $abc$8788$new_n1794 _zz_execute_SrcPlugin_addSub_2[31] dBus_cmd_payload_address[31] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1531 $abc$8788$new_n1584 _zz_execute_SrcPlugin_addSub_2[29] $abc$8788$new_n1585 $abc$8788$new_n1795 $abc$8788$new_n1794 +00101 1 +01001 1 +01101 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_4 _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n1795 +001 1 +010 1 +100 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_4 $abc$8788$new_n1797 $abc$8788$new_n1796 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] $abc$8788$new_n1797 +00 1 +11 1 +.names _zz_execute_SrcPlugin_addSub_2[30] _zz_execute_SrcPlugin_addSub_4 decode_to_execute_SRC2[30] $abc$8788$new_n1798 +101 1 +110 1 +.names $abc$8788$new_n1595 $abc$8788$new_n1800 dBus_cmd_payload_address[0] $abc$8788$new_n1799 +000 1 +010 1 +110 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n1800 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +1010 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] decode_to_execute_SRC2_FORCE_ZERO dBus_cmd_payload_address[0] +010 1 +100 1 +101 1 +111 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC_LESS_UNSIGNED decode_to_execute_SRC2[31] $abc$8788$new_n1802 +000 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n1323 execute_to_memory_REGFILE_WRITE_DATA[0] $abc$8788$new_n1782 $abc$8788$new_n1592 $abc$8788$new_n1803 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_to_memory_MEMORY_ADDRESS_LOW[0] dBus_cmd_payload_address[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7119 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1806 decode_to_execute_SRC2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7121 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] _zz_decode_SRC2 $abc$8788$new_n1806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n1807 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1809 decode_to_execute_SRC2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7123 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] _zz_decode_SRC2 $abc$8788$new_n1809 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1811 decode_to_execute_SRC2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7125 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] _zz_decode_SRC2 $abc$8788$new_n1811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1813 decode_to_execute_SRC2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7127 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] _zz_decode_SRC2 $abc$8788$new_n1813 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1815 decode_to_execute_SRC2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7129 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] _zz_decode_SRC2 $abc$8788$new_n1815 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1817 decode_to_execute_SRC2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7131 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] _zz_decode_SRC2 $abc$8788$new_n1817 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1819 decode_to_execute_SRC2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7133 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] _zz_decode_SRC2 $abc$8788$new_n1819 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1821 decode_to_execute_SRC2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7135 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] _zz_decode_SRC2 $abc$8788$new_n1821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1823 decode_to_execute_SRC2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7137 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] _zz_decode_SRC2 $abc$8788$new_n1823 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1825 decode_to_execute_SRC2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7139 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] _zz_decode_SRC2 $abc$8788$new_n1825 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1827 decode_to_execute_SRC2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7141 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] _zz_decode_SRC2 $abc$8788$new_n1827 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1829 decode_to_execute_SRC2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7143 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] _zz_decode_SRC2 $abc$8788$new_n1829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1831 decode_to_execute_SRC2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7145 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] _zz_decode_SRC2 $abc$8788$new_n1831 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1833 decode_to_execute_SRC2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7147 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] _zz_decode_SRC2 $abc$8788$new_n1833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1835 decode_to_execute_SRC2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7149 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] _zz_decode_SRC2 $abc$8788$new_n1835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1837 decode_to_execute_SRC2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7151 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] _zz_decode_SRC2 $abc$8788$new_n1837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1839 decode_to_execute_SRC2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7153 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] _zz_decode_SRC2 $abc$8788$new_n1839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1841 decode_to_execute_SRC2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7155 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] _zz_decode_SRC2 $abc$8788$new_n1841 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1843 decode_to_execute_SRC2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7157 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] _zz_decode_SRC2 $abc$8788$new_n1843 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1845 decode_to_execute_SRC2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7159 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] _zz_decode_SRC2 $abc$8788$new_n1845 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1847 decode_to_execute_SRC2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7161 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n1847 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1849 decode_to_execute_SRC2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7163 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] $abc$8788$new_n1849 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1851 decode_to_execute_SRC2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7165 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] $abc$8788$new_n1851 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1853 decode_to_execute_SRC2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7167 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n1853 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1855 decode_to_execute_SRC2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7169 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n1855 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1857 decode_to_execute_SRC2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7171 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] $abc$8788$new_n1857 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1859 decode_to_execute_SRC2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7173 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1860 _zz_RegFilePlugin_regFile_port1[4] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[4] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1859 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n1860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n1861 +1000 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 $abc$8788$new_n1862 +00 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1864 decode_to_execute_SRC2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7175 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1865 _zz_RegFilePlugin_regFile_port1[3] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[3] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1864 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n1865 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1867 decode_to_execute_SRC2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7177 +001 1 +011 1 +100 1 +101 1 +.names $abc$8788$new_n1868 _zz_RegFilePlugin_regFile_port1[2] $abc$8788$new_n1807 IBusSimplePlugin_injector_decodeInput_payload_pc[2] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1867 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$new_n1861 $abc$8788$new_n1862 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n1868 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1870 decode_to_execute_SRC2[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[1] $abc$8788$new_n1870 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1872 decode_to_execute_SRC2[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] $abc$8788$new_n1862 $abc$8788$auto$rtlil.cc:2693:MuxGate$7181 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] $abc$8788$new_n1861 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[0] $abc$8788$new_n1872 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[30] decode_to_execute_RS2[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7183 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[29] decode_to_execute_RS2[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7185 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[28] decode_to_execute_RS2[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7187 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[27] decode_to_execute_RS2[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7189 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[26] decode_to_execute_RS2[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7191 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[25] decode_to_execute_RS2[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7193 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[24] decode_to_execute_RS2[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7195 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[23] decode_to_execute_RS2[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7197 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[22] decode_to_execute_RS2[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7199 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[21] decode_to_execute_RS2[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7201 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[20] decode_to_execute_RS2[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7203 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[19] decode_to_execute_RS2[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7205 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[18] decode_to_execute_RS2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7207 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[17] decode_to_execute_RS2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7209 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[16] decode_to_execute_RS2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7211 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[15] decode_to_execute_RS2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7213 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[14] decode_to_execute_RS2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7215 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[13] decode_to_execute_RS2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7217 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[12] decode_to_execute_RS2[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7219 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[11] decode_to_execute_RS2[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7221 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[10] decode_to_execute_RS2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7223 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[9] decode_to_execute_RS2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7225 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[8] decode_to_execute_RS2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7227 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[7] dBus_cmd_payload_data[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7229 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[6] dBus_cmd_payload_data[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7231 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[5] dBus_cmd_payload_data[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7233 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[4] dBus_cmd_payload_data[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7235 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[3] dBus_cmd_payload_data[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7237 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[2] dBus_cmd_payload_data[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7239 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[1] dBus_cmd_payload_data[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7241 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[0] dBus_cmd_payload_data[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7243 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[30] decode_to_execute_RS1[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7245 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[29] decode_to_execute_RS1[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7247 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[28] decode_to_execute_RS1[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7249 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[27] decode_to_execute_RS1[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7251 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[26] decode_to_execute_RS1[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7253 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[25] decode_to_execute_RS1[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7255 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[24] decode_to_execute_RS1[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7257 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[23] decode_to_execute_RS1[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7259 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[22] decode_to_execute_RS1[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7261 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[21] decode_to_execute_RS1[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7263 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[20] decode_to_execute_RS1[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7265 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[19] decode_to_execute_RS1[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7267 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[18] decode_to_execute_RS1[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7269 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[17] decode_to_execute_RS1[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7271 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[16] decode_to_execute_RS1[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7273 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[15] decode_to_execute_RS1[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7275 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[14] decode_to_execute_RS1[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7277 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[13] decode_to_execute_RS1[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7279 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[12] decode_to_execute_RS1[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7281 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[11] decode_to_execute_RS1[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7283 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[10] decode_to_execute_RS1[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7285 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[9] decode_to_execute_RS1[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7287 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[8] decode_to_execute_RS1[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7289 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[7] decode_to_execute_RS1[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7291 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[6] decode_to_execute_RS1[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7293 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[5] decode_to_execute_RS1[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7295 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[4] decode_to_execute_RS1[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7297 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[3] decode_to_execute_RS1[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7299 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[2] decode_to_execute_RS1[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7301 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[1] decode_to_execute_RS1[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7303 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[0] decode_to_execute_RS1[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7305 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_BRANCH_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7307 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1937 _zz_execute_SHIFT_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7309 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n1937 +11000 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_BITWISE_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7311 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7313 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7317 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7319 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7347 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7349 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[12] dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7351 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7353 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7355 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7357 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7359 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_INSTRUCTION[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7361 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7377 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7379 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7381 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7383 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7385 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7387 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7389 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] _zz__zz_execute_BranchPlugin_branch_src2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7391 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] _zz__zz_execute_BranchPlugin_branch_src2[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7393 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] _zz__zz_execute_BranchPlugin_branch_src2[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7395 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7397 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7399 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7401 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7403 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7405 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7407 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7409 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] switch_Misc_l241_1 $abc$8788$auto$rtlil.cc:2693:MuxGate$7411 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 dBus_cmd_payload_size[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7413 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7415 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7417 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7419 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$auto$rtlil.cc:2693:MuxGate$7421 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7423 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[30] IBusSimplePlugin_injector_decodeInput_payload_pc[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7505 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[29] IBusSimplePlugin_injector_decodeInput_payload_pc[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7507 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[28] IBusSimplePlugin_injector_decodeInput_payload_pc[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7509 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[27] IBusSimplePlugin_injector_decodeInput_payload_pc[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7511 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[26] IBusSimplePlugin_injector_decodeInput_payload_pc[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7513 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[25] IBusSimplePlugin_injector_decodeInput_payload_pc[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7515 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[24] IBusSimplePlugin_injector_decodeInput_payload_pc[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7517 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[23] IBusSimplePlugin_injector_decodeInput_payload_pc[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7519 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[22] IBusSimplePlugin_injector_decodeInput_payload_pc[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7521 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[21] IBusSimplePlugin_injector_decodeInput_payload_pc[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7523 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[20] IBusSimplePlugin_injector_decodeInput_payload_pc[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7525 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[19] IBusSimplePlugin_injector_decodeInput_payload_pc[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7527 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[18] IBusSimplePlugin_injector_decodeInput_payload_pc[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7529 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[17] IBusSimplePlugin_injector_decodeInput_payload_pc[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7531 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[16] IBusSimplePlugin_injector_decodeInput_payload_pc[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7533 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[15] IBusSimplePlugin_injector_decodeInput_payload_pc[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7535 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[14] IBusSimplePlugin_injector_decodeInput_payload_pc[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7537 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[13] IBusSimplePlugin_injector_decodeInput_payload_pc[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7539 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[12] IBusSimplePlugin_injector_decodeInput_payload_pc[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7541 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[11] IBusSimplePlugin_injector_decodeInput_payload_pc[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7543 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[10] IBusSimplePlugin_injector_decodeInput_payload_pc[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7545 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[9] IBusSimplePlugin_injector_decodeInput_payload_pc[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7547 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[8] IBusSimplePlugin_injector_decodeInput_payload_pc[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7549 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[7] IBusSimplePlugin_injector_decodeInput_payload_pc[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7551 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[6] IBusSimplePlugin_injector_decodeInput_payload_pc[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7553 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[5] IBusSimplePlugin_injector_decodeInput_payload_pc[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7555 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[4] IBusSimplePlugin_injector_decodeInput_payload_pc[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7557 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[3] IBusSimplePlugin_injector_decodeInput_payload_pc[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7559 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[2] IBusSimplePlugin_injector_decodeInput_payload_pc[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7561 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2004 BranchPlugin_jumpInterface_payload[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7563 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2059 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 $abc$8788$new_n2004 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2058 $abc$8788$new_n2057 $abc$8788$new_n2056 $abc$8788$new_n2006 $abc$8788$new_n2005 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2020 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2007 decode_to_execute_PC[25] decode_to_execute_RS1[25] $abc$8788$new_n2006 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2055 $abc$8788$new_n2054 $abc$8788$new_n2008 $abc$8788$new_n2007 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2053 $abc$8788$new_n2052 $abc$8788$new_n2051 $abc$8788$new_n2009 $abc$8788$new_n2008 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$8788$new_n2050 $abc$8788$new_n2048 $abc$8788$new_n2049 $abc$8788$new_n2047 $abc$8788$new_n2010 $abc$8788$new_n2009 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2046 $abc$8788$new_n2044 $abc$8788$new_n2045 $abc$8788$new_n2043 $abc$8788$new_n2011 $abc$8788$new_n2010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2042 $abc$8788$new_n2040 $abc$8788$new_n2041 $abc$8788$new_n2039 $abc$8788$new_n2012 $abc$8788$new_n2011 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2036 $abc$8788$new_n2013 $abc$8788$new_n2012 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2032 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2014 $abc$8788$new_n2013 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names $abc$8788$new_n2030 _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$new_n2029 $abc$8788$new_n2015 $abc$8788$new_n2014 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2016 $abc$8788$new_n2015 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2017 $abc$8788$new_n2016 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2017 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2018 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[2] decode_to_execute_PC[2] $abc$8788$new_n2019 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2020 +11 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[0] _zz__zz_execute_BranchPlugin_branch_src2[10] _zz__zz_execute_BranchPlugin_branch_src2[0] decode_to_execute_RS1[1] $abc$8788$new_n2021 +10011 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[3] decode_to_execute_PC[3] $abc$8788$new_n2023 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[5] decode_to_execute_PC[5] $abc$8788$new_n2024 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[4] decode_to_execute_PC[4] $abc$8788$new_n2025 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz__zz_execute_BranchPlugin_branch_src2_4[3] _zz__zz_execute_BranchPlugin_branch_src2[3] $abc$8788$new_n2026 +000 1 +001 1 +100 1 +110 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[7] decode_to_execute_PC[7] $abc$8788$new_n2027 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[6] decode_to_execute_PC[6] $abc$8788$new_n2028 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[9] decode_to_execute_PC[9] $abc$8788$new_n2029 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[8] decode_to_execute_PC[8] $abc$8788$new_n2030 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[11] decode_to_execute_PC[11] $abc$8788$new_n2031 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[10] decode_to_execute_PC[10] $abc$8788$new_n2032 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz__zz_execute_BranchPlugin_branch_src2_4[10] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[10] $abc$8788$new_n2033 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2034 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01110 1 +01111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[12] decode_to_execute_PC[12] $abc$8788$new_n2035 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2035 _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 dBus_cmd_payload_size[0] $abc$8788$new_n2036 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[13] decode_to_execute_PC[13] $abc$8788$new_n2037 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 switch_Misc_l241_1 $abc$8788$new_n2038 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[15] decode_to_execute_PC[15] $abc$8788$new_n2039 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[14] decode_to_execute_PC[14] $abc$8788$new_n2040 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[14] $abc$8788$new_n2041 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1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[19] decode_to_execute_PC[19] $abc$8788$new_n2047 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[18] decode_to_execute_PC[18] $abc$8788$new_n2048 +000 1 +010 1 +100 1 +101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[18] $abc$8788$new_n2049 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names _zz_execute_BRANCH_CTRL[1] _zz_execute_BRANCH_CTRL[0] _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[17] $abc$8788$new_n2050 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[22] decode_to_execute_PC[22] $abc$8788$new_n2051 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[21] decode_to_execute_PC[21] $abc$8788$new_n2052 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[20] decode_to_execute_PC[20] $abc$8788$new_n2053 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[24] decode_to_execute_PC[24] $abc$8788$new_n2054 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[23] decode_to_execute_PC[23] $abc$8788$new_n2055 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[28] decode_to_execute_PC[28] $abc$8788$new_n2056 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[27] decode_to_execute_PC[27] $abc$8788$new_n2057 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[26] decode_to_execute_PC[26] $abc$8788$new_n2058 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[30] decode_to_execute_PC[30] $abc$8788$new_n2059 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2020 decode_to_execute_RS1[29] decode_to_execute_PC[29] $abc$8788$new_n2060 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2005 BranchPlugin_jumpInterface_payload[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7565 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2056 $abc$8788$new_n2063 BranchPlugin_jumpInterface_payload[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7567 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2057 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2064 $abc$8788$new_n2063 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2058 _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2006 $abc$8788$new_n2064 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz_execute_BranchPlugin_branch_src2 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$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2038 $abc$8788$new_n2037 $abc$8788$new_n2087 BranchPlugin_jumpInterface_payload[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7597 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2034 $abc$8788$new_n2013 $abc$8788$new_n2036 $abc$8788$new_n2087 +000 1 +001 1 +010 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2036 $abc$8788$new_n2013 BranchPlugin_jumpInterface_payload[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7599 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2033 $abc$8788$new_n2031 $abc$8788$new_n2090 BranchPlugin_jumpInterface_payload[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7601 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2032 _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2014 $abc$8788$new_n2090 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[9] $abc$8788$new_n2032 $abc$8788$new_n2014 BranchPlugin_jumpInterface_payload[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7603 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[8] $abc$8788$new_n2029 $abc$8788$new_n2093 BranchPlugin_jumpInterface_payload[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7605 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2030 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2015 $abc$8788$new_n2093 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[7] $abc$8788$new_n2030 $abc$8788$new_n2015 BranchPlugin_jumpInterface_payload[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7607 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[6] $abc$8788$new_n2027 $abc$8788$new_n2096 BranchPlugin_jumpInterface_payload[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7609 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2028 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2016 $abc$8788$new_n2096 +001 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[5] $abc$8788$new_n2028 $abc$8788$new_n2016 BranchPlugin_jumpInterface_payload[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7611 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 _zz__zz_execute_BranchPlugin_branch_src2[4] $abc$8788$new_n2024 $abc$8788$new_n2099 BranchPlugin_jumpInterface_payload[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7613 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 $abc$8788$new_n2099 +011 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2026 $abc$8788$new_n2025 $abc$8788$new_n2017 BranchPlugin_jumpInterface_payload[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7615 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2102 BranchPlugin_jumpInterface_payload[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7617 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2023 $abc$8788$new_n2018 _zz__zz_execute_BranchPlugin_branch_src2[2] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2102 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2104 BranchPlugin_jumpInterface_payload[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7619 +010 1 +011 1 +101 1 +111 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n2021 $abc$8788$new_n2019 _zz__zz_execute_BranchPlugin_branch_src2[1] _zz__zz_execute_BranchPlugin_branch_src2_4[1] $abc$8788$new_n2104 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] iBus_rsp_payload_inst[30] decode_INSTRUCTION_ANTICIPATED[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] iBus_rsp_payload_inst[29] decode_INSTRUCTION_ANTICIPATED[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] iBus_rsp_payload_inst[28] decode_INSTRUCTION_ANTICIPATED[28] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] iBus_rsp_payload_inst[27] decode_INSTRUCTION_ANTICIPATED[27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] iBus_rsp_payload_inst[26] decode_INSTRUCTION_ANTICIPATED[26] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 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IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] iBus_rsp_payload_inst[13] decode_INSTRUCTION_ANTICIPATED[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] iBus_rsp_payload_inst[12] decode_INSTRUCTION_ANTICIPATED[12] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] iBus_rsp_payload_inst[11] decode_INSTRUCTION_ANTICIPATED[11] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] iBus_rsp_payload_inst[10] decode_INSTRUCTION_ANTICIPATED[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] iBus_rsp_payload_inst[9] decode_INSTRUCTION_ANTICIPATED[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 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IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] iBus_rsp_payload_inst[6] decode_INSTRUCTION_ANTICIPATED[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] iBus_rsp_payload_inst[5] decode_INSTRUCTION_ANTICIPATED[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] iBus_rsp_payload_inst[4] decode_INSTRUCTION_ANTICIPATED[4] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] iBus_rsp_payload_inst[3] decode_INSTRUCTION_ANTICIPATED[3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] iBus_rsp_payload_inst[2] decode_INSTRUCTION_ANTICIPATED[2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2126 _zz_execute_SrcPlugin_addSub_2[30] _zz_RegFilePlugin_regFile_port0[30] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1296 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2125 +001 1 +011 1 +110 1 +111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2126 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2128 _zz_execute_SrcPlugin_addSub_2[29] _zz_RegFilePlugin_regFile_port0[29] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2128 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2130 _zz_execute_SrcPlugin_addSub_2[28] _zz_RegFilePlugin_regFile_port0[28] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7669 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2130 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2132 _zz_execute_SrcPlugin_addSub_2[27] _zz_RegFilePlugin_regFile_port0[27] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7671 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2132 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2134 _zz_execute_SrcPlugin_addSub_2[26] _zz_RegFilePlugin_regFile_port0[26] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2134 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2136 _zz_execute_SrcPlugin_addSub_2[25] _zz_RegFilePlugin_regFile_port0[25] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7675 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2136 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2138 _zz_execute_SrcPlugin_addSub_2[24] _zz_RegFilePlugin_regFile_port0[24] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7677 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2138 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2140 _zz_execute_SrcPlugin_addSub_2[23] _zz_RegFilePlugin_regFile_port0[23] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2140 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2142 _zz_execute_SrcPlugin_addSub_2[22] _zz_RegFilePlugin_regFile_port0[22] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7681 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2142 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2144 _zz_execute_SrcPlugin_addSub_2[21] _zz_RegFilePlugin_regFile_port0[21] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7683 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2144 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2146 _zz_execute_SrcPlugin_addSub_2[20] _zz_RegFilePlugin_regFile_port0[20] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7685 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2146 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2148 _zz_execute_SrcPlugin_addSub_2[19] _zz_RegFilePlugin_regFile_port0[19] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2148 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2150 _zz_execute_SrcPlugin_addSub_2[18] _zz_RegFilePlugin_regFile_port0[18] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2150 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2152 _zz_execute_SrcPlugin_addSub_2[17] _zz_RegFilePlugin_regFile_port0[17] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2152 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2154 _zz_execute_SrcPlugin_addSub_2[16] _zz_RegFilePlugin_regFile_port0[16] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7693 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2154 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2156 _zz_execute_SrcPlugin_addSub_2[15] _zz_RegFilePlugin_regFile_port0[15] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2156 +1110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2158 _zz_execute_SrcPlugin_addSub_2[14] _zz_RegFilePlugin_regFile_port0[14] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7697 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2158 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2160 _zz_execute_SrcPlugin_addSub_2[13] _zz_RegFilePlugin_regFile_port0[13] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7699 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2160 +11110 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2162 _zz_execute_SrcPlugin_addSub_2[12] _zz_RegFilePlugin_regFile_port0[12] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7701 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2162 +11110 1 +.names $abc$8788$new_n2164 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7703 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2165 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2164 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz_RegFilePlugin_regFile_port0[2] $abc$8788$new_n2165 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2167 _zz_execute_SrcPlugin_addSub_2[3] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7707 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz_RegFilePlugin_regFile_port0[3] $abc$8788$new_n2167 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2168 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n2170 _zz_execute_SrcPlugin_addSub_2[1] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7711 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz_RegFilePlugin_regFile_port0[1] $abc$8788$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2172 _zz_execute_SrcPlugin_addSub_2[0] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7715 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz_RegFilePlugin_regFile_port0[0] $abc$8788$new_n2172 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[10] _zz_RegFilePlugin_regFile_port0[10] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7719 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[9] _zz_RegFilePlugin_regFile_port0[9] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7723 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[8] _zz_RegFilePlugin_regFile_port0[8] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7727 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[7] _zz_RegFilePlugin_regFile_port0[7] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7731 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[6] _zz_RegFilePlugin_regFile_port0[6] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7735 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[5] _zz_RegFilePlugin_regFile_port0[5] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7739 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[30] decode_to_execute_PC[30] $abc$8788$auto$rtlil.cc:2693:MuxGate$7803 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[29] decode_to_execute_PC[29] $abc$8788$auto$rtlil.cc:2693:MuxGate$7805 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[28] decode_to_execute_PC[28] $abc$8788$auto$rtlil.cc:2693:MuxGate$7807 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[27] decode_to_execute_PC[27] $abc$8788$auto$rtlil.cc:2693:MuxGate$7809 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[26] decode_to_execute_PC[26] $abc$8788$auto$rtlil.cc:2693:MuxGate$7811 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[25] decode_to_execute_PC[25] $abc$8788$auto$rtlil.cc:2693:MuxGate$7813 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[24] decode_to_execute_PC[24] $abc$8788$auto$rtlil.cc:2693:MuxGate$7815 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[23] decode_to_execute_PC[23] $abc$8788$auto$rtlil.cc:2693:MuxGate$7817 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[22] decode_to_execute_PC[22] $abc$8788$auto$rtlil.cc:2693:MuxGate$7819 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[21] decode_to_execute_PC[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7821 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[20] decode_to_execute_PC[20] $abc$8788$auto$rtlil.cc:2693:MuxGate$7823 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[19] decode_to_execute_PC[19] $abc$8788$auto$rtlil.cc:2693:MuxGate$7825 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[18] decode_to_execute_PC[18] $abc$8788$auto$rtlil.cc:2693:MuxGate$7827 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[17] decode_to_execute_PC[17] $abc$8788$auto$rtlil.cc:2693:MuxGate$7829 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[16] decode_to_execute_PC[16] $abc$8788$auto$rtlil.cc:2693:MuxGate$7831 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[15] decode_to_execute_PC[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7833 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[14] decode_to_execute_PC[14] $abc$8788$auto$rtlil.cc:2693:MuxGate$7835 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[13] decode_to_execute_PC[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7837 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[12] decode_to_execute_PC[12] $abc$8788$auto$rtlil.cc:2693:MuxGate$7839 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[11] decode_to_execute_PC[11] $abc$8788$auto$rtlil.cc:2693:MuxGate$7841 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[10] decode_to_execute_PC[10] $abc$8788$auto$rtlil.cc:2693:MuxGate$7843 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[9] decode_to_execute_PC[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7845 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[8] decode_to_execute_PC[8] $abc$8788$auto$rtlil.cc:2693:MuxGate$7847 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[7] decode_to_execute_PC[7] $abc$8788$auto$rtlil.cc:2693:MuxGate$7849 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[6] decode_to_execute_PC[6] $abc$8788$auto$rtlil.cc:2693:MuxGate$7851 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[5] decode_to_execute_PC[5] $abc$8788$auto$rtlil.cc:2693:MuxGate$7853 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[4] decode_to_execute_PC[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7855 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[3] decode_to_execute_PC[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7857 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[2] decode_to_execute_PC[2] $abc$8788$auto$rtlil.cc:2693:MuxGate$7859 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_834 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2209 $abc$8788$auto$rtlil.cc:2693:MuxGate$7887 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2210 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2209 +11000 1 +.names $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2210 +1000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] $abc$8788$new_n2211 +1100 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_772 $abc$8788$new_n2214 $abc$8788$new_n2213 $abc$8788$auto$rtlil.cc:2693:MuxGate$7889 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] $abc$8788$new_n2211 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2213 +11000 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2214 +0000 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2216 execute_CsrPlugin_csr_836 $abc$8788$auto$rtlil.cc:2693:MuxGate$7891 +001 1 +011 1 +110 1 +111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] $abc$8788$new_n2213 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] $abc$8788$new_n2216 +11000 1 +.names $abc$8788$new_n2458 execute_CsrPlugin_csr_768 $abc$8788$new_n2210 $abc$8788$new_n2214 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$auto$rtlil.cc:2693:MuxGate$7893 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$8788$new_n2245 _zz_execute_BRANCH_CTRL[0] $abc$8788$new_n2246 $abc$8788$new_n2219 $abc$8788$new_n2242 $abc$8788$auto$rtlil.cc:2693:MuxGate$7897 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2220 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n1802 $abc$8788$new_n1797 dBus_cmd_payload_address[31] $abc$8788$new_n2219 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[13] switch_Misc_l241_1 $abc$8788$new_n2221 $abc$8788$new_n2220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2236 $abc$8788$new_n2222 _zz_execute_SrcPlugin_addSub_2[11] decode_to_execute_SRC2[11] $abc$8788$new_n2221 +1100 1 +1111 1 +.names $abc$8788$new_n2233 $abc$8788$new_n2223 $abc$8788$new_n2235 _zz_execute_SrcPlugin_addSub_2[27] decode_to_execute_SRC2[27] $abc$8788$new_n2222 +11100 1 +11111 1 +.names $abc$8788$new_n2229 $abc$8788$new_n2224 $abc$8788$new_n2231 _zz_execute_SrcPlugin_addSub_2[8] decode_to_execute_SRC2[8] $abc$8788$new_n2223 +11100 1 +11111 1 +.names $abc$8788$new_n2228 $abc$8788$new_n2225 _zz_execute_SrcPlugin_addSub_2[16] decode_to_execute_SRC2[16] $abc$8788$new_n2227 $abc$8788$new_n2224 +11000 1 +11110 1 +.names $abc$8788$new_n2226 $abc$8788$new_n1797 _zz_execute_SrcPlugin_addSub_2[15] decode_to_execute_SRC2[15] $abc$8788$new_n2225 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[0] decode_to_execute_SRC2[0] _zz_execute_SrcPlugin_addSub_2[30] decode_to_execute_SRC2[30] $abc$8788$new_n2226 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[5] decode_to_execute_SRC2[5] $abc$8788$new_n2227 +01 1 +10 1 +.names _zz_execute_SrcPlugin_addSub_2[4] decode_to_execute_SRC2[4] _zz_execute_SrcPlugin_addSub_2[21] decode_to_execute_SRC2[21] $abc$8788$new_n2228 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2230 _zz_execute_SrcPlugin_addSub_2[12] decode_to_execute_SRC2[12] _zz_execute_SrcPlugin_addSub_2[19] decode_to_execute_SRC2[19] $abc$8788$new_n2229 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[10] decode_to_execute_SRC2[10] _zz_execute_SrcPlugin_addSub_2[13] decode_to_execute_SRC2[13] $abc$8788$new_n2230 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[7] decode_to_execute_SRC2[7] _zz_execute_SrcPlugin_addSub_2[14] decode_to_execute_SRC2[14] $abc$8788$new_n2232 $abc$8788$new_n2231 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[28] decode_to_execute_SRC2[28] $abc$8788$new_n2232 +01 1 +10 1 +.names $abc$8788$new_n2234 _zz_execute_SrcPlugin_addSub_2[1] decode_to_execute_SRC2[1] _zz_execute_SrcPlugin_addSub_2[3] decode_to_execute_SRC2[3] $abc$8788$new_n2233 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[17] decode_to_execute_SRC2[17] _zz_execute_SrcPlugin_addSub_2[24] decode_to_execute_SRC2[24] $abc$8788$new_n2234 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[6] decode_to_execute_SRC2[6] _zz_execute_SrcPlugin_addSub_2[29] decode_to_execute_SRC2[29] $abc$8788$new_n2235 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$8788$new_n2239 $abc$8788$new_n2237 _zz_execute_SrcPlugin_addSub_2[18] decode_to_execute_SRC2[18] $abc$8788$new_n2236 +1100 1 +1111 1 +.names $abc$8788$new_n2238 _zz_execute_SrcPlugin_addSub_2[9] decode_to_execute_SRC2[9] _zz_execute_SrcPlugin_addSub_2[20] decode_to_execute_SRC2[20] $abc$8788$new_n2237 +10000 1 +10011 1 +11100 1 +11111 1 +.names _zz_execute_SrcPlugin_addSub_2[25] decode_to_execute_SRC2[25] _zz_execute_SrcPlugin_addSub_2[26] decode_to_execute_SRC2[26] $abc$8788$new_n2238 +0000 1 +0011 1 +1100 1 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[2] decode_to_execute_SRC2[2] _zz_execute_SrcPlugin_addSub_2[23] decode_to_execute_SRC2[23] $abc$8788$new_n2240 $abc$8788$new_n2239 +00000 1 +00110 1 +11000 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[22] decode_to_execute_SRC2[22] $abc$8788$new_n2240 +01 1 +10 1 +.names $abc$8788$new_n2243 $abc$8788$new_n1802 $abc$8788$new_n2244 dBus_cmd_payload_address[31] $abc$8788$new_n1797 $abc$8788$new_n2242 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[13] dBus_cmd_payload_size[0] $abc$8788$new_n2221 switch_Misc_l241_1 $abc$8788$new_n2243 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[13] $abc$8788$new_n2244 +000 1 +.names $abc$8788$new_n1321 execute_to_memory_BRANCH_DO $abc$8788$new_n2245 +10 1 +.names _zz_execute_BRANCH_CTRL[1] $abc$8788$new_n1321 $abc$8788$new_n2246 +00 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2248 execute_to_memory_REGFILE_WRITE_DATA[31] $abc$8788$new_n1323 $abc$8788$new_n2250 $abc$8788$auto$rtlil.cc:2693:MuxGate$7899 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1786 $abc$8788$new_n1595 $abc$8788$new_n1588 dBus_cmd_payload_address[31] $abc$8788$new_n2249 $abc$8788$new_n2248 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names _zz_execute_SrcPlugin_addSub_2[31] decode_to_execute_SRC2[31] _zz_execute_ALU_BITWISE_CTRL[1] _zz_execute_ALU_BITWISE_CTRL[0] $abc$8788$new_n2249 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +.names $abc$8788$new_n2251 execute_LightShifterPlugin_isActive $abc$8788$new_n1592 execute_to_memory_REGFILE_WRITE_DATA[30] _zz_execute_SrcPlugin_addSub_2[30] $abc$8788$new_n2250 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names _zz_execute_SHIFT_CTRL[0] _zz_execute_SHIFT_CTRL[1] execute_LightShifterPlugin_isActive execute_to_memory_REGFILE_WRITE_DATA[31] _zz_execute_SrcPlugin_addSub_2[31] $abc$8788$new_n2251 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 dBus_cmd_payload_address[1] execute_to_memory_MEMORY_ADDRESS_LOW[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7901 +010 1 +011 1 +101 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2254 decode_to_execute_SRC2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7903 +001 1 +011 1 +100 1 +101 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n1807 _zz_RegFilePlugin_regFile_port1[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] _zz_decode_SRC2 $abc$8788$new_n2254 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names $abc$8788$new_n2256 decode_to_execute_SRC2_FORCE_ZERO $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7905 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2257 $abc$8788$new_n1937 _zz_decode_SRC_LESS_UNSIGNED_4 _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2256 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2258 $abc$8788$new_n2257 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2258 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port1[31] decode_to_execute_RS2[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7907 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_RegFilePlugin_regFile_port0[31] decode_to_execute_RS1[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7909 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2262 _zz_execute_BRANCH_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7911 +001 1 +011 1 +100 1 +101 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$new_n2262 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8788$new_n2458 _zz_execute_SHIFT_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n1937 $abc$8788$auto$rtlil.cc:2693:MuxGate$7913 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_13 _zz_execute_ALU_BITWISE_CTRL[1] $abc$8788$auto$rtlil.cc:2693:MuxGate$7915 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1316 decode_to_execute_SRC_LESS_UNSIGNED IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] $abc$8788$auto$rtlil.cc:2693:MuxGate$7917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 _zz_execute_ALU_CTRL[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] $abc$8788$new_n2267 $abc$8788$auto$rtlil.cc:2693:MuxGate$7919 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$new_n2267 +000 1 +010 1 +011 1 +.names $abc$8788$new_n1321 _zz_memory_ENV_CTRL _zz_execute_ENV_CTRL $abc$8788$auto$rtlil.cc:2693:MuxGate$7921 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_ENV_CTRL $abc$8788$new_n1296 _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$auto$rtlil.cc:2693:MuxGate$7923 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1296 decode_to_execute_IS_CSR IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] _zz__zz_decode_SRC_LESS_UNSIGNED_13 $abc$8788$auto$rtlil.cc:2693:MuxGate$7925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names dBus_cmd_payload_wr $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7927 +10 1 +.names $abc$8788$new_n2458 _zz__zz_decode_SRC_LESS_UNSIGNED_47 dBus_cmd_payload_wr $abc$8788$auto$rtlil.cc:2693:MuxGate$7929 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1321 execute_to_memory_REGFILE_WRITE_VALID decode_to_execute_REGFILE_WRITE_VALID $abc$8788$auto$rtlil.cc:2693:MuxGate$7931 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2275 decode_to_execute_REGFILE_WRITE_VALID $abc$8788$new_n2277 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] $abc$8788$auto$rtlil.cc:2693:MuxGate$7935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8788$new_n2276 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2275 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] $abc$8788$new_n2276 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] $abc$8788$new_n2277 +0000 1 +.names decode_to_execute_MEMORY_ENABLE $abc$8788$new_n1321 $abc$8788$auto$rtlil.cc:2693:MuxGate$7937 +01 1 +10 1 +11 1 +.names $abc$8788$new_n2458 decode_to_execute_MEMORY_ENABLE IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] $abc$8788$auto$rtlil.cc:2693:MuxGate$7939 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +.names $abc$8788$new_n2257 $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_4 $abc$8788$auto$rtlil.cc:2693:MuxGate$7941 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2458 decode_to_execute_CSR_WRITE_OPCODE $abc$8788$new_n2282 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] $abc$8788$auto$rtlil.cc:2693:MuxGate$7943 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2282 +10000 1 +.names $abc$8788$new_n2458 _zz_decode_SRC2 _zz_execute_BranchPlugin_branch_src2 $abc$8788$auto$rtlil.cc:2693:MuxGate$7947 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy _zz_decode_SRC2 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] iBus_rsp_payload_inst[31] decode_INSTRUCTION_ANTICIPATED[31] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 $abc$8788$new_n2287 $abc$8788$new_n2286 BranchPlugin_jumpInterface_payload[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7965 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2060 $abc$8788$new_n2059 $abc$8788$new_n2005 $abc$8788$new_n2286 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names _zz_execute_BranchPlugin_branch_src2 $abc$8788$new_n2020 decode_to_execute_PC[31] decode_to_execute_RS1[31] $abc$8788$new_n2287 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_fetchPc_pcReg[31] IBusSimplePlugin_injector_decodeInput_payload_pc[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7971 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 IBusSimplePlugin_injector_decodeInput_payload_pc[31] decode_to_execute_PC[31] $abc$8788$auto$rtlil.cc:2693:MuxGate$7973 +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n2458 _zz_execute_SrcPlugin_addSub_2[11] _zz_RegFilePlugin_regFile_port0[11] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7979 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$8788$new_n2292 _zz_execute_SrcPlugin_addSub_2[4] $abc$8788$new_n2458 $abc$8788$auto$rtlil.cc:2693:MuxGate$7983 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$8788$new_n2168 $abc$8788$new_n2125 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz_RegFilePlugin_regFile_port0[4] $abc$8788$new_n2292 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n2294 _zz_execute_SrcPlugin_addSub_2[31] _zz_RegFilePlugin_regFile_port0[31] $abc$8788$new_n2125 $abc$8788$auto$rtlil.cc:2693:MuxGate$7985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names _zz_decode_SRC2 _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] $abc$8788$new_n2294 +1110 1 +.names decode_to_execute_MEMORY_ENABLE execute_arbitration_isValid $abc$8788$new_n1270 $abc$8788$new_n1321 dBus_cmd_valid +1110 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[8] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[9] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[10] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[11] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[12] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[13] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[14] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dBus_cmd_payload_size[0] switch_Misc_l241_1 decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[15] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[16] dBus_cmd_payload_data[0] dBus_cmd_payload_data[16] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[17] dBus_cmd_payload_data[1] dBus_cmd_payload_data[17] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[18] dBus_cmd_payload_data[2] dBus_cmd_payload_data[18] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[19] dBus_cmd_payload_data[3] dBus_cmd_payload_data[19] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[20] dBus_cmd_payload_data[4] dBus_cmd_payload_data[20] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[21] dBus_cmd_payload_data[5] dBus_cmd_payload_data[21] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[22] dBus_cmd_payload_data[6] dBus_cmd_payload_data[22] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 decode_to_execute_RS2[23] dBus_cmd_payload_data[7] dBus_cmd_payload_data[23] +001 1 +011 1 +110 1 +111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[24] decode_to_execute_RS2[8] dBus_cmd_payload_data[0] dBus_cmd_payload_data[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[25] decode_to_execute_RS2[9] dBus_cmd_payload_data[1] dBus_cmd_payload_data[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[26] decode_to_execute_RS2[10] dBus_cmd_payload_data[2] dBus_cmd_payload_data[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[27] decode_to_execute_RS2[11] dBus_cmd_payload_data[3] dBus_cmd_payload_data[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[28] decode_to_execute_RS2[12] dBus_cmd_payload_data[4] dBus_cmd_payload_data[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[29] decode_to_execute_RS2[13] dBus_cmd_payload_data[5] dBus_cmd_payload_data[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[30] decode_to_execute_RS2[14] dBus_cmd_payload_data[6] dBus_cmd_payload_data[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[0] decode_to_execute_RS2[31] decode_to_execute_RS2[15] dBus_cmd_payload_data[7] dBus_cmd_payload_data[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2321 $abc$8788$new_n1492 softwareInterrupt $0\CsrPlugin_mip_MSIP[0:0] +001 1 +011 1 +110 1 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_836 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2321 +1111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] iBus_rsp_payload_inst[15] decode_INSTRUCTION_ANTICIPATED[15] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] iBus_rsp_payload_inst[16] decode_INSTRUCTION_ANTICIPATED[16] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] iBus_rsp_payload_inst[17] decode_INSTRUCTION_ANTICIPATED[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] iBus_rsp_payload_inst[18] decode_INSTRUCTION_ANTICIPATED[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] iBus_rsp_payload_inst[19] decode_INSTRUCTION_ANTICIPATED[19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] iBus_rsp_payload_inst[20] decode_INSTRUCTION_ANTICIPATED[20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] iBus_rsp_payload_inst[21] decode_INSTRUCTION_ANTICIPATED[21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] iBus_rsp_payload_inst[22] decode_INSTRUCTION_ANTICIPATED[22] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] iBus_rsp_payload_inst[23] decode_INSTRUCTION_ANTICIPATED[23] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n2461 IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] iBus_rsp_payload_inst[24] decode_INSTRUCTION_ANTICIPATED[24] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$8788$new_n1516 $abc$8788$new_n1272 $0\CsrPlugin_interrupt_valid[0:0] +10 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2334 $abc$8788$new_n2335 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] +000 1 +001 1 +100 1 +110 1 +.names IBusSimplePlugin_pending_value[0] $abc$8788$new_n1454 iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2334 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2335 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01000 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1270 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2339 $abc$8788$new_n2338 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1454 IBusSimplePlugin_pending_value[0] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2337 +0001 1 +0010 1 +0011 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] iBus_rsp_valid IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy $abc$8788$new_n2338 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy iBus_rsp_valid $abc$8788$new_n2339 +10001 1 +10010 1 +10011 1 +.names $abc$8788$new_n1270 $abc$8788$new_n2341 IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] $abc$8788$new_n2339 $0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 IBusSimplePlugin_pending_value[1] $abc$8788$new_n2341 +010 1 +100 1 +101 1 +111 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[0] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][0] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2345 $abc$8788$new_n1500 $abc$8788$new_n2344 $abc$8788$new_n2343 +111 1 +.names decode_to_execute_CSR_WRITE_OPCODE execute_CsrPlugin_csr_768 $abc$8788$new_n1322 $abc$8788$new_n2458 $abc$8788$new_n2344 +1111 1 +.names _zz_execute_SrcPlugin_addSub_2[12] switch_Misc_l241_1 dBus_cmd_payload_size[0] CsrPlugin_mstatus_MPP[1] execute_CsrPlugin_csr_768 $abc$8788$new_n2345 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8788$new_n2343 $abc$8788$new_n1274 CsrPlugin_mstatus_MPP[1] $abc$8788$new_n1272 $0\CsrPlugin_mstatus_MPP[1:0][1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1496 $abc$8788$new_n2348 $0\CsrPlugin_mstatus_MPIE[0:0] +000 1 +010 1 +110 1 +111 1 +.names $abc$8788$new_n1272 $abc$8788$new_n1274 CsrPlugin_mstatus_MIE CsrPlugin_mstatus_MPIE $abc$8788$new_n2348 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$8788$new_n2344 $abc$8788$new_n1492 $abc$8788$new_n2350 $0\CsrPlugin_mstatus_MIE[0:0] +001 1 +011 1 +110 1 +111 1 +.names $abc$8788$new_n1274 CsrPlugin_mstatus_MPIE CsrPlugin_mstatus_MIE $abc$8788$new_n1272 $abc$8788$new_n2350 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names memory_arbitration_isValid $abc$8788$new_n1271 $abc$8788$new_n1321 $0\writeBack_arbitration_isValid[0:0] +110 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2353 memory_to_writeBack_REGFILE_WRITE_DATA[0] lastStageRegFileWrite_payload_data[0] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2354 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[16] $abc$8788$new_n2353 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[8] memory_to_writeBack_MEMORY_READ_DATA[0] $abc$8788$new_n2354 +000 1 +010 1 +100 1 +101 1 +.names memory_to_writeBack_MEMORY_ENABLE lastStageIsFiring $abc$8788$new_n2355 +11 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2357 memory_to_writeBack_REGFILE_WRITE_DATA[1] lastStageRegFileWrite_payload_data[1] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2358 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[17] $abc$8788$new_n2357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[9] memory_to_writeBack_MEMORY_READ_DATA[1] $abc$8788$new_n2358 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2360 memory_to_writeBack_REGFILE_WRITE_DATA[2] lastStageRegFileWrite_payload_data[2] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2361 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[18] $abc$8788$new_n2360 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[10] memory_to_writeBack_MEMORY_READ_DATA[2] $abc$8788$new_n2361 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2363 memory_to_writeBack_REGFILE_WRITE_DATA[3] lastStageRegFileWrite_payload_data[3] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2364 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[19] $abc$8788$new_n2363 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[11] memory_to_writeBack_MEMORY_READ_DATA[3] $abc$8788$new_n2364 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2366 memory_to_writeBack_REGFILE_WRITE_DATA[4] lastStageRegFileWrite_payload_data[4] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2367 writeBack_MEMORY_READ_DATA[28] writeBack_MEMORY_READ_DATA[20] $abc$8788$new_n2366 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[12] memory_to_writeBack_MEMORY_READ_DATA[4] $abc$8788$new_n2367 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2369 memory_to_writeBack_REGFILE_WRITE_DATA[5] lastStageRegFileWrite_payload_data[5] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2370 writeBack_MEMORY_READ_DATA[29] writeBack_MEMORY_READ_DATA[21] $abc$8788$new_n2369 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[13] memory_to_writeBack_MEMORY_READ_DATA[5] $abc$8788$new_n2370 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2372 memory_to_writeBack_REGFILE_WRITE_DATA[6] lastStageRegFileWrite_payload_data[6] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2373 writeBack_MEMORY_READ_DATA[30] writeBack_MEMORY_READ_DATA[22] $abc$8788$new_n2372 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[14] memory_to_writeBack_MEMORY_READ_DATA[6] $abc$8788$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2355 _zz_5 $abc$8788$new_n2375 memory_to_writeBack_REGFILE_WRITE_DATA[7] lastStageRegFileWrite_payload_data[7] +0001 1 +0011 1 +1000 1 +1001 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2376 writeBack_MEMORY_READ_DATA[31] writeBack_MEMORY_READ_DATA[23] $abc$8788$new_n2375 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[0] memory_to_writeBack_MEMORY_READ_DATA[15] memory_to_writeBack_MEMORY_READ_DATA[7] $abc$8788$new_n2376 +000 1 +010 1 +100 1 +101 1 +.names _zz_5 $abc$8788$new_n2379 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[8] lastStageRegFileWrite_payload_data[8] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2355 _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2375 _zz_lastStageRegFileWrite_payload_address[14] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2378 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[24] memory_to_writeBack_MEMORY_READ_DATA[8] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2379 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names memory_to_writeBack_MEMORY_ADDRESS_LOW[1] memory_to_writeBack_MEMORY_ADDRESS_LOW[0] $abc$8788$new_n2380 +10 1 +.names _zz_5 $abc$8788$new_n2382 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[9] lastStageRegFileWrite_payload_data[9] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[25] memory_to_writeBack_MEMORY_READ_DATA[9] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2382 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2384 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[10] lastStageRegFileWrite_payload_data[10] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[26] memory_to_writeBack_MEMORY_READ_DATA[10] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2384 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2386 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[11] lastStageRegFileWrite_payload_data[11] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[27] memory_to_writeBack_MEMORY_READ_DATA[11] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2386 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2388 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[12] lastStageRegFileWrite_payload_data[12] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[28] memory_to_writeBack_MEMORY_READ_DATA[12] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2388 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2390 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[13] lastStageRegFileWrite_payload_data[13] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[29] memory_to_writeBack_MEMORY_READ_DATA[13] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2390 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2392 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[14] lastStageRegFileWrite_payload_data[14] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[30] memory_to_writeBack_MEMORY_READ_DATA[14] _zz_lastStageRegFileWrite_payload_address[13] _zz_lastStageRegFileWrite_payload_address[12] $abc$8788$new_n2392 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names _zz_5 $abc$8788$new_n2394 $abc$8788$new_n2378 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[15] lastStageRegFileWrite_payload_data[15] +00001 1 +00010 1 +00011 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2394 +001 1 +010 1 +011 1 +.names $abc$8788$new_n2380 writeBack_MEMORY_READ_DATA[31] memory_to_writeBack_MEMORY_READ_DATA[15] $abc$8788$new_n2395 +000 1 +010 1 +100 1 +101 1 +.names $abc$8788$new_n2397 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[16] lastStageRegFileWrite_payload_data[16] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[16] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2397 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2378 _zz_lastStageRegFileWrite_payload_address[12] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2395 _zz_lastStageRegFileWrite_payload_address[14] $abc$8788$new_n2398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2400 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[17] lastStageRegFileWrite_payload_data[17] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[17] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2400 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2402 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[18] lastStageRegFileWrite_payload_data[18] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[18] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2402 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2404 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[19] lastStageRegFileWrite_payload_data[19] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 memory_to_writeBack_MEMORY_READ_DATA[19] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2404 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2406 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[20] lastStageRegFileWrite_payload_data[20] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[20] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2406 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2408 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[21] lastStageRegFileWrite_payload_data[21] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[21] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2408 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2410 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[22] lastStageRegFileWrite_payload_data[22] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[22] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2410 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2412 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[23] lastStageRegFileWrite_payload_data[23] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[23] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2412 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2414 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[24] lastStageRegFileWrite_payload_data[24] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[24] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2414 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2416 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[25] lastStageRegFileWrite_payload_data[25] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[25] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2416 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2418 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[26] lastStageRegFileWrite_payload_data[26] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[26] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2418 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2420 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[27] lastStageRegFileWrite_payload_data[27] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[27] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2420 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2422 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[28] lastStageRegFileWrite_payload_data[28] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[28] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2422 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2424 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[29] lastStageRegFileWrite_payload_data[29] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[29] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2424 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2426 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[30] lastStageRegFileWrite_payload_data[30] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[30] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2426 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$8788$new_n2428 $abc$8788$new_n2355 memory_to_writeBack_REGFILE_WRITE_DATA[31] lastStageRegFileWrite_payload_data[31] +101 1 +110 1 +111 1 +.names _zz_5 $abc$8788$new_n2398 writeBack_MEMORY_READ_DATA[31] _zz_lastStageRegFileWrite_payload_address[13] $abc$8788$new_n2428 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_5 lastStageRegFileWrite_payload_address[0] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_5 lastStageRegFileWrite_payload_address[1] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_5 lastStageRegFileWrite_payload_address[2] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_5 lastStageRegFileWrite_payload_address[3] +10 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_5 lastStageRegFileWrite_payload_address[4] +10 1 +.names _zz_5 HazardSimplePlugin_writeBackWrites_valid _zz_1 +01 1 +10 1 +11 1 +.names IBusSimplePlugin_pending_value[1] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[1] +001 1 +010 1 +100 1 +111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 $abc$8788$new_n2436 +10 1 +.names IBusSimplePlugin_pending_value[1] IBusSimplePlugin_pending_value[2] $abc$8788$new_n2337 $abc$8788$new_n2436 IBusSimplePlugin_pending_next[2] +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$8788$new_n1505 $abc$8788$new_n2334 IBusSimplePlugin_pending_next[0] +00 1 +11 1 +.names $abc$8788$new_n1283 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] execute_to_memory_INSTRUCTION[8] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] execute_to_memory_INSTRUCTION[9] $abc$8788$new_n2439 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2439 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] execute_to_memory_INSTRUCTION[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] execute_to_memory_INSTRUCTION[11] $abc$8788$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] $abc$8788$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2442 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] $abc$8788$new_n2443 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n1304 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] execute_to_memory_INSTRUCTION[7] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] execute_to_memory_INSTRUCTION[8] $abc$8788$new_n2445 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2445 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] execute_to_memory_INSTRUCTION[9] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] execute_to_memory_INSTRUCTION[10] $abc$8788$new_n2446 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +.names execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] _zz__zz_execute_BranchPlugin_branch_src2_4[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] _zz__zz_execute_BranchPlugin_branch_src2_4[2] $abc$8788$new_n2448 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_REGFILE_WRITE_VALID IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] _zz__zz_execute_BranchPlugin_branch_src2_4[10] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] _zz__zz_execute_BranchPlugin_branch_src2_4[0] $abc$8788$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2448 $abc$8788$new_n2449 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2450 +1100 1 +1111 1 +.names HazardSimplePlugin_writeBackBuffer_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackBuffer_payload_address[0] HazardSimplePlugin_writeBackBuffer_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2451 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2451 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackBuffer_payload_address[2] HazardSimplePlugin_writeBackBuffer_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2452 +10000 1 +10011 1 +11100 1 +11111 1 +.names HazardSimplePlugin_writeBackWrites_valid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] HazardSimplePlugin_writeBackWrites_payload_address[0] HazardSimplePlugin_writeBackWrites_payload_address[1] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] $abc$8788$new_n2454 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$8788$new_n2454 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] HazardSimplePlugin_writeBackWrites_payload_address[2] HazardSimplePlugin_writeBackWrites_payload_address[3] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] $abc$8788$new_n2455 +10000 1 +10011 1 +11100 1 +11111 1 +.names decode_to_execute_IS_CSR memory_arbitration_isValid lastStageIsFiring decode_to_execute_MEMORY_ENABLE dBus_cmd_ready $abc$8788$new_n2457 +00010 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n1321 execute_arbitration_isValid $abc$8788$new_n2457 $abc$8788$new_n1323 $abc$8788$new_n1325 $abc$8788$new_n2458 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] $abc$8788$new_n2452 HazardSimplePlugin_writeBackBuffer_payload_address[4] $abc$8788$new_n2455 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2459 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$8788$new_n1278 $abc$8788$new_n1315 $abc$8788$new_n2446 $abc$8788$new_n2459 $abc$8788$new_n2450 $abc$8788$new_n2460 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8788$new_n2458 $abc$8788$new_n1328 IBusSimplePlugin_injector_decodeInput_valid $abc$8788$new_n2460 $abc$8788$new_n2461 +1100 1 +1101 1 +1110 1 +.names $abc$8788$new_n1285 decode_to_execute_REGFILE_WRITE_VALID execute_arbitration_isValid IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] _zz__zz_execute_BranchPlugin_branch_src2_4[10] $abc$8788$new_n2462 +11100 1 +11111 1 +.names IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] $abc$8788$new_n2443 HazardSimplePlugin_writeBackWrites_payload_address[4] $abc$8788$new_n2462 _zz__zz_execute_BranchPlugin_branch_src2_4[3] $abc$8788$new_n2463 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 _zz_decode_SRC_LESS_UNSIGNED_4 $abc$8788$new_n2463 $abc$8788$new_n1288 $abc$8788$new_n2440 $abc$8788$new_n2464 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7861 Q=CsrPlugin_mcause_exceptionCode[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7969 Q=CsrPlugin_mcause_exceptionCode[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7957 Q=CsrPlugin_interrupt_code[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[15] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[15] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[16] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[16] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[17] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[17] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[18] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[18] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[19] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[19] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[20] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[20] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[21] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[21] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[22] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[22] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[23] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[23] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[24] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7859 Q=decode_to_execute_PC[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7857 Q=decode_to_execute_PC[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7855 Q=decode_to_execute_PC[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7853 Q=decode_to_execute_PC[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7851 Q=decode_to_execute_PC[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7849 Q=decode_to_execute_PC[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7847 Q=decode_to_execute_PC[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7845 Q=decode_to_execute_PC[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7843 Q=decode_to_execute_PC[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7841 Q=decode_to_execute_PC[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7839 Q=decode_to_execute_PC[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7837 Q=decode_to_execute_PC[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7835 Q=decode_to_execute_PC[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7833 Q=decode_to_execute_PC[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7831 Q=decode_to_execute_PC[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7829 Q=decode_to_execute_PC[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7827 Q=decode_to_execute_PC[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7825 Q=decode_to_execute_PC[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7823 Q=decode_to_execute_PC[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7821 Q=decode_to_execute_PC[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7819 Q=decode_to_execute_PC[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7817 Q=decode_to_execute_PC[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7815 Q=decode_to_execute_PC[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7813 Q=decode_to_execute_PC[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7811 Q=decode_to_execute_PC[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7809 Q=decode_to_execute_PC[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7807 Q=decode_to_execute_PC[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7805 Q=decode_to_execute_PC[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7803 Q=decode_to_execute_PC[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7973 Q=decode_to_execute_PC[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7797 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7795 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7793 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7791 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7789 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7787 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7785 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7783 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7781 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7779 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7777 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7775 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7773 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7771 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7769 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7767 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7765 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7763 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7761 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7759 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7757 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7755 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7753 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7751 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7749 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7747 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7745 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7743 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7741 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7963 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_push_rData_inst[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7953 Q=CsrPlugin_interrupt_code[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7739 Q=_zz_execute_SrcPlugin_addSub_2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7735 Q=_zz_execute_SrcPlugin_addSub_2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7731 Q=_zz_execute_SrcPlugin_addSub_2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7727 Q=_zz_execute_SrcPlugin_addSub_2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7723 Q=_zz_execute_SrcPlugin_addSub_2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7719 Q=_zz_execute_SrcPlugin_addSub_2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7979 Q=_zz_execute_SrcPlugin_addSub_2[11] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7863 Q=execute_LightShifterPlugin_isActive R=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7715 Q=_zz_execute_SrcPlugin_addSub_2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7711 Q=_zz_execute_SrcPlugin_addSub_2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7707 Q=_zz_execute_SrcPlugin_addSub_2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7983 Q=_zz_execute_SrcPlugin_addSub_2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7703 Q=_zz_execute_SrcPlugin_addSub_2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7701 Q=_zz_execute_SrcPlugin_addSub_2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7699 Q=_zz_execute_SrcPlugin_addSub_2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7697 Q=_zz_execute_SrcPlugin_addSub_2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7695 Q=_zz_execute_SrcPlugin_addSub_2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7693 Q=_zz_execute_SrcPlugin_addSub_2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7691 Q=_zz_execute_SrcPlugin_addSub_2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7689 Q=_zz_execute_SrcPlugin_addSub_2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7687 Q=_zz_execute_SrcPlugin_addSub_2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7685 Q=_zz_execute_SrcPlugin_addSub_2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7683 Q=_zz_execute_SrcPlugin_addSub_2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7681 Q=_zz_execute_SrcPlugin_addSub_2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7679 Q=_zz_execute_SrcPlugin_addSub_2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7677 Q=_zz_execute_SrcPlugin_addSub_2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7675 Q=_zz_execute_SrcPlugin_addSub_2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7673 Q=_zz_execute_SrcPlugin_addSub_2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7671 Q=_zz_execute_SrcPlugin_addSub_2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7669 Q=_zz_execute_SrcPlugin_addSub_2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7667 Q=_zz_execute_SrcPlugin_addSub_2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7665 Q=_zz_execute_SrcPlugin_addSub_2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7985 Q=_zz_execute_SrcPlugin_addSub_2[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7961 Q=IBusSimplePlugin_rspJoin_rspBuffer_c.fifo.io_occupancy R=reset +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[2] Q=_zz_decode_SRC_LESS_UNSIGNED_4 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[3] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[3] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[4] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[4] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[5] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_47 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[6] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[6] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[7] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[7] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[8] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[8] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[9] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[9] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[10] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[10] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[11] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[11] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[12] Q=_zz__zz_decode_SRC_LESS_UNSIGNED_13 +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[13] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[13] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[14] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[14] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[25] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[25] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[26] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[26] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[27] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[27] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[28] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[28] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[29] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[29] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[30] Q=IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[30] +.subckt dff C=clk D=decode_INSTRUCTION_ANTICIPATED[31] Q=_zz_decode_SRC2 +.subckt dff C=clk D=externalInterrupt Q=CsrPlugin_mip_MEIP +.subckt dff C=clk D=timerInterrupt Q=CsrPlugin_mip_MTIP +.subckt dff C=clk D=$0\CsrPlugin_mip_MSIP[0:0] Q=CsrPlugin_mip_MSIP +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7619 Q=BranchPlugin_jumpInterface_payload[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7617 Q=BranchPlugin_jumpInterface_payload[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7615 Q=BranchPlugin_jumpInterface_payload[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7613 Q=BranchPlugin_jumpInterface_payload[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7611 Q=BranchPlugin_jumpInterface_payload[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7609 Q=BranchPlugin_jumpInterface_payload[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7607 Q=BranchPlugin_jumpInterface_payload[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7605 Q=BranchPlugin_jumpInterface_payload[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7603 Q=BranchPlugin_jumpInterface_payload[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7601 Q=BranchPlugin_jumpInterface_payload[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7599 Q=BranchPlugin_jumpInterface_payload[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7597 Q=BranchPlugin_jumpInterface_payload[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7595 Q=BranchPlugin_jumpInterface_payload[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7593 Q=BranchPlugin_jumpInterface_payload[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7591 Q=BranchPlugin_jumpInterface_payload[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7589 Q=BranchPlugin_jumpInterface_payload[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7587 Q=BranchPlugin_jumpInterface_payload[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7585 Q=BranchPlugin_jumpInterface_payload[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7583 Q=BranchPlugin_jumpInterface_payload[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7581 Q=BranchPlugin_jumpInterface_payload[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7579 Q=BranchPlugin_jumpInterface_payload[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7577 Q=BranchPlugin_jumpInterface_payload[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7575 Q=BranchPlugin_jumpInterface_payload[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7573 Q=BranchPlugin_jumpInterface_payload[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7571 Q=BranchPlugin_jumpInterface_payload[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7569 Q=BranchPlugin_jumpInterface_payload[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7567 Q=BranchPlugin_jumpInterface_payload[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7565 Q=BranchPlugin_jumpInterface_payload[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7563 Q=BranchPlugin_jumpInterface_payload[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7965 Q=BranchPlugin_jumpInterface_payload[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7561 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7559 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7557 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7555 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7553 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7551 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7549 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7547 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7545 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7543 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7541 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7539 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7537 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7535 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7533 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7531 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7529 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7527 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7525 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7523 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7521 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7519 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7517 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7515 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7513 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7511 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7509 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7507 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7505 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7971 Q=IBusSimplePlugin_injector_decodeInput_payload_pc[31] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[0] Q=HazardSimplePlugin_writeBackBuffer_payload_address[0] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[1] Q=HazardSimplePlugin_writeBackBuffer_payload_address[1] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[2] Q=HazardSimplePlugin_writeBackBuffer_payload_address[2] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[3] Q=HazardSimplePlugin_writeBackBuffer_payload_address[3] +.subckt dff C=clk D=HazardSimplePlugin_writeBackWrites_payload_address[4] Q=HazardSimplePlugin_writeBackBuffer_payload_address[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7503 Q=execute_LightShifterPlugin_amplitudeReg[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7501 Q=execute_LightShifterPlugin_amplitudeReg[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7499 Q=execute_LightShifterPlugin_amplitudeReg[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7497 Q=execute_LightShifterPlugin_amplitudeReg[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7949 Q=execute_LightShifterPlugin_amplitudeReg[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7495 Q=CsrPlugin_mepc[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7493 Q=CsrPlugin_mepc[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7491 Q=CsrPlugin_mepc[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7489 Q=CsrPlugin_mepc[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7487 Q=CsrPlugin_mepc[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7485 Q=CsrPlugin_mepc[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7483 Q=CsrPlugin_mepc[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7481 Q=CsrPlugin_mepc[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7479 Q=CsrPlugin_mepc[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7477 Q=CsrPlugin_mepc[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7475 Q=CsrPlugin_mepc[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7473 Q=CsrPlugin_mepc[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7471 Q=CsrPlugin_mepc[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7469 Q=CsrPlugin_mepc[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7467 Q=CsrPlugin_mepc[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7465 Q=CsrPlugin_mepc[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7463 Q=CsrPlugin_mepc[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7461 Q=CsrPlugin_mepc[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7459 Q=CsrPlugin_mepc[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7457 Q=CsrPlugin_mepc[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7455 Q=CsrPlugin_mepc[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7453 Q=CsrPlugin_mepc[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7451 Q=CsrPlugin_mepc[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7449 Q=CsrPlugin_mepc[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7447 Q=CsrPlugin_mepc[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7445 Q=CsrPlugin_mepc[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7443 Q=CsrPlugin_mepc[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7441 Q=CsrPlugin_mepc[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7439 Q=CsrPlugin_mepc[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7975 Q=CsrPlugin_mepc[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7423 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7421 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7419 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7417 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7415 Q=_zz__zz_execute_BranchPlugin_branch_src2_4[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7413 Q=dBus_cmd_payload_size[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7411 Q=switch_Misc_l241_1 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7409 Q=_zz__zz_execute_BranchPlugin_branch_src2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7407 Q=_zz__zz_execute_BranchPlugin_branch_src2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7405 Q=_zz__zz_execute_BranchPlugin_branch_src2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7403 Q=_zz__zz_execute_BranchPlugin_branch_src2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7401 Q=_zz__zz_execute_BranchPlugin_branch_src2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7399 Q=_zz__zz_execute_BranchPlugin_branch_src2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7397 Q=_zz__zz_execute_BranchPlugin_branch_src2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7395 Q=_zz__zz_execute_BranchPlugin_branch_src2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7393 Q=_zz__zz_execute_BranchPlugin_branch_src2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7391 Q=_zz__zz_execute_BranchPlugin_branch_src2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7389 Q=_zz__zz_execute_BranchPlugin_branch_src2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7387 Q=_zz__zz_execute_BranchPlugin_branch_src2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7385 Q=_zz__zz_execute_BranchPlugin_branch_src2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7383 Q=_zz__zz_execute_BranchPlugin_branch_src2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7381 Q=_zz__zz_execute_BranchPlugin_branch_src2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7379 Q=_zz__zz_execute_BranchPlugin_branch_src2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7377 Q=_zz__zz_execute_BranchPlugin_branch_src2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7947 Q=_zz_execute_BranchPlugin_branch_src2 +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[7] Q=HazardSimplePlugin_writeBackWrites_payload_address[0] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[8] Q=HazardSimplePlugin_writeBackWrites_payload_address[1] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[9] Q=HazardSimplePlugin_writeBackWrites_payload_address[2] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[10] Q=HazardSimplePlugin_writeBackWrites_payload_address[3] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[11] Q=HazardSimplePlugin_writeBackWrites_payload_address[4] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[12] Q=_zz_lastStageRegFileWrite_payload_address[12] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[13] Q=_zz_lastStageRegFileWrite_payload_address[13] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[14] Q=_zz_lastStageRegFileWrite_payload_address[14] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[28] Q=_zz_lastStageRegFileWrite_payload_address[28] +.subckt dff C=clk D=execute_to_memory_INSTRUCTION[29] Q=_zz_lastStageRegFileWrite_payload_address[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7361 Q=execute_to_memory_INSTRUCTION[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7359 Q=execute_to_memory_INSTRUCTION[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7357 Q=execute_to_memory_INSTRUCTION[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7355 Q=execute_to_memory_INSTRUCTION[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7353 Q=execute_to_memory_INSTRUCTION[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7351 Q=execute_to_memory_INSTRUCTION[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7349 Q=execute_to_memory_INSTRUCTION[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7347 Q=execute_to_memory_INSTRUCTION[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7319 Q=execute_to_memory_INSTRUCTION[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7317 Q=execute_to_memory_INSTRUCTION[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7943 Q=decode_to_execute_CSR_WRITE_OPCODE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7941 Q=_zz_execute_SrcPlugin_addSub_4 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7939 Q=decode_to_execute_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_MEMORY_ENABLE Q=memory_to_writeBack_MEMORY_ENABLE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7935 Q=decode_to_execute_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7937 Q=execute_to_memory_MEMORY_ENABLE +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_VALID Q=_zz_lastStageRegFileWrite_valid +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7931 Q=execute_to_memory_REGFILE_WRITE_VALID +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7929 Q=dBus_cmd_payload_wr +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7927 Q=execute_to_memory_MEMORY_STORE +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7925 Q=decode_to_execute_IS_CSR +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7923 Q=_zz_execute_ENV_CTRL +.subckt dff C=clk D=_zz_memory_ENV_CTRL Q=_zz_writeBack_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7921 Q=_zz_memory_ENV_CTRL +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7313 Q=_zz_execute_ALU_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7919 Q=_zz_execute_ALU_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7917 Q=decode_to_execute_SRC_LESS_UNSIGNED +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7311 Q=_zz_execute_ALU_BITWISE_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7915 Q=_zz_execute_ALU_BITWISE_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7309 Q=_zz_execute_SHIFT_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7913 Q=_zz_execute_SHIFT_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7307 Q=_zz_execute_BRANCH_CTRL[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7911 Q=_zz_execute_BRANCH_CTRL[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7305 Q=decode_to_execute_RS1[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7303 Q=decode_to_execute_RS1[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7301 Q=decode_to_execute_RS1[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7299 Q=decode_to_execute_RS1[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7297 Q=decode_to_execute_RS1[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7295 Q=decode_to_execute_RS1[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7293 Q=decode_to_execute_RS1[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7291 Q=decode_to_execute_RS1[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7289 Q=decode_to_execute_RS1[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7287 Q=decode_to_execute_RS1[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7285 Q=decode_to_execute_RS1[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7283 Q=decode_to_execute_RS1[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7281 Q=decode_to_execute_RS1[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7279 Q=decode_to_execute_RS1[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7277 Q=decode_to_execute_RS1[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7275 Q=decode_to_execute_RS1[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7273 Q=decode_to_execute_RS1[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7271 Q=decode_to_execute_RS1[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7269 Q=decode_to_execute_RS1[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7267 Q=decode_to_execute_RS1[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7265 Q=decode_to_execute_RS1[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7263 Q=decode_to_execute_RS1[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7261 Q=decode_to_execute_RS1[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7259 Q=decode_to_execute_RS1[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7257 Q=decode_to_execute_RS1[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7255 Q=decode_to_execute_RS1[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7253 Q=decode_to_execute_RS1[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7251 Q=decode_to_execute_RS1[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7249 Q=decode_to_execute_RS1[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7247 Q=decode_to_execute_RS1[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7245 Q=decode_to_execute_RS1[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7909 Q=decode_to_execute_RS1[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7243 Q=dBus_cmd_payload_data[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7241 Q=dBus_cmd_payload_data[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7239 Q=dBus_cmd_payload_data[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7237 Q=dBus_cmd_payload_data[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7235 Q=dBus_cmd_payload_data[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7233 Q=dBus_cmd_payload_data[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7231 Q=dBus_cmd_payload_data[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7229 Q=dBus_cmd_payload_data[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7227 Q=decode_to_execute_RS2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7225 Q=decode_to_execute_RS2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7223 Q=decode_to_execute_RS2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7221 Q=decode_to_execute_RS2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7219 Q=decode_to_execute_RS2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7217 Q=decode_to_execute_RS2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7215 Q=decode_to_execute_RS2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7213 Q=decode_to_execute_RS2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7211 Q=decode_to_execute_RS2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7209 Q=decode_to_execute_RS2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7207 Q=decode_to_execute_RS2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7205 Q=decode_to_execute_RS2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7203 Q=decode_to_execute_RS2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7201 Q=decode_to_execute_RS2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7199 Q=decode_to_execute_RS2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7197 Q=decode_to_execute_RS2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7195 Q=decode_to_execute_RS2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7193 Q=decode_to_execute_RS2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7191 Q=decode_to_execute_RS2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7189 Q=decode_to_execute_RS2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7187 Q=decode_to_execute_RS2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7185 Q=decode_to_execute_RS2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7183 Q=decode_to_execute_RS2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7907 Q=decode_to_execute_RS2[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7905 Q=decode_to_execute_SRC2_FORCE_ZERO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7181 Q=decode_to_execute_SRC2[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7179 Q=decode_to_execute_SRC2[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7177 Q=decode_to_execute_SRC2[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7175 Q=decode_to_execute_SRC2[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7173 Q=decode_to_execute_SRC2[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7171 Q=decode_to_execute_SRC2[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7169 Q=decode_to_execute_SRC2[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7167 Q=decode_to_execute_SRC2[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7165 Q=decode_to_execute_SRC2[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7163 Q=decode_to_execute_SRC2[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7161 Q=decode_to_execute_SRC2[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7159 Q=decode_to_execute_SRC2[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7157 Q=decode_to_execute_SRC2[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7155 Q=decode_to_execute_SRC2[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7153 Q=decode_to_execute_SRC2[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7151 Q=decode_to_execute_SRC2[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7149 Q=decode_to_execute_SRC2[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7147 Q=decode_to_execute_SRC2[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7145 Q=decode_to_execute_SRC2[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7143 Q=decode_to_execute_SRC2[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7141 Q=decode_to_execute_SRC2[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7139 Q=decode_to_execute_SRC2[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7137 Q=decode_to_execute_SRC2[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7135 Q=decode_to_execute_SRC2[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7133 Q=decode_to_execute_SRC2[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7131 Q=decode_to_execute_SRC2[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7129 Q=decode_to_execute_SRC2[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7127 Q=decode_to_execute_SRC2[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7125 Q=decode_to_execute_SRC2[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7123 Q=decode_to_execute_SRC2[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7121 Q=decode_to_execute_SRC2[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7903 Q=decode_to_execute_SRC2[31] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[0] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=execute_to_memory_MEMORY_ADDRESS_LOW[1] Q=memory_to_writeBack_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7119 Q=execute_to_memory_MEMORY_ADDRESS_LOW[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7901 Q=execute_to_memory_MEMORY_ADDRESS_LOW[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[0] Q=memory_to_writeBack_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[1] Q=memory_to_writeBack_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[2] Q=memory_to_writeBack_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[3] Q=memory_to_writeBack_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[4] Q=memory_to_writeBack_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[5] Q=memory_to_writeBack_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[6] Q=memory_to_writeBack_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[7] Q=memory_to_writeBack_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[8] Q=memory_to_writeBack_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[9] Q=memory_to_writeBack_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[10] Q=memory_to_writeBack_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[11] Q=memory_to_writeBack_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[12] Q=memory_to_writeBack_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[13] Q=memory_to_writeBack_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[14] Q=memory_to_writeBack_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[15] Q=memory_to_writeBack_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[16] Q=memory_to_writeBack_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[17] Q=memory_to_writeBack_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[18] Q=memory_to_writeBack_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[19] Q=memory_to_writeBack_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[20] Q=memory_to_writeBack_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[21] Q=memory_to_writeBack_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[22] Q=memory_to_writeBack_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[23] Q=memory_to_writeBack_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[24] Q=memory_to_writeBack_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[25] Q=memory_to_writeBack_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[26] Q=memory_to_writeBack_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[27] Q=memory_to_writeBack_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[28] Q=memory_to_writeBack_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[29] Q=memory_to_writeBack_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[30] Q=memory_to_writeBack_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=execute_to_memory_REGFILE_WRITE_DATA[31] Q=memory_to_writeBack_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7897 Q=execute_to_memory_BRANCH_DO +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7117 Q=execute_to_memory_REGFILE_WRITE_DATA[0] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7115 Q=execute_to_memory_REGFILE_WRITE_DATA[1] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7113 Q=execute_to_memory_REGFILE_WRITE_DATA[2] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7111 Q=execute_to_memory_REGFILE_WRITE_DATA[3] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7109 Q=execute_to_memory_REGFILE_WRITE_DATA[4] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7107 Q=execute_to_memory_REGFILE_WRITE_DATA[5] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7105 Q=execute_to_memory_REGFILE_WRITE_DATA[6] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7103 Q=execute_to_memory_REGFILE_WRITE_DATA[7] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7101 Q=execute_to_memory_REGFILE_WRITE_DATA[8] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7099 Q=execute_to_memory_REGFILE_WRITE_DATA[9] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7097 Q=execute_to_memory_REGFILE_WRITE_DATA[10] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7095 Q=execute_to_memory_REGFILE_WRITE_DATA[11] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7093 Q=execute_to_memory_REGFILE_WRITE_DATA[12] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7091 Q=execute_to_memory_REGFILE_WRITE_DATA[13] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7089 Q=execute_to_memory_REGFILE_WRITE_DATA[14] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7087 Q=execute_to_memory_REGFILE_WRITE_DATA[15] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7085 Q=execute_to_memory_REGFILE_WRITE_DATA[16] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7083 Q=execute_to_memory_REGFILE_WRITE_DATA[17] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7081 Q=execute_to_memory_REGFILE_WRITE_DATA[18] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7079 Q=execute_to_memory_REGFILE_WRITE_DATA[19] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7077 Q=execute_to_memory_REGFILE_WRITE_DATA[20] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7075 Q=execute_to_memory_REGFILE_WRITE_DATA[21] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7073 Q=execute_to_memory_REGFILE_WRITE_DATA[22] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7071 Q=execute_to_memory_REGFILE_WRITE_DATA[23] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7069 Q=execute_to_memory_REGFILE_WRITE_DATA[24] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7067 Q=execute_to_memory_REGFILE_WRITE_DATA[25] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7065 Q=execute_to_memory_REGFILE_WRITE_DATA[26] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7063 Q=execute_to_memory_REGFILE_WRITE_DATA[27] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7061 Q=execute_to_memory_REGFILE_WRITE_DATA[28] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7059 Q=execute_to_memory_REGFILE_WRITE_DATA[29] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7057 Q=execute_to_memory_REGFILE_WRITE_DATA[30] +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7899 Q=execute_to_memory_REGFILE_WRITE_DATA[31] +.subckt dff C=clk D=dBus_rsp_data[0] Q=memory_to_writeBack_MEMORY_READ_DATA[0] +.subckt dff C=clk D=dBus_rsp_data[1] Q=memory_to_writeBack_MEMORY_READ_DATA[1] +.subckt dff C=clk D=dBus_rsp_data[2] Q=memory_to_writeBack_MEMORY_READ_DATA[2] +.subckt dff C=clk D=dBus_rsp_data[3] Q=memory_to_writeBack_MEMORY_READ_DATA[3] +.subckt dff C=clk D=dBus_rsp_data[4] Q=memory_to_writeBack_MEMORY_READ_DATA[4] +.subckt dff C=clk D=dBus_rsp_data[5] Q=memory_to_writeBack_MEMORY_READ_DATA[5] +.subckt dff C=clk D=dBus_rsp_data[6] Q=memory_to_writeBack_MEMORY_READ_DATA[6] +.subckt dff C=clk D=dBus_rsp_data[7] Q=memory_to_writeBack_MEMORY_READ_DATA[7] +.subckt dff C=clk D=dBus_rsp_data[8] Q=memory_to_writeBack_MEMORY_READ_DATA[8] +.subckt dff C=clk D=dBus_rsp_data[9] Q=memory_to_writeBack_MEMORY_READ_DATA[9] +.subckt dff C=clk D=dBus_rsp_data[10] Q=memory_to_writeBack_MEMORY_READ_DATA[10] +.subckt dff C=clk D=dBus_rsp_data[11] Q=memory_to_writeBack_MEMORY_READ_DATA[11] +.subckt dff C=clk D=dBus_rsp_data[12] Q=memory_to_writeBack_MEMORY_READ_DATA[12] +.subckt dff C=clk D=dBus_rsp_data[13] Q=memory_to_writeBack_MEMORY_READ_DATA[13] +.subckt dff C=clk D=dBus_rsp_data[14] Q=memory_to_writeBack_MEMORY_READ_DATA[14] +.subckt dff C=clk D=dBus_rsp_data[15] Q=memory_to_writeBack_MEMORY_READ_DATA[15] +.subckt dff C=clk D=dBus_rsp_data[16] Q=memory_to_writeBack_MEMORY_READ_DATA[16] +.subckt dff C=clk D=dBus_rsp_data[17] Q=memory_to_writeBack_MEMORY_READ_DATA[17] +.subckt dff C=clk D=dBus_rsp_data[18] Q=memory_to_writeBack_MEMORY_READ_DATA[18] +.subckt dff C=clk D=dBus_rsp_data[19] Q=memory_to_writeBack_MEMORY_READ_DATA[19] +.subckt dff C=clk D=dBus_rsp_data[20] Q=writeBack_MEMORY_READ_DATA[20] +.subckt dff C=clk D=dBus_rsp_data[21] Q=writeBack_MEMORY_READ_DATA[21] +.subckt dff C=clk D=dBus_rsp_data[22] Q=writeBack_MEMORY_READ_DATA[22] +.subckt dff C=clk D=dBus_rsp_data[23] Q=writeBack_MEMORY_READ_DATA[23] +.subckt dff C=clk D=dBus_rsp_data[24] Q=writeBack_MEMORY_READ_DATA[24] +.subckt dff C=clk D=dBus_rsp_data[25] Q=writeBack_MEMORY_READ_DATA[25] +.subckt dff C=clk D=dBus_rsp_data[26] Q=writeBack_MEMORY_READ_DATA[26] +.subckt dff C=clk D=dBus_rsp_data[27] Q=writeBack_MEMORY_READ_DATA[27] +.subckt dff C=clk D=dBus_rsp_data[28] Q=writeBack_MEMORY_READ_DATA[28] +.subckt dff C=clk D=dBus_rsp_data[29] Q=writeBack_MEMORY_READ_DATA[29] +.subckt dff C=clk D=dBus_rsp_data[30] Q=writeBack_MEMORY_READ_DATA[30] +.subckt dff C=clk D=dBus_rsp_data[31] Q=writeBack_MEMORY_READ_DATA[31] +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7055 Q=IBusSimplePlugin_fetchPc_pcReg[2] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7053 Q=IBusSimplePlugin_fetchPc_pcReg[3] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7051 Q=IBusSimplePlugin_fetchPc_pcReg[4] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7049 Q=IBusSimplePlugin_fetchPc_pcReg[5] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7047 Q=IBusSimplePlugin_fetchPc_pcReg[6] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7045 Q=IBusSimplePlugin_fetchPc_pcReg[7] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7043 Q=IBusSimplePlugin_fetchPc_pcReg[8] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7041 Q=IBusSimplePlugin_fetchPc_pcReg[9] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7039 Q=IBusSimplePlugin_fetchPc_pcReg[10] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7037 Q=IBusSimplePlugin_fetchPc_pcReg[11] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7035 Q=IBusSimplePlugin_fetchPc_pcReg[12] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7033 Q=IBusSimplePlugin_fetchPc_pcReg[13] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7031 Q=IBusSimplePlugin_fetchPc_pcReg[14] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7029 Q=IBusSimplePlugin_fetchPc_pcReg[15] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7027 Q=IBusSimplePlugin_fetchPc_pcReg[16] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7025 Q=IBusSimplePlugin_fetchPc_pcReg[17] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7023 Q=IBusSimplePlugin_fetchPc_pcReg[18] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7021 Q=IBusSimplePlugin_fetchPc_pcReg[19] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7019 Q=IBusSimplePlugin_fetchPc_pcReg[20] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7017 Q=IBusSimplePlugin_fetchPc_pcReg[21] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7015 Q=IBusSimplePlugin_fetchPc_pcReg[22] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7013 Q=IBusSimplePlugin_fetchPc_pcReg[23] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7011 Q=IBusSimplePlugin_fetchPc_pcReg[24] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7009 Q=IBusSimplePlugin_fetchPc_pcReg[25] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7007 Q=IBusSimplePlugin_fetchPc_pcReg[26] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7005 Q=IBusSimplePlugin_fetchPc_pcReg[27] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7003 Q=IBusSimplePlugin_fetchPc_pcReg[28] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7001 Q=IBusSimplePlugin_fetchPc_pcReg[29] R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$6999 Q=IBusSimplePlugin_fetchPc_pcReg[30] R=reset +.subckt dffs C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7967 Q=IBusSimplePlugin_fetchPc_pcReg[31] S=reset +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7893 Q=execute_CsrPlugin_csr_768 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7891 Q=execute_CsrPlugin_csr_836 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7889 Q=execute_CsrPlugin_csr_772 +.subckt dff C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7887 Q=execute_CsrPlugin_csr_834 +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7885 Q=execute_arbitration_isValid R=reset +.subckt dffr C=clk D=$0\writeBack_arbitration_isValid[0:0] Q=lastStageIsFiring R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7883 Q=memory_arbitration_isValid R=reset +.subckt dffr C=clk D=$true Q=IBusSimplePlugin_fetchPc_booted R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7881 Q=IBusSimplePlugin_fetchPc_inc R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7879 Q=IBusSimplePlugin_iBusRsp_stages_1_input_valid R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[0] Q=IBusSimplePlugin_pending_value[0] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[1] Q=IBusSimplePlugin_pending_value[1] R=reset +.subckt dffr C=clk D=IBusSimplePlugin_pending_next[2] Q=IBusSimplePlugin_pending_value[2] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][0] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[0] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][1] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[1] R=reset +.subckt dffr C=clk D=$0\IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2:0][2] Q=IBusSimplePlugin_rspJoin_rspBuffer_discardCounter[2] R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MIE[0:0] Q=CsrPlugin_mstatus_MIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_mstatus_MPIE[0:0] Q=CsrPlugin_mstatus_MPIE R=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][0] Q=CsrPlugin_mstatus_MPP[0] S=reset +.subckt dffs C=clk D=$0\CsrPlugin_mstatus_MPP[1:0][1] Q=CsrPlugin_mstatus_MPP[1] S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7877 Q=IBusSimplePlugin_injector_decodeInput_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7875 Q=CsrPlugin_mie_MEIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7873 Q=CsrPlugin_mie_MTIE R=reset +.subckt dffr C=clk D=$0\CsrPlugin_interrupt_valid[0:0] Q=CsrPlugin_interrupt_valid R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7871 Q=CsrPlugin_mie_MSIE R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7869 Q=CsrPlugin_pipelineLiberator_pcValids_0 R=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7867 Q=CsrPlugin_pipelineLiberator_pcValids_1 R=reset +.subckt dffs C=clk D=$false Q=_zz_5 S=reset +.subckt dffr C=clk D=$abc$8788$auto$rtlil.cc:2693:MuxGate$7865 Q=CsrPlugin_pipelineLiberator_done R=reset +.subckt dffr C=clk D=HazardSimplePlugin_writeBackWrites_valid Q=HazardSimplePlugin_writeBackBuffer_valid R=reset +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port1[0] q_o[34]=_zz_RegFilePlugin_regFile_port1[1] q_o[33]=_zz_RegFilePlugin_regFile_port1[2] q_o[32]=_zz_RegFilePlugin_regFile_port1[3] q_o[31]=_zz_RegFilePlugin_regFile_port1[4] q_o[30]=_zz_RegFilePlugin_regFile_port1[5] q_o[29]=_zz_RegFilePlugin_regFile_port1[6] q_o[28]=_zz_RegFilePlugin_regFile_port1[7] q_o[27]=_zz_RegFilePlugin_regFile_port1[8] q_o[26]=_zz_RegFilePlugin_regFile_port1[9] q_o[25]=_zz_RegFilePlugin_regFile_port1[10] q_o[24]=_zz_RegFilePlugin_regFile_port1[11] q_o[23]=_zz_RegFilePlugin_regFile_port1[12] q_o[22]=_zz_RegFilePlugin_regFile_port1[13] q_o[21]=_zz_RegFilePlugin_regFile_port1[14] q_o[20]=_zz_RegFilePlugin_regFile_port1[15] q_o[19]=_zz_RegFilePlugin_regFile_port1[16] q_o[18]=_zz_RegFilePlugin_regFile_port1[17] q_o[17]=_zz_RegFilePlugin_regFile_port1[18] q_o[16]=_zz_RegFilePlugin_regFile_port1[19] q_o[15]=_zz_RegFilePlugin_regFile_port1[20] q_o[14]=_zz_RegFilePlugin_regFile_port1[21] q_o[13]=_zz_RegFilePlugin_regFile_port1[22] q_o[12]=_zz_RegFilePlugin_regFile_port1[23] q_o[11]=_zz_RegFilePlugin_regFile_port1[24] q_o[10]=_zz_RegFilePlugin_regFile_port1[25] q_o[9]=_zz_RegFilePlugin_regFile_port1[26] q_o[8]=_zz_RegFilePlugin_regFile_port1[27] q_o[7]=_zz_RegFilePlugin_regFile_port1[28] q_o[6]=_zz_RegFilePlugin_regFile_port1[29] q_o[5]=_zz_RegFilePlugin_regFile_port1[30] q_o[4]=_zz_RegFilePlugin_regFile_port1[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2203[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2203[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2203[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2203[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[20] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[21] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[22] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[23] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[24] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=lastStageRegFileWrite_payload_data[0] data_i[34]=lastStageRegFileWrite_payload_data[1] data_i[33]=lastStageRegFileWrite_payload_data[2] data_i[32]=lastStageRegFileWrite_payload_data[3] data_i[31]=lastStageRegFileWrite_payload_data[4] data_i[30]=lastStageRegFileWrite_payload_data[5] data_i[29]=lastStageRegFileWrite_payload_data[6] data_i[28]=lastStageRegFileWrite_payload_data[7] data_i[27]=lastStageRegFileWrite_payload_data[8] data_i[26]=lastStageRegFileWrite_payload_data[9] data_i[25]=lastStageRegFileWrite_payload_data[10] data_i[24]=lastStageRegFileWrite_payload_data[11] data_i[23]=lastStageRegFileWrite_payload_data[12] data_i[22]=lastStageRegFileWrite_payload_data[13] data_i[21]=lastStageRegFileWrite_payload_data[14] data_i[20]=lastStageRegFileWrite_payload_data[15] data_i[19]=lastStageRegFileWrite_payload_data[16] data_i[18]=lastStageRegFileWrite_payload_data[17] data_i[17]=lastStageRegFileWrite_payload_data[18] data_i[16]=lastStageRegFileWrite_payload_data[19] data_i[15]=lastStageRegFileWrite_payload_data[20] data_i[14]=lastStageRegFileWrite_payload_data[21] data_i[13]=lastStageRegFileWrite_payload_data[22] data_i[12]=lastStageRegFileWrite_payload_data[23] data_i[11]=lastStageRegFileWrite_payload_data[24] data_i[10]=lastStageRegFileWrite_payload_data[25] data_i[9]=lastStageRegFileWrite_payload_data[26] data_i[8]=lastStageRegFileWrite_payload_data[27] data_i[7]=lastStageRegFileWrite_payload_data[28] data_i[6]=lastStageRegFileWrite_payload_data[29] data_i[5]=lastStageRegFileWrite_payload_data[30] data_i[4]=lastStageRegFileWrite_payload_data[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=_zz_RegFilePlugin_regFile_port0[0] q_o[34]=_zz_RegFilePlugin_regFile_port0[1] q_o[33]=_zz_RegFilePlugin_regFile_port0[2] q_o[32]=_zz_RegFilePlugin_regFile_port0[3] q_o[31]=_zz_RegFilePlugin_regFile_port0[4] q_o[30]=_zz_RegFilePlugin_regFile_port0[5] q_o[29]=_zz_RegFilePlugin_regFile_port0[6] q_o[28]=_zz_RegFilePlugin_regFile_port0[7] q_o[27]=_zz_RegFilePlugin_regFile_port0[8] q_o[26]=_zz_RegFilePlugin_regFile_port0[9] q_o[25]=_zz_RegFilePlugin_regFile_port0[10] q_o[24]=_zz_RegFilePlugin_regFile_port0[11] q_o[23]=_zz_RegFilePlugin_regFile_port0[12] q_o[22]=_zz_RegFilePlugin_regFile_port0[13] q_o[21]=_zz_RegFilePlugin_regFile_port0[14] q_o[20]=_zz_RegFilePlugin_regFile_port0[15] q_o[19]=_zz_RegFilePlugin_regFile_port0[16] q_o[18]=_zz_RegFilePlugin_regFile_port0[17] q_o[17]=_zz_RegFilePlugin_regFile_port0[18] q_o[16]=_zz_RegFilePlugin_regFile_port0[19] q_o[15]=_zz_RegFilePlugin_regFile_port0[20] q_o[14]=_zz_RegFilePlugin_regFile_port0[21] q_o[13]=_zz_RegFilePlugin_regFile_port0[22] q_o[12]=_zz_RegFilePlugin_regFile_port0[23] q_o[11]=_zz_RegFilePlugin_regFile_port0[24] q_o[10]=_zz_RegFilePlugin_regFile_port0[25] q_o[9]=_zz_RegFilePlugin_regFile_port0[26] q_o[8]=_zz_RegFilePlugin_regFile_port0[27] q_o[7]=_zz_RegFilePlugin_regFile_port0[28] q_o[6]=_zz_RegFilePlugin_regFile_port0[29] q_o[5]=_zz_RegFilePlugin_regFile_port0[30] q_o[4]=_zz_RegFilePlugin_regFile_port0[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$2204[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$2204[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$2204[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$2204[35] raddr_i[7]=decode_INSTRUCTION_ANTICIPATED[15] raddr_i[6]=decode_INSTRUCTION_ANTICIPATED[16] raddr_i[5]=decode_INSTRUCTION_ANTICIPATED[17] raddr_i[4]=decode_INSTRUCTION_ANTICIPATED[18] raddr_i[3]=decode_INSTRUCTION_ANTICIPATED[19] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=lastStageRegFileWrite_payload_address[0] waddr_i[6]=lastStageRegFileWrite_payload_address[1] waddr_i[5]=lastStageRegFileWrite_payload_address[2] waddr_i[4]=lastStageRegFileWrite_payload_address[3] waddr_i[3]=lastStageRegFileWrite_payload_address[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=_zz_1 +.names $false BranchPlugin_jumpInterface_payload[0] +1 1 +.names $true CsrPlugin_interrupt_code[0] +1 1 +.names $true CsrPlugin_interrupt_code[1] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[0] +1 1 +.names $true CsrPlugin_mcause_exceptionCode[1] +1 1 +.names $false CsrPlugin_mepc[0] +1 1 +.names $false CsrPlugin_mepc[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[0] $auto$memory_bram.cc:844:replace_memory$2203[0] +1 1 +.names _zz_RegFilePlugin_regFile_port1[1] $auto$memory_bram.cc:844:replace_memory$2203[1] +1 1 +.names _zz_RegFilePlugin_regFile_port1[2] $auto$memory_bram.cc:844:replace_memory$2203[2] +1 1 +.names _zz_RegFilePlugin_regFile_port1[3] $auto$memory_bram.cc:844:replace_memory$2203[3] +1 1 +.names _zz_RegFilePlugin_regFile_port1[4] $auto$memory_bram.cc:844:replace_memory$2203[4] +1 1 +.names _zz_RegFilePlugin_regFile_port1[5] $auto$memory_bram.cc:844:replace_memory$2203[5] +1 1 +.names _zz_RegFilePlugin_regFile_port1[6] $auto$memory_bram.cc:844:replace_memory$2203[6] +1 1 +.names _zz_RegFilePlugin_regFile_port1[7] $auto$memory_bram.cc:844:replace_memory$2203[7] +1 1 +.names _zz_RegFilePlugin_regFile_port1[8] $auto$memory_bram.cc:844:replace_memory$2203[8] +1 1 +.names _zz_RegFilePlugin_regFile_port1[9] $auto$memory_bram.cc:844:replace_memory$2203[9] +1 1 +.names _zz_RegFilePlugin_regFile_port1[10] $auto$memory_bram.cc:844:replace_memory$2203[10] +1 1 +.names _zz_RegFilePlugin_regFile_port1[11] $auto$memory_bram.cc:844:replace_memory$2203[11] +1 1 +.names _zz_RegFilePlugin_regFile_port1[12] $auto$memory_bram.cc:844:replace_memory$2203[12] +1 1 +.names _zz_RegFilePlugin_regFile_port1[13] $auto$memory_bram.cc:844:replace_memory$2203[13] +1 1 +.names _zz_RegFilePlugin_regFile_port1[14] $auto$memory_bram.cc:844:replace_memory$2203[14] +1 1 +.names _zz_RegFilePlugin_regFile_port1[15] $auto$memory_bram.cc:844:replace_memory$2203[15] +1 1 +.names _zz_RegFilePlugin_regFile_port1[16] $auto$memory_bram.cc:844:replace_memory$2203[16] +1 1 +.names _zz_RegFilePlugin_regFile_port1[17] $auto$memory_bram.cc:844:replace_memory$2203[17] +1 1 +.names _zz_RegFilePlugin_regFile_port1[18] $auto$memory_bram.cc:844:replace_memory$2203[18] +1 1 +.names _zz_RegFilePlugin_regFile_port1[19] $auto$memory_bram.cc:844:replace_memory$2203[19] +1 1 +.names _zz_RegFilePlugin_regFile_port1[20] $auto$memory_bram.cc:844:replace_memory$2203[20] +1 1 +.names _zz_RegFilePlugin_regFile_port1[21] $auto$memory_bram.cc:844:replace_memory$2203[21] +1 1 +.names _zz_RegFilePlugin_regFile_port1[22] $auto$memory_bram.cc:844:replace_memory$2203[22] +1 1 +.names _zz_RegFilePlugin_regFile_port1[23] $auto$memory_bram.cc:844:replace_memory$2203[23] +1 1 +.names _zz_RegFilePlugin_regFile_port1[24] $auto$memory_bram.cc:844:replace_memory$2203[24] +1 1 +.names _zz_RegFilePlugin_regFile_port1[25] $auto$memory_bram.cc:844:replace_memory$2203[25] +1 1 +.names _zz_RegFilePlugin_regFile_port1[26] $auto$memory_bram.cc:844:replace_memory$2203[26] +1 1 +.names _zz_RegFilePlugin_regFile_port1[27] $auto$memory_bram.cc:844:replace_memory$2203[27] +1 1 +.names _zz_RegFilePlugin_regFile_port1[28] $auto$memory_bram.cc:844:replace_memory$2203[28] +1 1 +.names _zz_RegFilePlugin_regFile_port1[29] $auto$memory_bram.cc:844:replace_memory$2203[29] +1 1 +.names _zz_RegFilePlugin_regFile_port1[30] $auto$memory_bram.cc:844:replace_memory$2203[30] +1 1 +.names _zz_RegFilePlugin_regFile_port1[31] $auto$memory_bram.cc:844:replace_memory$2203[31] +1 1 +.names _zz_RegFilePlugin_regFile_port0[0] $auto$memory_bram.cc:844:replace_memory$2204[0] +1 1 +.names _zz_RegFilePlugin_regFile_port0[1] $auto$memory_bram.cc:844:replace_memory$2204[1] +1 1 +.names _zz_RegFilePlugin_regFile_port0[2] $auto$memory_bram.cc:844:replace_memory$2204[2] +1 1 +.names _zz_RegFilePlugin_regFile_port0[3] $auto$memory_bram.cc:844:replace_memory$2204[3] +1 1 +.names _zz_RegFilePlugin_regFile_port0[4] $auto$memory_bram.cc:844:replace_memory$2204[4] +1 1 +.names _zz_RegFilePlugin_regFile_port0[5] $auto$memory_bram.cc:844:replace_memory$2204[5] +1 1 +.names _zz_RegFilePlugin_regFile_port0[6] $auto$memory_bram.cc:844:replace_memory$2204[6] +1 1 +.names _zz_RegFilePlugin_regFile_port0[7] $auto$memory_bram.cc:844:replace_memory$2204[7] +1 1 +.names _zz_RegFilePlugin_regFile_port0[8] $auto$memory_bram.cc:844:replace_memory$2204[8] +1 1 +.names _zz_RegFilePlugin_regFile_port0[9] $auto$memory_bram.cc:844:replace_memory$2204[9] +1 1 +.names _zz_RegFilePlugin_regFile_port0[10] $auto$memory_bram.cc:844:replace_memory$2204[10] +1 1 +.names _zz_RegFilePlugin_regFile_port0[11] $auto$memory_bram.cc:844:replace_memory$2204[11] +1 1 +.names _zz_RegFilePlugin_regFile_port0[12] $auto$memory_bram.cc:844:replace_memory$2204[12] +1 1 +.names _zz_RegFilePlugin_regFile_port0[13] $auto$memory_bram.cc:844:replace_memory$2204[13] +1 1 +.names _zz_RegFilePlugin_regFile_port0[14] $auto$memory_bram.cc:844:replace_memory$2204[14] +1 1 +.names _zz_RegFilePlugin_regFile_port0[15] $auto$memory_bram.cc:844:replace_memory$2204[15] +1 1 +.names _zz_RegFilePlugin_regFile_port0[16] $auto$memory_bram.cc:844:replace_memory$2204[16] +1 1 +.names _zz_RegFilePlugin_regFile_port0[17] $auto$memory_bram.cc:844:replace_memory$2204[17] +1 1 +.names _zz_RegFilePlugin_regFile_port0[18] $auto$memory_bram.cc:844:replace_memory$2204[18] +1 1 +.names _zz_RegFilePlugin_regFile_port0[19] $auto$memory_bram.cc:844:replace_memory$2204[19] +1 1 +.names _zz_RegFilePlugin_regFile_port0[20] $auto$memory_bram.cc:844:replace_memory$2204[20] +1 1 +.names _zz_RegFilePlugin_regFile_port0[21] $auto$memory_bram.cc:844:replace_memory$2204[21] +1 1 +.names _zz_RegFilePlugin_regFile_port0[22] $auto$memory_bram.cc:844:replace_memory$2204[22] +1 1 +.names _zz_RegFilePlugin_regFile_port0[23] $auto$memory_bram.cc:844:replace_memory$2204[23] +1 1 +.names _zz_RegFilePlugin_regFile_port0[24] $auto$memory_bram.cc:844:replace_memory$2204[24] +1 1 +.names _zz_RegFilePlugin_regFile_port0[25] $auto$memory_bram.cc:844:replace_memory$2204[25] +1 1 +.names _zz_RegFilePlugin_regFile_port0[26] $auto$memory_bram.cc:844:replace_memory$2204[26] +1 1 +.names _zz_RegFilePlugin_regFile_port0[27] $auto$memory_bram.cc:844:replace_memory$2204[27] +1 1 +.names _zz_RegFilePlugin_regFile_port0[28] $auto$memory_bram.cc:844:replace_memory$2204[28] +1 1 +.names _zz_RegFilePlugin_regFile_port0[29] $auto$memory_bram.cc:844:replace_memory$2204[29] +1 1 +.names _zz_RegFilePlugin_regFile_port0[30] $auto$memory_bram.cc:844:replace_memory$2204[30] +1 1 +.names _zz_RegFilePlugin_regFile_port0[31] $auto$memory_bram.cc:844:replace_memory$2204[31] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[0] +1 1 +.names $false IBusSimplePlugin_fetchPc_pcReg[1] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[0] +1 1 +.names $false IBusSimplePlugin_injector_decodeInput_payload_pc[1] +1 1 +.names _zz_decode_SRC_LESS_UNSIGNED_4 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[2] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_47 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[5] +1 1 +.names _zz__zz_decode_SRC_LESS_UNSIGNED_13 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[12] +1 1 +.names _zz_decode_SRC2 IBusSimplePlugin_injector_decodeInput_payload_rsp_inst[31] +1 1 +.names dBus_cmd_payload_size[0] _zz__zz_execute_BranchPlugin_branch_src2[11] +1 1 +.names switch_Misc_l241_1 _zz__zz_execute_BranchPlugin_branch_src2[12] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2[19] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[4] _zz__zz_execute_BranchPlugin_branch_src2_4[4] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[5] _zz__zz_execute_BranchPlugin_branch_src2_4[5] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[6] _zz__zz_execute_BranchPlugin_branch_src2_4[6] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[7] _zz__zz_execute_BranchPlugin_branch_src2_4[7] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[8] _zz__zz_execute_BranchPlugin_branch_src2_4[8] +1 1 +.names _zz__zz_execute_BranchPlugin_branch_src2[9] _zz__zz_execute_BranchPlugin_branch_src2_4[9] +1 1 +.names _zz_execute_BranchPlugin_branch_src2 _zz__zz_execute_BranchPlugin_branch_src2_4[11] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[0] _zz_lastStageRegFileWrite_payload_address[7] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[1] _zz_lastStageRegFileWrite_payload_address[8] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[2] _zz_lastStageRegFileWrite_payload_address[9] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[3] _zz_lastStageRegFileWrite_payload_address[10] +1 1 +.names HazardSimplePlugin_writeBackWrites_payload_address[4] _zz_lastStageRegFileWrite_payload_address[11] +1 1 +.names switch_Misc_l241_1 dBus_cmd_payload_size[1] +1 1 +.names $false decode_to_execute_PC[0] +1 1 +.names $false decode_to_execute_PC[1] +1 1 +.names dBus_cmd_payload_data[0] decode_to_execute_RS2[0] +1 1 +.names dBus_cmd_payload_data[1] decode_to_execute_RS2[1] +1 1 +.names dBus_cmd_payload_data[2] decode_to_execute_RS2[2] +1 1 +.names dBus_cmd_payload_data[3] decode_to_execute_RS2[3] +1 1 +.names dBus_cmd_payload_data[4] decode_to_execute_RS2[4] +1 1 +.names dBus_cmd_payload_data[5] decode_to_execute_RS2[5] +1 1 +.names dBus_cmd_payload_data[6] decode_to_execute_RS2[6] +1 1 +.names dBus_cmd_payload_data[7] decode_to_execute_RS2[7] +1 1 +.names $false iBus_cmd_payload_pc[0] +1 1 +.names $false iBus_cmd_payload_pc[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[0] writeBack_MEMORY_READ_DATA[0] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[1] writeBack_MEMORY_READ_DATA[1] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[2] writeBack_MEMORY_READ_DATA[2] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[3] writeBack_MEMORY_READ_DATA[3] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[4] writeBack_MEMORY_READ_DATA[4] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[5] writeBack_MEMORY_READ_DATA[5] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[6] writeBack_MEMORY_READ_DATA[6] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[7] writeBack_MEMORY_READ_DATA[7] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[8] writeBack_MEMORY_READ_DATA[8] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[9] writeBack_MEMORY_READ_DATA[9] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[10] writeBack_MEMORY_READ_DATA[10] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[11] writeBack_MEMORY_READ_DATA[11] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[12] writeBack_MEMORY_READ_DATA[12] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[13] writeBack_MEMORY_READ_DATA[13] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[14] writeBack_MEMORY_READ_DATA[14] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[15] writeBack_MEMORY_READ_DATA[15] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[16] writeBack_MEMORY_READ_DATA[16] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[17] writeBack_MEMORY_READ_DATA[17] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[18] writeBack_MEMORY_READ_DATA[18] +1 1 +.names memory_to_writeBack_MEMORY_READ_DATA[19] writeBack_MEMORY_READ_DATA[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif new file mode 100644 index 00000000000..66d55f64118 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/boxcar.blif @@ -0,0 +1,1473 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model boxcar +.inputs i_clk i_reset i_navg[0] i_navg[1] i_navg[2] i_navg[3] i_navg[4] i_navg[5] i_ce i_sample[0] i_sample[1] i_sample[2] i_sample[3] i_sample[4] i_sample[5] i_sample[6] i_sample[7] i_sample[8] i_sample[9] i_sample[10] i_sample[11] i_sample[12] i_sample[13] i_sample[14] i_sample[15] +.outputs o_result[0] o_result[1] o_result[2] o_result[3] o_result[4] o_result[5] o_result[6] o_result[7] o_result[8] o_result[9] o_result[10] o_result[11] o_result[12] o_result[13] o_result[14] o_result[15] o_result[16] o_result[17] o_result[18] o_result[19] o_result[20] o_result[21] +.names $false +.names $true +1 +.names $undef +.names wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1509 +01 1 +10 1 +.names wraddr[0] wraddr[1] wraddr[2] wraddr[3] i_ce $abc$1868$new_n225 +11111 1 +.names wraddr[3] wraddr[0] wraddr[1] wraddr[2] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1511 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names wraddr[2] wraddr[0] wraddr[1] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1513 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names wraddr[1] wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1515 +011 1 +100 1 +101 1 +110 1 +.names wraddr[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1517 +01 1 +10 1 +.names i_ce i_sample[14] preval[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1519 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[13] preval[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1521 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[12] preval[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1523 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[11] preval[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1525 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[10] preval[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1527 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[9] preval[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1529 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[8] preval[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1531 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[7] preval[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1533 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[6] preval[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1535 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[5] preval[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1537 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[4] preval[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1539 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[3] preval[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1541 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[2] preval[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1543 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[1] preval[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1545 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_sample[0] preval[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1547 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[20] o_result[20] $abc$1868$auto$rtlil.cc:2693:MuxGate$1549 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[19] o_result[19] $abc$1868$auto$rtlil.cc:2693:MuxGate$1551 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[18] o_result[18] $abc$1868$auto$rtlil.cc:2693:MuxGate$1553 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[17] o_result[17] $abc$1868$auto$rtlil.cc:2693:MuxGate$1555 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[16] o_result[16] $abc$1868$auto$rtlil.cc:2693:MuxGate$1557 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[15] o_result[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1559 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[14] o_result[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1561 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[13] o_result[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1563 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[12] o_result[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1565 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[11] o_result[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1567 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[10] o_result[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1569 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[9] o_result[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1571 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[8] o_result[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1573 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[7] o_result[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1575 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[6] o_result[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1577 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[5] o_result[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1579 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[4] o_result[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1581 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[3] o_result[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1583 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[2] o_result[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1585 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[1] o_result[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1587 +001 1 +011 1 +110 1 +111 1 +.names i_ce acc[0] o_result[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1589 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$1868$new_n267 sub[15] full preval[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1591 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names full $abc$1868$new_n288 preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n267 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names preval[13] $abc$1868$new_n284 $abc$1868$new_n286 $abc$1868$new_n269 $abc$1868$new_n285 $abc$1868$new_n268 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names preval[10] preval[11] $abc$1868$new_n283 $abc$1868$new_n282 $abc$1868$new_n270 $abc$1868$new_n269 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$new_n281 preval[8] preval[9] $abc$1868$new_n280 $abc$1868$new_n271 $abc$1868$new_n270 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names preval[6] preval[7] $abc$1868$new_n279 $abc$1868$new_n278 $abc$1868$new_n272 $abc$1868$new_n271 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$new_n277 preval[4] preval[5] $abc$1868$new_n276 $abc$1868$new_n273 $abc$1868$new_n272 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$mem.cc:1432:emulate_reset$543 preval[3] $abc$1868$new_n274 $abc$1868$new_n273 +0001 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$mem.cc:1432:emulate_reset$543 preval[2] $abc$1868$new_n275 $abc$1868$new_n274 +0001 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] preval[0] preval[1] $abc$1868$new_n275 +10100 1 +10110 1 +11000 1 +11100 1 +11101 1 +11110 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[5] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n276 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[4] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n277 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[7] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n278 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[6] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n279 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n280 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n281 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n282 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n283 +11 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[13] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n284 +11 1 +.names preval[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $abc$1868$new_n285 +100 1 +101 1 +110 1 +.names preval[12] $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n286 +000 1 +001 1 +010 1 +111 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[14] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n287 +11 1 +.names preval[15] $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n288 +000 1 +001 1 +010 1 +111 1 +.names i_ce full sub[14] $abc$1868$new_n290 preval[14] $abc$1868$auto$rtlil.cc:2693:MuxGate$1593 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n290 +000 1 +011 1 +101 1 +110 1 +.names i_ce full sub[12] $abc$1868$new_n295 preval[12] $abc$1868$auto$rtlil.cc:2693:MuxGate$1597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$1868$new_n286 $abc$1868$new_n269 $abc$1868$new_n295 +01 1 +10 1 +.names i_ce full sub[10] $abc$1868$new_n300 preval[10] $abc$1868$auto$rtlil.cc:2693:MuxGate$1601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[10] $abc$1868$new_n283 $abc$1868$new_n270 $abc$1868$new_n300 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[8] $abc$1868$new_n305 preval[8] $abc$1868$auto$rtlil.cc:2693:MuxGate$1605 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[8] $abc$1868$new_n281 $abc$1868$new_n271 $abc$1868$new_n305 +000 1 +011 1 +101 1 +110 1 +.names i_ce full sub[7] $abc$1868$new_n307 preval[7] $abc$1868$auto$rtlil.cc:2693:MuxGate$1607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[7] $abc$1868$new_n278 preval[6] $abc$1868$new_n279 $abc$1868$new_n272 $abc$1868$new_n307 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce full sub[6] $abc$1868$new_n309 preval[6] $abc$1868$auto$rtlil.cc:2693:MuxGate$1609 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[6] $abc$1868$new_n279 $abc$1868$new_n272 $abc$1868$new_n309 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[5] $abc$1868$new_n311 preval[5] $abc$1868$auto$rtlil.cc:2693:MuxGate$1611 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[5] $abc$1868$new_n276 preval[4] $abc$1868$new_n277 $abc$1868$new_n273 $abc$1868$new_n311 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce full sub[4] $abc$1868$new_n313 preval[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1613 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[4] $abc$1868$new_n277 $abc$1868$new_n273 $abc$1868$new_n313 +001 1 +010 1 +100 1 +111 1 +.names i_ce full sub[3] $abc$1868$new_n315 preval[3] $abc$1868$auto$rtlil.cc:2693:MuxGate$1615 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[3] $abc$1868$new_n274 $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n315 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce full sub[2] $abc$1868$new_n317 preval[2] $abc$1868$auto$rtlil.cc:2693:MuxGate$1617 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[2] $abc$1868$new_n275 $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n317 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce full sub[1] $abc$1868$new_n319 preval[1] $abc$1868$auto$rtlil.cc:2693:MuxGate$1619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names preval[1] $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] preval[0] $abc$1868$new_n319 +00110 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce $abc$1868$new_n321 sub[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1621 +001 1 +011 1 +100 1 +101 1 +.names preval[0] $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $auto$mem.cc:1432:emulate_reset$543 full $abc$1868$new_n321 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1111 1 +.names acc[20] acc[18] acc[19] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1623 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[17] i_ce sub[16] acc[16] $abc$1868$new_n324 $abc$1868$new_n323 +11010 1 +11100 1 +11110 1 +11111 1 +.names sub[14] acc[14] sub[15] acc[15] $abc$1868$new_n325 $abc$1868$new_n324 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[12] acc[12] sub[13] acc[13] $abc$1868$new_n326 $abc$1868$new_n325 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[10] acc[10] sub[11] acc[11] $abc$1868$new_n327 $abc$1868$new_n326 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[8] acc[8] sub[9] acc[9] $abc$1868$new_n328 $abc$1868$new_n327 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[6] acc[6] sub[7] acc[7] $abc$1868$new_n329 $abc$1868$new_n328 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[4] acc[4] sub[5] acc[5] $abc$1868$new_n330 $abc$1868$new_n329 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[2] acc[2] sub[3] acc[3] $abc$1868$new_n331 $abc$1868$new_n330 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names sub[0] acc[0] sub[1] acc[1] $abc$1868$new_n331 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names acc[19] acc[18] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1625 +011 1 +100 1 +101 1 +110 1 +.names acc[18] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1627 +01 1 +10 1 +.names acc[17] i_ce sub[16] acc[16] $abc$1868$new_n324 $abc$1868$auto$rtlil.cc:2693:MuxGate$1629 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names acc[16] sub[16] $abc$1868$new_n324 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1631 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[15] sub[15] $abc$1868$new_n337 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1633 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[14] acc[14] $abc$1868$new_n325 $abc$1868$new_n337 +000 1 +001 1 +011 1 +101 1 +.names acc[14] sub[14] $abc$1868$new_n325 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1635 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[13] sub[13] $abc$1868$new_n340 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1637 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[12] acc[12] $abc$1868$new_n326 $abc$1868$new_n340 +000 1 +001 1 +011 1 +101 1 +.names acc[12] sub[12] $abc$1868$new_n326 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1639 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[11] sub[11] $abc$1868$new_n343 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1641 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[10] acc[10] $abc$1868$new_n327 $abc$1868$new_n343 +000 1 +001 1 +011 1 +101 1 +.names acc[10] sub[10] $abc$1868$new_n327 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1643 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[9] sub[9] $abc$1868$new_n346 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1645 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[8] acc[8] $abc$1868$new_n328 $abc$1868$new_n346 +000 1 +001 1 +011 1 +101 1 +.names acc[8] sub[8] $abc$1868$new_n328 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1647 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[7] sub[7] $abc$1868$new_n349 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1649 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[6] acc[6] $abc$1868$new_n329 $abc$1868$new_n349 +000 1 +001 1 +011 1 +101 1 +.names acc[6] sub[6] $abc$1868$new_n329 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1651 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[5] sub[5] $abc$1868$new_n352 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1653 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[4] acc[4] $abc$1868$new_n330 $abc$1868$new_n352 +000 1 +001 1 +011 1 +101 1 +.names acc[4] sub[4] $abc$1868$new_n330 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1655 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[3] sub[3] $abc$1868$new_n355 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1657 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names sub[2] acc[2] $abc$1868$new_n331 $abc$1868$new_n355 +000 1 +001 1 +011 1 +101 1 +.names acc[2] sub[2] $abc$1868$new_n331 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1659 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names acc[1] sub[1] sub[0] acc[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1661 +00111 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names acc[0] sub[0] i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1663 +011 1 +100 1 +101 1 +110 1 +.names i_reset rdaddr[4] $abc$1868$new_n360 $abc$1868$new_n363 $abc$1868$auto$rtlil.cc:2693:MuxGate$1665 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n360 +111 1 +.names rdaddr[2] $abc$1868$new_n362 $abc$1868$new_n361 +11 1 +.names rdaddr[0] rdaddr[1] $abc$1868$new_n362 +11 1 +.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n363 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_reset rdaddr[3] i_ce $abc$1868$new_n361 $abc$1868$new_n365 $abc$1868$auto$rtlil.cc:2693:MuxGate$1667 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n365 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_reset rdaddr[2] i_ce $abc$1868$new_n362 $abc$1868$new_n367 $abc$1868$auto$rtlil.cc:2693:MuxGate$1669 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n367 +001 1 +010 1 +011 1 +100 1 +.names rdaddr[1] $abc$1868$new_n369 rdaddr[0] i_ce i_reset $abc$1868$auto$rtlil.cc:2693:MuxGate$1671 +00110 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_reset i_navg[1] i_navg[0] $abc$1868$new_n369 +101 1 +110 1 +.names i_reset rdaddr[0] i_ce i_navg[0] $abc$1868$auto$rtlil.cc:2693:MuxGate$1673 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_reset rdaddr[5] i_ce $abc$1868$new_n372 $abc$1868$new_n373 $abc$1868$auto$rtlil.cc:2693:MuxGate$1675 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names rdaddr[3] rdaddr[4] $abc$1868$new_n361 $abc$1868$new_n372 +111 1 +.names i_navg[5] $abc$1868$new_n374 $abc$1868$new_n373 +01 1 +10 1 +.names i_navg[4] i_navg[3] i_navg[2] i_navg[1] i_navg[0] $abc$1868$new_n374 +00000 1 +.names i_ce acc[21] o_result[21] $abc$1868$auto$rtlil.cc:2693:MuxGate$1677 +001 1 +011 1 +110 1 +111 1 +.names acc[21] acc[18] acc[19] acc[20] $abc$1868$new_n323 $abc$1868$auto$rtlil.cc:2693:MuxGate$1679 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce sub[16] $abc$1868$new_n379 $abc$1868$new_n378 $abc$1868$auto$rtlil.cc:2693:MuxGate$1681 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$1868$new_n288 preval[14] $abc$1868$new_n287 $abc$1868$new_n268 $abc$1868$new_n378 +1001 1 +1100 1 +1101 1 +1111 1 +.names full preval[15] $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n379 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names full $abc$1868$new_n381 i_ce rdaddr[4] $abc$1868$auto$rtlil.cc:2693:MuxGate$1683 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rdaddr[5] rdaddr[0] rdaddr[1] rdaddr[2] rdaddr[3] $abc$1868$new_n381 +00000 1 +.names i_ce i_sample[15] preval[15] $abc$1868$auto$rtlil.cc:2693:MuxGate$1685 +001 1 +011 1 +110 1 +111 1 +.names wraddr[5] wraddr[4] $abc$1868$new_n225 $abc$1868$auto$rtlil.cc:2693:MuxGate$1687 +011 1 +100 1 +101 1 +110 1 +.names $auto$mem.cc:1432:emulate_reset$543 i_ce $abc$1868$auto$rtlil.cc:2693:MuxGate$1689 +01 1 +10 1 +11 1 +.names $abc$1868$new_n284 $abc$1868$new_n269 preval[12] $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$mem.cc:1432:emulate_reset$543 $abc$1868$new_n385 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce preval[13] full $abc$1868$new_n385 sub[13] $abc$1868$auto$rtlil.cc:2693:MuxGate$1595 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $abc$1868$new_n270 preval[10] $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $abc$1868$new_n387 +00100 1 +00101 1 +01100 1 +01101 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names i_ce preval[11] full $abc$1868$new_n387 sub[11] $abc$1868$auto$rtlil.cc:2693:MuxGate$1599 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$mem.cc:1432:emulate_reset$543 $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $abc$1868$new_n271 preval[8] $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $abc$1868$new_n389 +00000 1 +00001 1 +01000 1 +01001 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce preval[9] full $abc$1868$new_n389 sub[9] $abc$1868$auto$rtlil.cc:2693:MuxGate$1603 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1673 Q=rdaddr[0] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1671 Q=rdaddr[1] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1669 Q=rdaddr[2] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1667 Q=rdaddr[3] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1665 Q=rdaddr[4] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1675 Q=rdaddr[5] +.subckt dff C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1689 Q=$auto$mem.cc:1432:emulate_reset$543 +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1663 Q=acc[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1661 Q=acc[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1659 Q=acc[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1657 Q=acc[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1655 Q=acc[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1653 Q=acc[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1651 Q=acc[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1649 Q=acc[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1647 Q=acc[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1645 Q=acc[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1643 Q=acc[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1641 Q=acc[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1639 Q=acc[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1637 Q=acc[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1635 Q=acc[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1633 Q=acc[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1631 Q=acc[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1629 Q=acc[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1627 Q=acc[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1625 Q=acc[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1623 Q=acc[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1679 Q=acc[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1621 Q=sub[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1619 Q=sub[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1617 Q=sub[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1615 Q=sub[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1613 Q=sub[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1611 Q=sub[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1609 Q=sub[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1607 Q=sub[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1605 Q=sub[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1603 Q=sub[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1601 Q=sub[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1599 Q=sub[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1597 Q=sub[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1595 Q=sub[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1593 Q=sub[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1591 Q=sub[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1681 Q=sub[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1683 Q=full R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1589 Q=o_result[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1587 Q=o_result[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1585 Q=o_result[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1583 Q=o_result[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1581 Q=o_result[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1579 Q=o_result[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1577 Q=o_result[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1575 Q=o_result[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1573 Q=o_result[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1571 Q=o_result[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1569 Q=o_result[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1567 Q=o_result[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1565 Q=o_result[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1563 Q=o_result[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1561 Q=o_result[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1559 Q=o_result[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1557 Q=o_result[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1555 Q=o_result[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1553 Q=o_result[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1551 Q=o_result[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1549 Q=o_result[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1677 Q=o_result[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1547 Q=preval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1545 Q=preval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1543 Q=preval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1541 Q=preval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1539 Q=preval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1537 Q=preval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1535 Q=preval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1533 Q=preval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1531 Q=preval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1529 Q=preval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1527 Q=preval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1525 Q=preval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1523 Q=preval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1521 Q=preval[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1519 Q=preval[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1685 Q=preval[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1517 Q=wraddr[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1515 Q=wraddr[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1513 Q=wraddr[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1511 Q=wraddr[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1509 Q=wraddr[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$1868$auto$rtlil.cc:2693:MuxGate$1687 Q=wraddr[5] R=i_reset +.subckt dpram512x18 bwen_ni[17]=$true bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[17]=i_sample[0] data_i[16]=i_sample[1] data_i[15]=i_sample[2] data_i[14]=i_sample[3] data_i[13]=i_sample[4] data_i[12]=i_sample[5] data_i[11]=i_sample[6] data_i[10]=i_sample[7] data_i[9]=i_sample[8] data_i[8]=i_sample[9] data_i[7]=i_sample[10] data_i[6]=i_sample[11] data_i[5]=i_sample[12] data_i[4]=i_sample[13] data_i[3]=i_sample[14] data_i[2]=i_sample[15] data_i[1]=$undef data_i[0]=$undef q_o[17]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[0] q_o[16]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[1] q_o[15]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[2] q_o[14]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[3] q_o[13]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[4] q_o[12]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[5] q_o[11]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[6] q_o[10]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[7] q_o[9]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[8] q_o[8]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[9] q_o[7]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[10] q_o[6]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[11] q_o[5]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[12] q_o[4]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[13] q_o[3]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[14] q_o[2]=$abc$1868$auto$mem.cc:1434:emulate_reset$545[15] q_o[1]=$auto$memory_bram.cc:844:replace_memory$547[16] q_o[0]=$auto$memory_bram.cc:844:replace_memory$547[17] raddr_i[8]=rdaddr[0] raddr_i[7]=rdaddr[1] raddr_i[6]=rdaddr[2] raddr_i[5]=rdaddr[3] raddr_i[4]=rdaddr[4] raddr_i[3]=rdaddr[5] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=i_clk ren_ni=i_ce waddr_i[8]=wraddr[0] waddr_i[7]=wraddr[1] waddr_i[6]=wraddr[2] waddr_i[5]=wraddr[3] waddr_i[4]=wraddr[4] waddr_i[3]=wraddr[5] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=i_clk wen_ni=i_ce +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[0] $auto$memory_bram.cc:844:replace_memory$547[0] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[1] $auto$memory_bram.cc:844:replace_memory$547[1] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[2] $auto$memory_bram.cc:844:replace_memory$547[2] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[3] $auto$memory_bram.cc:844:replace_memory$547[3] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[4] $auto$memory_bram.cc:844:replace_memory$547[4] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[5] $auto$memory_bram.cc:844:replace_memory$547[5] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[6] $auto$memory_bram.cc:844:replace_memory$547[6] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[7] $auto$memory_bram.cc:844:replace_memory$547[7] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[8] $auto$memory_bram.cc:844:replace_memory$547[8] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[9] $auto$memory_bram.cc:844:replace_memory$547[9] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[10] $auto$memory_bram.cc:844:replace_memory$547[10] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[11] $auto$memory_bram.cc:844:replace_memory$547[11] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[12] $auto$memory_bram.cc:844:replace_memory$547[12] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[13] $auto$memory_bram.cc:844:replace_memory$547[13] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[14] $auto$memory_bram.cc:844:replace_memory$547[14] +1 1 +.names $abc$1868$auto$mem.cc:1434:emulate_reset$545[15] $auto$memory_bram.cc:844:replace_memory$547[15] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif new file mode 100644 index 00000000000..5c089e7eadc --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordic.blif @@ -0,0 +1,27532 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model cordic +.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] i_aux +.outputs o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux +.names $false +.names $true +1 +.names $undef +.names i_ce ax[15] ax[14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19848 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[14] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19850 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[12] ax[13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19852 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[11] ax[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19854 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[10] ax[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19856 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[9] ax[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19858 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[8] ax[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19860 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[7] ax[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19862 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[6] ax[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19864 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[5] ax[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19866 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[4] ax[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19868 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[3] ax[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19870 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[2] ax[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19872 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[1] ax[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19874 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[0] ax[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19876 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_aux ax[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19878 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[17] ph[0][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$19880 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[17] ph[0][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$19882 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[16] ph[0][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$19884 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[15] ph[0][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$19886 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[14] ph[0][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$19888 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[13] ph[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19890 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[12] ph[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19892 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[11] ph[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19894 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[10] ph[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19896 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[9] ph[0][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19898 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[8] ph[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19900 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[7] ph[0][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19902 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[6] ph[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19904 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[5] ph[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19906 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[4] ph[0][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19908 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[3] ph[0][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19910 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[2] ph[0][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19912 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[1] ph[0][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19914 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_phase[0] ph[0][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19916 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][14] $abc$23348$new_n1870 $abc$23348$new_n1874 $abc$23348$new_n1864 $abc$23348$auto$rtlil.cc:2693:MuxGate$19918 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$23348$new_n1869 i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n1864 +100 1 +111 1 +.names $abc$23348$new_n1866 i_yval[11] i_yval[10] $abc$23348$new_n1865 +100 1 +.names $abc$23348$new_n1867 i_yval[9] $abc$23348$new_n1866 +10 1 +.names $abc$23348$new_n1868 i_yval[8] i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1867 +10000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1868 +00000 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1869 +011 1 +100 1 +.names i_xval[12] i_phase[19] $abc$23348$new_n1871 i_phase[18] i_phase[17] $abc$23348$new_n1870 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10011 1 +10100 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names $abc$23348$new_n1872 i_xval[11] i_xval[10] i_xval[9] $abc$23348$new_n1871 +1000 1 +.names $abc$23348$new_n1873 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1872 +10000 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1873 +00000 1 +.names i_ce $abc$23348$new_n1875 i_yval[12] $abc$23348$new_n1874 +100 1 +101 1 +110 1 +.names i_phase[18] i_phase[19] i_phase[17] $abc$23348$new_n1875 +000 1 +111 1 +.names i_ce $abc$23348$new_n1877 yv[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19920 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1878 $abc$23348$new_n1881 $abc$23348$new_n1880 $abc$23348$new_n1875 i_yval[11] $abc$23348$new_n1877 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$23348$new_n1879 $abc$23348$new_n1878 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11011 1 +.names i_yval[11] $abc$23348$new_n1866 i_yval[10] $abc$23348$new_n1879 +000 1 +001 1 +011 1 +110 1 +.names i_xval[11] $abc$23348$new_n1872 i_xval[10] i_xval[9] $abc$23348$new_n1880 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1881 +101 1 +110 1 +.names i_ce $abc$23348$new_n1883 yv[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19922 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1884 $abc$23348$new_n1881 $abc$23348$new_n1886 $abc$23348$new_n1875 i_yval[10] $abc$23348$new_n1883 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[10] $abc$23348$new_n1866 i_xval[10] $abc$23348$new_n1884 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$23348$new_n1885 +001 1 +010 1 +011 1 +100 1 +.names i_xval[10] $abc$23348$new_n1872 i_xval[9] $abc$23348$new_n1886 +000 1 +001 1 +011 1 +110 1 +.names i_ce $abc$23348$new_n1888 yv[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19924 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1889 $abc$23348$new_n1881 $abc$23348$new_n1890 $abc$23348$new_n1875 i_yval[9] $abc$23348$new_n1888 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[9] $abc$23348$new_n1867 i_xval[9] $abc$23348$new_n1889 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_xval[9] $abc$23348$new_n1872 $abc$23348$new_n1890 +00 1 +11 1 +.names i_ce $abc$23348$new_n1892 yv[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19926 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1893 $abc$23348$new_n1881 $abc$23348$new_n1895 $abc$23348$new_n1875 i_yval[8] $abc$23348$new_n1892 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1894 i_xval[8] $abc$23348$new_n1893 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[8] $abc$23348$new_n1868 i_yval[7] i_yval[6] i_yval[5] $abc$23348$new_n1894 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[8] $abc$23348$new_n1873 i_xval[7] i_xval[6] i_xval[5] $abc$23348$new_n1895 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$23348$new_n1899 $abc$23348$new_n1897 yv[0][9] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19928 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1898 i_xval[7] $abc$23348$new_n1897 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[7] $abc$23348$new_n1868 i_yval[6] i_yval[5] $abc$23348$new_n1898 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n1900 $abc$23348$new_n1881 $abc$23348$new_n1875 i_yval[7] $abc$23348$new_n1899 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names i_xval[7] $abc$23348$new_n1873 i_xval[6] i_xval[5] $abc$23348$new_n1900 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n1902 yv[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19930 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1903 $abc$23348$new_n1881 $abc$23348$new_n1905 $abc$23348$new_n1875 i_yval[6] $abc$23348$new_n1902 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n1904 i_xval[6] $abc$23348$new_n1903 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_yval[6] $abc$23348$new_n1868 i_yval[5] $abc$23348$new_n1904 +000 1 +001 1 +011 1 +110 1 +.names i_xval[6] $abc$23348$new_n1873 i_xval[5] $abc$23348$new_n1905 +000 1 +001 1 +011 1 +110 1 +.names i_ce yv[0][7] $abc$23348$new_n1909 $abc$23348$new_n1908 $abc$23348$new_n1907 $abc$23348$auto$rtlil.cc:2693:MuxGate$19932 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[5] $abc$23348$new_n1868 i_xval[5] $abc$23348$new_n1907 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n1881 i_xval[5] $abc$23348$new_n1873 $abc$23348$new_n1908 +100 1 +111 1 +.names i_yval[5] $abc$23348$new_n1875 $abc$23348$new_n1909 +11 1 +.names i_ce $abc$23348$new_n1911 yv[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19934 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1912 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1914 i_xval[4] $abc$23348$new_n1911 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1913 $abc$23348$new_n1881 i_yval[4] $abc$23348$new_n1875 $abc$23348$new_n1912 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1913 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1914 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_ce $abc$23348$new_n1916 yv[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19936 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1917 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1919 i_xval[3] $abc$23348$new_n1916 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1918 $abc$23348$new_n1881 i_yval[3] $abc$23348$new_n1875 $abc$23348$new_n1917 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1918 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1919 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_ce $abc$23348$new_n1921 yv[0][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19938 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1922 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1924 i_xval[2] $abc$23348$new_n1921 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1923 $abc$23348$new_n1881 i_yval[2] $abc$23348$new_n1875 $abc$23348$new_n1922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[2] i_xval[1] i_xval[0] $abc$23348$new_n1923 +001 1 +010 1 +011 1 +100 1 +.names i_yval[2] i_yval[1] i_yval[0] $abc$23348$new_n1924 +001 1 +010 1 +011 1 +100 1 +.names i_ce yv[0][3] $abc$23348$new_n1927 $abc$23348$new_n1926 $abc$23348$auto$rtlil.cc:2693:MuxGate$19940 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[1] i_yval[0] i_xval[1] $abc$23348$new_n1926 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n1881 i_xval[1] i_xval[0] i_yval[1] $abc$23348$new_n1875 $abc$23348$new_n1927 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1929 yv[0][2] i_yval[0] i_xval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19942 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$23348$new_n1875 $abc$23348$new_n1869 $abc$23348$new_n1929 +01 1 +10 1 +11 1 +.names yv[0][1] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19944 +10 1 +.names yv[0][0] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19946 +10 1 +.names $abc$23348$new_n1935 $abc$23348$new_n1933 xv[0][14] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19948 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n1934 $abc$23348$new_n1933 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_xval[12] $abc$23348$new_n1871 $abc$23348$new_n1934 +01 1 +10 1 +.names i_ce i_yval[12] $abc$23348$new_n1881 i_xval[12] $abc$23348$new_n1875 $abc$23348$new_n1935 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n1937 xv[0][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$19950 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1938 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1879 $abc$23348$new_n1880 $abc$23348$new_n1937 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[11] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[11] $abc$23348$new_n1938 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1940 xv[0][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$19952 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1941 i_yval[10] $abc$23348$new_n1881 i_xval[10] $abc$23348$new_n1875 $abc$23348$new_n1940 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[10] $abc$23348$new_n1866 $abc$23348$new_n1886 $abc$23348$new_n1941 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n1943 xv[0][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19954 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1944 i_yval[9] $abc$23348$new_n1881 i_xval[9] $abc$23348$new_n1875 $abc$23348$new_n1943 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 i_yval[9] $abc$23348$new_n1867 $abc$23348$new_n1890 $abc$23348$new_n1944 +10000 1 +10001 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n1946 xv[0][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19956 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1947 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1894 $abc$23348$new_n1895 $abc$23348$new_n1946 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[8] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[8] $abc$23348$new_n1947 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1949 xv[0][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19958 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1950 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1898 $abc$23348$new_n1900 $abc$23348$new_n1949 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[7] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[7] $abc$23348$new_n1950 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1952 xv[0][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19960 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1953 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1904 $abc$23348$new_n1905 $abc$23348$new_n1952 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_yval[6] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[6] $abc$23348$new_n1953 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1956 xv[0][7] $abc$23348$new_n1885 $abc$23348$new_n1955 $abc$23348$auto$rtlil.cc:2693:MuxGate$19962 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$23348$new_n1869 i_xval[5] $abc$23348$new_n1873 i_yval[5] $abc$23348$new_n1868 $abc$23348$new_n1955 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[5] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[5] $abc$23348$new_n1956 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1958 xv[0][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19964 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1959 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1913 $abc$23348$new_n1914 $abc$23348$new_n1958 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[4] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[4] $abc$23348$new_n1959 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1961 xv[0][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19966 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n1962 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n1918 $abc$23348$new_n1919 $abc$23348$new_n1961 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[3] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[3] $abc$23348$new_n1962 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1965 xv[0][4] $abc$23348$new_n1885 $abc$23348$new_n1964 $abc$23348$auto$rtlil.cc:2693:MuxGate$19968 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$23348$new_n1869 $abc$23348$new_n1923 $abc$23348$new_n1924 $abc$23348$new_n1964 +000 1 +010 1 +100 1 +101 1 +.names i_yval[2] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[2] $abc$23348$new_n1965 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[1] $abc$23348$new_n1881 $abc$23348$new_n1875 i_xval[1] $abc$23348$new_n1969 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$23348$new_n1929 xv[0][2] i_xval[0] i_yval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$19972 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[0][1] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19974 +10 1 +.names xv[0][0] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$19976 +10 1 +.names i_ce yv[16][14] yv[16][13] $abc$23348$new_n1974 o_yval[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$19978 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[16][11] yv[16][12] $abc$23348$new_n1975 $abc$23348$new_n1974 +111 1 +.names yv[16][7] yv[16][8] yv[16][9] yv[16][10] $abc$23348$new_n1976 $abc$23348$new_n1975 +11111 1 +.names yv[16][2] yv[16][3] yv[16][4] yv[16][5] yv[16][6] $abc$23348$new_n1976 +11111 1 +.names i_ce yv[16][13] $abc$23348$new_n1974 o_yval[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$19980 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[16][12] yv[16][11] $abc$23348$new_n1975 o_yval[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$19982 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[16][11] $abc$23348$new_n1975 o_yval[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$19984 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n1981 o_yval[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$19986 +001 1 +011 1 +110 1 +111 1 +.names yv[16][10] yv[16][7] yv[16][8] yv[16][9] $abc$23348$new_n1976 $abc$23348$new_n1981 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1983 o_yval[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$19988 +001 1 +011 1 +110 1 +111 1 +.names yv[16][9] yv[16][7] yv[16][8] $abc$23348$new_n1976 $abc$23348$new_n1983 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[16][8] yv[16][7] $abc$23348$new_n1976 o_yval[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$19990 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[16][7] $abc$23348$new_n1976 o_yval[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$19992 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n1987 o_yval[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$19994 +001 1 +011 1 +110 1 +111 1 +.names yv[16][6] yv[16][2] yv[16][3] yv[16][4] yv[16][5] $abc$23348$new_n1987 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1989 o_yval[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$19996 +001 1 +011 1 +110 1 +111 1 +.names yv[16][5] yv[16][2] yv[16][3] yv[16][4] $abc$23348$new_n1989 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[16][4] yv[16][2] yv[16][3] o_yval[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$19998 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n1992 o_yval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20000 +001 1 +011 1 +110 1 +111 1 +.names yv[16][2] yv[16][3] yv[16][1] yv[16][0] $abc$23348$new_n1992 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce xv[16][14] xv[16][13] $abc$23348$new_n1994 o_xval[11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20002 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][11] xv[16][12] $abc$23348$new_n1995 $abc$23348$new_n1994 +111 1 +.names xv[16][7] xv[16][8] xv[16][9] xv[16][10] $abc$23348$new_n1996 $abc$23348$new_n1995 +11111 1 +.names xv[16][2] xv[16][3] xv[16][4] xv[16][5] xv[16][6] $abc$23348$new_n1996 +11111 1 +.names i_ce xv[16][13] $abc$23348$new_n1994 o_xval[10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20004 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][12] xv[16][11] $abc$23348$new_n1995 o_xval[9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20006 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[16][11] $abc$23348$new_n1995 o_xval[8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20008 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2001 o_xval[7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20010 +001 1 +011 1 +110 1 +111 1 +.names xv[16][10] xv[16][7] xv[16][8] xv[16][9] $abc$23348$new_n1996 $abc$23348$new_n2001 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2003 o_xval[6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20012 +001 1 +011 1 +110 1 +111 1 +.names xv[16][9] xv[16][7] xv[16][8] $abc$23348$new_n1996 $abc$23348$new_n2003 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[16][8] xv[16][7] $abc$23348$new_n1996 o_xval[5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20014 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[16][7] $abc$23348$new_n1996 o_xval[4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20016 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2007 o_xval[3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20018 +001 1 +011 1 +110 1 +111 1 +.names xv[16][6] xv[16][2] xv[16][3] xv[16][4] xv[16][5] $abc$23348$new_n2007 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2009 o_xval[2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20020 +001 1 +011 1 +110 1 +111 1 +.names xv[16][5] xv[16][2] xv[16][3] xv[16][4] $abc$23348$new_n2009 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[16][4] xv[16][2] xv[16][3] o_xval[1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20022 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2012 o_xval[0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20024 +001 1 +011 1 +110 1 +111 1 +.names xv[16][2] xv[16][3] xv[16][1] xv[16][0] $abc$23348$new_n2012 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce ph[0][18] $abc$23348$new_n2019 $abc$23348$new_n2014 ph[1][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20026 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2015 ph[0][17] ph[0][19] $abc$23348$new_n2014 +000 1 +010 1 +011 1 +.names ph[0][19] ph[0][16] $abc$23348$new_n2016 ph[0][15] ph[0][14] $abc$23348$new_n2015 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names ph[0][13] ph[0][12] $abc$23348$new_n2017 ph[0][11] $abc$23348$new_n2016 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2018 ph[0][10] $abc$23348$new_n2017 +10 1 +.names ph[0][9] ph[0][7] ph[0][8] ph[0][6] $abc$23348$new_n2018 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[0][19] ph[0][17] ph[0][16] $abc$23348$new_n2020 $abc$23348$new_n2019 +0000 1 +0001 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[0][14] ph[0][15] $abc$23348$new_n2021 $abc$23348$new_n2020 +000 1 +.names ph[0][13] ph[0][12] ph[0][11] $abc$23348$new_n2022 $abc$23348$new_n2021 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[0][10] $abc$23348$new_n2023 $abc$23348$new_n2022 +11 1 +.names ph[0][9] ph[0][7] ph[0][8] ph[0][6] $abc$23348$new_n2023 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2025 ph[1][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20028 +001 1 +011 1 +100 1 +101 1 +.names ph[0][17] $abc$23348$new_n2015 ph[0][16] ph[0][19] $abc$23348$new_n2020 $abc$23348$new_n2025 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names i_ce $abc$23348$new_n2027 ph[1][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20030 +001 1 +011 1 +110 1 +111 1 +.names ph[0][16] ph[0][14] ph[0][15] $abc$23348$new_n2029 $abc$23348$new_n2028 $abc$23348$new_n2027 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2016 $abc$23348$new_n2028 +10 1 +.names ph[0][19] $abc$23348$new_n2021 $abc$23348$new_n2029 +00 1 +.names i_ce $abc$23348$new_n2031 ph[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20032 +001 1 +011 1 +110 1 +111 1 +.names ph[0][15] ph[0][14] $abc$23348$new_n2029 $abc$23348$new_n2028 $abc$23348$new_n2031 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[0][14] $abc$23348$new_n2029 $abc$23348$new_n2028 ph[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20034 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2034 ph[0][13] ph[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20036 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[0][19] ph[0][12] ph[0][11] $abc$23348$new_n2017 $abc$23348$new_n2022 $abc$23348$new_n2034 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2036 ph[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20038 +001 1 +011 1 +100 1 +101 1 +.names ph[0][10] ph[0][12] ph[0][11] $abc$23348$new_n2038 $abc$23348$new_n2037 $abc$23348$new_n2036 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] $abc$23348$new_n2018 $abc$23348$new_n2037 +11 1 +.names $abc$23348$new_n2023 ph[0][19] $abc$23348$new_n2038 +10 1 +.names i_ce $abc$23348$new_n2040 ph[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20040 +001 1 +011 1 +100 1 +101 1 +.names ph[0][10] ph[0][11] $abc$23348$new_n2038 $abc$23348$new_n2037 $abc$23348$new_n2040 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[0][10] $abc$23348$new_n2038 $abc$23348$new_n2037 ph[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20042 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2043 ph[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20044 +001 1 +011 1 +110 1 +111 1 +.names ph[0][9] ph[0][19] ph[0][6] ph[0][7] ph[0][8] $abc$23348$new_n2043 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11111 1 +.names i_ce $abc$23348$new_n2045 ph[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20046 +001 1 +011 1 +100 1 +101 1 +.names ph[0][8] ph[0][19] ph[0][6] ph[0][7] $abc$23348$new_n2045 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[0][19] ph[0][6] ph[0][7] ph[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20048 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[0][6] ph[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20050 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[0][5] ph[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20052 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][4] ph[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20054 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][3] ph[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20056 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][2] ph[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20058 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][1] ph[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20060 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[0][0] ph[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20062 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][15] yv[0][14] $abc$23348$new_n2055 yv[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20064 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2056 $abc$23348$new_n2063 $abc$23348$new_n2055 +000 1 +001 1 +101 1 +111 1 +.names xv[0][13] yv[0][12] xv[0][14] yv[0][13] $abc$23348$new_n2057 $abc$23348$new_n2056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][11] yv[0][10] xv[0][12] yv[0][11] $abc$23348$new_n2058 $abc$23348$new_n2057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][9] yv[0][8] xv[0][10] yv[0][9] $abc$23348$new_n2059 $abc$23348$new_n2058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][7] yv[0][6] xv[0][8] yv[0][7] $abc$23348$new_n2060 $abc$23348$new_n2059 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][5] yv[0][4] xv[0][6] yv[0][5] $abc$23348$new_n2061 $abc$23348$new_n2060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][3] yv[0][2] xv[0][4] yv[0][3] $abc$23348$new_n2062 $abc$23348$new_n2061 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][1] yv[0][0] xv[0][2] yv[0][1] $abc$23348$new_n2062 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[0][13] xv[0][14] yv[0][12] yv[0][13] $abc$23348$new_n2064 $abc$23348$new_n2063 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][11] xv[0][12] yv[0][10] yv[0][11] $abc$23348$new_n2065 $abc$23348$new_n2064 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][9] xv[0][10] yv[0][8] yv[0][9] $abc$23348$new_n2066 $abc$23348$new_n2065 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][7] xv[0][8] yv[0][6] yv[0][7] $abc$23348$new_n2067 $abc$23348$new_n2066 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][5] xv[0][6] yv[0][4] yv[0][5] $abc$23348$new_n2068 $abc$23348$new_n2067 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][3] xv[0][4] yv[0][2] yv[0][3] $abc$23348$new_n2069 $abc$23348$new_n2068 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[0][1] xv[0][2] yv[0][0] yv[0][1] $abc$23348$new_n2069 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2075 yv[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20068 +001 1 +011 1 +110 1 +111 1 +.names ph[0][19] xv[0][13] yv[0][12] $abc$23348$new_n2064 $abc$23348$new_n2057 $abc$23348$new_n2075 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2081 yv[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20072 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][11] yv[0][10] $abc$23348$new_n2065 $abc$23348$new_n2058 $abc$23348$new_n2081 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][10] yv[0][9] $abc$23348$new_n2083 yv[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20074 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][9] yv[0][8] $abc$23348$new_n2066 $abc$23348$new_n2059 $abc$23348$new_n2083 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2085 yv[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20076 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][9] yv[0][8] $abc$23348$new_n2066 $abc$23348$new_n2059 $abc$23348$new_n2085 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][8] yv[0][7] $abc$23348$new_n2087 yv[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20078 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][7] yv[0][6] $abc$23348$new_n2067 $abc$23348$new_n2060 $abc$23348$new_n2087 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2089 yv[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20080 +001 1 +011 1 +100 1 +101 1 +.names ph[0][19] xv[0][7] yv[0][6] $abc$23348$new_n2067 $abc$23348$new_n2060 $abc$23348$new_n2089 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[0][6] yv[0][5] $abc$23348$new_n2091 yv[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20082 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][5] yv[0][4] $abc$23348$new_n2068 $abc$23348$new_n2061 $abc$23348$new_n2091 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2093 yv[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20084 +001 1 +011 1 +110 1 +111 1 +.names ph[0][19] xv[0][5] yv[0][4] $abc$23348$new_n2068 $abc$23348$new_n2061 $abc$23348$new_n2093 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[0][4] yv[0][3] $abc$23348$new_n2095 yv[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20086 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] yv[0][2] xv[0][3] $abc$23348$new_n2069 $abc$23348$new_n2062 $abc$23348$new_n2095 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[0][3] yv[0][2] $abc$23348$new_n2097 yv[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20088 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2062 $abc$23348$new_n2069 $abc$23348$new_n2097 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$23348$new_n2099 yv[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20090 +001 1 +011 1 +110 1 +111 1 +.names xv[0][2] yv[0][1] ph[0][19] yv[0][0] xv[0][1] $abc$23348$new_n2099 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[0][1] yv[0][0] yv[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20092 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[0][15] xv[0][14] $abc$23348$new_n2102 xv[1][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20094 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] $abc$23348$new_n2103 $abc$23348$new_n2110 $abc$23348$new_n2102 +001 1 +011 1 +100 1 +101 1 +.names xv[0][12] yv[0][13] xv[0][13] yv[0][14] $abc$23348$new_n2104 $abc$23348$new_n2103 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][10] yv[0][11] xv[0][11] yv[0][12] $abc$23348$new_n2105 $abc$23348$new_n2104 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][8] yv[0][9] xv[0][9] yv[0][10] $abc$23348$new_n2106 $abc$23348$new_n2105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][6] yv[0][7] xv[0][7] yv[0][8] $abc$23348$new_n2107 $abc$23348$new_n2106 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][4] yv[0][5] xv[0][5] yv[0][6] $abc$23348$new_n2108 $abc$23348$new_n2107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[0][2] yv[0][3] xv[0][3] yv[0][4] $abc$23348$new_n2109 $abc$23348$new_n2108 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][0] yv[0][1] xv[0][1] yv[0][2] $abc$23348$new_n2109 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[0][13] xv[0][12] xv[0][13] yv[0][14] $abc$23348$new_n2111 $abc$23348$new_n2110 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][10] xv[0][11] yv[0][11] yv[0][12] $abc$23348$new_n2112 $abc$23348$new_n2111 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][9] xv[0][8] xv[0][9] yv[0][10] $abc$23348$new_n2113 $abc$23348$new_n2112 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][6] xv[0][7] yv[0][7] yv[0][8] $abc$23348$new_n2114 $abc$23348$new_n2113 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][5] xv[0][4] xv[0][5] yv[0][6] $abc$23348$new_n2115 $abc$23348$new_n2114 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][3] xv[0][2] xv[0][3] yv[0][4] $abc$23348$new_n2116 $abc$23348$new_n2115 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][1] xv[0][0] xv[0][1] yv[0][2] $abc$23348$new_n2116 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names i_ce xv[0][13] yv[0][14] $abc$23348$new_n2118 xv[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20096 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][12] yv[0][13] $abc$23348$new_n2111 $abc$23348$new_n2104 $abc$23348$new_n2118 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2120 xv[1][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20098 +001 1 +011 1 +100 1 +101 1 +.names xv[0][12] yv[0][13] ph[0][19] $abc$23348$new_n2111 $abc$23348$new_n2104 $abc$23348$new_n2120 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][11] yv[0][12] $abc$23348$new_n2122 xv[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20100 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][10] yv[0][11] $abc$23348$new_n2112 $abc$23348$new_n2105 $abc$23348$new_n2122 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2124 xv[1][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20102 +001 1 +011 1 +110 1 +111 1 +.names xv[0][10] yv[0][11] ph[0][19] $abc$23348$new_n2112 $abc$23348$new_n2105 $abc$23348$new_n2124 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][9] yv[0][10] $abc$23348$new_n2126 xv[1][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20104 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][8] yv[0][9] $abc$23348$new_n2113 $abc$23348$new_n2106 $abc$23348$new_n2126 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2128 xv[1][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20106 +001 1 +011 1 +100 1 +101 1 +.names xv[0][8] yv[0][9] ph[0][19] $abc$23348$new_n2113 $abc$23348$new_n2106 $abc$23348$new_n2128 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][7] yv[0][8] $abc$23348$new_n2130 xv[1][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20108 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][6] yv[0][7] $abc$23348$new_n2114 $abc$23348$new_n2107 $abc$23348$new_n2130 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2132 xv[1][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20110 +001 1 +011 1 +110 1 +111 1 +.names xv[0][6] yv[0][7] ph[0][19] $abc$23348$new_n2114 $abc$23348$new_n2107 $abc$23348$new_n2132 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][5] yv[0][6] $abc$23348$new_n2134 xv[1][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20112 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][4] yv[0][5] $abc$23348$new_n2115 $abc$23348$new_n2108 $abc$23348$new_n2134 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n2136 xv[1][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20114 +001 1 +011 1 +110 1 +111 1 +.names xv[0][4] yv[0][5] ph[0][19] $abc$23348$new_n2115 $abc$23348$new_n2108 $abc$23348$new_n2136 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][3] yv[0][4] $abc$23348$new_n2138 xv[1][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20116 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][2] yv[0][3] $abc$23348$new_n2116 $abc$23348$new_n2109 $abc$23348$new_n2138 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][2] yv[0][3] $abc$23348$new_n2140 xv[1][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20118 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] $abc$23348$new_n2109 $abc$23348$new_n2116 $abc$23348$new_n2140 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2142 xv[1][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20120 +001 1 +011 1 +110 1 +111 1 +.names xv[0][1] yv[0][2] ph[0][19] xv[0][0] yv[0][1] $abc$23348$new_n2142 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[0][0] yv[0][1] xv[1][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20122 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2145 ph[2][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20124 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][18] ph[1][17] $abc$23348$new_n2151 $abc$23348$new_n2146 $abc$23348$new_n2145 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[1][16] ph[1][15] ph[1][13] $abc$23348$new_n2147 $abc$23348$new_n2146 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[1][14] $abc$23348$new_n2148 $abc$23348$new_n2147 +10 1 +.names $abc$23348$new_n2150 ph[1][7] ph[1][6] $abc$23348$new_n2149 ph[1][5] $abc$23348$new_n2148 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +.names ph[1][4] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2149 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$23348$new_n2150 +00000 1 +.names ph[1][16] ph[1][15] $abc$23348$new_n2152 ph[1][13] $abc$23348$new_n2151 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names ph[1][14] $abc$23348$new_n2153 $abc$23348$new_n2152 +00 1 +.names ph[1][7] $abc$23348$new_n2155 ph[1][6] ph[1][5] $abc$23348$new_n2154 $abc$23348$new_n2153 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[1][4] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2154 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$23348$new_n2155 +11111 1 +.names i_ce $abc$23348$new_n2157 ph[2][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20126 +001 1 +011 1 +110 1 +111 1 +.names ph[1][17] ph[1][19] $abc$23348$new_n2151 $abc$23348$new_n2146 $abc$23348$new_n2157 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2159 ph[1][16] ph[2][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20128 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][19] ph[1][15] ph[1][13] $abc$23348$new_n2147 $abc$23348$new_n2152 $abc$23348$new_n2159 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names i_ce $abc$23348$new_n2161 ph[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20130 +001 1 +011 1 +110 1 +111 1 +.names ph[1][15] ph[1][13] ph[1][14] $abc$23348$new_n2163 $abc$23348$new_n2162 $abc$23348$new_n2161 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2153 $abc$23348$new_n2162 +00 1 +.names ph[1][19] $abc$23348$new_n2148 $abc$23348$new_n2163 +10 1 +.names i_ce $abc$23348$new_n2165 ph[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20132 +001 1 +011 1 +110 1 +111 1 +.names ph[1][13] ph[1][14] $abc$23348$new_n2163 $abc$23348$new_n2162 $abc$23348$new_n2165 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][13] $abc$23348$new_n2163 $abc$23348$new_n2162 ph[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20134 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2168 ph[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20136 +001 1 +011 1 +110 1 +111 1 +.names ph[1][11] ph[1][12] $abc$23348$new_n2172 $abc$23348$new_n2169 $abc$23348$new_n2168 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n2170 ph[1][8] ph[1][9] ph[1][10] $abc$23348$new_n2169 +1000 1 +.names $abc$23348$new_n2171 ph[1][7] $abc$23348$new_n2170 +10 1 +.names ph[1][19] ph[1][6] $abc$23348$new_n2149 ph[1][5] $abc$23348$new_n2171 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names ph[1][8] ph[1][9] ph[1][10] $abc$23348$new_n2173 $abc$23348$new_n2172 +1111 1 +.names ph[1][7] $abc$23348$new_n2174 $abc$23348$new_n2173 +11 1 +.names ph[1][19] ph[1][6] ph[1][5] $abc$23348$new_n2154 $abc$23348$new_n2174 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[1][11] $abc$23348$new_n2172 $abc$23348$new_n2169 ph[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20138 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2177 ph[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20140 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][10] ph[1][9] $abc$23348$new_n2173 $abc$23348$new_n2170 $abc$23348$new_n2177 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2179 ph[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20142 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][9] $abc$23348$new_n2173 $abc$23348$new_n2170 $abc$23348$new_n2179 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][8] $abc$23348$new_n2173 $abc$23348$new_n2170 ph[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20144 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[1][7] $abc$23348$new_n2174 $abc$23348$new_n2171 ph[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20146 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2183 ph[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20148 +001 1 +011 1 +110 1 +111 1 +.names ph[1][6] ph[1][5] $abc$23348$new_n2185 $abc$23348$new_n2184 $abc$23348$new_n2183 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$23348$new_n2154 ph[1][19] $abc$23348$new_n2184 +10 1 +.names ph[1][19] $abc$23348$new_n2149 $abc$23348$new_n2185 +11 1 +.names i_ce ph[1][5] $abc$23348$new_n2185 $abc$23348$new_n2184 ph[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20150 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2188 ph[1][4] ph[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20152 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][19] ph[1][2] ph[1][3] ph[1][0] ph[1][1] $abc$23348$new_n2188 +00000 1 +00001 1 +00010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2190 ph[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20154 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][3] ph[1][2] ph[1][0] ph[1][1] $abc$23348$new_n2190 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$23348$new_n2192 ph[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20156 +001 1 +011 1 +110 1 +111 1 +.names ph[1][2] ph[1][19] ph[1][0] ph[1][1] $abc$23348$new_n2192 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[1][19] ph[1][0] ph[1][1] ph[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20158 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[1][0] ph[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20160 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[1][15] yv[1][14] $abc$23348$new_n2196 yv[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2197 $abc$23348$new_n2204 $abc$23348$new_n2196 +000 1 +001 1 +101 1 +111 1 +.names xv[1][14] yv[1][12] xv[1][15] yv[1][13] $abc$23348$new_n2198 $abc$23348$new_n2197 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][10] xv[1][13] yv[1][11] $abc$23348$new_n2199 $abc$23348$new_n2198 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][8] xv[1][11] yv[1][9] $abc$23348$new_n2200 $abc$23348$new_n2199 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][6] xv[1][9] yv[1][7] $abc$23348$new_n2201 $abc$23348$new_n2200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][4] xv[1][7] yv[1][5] $abc$23348$new_n2202 $abc$23348$new_n2201 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][2] xv[1][5] yv[1][3] $abc$23348$new_n2203 $abc$23348$new_n2202 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][0] xv[1][3] yv[1][1] $abc$23348$new_n2203 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[1][14] xv[1][15] yv[1][12] yv[1][13] $abc$23348$new_n2205 $abc$23348$new_n2204 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][12] xv[1][13] yv[1][10] yv[1][11] $abc$23348$new_n2206 $abc$23348$new_n2205 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][10] xv[1][11] yv[1][8] yv[1][9] $abc$23348$new_n2207 $abc$23348$new_n2206 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][8] xv[1][9] yv[1][6] yv[1][7] $abc$23348$new_n2208 $abc$23348$new_n2207 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][6] xv[1][7] yv[1][4] yv[1][5] $abc$23348$new_n2209 $abc$23348$new_n2208 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][4] xv[1][5] yv[1][2] yv[1][3] $abc$23348$new_n2210 $abc$23348$new_n2209 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[1][2] xv[1][3] yv[1][0] yv[1][1] $abc$23348$new_n2210 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2216 yv[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20166 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][14] yv[1][12] $abc$23348$new_n2205 $abc$23348$new_n2198 $abc$23348$new_n2216 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2222 yv[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20170 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][12] yv[1][10] $abc$23348$new_n2206 $abc$23348$new_n2199 $abc$23348$new_n2222 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][11] yv[1][9] $abc$23348$new_n2224 yv[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20172 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][10] yv[1][8] $abc$23348$new_n2207 $abc$23348$new_n2200 $abc$23348$new_n2224 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2226 yv[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20174 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][10] yv[1][8] $abc$23348$new_n2207 $abc$23348$new_n2200 $abc$23348$new_n2226 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][9] yv[1][7] $abc$23348$new_n2228 yv[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20176 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][8] yv[1][6] $abc$23348$new_n2208 $abc$23348$new_n2201 $abc$23348$new_n2228 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][8] yv[1][6] $abc$23348$new_n2230 yv[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20178 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2201 $abc$23348$new_n2208 $abc$23348$new_n2230 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][7] yv[1][5] $abc$23348$new_n2232 yv[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20180 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][6] yv[1][4] $abc$23348$new_n2209 $abc$23348$new_n2202 $abc$23348$new_n2232 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][6] yv[1][4] $abc$23348$new_n2234 yv[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20182 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2202 $abc$23348$new_n2209 $abc$23348$new_n2234 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][5] yv[1][3] $abc$23348$new_n2236 yv[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20184 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][4] yv[1][2] $abc$23348$new_n2210 $abc$23348$new_n2203 $abc$23348$new_n2236 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][4] yv[1][2] $abc$23348$new_n2238 yv[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20186 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2203 $abc$23348$new_n2210 $abc$23348$new_n2238 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2240 yv[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20188 +001 1 +011 1 +110 1 +111 1 +.names xv[1][3] yv[1][1] ph[1][19] yv[1][0] xv[1][2] $abc$23348$new_n2240 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[1][2] yv[1][0] yv[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20190 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[1][15] xv[1][14] $abc$23348$new_n2243 xv[2][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20192 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2244 $abc$23348$new_n2251 $abc$23348$new_n2243 +000 1 +001 1 +101 1 +111 1 +.names yv[1][14] yv[1][15] xv[1][12] xv[1][13] $abc$23348$new_n2245 $abc$23348$new_n2244 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[1][10] xv[1][11] yv[1][12] yv[1][13] $abc$23348$new_n2246 $abc$23348$new_n2245 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][10] xv[1][8] xv[1][9] yv[1][11] $abc$23348$new_n2247 $abc$23348$new_n2246 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[1][6] xv[1][7] yv[1][8] yv[1][9] $abc$23348$new_n2248 $abc$23348$new_n2247 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][6] xv[1][4] xv[1][5] yv[1][7] $abc$23348$new_n2249 $abc$23348$new_n2248 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][4] xv[1][2] xv[1][3] yv[1][5] $abc$23348$new_n2250 $abc$23348$new_n2249 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][2] xv[1][0] xv[1][1] yv[1][3] $abc$23348$new_n2250 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[1][12] yv[1][14] yv[1][15] xv[1][13] $abc$23348$new_n2252 $abc$23348$new_n2251 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][12] xv[1][11] yv[1][13] $abc$23348$new_n2253 $abc$23348$new_n2252 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][10] xv[1][9] yv[1][11] $abc$23348$new_n2254 $abc$23348$new_n2253 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][8] xv[1][7] yv[1][9] $abc$23348$new_n2255 $abc$23348$new_n2254 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][6] xv[1][5] yv[1][7] $abc$23348$new_n2256 $abc$23348$new_n2255 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][4] xv[1][3] yv[1][5] $abc$23348$new_n2257 $abc$23348$new_n2256 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][0] yv[1][2] xv[1][1] yv[1][3] $abc$23348$new_n2257 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[1][15] xv[1][13] $abc$23348$new_n2259 xv[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20194 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][12] yv[1][14] $abc$23348$new_n2252 $abc$23348$new_n2245 $abc$23348$new_n2259 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2261 xv[2][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20196 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][12] yv[1][14] $abc$23348$new_n2252 $abc$23348$new_n2245 $abc$23348$new_n2261 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][11] yv[1][13] $abc$23348$new_n2263 xv[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20198 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][10] yv[1][12] $abc$23348$new_n2253 $abc$23348$new_n2246 $abc$23348$new_n2263 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2265 xv[2][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20200 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][10] yv[1][12] $abc$23348$new_n2253 $abc$23348$new_n2246 $abc$23348$new_n2265 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][9] yv[1][11] $abc$23348$new_n2267 xv[2][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20202 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][8] yv[1][10] $abc$23348$new_n2254 $abc$23348$new_n2247 $abc$23348$new_n2267 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][8] yv[1][10] $abc$23348$new_n2269 xv[2][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20204 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] $abc$23348$new_n2247 $abc$23348$new_n2254 $abc$23348$new_n2269 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[1][7] yv[1][9] $abc$23348$new_n2271 xv[2][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20206 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][6] yv[1][8] $abc$23348$new_n2255 $abc$23348$new_n2248 $abc$23348$new_n2271 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2273 xv[2][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20208 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] xv[1][6] yv[1][8] $abc$23348$new_n2255 $abc$23348$new_n2248 $abc$23348$new_n2273 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2279 xv[2][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20212 +001 1 +011 1 +100 1 +101 1 +.names ph[1][19] xv[1][4] yv[1][6] $abc$23348$new_n2256 $abc$23348$new_n2249 $abc$23348$new_n2279 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][3] yv[1][5] $abc$23348$new_n2281 xv[2][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20214 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][2] yv[1][4] $abc$23348$new_n2257 $abc$23348$new_n2250 $abc$23348$new_n2281 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][2] yv[1][4] $abc$23348$new_n2283 xv[2][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20216 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] $abc$23348$new_n2250 $abc$23348$new_n2257 $abc$23348$new_n2283 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2285 xv[2][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20218 +001 1 +011 1 +110 1 +111 1 +.names xv[1][1] yv[1][3] ph[1][19] xv[1][0] yv[1][2] $abc$23348$new_n2285 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[1][0] yv[1][2] xv[2][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20220 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2288 ph[3][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20222 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][18] ph[2][17] $abc$23348$new_n2294 $abc$23348$new_n2289 $abc$23348$new_n2288 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[2][15] ph[2][16] ph[2][14] ph[2][13] $abc$23348$new_n2290 $abc$23348$new_n2289 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][12] ph[2][11] $abc$23348$new_n2291 ph[2][10] $abc$23348$new_n2290 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[2][9] ph[2][8] ph[2][7] $abc$23348$new_n2292 ph[2][6] $abc$23348$new_n2291 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][5] ph[2][4] ph[2][3] $abc$23348$new_n2293 ph[2][2] $abc$23348$new_n2292 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][0] ph[2][1] $abc$23348$new_n2293 +11 1 +.names ph[2][15] ph[2][16] ph[2][14] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2294 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[2][12] $abc$23348$new_n2296 ph[2][10] ph[2][11] $abc$23348$new_n2295 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[2][9] ph[2][8] $abc$23348$new_n2297 ph[2][6] ph[2][7] $abc$23348$new_n2296 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][5] ph[2][4] $abc$23348$new_n2298 ph[2][2] ph[2][3] $abc$23348$new_n2297 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][0] ph[2][1] $abc$23348$new_n2298 +00 1 +.names i_ce $abc$23348$new_n2300 ph[3][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20224 +001 1 +011 1 +100 1 +101 1 +.names ph[2][17] ph[2][19] $abc$23348$new_n2294 $abc$23348$new_n2289 $abc$23348$new_n2300 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$23348$new_n2302 ph[3][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20226 +001 1 +011 1 +110 1 +111 1 +.names ph[2][15] ph[2][16] $abc$23348$new_n2304 $abc$23348$new_n2303 $abc$23348$new_n2302 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] ph[2][14] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2303 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[2][19] ph[2][14] ph[2][13] $abc$23348$new_n2290 $abc$23348$new_n2304 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[2][15] $abc$23348$new_n2304 $abc$23348$new_n2303 ph[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20228 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2307 ph[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20230 +001 1 +011 1 +110 1 +111 1 +.names ph[2][14] ph[2][19] ph[2][13] $abc$23348$new_n2295 $abc$23348$new_n2290 $abc$23348$new_n2307 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2309 ph[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20232 +001 1 +011 1 +100 1 +101 1 +.names ph[2][13] ph[2][19] $abc$23348$new_n2295 $abc$23348$new_n2290 $abc$23348$new_n2309 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2311 ph[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20234 +001 1 +011 1 +100 1 +101 1 +.names ph[2][10] ph[2][12] ph[2][11] $abc$23348$new_n2314 $abc$23348$new_n2312 $abc$23348$new_n2311 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2313 ph[2][9] $abc$23348$new_n2312 +10 1 +.names ph[2][19] ph[2][8] $abc$23348$new_n2297 ph[2][6] ph[2][7] $abc$23348$new_n2313 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][9] $abc$23348$new_n2315 $abc$23348$new_n2314 +11 1 +.names ph[2][19] ph[2][8] ph[2][7] $abc$23348$new_n2292 ph[2][6] $abc$23348$new_n2315 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2317 ph[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20236 +001 1 +011 1 +110 1 +111 1 +.names ph[2][10] ph[2][11] $abc$23348$new_n2314 $abc$23348$new_n2312 $abc$23348$new_n2317 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[2][10] $abc$23348$new_n2314 $abc$23348$new_n2312 ph[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20238 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][9] $abc$23348$new_n2315 $abc$23348$new_n2313 ph[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20240 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2321 ph[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20242 +001 1 +011 1 +100 1 +101 1 +.names ph[2][6] ph[2][8] ph[2][7] $abc$23348$new_n2324 $abc$23348$new_n2322 $abc$23348$new_n2321 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2323 ph[2][5] $abc$23348$new_n2322 +10 1 +.names ph[2][19] ph[2][4] $abc$23348$new_n2298 ph[2][2] ph[2][3] $abc$23348$new_n2323 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names ph[2][5] $abc$23348$new_n2325 $abc$23348$new_n2324 +11 1 +.names ph[2][19] ph[2][4] ph[2][3] $abc$23348$new_n2293 ph[2][2] $abc$23348$new_n2325 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2327 ph[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20244 +001 1 +011 1 +110 1 +111 1 +.names ph[2][6] ph[2][7] $abc$23348$new_n2324 $abc$23348$new_n2322 $abc$23348$new_n2327 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[2][6] $abc$23348$new_n2324 $abc$23348$new_n2322 ph[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20246 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][5] $abc$23348$new_n2325 $abc$23348$new_n2323 ph[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20248 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][4] $abc$23348$new_n2331 ph[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20250 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] ph[2][0] ph[2][1] ph[2][2] ph[2][3] $abc$23348$new_n2331 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2333 ph[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20252 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][3] ph[2][0] ph[2][1] ph[2][2] $abc$23348$new_n2333 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n2335 ph[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20254 +001 1 +011 1 +100 1 +101 1 +.names ph[2][2] ph[2][19] ph[2][0] ph[2][1] $abc$23348$new_n2335 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[2][19] ph[2][0] ph[2][1] ph[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20256 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[2][0] ph[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20258 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[2][15] yv[2][14] $abc$23348$new_n2339 yv[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20260 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2340 $abc$23348$new_n2347 $abc$23348$new_n2339 +000 1 +001 1 +101 1 +111 1 +.names xv[2][15] $abc$23348$new_n2341 yv[2][12] yv[2][13] $abc$23348$new_n2340 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[2][13] yv[2][10] xv[2][14] yv[2][11] $abc$23348$new_n2342 $abc$23348$new_n2341 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][11] yv[2][8] xv[2][12] yv[2][9] $abc$23348$new_n2343 $abc$23348$new_n2342 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][9] yv[2][6] xv[2][10] yv[2][7] $abc$23348$new_n2344 $abc$23348$new_n2343 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][7] yv[2][4] xv[2][8] yv[2][5] $abc$23348$new_n2345 $abc$23348$new_n2344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][5] yv[2][2] xv[2][6] yv[2][3] $abc$23348$new_n2346 $abc$23348$new_n2345 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][3] yv[2][0] xv[2][4] yv[2][1] $abc$23348$new_n2346 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[2][15] $abc$23348$new_n2348 yv[2][12] yv[2][13] $abc$23348$new_n2347 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[2][13] xv[2][14] yv[2][10] yv[2][11] $abc$23348$new_n2349 $abc$23348$new_n2348 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][11] xv[2][12] yv[2][8] yv[2][9] $abc$23348$new_n2350 $abc$23348$new_n2349 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][9] xv[2][10] yv[2][6] yv[2][7] $abc$23348$new_n2351 $abc$23348$new_n2350 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][7] xv[2][8] yv[2][4] yv[2][5] $abc$23348$new_n2352 $abc$23348$new_n2351 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][5] xv[2][6] yv[2][2] yv[2][3] $abc$23348$new_n2353 $abc$23348$new_n2352 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[2][3] xv[2][4] yv[2][0] yv[2][1] $abc$23348$new_n2353 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce $abc$23348$new_n2359 yv[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20264 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][15] yv[2][12] $abc$23348$new_n2348 $abc$23348$new_n2341 $abc$23348$new_n2359 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][14] yv[2][11] $abc$23348$new_n2361 yv[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20266 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] yv[2][10] xv[2][13] $abc$23348$new_n2349 $abc$23348$new_n2342 $abc$23348$new_n2361 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][13] yv[2][10] $abc$23348$new_n2363 yv[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20268 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2342 $abc$23348$new_n2349 $abc$23348$new_n2363 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][12] yv[2][9] $abc$23348$new_n2365 yv[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20270 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][11] yv[2][8] $abc$23348$new_n2350 $abc$23348$new_n2343 $abc$23348$new_n2365 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2367 yv[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20272 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][11] yv[2][8] $abc$23348$new_n2350 $abc$23348$new_n2343 $abc$23348$new_n2367 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][10] yv[2][7] $abc$23348$new_n2369 yv[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20274 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][9] yv[2][6] $abc$23348$new_n2351 $abc$23348$new_n2344 $abc$23348$new_n2369 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][9] yv[2][6] $abc$23348$new_n2371 yv[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20276 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2344 $abc$23348$new_n2351 $abc$23348$new_n2371 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][8] yv[2][5] $abc$23348$new_n2373 yv[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20278 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][7] yv[2][4] $abc$23348$new_n2352 $abc$23348$new_n2345 $abc$23348$new_n2373 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][7] yv[2][4] $abc$23348$new_n2375 yv[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20280 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] $abc$23348$new_n2345 $abc$23348$new_n2352 $abc$23348$new_n2375 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[2][6] yv[2][3] $abc$23348$new_n2377 yv[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20282 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] yv[2][2] xv[2][5] $abc$23348$new_n2353 $abc$23348$new_n2346 $abc$23348$new_n2377 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][5] yv[2][2] $abc$23348$new_n2379 yv[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20284 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2346 $abc$23348$new_n2353 $abc$23348$new_n2379 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2381 yv[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20286 +001 1 +011 1 +110 1 +111 1 +.names xv[2][4] yv[2][1] ph[2][19] yv[2][0] xv[2][3] $abc$23348$new_n2381 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[2][3] yv[2][0] yv[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20288 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[2][15] xv[2][14] $abc$23348$new_n2384 xv[3][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20290 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2385 $abc$23348$new_n2392 $abc$23348$new_n2384 +000 1 +001 1 +101 1 +111 1 +.names yv[2][15] xv[2][12] xv[2][13] $abc$23348$new_n2386 $abc$23348$new_n2385 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[2][10] xv[2][11] yv[2][13] yv[2][14] $abc$23348$new_n2387 $abc$23348$new_n2386 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][11] xv[2][8] xv[2][9] yv[2][12] $abc$23348$new_n2388 $abc$23348$new_n2387 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[2][6] xv[2][7] yv[2][9] yv[2][10] $abc$23348$new_n2389 $abc$23348$new_n2388 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][7] xv[2][4] xv[2][5] yv[2][8] $abc$23348$new_n2390 $abc$23348$new_n2389 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][5] xv[2][2] xv[2][3] yv[2][6] $abc$23348$new_n2391 $abc$23348$new_n2390 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][3] xv[2][0] xv[2][1] yv[2][4] $abc$23348$new_n2391 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[2][15] $abc$23348$new_n2393 xv[2][12] xv[2][13] $abc$23348$new_n2392 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[2][10] yv[2][13] xv[2][11] yv[2][14] $abc$23348$new_n2394 $abc$23348$new_n2393 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][8] yv[2][11] xv[2][9] yv[2][12] $abc$23348$new_n2395 $abc$23348$new_n2394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][6] yv[2][9] xv[2][7] yv[2][10] $abc$23348$new_n2396 $abc$23348$new_n2395 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][4] yv[2][7] xv[2][5] yv[2][8] $abc$23348$new_n2397 $abc$23348$new_n2396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][2] yv[2][5] xv[2][3] yv[2][6] $abc$23348$new_n2398 $abc$23348$new_n2397 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][0] yv[2][3] xv[2][1] yv[2][4] $abc$23348$new_n2398 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[2][15] xv[2][13] $abc$23348$new_n2400 xv[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20292 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] yv[2][15] xv[2][12] $abc$23348$new_n2393 $abc$23348$new_n2386 $abc$23348$new_n2400 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2402 xv[3][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20294 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] yv[2][15] xv[2][12] $abc$23348$new_n2393 $abc$23348$new_n2386 $abc$23348$new_n2402 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][11] yv[2][14] $abc$23348$new_n2404 xv[3][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20296 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][10] yv[2][13] $abc$23348$new_n2394 $abc$23348$new_n2387 $abc$23348$new_n2404 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2406 xv[3][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20298 +001 1 +011 1 +100 1 +101 1 +.names ph[2][19] xv[2][10] yv[2][13] $abc$23348$new_n2394 $abc$23348$new_n2387 $abc$23348$new_n2406 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2412 xv[3][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20302 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][8] yv[2][11] $abc$23348$new_n2395 $abc$23348$new_n2388 $abc$23348$new_n2412 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][7] yv[2][10] $abc$23348$new_n2414 xv[3][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20304 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][6] yv[2][9] $abc$23348$new_n2396 $abc$23348$new_n2389 $abc$23348$new_n2414 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2416 xv[3][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20306 +001 1 +011 1 +100 1 +101 1 +.names ph[2][19] xv[2][6] yv[2][9] $abc$23348$new_n2396 $abc$23348$new_n2389 $abc$23348$new_n2416 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2422 xv[3][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20310 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] xv[2][4] yv[2][7] $abc$23348$new_n2397 $abc$23348$new_n2390 $abc$23348$new_n2422 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][3] yv[2][6] $abc$23348$new_n2424 xv[3][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20312 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][2] yv[2][5] $abc$23348$new_n2398 $abc$23348$new_n2391 $abc$23348$new_n2424 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[2][2] yv[2][5] $abc$23348$new_n2426 xv[3][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20314 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] $abc$23348$new_n2391 $abc$23348$new_n2398 $abc$23348$new_n2426 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2428 xv[3][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20316 +001 1 +011 1 +110 1 +111 1 +.names xv[2][1] yv[2][4] ph[2][19] xv[2][0] yv[2][3] $abc$23348$new_n2428 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[2][0] yv[2][3] xv[3][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20318 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[3][18] $abc$23348$new_n2435 $abc$23348$new_n2431 ph[4][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20320 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2440 ph[3][17] $abc$23348$new_n2431 +100 1 +101 1 +110 1 +.names ph[3][11] ph[3][10] $abc$23348$new_n2434 ph[3][9] $abc$23348$new_n2433 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[3][8] ph[3][6] ph[3][7] ph[3][5] ph[3][4] $abc$23348$new_n2434 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2440 ph[3][17] $abc$23348$new_n2435 +001 1 +010 1 +011 1 +.names ph[3][11] $abc$23348$new_n2438 ph[3][9] ph[3][10] $abc$23348$new_n2437 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[3][8] ph[3][6] ph[3][7] ph[3][5] ph[3][4] $abc$23348$new_n2438 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names i_ce $abc$23348$new_n2440 ph[4][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20322 +001 1 +011 1 +100 1 +101 1 +.names ph[3][17] ph[3][15] ph[3][16] $abc$23348$new_n2442 $abc$23348$new_n2441 $abc$23348$new_n2440 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names ph[3][19] ph[3][14] ph[3][13] ph[3][12] $abc$23348$new_n2437 $abc$23348$new_n2441 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[3][19] ph[3][14] ph[3][13] ph[3][12] $abc$23348$new_n2433 $abc$23348$new_n2442 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2444 ph[4][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20324 +001 1 +011 1 +100 1 +101 1 +.names ph[3][15] ph[3][16] $abc$23348$new_n2442 $abc$23348$new_n2441 $abc$23348$new_n2444 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[3][15] $abc$23348$new_n2442 $abc$23348$new_n2441 ph[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20326 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2447 ph[3][14] ph[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20328 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][19] ph[3][13] ph[3][12] $abc$23348$new_n2433 $abc$23348$new_n2437 $abc$23348$new_n2447 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_ce $abc$23348$new_n2449 ph[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20330 +001 1 +011 1 +110 1 +111 1 +.names ph[3][13] ph[3][19] ph[3][12] $abc$23348$new_n2437 $abc$23348$new_n2433 $abc$23348$new_n2449 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2451 ph[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20332 +001 1 +011 1 +110 1 +111 1 +.names ph[3][12] ph[3][19] $abc$23348$new_n2437 $abc$23348$new_n2433 $abc$23348$new_n2451 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[3][11] $abc$23348$new_n2453 ph[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20334 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[3][19] ph[3][9] ph[3][10] $abc$23348$new_n2434 $abc$23348$new_n2438 $abc$23348$new_n2453 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2455 ph[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20336 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] ph[3][10] ph[3][9] $abc$23348$new_n2438 $abc$23348$new_n2434 $abc$23348$new_n2455 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2457 ph[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20338 +001 1 +011 1 +110 1 +111 1 +.names ph[3][9] ph[3][19] $abc$23348$new_n2438 $abc$23348$new_n2434 $abc$23348$new_n2457 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2459 ph[3][8] ph[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20340 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][19] ph[3][7] ph[3][4] ph[3][5] ph[3][6] $abc$23348$new_n2459 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +.names i_ce $abc$23348$new_n2461 ph[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20342 +001 1 +011 1 +110 1 +111 1 +.names ph[3][7] ph[3][19] ph[3][6] ph[3][4] ph[3][5] $abc$23348$new_n2461 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +10000 1 +10001 1 +10010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2463 ph[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20344 +001 1 +011 1 +110 1 +111 1 +.names ph[3][6] ph[3][19] ph[3][4] ph[3][5] $abc$23348$new_n2463 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[3][19] ph[3][4] ph[3][5] ph[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20346 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[3][4] ph[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20348 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[3][3] ph[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20350 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][2] ph[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20352 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][1] ph[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20354 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[3][0] ph[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20356 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[3][15] yv[3][14] $abc$23348$new_n2471 yv[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20358 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2472 $abc$23348$new_n2479 $abc$23348$new_n2471 +000 1 +001 1 +101 1 +111 1 +.names xv[3][15] $abc$23348$new_n2473 yv[3][11] yv[3][12] yv[3][13] $abc$23348$new_n2472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[3][13] yv[3][9] xv[3][14] yv[3][10] $abc$23348$new_n2474 $abc$23348$new_n2473 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][11] yv[3][7] xv[3][12] yv[3][8] $abc$23348$new_n2475 $abc$23348$new_n2474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][9] yv[3][5] xv[3][10] yv[3][6] $abc$23348$new_n2476 $abc$23348$new_n2475 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][7] yv[3][3] xv[3][8] yv[3][4] $abc$23348$new_n2477 $abc$23348$new_n2476 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][2] $abc$23348$new_n2478 $abc$23348$new_n2477 +000 1 +001 1 +011 1 +101 1 +.names xv[3][4] yv[3][0] xv[3][5] yv[3][1] $abc$23348$new_n2478 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[3][15] $abc$23348$new_n2480 yv[3][12] yv[3][13] $abc$23348$new_n2479 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[3][14] xv[3][15] yv[3][10] yv[3][11] $abc$23348$new_n2481 $abc$23348$new_n2480 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][12] xv[3][13] yv[3][8] yv[3][9] $abc$23348$new_n2482 $abc$23348$new_n2481 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][10] xv[3][11] yv[3][6] yv[3][7] $abc$23348$new_n2483 $abc$23348$new_n2482 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][8] xv[3][9] yv[3][4] yv[3][5] $abc$23348$new_n2484 $abc$23348$new_n2483 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][6] xv[3][7] yv[3][2] yv[3][3] $abc$23348$new_n2485 $abc$23348$new_n2484 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[3][4] xv[3][5] yv[3][0] yv[3][1] $abc$23348$new_n2485 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names xv[3][15] $abc$23348$new_n2473 yv[3][11] yv[3][12] $abc$23348$new_n2489 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[3][15] yv[3][12] $abc$23348$new_n2491 yv[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] yv[3][11] $abc$23348$new_n2492 $abc$23348$new_n2473 $abc$23348$new_n2491 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[3][14] yv[3][10] $abc$23348$new_n2481 $abc$23348$new_n2492 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2494 yv[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20364 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][15] yv[3][11] $abc$23348$new_n2492 $abc$23348$new_n2473 $abc$23348$new_n2494 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][14] yv[3][10] $abc$23348$new_n2496 yv[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20366 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][13] yv[3][9] $abc$23348$new_n2474 $abc$23348$new_n2481 $abc$23348$new_n2496 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][13] yv[3][9] $abc$23348$new_n2498 yv[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20368 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][12] yv[3][8] $abc$23348$new_n2482 $abc$23348$new_n2474 $abc$23348$new_n2498 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][12] yv[3][8] $abc$23348$new_n2500 yv[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20370 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][11] yv[3][7] $abc$23348$new_n2475 $abc$23348$new_n2482 $abc$23348$new_n2500 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][11] yv[3][7] $abc$23348$new_n2502 yv[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20372 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][10] yv[3][6] $abc$23348$new_n2483 $abc$23348$new_n2475 $abc$23348$new_n2502 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][10] yv[3][6] $abc$23348$new_n2504 yv[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][9] yv[3][5] $abc$23348$new_n2476 $abc$23348$new_n2483 $abc$23348$new_n2504 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][9] yv[3][5] $abc$23348$new_n2506 yv[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20376 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][8] yv[3][4] $abc$23348$new_n2484 $abc$23348$new_n2476 $abc$23348$new_n2506 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][8] yv[3][4] $abc$23348$new_n2508 yv[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20378 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][7] yv[3][3] $abc$23348$new_n2477 $abc$23348$new_n2484 $abc$23348$new_n2508 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[3][7] yv[3][3] $abc$23348$new_n2510 yv[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20380 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][6] yv[3][2] $abc$23348$new_n2485 $abc$23348$new_n2478 $abc$23348$new_n2510 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][6] yv[3][2] $abc$23348$new_n2512 yv[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20382 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2478 $abc$23348$new_n2485 $abc$23348$new_n2512 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2514 yv[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20384 +001 1 +011 1 +110 1 +111 1 +.names xv[3][5] yv[3][1] ph[3][19] yv[3][0] xv[3][4] $abc$23348$new_n2514 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[3][4] yv[3][0] yv[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20386 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[3][15] xv[3][14] $abc$23348$new_n2517 xv[4][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20388 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2518 $abc$23348$new_n2525 $abc$23348$new_n2517 +000 1 +001 1 +101 1 +111 1 +.names yv[3][15] xv[3][12] xv[3][13] $abc$23348$new_n2519 $abc$23348$new_n2518 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[3][10] yv[3][14] yv[3][15] xv[3][11] $abc$23348$new_n2520 $abc$23348$new_n2519 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3][12] xv[3][8] xv[3][9] yv[3][13] $abc$23348$new_n2521 $abc$23348$new_n2520 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[3][6] xv[3][7] yv[3][10] yv[3][11] $abc$23348$new_n2522 $abc$23348$new_n2521 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[3][8] xv[3][4] xv[3][5] yv[3][9] $abc$23348$new_n2523 $abc$23348$new_n2522 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][6] xv[3][2] xv[3][3] yv[3][7] $abc$23348$new_n2524 $abc$23348$new_n2523 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][4] xv[3][0] xv[3][1] yv[3][5] $abc$23348$new_n2524 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[3][15] $abc$23348$new_n2526 xv[3][12] xv[3][13] $abc$23348$new_n2525 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[3][10] yv[3][14] yv[3][15] xv[3][11] $abc$23348$new_n2527 $abc$23348$new_n2526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][12] xv[3][9] yv[3][13] $abc$23348$new_n2528 $abc$23348$new_n2527 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][10] xv[3][7] yv[3][11] $abc$23348$new_n2529 $abc$23348$new_n2528 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][8] xv[3][5] yv[3][9] $abc$23348$new_n2530 $abc$23348$new_n2529 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][2] yv[3][6] xv[3][3] yv[3][7] $abc$23348$new_n2531 $abc$23348$new_n2530 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][0] yv[3][4] xv[3][1] yv[3][5] $abc$23348$new_n2531 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[3][15] xv[3][13] $abc$23348$new_n2533 xv[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20390 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] yv[3][15] xv[3][12] $abc$23348$new_n2526 $abc$23348$new_n2519 $abc$23348$new_n2533 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2535 xv[4][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20392 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] yv[3][15] xv[3][12] $abc$23348$new_n2526 $abc$23348$new_n2519 $abc$23348$new_n2535 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[3][15] xv[3][11] $abc$23348$new_n2537 xv[4][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20394 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][10] yv[3][14] $abc$23348$new_n2527 $abc$23348$new_n2520 $abc$23348$new_n2537 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2539 xv[4][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20396 +001 1 +011 1 +100 1 +101 1 +.names ph[3][19] xv[3][10] yv[3][14] $abc$23348$new_n2527 $abc$23348$new_n2520 $abc$23348$new_n2539 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][9] yv[3][13] $abc$23348$new_n2541 xv[4][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20398 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][8] yv[3][12] $abc$23348$new_n2528 $abc$23348$new_n2521 $abc$23348$new_n2541 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2543 xv[4][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20400 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][8] yv[3][12] $abc$23348$new_n2528 $abc$23348$new_n2521 $abc$23348$new_n2543 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][7] yv[3][11] $abc$23348$new_n2545 xv[4][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20402 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][6] yv[3][10] $abc$23348$new_n2529 $abc$23348$new_n2522 $abc$23348$new_n2545 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][6] yv[3][10] $abc$23348$new_n2547 xv[4][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20404 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] $abc$23348$new_n2522 $abc$23348$new_n2529 $abc$23348$new_n2547 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[3][5] yv[3][9] $abc$23348$new_n2549 xv[4][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20406 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][4] yv[3][8] $abc$23348$new_n2530 $abc$23348$new_n2523 $abc$23348$new_n2549 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2551 xv[4][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20408 +001 1 +011 1 +110 1 +111 1 +.names ph[3][19] xv[3][4] yv[3][8] $abc$23348$new_n2530 $abc$23348$new_n2523 $abc$23348$new_n2551 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][3] yv[3][7] $abc$23348$new_n2553 xv[4][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20410 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][2] yv[3][6] $abc$23348$new_n2531 $abc$23348$new_n2524 $abc$23348$new_n2553 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][2] yv[3][6] $abc$23348$new_n2555 xv[4][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20412 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] $abc$23348$new_n2524 $abc$23348$new_n2531 $abc$23348$new_n2555 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2557 xv[4][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20414 +001 1 +011 1 +110 1 +111 1 +.names xv[3][1] yv[3][5] ph[3][19] xv[3][0] yv[3][4] $abc$23348$new_n2557 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[3][0] yv[3][4] xv[4][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20416 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[4][18] $abc$23348$new_n2567 $abc$23348$new_n2560 ph[5][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20418 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][19] ph[4][16] ph[4][17] $abc$23348$new_n2561 ph[4][15] $abc$23348$new_n2560 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ph[4][14] ph[4][13] $abc$23348$new_n2562 ph[4][12] $abc$23348$new_n2561 +1101 1 +1110 1 +1111 1 +.names ph[4][11] $abc$23348$new_n2563 $abc$23348$new_n2562 +10 1 +.names ph[4][10] ph[4][8] ph[4][9] ph[4][7] $abc$23348$new_n2564 $abc$23348$new_n2563 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[4][6] ph[4][5] $abc$23348$new_n2565 ph[4][4] $abc$23348$new_n2564 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2566 ph[4][3] $abc$23348$new_n2565 +10 1 +.names ph[4][2] ph[4][1] ph[4][0] $abc$23348$new_n2566 +000 1 +001 1 +010 1 +.names ph[4][19] $abc$23348$new_n2568 ph[4][16] ph[4][17] ph[4][15] $abc$23348$new_n2567 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ph[4][14] ph[4][13] $abc$23348$new_n2569 ph[4][12] $abc$23348$new_n2568 +0000 1 +0010 1 +0011 1 +.names ph[4][11] $abc$23348$new_n2570 $abc$23348$new_n2569 +00 1 +.names ph[4][10] ph[4][9] $abc$23348$new_n2571 ph[4][7] ph[4][8] $abc$23348$new_n2570 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][6] ph[4][5] ph[4][4] $abc$23348$new_n2572 $abc$23348$new_n2571 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][3] $abc$23348$new_n2573 $abc$23348$new_n2572 +11 1 +.names ph[4][2] ph[4][1] ph[4][0] $abc$23348$new_n2573 +101 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2575 ph[5][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20420 +001 1 +011 1 +110 1 +111 1 +.names ph[4][15] ph[4][17] ph[4][16] $abc$23348$new_n2577 $abc$23348$new_n2576 $abc$23348$new_n2575 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[4][19] $abc$23348$new_n2561 $abc$23348$new_n2576 +11 1 +.names $abc$23348$new_n2568 ph[4][19] $abc$23348$new_n2577 +10 1 +.names i_ce $abc$23348$new_n2579 ph[5][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20422 +001 1 +011 1 +110 1 +111 1 +.names ph[4][16] ph[4][15] $abc$23348$new_n2577 $abc$23348$new_n2576 $abc$23348$new_n2579 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][15] $abc$23348$new_n2577 $abc$23348$new_n2576 ph[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20424 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[4][14] $abc$23348$new_n2582 ph[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20426 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][19] ph[4][13] ph[4][12] $abc$23348$new_n2562 $abc$23348$new_n2569 $abc$23348$new_n2582 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2584 ph[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20428 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] ph[4][13] ph[4][12] $abc$23348$new_n2569 $abc$23348$new_n2562 $abc$23348$new_n2584 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2586 ph[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20430 +001 1 +011 1 +110 1 +111 1 +.names ph[4][12] ph[4][11] $abc$23348$new_n2588 $abc$23348$new_n2587 $abc$23348$new_n2586 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names ph[4][19] $abc$23348$new_n2563 $abc$23348$new_n2587 +10 1 +.names ph[4][19] $abc$23348$new_n2570 $abc$23348$new_n2588 +00 1 +.names i_ce ph[4][11] $abc$23348$new_n2588 $abc$23348$new_n2587 ph[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20432 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2591 ph[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20434 +001 1 +011 1 +100 1 +101 1 +.names ph[4][8] ph[4][10] ph[4][9] $abc$23348$new_n2594 $abc$23348$new_n2592 $abc$23348$new_n2591 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[4][7] $abc$23348$new_n2593 $abc$23348$new_n2592 +11 1 +.names ph[4][19] $abc$23348$new_n2564 $abc$23348$new_n2593 +10 1 +.names $abc$23348$new_n2595 ph[4][7] $abc$23348$new_n2594 +10 1 +.names ph[4][19] $abc$23348$new_n2571 $abc$23348$new_n2595 +00 1 +.names i_ce $abc$23348$new_n2597 ph[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20436 +001 1 +011 1 +110 1 +111 1 +.names ph[4][9] ph[4][8] $abc$23348$new_n2594 $abc$23348$new_n2592 $abc$23348$new_n2597 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][8] $abc$23348$new_n2594 $abc$23348$new_n2592 ph[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20438 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[4][7] $abc$23348$new_n2595 $abc$23348$new_n2593 ph[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20440 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2601 ph[4][6] ph[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20442 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][19] ph[4][5] ph[4][4] $abc$23348$new_n2565 $abc$23348$new_n2572 $abc$23348$new_n2601 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[4][5] $abc$23348$new_n2603 ph[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20444 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][3] ph[4][4] ph[4][19] $abc$23348$new_n2566 $abc$23348$new_n2573 $abc$23348$new_n2603 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2605 ph[4][4] ph[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20446 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][3] ph[4][19] $abc$23348$new_n2566 $abc$23348$new_n2573 $abc$23348$new_n2605 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2607 ph[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20448 +001 1 +011 1 +110 1 +111 1 +.names ph[4][3] ph[4][19] $abc$23348$new_n2573 $abc$23348$new_n2566 $abc$23348$new_n2607 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n2609 ph[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20450 +001 1 +011 1 +110 1 +111 1 +.names ph[4][2] ph[4][19] ph[4][0] ph[4][1] $abc$23348$new_n2609 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[4][19] ph[4][0] ph[4][1] ph[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20452 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[4][0] ph[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20454 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[4][15] yv[4][14] $abc$23348$new_n2613 yv[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20456 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] $abc$23348$new_n2614 $abc$23348$new_n2621 $abc$23348$new_n2613 +000 1 +001 1 +101 1 +111 1 +.names xv[4][15] $abc$23348$new_n2615 yv[4][12] yv[4][13] $abc$23348$new_n2614 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][15] $abc$23348$new_n2616 yv[4][10] yv[4][11] $abc$23348$new_n2615 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][13] yv[4][8] xv[4][14] yv[4][9] $abc$23348$new_n2617 $abc$23348$new_n2616 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][11] yv[4][6] xv[4][12] yv[4][7] $abc$23348$new_n2618 $abc$23348$new_n2617 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][9] yv[4][4] xv[4][10] yv[4][5] $abc$23348$new_n2619 $abc$23348$new_n2618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[4][7] yv[4][2] xv[4][8] yv[4][3] $abc$23348$new_n2620 $abc$23348$new_n2619 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][5] yv[4][0] xv[4][6] yv[4][1] $abc$23348$new_n2620 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[4][15] yv[4][13] $abc$23348$new_n2622 $abc$23348$new_n2621 +001 1 +100 1 +101 1 +111 1 +.names xv[4][15] $abc$23348$new_n2623 yv[4][10] yv[4][11] yv[4][12] $abc$23348$new_n2622 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][13] xv[4][14] yv[4][8] yv[4][9] $abc$23348$new_n2624 $abc$23348$new_n2623 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][11] xv[4][12] yv[4][6] yv[4][7] $abc$23348$new_n2625 $abc$23348$new_n2624 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][9] xv[4][10] yv[4][4] yv[4][5] $abc$23348$new_n2626 $abc$23348$new_n2625 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][7] xv[4][8] yv[4][2] yv[4][3] $abc$23348$new_n2627 $abc$23348$new_n2626 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[4][5] xv[4][6] yv[4][0] yv[4][1] $abc$23348$new_n2627 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[4][15] yv[4][13] $abc$23348$new_n2629 yv[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20458 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2622 $abc$23348$new_n2615 ph[4][19] yv[4][12] $abc$23348$new_n2629 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[4][15] yv[4][10] $abc$23348$new_n2623 $abc$23348$new_n2633 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2638 yv[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20464 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][15] yv[4][10] $abc$23348$new_n2623 $abc$23348$new_n2616 $abc$23348$new_n2638 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][14] yv[4][9] $abc$23348$new_n2640 yv[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20466 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][13] yv[4][8] $abc$23348$new_n2624 $abc$23348$new_n2617 $abc$23348$new_n2640 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2642 yv[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20468 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][13] yv[4][8] $abc$23348$new_n2624 $abc$23348$new_n2617 $abc$23348$new_n2642 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][12] yv[4][7] $abc$23348$new_n2644 yv[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20470 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][11] yv[4][6] $abc$23348$new_n2625 $abc$23348$new_n2618 $abc$23348$new_n2644 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][11] yv[4][6] $abc$23348$new_n2646 yv[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20472 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] $abc$23348$new_n2618 $abc$23348$new_n2625 $abc$23348$new_n2646 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[4][10] yv[4][5] $abc$23348$new_n2648 yv[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20474 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][9] yv[4][4] $abc$23348$new_n2626 $abc$23348$new_n2619 $abc$23348$new_n2648 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2650 yv[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20476 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][9] yv[4][4] $abc$23348$new_n2626 $abc$23348$new_n2619 $abc$23348$new_n2650 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][8] yv[4][3] $abc$23348$new_n2652 yv[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20478 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][7] yv[4][2] $abc$23348$new_n2627 $abc$23348$new_n2620 $abc$23348$new_n2652 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][2] $abc$23348$new_n2654 yv[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20480 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2620 $abc$23348$new_n2627 $abc$23348$new_n2654 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2656 yv[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20482 +001 1 +011 1 +110 1 +111 1 +.names xv[4][6] yv[4][1] ph[4][19] yv[4][0] xv[4][5] $abc$23348$new_n2656 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[4][5] yv[4][0] yv[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20484 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[4][15] xv[4][14] $abc$23348$new_n2659 xv[5][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20486 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2660 $abc$23348$new_n2667 $abc$23348$new_n2659 +000 1 +001 1 +101 1 +111 1 +.names yv[4][15] $abc$23348$new_n2661 xv[4][12] xv[4][13] $abc$23348$new_n2660 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[4][15] $abc$23348$new_n2662 xv[4][10] xv[4][11] $abc$23348$new_n2661 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[4][13] xv[4][8] xv[4][9] yv[4][14] $abc$23348$new_n2663 $abc$23348$new_n2662 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[4][6] xv[4][7] yv[4][11] yv[4][12] $abc$23348$new_n2664 $abc$23348$new_n2663 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[4][9] xv[4][4] xv[4][5] yv[4][10] $abc$23348$new_n2665 $abc$23348$new_n2664 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][7] xv[4][2] xv[4][3] yv[4][8] $abc$23348$new_n2666 $abc$23348$new_n2665 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][5] xv[4][0] xv[4][1] yv[4][6] $abc$23348$new_n2666 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[4][15] xv[4][13] $abc$23348$new_n2668 $abc$23348$new_n2667 +000 1 +001 1 +011 1 +101 1 +.names yv[4][15] $abc$23348$new_n2669 xv[4][10] xv[4][11] xv[4][12] $abc$23348$new_n2668 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[4][8] yv[4][13] xv[4][9] yv[4][14] $abc$23348$new_n2670 $abc$23348$new_n2669 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][6] yv[4][11] xv[4][7] yv[4][12] $abc$23348$new_n2671 $abc$23348$new_n2670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][4] yv[4][9] xv[4][5] yv[4][10] $abc$23348$new_n2672 $abc$23348$new_n2671 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][2] yv[4][7] xv[4][3] yv[4][8] $abc$23348$new_n2673 $abc$23348$new_n2672 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][0] yv[4][5] xv[4][1] yv[4][6] $abc$23348$new_n2673 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[4][15] xv[4][13] $abc$23348$new_n2675 xv[5][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20488 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] yv[4][15] xv[4][12] $abc$23348$new_n2676 $abc$23348$new_n2661 $abc$23348$new_n2675 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[4][15] $abc$23348$new_n2669 xv[4][10] xv[4][11] $abc$23348$new_n2676 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n2678 xv[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20490 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] yv[4][15] xv[4][12] $abc$23348$new_n2676 $abc$23348$new_n2661 $abc$23348$new_n2678 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[4][15] xv[4][11] $abc$23348$new_n2680 xv[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20492 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][10] yv[4][15] $abc$23348$new_n2669 $abc$23348$new_n2662 $abc$23348$new_n2680 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2682 xv[5][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20494 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] yv[4][15] xv[4][10] $abc$23348$new_n2669 $abc$23348$new_n2662 $abc$23348$new_n2682 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][9] yv[4][14] $abc$23348$new_n2684 xv[5][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20496 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][8] yv[4][13] $abc$23348$new_n2670 $abc$23348$new_n2663 $abc$23348$new_n2684 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2686 xv[5][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20498 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][8] yv[4][13] $abc$23348$new_n2670 $abc$23348$new_n2663 $abc$23348$new_n2686 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][12] $abc$23348$new_n2688 xv[5][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20500 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][6] yv[4][11] $abc$23348$new_n2671 $abc$23348$new_n2664 $abc$23348$new_n2688 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2690 xv[5][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20502 +001 1 +011 1 +100 1 +101 1 +.names ph[4][19] xv[4][6] yv[4][11] $abc$23348$new_n2671 $abc$23348$new_n2664 $abc$23348$new_n2690 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][5] yv[4][10] $abc$23348$new_n2692 xv[5][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20504 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][4] yv[4][9] $abc$23348$new_n2672 $abc$23348$new_n2665 $abc$23348$new_n2692 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2694 xv[5][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20506 +001 1 +011 1 +110 1 +111 1 +.names ph[4][19] xv[4][4] yv[4][9] $abc$23348$new_n2672 $abc$23348$new_n2665 $abc$23348$new_n2694 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][3] yv[4][8] $abc$23348$new_n2696 xv[5][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20508 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][2] yv[4][7] $abc$23348$new_n2673 $abc$23348$new_n2666 $abc$23348$new_n2696 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][2] yv[4][7] $abc$23348$new_n2698 xv[5][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20510 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] $abc$23348$new_n2666 $abc$23348$new_n2673 $abc$23348$new_n2698 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2700 xv[5][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20512 +001 1 +011 1 +110 1 +111 1 +.names xv[4][1] yv[4][6] ph[4][19] xv[4][0] yv[4][5] $abc$23348$new_n2700 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[4][0] yv[4][5] xv[5][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20514 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2703 ph[6][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20516 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][18] ph[5][17] $abc$23348$new_n2711 $abc$23348$new_n2704 $abc$23348$new_n2703 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[5][16] $abc$23348$new_n2705 $abc$23348$new_n2704 +11 1 +.names ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2705 +11 1 +.names ph[5][14] ph[5][12] ph[5][13] $abc$23348$new_n2707 ph[5][11] $abc$23348$new_n2706 +11101 1 +11110 1 +11111 1 +.names ph[5][10] ph[5][9] ph[5][8] $abc$23348$new_n2708 $abc$23348$new_n2707 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2708 +11 1 +.names ph[5][6] $abc$23348$new_n2710 ph[5][5] $abc$23348$new_n2709 +101 1 +110 1 +111 1 +.names ph[5][4] ph[5][2] ph[5][3] ph[5][0] ph[5][1] $abc$23348$new_n2710 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n2712 ph[5][15] ph[5][16] $abc$23348$new_n2711 +100 1 +.names ph[5][14] ph[5][12] ph[5][13] $abc$23348$new_n2713 ph[5][11] $abc$23348$new_n2712 +00000 1 +00010 1 +00011 1 +.names ph[5][10] ph[5][9] $abc$23348$new_n2714 ph[5][8] $abc$23348$new_n2713 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n2715 ph[5][7] $abc$23348$new_n2714 +10 1 +.names ph[5][6] $abc$23348$new_n2716 ph[5][5] $abc$23348$new_n2715 +000 1 +010 1 +011 1 +.names ph[5][4] ph[5][2] ph[5][3] ph[5][0] ph[5][1] $abc$23348$new_n2716 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce $abc$23348$new_n2718 ph[6][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20518 +001 1 +011 1 +100 1 +101 1 +.names ph[5][17] ph[5][19] $abc$23348$new_n2711 $abc$23348$new_n2704 $abc$23348$new_n2718 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$23348$new_n2720 ph[6][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20520 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][16] ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2712 $abc$23348$new_n2720 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2722 ph[6][15] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20522 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[5][19] ph[5][15] $abc$23348$new_n2706 $abc$23348$new_n2712 $abc$23348$new_n2722 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2724 ph[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20524 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] ph[5][14] ph[5][13] $abc$23348$new_n2726 $abc$23348$new_n2725 $abc$23348$new_n2724 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2713 ph[5][11] $abc$23348$new_n2725 +000 1 +010 1 +011 1 +.names ph[5][19] $abc$23348$new_n2707 ph[5][11] $abc$23348$new_n2726 +101 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n2728 ph[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20526 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] ph[5][13] $abc$23348$new_n2726 $abc$23348$new_n2725 $abc$23348$new_n2728 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[5][12] $abc$23348$new_n2726 $abc$23348$new_n2725 ph[6][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2731 ph[6][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20530 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][11] $abc$23348$new_n2707 $abc$23348$new_n2713 $abc$23348$new_n2731 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][10] $abc$23348$new_n2733 ph[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20532 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][19] ph[5][8] ph[5][9] $abc$23348$new_n2714 $abc$23348$new_n2708 $abc$23348$new_n2733 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2735 ph[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20534 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] ph[5][9] ph[5][8] $abc$23348$new_n2708 $abc$23348$new_n2714 $abc$23348$new_n2735 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2737 ph[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20536 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][19] ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2715 $abc$23348$new_n2737 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2739 ph[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20538 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][7] $abc$23348$new_n2709 $abc$23348$new_n2715 $abc$23348$new_n2739 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2741 ph[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20540 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] ph[5][6] ph[5][5] $abc$23348$new_n2710 $abc$23348$new_n2716 $abc$23348$new_n2741 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2743 ph[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20542 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][5] $abc$23348$new_n2710 $abc$23348$new_n2716 $abc$23348$new_n2743 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][4] $abc$23348$new_n2745 ph[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20544 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][19] ph[5][0] ph[5][1] ph[5][2] ph[5][3] $abc$23348$new_n2745 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2747 ph[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20546 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][3] ph[5][0] ph[5][1] ph[5][2] $abc$23348$new_n2747 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2749 ph[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20548 +001 1 +011 1 +100 1 +101 1 +.names ph[5][2] ph[5][19] ph[5][0] ph[5][1] $abc$23348$new_n2749 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[5][19] ph[5][0] ph[5][1] ph[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20550 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[5][0] ph[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20552 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[5][15] yv[5][14] $abc$23348$new_n2753 yv[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20554 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] $abc$23348$new_n2754 $abc$23348$new_n2761 $abc$23348$new_n2753 +000 1 +001 1 +101 1 +111 1 +.names xv[5][15] $abc$23348$new_n2755 yv[5][12] yv[5][13] $abc$23348$new_n2754 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[5][15] $abc$23348$new_n2756 yv[5][9] yv[5][10] yv[5][11] $abc$23348$new_n2755 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[5][13] yv[5][7] xv[5][14] yv[5][8] $abc$23348$new_n2757 $abc$23348$new_n2756 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][11] yv[5][5] xv[5][12] yv[5][6] $abc$23348$new_n2758 $abc$23348$new_n2757 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][9] yv[5][3] xv[5][10] yv[5][4] $abc$23348$new_n2759 $abc$23348$new_n2758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][8] yv[5][2] $abc$23348$new_n2760 $abc$23348$new_n2759 +000 1 +001 1 +011 1 +101 1 +.names xv[5][6] yv[5][0] xv[5][7] yv[5][1] $abc$23348$new_n2760 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[5][15] yv[5][13] $abc$23348$new_n2762 $abc$23348$new_n2761 +001 1 +100 1 +101 1 +111 1 +.names xv[5][15] $abc$23348$new_n2763 yv[5][10] yv[5][11] yv[5][12] $abc$23348$new_n2762 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][14] xv[5][15] yv[5][8] yv[5][9] $abc$23348$new_n2764 $abc$23348$new_n2763 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][12] xv[5][13] yv[5][6] yv[5][7] $abc$23348$new_n2765 $abc$23348$new_n2764 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][10] xv[5][11] yv[5][4] yv[5][5] $abc$23348$new_n2766 $abc$23348$new_n2765 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][2] yv[5][3] $abc$23348$new_n2767 $abc$23348$new_n2766 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[5][6] xv[5][7] yv[5][0] yv[5][1] $abc$23348$new_n2767 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[5][15] yv[5][13] $abc$23348$new_n2769 yv[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20556 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2762 $abc$23348$new_n2755 ph[5][19] yv[5][12] $abc$23348$new_n2769 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[5][15] yv[5][12] $abc$23348$new_n2771 yv[6][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20558 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n2755 ph[5][19] $abc$23348$new_n2772 yv[5][11] $abc$23348$new_n2771 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[5][15] yv[5][10] $abc$23348$new_n2763 $abc$23348$new_n2772 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2774 yv[6][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20560 +001 1 +011 1 +110 1 +111 1 +.names xv[5][15] yv[5][11] ph[5][19] $abc$23348$new_n2775 $abc$23348$new_n2772 $abc$23348$new_n2774 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names xv[5][15] $abc$23348$new_n2756 yv[5][9] yv[5][10] $abc$23348$new_n2775 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[5][15] yv[5][10] $abc$23348$new_n2777 yv[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][15] yv[5][9] $abc$23348$new_n2756 $abc$23348$new_n2763 $abc$23348$new_n2777 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][15] yv[5][9] $abc$23348$new_n2779 yv[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20564 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][14] yv[5][8] $abc$23348$new_n2764 $abc$23348$new_n2756 $abc$23348$new_n2779 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][14] yv[5][8] $abc$23348$new_n2781 yv[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20566 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][13] yv[5][7] $abc$23348$new_n2757 $abc$23348$new_n2764 $abc$23348$new_n2781 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][13] yv[5][7] $abc$23348$new_n2783 yv[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20568 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][12] yv[5][6] $abc$23348$new_n2765 $abc$23348$new_n2757 $abc$23348$new_n2783 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][12] yv[5][6] $abc$23348$new_n2785 yv[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20570 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][11] yv[5][5] $abc$23348$new_n2758 $abc$23348$new_n2765 $abc$23348$new_n2785 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][11] yv[5][5] $abc$23348$new_n2787 yv[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][10] yv[5][4] $abc$23348$new_n2766 $abc$23348$new_n2758 $abc$23348$new_n2787 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][10] yv[5][4] $abc$23348$new_n2789 yv[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20574 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][9] yv[5][3] $abc$23348$new_n2759 $abc$23348$new_n2766 $abc$23348$new_n2789 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][9] yv[5][3] $abc$23348$new_n2791 yv[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20576 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] yv[5][2] xv[5][8] $abc$23348$new_n2767 $abc$23348$new_n2760 $abc$23348$new_n2791 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][8] yv[5][2] $abc$23348$new_n2793 yv[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20578 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2760 $abc$23348$new_n2767 $abc$23348$new_n2793 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[5][7] yv[5][1] $abc$23348$new_n2795 yv[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20580 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[5][6] ph[5][19] yv[5][0] $abc$23348$new_n2795 +101 1 +110 1 +.names i_ce xv[5][6] yv[5][0] yv[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20582 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[5][15] xv[5][14] $abc$23348$new_n2798 xv[6][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20584 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2799 $abc$23348$new_n2806 $abc$23348$new_n2798 +000 1 +001 1 +101 1 +111 1 +.names yv[5][15] $abc$23348$new_n2800 xv[5][12] xv[5][13] $abc$23348$new_n2799 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[5][15] $abc$23348$new_n2801 xv[5][9] xv[5][10] xv[5][11] $abc$23348$new_n2800 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[5][14] xv[5][8] $abc$23348$new_n2802 $abc$23348$new_n2801 +000 1 +100 1 +101 1 +110 1 +.names xv[5][6] xv[5][7] yv[5][12] yv[5][13] $abc$23348$new_n2803 $abc$23348$new_n2802 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[5][10] xv[5][4] xv[5][5] yv[5][11] $abc$23348$new_n2804 $abc$23348$new_n2803 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][8] xv[5][2] xv[5][3] yv[5][9] $abc$23348$new_n2805 $abc$23348$new_n2804 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][6] xv[5][0] xv[5][1] yv[5][7] $abc$23348$new_n2805 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[5][15] $abc$23348$new_n2807 xv[5][12] xv[5][13] $abc$23348$new_n2806 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[5][15] $abc$23348$new_n2808 xv[5][9] xv[5][10] xv[5][11] $abc$23348$new_n2807 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[5][8] yv[5][14] $abc$23348$new_n2809 $abc$23348$new_n2808 +000 1 +001 1 +011 1 +101 1 +.names xv[5][6] yv[5][12] xv[5][7] yv[5][13] $abc$23348$new_n2810 $abc$23348$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][4] yv[5][10] xv[5][5] yv[5][11] $abc$23348$new_n2811 $abc$23348$new_n2810 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[5][2] yv[5][8] xv[5][3] yv[5][9] $abc$23348$new_n2812 $abc$23348$new_n2811 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][0] yv[5][6] xv[5][1] yv[5][7] $abc$23348$new_n2812 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[5][15] xv[5][13] $abc$23348$new_n2814 xv[6][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20586 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] yv[5][15] xv[5][12] $abc$23348$new_n2807 $abc$23348$new_n2800 $abc$23348$new_n2814 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2816 xv[6][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20588 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] yv[5][15] xv[5][12] $abc$23348$new_n2807 $abc$23348$new_n2800 $abc$23348$new_n2816 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[5][15] xv[5][11] $abc$23348$new_n2818 xv[6][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20590 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][10] yv[5][15] $abc$23348$new_n2820 $abc$23348$new_n2819 $abc$23348$new_n2818 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[5][15] xv[5][9] $abc$23348$new_n2801 $abc$23348$new_n2819 +001 1 +100 1 +101 1 +111 1 +.names yv[5][15] xv[5][9] $abc$23348$new_n2808 $abc$23348$new_n2820 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n2822 xv[6][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20592 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] yv[5][15] xv[5][10] $abc$23348$new_n2820 $abc$23348$new_n2819 $abc$23348$new_n2822 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2824 xv[6][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20594 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] yv[5][15] xv[5][9] $abc$23348$new_n2808 $abc$23348$new_n2801 $abc$23348$new_n2824 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2826 xv[6][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20596 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] xv[5][8] yv[5][14] $abc$23348$new_n2809 $abc$23348$new_n2802 $abc$23348$new_n2826 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][7] yv[5][13] $abc$23348$new_n2828 xv[6][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20598 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][6] yv[5][12] $abc$23348$new_n2810 $abc$23348$new_n2803 $abc$23348$new_n2828 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2830 xv[6][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20600 +001 1 +011 1 +100 1 +101 1 +.names ph[5][19] xv[5][6] yv[5][12] $abc$23348$new_n2810 $abc$23348$new_n2803 $abc$23348$new_n2830 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[5][5] yv[5][11] $abc$23348$new_n2832 xv[6][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][4] yv[5][10] $abc$23348$new_n2811 $abc$23348$new_n2804 $abc$23348$new_n2832 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2834 xv[6][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20604 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] xv[5][4] yv[5][10] $abc$23348$new_n2811 $abc$23348$new_n2804 $abc$23348$new_n2834 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[5][3] yv[5][9] $abc$23348$new_n2836 xv[6][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20606 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][2] yv[5][8] $abc$23348$new_n2812 $abc$23348$new_n2805 $abc$23348$new_n2836 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][2] yv[5][8] $abc$23348$new_n2838 xv[6][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20608 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] $abc$23348$new_n2805 $abc$23348$new_n2812 $abc$23348$new_n2838 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n2840 xv[6][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20610 +001 1 +011 1 +110 1 +111 1 +.names xv[5][1] yv[5][7] ph[5][19] xv[5][0] yv[5][6] $abc$23348$new_n2840 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[5][0] yv[5][6] xv[6][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20612 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][18] $abc$23348$new_n2843 ph[7][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20614 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n2844 ph[6][19] ph[6][17] $abc$23348$new_n2850 ph[6][16] $abc$23348$new_n2843 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +.names $abc$23348$new_n2845 ph[6][19] ph[6][16] ph[6][17] $abc$23348$new_n2844 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[6][19] $abc$23348$new_n2846 ph[6][14] ph[6][15] ph[6][13] $abc$23348$new_n2845 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ph[6][12] ph[6][11] $abc$23348$new_n2847 ph[6][10] $abc$23348$new_n2846 +0000 1 +0010 1 +0011 1 +.names ph[6][9] $abc$23348$new_n2848 $abc$23348$new_n2847 +00 1 +.names ph[6][8] ph[6][7] $abc$23348$new_n2849 ph[6][5] ph[6][6] $abc$23348$new_n2848 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][4] ph[6][3] ph[6][1] ph[6][2] ph[6][0] $abc$23348$new_n2849 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][14] ph[6][15] $abc$23348$new_n2851 $abc$23348$new_n2850 +111 1 +.names ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2851 +11 1 +.names ph[6][12] ph[6][11] $abc$23348$new_n2853 ph[6][10] $abc$23348$new_n2852 +1101 1 +1110 1 +1111 1 +.names ph[6][9] $abc$23348$new_n2854 $abc$23348$new_n2853 +10 1 +.names ph[6][8] ph[6][6] ph[6][7] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2854 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[6][4] ph[6][3] ph[6][1] ph[6][2] ph[6][0] $abc$23348$new_n2855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names i_ce $abc$23348$new_n2857 ph[7][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20616 +001 1 +011 1 +110 1 +111 1 +.names ph[6][17] ph[6][19] ph[6][16] $abc$23348$new_n2845 $abc$23348$new_n2850 $abc$23348$new_n2857 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2859 ph[7][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20618 +001 1 +011 1 +110 1 +111 1 +.names ph[6][16] $abc$23348$new_n2845 ph[6][19] $abc$23348$new_n2850 $abc$23348$new_n2859 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2864 ph[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20622 +001 1 +011 1 +100 1 +101 1 +.names ph[6][14] ph[6][19] ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2846 $abc$23348$new_n2864 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n2866 ph[7][13] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20624 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[6][19] ph[6][13] $abc$23348$new_n2852 $abc$23348$new_n2846 $abc$23348$new_n2866 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2868 ph[6][12] ph[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20626 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][19] ph[6][10] ph[6][11] $abc$23348$new_n2847 $abc$23348$new_n2853 $abc$23348$new_n2868 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2870 ph[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20628 +001 1 +011 1 +110 1 +111 1 +.names ph[6][11] ph[6][19] ph[6][10] $abc$23348$new_n2853 $abc$23348$new_n2847 $abc$23348$new_n2870 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2872 ph[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20630 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] ph[6][10] $abc$23348$new_n2853 $abc$23348$new_n2847 $abc$23348$new_n2872 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2874 ph[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20632 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] ph[6][9] $abc$23348$new_n2854 $abc$23348$new_n2848 $abc$23348$new_n2874 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n2876 ph[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20634 +001 1 +011 1 +100 1 +101 1 +.names ph[6][6] ph[6][8] ph[6][7] $abc$23348$new_n2878 $abc$23348$new_n2877 $abc$23348$new_n2876 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2849 $abc$23348$new_n2877 +000 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2878 +110 1 +.names i_ce $abc$23348$new_n2880 ph[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20636 +001 1 +011 1 +110 1 +111 1 +.names ph[6][6] ph[6][7] $abc$23348$new_n2878 $abc$23348$new_n2877 $abc$23348$new_n2880 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][6] $abc$23348$new_n2878 $abc$23348$new_n2877 ph[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20638 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n2883 ph[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20640 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] ph[6][5] $abc$23348$new_n2855 $abc$23348$new_n2849 $abc$23348$new_n2883 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][4] $abc$23348$new_n2885 ph[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20642 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][19] ph[6][0] ph[6][1] ph[6][2] ph[6][3] $abc$23348$new_n2885 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n2887 ph[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20644 +001 1 +011 1 +110 1 +111 1 +.names ph[6][3] ph[6][19] ph[6][0] ph[6][1] ph[6][2] $abc$23348$new_n2887 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$23348$new_n2889 ph[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20646 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] ph[6][2] ph[6][0] ph[6][1] $abc$23348$new_n2889 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[6][19] ph[6][0] ph[6][1] ph[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20648 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[6][0] ph[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20650 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][15] yv[6][14] $abc$23348$new_n2893 yv[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20652 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] $abc$23348$new_n2894 $abc$23348$new_n2906 $abc$23348$new_n2893 +000 1 +001 1 +101 1 +111 1 +.names xv[6][15] $abc$23348$new_n2895 yv[6][12] yv[6][13] $abc$23348$new_n2894 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[6][9] $abc$23348$new_n2903 $abc$23348$new_n2905 $abc$23348$new_n2896 $abc$23348$new_n2904 $abc$23348$new_n2895 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names xv[6][14] yv[6][7] $abc$23348$new_n2897 $abc$23348$new_n2896 +000 1 +001 1 +011 1 +101 1 +.names xv[6][12] yv[6][5] xv[6][13] yv[6][6] $abc$23348$new_n2898 $abc$23348$new_n2897 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][10] yv[6][3] xv[6][11] yv[6][4] $abc$23348$new_n2899 $abc$23348$new_n2898 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][9] yv[6][2] $abc$23348$new_n2900 $abc$23348$new_n2899 +000 1 +001 1 +011 1 +101 1 +.names xv[6][7] yv[6][0] xv[6][8] yv[6][1] $abc$23348$new_n2900 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[6][8] yv[6][9] $abc$23348$new_n2902 +00 1 +.names xv[6][15] yv[6][9] $abc$23348$new_n2903 +00 1 +11 1 +.names xv[6][15] yv[6][8] $abc$23348$new_n2904 +00 1 +11 1 +.names xv[6][15] yv[6][10] yv[6][11] $abc$23348$new_n2905 +011 1 +100 1 +.names xv[6][15] $abc$23348$new_n2907 yv[6][12] yv[6][13] $abc$23348$new_n2906 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][15] yv[6][10] yv[6][11] $abc$23348$new_n2908 $abc$23348$new_n2902 $abc$23348$new_n2907 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2904 $abc$23348$new_n2903 $abc$23348$new_n2909 $abc$23348$new_n2908 +110 1 +.names xv[6][13] xv[6][14] yv[6][6] yv[6][7] $abc$23348$new_n2910 $abc$23348$new_n2909 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][11] xv[6][12] yv[6][4] yv[6][5] $abc$23348$new_n2911 $abc$23348$new_n2910 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][9] xv[6][10] yv[6][2] yv[6][3] $abc$23348$new_n2912 $abc$23348$new_n2911 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[6][7] xv[6][8] yv[6][0] yv[6][1] $abc$23348$new_n2912 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[6][15] yv[6][13] $abc$23348$new_n2914 yv[7][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20654 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][15] yv[6][12] $abc$23348$new_n2907 $abc$23348$new_n2895 $abc$23348$new_n2914 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2916 yv[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20656 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] xv[6][15] yv[6][12] $abc$23348$new_n2907 $abc$23348$new_n2895 $abc$23348$new_n2916 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][15] yv[6][11] $abc$23348$new_n2918 yv[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20658 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][10] ph[6][19] $abc$23348$new_n2919 xv[6][15] $abc$23348$new_n2920 $abc$23348$new_n2918 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[6][19] $abc$23348$new_n2908 xv[6][15] $abc$23348$new_n2902 $abc$23348$new_n2919 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][15] $abc$23348$new_n2896 yv[6][8] yv[6][9] $abc$23348$new_n2920 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n2922 yv[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20660 +001 1 +011 1 +110 1 +111 1 +.names xv[6][15] yv[6][10] $abc$23348$new_n2919 $abc$23348$new_n2920 ph[6][19] $abc$23348$new_n2922 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n2903 $abc$23348$new_n2924 yv[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20662 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][19] yv[6][8] xv[6][15] $abc$23348$new_n2909 $abc$23348$new_n2896 $abc$23348$new_n2924 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n2926 yv[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20664 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] $abc$23348$new_n2904 $abc$23348$new_n2909 $abc$23348$new_n2896 $abc$23348$new_n2926 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[6][14] yv[6][7] $abc$23348$new_n2928 yv[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20666 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][13] yv[6][6] $abc$23348$new_n2910 $abc$23348$new_n2897 $abc$23348$new_n2928 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][13] yv[6][6] $abc$23348$new_n2930 yv[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20668 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][12] yv[6][5] $abc$23348$new_n2898 $abc$23348$new_n2910 $abc$23348$new_n2930 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][12] yv[6][5] $abc$23348$new_n2932 yv[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20670 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][11] yv[6][4] $abc$23348$new_n2911 $abc$23348$new_n2898 $abc$23348$new_n2932 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][11] yv[6][4] $abc$23348$new_n2934 yv[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20672 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][10] yv[6][3] $abc$23348$new_n2899 $abc$23348$new_n2911 $abc$23348$new_n2934 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][10] yv[6][3] $abc$23348$new_n2936 yv[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20674 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] yv[6][2] xv[6][9] $abc$23348$new_n2912 $abc$23348$new_n2900 $abc$23348$new_n2936 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][9] yv[6][2] $abc$23348$new_n2938 yv[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20676 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] $abc$23348$new_n2900 $abc$23348$new_n2912 $abc$23348$new_n2938 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[6][8] yv[6][1] $abc$23348$new_n2940 yv[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20678 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[6][7] ph[6][19] yv[6][0] $abc$23348$new_n2940 +101 1 +110 1 +.names i_ce xv[6][7] yv[6][0] yv[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20680 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[6][15] xv[6][14] $abc$23348$new_n2943 xv[7][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20682 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] $abc$23348$new_n2944 $abc$23348$new_n2955 $abc$23348$new_n2943 +000 1 +001 1 +101 1 +111 1 +.names yv[6][15] $abc$23348$new_n2945 xv[6][12] xv[6][13] $abc$23348$new_n2944 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][9] $abc$23348$new_n2952 $abc$23348$new_n2954 $abc$23348$new_n2946 $abc$23348$new_n2953 $abc$23348$new_n2945 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names xv[6][6] xv[6][7] yv[6][13] yv[6][14] $abc$23348$new_n2947 $abc$23348$new_n2946 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[6][12] xv[6][5] $abc$23348$new_n2948 $abc$23348$new_n2947 +001 1 +100 1 +101 1 +111 1 +.names yv[6][10] xv[6][3] xv[6][4] yv[6][11] $abc$23348$new_n2949 $abc$23348$new_n2948 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][9] xv[6][2] $abc$23348$new_n2950 $abc$23348$new_n2949 +001 1 +100 1 +101 1 +111 1 +.names yv[6][7] xv[6][0] xv[6][1] yv[6][8] $abc$23348$new_n2950 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[6][15] xv[6][9] $abc$23348$new_n2952 +01 1 +10 1 +.names yv[6][15] xv[6][8] $abc$23348$new_n2953 +01 1 +10 1 +.names yv[6][15] xv[6][10] xv[6][11] $abc$23348$new_n2954 +000 1 +111 1 +.names yv[6][15] $abc$23348$new_n2956 xv[6][12] xv[6][13] $abc$23348$new_n2955 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[6][8] $abc$23348$new_n2953 $abc$23348$new_n2963 $abc$23348$new_n2952 $abc$23348$new_n2957 $abc$23348$new_n2956 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][7] yv[6][14] $abc$23348$new_n2958 $abc$23348$new_n2957 +000 1 +001 1 +011 1 +101 1 +.names xv[6][5] yv[6][12] xv[6][6] yv[6][13] $abc$23348$new_n2959 $abc$23348$new_n2958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][3] yv[6][10] xv[6][4] yv[6][11] $abc$23348$new_n2960 $abc$23348$new_n2959 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][2] yv[6][9] $abc$23348$new_n2961 $abc$23348$new_n2960 +000 1 +001 1 +011 1 +101 1 +.names xv[6][0] yv[6][7] xv[6][1] yv[6][8] $abc$23348$new_n2961 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[6][15] xv[6][10] xv[6][11] $abc$23348$new_n2963 +011 1 +100 1 +.names i_ce yv[6][15] xv[6][13] $abc$23348$new_n2965 xv[7][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20684 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][12] yv[6][15] $abc$23348$new_n2956 $abc$23348$new_n2945 $abc$23348$new_n2965 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2967 xv[7][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20686 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] yv[6][15] xv[6][12] $abc$23348$new_n2956 $abc$23348$new_n2945 $abc$23348$new_n2967 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[6][15] xv[6][11] $abc$23348$new_n2969 xv[7][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20688 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][10] yv[6][15] $abc$23348$new_n2971 $abc$23348$new_n2970 $abc$23348$new_n2969 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[6][15] $abc$23348$new_n2957 xv[6][8] xv[6][9] $abc$23348$new_n2970 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[6][15] xv[6][8] xv[6][9] $abc$23348$new_n2946 $abc$23348$new_n2971 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$23348$new_n2973 xv[7][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20690 +001 1 +011 1 +100 1 +101 1 +.names yv[6][15] xv[6][10] ph[6][19] $abc$23348$new_n2971 $abc$23348$new_n2970 $abc$23348$new_n2973 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n2975 $abc$23348$new_n2952 xv[7][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20692 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][19] xv[6][8] yv[6][15] $abc$23348$new_n2957 $abc$23348$new_n2946 $abc$23348$new_n2975 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n2977 xv[7][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20694 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] $abc$23348$new_n2953 $abc$23348$new_n2957 $abc$23348$new_n2946 $abc$23348$new_n2977 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[6][7] yv[6][14] $abc$23348$new_n2979 xv[7][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20696 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][6] yv[6][13] $abc$23348$new_n2947 $abc$23348$new_n2958 $abc$23348$new_n2979 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][6] yv[6][13] $abc$23348$new_n2981 xv[7][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20698 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] yv[6][12] xv[6][5] $abc$23348$new_n2959 $abc$23348$new_n2948 $abc$23348$new_n2981 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2983 xv[7][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20700 +001 1 +011 1 +100 1 +101 1 +.names ph[6][19] xv[6][5] yv[6][12] $abc$23348$new_n2959 $abc$23348$new_n2948 $abc$23348$new_n2983 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][4] yv[6][11] $abc$23348$new_n2985 xv[7][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20702 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] yv[6][10] xv[6][3] $abc$23348$new_n2960 $abc$23348$new_n2949 $abc$23348$new_n2985 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2987 xv[7][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20704 +001 1 +011 1 +110 1 +111 1 +.names ph[6][19] xv[6][3] yv[6][10] $abc$23348$new_n2960 $abc$23348$new_n2949 $abc$23348$new_n2987 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][2] yv[6][9] $abc$23348$new_n2989 xv[7][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20706 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] $abc$23348$new_n2950 $abc$23348$new_n2961 $abc$23348$new_n2989 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[6][1] yv[6][8] $abc$23348$new_n2991 xv[7][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20708 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][7] ph[6][19] xv[6][0] $abc$23348$new_n2991 +100 1 +111 1 +.names i_ce xv[6][0] yv[6][7] xv[7][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20710 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n2994 ph[8][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20712 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][18] ph[7][17] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n2994 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n2996 ph[7][14] ph[7][15] ph[7][16] $abc$23348$new_n2995 +1000 1 +.names $abc$23348$new_n2997 ph[7][13] $abc$23348$new_n2996 +10 1 +.names ph[7][10] ph[7][11] ph[7][12] $abc$23348$new_n2998 $abc$23348$new_n2997 +0000 1 +.names ph[7][9] ph[7][8] ph[7][7] $abc$23348$new_n2999 $abc$23348$new_n2998 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][4] ph[7][5] ph[7][6] $abc$23348$new_n3000 $abc$23348$new_n2999 +0000 1 +.names ph[7][3] ph[7][2] ph[7][0] ph[7][1] $abc$23348$new_n3000 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][14] ph[7][15] ph[7][16] $abc$23348$new_n3002 $abc$23348$new_n3001 +1111 1 +.names ph[7][11] ph[7][12] ph[7][13] $abc$23348$new_n3003 $abc$23348$new_n3002 +1111 1 +.names ph[7][10] ph[7][8] ph[7][9] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3003 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[7][5] ph[7][6] $abc$23348$new_n3005 $abc$23348$new_n3004 +111 1 +.names ph[7][4] ph[7][2] ph[7][3] ph[7][1] ph[7][0] $abc$23348$new_n3005 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3007 ph[8][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20714 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][17] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n3007 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[7][16] $abc$23348$new_n3009 ph[8][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20716 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][19] ph[7][14] ph[7][15] $abc$23348$new_n2996 $abc$23348$new_n3002 $abc$23348$new_n3009 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3014 ph[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20720 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] ph[7][14] $abc$23348$new_n3002 $abc$23348$new_n2996 $abc$23348$new_n3014 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3019 ph[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20724 +001 1 +011 1 +110 1 +111 1 +.names ph[7][11] ph[7][12] $abc$23348$new_n3022 $abc$23348$new_n3020 $abc$23348$new_n3019 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n3021 ph[7][10] $abc$23348$new_n3020 +10 1 +.names ph[7][19] $abc$23348$new_n2998 $abc$23348$new_n3021 +00 1 +.names ph[7][10] $abc$23348$new_n3023 $abc$23348$new_n3022 +11 1 +.names ph[7][19] ph[7][8] ph[7][9] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3023 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[7][11] $abc$23348$new_n3022 $abc$23348$new_n3020 ph[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20726 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[7][10] $abc$23348$new_n3023 $abc$23348$new_n3021 ph[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20728 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3027 ph[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20730 +001 1 +011 1 +110 1 +111 1 +.names ph[7][9] ph[7][8] $abc$23348$new_n3029 $abc$23348$new_n3028 $abc$23348$new_n3027 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names ph[7][19] $abc$23348$new_n3004 ph[7][7] $abc$23348$new_n3028 +101 1 +110 1 +111 1 +.names ph[7][19] $abc$23348$new_n2999 ph[7][7] $abc$23348$new_n3029 +000 1 +010 1 +011 1 +.names i_ce ph[7][8] $abc$23348$new_n3029 $abc$23348$new_n3028 ph[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20732 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3032 ph[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20734 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] ph[7][7] $abc$23348$new_n3004 $abc$23348$new_n2999 $abc$23348$new_n3032 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3034 ph[7][6] ph[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20736 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][19] ph[7][5] $abc$23348$new_n3005 ph[7][4] $abc$23348$new_n3000 $abc$23348$new_n3034 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3036 ph[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20738 +001 1 +011 1 +110 1 +111 1 +.names ph[7][5] ph[7][19] ph[7][4] $abc$23348$new_n3000 $abc$23348$new_n3005 $abc$23348$new_n3036 +00000 1 +00001 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3038 ph[7][4] ph[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20740 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][19] ph[7][3] ph[7][0] ph[7][1] ph[7][2] $abc$23348$new_n3038 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +.names i_ce $abc$23348$new_n3040 ph[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20742 +001 1 +011 1 +110 1 +111 1 +.names ph[7][3] ph[7][19] ph[7][2] ph[7][0] ph[7][1] $abc$23348$new_n3040 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +10000 1 +10001 1 +10010 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3042 ph[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20744 +001 1 +011 1 +110 1 +111 1 +.names ph[7][2] ph[7][19] ph[7][0] ph[7][1] $abc$23348$new_n3042 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce ph[7][19] ph[7][0] ph[7][1] ph[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20746 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[7][0] ph[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20748 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[7][15] yv[7][14] $abc$23348$new_n3046 yv[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20750 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] $abc$23348$new_n3047 $abc$23348$new_n3055 $abc$23348$new_n3046 +000 1 +001 1 +101 1 +111 1 +.names xv[7][15] $abc$23348$new_n3048 yv[7][12] yv[7][13] $abc$23348$new_n3047 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[7][15] yv[7][10] yv[7][11] $abc$23348$new_n3049 $abc$23348$new_n3054 $abc$23348$new_n3048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[7][8] yv[7][9] xv[7][15] yv[7][7] $abc$23348$new_n3050 $abc$23348$new_n3049 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[7][13] yv[7][5] xv[7][14] yv[7][6] $abc$23348$new_n3051 $abc$23348$new_n3050 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][11] yv[7][3] xv[7][12] yv[7][4] $abc$23348$new_n3052 $abc$23348$new_n3051 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][10] yv[7][2] $abc$23348$new_n3053 $abc$23348$new_n3052 +000 1 +001 1 +011 1 +101 1 +.names xv[7][8] yv[7][0] xv[7][9] yv[7][1] $abc$23348$new_n3053 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[7][8] yv[7][9] $abc$23348$new_n3054 +00 1 +.names xv[7][15] $abc$23348$new_n3056 yv[7][12] yv[7][13] $abc$23348$new_n3055 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[7][15] yv[7][10] yv[7][11] $abc$23348$new_n3057 $abc$23348$new_n3054 $abc$23348$new_n3056 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[7][15] yv[7][8] yv[7][9] $abc$23348$new_n3058 $abc$23348$new_n3057 +0000 1 +1110 1 +.names xv[7][14] xv[7][15] yv[7][6] yv[7][7] $abc$23348$new_n3059 $abc$23348$new_n3058 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][12] xv[7][13] yv[7][4] yv[7][5] $abc$23348$new_n3060 $abc$23348$new_n3059 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][10] xv[7][11] yv[7][2] yv[7][3] $abc$23348$new_n3061 $abc$23348$new_n3060 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[7][8] xv[7][9] yv[7][0] yv[7][1] $abc$23348$new_n3061 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[7][15] yv[7][13] $abc$23348$new_n3063 yv[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20752 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][12] $abc$23348$new_n3056 $abc$23348$new_n3048 $abc$23348$new_n3063 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3065 yv[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20754 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][15] yv[7][12] $abc$23348$new_n3056 $abc$23348$new_n3048 $abc$23348$new_n3065 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][15] yv[7][11] $abc$23348$new_n3067 yv[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20756 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][10] $abc$23348$new_n3069 $abc$23348$new_n3068 $abc$23348$new_n3067 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3057 $abc$23348$new_n3054 xv[7][15] $abc$23348$new_n3068 +001 1 +010 1 +011 1 +.names $abc$23348$new_n3049 $abc$23348$new_n3054 xv[7][15] $abc$23348$new_n3069 +000 1 +010 1 +011 1 +.names i_ce xv[7][15] yv[7][10] $abc$23348$new_n3071 yv[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20758 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] $abc$23348$new_n3068 $abc$23348$new_n3069 $abc$23348$new_n3071 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[7][15] yv[7][9] $abc$23348$new_n3073 yv[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20760 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] yv[7][8] xv[7][15] $abc$23348$new_n3058 $abc$23348$new_n3074 $abc$23348$new_n3073 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[7][15] yv[7][7] $abc$23348$new_n3050 $abc$23348$new_n3074 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3076 yv[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20762 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][15] yv[7][8] $abc$23348$new_n3058 $abc$23348$new_n3074 $abc$23348$new_n3076 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][15] yv[7][7] $abc$23348$new_n3078 yv[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20764 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][14] yv[7][6] $abc$23348$new_n3059 $abc$23348$new_n3050 $abc$23348$new_n3078 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][14] yv[7][6] $abc$23348$new_n3080 yv[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20766 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][13] yv[7][5] $abc$23348$new_n3051 $abc$23348$new_n3059 $abc$23348$new_n3080 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][13] yv[7][5] $abc$23348$new_n3082 yv[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20768 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][12] yv[7][4] $abc$23348$new_n3060 $abc$23348$new_n3051 $abc$23348$new_n3082 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][12] yv[7][4] $abc$23348$new_n3084 yv[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20770 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][11] yv[7][3] $abc$23348$new_n3052 $abc$23348$new_n3060 $abc$23348$new_n3084 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][11] yv[7][3] $abc$23348$new_n3086 yv[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20772 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][10] yv[7][2] $abc$23348$new_n3061 $abc$23348$new_n3053 $abc$23348$new_n3086 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][10] yv[7][2] $abc$23348$new_n3088 yv[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20774 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3053 $abc$23348$new_n3061 $abc$23348$new_n3088 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3090 yv[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20776 +001 1 +011 1 +110 1 +111 1 +.names xv[7][9] yv[7][1] ph[7][19] yv[7][0] xv[7][8] $abc$23348$new_n3090 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[7][8] yv[7][0] yv[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20778 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[7][15] xv[7][14] $abc$23348$new_n3093 xv[8][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20780 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3094 $abc$23348$new_n3102 $abc$23348$new_n3093 +000 1 +001 1 +101 1 +111 1 +.names yv[7][15] $abc$23348$new_n3095 xv[7][12] xv[7][13] $abc$23348$new_n3094 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[7][15] xv[7][10] xv[7][11] $abc$23348$new_n3096 $abc$23348$new_n3101 $abc$23348$new_n3095 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3097 yv[7][15] xv[7][8] xv[7][9] $abc$23348$new_n3096 +1000 1 +1111 1 +.names xv[7][6] yv[7][14] yv[7][15] xv[7][7] $abc$23348$new_n3098 $abc$23348$new_n3097 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[7][12] xv[7][4] xv[7][5] yv[7][13] $abc$23348$new_n3099 $abc$23348$new_n3098 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][10] xv[7][2] xv[7][3] yv[7][11] $abc$23348$new_n3100 $abc$23348$new_n3099 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][8] xv[7][0] xv[7][1] yv[7][9] $abc$23348$new_n3100 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[7][8] xv[7][9] $abc$23348$new_n3101 +00 1 +.names yv[7][15] $abc$23348$new_n3103 xv[7][12] xv[7][13] $abc$23348$new_n3102 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[7][15] xv[7][10] xv[7][11] $abc$23348$new_n3104 $abc$23348$new_n3101 $abc$23348$new_n3103 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[7][8] xv[7][9] yv[7][15] xv[7][7] $abc$23348$new_n3105 $abc$23348$new_n3104 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[7][5] yv[7][13] xv[7][6] yv[7][14] $abc$23348$new_n3106 $abc$23348$new_n3105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3106 +000 1 +001 1 +011 1 +101 1 +.names xv[7][2] yv[7][10] xv[7][3] yv[7][11] $abc$23348$new_n3108 $abc$23348$new_n3107 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][0] yv[7][8] xv[7][1] yv[7][9] $abc$23348$new_n3108 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[7][15] xv[7][13] $abc$23348$new_n3110 xv[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20782 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][12] yv[7][15] $abc$23348$new_n3103 $abc$23348$new_n3095 $abc$23348$new_n3110 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3112 xv[8][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20784 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] yv[7][15] xv[7][12] $abc$23348$new_n3103 $abc$23348$new_n3095 $abc$23348$new_n3112 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[7][15] xv[7][11] $abc$23348$new_n3114 xv[8][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20786 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][10] yv[7][15] $abc$23348$new_n3116 $abc$23348$new_n3115 $abc$23348$new_n3114 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3104 $abc$23348$new_n3101 yv[7][15] $abc$23348$new_n3115 +000 1 +010 1 +011 1 +.names $abc$23348$new_n3096 $abc$23348$new_n3101 yv[7][15] $abc$23348$new_n3116 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3118 xv[8][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20788 +001 1 +011 1 +100 1 +101 1 +.names yv[7][15] xv[7][10] ph[7][19] $abc$23348$new_n3116 $abc$23348$new_n3115 $abc$23348$new_n3118 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[7][15] xv[7][9] $abc$23348$new_n3120 xv[8][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20790 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][8] yv[7][15] $abc$23348$new_n3097 $abc$23348$new_n3121 $abc$23348$new_n3120 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[7][15] xv[7][7] $abc$23348$new_n3105 $abc$23348$new_n3121 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3123 xv[8][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20792 +001 1 +011 1 +100 1 +101 1 +.names yv[7][15] xv[7][8] ph[7][19] $abc$23348$new_n3097 $abc$23348$new_n3121 $abc$23348$new_n3123 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce yv[7][15] xv[7][7] $abc$23348$new_n3125 xv[8][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20794 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][6] yv[7][14] $abc$23348$new_n3098 $abc$23348$new_n3105 $abc$23348$new_n3125 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][6] yv[7][14] $abc$23348$new_n3127 xv[8][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20796 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][5] yv[7][13] $abc$23348$new_n3106 $abc$23348$new_n3098 $abc$23348$new_n3127 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[7][5] yv[7][13] $abc$23348$new_n3129 xv[8][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20798 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3099 $abc$23348$new_n3129 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3131 xv[8][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20800 +001 1 +011 1 +100 1 +101 1 +.names ph[7][19] xv[7][4] yv[7][12] $abc$23348$new_n3107 $abc$23348$new_n3099 $abc$23348$new_n3131 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[7][3] yv[7][11] $abc$23348$new_n3133 xv[8][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20802 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][2] yv[7][10] $abc$23348$new_n3108 $abc$23348$new_n3100 $abc$23348$new_n3133 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[7][2] yv[7][10] $abc$23348$new_n3135 xv[8][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20804 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] $abc$23348$new_n3100 $abc$23348$new_n3108 $abc$23348$new_n3135 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[7][1] yv[7][9] $abc$23348$new_n3137 xv[8][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20806 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][8] ph[7][19] xv[7][0] $abc$23348$new_n3137 +100 1 +111 1 +.names i_ce xv[7][0] yv[7][8] xv[8][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20808 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[8][18] $abc$23348$new_n3140 ph[9][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20810 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n3148 $abc$23348$new_n3141 $abc$23348$new_n3140 +00000 1 +00001 1 +11101 1 +.names ph[8][14] ph[8][15] $abc$23348$new_n3142 $abc$23348$new_n3141 +111 1 +.names ph[8][13] $abc$23348$new_n3147 $abc$23348$new_n3143 $abc$23348$new_n3142 +111 1 +.names ph[8][9] $abc$23348$new_n3144 ph[8][8] $abc$23348$new_n3143 +101 1 +110 1 +111 1 +.names ph[8][7] ph[8][6] ph[8][5] $abc$23348$new_n3145 $abc$23348$new_n3144 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][4] $abc$23348$new_n3146 $abc$23348$new_n3145 +11 1 +.names ph[8][3] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3146 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$23348$new_n3147 +111 1 +.names ph[8][19] $abc$23348$new_n3149 ph[8][14] ph[8][15] $abc$23348$new_n3148 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$23348$new_n3150 $abc$23348$new_n3154 ph[8][13] $abc$23348$new_n3149 +110 1 +.names ph[8][9] $abc$23348$new_n3151 ph[8][8] $abc$23348$new_n3150 +000 1 +010 1 +011 1 +.names ph[8][7] ph[8][6] $abc$23348$new_n3152 ph[8][5] $abc$23348$new_n3151 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$23348$new_n3153 ph[8][4] $abc$23348$new_n3152 +10 1 +.names ph[8][3] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3153 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$23348$new_n3154 +000 1 +.names i_ce $abc$23348$new_n3156 ph[9][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20812 +001 1 +011 1 +110 1 +111 1 +.names ph[8][17] ph[8][19] ph[8][16] $abc$23348$new_n3148 $abc$23348$new_n3141 $abc$23348$new_n3156 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3158 ph[9][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20814 +001 1 +011 1 +110 1 +111 1 +.names ph[8][16] $abc$23348$new_n3148 ph[8][19] $abc$23348$new_n3141 $abc$23348$new_n3158 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3163 ph[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20818 +001 1 +011 1 +110 1 +111 1 +.names ph[8][14] ph[8][19] $abc$23348$new_n3149 $abc$23348$new_n3142 $abc$23348$new_n3163 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$23348$new_n3168 ph[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20822 +001 1 +011 1 +110 1 +111 1 +.names ph[8][10] ph[8][12] ph[8][11] $abc$23348$new_n3170 $abc$23348$new_n3169 $abc$23348$new_n3168 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[8][19] $abc$23348$new_n3143 $abc$23348$new_n3169 +11 1 +.names $abc$23348$new_n3150 ph[8][19] $abc$23348$new_n3170 +10 1 +.names i_ce $abc$23348$new_n3172 ph[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20824 +001 1 +011 1 +110 1 +111 1 +.names ph[8][11] ph[8][10] $abc$23348$new_n3170 $abc$23348$new_n3169 $abc$23348$new_n3172 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[8][10] $abc$23348$new_n3170 $abc$23348$new_n3169 ph[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20826 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3175 ph[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20828 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] ph[8][9] ph[8][8] $abc$23348$new_n3151 $abc$23348$new_n3144 $abc$23348$new_n3175 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3177 ph[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20830 +001 1 +011 1 +110 1 +111 1 +.names ph[8][8] ph[8][19] $abc$23348$new_n3151 $abc$23348$new_n3144 $abc$23348$new_n3177 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[8][7] $abc$23348$new_n3179 ph[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20832 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][5] ph[8][6] $abc$23348$new_n3145 $abc$23348$new_n3152 $abc$23348$new_n3179 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3181 ph[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20834 +001 1 +011 1 +100 1 +101 1 +.names ph[8][4] ph[8][6] ph[8][5] $abc$23348$new_n3183 $abc$23348$new_n3182 $abc$23348$new_n3181 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3153 ph[8][19] $abc$23348$new_n3182 +10 1 +.names ph[8][19] $abc$23348$new_n3146 $abc$23348$new_n3183 +11 1 +.names i_ce $abc$23348$new_n3185 ph[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20836 +001 1 +011 1 +100 1 +101 1 +.names ph[8][4] ph[8][5] $abc$23348$new_n3183 $abc$23348$new_n3182 $abc$23348$new_n3185 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[8][4] $abc$23348$new_n3183 $abc$23348$new_n3182 ph[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20838 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3188 ph[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20840 +001 1 +011 1 +110 1 +111 1 +.names ph[8][3] ph[8][19] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3188 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3190 ph[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20842 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] ph[8][2] ph[8][0] ph[8][1] $abc$23348$new_n3190 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[8][19] ph[8][0] ph[8][1] ph[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20844 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[8][0] ph[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20846 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[8][15] yv[8][14] $abc$23348$new_n3194 yv[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20848 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3195 $abc$23348$new_n3204 $abc$23348$new_n3194 +000 1 +001 1 +101 1 +111 1 +.names xv[8][15] yv[8][12] yv[8][13] $abc$23348$new_n3196 $abc$23348$new_n3202 $abc$23348$new_n3195 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$23348$new_n3197 xv[8][15] yv[8][9] yv[8][10] yv[8][11] $abc$23348$new_n3196 +10111 1 +11000 1 +.names yv[8][8] xv[8][15] yv[8][6] yv[8][7] $abc$23348$new_n3198 $abc$23348$new_n3197 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[8][14] yv[8][5] $abc$23348$new_n3199 $abc$23348$new_n3198 +000 1 +001 1 +011 1 +101 1 +.names xv[8][12] yv[8][3] xv[8][13] yv[8][4] $abc$23348$new_n3200 $abc$23348$new_n3199 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][11] yv[8][2] $abc$23348$new_n3201 $abc$23348$new_n3200 +000 1 +001 1 +011 1 +101 1 +.names xv[8][9] yv[8][0] xv[8][10] yv[8][1] $abc$23348$new_n3201 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$23348$new_n3203 yv[8][10] yv[8][11] $abc$23348$new_n3202 +100 1 +.names yv[8][8] yv[8][9] $abc$23348$new_n3203 +00 1 +.names xv[8][15] $abc$23348$new_n3205 yv[8][12] yv[8][13] $abc$23348$new_n3204 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[8][15] yv[8][10] yv[8][11] $abc$23348$new_n3206 $abc$23348$new_n3203 $abc$23348$new_n3205 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][15] yv[8][8] yv[8][9] $abc$23348$new_n3207 $abc$23348$new_n3206 +0000 1 +1110 1 +.names xv[8][15] $abc$23348$new_n3208 yv[8][6] yv[8][7] $abc$23348$new_n3207 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[8][13] xv[8][14] yv[8][4] yv[8][5] $abc$23348$new_n3209 $abc$23348$new_n3208 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][11] xv[8][12] yv[8][2] yv[8][3] $abc$23348$new_n3210 $abc$23348$new_n3209 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[8][9] xv[8][10] yv[8][0] yv[8][1] $abc$23348$new_n3210 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[8][15] yv[8][13] $abc$23348$new_n3212 yv[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20850 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][12] $abc$23348$new_n3205 $abc$23348$new_n3213 $abc$23348$new_n3212 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3196 $abc$23348$new_n3202 xv[8][15] $abc$23348$new_n3213 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3215 yv[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20852 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][15] yv[8][12] $abc$23348$new_n3205 $abc$23348$new_n3213 $abc$23348$new_n3215 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][15] yv[8][11] $abc$23348$new_n3217 yv[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20854 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][10] $abc$23348$new_n3219 $abc$23348$new_n3218 $abc$23348$new_n3217 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3206 $abc$23348$new_n3203 xv[8][15] $abc$23348$new_n3218 +001 1 +010 1 +011 1 +.names xv[8][15] $abc$23348$new_n3197 yv[8][9] $abc$23348$new_n3203 $abc$23348$new_n3219 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1111 1 +.names i_ce xv[8][15] yv[8][10] $abc$23348$new_n3221 yv[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20856 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3218 $abc$23348$new_n3219 $abc$23348$new_n3221 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[8][15] yv[8][9] $abc$23348$new_n3223 yv[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20858 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] yv[8][8] xv[8][15] $abc$23348$new_n3207 $abc$23348$new_n3224 $abc$23348$new_n3223 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][15] $abc$23348$new_n3198 yv[8][6] yv[8][7] $abc$23348$new_n3224 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3226 yv[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20860 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][15] yv[8][8] $abc$23348$new_n3207 $abc$23348$new_n3224 $abc$23348$new_n3226 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][15] yv[8][7] $abc$23348$new_n3228 yv[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20862 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] yv[8][6] xv[8][15] $abc$23348$new_n3208 $abc$23348$new_n3198 $abc$23348$new_n3228 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n3230 yv[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20864 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] xv[8][15] yv[8][6] $abc$23348$new_n3208 $abc$23348$new_n3198 $abc$23348$new_n3230 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][14] yv[8][5] $abc$23348$new_n3232 yv[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20866 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][13] yv[8][4] $abc$23348$new_n3209 $abc$23348$new_n3199 $abc$23348$new_n3232 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][13] yv[8][4] $abc$23348$new_n3234 yv[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20868 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][12] yv[8][3] $abc$23348$new_n3200 $abc$23348$new_n3209 $abc$23348$new_n3234 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][12] yv[8][3] $abc$23348$new_n3236 yv[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20870 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][11] yv[8][2] $abc$23348$new_n3210 $abc$23348$new_n3201 $abc$23348$new_n3236 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][11] yv[8][2] $abc$23348$new_n3238 yv[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20872 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3201 $abc$23348$new_n3210 $abc$23348$new_n3238 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3240 yv[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20874 +001 1 +011 1 +110 1 +111 1 +.names xv[8][10] yv[8][1] ph[8][19] yv[8][0] xv[8][9] $abc$23348$new_n3240 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[8][9] yv[8][0] yv[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20876 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[8][15] xv[8][14] $abc$23348$new_n3243 xv[9][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20878 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3244 $abc$23348$new_n3254 $abc$23348$new_n3243 +000 1 +001 1 +101 1 +111 1 +.names yv[8][15] xv[8][12] xv[8][13] $abc$23348$new_n3245 $abc$23348$new_n3252 $abc$23348$new_n3244 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3251 yv[8][15] xv[8][8] xv[8][9] $abc$23348$new_n3246 $abc$23348$new_n3245 +10000 1 +11110 1 +.names yv[8][15] $abc$23348$new_n3247 xv[8][6] xv[8][7] $abc$23348$new_n3246 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[8][14] xv[8][5] $abc$23348$new_n3248 $abc$23348$new_n3247 +001 1 +100 1 +101 1 +111 1 +.names yv[8][12] xv[8][3] xv[8][4] yv[8][13] $abc$23348$new_n3249 $abc$23348$new_n3248 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][11] xv[8][2] $abc$23348$new_n3250 $abc$23348$new_n3249 +001 1 +100 1 +101 1 +111 1 +.names yv[8][9] xv[8][0] xv[8][1] yv[8][10] $abc$23348$new_n3250 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[8][15] xv[8][10] xv[8][11] $abc$23348$new_n3251 +000 1 +111 1 +.names $abc$23348$new_n3253 xv[8][10] xv[8][11] $abc$23348$new_n3252 +100 1 +.names xv[8][8] xv[8][9] $abc$23348$new_n3253 +00 1 +.names yv[8][15] $abc$23348$new_n3255 xv[8][12] xv[8][13] $abc$23348$new_n3254 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[8][15] xv[8][10] xv[8][11] $abc$23348$new_n3256 $abc$23348$new_n3253 $abc$23348$new_n3255 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[8][8] xv[8][9] yv[8][15] xv[8][7] $abc$23348$new_n3257 $abc$23348$new_n3256 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[8][5] yv[8][14] yv[8][15] xv[8][6] $abc$23348$new_n3258 $abc$23348$new_n3257 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][3] yv[8][12] xv[8][4] yv[8][13] $abc$23348$new_n3259 $abc$23348$new_n3258 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][2] yv[8][11] $abc$23348$new_n3260 $abc$23348$new_n3259 +000 1 +001 1 +011 1 +101 1 +.names xv[8][0] yv[8][9] xv[8][1] yv[8][10] $abc$23348$new_n3260 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[8][15] xv[8][13] $abc$23348$new_n3262 xv[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20880 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][12] yv[8][15] $abc$23348$new_n3255 $abc$23348$new_n3263 $abc$23348$new_n3262 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$23348$new_n3245 $abc$23348$new_n3252 yv[8][15] $abc$23348$new_n3263 +001 1 +010 1 +011 1 +.names i_ce yv[8][15] xv[8][12] $abc$23348$new_n3265 xv[9][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20882 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3263 $abc$23348$new_n3255 $abc$23348$new_n3265 +000 1 +001 1 +101 1 +111 1 +.names i_ce yv[8][15] xv[8][11] $abc$23348$new_n3267 xv[9][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20884 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][10] yv[8][15] $abc$23348$new_n3269 $abc$23348$new_n3268 $abc$23348$new_n3267 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3256 $abc$23348$new_n3253 yv[8][15] $abc$23348$new_n3268 +000 1 +010 1 +011 1 +.names yv[8][15] $abc$23348$new_n3246 xv[8][8] xv[8][9] $abc$23348$new_n3269 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce yv[8][15] xv[8][10] $abc$23348$new_n3271 xv[9][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20886 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] $abc$23348$new_n3268 $abc$23348$new_n3269 $abc$23348$new_n3271 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[8][15] xv[8][9] $abc$23348$new_n3273 xv[9][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20888 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][8] yv[8][15] $abc$23348$new_n3274 $abc$23348$new_n3246 $abc$23348$new_n3273 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[8][15] xv[8][7] $abc$23348$new_n3257 $abc$23348$new_n3274 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3276 xv[9][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20890 +001 1 +011 1 +100 1 +101 1 +.names ph[8][19] yv[8][15] xv[8][8] $abc$23348$new_n3274 $abc$23348$new_n3246 $abc$23348$new_n3276 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[8][15] xv[8][7] $abc$23348$new_n3278 xv[9][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20892 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][6] yv[8][15] $abc$23348$new_n3247 $abc$23348$new_n3257 $abc$23348$new_n3278 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce yv[8][15] xv[8][6] $abc$23348$new_n3280 xv[9][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20894 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] yv[8][14] xv[8][5] $abc$23348$new_n3258 $abc$23348$new_n3248 $abc$23348$new_n3280 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3282 xv[9][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20896 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] xv[8][5] yv[8][14] $abc$23348$new_n3258 $abc$23348$new_n3248 $abc$23348$new_n3282 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][4] yv[8][13] $abc$23348$new_n3284 xv[9][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20898 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][3] yv[8][12] $abc$23348$new_n3259 $abc$23348$new_n3249 $abc$23348$new_n3284 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[8][3] yv[8][12] $abc$23348$new_n3286 xv[9][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20900 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3249 $abc$23348$new_n3259 $abc$23348$new_n3286 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][2] yv[8][11] $abc$23348$new_n3288 xv[9][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20902 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] $abc$23348$new_n3250 $abc$23348$new_n3260 $abc$23348$new_n3288 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3290 xv[9][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20904 +001 1 +011 1 +110 1 +111 1 +.names xv[8][1] yv[8][10] ph[8][19] xv[8][0] yv[8][9] $abc$23348$new_n3290 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[8][0] yv[8][9] xv[9][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20906 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3293 ph[10][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$20908 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] ph[9][18] ph[9][17] $abc$23348$new_n3299 $abc$23348$new_n3294 $abc$23348$new_n3293 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[9][14] ph[9][15] ph[9][16] $abc$23348$new_n3295 $abc$23348$new_n3294 +1111 1 +.names ph[9][10] ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3296 $abc$23348$new_n3295 +11111 1 +.names ph[9][9] ph[9][8] $abc$23348$new_n3297 ph[9][7] $abc$23348$new_n3296 +1101 1 +1110 1 +1111 1 +.names ph[9][6] $abc$23348$new_n3298 $abc$23348$new_n3297 +10 1 +.names ph[9][5] ph[9][3] ph[9][4] ph[9][1] ph[9][2] $abc$23348$new_n3298 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$23348$new_n3300 ph[9][14] ph[9][15] ph[9][16] $abc$23348$new_n3299 +1000 1 +.names $abc$23348$new_n3301 ph[9][10] ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3300 +10000 1 +.names ph[9][9] ph[9][8] $abc$23348$new_n3302 ph[9][7] $abc$23348$new_n3301 +0000 1 +0010 1 +0011 1 +.names ph[9][6] $abc$23348$new_n3303 $abc$23348$new_n3302 +00 1 +.names ph[9][5] ph[9][3] ph[9][4] ph[9][1] ph[9][2] $abc$23348$new_n3303 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3305 ph[10][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$20910 +001 1 +011 1 +100 1 +101 1 +.names ph[9][17] ph[9][19] $abc$23348$new_n3299 $abc$23348$new_n3294 $abc$23348$new_n3305 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[9][16] $abc$23348$new_n3307 ph[10][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$20912 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[9][19] ph[9][14] ph[9][15] $abc$23348$new_n3295 $abc$23348$new_n3300 $abc$23348$new_n3307 +00001 1 +00011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3309 ph[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20914 +001 1 +011 1 +110 1 +111 1 +.names ph[9][15] ph[9][14] $abc$23348$new_n3313 $abc$23348$new_n3310 $abc$23348$new_n3309 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names ph[9][11] ph[9][12] ph[9][13] $abc$23348$new_n3311 $abc$23348$new_n3310 +1111 1 +.names ph[9][10] $abc$23348$new_n3312 $abc$23348$new_n3311 +11 1 +.names ph[9][19] $abc$23348$new_n3296 $abc$23348$new_n3312 +11 1 +.names $abc$23348$new_n3300 ph[9][19] $abc$23348$new_n3313 +10 1 +.names i_ce ph[9][14] $abc$23348$new_n3313 $abc$23348$new_n3310 ph[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20916 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3316 ph[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20918 +001 1 +011 1 +100 1 +101 1 +.names ph[9][13] ph[9][11] ph[9][12] $abc$23348$new_n3317 $abc$23348$new_n3311 $abc$23348$new_n3316 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3318 ph[9][10] $abc$23348$new_n3317 +10 1 +.names $abc$23348$new_n3301 ph[9][19] $abc$23348$new_n3318 +10 1 +.names $abc$23348$new_n3320 ph[10][12] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$20920 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[9][12] ph[9][11] $abc$23348$new_n3317 $abc$23348$new_n3311 $abc$23348$new_n3320 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[9][11] $abc$23348$new_n3317 $abc$23348$new_n3311 ph[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20922 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][10] $abc$23348$new_n3318 $abc$23348$new_n3312 ph[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20924 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3324 ph[9][9] ph[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20926 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][19] ph[9][7] ph[9][8] $abc$23348$new_n3297 $abc$23348$new_n3302 $abc$23348$new_n3324 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3326 ph[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20928 +001 1 +011 1 +110 1 +111 1 +.names ph[9][8] ph[9][19] ph[9][7] $abc$23348$new_n3302 $abc$23348$new_n3297 $abc$23348$new_n3326 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n3328 ph[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20930 +001 1 +011 1 +110 1 +111 1 +.names ph[9][6] ph[9][7] $abc$23348$new_n3330 $abc$23348$new_n3329 $abc$23348$new_n3328 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][19] $abc$23348$new_n3303 $abc$23348$new_n3329 +00 1 +.names ph[9][19] $abc$23348$new_n3298 $abc$23348$new_n3330 +10 1 +.names i_ce ph[9][6] $abc$23348$new_n3330 $abc$23348$new_n3329 ph[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20932 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][5] $abc$23348$new_n3333 ph[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20934 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[9][19] ph[9][1] ph[9][2] ph[9][3] ph[9][4] $abc$23348$new_n3333 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3335 ph[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20936 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] ph[9][4] ph[9][1] ph[9][2] ph[9][3] $abc$23348$new_n3335 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3337 ph[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20938 +001 1 +011 1 +100 1 +101 1 +.names ph[9][3] ph[9][19] ph[9][1] ph[9][2] $abc$23348$new_n3337 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[9][19] ph[9][1] ph[9][2] ph[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20940 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[9][1] ph[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20942 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[9][0] ph[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20944 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[9][15] yv[9][14] $abc$23348$new_n3342 yv[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20946 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] $abc$23348$new_n3343 $abc$23348$new_n3351 $abc$23348$new_n3342 +000 1 +001 1 +101 1 +111 1 +.names xv[9][15] $abc$23348$new_n3344 yv[9][12] yv[9][13] $abc$23348$new_n3343 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[9][15] yv[9][10] yv[9][11] $abc$23348$new_n3345 $abc$23348$new_n3350 $abc$23348$new_n3344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[9][15] yv[9][8] yv[9][9] $abc$23348$new_n3346 $abc$23348$new_n3345 +0110 1 +1000 1 +.names xv[9][15] $abc$23348$new_n3347 yv[9][5] yv[9][6] yv[9][7] $abc$23348$new_n3346 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[9][13] yv[9][3] xv[9][14] yv[9][4] $abc$23348$new_n3348 $abc$23348$new_n3347 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][12] yv[9][2] $abc$23348$new_n3349 $abc$23348$new_n3348 +000 1 +001 1 +011 1 +101 1 +.names xv[9][10] yv[9][0] xv[9][11] yv[9][1] $abc$23348$new_n3349 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][8] yv[9][9] $abc$23348$new_n3350 +00 1 +.names xv[9][15] $abc$23348$new_n3352 yv[9][12] yv[9][13] $abc$23348$new_n3351 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[9][15] yv[9][10] yv[9][11] $abc$23348$new_n3353 $abc$23348$new_n3350 $abc$23348$new_n3352 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][15] yv[9][9] yv[9][8] yv[9][7] $abc$23348$new_n3354 $abc$23348$new_n3353 +00000 1 +00010 1 +00011 1 +11110 1 +.names xv[9][15] yv[9][6] $abc$23348$new_n3355 $abc$23348$new_n3354 +001 1 +100 1 +101 1 +111 1 +.names xv[9][14] xv[9][15] yv[9][4] yv[9][5] $abc$23348$new_n3356 $abc$23348$new_n3355 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][12] xv[9][13] yv[9][2] yv[9][3] $abc$23348$new_n3357 $abc$23348$new_n3356 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[9][10] xv[9][11] yv[9][0] yv[9][1] $abc$23348$new_n3357 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[9][15] yv[9][13] $abc$23348$new_n3359 yv[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20948 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][12] $abc$23348$new_n3352 $abc$23348$new_n3344 $abc$23348$new_n3359 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3361 yv[10][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20950 +001 1 +011 1 +100 1 +101 1 +.names ph[9][19] xv[9][15] yv[9][12] $abc$23348$new_n3352 $abc$23348$new_n3344 $abc$23348$new_n3361 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][15] yv[9][11] $abc$23348$new_n3363 yv[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20952 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][10] $abc$23348$new_n3365 $abc$23348$new_n3364 $abc$23348$new_n3363 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$23348$new_n3353 $abc$23348$new_n3350 xv[9][15] $abc$23348$new_n3364 +001 1 +010 1 +011 1 +.names $abc$23348$new_n3345 $abc$23348$new_n3350 xv[9][15] $abc$23348$new_n3365 +000 1 +010 1 +011 1 +.names i_ce xv[9][15] yv[9][10] $abc$23348$new_n3367 yv[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20954 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] $abc$23348$new_n3364 $abc$23348$new_n3365 $abc$23348$new_n3367 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[9][15] yv[9][9] $abc$23348$new_n3369 yv[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20956 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] yv[9][8] xv[9][15] $abc$23348$new_n3346 $abc$23348$new_n3370 $abc$23348$new_n3369 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[9][15] yv[9][7] $abc$23348$new_n3354 $abc$23348$new_n3370 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3372 yv[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20958 +001 1 +011 1 +110 1 +111 1 +.names xv[9][15] yv[9][8] ph[9][19] $abc$23348$new_n3346 $abc$23348$new_n3370 $abc$23348$new_n3372 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][15] yv[9][7] $abc$23348$new_n3374 yv[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20960 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] yv[9][6] xv[9][15] $abc$23348$new_n3355 $abc$23348$new_n3375 $abc$23348$new_n3374 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][15] yv[9][5] $abc$23348$new_n3347 $abc$23348$new_n3375 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3377 yv[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20962 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] xv[9][15] yv[9][6] $abc$23348$new_n3355 $abc$23348$new_n3375 $abc$23348$new_n3377 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[9][15] yv[9][5] $abc$23348$new_n3379 yv[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20964 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][14] yv[9][4] $abc$23348$new_n3356 $abc$23348$new_n3347 $abc$23348$new_n3379 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][14] yv[9][4] $abc$23348$new_n3381 yv[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20966 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][13] yv[9][3] $abc$23348$new_n3348 $abc$23348$new_n3356 $abc$23348$new_n3381 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][13] yv[9][3] $abc$23348$new_n3383 yv[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20968 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][12] yv[9][2] $abc$23348$new_n3357 $abc$23348$new_n3349 $abc$23348$new_n3383 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][12] yv[9][2] $abc$23348$new_n3385 yv[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$20970 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3349 $abc$23348$new_n3357 $abc$23348$new_n3385 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3387 yv[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$20972 +001 1 +011 1 +110 1 +111 1 +.names xv[9][11] yv[9][1] ph[9][19] yv[9][0] xv[9][10] $abc$23348$new_n3387 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[9][10] yv[9][0] yv[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$20974 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[9][15] xv[9][14] $abc$23348$new_n3390 xv[10][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$20976 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3391 $abc$23348$new_n3399 $abc$23348$new_n3390 +000 1 +001 1 +101 1 +111 1 +.names yv[9][15] $abc$23348$new_n3392 xv[9][12] xv[9][13] $abc$23348$new_n3391 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[9][15] xv[9][10] xv[9][11] $abc$23348$new_n3393 $abc$23348$new_n3398 $abc$23348$new_n3392 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][15] xv[9][8] xv[9][9] $abc$23348$new_n3394 $abc$23348$new_n3393 +0000 1 +1110 1 +.names yv[9][15] $abc$23348$new_n3395 xv[9][5] xv[9][6] xv[9][7] $abc$23348$new_n3394 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[9][14] xv[9][4] $abc$23348$new_n3396 $abc$23348$new_n3395 +001 1 +100 1 +101 1 +111 1 +.names yv[9][12] xv[9][2] xv[9][3] yv[9][13] $abc$23348$new_n3397 $abc$23348$new_n3396 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][10] xv[9][0] xv[9][1] yv[9][11] $abc$23348$new_n3397 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[9][8] xv[9][9] $abc$23348$new_n3398 +00 1 +.names yv[9][15] $abc$23348$new_n3400 xv[9][12] xv[9][13] $abc$23348$new_n3399 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[9][15] xv[9][10] xv[9][11] $abc$23348$new_n3401 $abc$23348$new_n3398 $abc$23348$new_n3400 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[9][15] xv[9][8] xv[9][9] $abc$23348$new_n3402 $abc$23348$new_n3401 +0110 1 +1000 1 +.names yv[9][15] $abc$23348$new_n3403 xv[9][5] xv[9][6] xv[9][7] $abc$23348$new_n3402 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[9][3] yv[9][13] xv[9][4] yv[9][14] $abc$23348$new_n3404 $abc$23348$new_n3403 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][2] yv[9][12] $abc$23348$new_n3405 $abc$23348$new_n3404 +000 1 +001 1 +011 1 +101 1 +.names xv[9][0] yv[9][10] xv[9][1] yv[9][11] $abc$23348$new_n3405 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce yv[9][15] xv[9][13] $abc$23348$new_n3407 xv[10][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20978 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][12] yv[9][15] $abc$23348$new_n3400 $abc$23348$new_n3392 $abc$23348$new_n3407 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3409 xv[10][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20980 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] yv[9][15] xv[9][12] $abc$23348$new_n3400 $abc$23348$new_n3392 $abc$23348$new_n3409 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[9][15] xv[9][11] $abc$23348$new_n3411 xv[10][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20982 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][10] yv[9][15] $abc$23348$new_n3413 $abc$23348$new_n3412 $abc$23348$new_n3411 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3401 $abc$23348$new_n3398 yv[9][15] $abc$23348$new_n3412 +000 1 +010 1 +011 1 +.names $abc$23348$new_n3393 $abc$23348$new_n3398 yv[9][15] $abc$23348$new_n3413 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3415 xv[10][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$20984 +001 1 +011 1 +100 1 +101 1 +.names yv[9][15] xv[9][10] ph[9][19] $abc$23348$new_n3413 $abc$23348$new_n3412 $abc$23348$new_n3415 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[9][15] xv[9][9] $abc$23348$new_n3417 xv[10][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20986 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][8] yv[9][15] $abc$23348$new_n3402 $abc$23348$new_n3394 $abc$23348$new_n3417 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3419 xv[10][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$20988 +001 1 +011 1 +100 1 +101 1 +.names ph[9][19] yv[9][15] xv[9][8] $abc$23348$new_n3402 $abc$23348$new_n3394 $abc$23348$new_n3419 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[9][15] xv[9][7] $abc$23348$new_n3421 xv[10][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$20990 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][6] yv[9][15] $abc$23348$new_n3423 $abc$23348$new_n3422 $abc$23348$new_n3421 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[9][15] xv[9][5] $abc$23348$new_n3395 $abc$23348$new_n3422 +001 1 +100 1 +101 1 +111 1 +.names yv[9][15] xv[9][5] $abc$23348$new_n3403 $abc$23348$new_n3423 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3425 xv[10][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$20992 +001 1 +011 1 +110 1 +111 1 +.names ph[9][19] yv[9][15] xv[9][6] $abc$23348$new_n3423 $abc$23348$new_n3422 $abc$23348$new_n3425 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[9][15] xv[9][5] $abc$23348$new_n3427 xv[10][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20994 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3395 $abc$23348$new_n3403 $abc$23348$new_n3427 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[9][4] yv[9][14] $abc$23348$new_n3429 xv[10][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$20996 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][3] yv[9][13] $abc$23348$new_n3404 $abc$23348$new_n3396 $abc$23348$new_n3429 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[9][3] yv[9][13] $abc$23348$new_n3431 xv[10][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$20998 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][2] yv[9][12] $abc$23348$new_n3405 $abc$23348$new_n3397 $abc$23348$new_n3431 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[9][2] yv[9][12] $abc$23348$new_n3433 xv[10][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21000 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] $abc$23348$new_n3397 $abc$23348$new_n3405 $abc$23348$new_n3433 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3435 xv[10][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21002 +001 1 +011 1 +110 1 +111 1 +.names xv[9][1] yv[9][11] ph[9][19] xv[9][0] yv[9][10] $abc$23348$new_n3435 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[9][0] yv[9][10] xv[10][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21004 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[10][18] $abc$23348$new_n3438 ph[11][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21006 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][16] ph[10][17] $abc$23348$new_n3445 $abc$23348$new_n3439 $abc$23348$new_n3438 +00000 1 +00001 1 +11101 1 +.names ph[10][14] ph[10][15] $abc$23348$new_n3440 $abc$23348$new_n3439 +111 1 +.names ph[10][13] $abc$23348$new_n3441 $abc$23348$new_n3440 +11 1 +.names ph[10][9] ph[10][10] ph[10][11] ph[10][12] $abc$23348$new_n3442 $abc$23348$new_n3441 +11111 1 +.names ph[10][8] ph[10][7] $abc$23348$new_n3443 ph[10][6] $abc$23348$new_n3442 +1101 1 +1110 1 +1111 1 +.names ph[10][5] $abc$23348$new_n3444 $abc$23348$new_n3443 +10 1 +.names ph[10][4] ph[10][2] ph[10][3] ph[10][0] ph[10][1] $abc$23348$new_n3444 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[10][19] $abc$23348$new_n3446 ph[10][14] ph[10][15] ph[10][13] $abc$23348$new_n3445 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$23348$new_n3447 ph[10][9] ph[10][10] ph[10][11] ph[10][12] $abc$23348$new_n3446 +10000 1 +.names ph[10][8] ph[10][7] $abc$23348$new_n3448 ph[10][6] $abc$23348$new_n3447 +0000 1 +0010 1 +0011 1 +.names ph[10][5] $abc$23348$new_n3449 $abc$23348$new_n3448 +00 1 +.names ph[10][4] ph[10][2] ph[10][3] ph[10][0] ph[10][1] $abc$23348$new_n3449 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3451 ph[11][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21008 +001 1 +011 1 +110 1 +111 1 +.names ph[10][17] ph[10][19] ph[10][16] $abc$23348$new_n3445 $abc$23348$new_n3439 $abc$23348$new_n3451 +00000 1 +00001 1 +01101 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3453 ph[11][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21010 +001 1 +011 1 +110 1 +111 1 +.names ph[10][16] $abc$23348$new_n3445 ph[10][19] $abc$23348$new_n3439 $abc$23348$new_n3453 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3458 ph[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21014 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][14] ph[10][13] $abc$23348$new_n3446 $abc$23348$new_n3441 $abc$23348$new_n3458 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$23348$new_n3460 ph[11][13] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$21016 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][13] ph[10][19] $abc$23348$new_n3446 $abc$23348$new_n3441 $abc$23348$new_n3460 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3462 ph[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21018 +001 1 +011 1 +110 1 +111 1 +.names ph[10][10] ph[10][12] ph[10][11] $abc$23348$new_n3465 $abc$23348$new_n3463 $abc$23348$new_n3462 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10][9] $abc$23348$new_n3464 $abc$23348$new_n3463 +11 1 +.names ph[10][19] $abc$23348$new_n3442 $abc$23348$new_n3464 +11 1 +.names $abc$23348$new_n3466 ph[10][9] $abc$23348$new_n3465 +10 1 +.names $abc$23348$new_n3447 ph[10][19] $abc$23348$new_n3466 +10 1 +.names i_ce $abc$23348$new_n3468 ph[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21020 +001 1 +011 1 +110 1 +111 1 +.names ph[10][11] ph[10][10] $abc$23348$new_n3465 $abc$23348$new_n3463 $abc$23348$new_n3468 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][10] $abc$23348$new_n3465 $abc$23348$new_n3463 ph[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21022 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][9] $abc$23348$new_n3466 $abc$23348$new_n3464 ph[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21024 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3472 ph[10][8] ph[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21026 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] ph[10][6] ph[10][7] $abc$23348$new_n3443 $abc$23348$new_n3448 $abc$23348$new_n3472 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3474 ph[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21028 +001 1 +011 1 +110 1 +111 1 +.names ph[10][7] ph[10][19] ph[10][6] $abc$23348$new_n3448 $abc$23348$new_n3443 $abc$23348$new_n3474 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$23348$new_n3476 ph[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21030 +001 1 +011 1 +110 1 +111 1 +.names ph[10][6] ph[10][19] ph[10][5] $abc$23348$new_n3449 $abc$23348$new_n3444 $abc$23348$new_n3476 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3478 ph[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21032 +001 1 +011 1 +100 1 +101 1 +.names ph[10][5] ph[10][19] $abc$23348$new_n3449 $abc$23348$new_n3444 $abc$23348$new_n3478 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][4] $abc$23348$new_n3480 ph[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21034 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][0] ph[10][1] ph[10][2] ph[10][3] $abc$23348$new_n3480 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3482 ph[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21036 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][3] ph[10][0] ph[10][1] ph[10][2] $abc$23348$new_n3482 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3484 ph[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21038 +001 1 +011 1 +100 1 +101 1 +.names ph[10][2] ph[10][19] ph[10][0] ph[10][1] $abc$23348$new_n3484 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce ph[10][19] ph[10][0] ph[10][1] ph[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21040 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[10][0] ph[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21042 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[10][15] yv[10][14] $abc$23348$new_n3488 yv[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21044 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] $abc$23348$new_n3489 $abc$23348$new_n3501 $abc$23348$new_n3488 +000 1 +001 1 +101 1 +111 1 +.names xv[10][15] $abc$23348$new_n3490 yv[10][12] yv[10][13] $abc$23348$new_n3489 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$23348$new_n3496 $abc$23348$new_n3491 $abc$23348$new_n3499 $abc$23348$new_n3498 $abc$23348$new_n3500 $abc$23348$new_n3490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names yv[10][8] xv[10][15] yv[10][6] yv[10][7] $abc$23348$new_n3492 $abc$23348$new_n3491 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[10][15] yv[10][4] yv[10][5] $abc$23348$new_n3493 $abc$23348$new_n3492 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[10][14] yv[10][3] $abc$23348$new_n3494 $abc$23348$new_n3493 +010 1 +100 1 +110 1 +111 1 +.names xv[10][13] yv[10][2] $abc$23348$new_n3495 $abc$23348$new_n3494 +000 1 +001 1 +011 1 +101 1 +.names xv[10][11] yv[10][0] xv[10][12] yv[10][1] $abc$23348$new_n3495 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][15] $abc$23348$new_n3497 yv[10][10] yv[10][11] $abc$23348$new_n3496 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[10][8] yv[10][9] $abc$23348$new_n3497 +00 1 +.names xv[10][15] yv[10][9] $abc$23348$new_n3498 +00 1 +11 1 +.names xv[10][15] yv[10][11] $abc$23348$new_n3499 +00 1 +11 1 +.names xv[10][15] yv[10][10] $abc$23348$new_n3500 +00 1 +11 1 +.names xv[10][15] $abc$23348$new_n3502 yv[10][12] yv[10][13] $abc$23348$new_n3501 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[10][15] $abc$23348$new_n3511 $abc$23348$new_n3498 $abc$23348$new_n3510 $abc$23348$new_n3503 $abc$23348$new_n3502 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[10][15] yv[10][6] yv[10][7] $abc$23348$new_n3504 $abc$23348$new_n3508 $abc$23348$new_n3503 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3505 xv[10][15] yv[10][5] $abc$23348$new_n3504 +100 1 +111 1 +.names xv[10][14] yv[10][3] xv[10][15] yv[10][4] $abc$23348$new_n3506 $abc$23348$new_n3505 +00001 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +11001 1 +11111 1 +.names yv[10][2] xv[10][13] $abc$23348$new_n3507 $abc$23348$new_n3506 +001 1 +100 1 +101 1 +111 1 +.names xv[10][11] xv[10][12] yv[10][0] yv[10][1] $abc$23348$new_n3507 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[10][4] yv[10][5] $abc$23348$new_n3508 +00 1 +.names $abc$23348$new_n3500 $abc$23348$new_n3499 $abc$23348$new_n3510 +11 1 +.names xv[10][15] yv[10][8] $abc$23348$new_n3511 +00 1 +11 1 +.names i_ce xv[10][15] yv[10][13] $abc$23348$new_n3513 yv[11][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21046 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][12] $abc$23348$new_n3502 $abc$23348$new_n3490 $abc$23348$new_n3513 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3515 yv[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21048 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] xv[10][15] yv[10][12] $abc$23348$new_n3502 $abc$23348$new_n3490 $abc$23348$new_n3515 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4370 $abc$23348$new_n3499 yv[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21050 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n4372 $abc$23348$new_n3500 yv[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21052 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3525 $abc$23348$new_n3498 yv[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21054 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] xv[10][15] yv[10][8] $abc$23348$new_n3503 $abc$23348$new_n3526 $abc$23348$new_n3525 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[10][15] $abc$23348$new_n3492 yv[10][6] yv[10][7] $abc$23348$new_n3526 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3528 yv[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21056 +001 1 +011 1 +100 1 +101 1 +.names ph[10][19] $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n3526 $abc$23348$new_n3528 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][15] yv[10][7] $abc$23348$new_n3530 yv[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21058 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][6] ph[10][19] $abc$23348$new_n3531 xv[10][15] $abc$23348$new_n3492 $abc$23348$new_n3530 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[10][19] $abc$23348$new_n3504 xv[10][15] $abc$23348$new_n3508 $abc$23348$new_n3531 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3533 yv[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21060 +001 1 +011 1 +110 1 +111 1 +.names xv[10][15] yv[10][6] $abc$23348$new_n3531 $abc$23348$new_n3492 ph[10][19] $abc$23348$new_n3533 +00000 1 +00001 1 +00011 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names i_ce xv[10][15] yv[10][5] $abc$23348$new_n3535 yv[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21062 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][4] $abc$23348$new_n3505 $abc$23348$new_n3493 $abc$23348$new_n3535 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_ce xv[10][15] yv[10][4] $abc$23348$new_n3537 yv[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21064 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][14] yv[10][3] $abc$23348$new_n3506 $abc$23348$new_n3494 $abc$23348$new_n3537 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[10][14] yv[10][3] $abc$23348$new_n3539 yv[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21066 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3494 $abc$23348$new_n3506 $abc$23348$new_n3539 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[10][13] yv[10][2] $abc$23348$new_n3541 yv[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21068 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3495 $abc$23348$new_n3507 $abc$23348$new_n3541 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3543 yv[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21070 +001 1 +011 1 +110 1 +111 1 +.names xv[10][12] yv[10][1] ph[10][19] yv[10][0] xv[10][11] $abc$23348$new_n3543 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[10][11] yv[10][0] yv[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21072 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[10][15] xv[10][14] $abc$23348$new_n3546 xv[11][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21074 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3547 $abc$23348$new_n3557 $abc$23348$new_n3546 +000 1 +001 1 +101 1 +111 1 +.names yv[10][15] $abc$23348$new_n3548 xv[10][12] xv[10][13] $abc$23348$new_n3547 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][15] xv[10][10] xv[10][11] $abc$23348$new_n3549 $abc$23348$new_n3556 $abc$23348$new_n3548 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3555 $abc$23348$new_n3554 $abc$23348$new_n3550 $abc$23348$new_n3549 +000 1 +.names yv[10][15] $abc$23348$new_n3551 xv[10][6] xv[10][7] $abc$23348$new_n3550 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][15] $abc$23348$new_n3552 xv[10][4] xv[10][5] $abc$23348$new_n3551 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[10][13] xv[10][2] xv[10][3] yv[10][14] $abc$23348$new_n3553 $abc$23348$new_n3552 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][11] xv[10][0] xv[10][1] yv[10][12] $abc$23348$new_n3553 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[10][15] xv[10][9] $abc$23348$new_n3554 +01 1 +10 1 +.names yv[10][15] xv[10][8] $abc$23348$new_n3555 +01 1 +10 1 +.names xv[10][8] xv[10][9] $abc$23348$new_n3556 +00 1 +.names yv[10][15] $abc$23348$new_n3558 xv[10][12] xv[10][13] $abc$23348$new_n3557 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[10][15] $abc$23348$new_n3566 $abc$23348$new_n3555 $abc$23348$new_n3554 $abc$23348$new_n3559 $abc$23348$new_n3558 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11111 1 +.names yv[10][15] xv[10][6] xv[10][7] $abc$23348$new_n3560 $abc$23348$new_n3564 $abc$23348$new_n3559 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$23348$new_n3561 yv[10][15] xv[10][5] $abc$23348$new_n3560 +101 1 +110 1 +.names yv[10][15] xv[10][4] xv[10][3] yv[10][14] $abc$23348$new_n3562 $abc$23348$new_n3561 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +.names xv[10][2] yv[10][13] $abc$23348$new_n3563 $abc$23348$new_n3562 +000 1 +001 1 +011 1 +101 1 +.names xv[10][0] yv[10][11] xv[10][1] yv[10][12] $abc$23348$new_n3563 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][4] xv[10][5] $abc$23348$new_n3564 +00 1 +.names yv[10][15] xv[10][10] xv[10][11] $abc$23348$new_n3566 +011 1 +100 1 +.names i_ce yv[10][15] xv[10][13] $abc$23348$new_n3568 xv[11][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21076 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][12] yv[10][15] $abc$23348$new_n3558 $abc$23348$new_n3548 $abc$23348$new_n3568 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3570 xv[11][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21078 +001 1 +011 1 +100 1 +101 1 +.names ph[10][19] yv[10][15] xv[10][12] $abc$23348$new_n3558 $abc$23348$new_n3548 $abc$23348$new_n3570 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[10][15] xv[10][11] $abc$23348$new_n3572 xv[11][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21080 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][10] yv[10][15] $abc$23348$new_n3574 $abc$23348$new_n3573 $abc$23348$new_n3572 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[10][15] $abc$23348$new_n3559 xv[10][8] xv[10][9] $abc$23348$new_n3573 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$23348$new_n3549 $abc$23348$new_n3556 yv[10][15] $abc$23348$new_n3574 +001 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3576 xv[11][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21082 +001 1 +011 1 +110 1 +111 1 +.names yv[10][15] xv[10][10] ph[10][19] $abc$23348$new_n3574 $abc$23348$new_n3573 $abc$23348$new_n3576 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3578 $abc$23348$new_n3554 xv[11][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21084 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][19] xv[10][8] yv[10][15] $abc$23348$new_n3550 $abc$23348$new_n3559 $abc$23348$new_n3578 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$23348$new_n3580 xv[11][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21086 +001 1 +011 1 +100 1 +101 1 +.names $abc$23348$new_n3555 ph[10][19] $abc$23348$new_n3550 $abc$23348$new_n3559 $abc$23348$new_n3580 +0000 1 +0001 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names i_ce yv[10][15] xv[10][7] $abc$23348$new_n3582 xv[11][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21088 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][6] yv[10][15] $abc$23348$new_n3551 $abc$23348$new_n3583 $abc$23348$new_n3582 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3560 $abc$23348$new_n3564 yv[10][15] $abc$23348$new_n3583 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3585 xv[11][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21090 +001 1 +011 1 +100 1 +101 1 +.names yv[10][15] xv[10][6] ph[10][19] $abc$23348$new_n3551 $abc$23348$new_n3583 $abc$23348$new_n3585 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[10][15] xv[10][5] $abc$23348$new_n3587 xv[11][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21092 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][4] yv[10][15] $abc$23348$new_n3552 $abc$23348$new_n3561 $abc$23348$new_n3587 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce yv[10][15] xv[10][4] $abc$23348$new_n3589 xv[11][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21094 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][3] yv[10][14] $abc$23348$new_n3562 $abc$23348$new_n3552 $abc$23348$new_n3589 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[10][3] yv[10][14] $abc$23348$new_n3591 xv[11][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21096 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][2] yv[10][13] $abc$23348$new_n3563 $abc$23348$new_n3553 $abc$23348$new_n3591 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[10][2] yv[10][13] $abc$23348$new_n3593 xv[11][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21098 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] $abc$23348$new_n3553 $abc$23348$new_n3563 $abc$23348$new_n3593 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3595 xv[11][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21100 +001 1 +011 1 +110 1 +111 1 +.names xv[10][1] yv[10][12] ph[10][19] xv[10][0] yv[10][11] $abc$23348$new_n3595 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[10][0] yv[10][11] xv[11][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21102 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3598 ph[12][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21104 +001 1 +011 1 +100 1 +101 1 +.names ph[11][18] ph[11][19] ph[11][17] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n3598 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3600 ph[11][16] $abc$23348$new_n3599 +10 1 +.names $abc$23348$new_n3601 ph[11][13] ph[11][14] ph[11][15] $abc$23348$new_n3600 +1000 1 +.names $abc$23348$new_n3602 $abc$23348$new_n3604 ph[11][12] $abc$23348$new_n3601 +110 1 +.names $abc$23348$new_n3603 ph[11][10] ph[11][11] $abc$23348$new_n3602 +100 1 +.names ph[11][7] ph[11][8] ph[11][9] $abc$23348$new_n3603 +000 1 +.names ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3604 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[11][16] $abc$23348$new_n3606 $abc$23348$new_n3605 +11 1 +.names ph[11][13] ph[11][14] ph[11][15] $abc$23348$new_n3607 $abc$23348$new_n3606 +1111 1 +.names ph[11][12] $abc$23348$new_n3608 $abc$23348$new_n3607 +11 1 +.names $abc$23348$new_n3609 ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3608 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[11][7] ph[11][8] ph[11][9] ph[11][10] ph[11][11] $abc$23348$new_n3609 +11111 1 +.names i_ce $abc$23348$new_n3611 ph[12][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21106 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][17] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n3611 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3613 ph[12][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21108 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][16] $abc$23348$new_n3606 $abc$23348$new_n3600 $abc$23348$new_n3613 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[11][15] $abc$23348$new_n3615 ph[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21110 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[11][19] ph[11][13] ph[11][14] $abc$23348$new_n3601 $abc$23348$new_n3607 $abc$23348$new_n3615 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3620 ph[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21114 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] ph[11][13] $abc$23348$new_n3607 $abc$23348$new_n3601 $abc$23348$new_n3620 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3622 ph[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21116 +001 1 +011 1 +110 1 +111 1 +.names ph[11][12] ph[11][19] $abc$23348$new_n3604 $abc$23348$new_n3602 $abc$23348$new_n3608 $abc$23348$new_n3622 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3624 ph[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21118 +001 1 +011 1 +110 1 +111 1 +.names ph[11][11] ph[11][10] $abc$23348$new_n3603 $abc$23348$new_n3625 $abc$23348$new_n3626 $abc$23348$new_n3624 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$23348$new_n3604 ph[11][19] $abc$23348$new_n3625 +10 1 +.names ph[11][7] ph[11][8] ph[11][9] $abc$23348$new_n3627 $abc$23348$new_n3626 +1111 1 +.names ph[11][19] ph[11][6] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3627 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3629 ph[11][10] ph[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21120 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$23348$new_n3626 $abc$23348$new_n3625 $abc$23348$new_n3603 $abc$23348$new_n3629 +000 1 +001 1 +010 1 +.names i_ce ph[12][9] $abc$23348$new_n3631 $abc$23348$new_n3626 $abc$23348$auto$rtlil.cc:2693:MuxGate$21122 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names ph[11][9] ph[11][7] ph[11][8] $abc$23348$new_n3625 $abc$23348$new_n3627 $abc$23348$new_n3631 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +.names i_ce $abc$23348$new_n3633 ph[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21124 +001 1 +011 1 +110 1 +111 1 +.names ph[11][7] ph[11][8] $abc$23348$new_n3627 $abc$23348$new_n3625 $abc$23348$new_n3633 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[11][7] $abc$23348$new_n3627 $abc$23348$new_n3625 ph[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21126 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3636 ph[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21128 +001 1 +011 1 +110 1 +111 1 +.names ph[11][6] ph[11][19] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3638 ph[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21130 +001 1 +011 1 +100 1 +101 1 +.names ph[11][19] ph[11][5] ph[11][3] ph[11][4] $abc$23348$new_n3638 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[11][19] ph[11][3] ph[11][4] ph[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21132 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[11][3] ph[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21134 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[11][2] ph[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21136 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[11][1] ph[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21138 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[11][0] ph[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21140 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[11][15] yv[11][14] $abc$23348$new_n3645 yv[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21142 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3646 $abc$23348$new_n3653 $abc$23348$new_n3645 +000 1 +001 1 +101 1 +111 1 +.names xv[11][15] $abc$23348$new_n3647 yv[11][12] yv[11][13] $abc$23348$new_n3646 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3648 yv[11][10] yv[11][11] $abc$23348$new_n3647 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3649 yv[11][8] yv[11][9] $abc$23348$new_n3648 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3650 yv[11][6] yv[11][7] $abc$23348$new_n3649 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3651 yv[11][3] yv[11][4] yv[11][5] $abc$23348$new_n3650 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[11][14] yv[11][2] $abc$23348$new_n3652 $abc$23348$new_n3651 +000 1 +001 1 +011 1 +101 1 +.names xv[11][12] yv[11][0] xv[11][13] yv[11][1] $abc$23348$new_n3652 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[11][15] $abc$23348$new_n3654 yv[11][11] yv[11][12] yv[11][13] $abc$23348$new_n3653 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][15] yv[11][9] yv[11][10] $abc$23348$new_n3655 $abc$23348$new_n3654 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[11][8] xv[11][15] $abc$23348$new_n4376 $abc$23348$new_n3655 +000 1 +100 1 +101 1 +110 1 +.names yv[11][2] xv[11][14] $abc$23348$new_n3659 $abc$23348$new_n3658 +001 1 +100 1 +101 1 +111 1 +.names xv[11][12] xv[11][13] yv[11][0] yv[11][1] $abc$23348$new_n3659 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[11][15] yv[11][13] $abc$23348$new_n3662 yv[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21144 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] yv[11][12] xv[11][15] $abc$23348$new_n3647 $abc$23348$new_n3663 $abc$23348$new_n3662 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[11][15] yv[11][11] $abc$23348$new_n3654 $abc$23348$new_n3663 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[11][15] yv[11][12] $abc$23348$new_n3665 yv[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21146 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3663 $abc$23348$new_n3647 $abc$23348$new_n3665 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[11][15] yv[11][11] $abc$23348$new_n3667 yv[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21148 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] yv[11][10] xv[11][15] $abc$23348$new_n3648 $abc$23348$new_n3668 $abc$23348$new_n3667 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[11][15] yv[11][9] $abc$23348$new_n3655 $abc$23348$new_n3668 +000 1 +100 1 +101 1 +110 1 +.names i_ce $abc$23348$new_n3670 yv[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21150 +001 1 +011 1 +110 1 +111 1 +.names xv[11][15] yv[11][10] ph[11][19] $abc$23348$new_n3648 $abc$23348$new_n3668 $abc$23348$new_n3670 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[11][15] yv[11][9] $abc$23348$new_n3672 yv[12][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21152 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][8] $abc$23348$new_n4376 $abc$23348$new_n3649 $abc$23348$new_n3672 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3674 yv[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21154 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] xv[11][15] yv[11][8] $abc$23348$new_n4376 $abc$23348$new_n3649 $abc$23348$new_n3674 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][7] $abc$23348$new_n3676 yv[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21156 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][6] ph[11][19] $abc$23348$new_n3677 xv[11][15] $abc$23348$new_n3650 $abc$23348$new_n3676 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names ph[11][19] xv[11][15] yv[11][5] $abc$23348$new_n3678 yv[11][4] $abc$23348$new_n3677 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names xv[11][15] yv[11][4] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3678 +0001 1 +0010 1 +0011 1 +1111 1 +.names i_ce $abc$23348$new_n3680 yv[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21158 +001 1 +011 1 +100 1 +101 1 +.names xv[11][15] yv[11][6] $abc$23348$new_n3677 $abc$23348$new_n3650 ph[11][19] $abc$23348$new_n3680 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][5] $abc$23348$new_n3682 yv[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21160 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] yv[11][4] $abc$23348$new_n3685 xv[11][15] $abc$23348$new_n3682 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_ce xv[11][15] yv[11][4] $abc$23348$new_n3685 yv[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3651 $abc$23348$new_n3685 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n3687 yv[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21164 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] xv[11][15] yv[11][3] $abc$23348$new_n3658 $abc$23348$new_n3651 $abc$23348$new_n3687 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][14] yv[11][2] $abc$23348$new_n3689 yv[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21166 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] $abc$23348$new_n3652 $abc$23348$new_n3659 $abc$23348$new_n3689 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$23348$new_n3691 yv[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21168 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][1] ph[11][19] yv[11][0] xv[11][12] $abc$23348$new_n3691 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[11][12] yv[11][0] yv[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21170 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3694 xv[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21172 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][14] $abc$23348$new_n3702 $abc$23348$new_n3695 $abc$23348$new_n3694 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][15] $abc$23348$new_n3696 xv[11][12] xv[11][13] $abc$23348$new_n3695 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3697 xv[11][10] xv[11][11] $abc$23348$new_n3696 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3698 xv[11][8] xv[11][9] $abc$23348$new_n3697 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3699 xv[11][6] xv[11][7] $abc$23348$new_n3698 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[11][15] $abc$23348$new_n3700 xv[11][3] xv[11][4] xv[11][5] $abc$23348$new_n3699 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[11][14] xv[11][2] $abc$23348$new_n3701 $abc$23348$new_n3700 +001 1 +100 1 +101 1 +111 1 +.names yv[11][12] xv[11][0] xv[11][1] yv[11][13] $abc$23348$new_n3701 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[11][15] $abc$23348$new_n3703 xv[11][12] xv[11][13] $abc$23348$new_n3702 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] $abc$23348$new_n3704 xv[11][10] xv[11][11] $abc$23348$new_n3703 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] $abc$23348$new_n3705 xv[11][8] xv[11][9] $abc$23348$new_n3704 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[11][15] xv[11][6] xv[11][7] $abc$23348$new_n3706 $abc$23348$new_n3709 $abc$23348$new_n3705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[11][4] xv[11][5] yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3706 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[11][2] yv[11][14] $abc$23348$new_n3708 $abc$23348$new_n3707 +000 1 +001 1 +011 1 +101 1 +.names xv[11][0] yv[11][12] xv[11][1] yv[11][13] $abc$23348$new_n3708 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[11][4] xv[11][5] $abc$23348$new_n3709 +00 1 +.names i_ce yv[11][15] xv[11][13] $abc$23348$new_n3711 xv[12][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21174 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][12] yv[11][15] $abc$23348$new_n3703 $abc$23348$new_n3696 $abc$23348$new_n3711 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3713 xv[12][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21176 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][12] $abc$23348$new_n3703 $abc$23348$new_n3696 $abc$23348$new_n3713 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][11] $abc$23348$new_n3715 xv[12][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21178 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][10] yv[11][15] $abc$23348$new_n3704 $abc$23348$new_n3697 $abc$23348$new_n3715 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3717 xv[12][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21180 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][10] $abc$23348$new_n3704 $abc$23348$new_n3697 $abc$23348$new_n3717 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][9] $abc$23348$new_n3719 xv[12][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21182 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][8] yv[11][15] $abc$23348$new_n3705 $abc$23348$new_n3698 $abc$23348$new_n3719 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3721 xv[12][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21184 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][8] $abc$23348$new_n3705 $abc$23348$new_n3698 $abc$23348$new_n3721 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[11][15] xv[11][7] $abc$23348$new_n3723 xv[12][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21186 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][6] yv[11][15] $abc$23348$new_n3699 $abc$23348$new_n3724 $abc$23348$new_n3723 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3706 $abc$23348$new_n3709 yv[11][15] $abc$23348$new_n3724 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3726 xv[12][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21188 +001 1 +011 1 +100 1 +101 1 +.names yv[11][15] xv[11][6] ph[11][19] $abc$23348$new_n3699 $abc$23348$new_n3724 $abc$23348$new_n3726 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[11][15] xv[11][5] $abc$23348$new_n3728 xv[12][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21190 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] yv[11][15] xv[11][4] $abc$23348$new_n3730 $abc$23348$new_n3729 $abc$23348$new_n3728 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[11][15] xv[11][3] $abc$23348$new_n3700 $abc$23348$new_n3729 +001 1 +100 1 +101 1 +111 1 +.names yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3730 +010 1 +100 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n3732 xv[12][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21192 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][4] $abc$23348$new_n3730 $abc$23348$new_n3729 $abc$23348$new_n3732 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3734 xv[12][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21194 +001 1 +011 1 +110 1 +111 1 +.names ph[11][19] yv[11][15] xv[11][3] $abc$23348$new_n3707 $abc$23348$new_n3700 $abc$23348$new_n3734 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][2] yv[11][14] $abc$23348$new_n3736 xv[12][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21196 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] $abc$23348$new_n3701 $abc$23348$new_n3708 $abc$23348$new_n3736 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3738 xv[12][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21198 +001 1 +011 1 +110 1 +111 1 +.names xv[11][1] yv[11][13] ph[11][19] xv[11][0] yv[11][12] $abc$23348$new_n3738 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[11][0] yv[11][12] xv[12][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21200 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3741 ph[13][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21202 +001 1 +011 1 +100 1 +101 1 +.names ph[12][18] $abc$23348$new_n3746 ph[12][19] $abc$23348$new_n3742 ph[12][17] $abc$23348$new_n3741 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$23348$new_n3743 ph[12][14] ph[12][15] ph[12][16] $abc$23348$new_n3742 +1000 1 +.names $abc$23348$new_n3744 ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$23348$new_n3743 +10000 1 +.names $abc$23348$new_n3745 ph[12][6] ph[12][7] ph[12][8] ph[12][9] $abc$23348$new_n3744 +10000 1 +.names ph[12][5] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3745 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[12][19] $abc$23348$new_n3747 ph[12][17] $abc$23348$new_n3746 +100 1 +101 1 +110 1 +.names ph[12][13] ph[12][16] $abc$23348$new_n3750 $abc$23348$new_n3749 $abc$23348$new_n3748 $abc$23348$new_n3747 +11111 1 +.names ph[12][6] ph[12][7] ph[12][8] ph[12][14] ph[12][15] $abc$23348$new_n3748 +11111 1 +.names ph[12][5] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3749 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[12][9] ph[12][10] ph[12][11] ph[12][12] $abc$23348$new_n3750 +1111 1 +.names i_ce $abc$23348$new_n3752 ph[13][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21204 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] ph[12][17] $abc$23348$new_n3747 $abc$23348$new_n3742 $abc$23348$new_n3752 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3754 ph[13][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21206 +001 1 +011 1 +100 1 +101 1 +.names ph[12][16] ph[12][14] ph[12][15] $abc$23348$new_n3760 $abc$23348$new_n3755 $abc$23348$new_n3754 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names $abc$23348$new_n3756 ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$23348$new_n3755 +10000 1 +.names $abc$23348$new_n3757 ph[12][8] ph[12][9] $abc$23348$new_n3756 +100 1 +.names $abc$23348$new_n3758 ph[12][7] $abc$23348$new_n3757 +10 1 +.names $abc$23348$new_n3759 ph[12][6] $abc$23348$new_n3758 +10 1 +.names $abc$23348$new_n3745 ph[12][19] $abc$23348$new_n3759 +10 1 +.names ph[12][8] ph[12][13] $abc$23348$new_n3750 $abc$23348$new_n3761 $abc$23348$new_n3760 +1111 1 +.names ph[12][7] $abc$23348$new_n3762 $abc$23348$new_n3761 +11 1 +.names ph[12][6] $abc$23348$new_n3763 $abc$23348$new_n3762 +11 1 +.names ph[12][19] $abc$23348$new_n3749 $abc$23348$new_n3763 +11 1 +.names i_ce $abc$23348$new_n3765 ph[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21208 +001 1 +011 1 +100 1 +101 1 +.names ph[12][14] ph[12][15] $abc$23348$new_n3760 $abc$23348$new_n3755 $abc$23348$new_n3765 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[12][14] $abc$23348$new_n3760 $abc$23348$new_n3755 ph[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21210 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3768 ph[12][13] ph[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21212 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][10] ph[12][11] ph[12][12] $abc$23348$new_n3769 $abc$23348$new_n3756 $abc$23348$new_n3768 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][8] ph[12][9] $abc$23348$new_n3761 $abc$23348$new_n3769 +111 1 +.names i_ce $abc$23348$new_n3771 ph[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21214 +001 1 +011 1 +110 1 +111 1 +.names ph[12][10] ph[12][12] ph[12][11] $abc$23348$new_n3756 $abc$23348$new_n3769 $abc$23348$new_n3771 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3773 ph[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21216 +001 1 +011 1 +100 1 +101 1 +.names ph[12][11] ph[12][10] $abc$23348$new_n3756 $abc$23348$new_n3769 $abc$23348$new_n3773 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[12][10] $abc$23348$new_n3756 $abc$23348$new_n3769 ph[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21218 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3776 ph[12][9] ph[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21220 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][8] $abc$23348$new_n3761 $abc$23348$new_n3757 $abc$23348$new_n3776 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[12][8] $abc$23348$new_n3757 $abc$23348$new_n3761 ph[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21222 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[12][7] $abc$23348$new_n3758 $abc$23348$new_n3762 ph[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21224 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[12][6] $abc$23348$new_n3759 $abc$23348$new_n3763 ph[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21226 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3781 ph[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21228 +001 1 +011 1 +110 1 +111 1 +.names ph[12][5] ph[12][19] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3781 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3783 ph[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21230 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] ph[12][4] ph[12][2] ph[12][3] $abc$23348$new_n3783 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[12][19] ph[12][2] ph[12][3] ph[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21232 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[12][2] ph[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21234 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[12][1] ph[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21236 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][0] ph[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21238 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][15] yv[12][14] $abc$23348$new_n3789 yv[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21240 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] $abc$23348$new_n3790 $abc$23348$new_n3797 $abc$23348$new_n3789 +000 1 +001 1 +101 1 +111 1 +.names xv[12][15] $abc$23348$new_n3791 yv[12][12] yv[12][13] $abc$23348$new_n3790 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] yv[12][11] $abc$23348$new_n3792 $abc$23348$new_n3791 +000 1 +001 1 +011 1 +101 1 +.names xv[12][15] $abc$23348$new_n3793 yv[12][8] yv[12][9] yv[12][10] $abc$23348$new_n3792 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[12][15] $abc$23348$new_n3794 yv[12][6] yv[12][7] $abc$23348$new_n3793 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] $abc$23348$new_n3795 yv[12][4] yv[12][5] $abc$23348$new_n3794 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][15] $abc$23348$new_n3796 yv[12][2] yv[12][3] $abc$23348$new_n3795 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][13] yv[12][0] xv[12][14] yv[12][1] $abc$23348$new_n3796 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][15] yv[12][13] $abc$23348$new_n3798 $abc$23348$new_n3797 +000 1 +100 1 +101 1 +110 1 +.names yv[12][12] xv[12][15] $abc$23348$new_n3799 $abc$23348$new_n3798 +000 1 +100 1 +101 1 +110 1 +.names xv[12][15] yv[12][10] yv[12][11] $abc$23348$new_n3800 $abc$23348$new_n3804 $abc$23348$new_n3799 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][15] yv[12][9] yv[12][8] yv[12][7] $abc$23348$new_n3801 $abc$23348$new_n3800 +00000 1 +00010 1 +00011 1 +11110 1 +.names xv[12][15] $abc$23348$new_n3802 yv[12][5] yv[12][6] $abc$23348$new_n3801 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][15] yv[12][2] yv[12][3] yv[12][4] $abc$23348$new_n3803 $abc$23348$new_n3802 +00000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names xv[12][13] xv[12][14] yv[12][0] yv[12][1] $abc$23348$new_n3803 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[12][8] yv[12][9] $abc$23348$new_n3804 +00 1 +.names i_ce xv[12][15] yv[12][13] $abc$23348$new_n3806 yv[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21242 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3798 yv[12][12] ph[12][19] $abc$23348$new_n3791 $abc$23348$new_n3806 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3808 yv[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21244 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] xv[12][15] yv[12][12] $abc$23348$new_n3799 $abc$23348$new_n3791 $abc$23348$new_n3808 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][15] yv[12][11] $abc$23348$new_n3810 yv[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21246 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][10] $abc$23348$new_n3811 $abc$23348$new_n3792 ph[12][19] $abc$23348$new_n3810 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ph[12][19] $abc$23348$new_n3800 xv[12][15] $abc$23348$new_n3804 $abc$23348$new_n3811 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3813 yv[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21248 +001 1 +011 1 +110 1 +111 1 +.names xv[12][15] yv[12][10] $abc$23348$new_n3814 $abc$23348$new_n3811 $abc$23348$new_n3813 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names ph[12][19] xv[12][15] $abc$23348$new_n3793 yv[12][8] yv[12][9] $abc$23348$new_n3814 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names i_ce xv[12][15] yv[12][9] $abc$23348$new_n3816 yv[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21250 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] yv[12][8] xv[12][15] $abc$23348$new_n3817 $abc$23348$new_n3793 $abc$23348$new_n3816 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][15] yv[12][7] $abc$23348$new_n3801 $abc$23348$new_n3817 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3819 yv[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21252 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] xv[12][15] yv[12][8] $abc$23348$new_n3817 $abc$23348$new_n3793 $abc$23348$new_n3819 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[12][15] yv[12][7] $abc$23348$new_n3821 yv[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21254 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3801 $abc$23348$new_n3794 ph[12][19] yv[12][6] $abc$23348$new_n3821 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[12][15] yv[12][6] $abc$23348$new_n3823 yv[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21256 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3794 ph[12][19] $abc$23348$new_n3802 yv[12][5] $abc$23348$new_n3823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names i_ce xv[12][15] yv[12][5] $abc$23348$new_n3825 yv[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21258 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n3802 $abc$23348$new_n3795 ph[12][19] yv[12][4] $abc$23348$new_n3825 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3827 yv[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21260 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] xv[12][15] yv[12][4] $abc$23348$new_n3828 $abc$23348$new_n3795 $abc$23348$new_n3827 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[12][15] yv[12][2] yv[12][3] $abc$23348$new_n3803 $abc$23348$new_n3828 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[12][15] yv[12][3] $abc$23348$new_n3830 yv[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21262 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] yv[12][2] xv[12][15] $abc$23348$new_n3803 $abc$23348$new_n3796 $abc$23348$new_n3830 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][15] yv[12][2] $abc$23348$new_n3832 yv[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21264 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] $abc$23348$new_n3796 $abc$23348$new_n3803 $abc$23348$new_n3832 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3834 yv[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21266 +001 1 +011 1 +110 1 +111 1 +.names xv[12][14] yv[12][1] ph[12][19] yv[12][0] xv[12][13] $abc$23348$new_n3834 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[12][13] yv[12][0] yv[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21268 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$23348$new_n3837 xv[13][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21270 +001 1 +011 1 +110 1 +111 1 +.names ph[12][19] yv[12][15] xv[12][14] $abc$23348$new_n3845 $abc$23348$new_n3838 $abc$23348$new_n3837 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][15] $abc$23348$new_n3839 xv[12][12] xv[12][13] $abc$23348$new_n3838 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3840 xv[12][10] xv[12][11] $abc$23348$new_n3839 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3841 xv[12][8] xv[12][9] $abc$23348$new_n3840 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3842 xv[12][6] xv[12][7] $abc$23348$new_n3841 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3843 xv[12][4] xv[12][5] $abc$23348$new_n3842 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][15] $abc$23348$new_n3844 xv[12][2] xv[12][3] $abc$23348$new_n3843 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][13] xv[12][0] xv[12][1] yv[12][14] $abc$23348$new_n3844 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names yv[12][15] $abc$23348$new_n3846 xv[12][12] xv[12][13] $abc$23348$new_n3845 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][15] $abc$23348$new_n3860 xv[12][10] xv[12][11] $abc$23348$new_n3846 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][15] xv[12][6] xv[12][7] $abc$23348$new_n3849 $abc$23348$new_n3852 $abc$23348$new_n3848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[12][4] xv[12][5] yv[12][15] xv[12][3] $abc$23348$new_n3850 $abc$23348$new_n3849 +00100 1 +00110 1 +00111 1 +11010 1 +.names yv[12][15] xv[12][2] $abc$23348$new_n3851 $abc$23348$new_n3850 +000 1 +001 1 +011 1 +101 1 +.names xv[12][0] yv[12][13] xv[12][1] yv[12][14] $abc$23348$new_n3851 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][4] xv[12][5] $abc$23348$new_n3852 +00 1 +.names i_ce yv[12][15] xv[12][13] $abc$23348$new_n3855 xv[13][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21272 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][12] yv[12][15] $abc$23348$new_n3846 $abc$23348$new_n3839 $abc$23348$new_n3855 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3857 xv[13][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21274 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][12] $abc$23348$new_n3846 $abc$23348$new_n3839 $abc$23348$new_n3857 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][11] $abc$23348$new_n3859 xv[13][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21276 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][10] yv[12][15] $abc$23348$new_n3860 $abc$23348$new_n3840 $abc$23348$new_n3859 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names yv[12][15] $abc$23348$new_n3848 xv[12][8] xv[12][9] $abc$23348$new_n3860 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$23348$new_n3862 xv[13][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21278 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][10] $abc$23348$new_n3860 $abc$23348$new_n3840 $abc$23348$new_n3862 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][9] $abc$23348$new_n3864 xv[13][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21280 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][8] yv[12][15] $abc$23348$new_n3848 $abc$23348$new_n3841 $abc$23348$new_n3864 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n3866 xv[13][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21282 +001 1 +011 1 +100 1 +101 1 +.names ph[12][19] yv[12][15] xv[12][8] $abc$23348$new_n3848 $abc$23348$new_n3841 $abc$23348$new_n3866 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][7] $abc$23348$new_n3868 xv[13][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21284 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][6] yv[12][15] $abc$23348$new_n3842 $abc$23348$new_n3869 $abc$23348$new_n3868 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3849 $abc$23348$new_n3852 yv[12][15] $abc$23348$new_n3869 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n3871 xv[13][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21286 +001 1 +011 1 +100 1 +101 1 +.names yv[12][15] xv[12][6] ph[12][19] $abc$23348$new_n3842 $abc$23348$new_n3869 $abc$23348$new_n3871 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[12][15] xv[12][5] $abc$23348$new_n3873 xv[13][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21288 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][4] yv[12][15] $abc$23348$new_n3843 $abc$23348$new_n3874 $abc$23348$new_n3873 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names yv[12][15] xv[12][3] $abc$23348$new_n3850 $abc$23348$new_n3874 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$23348$new_n3876 xv[13][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21290 +001 1 +011 1 +100 1 +101 1 +.names yv[12][15] xv[12][4] ph[12][19] $abc$23348$new_n3843 $abc$23348$new_n3874 $abc$23348$new_n3876 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[12][15] xv[12][3] $abc$23348$new_n3878 xv[13][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21292 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] yv[12][15] xv[12][2] $abc$23348$new_n3851 $abc$23348$new_n3844 $abc$23348$new_n3878 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[12][15] xv[12][2] $abc$23348$new_n3880 xv[13][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21294 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] $abc$23348$new_n3844 $abc$23348$new_n3851 $abc$23348$new_n3880 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$23348$new_n3882 xv[13][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21296 +001 1 +011 1 +110 1 +111 1 +.names xv[12][1] yv[12][14] ph[12][19] xv[12][0] yv[12][13] $abc$23348$new_n3882 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[12][0] yv[12][13] xv[13][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21298 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][18] $abc$23348$new_n3890 $abc$23348$new_n3885 ph[14][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21300 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[13][19] $abc$23348$new_n3886 ph[13][17] $abc$23348$new_n3885 +000 1 +001 1 +011 1 +.names $abc$23348$new_n3887 ph[13][13] ph[13][14] ph[13][15] ph[13][16] $abc$23348$new_n3886 +10000 1 +.names $abc$23348$new_n3888 ph[13][9] ph[13][10] ph[13][11] ph[13][12] $abc$23348$new_n3887 +10000 1 +.names $abc$23348$new_n3889 ph[13][5] ph[13][6] ph[13][7] ph[13][8] $abc$23348$new_n3888 +10000 1 +.names ph[13][4] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3889 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[13][19] ph[13][16] $abc$23348$new_n3904 ph[13][17] ph[13][15] $abc$23348$new_n3890 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n3896 ph[14][17] $abc$23348$auto$rtlil.cc:2693:MuxGate$21302 +001 1 +011 1 +100 1 +101 1 +.names ph[13][16] ph[13][17] $abc$23348$new_n3903 $abc$23348$new_n3897 $abc$23348$new_n3896 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$23348$new_n3898 ph[13][15] $abc$23348$new_n3897 +10 1 +.names $abc$23348$new_n3899 ph[13][12] ph[13][13] ph[13][14] $abc$23348$new_n3898 +1000 1 +.names $abc$23348$new_n3900 ph[13][11] $abc$23348$new_n3899 +10 1 +.names $abc$23348$new_n3901 ph[13][7] ph[13][8] ph[13][9] ph[13][10] $abc$23348$new_n3900 +10000 1 +.names $abc$23348$new_n3902 ph[13][5] ph[13][6] $abc$23348$new_n3901 +100 1 +.names $abc$23348$new_n3889 ph[13][19] $abc$23348$new_n3902 +10 1 +.names ph[13][15] $abc$23348$new_n3904 $abc$23348$new_n3903 +11 1 +.names ph[13][12] ph[13][13] ph[13][14] $abc$23348$new_n3905 $abc$23348$new_n3904 +1111 1 +.names ph[13][11] $abc$23348$new_n3906 $abc$23348$new_n3905 +11 1 +.names ph[13][7] ph[13][8] ph[13][9] ph[13][10] $abc$23348$new_n3907 $abc$23348$new_n3906 +11111 1 +.names ph[13][5] ph[13][6] $abc$23348$new_n3908 $abc$23348$new_n3907 +111 1 +.names ph[13][4] ph[13][19] $abc$23348$new_n3928 $abc$23348$new_n3908 +110 1 +.names i_ce ph[13][16] $abc$23348$new_n3903 $abc$23348$new_n3897 ph[14][16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21304 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][15] $abc$23348$new_n3904 $abc$23348$new_n3898 ph[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21306 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3912 ph[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21308 +001 1 +011 1 +100 1 +101 1 +.names ph[13][14] ph[13][12] ph[13][13] $abc$23348$new_n3905 $abc$23348$new_n3899 $abc$23348$new_n3912 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3914 ph[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21310 +001 1 +011 1 +110 1 +111 1 +.names ph[13][12] ph[13][13] $abc$23348$new_n3905 $abc$23348$new_n3899 $abc$23348$new_n3914 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][12] $abc$23348$new_n3905 $abc$23348$new_n3899 ph[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21312 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][11] $abc$23348$new_n3906 $abc$23348$new_n3900 ph[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21314 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][10] $abc$23348$new_n3918 ph[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21316 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[13][7] ph[13][8] ph[13][9] $abc$23348$new_n3901 $abc$23348$new_n3907 $abc$23348$new_n3918 +00010 1 +00011 1 +11101 1 +11111 1 +.names i_ce $abc$23348$new_n3920 ph[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21318 +001 1 +011 1 +100 1 +101 1 +.names ph[13][9] ph[13][7] ph[13][8] $abc$23348$new_n3907 $abc$23348$new_n3901 $abc$23348$new_n3920 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3922 ph[13][8] ph[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21320 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[13][7] $abc$23348$new_n3901 $abc$23348$new_n3907 $abc$23348$new_n3922 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[13][7] $abc$23348$new_n3907 $abc$23348$new_n3901 ph[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21322 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3925 ph[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21324 +001 1 +011 1 +110 1 +111 1 +.names ph[13][5] ph[13][6] $abc$23348$new_n3908 $abc$23348$new_n3902 $abc$23348$new_n3925 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][5] $abc$23348$new_n3908 $abc$23348$new_n3902 ph[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21326 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$23348$new_n3928 ph[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21328 +001 1 +011 1 +110 1 +111 1 +.names ph[13][4] ph[13][19] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3928 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$23348$new_n3930 ph[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21330 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] ph[13][3] ph[13][1] ph[13][2] $abc$23348$new_n3930 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[13][19] ph[13][1] ph[13][2] ph[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21332 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[13][1] ph[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21334 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[13][0] ph[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21336 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$23348$new_n3935 yv[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21338 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] xv[13][15] yv[13][14] $abc$23348$new_n3943 $abc$23348$new_n3936 $abc$23348$new_n3935 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[13][15] $abc$23348$new_n3937 yv[13][12] yv[13][13] $abc$23348$new_n3936 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3938 yv[13][10] yv[13][11] $abc$23348$new_n3937 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3939 yv[13][8] yv[13][9] $abc$23348$new_n3938 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][15] yv[13][7] $abc$23348$new_n3940 $abc$23348$new_n3939 +000 1 +001 1 +011 1 +101 1 +.names xv[13][15] $abc$23348$new_n3941 yv[13][4] yv[13][5] yv[13][6] $abc$23348$new_n3940 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[13][15] $abc$23348$new_n3942 yv[13][2] yv[13][3] $abc$23348$new_n3941 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][0] xv[13][14] xv[13][15] yv[13][1] $abc$23348$new_n3942 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[13][15] $abc$23348$new_n3944 yv[13][12] yv[13][13] $abc$23348$new_n3943 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][15] $abc$23348$new_n3958 yv[13][10] yv[13][11] $abc$23348$new_n3944 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][15] yv[13][6] yv[13][7] $abc$23348$new_n3948 $abc$23348$new_n3950 $abc$23348$new_n3947 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][15] yv[13][5] yv[13][4] yv[13][3] $abc$23348$new_n3949 $abc$23348$new_n3948 +00001 1 +00010 1 +00011 1 +11111 1 +.names xv[13][15] xv[13][14] yv[13][0] yv[13][1] yv[13][2] $abc$23348$new_n3949 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11111 1 +.names yv[13][4] yv[13][5] $abc$23348$new_n3950 +00 1 +.names i_ce xv[13][15] yv[13][13] $abc$23348$new_n3953 yv[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21340 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][12] $abc$23348$new_n3944 $abc$23348$new_n3937 $abc$23348$new_n3953 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3955 yv[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21342 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][12] $abc$23348$new_n3944 $abc$23348$new_n3937 $abc$23348$new_n3955 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][11] $abc$23348$new_n3957 yv[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21344 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][10] $abc$23348$new_n3958 $abc$23348$new_n3938 $abc$23348$new_n3957 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] $abc$23348$new_n3947 yv[13][8] yv[13][9] $abc$23348$new_n3958 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3960 yv[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21346 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][10] $abc$23348$new_n3958 $abc$23348$new_n3938 $abc$23348$new_n3960 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][9] $abc$23348$new_n3962 yv[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21348 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] yv[13][8] xv[13][15] $abc$23348$new_n3939 $abc$23348$new_n3947 $abc$23348$new_n3962 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n3964 yv[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21350 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] xv[13][15] yv[13][8] $abc$23348$new_n3947 $abc$23348$new_n3939 $abc$23348$new_n3964 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][15] yv[13][7] $abc$23348$new_n3966 yv[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21352 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][6] $abc$23348$new_n3967 $abc$23348$new_n3940 ph[13][19] $abc$23348$new_n3966 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ph[13][19] $abc$23348$new_n3948 xv[13][15] $abc$23348$new_n3950 $abc$23348$new_n3967 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n3969 yv[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21354 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][6] $abc$23348$new_n3970 $abc$23348$new_n3967 $abc$23348$new_n3969 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names ph[13][19] xv[13][15] $abc$23348$new_n3941 yv[13][4] yv[13][5] $abc$23348$new_n3970 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +.names i_ce xv[13][15] yv[13][5] $abc$23348$new_n3972 yv[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21356 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][4] $abc$23348$new_n3973 $abc$23348$new_n3941 $abc$23348$new_n3972 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] yv[13][3] $abc$23348$new_n3949 $abc$23348$new_n3973 +000 1 +100 1 +101 1 +110 1 +.names i_ce $abc$23348$new_n3975 yv[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21358 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] xv[13][15] yv[13][4] $abc$23348$new_n3973 $abc$23348$new_n3941 $abc$23348$new_n3975 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[13][15] yv[13][3] $abc$23348$new_n3977 yv[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21360 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3949 yv[13][2] ph[13][19] $abc$23348$new_n3942 $abc$23348$new_n3977 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce xv[13][15] yv[13][2] $abc$23348$new_n3979 yv[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][14] xv[13][15] yv[13][0] yv[13][1] $abc$23348$new_n3979 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_ce $abc$23348$new_n3981 yv[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21364 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][1] ph[13][19] yv[13][0] xv[13][14] $abc$23348$new_n3981 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[13][14] yv[13][0] yv[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21366 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[13][15] xv[13][14] $abc$23348$new_n3984 xv[14][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21368 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] $abc$23348$new_n3985 $abc$23348$new_n3992 $abc$23348$new_n3984 +000 1 +001 1 +101 1 +111 1 +.names yv[13][15] $abc$23348$new_n3986 xv[13][12] xv[13][13] $abc$23348$new_n3985 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3987 xv[13][10] xv[13][11] $abc$23348$new_n3986 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3988 xv[13][8] xv[13][9] $abc$23348$new_n3987 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3989 xv[13][6] xv[13][7] $abc$23348$new_n3988 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3990 xv[13][4] xv[13][5] $abc$23348$new_n3989 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][15] $abc$23348$new_n3991 xv[13][2] xv[13][3] $abc$23348$new_n3990 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[13][14] yv[13][15] xv[13][0] xv[13][1] $abc$23348$new_n3991 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[13][15] $abc$23348$new_n3993 xv[13][12] xv[13][13] $abc$23348$new_n3992 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] $abc$23348$new_n3994 xv[13][10] xv[13][11] $abc$23348$new_n3993 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] $abc$23348$new_n3995 xv[13][8] xv[13][9] $abc$23348$new_n3994 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[13][15] xv[13][6] xv[13][7] $abc$23348$new_n3996 $abc$23348$new_n3999 $abc$23348$new_n3995 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[13][15] xv[13][4] xv[13][5] $abc$23348$new_n3997 $abc$23348$new_n3996 +0110 1 +1000 1 +.names yv[13][15] xv[13][3] $abc$23348$new_n3998 $abc$23348$new_n3997 +000 1 +001 1 +011 1 +101 1 +.names yv[13][15] xv[13][0] yv[13][14] xv[13][1] xv[13][2] $abc$23348$new_n3998 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +11000 1 +.names xv[13][4] xv[13][5] $abc$23348$new_n3999 +00 1 +.names i_ce yv[13][15] xv[13][13] $abc$23348$new_n4001 xv[14][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21370 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][12] yv[13][15] $abc$23348$new_n3993 $abc$23348$new_n3986 $abc$23348$new_n4001 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4003 xv[14][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21372 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] yv[13][15] xv[13][12] $abc$23348$new_n3993 $abc$23348$new_n3986 $abc$23348$new_n4003 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[13][15] xv[13][11] $abc$23348$new_n4005 xv[14][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][10] yv[13][15] $abc$23348$new_n3994 $abc$23348$new_n3987 $abc$23348$new_n4005 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4007 xv[14][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21376 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] yv[13][15] xv[13][10] $abc$23348$new_n3994 $abc$23348$new_n3987 $abc$23348$new_n4007 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[13][15] xv[13][9] $abc$23348$new_n4009 xv[14][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21378 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][8] yv[13][15] $abc$23348$new_n3995 $abc$23348$new_n3988 $abc$23348$new_n4009 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4011 xv[14][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21380 +001 1 +011 1 +100 1 +101 1 +.names ph[13][19] yv[13][15] xv[13][8] $abc$23348$new_n3995 $abc$23348$new_n3988 $abc$23348$new_n4011 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce yv[13][15] xv[13][7] $abc$23348$new_n4013 xv[14][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21382 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][6] yv[13][15] $abc$23348$new_n3989 $abc$23348$new_n4014 $abc$23348$new_n4013 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$23348$new_n3996 $abc$23348$new_n3999 yv[13][15] $abc$23348$new_n4014 +000 1 +010 1 +011 1 +.names i_ce $abc$23348$new_n4016 xv[14][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21384 +001 1 +011 1 +100 1 +101 1 +.names yv[13][15] xv[13][6] ph[13][19] $abc$23348$new_n3989 $abc$23348$new_n4014 $abc$23348$new_n4016 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce yv[13][15] xv[13][5] $abc$23348$new_n4018 xv[14][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21386 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][4] yv[13][15] $abc$23348$new_n3997 $abc$23348$new_n3990 $abc$23348$new_n4018 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4020 xv[14][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21388 +001 1 +011 1 +110 1 +111 1 +.names ph[13][19] yv[13][15] xv[13][4] $abc$23348$new_n3997 $abc$23348$new_n3990 $abc$23348$new_n4020 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[13][15] xv[13][3] $abc$23348$new_n4022 xv[14][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21390 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n3998 $abc$23348$new_n3991 ph[13][19] xv[13][2] $abc$23348$new_n4022 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce yv[13][15] xv[13][2] $abc$23348$new_n4024 xv[14][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21392 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] yv[13][14] yv[13][15] xv[13][0] xv[13][1] $abc$23348$new_n4024 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names i_ce $abc$23348$new_n4026 xv[14][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21394 +001 1 +011 1 +110 1 +111 1 +.names yv[13][15] xv[13][1] ph[13][19] xv[13][0] yv[13][14] $abc$23348$new_n4026 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[13][0] yv[13][14] xv[14][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21396 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][15] yv[14][14] $abc$23348$new_n4029 yv[15][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21436 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] $abc$23348$new_n4030 xv[14][15] $abc$23348$new_n4038 $abc$23348$new_n4029 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4031 xv[14][15] yv[14][12] yv[14][13] $abc$23348$new_n4030 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$23348$new_n4032 yv[14][11] xv[14][15] $abc$23348$new_n4031 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4033 xv[14][15] yv[14][9] yv[14][10] $abc$23348$new_n4032 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$23348$new_n4034 yv[14][8] xv[14][15] $abc$23348$new_n4033 +000 1 +010 1 +011 1 +.names xv[14][15] yv[14][7] $abc$23348$new_n4035 yv[14][6] $abc$23348$new_n4034 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n4036 xv[14][15] yv[14][4] yv[14][5] $abc$23348$new_n4035 +1000 1 +1111 1 +.names xv[14][15] yv[14][1] yv[14][2] yv[14][3] yv[14][0] $abc$23348$new_n4036 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$23348$new_n4039 yv[14][11] yv[14][12] yv[14][13] $abc$23348$new_n4038 +1000 1 +.names $abc$23348$new_n4040 yv[14][9] yv[14][10] $abc$23348$new_n4039 +100 1 +.names $abc$23348$new_n4041 yv[14][8] $abc$23348$new_n4040 +10 1 +.names $abc$23348$new_n4042 yv[14][5] yv[14][6] yv[14][7] $abc$23348$new_n4041 +1000 1 +.names $abc$23348$new_n4043 yv[14][4] $abc$23348$new_n4042 +10 1 +.names yv[14][0] yv[14][1] yv[14][2] yv[14][3] $abc$23348$new_n4043 +0000 1 +.names i_ce xv[14][15] yv[14][13] $abc$23348$new_n4045 yv[15][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21438 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][12] $abc$23348$new_n4031 xv[14][15] $abc$23348$new_n4046 $abc$23348$new_n4045 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n4039 yv[14][11] $abc$23348$new_n4046 +10 1 +.names i_ce xv[14][15] yv[14][12] $abc$23348$new_n4048 yv[15][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21440 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] $abc$23348$new_n4031 xv[14][15] $abc$23348$new_n4046 $abc$23348$new_n4048 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$23348$new_n4050 yv[15][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21442 +001 1 +011 1 +110 1 +111 1 +.names yv[14][11] ph[14][19] xv[14][15] $abc$23348$new_n4032 $abc$23348$new_n4039 $abc$23348$new_n4050 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][15] yv[14][10] $abc$23348$new_n4052 yv[15][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21444 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][9] $abc$23348$new_n4033 xv[14][15] $abc$23348$new_n4040 $abc$23348$new_n4052 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4054 yv[15][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21446 +001 1 +011 1 +110 1 +111 1 +.names yv[14][9] ph[14][19] xv[14][15] $abc$23348$new_n4033 $abc$23348$new_n4040 $abc$23348$new_n4054 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4056 yv[15][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21448 +001 1 +011 1 +110 1 +111 1 +.names yv[14][8] ph[14][19] xv[14][15] $abc$23348$new_n4034 $abc$23348$new_n4041 $abc$23348$new_n4056 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][15] yv[14][7] $abc$23348$new_n4058 yv[15][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21450 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][6] xv[14][15] ph[14][19] $abc$23348$new_n4060 $abc$23348$new_n4059 $abc$23348$new_n4058 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$23348$new_n4042 yv[14][5] $abc$23348$new_n4059 +10 1 +.names ph[14][19] $abc$23348$new_n4035 xv[14][15] $abc$23348$new_n4060 +100 1 +110 1 +111 1 +.names i_ce xv[14][15] yv[14][6] $abc$23348$new_n4062 yv[15][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21452 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n4060 ph[14][19] xv[14][15] $abc$23348$new_n4059 $abc$23348$new_n4062 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce xv[14][15] yv[14][5] $abc$23348$new_n4064 yv[15][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21454 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][4] xv[14][15] $abc$23348$new_n4036 $abc$23348$new_n4043 $abc$23348$new_n4064 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4066 yv[15][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21456 +001 1 +011 1 +110 1 +111 1 +.names yv[14][4] ph[14][19] xv[14][15] $abc$23348$new_n4036 $abc$23348$new_n4043 $abc$23348$new_n4066 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][15] yv[14][3] $abc$23348$new_n4068 yv[15][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21458 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][2] yv[14][0] yv[14][1] xv[14][15] $abc$23348$new_n4068 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4070 yv[15][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21460 +001 1 +011 1 +110 1 +111 1 +.names yv[14][2] ph[14][19] yv[14][0] yv[14][1] xv[14][15] $abc$23348$new_n4070 +00001 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n4072 yv[15][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21462 +001 1 +011 1 +100 1 +101 1 +.names yv[14][1] ph[14][19] yv[14][0] xv[14][15] $abc$23348$new_n4072 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1001 1 +1111 1 +.names i_ce xv[14][15] yv[14][0] yv[15][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21464 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[14][15] xv[14][14] $abc$23348$new_n4075 xv[15][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21466 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4084 $abc$23348$new_n4076 ph[14][19] $abc$23348$new_n4075 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4077 yv[14][15] xv[14][12] xv[14][13] $abc$23348$new_n4076 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$23348$new_n4083 yv[14][15] $abc$23348$new_n4079 xv[14][10] xv[14][11] $abc$23348$new_n4077 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$23348$new_n4082 yv[14][15] $abc$23348$new_n4081 xv[14][6] xv[14][7] $abc$23348$new_n4079 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names yv[14][15] xv[14][1] xv[14][2] xv[14][3] xv[14][0] $abc$23348$new_n4081 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[14][15] xv[14][5] xv[14][4] $abc$23348$new_n4082 +000 1 +001 1 +010 1 +011 1 +100 1 +.names yv[14][15] xv[14][9] xv[14][8] $abc$23348$new_n4083 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$23348$new_n4085 yv[14][15] ph[14][19] xv[14][13] $abc$23348$new_n4084 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4086 yv[14][15] ph[14][19] xv[14][12] xv[14][11] $abc$23348$new_n4085 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[14][15] ph[14][19] xv[14][9] xv[14][10] $abc$23348$new_n4087 $abc$23348$new_n4086 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14][5] xv[14][6] xv[14][7] xv[14][8] $abc$23348$new_n4088 $abc$23348$new_n4087 +11111 1 +.names xv[14][4] $abc$23348$new_n4089 $abc$23348$new_n4088 +11 1 +.names xv[14][0] xv[14][1] xv[14][2] xv[14][3] $abc$23348$new_n4089 +1111 1 +.names i_ce yv[14][15] xv[14][13] $abc$23348$new_n4091 xv[15][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21468 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4085 $abc$23348$new_n4077 ph[14][19] xv[14][12] yv[14][15] $abc$23348$new_n4091 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce yv[14][15] xv[14][12] $abc$23348$new_n4093 xv[15][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21470 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4086 ph[14][19] $abc$23348$new_n4077 xv[14][11] $abc$23348$new_n4093 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_ce yv[14][15] xv[14][11] $abc$23348$new_n4095 xv[15][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21472 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4086 $abc$23348$new_n4096 xv[14][10] yv[14][15] ph[14][19] $abc$23348$new_n4095 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names ph[14][19] $abc$23348$new_n4079 $abc$23348$new_n4083 $abc$23348$new_n4096 +100 1 +101 1 +110 1 +.names i_ce yv[14][15] xv[14][10] $abc$23348$new_n4098 xv[15][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21474 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4096 yv[14][15] ph[14][19] $abc$23348$new_n4087 xv[14][9] $abc$23348$new_n4098 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[14][15] xv[14][9] $abc$23348$new_n4100 xv[15][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21476 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] yv[14][15] xv[14][8] $abc$23348$new_n4079 $abc$23348$new_n4087 $abc$23348$new_n4100 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[14][15] xv[14][8] $abc$23348$new_n4102 xv[15][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21478 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4103 $abc$23348$new_n4079 xv[14][7] ph[14][19] $abc$23348$new_n4102 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names yv[14][15] ph[14][19] $abc$23348$new_n4088 xv[14][6] xv[14][5] $abc$23348$new_n4103 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce yv[14][15] xv[14][7] $abc$23348$new_n4105 xv[15][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21480 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4103 $abc$23348$new_n4106 xv[14][6] yv[14][15] ph[14][19] $abc$23348$new_n4105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names ph[14][19] $abc$23348$new_n4081 $abc$23348$new_n4082 $abc$23348$new_n4106 +100 1 +101 1 +110 1 +.names i_ce yv[14][15] xv[14][6] $abc$23348$new_n4108 xv[15][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21482 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4106 yv[14][15] ph[14][19] $abc$23348$new_n4088 xv[14][5] $abc$23348$new_n4108 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[14][15] xv[14][5] $abc$23348$new_n4110 xv[15][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21484 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] xv[14][4] yv[14][15] $abc$23348$new_n4081 $abc$23348$new_n4089 $abc$23348$new_n4110 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4112 xv[15][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21486 +001 1 +011 1 +110 1 +111 1 +.names xv[14][4] ph[14][19] yv[14][15] $abc$23348$new_n4081 $abc$23348$new_n4089 $abc$23348$new_n4112 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[14][15] xv[14][3] $abc$23348$new_n4114 xv[15][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21488 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[14][19] xv[14][2] xv[14][0] xv[14][1] yv[14][15] $abc$23348$new_n4114 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4116 xv[15][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21490 +001 1 +011 1 +110 1 +111 1 +.names xv[14][2] ph[14][19] xv[14][0] xv[14][1] yv[14][15] $abc$23348$new_n4116 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4118 xv[15][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21492 +001 1 +011 1 +110 1 +111 1 +.names xv[14][1] ph[14][19] xv[14][0] yv[14][15] $abc$23348$new_n4118 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce yv[14][15] xv[14][0] xv[15][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21494 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][15] yv[15][14] $abc$23348$new_n4121 yv[16][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21496 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] $abc$23348$new_n4130 xv[15][15] $abc$23348$new_n4122 $abc$23348$new_n4121 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4123 yv[15][13] $abc$23348$new_n4122 +10 1 +.names $abc$23348$new_n4124 yv[15][12] $abc$23348$new_n4123 +10 1 +.names $abc$23348$new_n4125 yv[15][10] yv[15][11] $abc$23348$new_n4124 +100 1 +.names $abc$23348$new_n4129 $abc$23348$new_n4126 $abc$23348$new_n4125 +11 1 +.names $abc$23348$new_n4127 yv[15][5] yv[15][6] yv[15][7] $abc$23348$new_n4126 +1000 1 +.names $abc$23348$new_n4128 yv[15][4] $abc$23348$new_n4127 +10 1 +.names yv[15][0] yv[15][1] yv[15][2] yv[15][3] $abc$23348$new_n4128 +0000 1 +.names yv[15][8] yv[15][9] $abc$23348$new_n4129 +00 1 +.names $abc$23348$new_n4131 xv[15][15] yv[15][12] yv[15][13] $abc$23348$new_n4130 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names xv[15][15] yv[15][11] $abc$23348$new_n4132 yv[15][10] $abc$23348$new_n4131 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[15][15] yv[15][8] yv[15][9] $abc$23348$new_n4133 $abc$23348$new_n4132 +0000 1 +1110 1 +.names xv[15][15] yv[15][7] $abc$23348$new_n4134 yv[15][6] $abc$23348$new_n4133 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n4135 xv[15][15] yv[15][4] yv[15][5] $abc$23348$new_n4134 +1000 1 +1111 1 +.names xv[15][15] yv[15][1] yv[15][2] yv[15][3] yv[15][0] $abc$23348$new_n4135 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names i_ce xv[15][15] yv[15][13] $abc$23348$new_n4138 yv[16][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21498 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][12] $abc$23348$new_n4131 xv[15][15] $abc$23348$new_n4124 $abc$23348$new_n4138 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4140 yv[16][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21500 +001 1 +011 1 +110 1 +111 1 +.names yv[15][12] ph[15][19] xv[15][15] $abc$23348$new_n4131 $abc$23348$new_n4124 $abc$23348$new_n4140 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][11] $abc$23348$new_n4142 yv[16][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21502 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[15][19] xv[15][15] yv[15][10] $abc$23348$new_n4143 $abc$23348$new_n4125 $abc$23348$new_n4142 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[15][15] $abc$23348$new_n4132 $abc$23348$new_n4143 +10 1 +.names i_ce $abc$23348$new_n4145 yv[16][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21504 +001 1 +011 1 +110 1 +111 1 +.names yv[15][10] ph[15][19] xv[15][15] $abc$23348$new_n4143 $abc$23348$new_n4125 $abc$23348$new_n4145 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][9] $abc$23348$new_n4147 yv[16][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21506 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][8] xv[15][15] $abc$23348$new_n4133 $abc$23348$new_n4126 $abc$23348$new_n4147 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4149 yv[16][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21508 +001 1 +011 1 +110 1 +111 1 +.names yv[15][8] ph[15][19] xv[15][15] $abc$23348$new_n4133 $abc$23348$new_n4126 $abc$23348$new_n4149 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][15] yv[15][7] $abc$23348$new_n4151 yv[16][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21510 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][6] xv[15][15] ph[15][19] $abc$23348$new_n4153 $abc$23348$new_n4152 $abc$23348$new_n4151 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$23348$new_n4127 yv[15][5] $abc$23348$new_n4152 +10 1 +.names ph[15][19] $abc$23348$new_n4134 xv[15][15] $abc$23348$new_n4153 +100 1 +110 1 +111 1 +.names i_ce xv[15][15] yv[15][6] $abc$23348$new_n4155 yv[16][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21512 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$23348$new_n4153 ph[15][19] xv[15][15] $abc$23348$new_n4152 $abc$23348$new_n4155 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce xv[15][15] yv[15][5] $abc$23348$new_n4157 yv[16][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21514 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][4] xv[15][15] $abc$23348$new_n4135 $abc$23348$new_n4128 $abc$23348$new_n4157 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4159 yv[16][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21516 +001 1 +011 1 +110 1 +111 1 +.names yv[15][4] ph[15][19] xv[15][15] $abc$23348$new_n4135 $abc$23348$new_n4128 $abc$23348$new_n4159 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[15][15] yv[15][3] $abc$23348$new_n4161 yv[16][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21518 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][2] yv[15][0] yv[15][1] xv[15][15] $abc$23348$new_n4161 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4163 yv[16][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21520 +001 1 +011 1 +110 1 +111 1 +.names yv[15][2] ph[15][19] yv[15][0] yv[15][1] xv[15][15] $abc$23348$new_n4163 +00001 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n4165 yv[16][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21522 +001 1 +011 1 +100 1 +101 1 +.names yv[15][1] ph[15][19] yv[15][0] xv[15][15] $abc$23348$new_n4165 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1001 1 +1111 1 +.names i_ce xv[15][15] yv[15][0] yv[16][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21524 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[15][15] xv[15][14] $abc$23348$new_n4168 xv[16][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21526 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4177 $abc$23348$new_n4169 ph[15][19] $abc$23348$new_n4168 +100 1 +110 1 +111 1 +.names $abc$23348$new_n4170 yv[15][15] xv[15][12] xv[15][13] $abc$23348$new_n4169 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$23348$new_n4176 yv[15][15] $abc$23348$new_n4172 xv[15][10] xv[15][11] $abc$23348$new_n4170 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$23348$new_n4175 yv[15][15] $abc$23348$new_n4174 xv[15][6] xv[15][7] $abc$23348$new_n4172 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names yv[15][15] xv[15][1] xv[15][2] xv[15][3] xv[15][0] $abc$23348$new_n4174 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[15][15] xv[15][5] xv[15][4] $abc$23348$new_n4175 +000 1 +001 1 +010 1 +011 1 +100 1 +.names yv[15][15] xv[15][9] xv[15][8] $abc$23348$new_n4176 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$23348$new_n4178 yv[15][15] ph[15][19] xv[15][13] $abc$23348$new_n4177 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n4179 yv[15][15] ph[15][19] xv[15][12] xv[15][11] $abc$23348$new_n4178 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[15][15] ph[15][19] xv[15][9] xv[15][10] $abc$23348$new_n4180 $abc$23348$new_n4179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][5] xv[15][6] xv[15][7] xv[15][8] $abc$23348$new_n4181 $abc$23348$new_n4180 +11111 1 +.names xv[15][4] $abc$23348$new_n4182 $abc$23348$new_n4181 +11 1 +.names xv[15][0] xv[15][1] xv[15][2] xv[15][3] $abc$23348$new_n4182 +1111 1 +.names i_ce yv[15][15] xv[15][13] $abc$23348$new_n4184 xv[16][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$21528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4178 $abc$23348$new_n4170 ph[15][19] xv[15][12] yv[15][15] $abc$23348$new_n4184 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce yv[15][15] xv[15][12] $abc$23348$new_n4186 xv[16][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21530 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4179 ph[15][19] $abc$23348$new_n4170 xv[15][11] $abc$23348$new_n4186 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_ce yv[15][15] xv[15][11] $abc$23348$new_n4188 xv[16][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$21532 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4179 $abc$23348$new_n4189 xv[15][10] yv[15][15] ph[15][19] $abc$23348$new_n4188 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names ph[15][19] $abc$23348$new_n4172 $abc$23348$new_n4176 $abc$23348$new_n4189 +100 1 +101 1 +110 1 +.names i_ce yv[15][15] xv[15][10] $abc$23348$new_n4191 xv[16][10] $abc$23348$auto$rtlil.cc:2693:MuxGate$21534 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4189 yv[15][15] ph[15][19] $abc$23348$new_n4180 xv[15][9] $abc$23348$new_n4191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[15][15] xv[15][9] $abc$23348$new_n4193 xv[16][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$21536 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] yv[15][15] xv[15][8] $abc$23348$new_n4172 $abc$23348$new_n4180 $abc$23348$new_n4193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[15][15] xv[15][8] $abc$23348$new_n4195 xv[16][8] $abc$23348$auto$rtlil.cc:2693:MuxGate$21538 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4196 $abc$23348$new_n4172 xv[15][7] ph[15][19] $abc$23348$new_n4195 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names yv[15][15] ph[15][19] $abc$23348$new_n4181 xv[15][6] xv[15][5] $abc$23348$new_n4196 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce yv[15][15] xv[15][7] $abc$23348$new_n4198 xv[16][7] $abc$23348$auto$rtlil.cc:2693:MuxGate$21540 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4196 $abc$23348$new_n4199 xv[15][6] yv[15][15] ph[15][19] $abc$23348$new_n4198 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names ph[15][19] $abc$23348$new_n4174 $abc$23348$new_n4175 $abc$23348$new_n4199 +100 1 +101 1 +110 1 +.names i_ce yv[15][15] xv[15][6] $abc$23348$new_n4201 xv[16][6] $abc$23348$auto$rtlil.cc:2693:MuxGate$21542 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4199 yv[15][15] ph[15][19] $abc$23348$new_n4181 xv[15][5] $abc$23348$new_n4201 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce yv[15][15] xv[15][5] $abc$23348$new_n4203 xv[16][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$21544 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] xv[15][4] yv[15][15] $abc$23348$new_n4174 $abc$23348$new_n4182 $abc$23348$new_n4203 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4205 xv[16][4] $abc$23348$auto$rtlil.cc:2693:MuxGate$21546 +001 1 +011 1 +110 1 +111 1 +.names xv[15][4] ph[15][19] yv[15][15] $abc$23348$new_n4174 $abc$23348$new_n4182 $abc$23348$new_n4205 +00101 1 +00111 1 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[15][15] xv[15][3] $abc$23348$new_n4207 xv[16][3] $abc$23348$auto$rtlil.cc:2693:MuxGate$21548 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[15][19] xv[15][2] xv[15][0] xv[15][1] yv[15][15] $abc$23348$new_n4207 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4209 xv[16][2] $abc$23348$auto$rtlil.cc:2693:MuxGate$21550 +001 1 +011 1 +110 1 +111 1 +.names xv[15][2] ph[15][19] xv[15][0] xv[15][1] yv[15][15] $abc$23348$new_n4209 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4211 xv[16][1] $abc$23348$auto$rtlil.cc:2693:MuxGate$21552 +001 1 +011 1 +110 1 +111 1 +.names xv[15][1] ph[15][19] xv[15][0] yv[15][15] $abc$23348$new_n4211 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce yv[15][15] xv[15][0] xv[16][0] $abc$23348$auto$rtlil.cc:2693:MuxGate$21554 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[15][15] xv[15][15] $abc$23348$new_n4214 xv[16][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21556 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4177 xv[15][14] ph[15][19] $abc$23348$new_n4169 yv[15][15] $abc$23348$new_n4214 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce yv[15][15] xv[15][15] $abc$23348$new_n4216 yv[16][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21558 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[15][19] xv[15][15] yv[15][14] $abc$23348$new_n4130 $abc$23348$new_n4122 $abc$23348$new_n4216 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[14][15] xv[14][15] $abc$23348$new_n4218 xv[15][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21560 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$23348$new_n4084 xv[14][14] ph[14][19] $abc$23348$new_n4076 yv[14][15] $abc$23348$new_n4218 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names i_ce yv[14][15] xv[14][15] $abc$23348$new_n4220 yv[15][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[14][19] xv[14][15] yv[14][14] $abc$23348$new_n4030 $abc$23348$new_n4038 $abc$23348$new_n4220 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4222 ph[15][19] ph[14][19] $abc$23348$new_n4227 $abc$23348$auto$rtlil.cc:2693:MuxGate$21564 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n4223 $abc$23348$new_n4226 ph[14][16] ph[14][17] ph[14][18] $abc$23348$new_n4222 +11000 1 +.names $abc$23348$new_n4224 $abc$23348$new_n4225 ph[14][7] ph[14][10] ph[14][15] $abc$23348$new_n4223 +11000 1 +.names ph[14][3] ph[14][4] ph[14][5] ph[14][6] $abc$23348$new_n4224 +0000 1 +.names ph[14][9] ph[14][8] ph[14][2] ph[14][0] ph[14][1] $abc$23348$new_n4225 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[14][11] ph[14][12] ph[14][13] ph[14][14] $abc$23348$new_n4226 +0000 1 +.names $abc$23348$new_n4228 $abc$23348$new_n4230 ph[14][2] ph[14][0] ph[14][1] $abc$23348$new_n4227 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[14][15] ph[14][16] ph[14][17] ph[14][18] $abc$23348$new_n4229 $abc$23348$new_n4228 +11111 1 +.names ph[14][11] ph[14][12] ph[14][13] ph[14][14] $abc$23348$new_n4229 +1111 1 +.names ph[14][7] ph[14][8] ph[14][9] ph[14][10] $abc$23348$new_n4231 $abc$23348$new_n4230 +11111 1 +.names ph[14][3] ph[14][4] ph[14][5] ph[14][6] $abc$23348$new_n4231 +1111 1 +.names i_ce yv[13][15] xv[13][15] $abc$23348$new_n4233 xv[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21566 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[13][19] xv[13][14] yv[13][15] $abc$23348$new_n3992 $abc$23348$new_n3985 $abc$23348$new_n4233 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[13][15] xv[13][15] $abc$23348$new_n4235 yv[14][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21568 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][19] xv[13][15] yv[13][14] $abc$23348$new_n3943 $abc$23348$new_n3936 $abc$23348$new_n4235 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n3885 ph[14][19] $abc$23348$new_n3890 ph[13][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21570 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names i_ce yv[12][15] xv[12][15] $abc$23348$new_n4238 xv[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[12][19] xv[12][14] yv[12][15] $abc$23348$new_n3845 $abc$23348$new_n3838 $abc$23348$new_n4238 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[12][15] xv[12][15] $abc$23348$new_n4240 yv[13][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21574 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[12][19] xv[12][15] yv[12][14] $abc$23348$new_n3797 $abc$23348$new_n3790 $abc$23348$new_n4240 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[13][19] $abc$23348$new_n4242 $abc$23348$new_n3746 $abc$23348$auto$rtlil.cc:2693:MuxGate$21576 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[12][18] ph[12][19] $abc$23348$new_n3742 ph[12][17] $abc$23348$new_n4242 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce yv[11][15] xv[11][15] $abc$23348$new_n4244 xv[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21578 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[11][19] xv[11][14] yv[11][15] $abc$23348$new_n3702 $abc$23348$new_n3695 $abc$23348$new_n4244 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[11][15] xv[11][15] $abc$23348$new_n4246 yv[12][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21580 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[11][19] xv[11][15] yv[11][14] $abc$23348$new_n3653 $abc$23348$new_n3646 $abc$23348$new_n4246 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[10][15] xv[10][15] $abc$23348$new_n4251 xv[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21584 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[10][19] xv[10][14] yv[10][15] $abc$23348$new_n3557 $abc$23348$new_n3547 $abc$23348$new_n4251 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[10][15] xv[10][15] $abc$23348$new_n4253 yv[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21586 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[10][19] xv[10][15] yv[10][14] $abc$23348$new_n3501 $abc$23348$new_n3489 $abc$23348$new_n4253 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[9][15] xv[9][15] $abc$23348$new_n4258 xv[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21590 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[9][19] xv[9][14] yv[9][15] $abc$23348$new_n3399 $abc$23348$new_n3391 $abc$23348$new_n4258 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[9][15] xv[9][15] $abc$23348$new_n4260 yv[10][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21592 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[9][19] xv[9][15] yv[9][14] $abc$23348$new_n3351 $abc$23348$new_n3343 $abc$23348$new_n4260 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[8][15] xv[8][15] $abc$23348$new_n4265 xv[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21596 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[8][19] xv[8][14] yv[8][15] $abc$23348$new_n3254 $abc$23348$new_n3244 $abc$23348$new_n4265 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[8][15] xv[8][15] $abc$23348$new_n4267 yv[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21598 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[8][19] xv[8][15] yv[8][14] $abc$23348$new_n3204 $abc$23348$new_n3195 $abc$23348$new_n4267 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[9][19] $abc$23348$new_n4269 $abc$23348$new_n4270 $abc$23348$auto$rtlil.cc:2693:MuxGate$21600 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n3141 $abc$23348$new_n4269 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$23348$new_n3148 ph[8][18] ph[8][19] ph[8][16] ph[8][17] $abc$23348$new_n4270 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names i_ce yv[7][15] xv[7][15] $abc$23348$new_n4272 xv[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[7][19] xv[7][14] yv[7][15] $abc$23348$new_n3102 $abc$23348$new_n3094 $abc$23348$new_n4272 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[7][15] xv[7][15] $abc$23348$new_n4274 yv[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21604 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[7][19] xv[7][15] yv[7][14] $abc$23348$new_n3055 $abc$23348$new_n3047 $abc$23348$new_n4274 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[6][15] xv[6][15] $abc$23348$new_n4279 xv[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21608 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[6][19] xv[6][14] yv[6][15] $abc$23348$new_n2955 $abc$23348$new_n2944 $abc$23348$new_n4279 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[6][15] xv[6][15] $abc$23348$new_n4281 yv[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21610 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[6][19] xv[6][15] yv[6][14] $abc$23348$new_n2906 $abc$23348$new_n2894 $abc$23348$new_n4281 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce ph[7][19] $abc$23348$new_n4283 $abc$23348$new_n2844 $abc$23348$auto$rtlil.cc:2693:MuxGate$21612 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names ph[6][18] ph[6][19] ph[6][16] ph[6][17] $abc$23348$new_n2850 $abc$23348$new_n4283 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names i_ce yv[5][15] xv[5][15] $abc$23348$new_n4285 xv[6][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21614 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[5][19] xv[5][14] yv[5][15] $abc$23348$new_n2806 $abc$23348$new_n2799 $abc$23348$new_n4285 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[5][15] xv[5][15] $abc$23348$new_n4287 yv[6][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21616 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[5][19] xv[5][15] yv[5][14] $abc$23348$new_n2761 $abc$23348$new_n2754 $abc$23348$new_n4287 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[4][15] xv[4][15] $abc$23348$new_n4292 xv[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21620 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[4][19] xv[4][14] yv[4][15] $abc$23348$new_n2667 $abc$23348$new_n2660 $abc$23348$new_n4292 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[4][15] xv[4][15] $abc$23348$new_n4294 yv[5][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21622 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[4][19] xv[4][15] yv[4][14] $abc$23348$new_n2621 $abc$23348$new_n2614 $abc$23348$new_n4294 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2560 ph[5][19] $abc$23348$new_n2567 ph[4][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21624 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[3][15] xv[3][15] $abc$23348$new_n4297 xv[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21626 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[3][19] xv[3][14] yv[3][15] $abc$23348$new_n2525 $abc$23348$new_n2518 $abc$23348$new_n4297 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[3][15] xv[3][15] $abc$23348$new_n4299 yv[4][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21628 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] yv[3][14] $abc$23348$new_n2479 $abc$23348$new_n2472 $abc$23348$new_n4299 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2431 ph[4][19] $abc$23348$new_n2435 ph[3][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce yv[2][15] xv[2][15] $abc$23348$new_n4302 xv[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21632 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[2][19] xv[2][14] yv[2][15] $abc$23348$new_n2392 $abc$23348$new_n2385 $abc$23348$new_n4302 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[2][15] xv[2][15] $abc$23348$new_n4304 yv[3][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21634 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][15] yv[2][14] $abc$23348$new_n2347 $abc$23348$new_n2340 $abc$23348$new_n4304 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[1][15] xv[1][15] $abc$23348$new_n4309 xv[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21638 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[1][19] xv[1][14] yv[1][15] $abc$23348$new_n2251 $abc$23348$new_n2244 $abc$23348$new_n4309 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce yv[1][15] xv[1][15] $abc$23348$new_n4311 yv[2][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21640 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][15] yv[1][14] $abc$23348$new_n2204 $abc$23348$new_n2197 $abc$23348$new_n4311 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[0][15] xv[0][15] $abc$23348$new_n4316 xv[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21644 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0][19] xv[0][14] yv[0][15] $abc$23348$new_n2110 $abc$23348$new_n2103 $abc$23348$new_n4316 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce yv[0][15] xv[0][15] $abc$23348$new_n4318 yv[1][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21646 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][15] yv[0][14] $abc$23348$new_n2063 $abc$23348$new_n2056 $abc$23348$new_n4318 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n2014 ph[1][19] $abc$23348$new_n2019 ph[0][18] $abc$23348$auto$rtlil.cc:2693:MuxGate$21648 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names i_ce $abc$23348$new_n4321 o_xval[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21650 +001 1 +011 1 +110 1 +111 1 +.names xv[16][15] xv[16][13] xv[16][14] $abc$23348$new_n1994 $abc$23348$new_n4321 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$23348$new_n4323 o_yval[12] $abc$23348$auto$rtlil.cc:2693:MuxGate$21652 +001 1 +011 1 +110 1 +111 1 +.names yv[16][15] yv[16][13] yv[16][14] $abc$23348$new_n1974 $abc$23348$new_n4323 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ax[16] o_aux $abc$23348$auto$rtlil.cc:2693:MuxGate$21654 +001 1 +011 1 +110 1 +111 1 +.names $abc$23348$new_n1935 $abc$23348$new_n4326 xv[0][15] i_ce $abc$23348$auto$rtlil.cc:2693:MuxGate$21656 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$23348$new_n1885 $abc$23348$new_n1869 $abc$23348$new_n4327 $abc$23348$new_n4328 $abc$23348$new_n4326 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_yval[12] $abc$23348$new_n1865 $abc$23348$new_n4327 +00 1 +.names i_xval[12] $abc$23348$new_n1871 $abc$23348$new_n4328 +00 1 +.names $abc$23348$new_n4330 $abc$23348$new_n4328 $abc$23348$new_n1881 i_ce yv[0][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21658 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11101 1 +11110 1 +11111 1 +.names $abc$23348$new_n1874 $abc$23348$new_n1869 $abc$23348$new_n1885 $abc$23348$new_n4327 i_xval[12] $abc$23348$new_n4330 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_phase[17] ph[0][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21660 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[15] ax[16] $abc$23348$auto$rtlil.cc:2693:MuxGate$21662 +001 1 +011 1 +110 1 +111 1 +.names $abc$23348$new_n1869 i_yval[1] i_yval[0] i_xval[1] i_xval[0] $abc$23348$new_n4333 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names i_ce $abc$23348$new_n1969 xv[0][3] $abc$23348$new_n1885 $abc$23348$new_n4333 $abc$23348$auto$rtlil.cc:2693:MuxGate$19970 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names ph[0][19] xv[0][13] yv[0][12] $abc$23348$new_n2057 $abc$23348$new_n2064 $abc$23348$new_n4335 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][14] $abc$23348$new_n4335 yv[0][13] yv[1][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20066 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[0][19] xv[0][11] yv[0][10] $abc$23348$new_n2058 $abc$23348$new_n2065 $abc$23348$new_n4337 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][12] $abc$23348$new_n4337 yv[0][11] yv[1][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20070 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][14] yv[1][12] $abc$23348$new_n2198 $abc$23348$new_n2205 $abc$23348$new_n4339 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[1][15] $abc$23348$new_n4339 yv[1][13] yv[2][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20164 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][12] yv[1][10] $abc$23348$new_n2199 $abc$23348$new_n2206 $abc$23348$new_n4341 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[1][13] $abc$23348$new_n4341 yv[1][11] yv[2][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20168 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[1][19] xv[1][4] yv[1][6] $abc$23348$new_n2249 $abc$23348$new_n2256 $abc$23348$new_n4343 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[1][5] $abc$23348$new_n4343 yv[1][7] xv[2][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20210 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][15] yv[2][12] $abc$23348$new_n2348 $abc$23348$new_n2341 $abc$23348$new_n4345 +00100 1 +00110 1 +01001 1 +01011 1 +10010 1 +10011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4345 yv[2][13] yv[3][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20262 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][19] xv[2][8] yv[2][11] $abc$23348$new_n2388 $abc$23348$new_n2395 $abc$23348$new_n4347 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][9] $abc$23348$new_n4347 yv[2][12] xv[3][9] $abc$23348$auto$rtlil.cc:2693:MuxGate$20300 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[2][19] xv[2][4] yv[2][7] $abc$23348$new_n2390 $abc$23348$new_n2397 $abc$23348$new_n4349 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][5] $abc$23348$new_n4349 yv[2][8] xv[3][5] $abc$23348$auto$rtlil.cc:2693:MuxGate$20308 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[3][19] xv[3][15] $abc$23348$new_n2480 yv[3][12] $abc$23348$new_n2489 $abc$23348$new_n4351 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4351 yv[3][13] yv[4][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20360 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[4][19] xv[4][15] $abc$23348$new_n2633 yv[4][11] $abc$23348$new_n2615 $abc$23348$new_n4353 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11010 1 +11011 1 +.names i_ce $abc$23348$new_n4353 yv[4][12] yv[5][12] $abc$23348$auto$rtlil.cc:2693:MuxGate$20460 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[4][15] ph[4][19] $abc$23348$new_n2616 yv[4][10] $abc$23348$new_n2633 $abc$23348$new_n4355 +00010 1 +00011 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4355 yv[4][11] yv[5][11] $abc$23348$auto$rtlil.cc:2693:MuxGate$20462 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[6][14] ph[6][19] $abc$23348$new_n2851 $abc$23348$new_n2846 ph[6][13] $abc$23348$new_n4357 +00010 1 +00110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4357 ph[6][15] ph[7][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20620 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][19] ph[7][15] ph[7][14] $abc$23348$new_n2996 $abc$23348$new_n3002 $abc$23348$new_n4359 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4359 ph[8][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20718 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] $abc$23348$new_n2997 $abc$23348$new_n3003 ph[7][12] ph[7][11] $abc$23348$new_n4361 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names i_ce $abc$23348$new_n4361 ph[7][13] ph[8][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20722 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][19] ph[8][15] ph[8][14] $abc$23348$new_n3149 $abc$23348$new_n3142 $abc$23348$new_n4363 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4363 ph[9][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$20816 +001 1 +011 1 +110 1 +111 1 +.names ph[8][19] $abc$23348$new_n3147 $abc$23348$new_n3143 $abc$23348$new_n3154 $abc$23348$new_n3150 $abc$23348$new_n4365 +00011 1 +00111 1 +01011 1 +01111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4365 ph[8][13] ph[9][13] $abc$23348$auto$rtlil.cc:2693:MuxGate$20820 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[10][19] ph[10][14] $abc$23348$new_n3440 $abc$23348$new_n3446 ph[10][13] $abc$23348$new_n4367 +00010 1 +00110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$23348$new_n4367 ph[10][15] ph[11][15] $abc$23348$auto$rtlil.cc:2693:MuxGate$21012 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4369 +00100 1 +00101 1 +00110 1 +00111 1 +11010 1 +11110 1 +.names $abc$23348$new_n4369 yv[10][10] xv[10][15] $abc$23348$new_n3497 ph[10][19] $abc$23348$new_n4370 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$23348$new_n3498 ph[10][19] $abc$23348$new_n3491 $abc$23348$new_n3511 $abc$23348$new_n3503 $abc$23348$new_n4371 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$23348$new_n4371 $abc$23348$new_n3497 ph[10][19] xv[10][15] $abc$23348$new_n4372 +0000 1 +0001 1 +0100 1 +0101 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names ph[11][19] ph[11][14] ph[11][13] $abc$23348$new_n3601 $abc$23348$new_n3607 $abc$23348$new_n4373 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$23348$new_n4373 ph[12][14] $abc$23348$auto$rtlil.cc:2693:MuxGate$21112 +001 1 +011 1 +110 1 +111 1 +.names yv[11][3] yv[11][4] yv[11][5] yv[11][6] yv[11][7] $abc$23348$new_n4375 +00000 1 +11111 1 +.names xv[11][15] $abc$23348$new_n4375 $abc$23348$new_n3658 yv[11][7] $abc$23348$new_n4376 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ph[11][19] ph[11][17] ph[11][18] $abc$23348$new_n3605 $abc$23348$new_n3599 $abc$23348$new_n4377 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4377 ph[12][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21582 +001 1 +011 1 +110 1 +111 1 +.names ph[10][19] ph[10][16] ph[10][17] ph[10][18] $abc$23348$new_n3439 $abc$23348$new_n4379 +00000 1 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce ph[11][19] $abc$23348$new_n4379 $abc$23348$new_n3445 $abc$23348$auto$rtlil.cc:2693:MuxGate$21588 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names ph[9][19] ph[9][17] ph[9][18] $abc$23348$new_n3294 $abc$23348$new_n3299 $abc$23348$new_n4381 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4381 ph[10][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21594 +001 1 +011 1 +110 1 +111 1 +.names ph[7][19] ph[7][17] ph[7][18] $abc$23348$new_n3001 $abc$23348$new_n2995 $abc$23348$new_n4383 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4383 ph[8][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21606 +001 1 +011 1 +110 1 +111 1 +.names ph[5][19] ph[5][17] ph[5][18] $abc$23348$new_n2704 $abc$23348$new_n2711 $abc$23348$new_n4385 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4385 ph[6][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21618 +001 1 +011 1 +110 1 +111 1 +.names ph[2][19] ph[2][17] ph[2][18] $abc$23348$new_n2289 $abc$23348$new_n2294 $abc$23348$new_n4387 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4387 ph[3][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21636 +001 1 +011 1 +110 1 +111 1 +.names ph[1][19] ph[1][17] ph[1][18] $abc$23348$new_n2146 $abc$23348$new_n2151 $abc$23348$new_n4389 +00001 1 +00011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$23348$new_n4389 ph[2][19] $abc$23348$auto$rtlil.cc:2693:MuxGate$21642 +001 1 +011 1 +110 1 +111 1 +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21554 Q=xv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21552 Q=xv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21550 Q=xv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21548 Q=xv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21546 Q=xv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21544 Q=xv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21542 Q=xv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21540 Q=xv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21538 Q=xv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21536 Q=xv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21534 Q=xv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21532 Q=xv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21530 Q=xv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21528 Q=xv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21526 Q=xv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21556 Q=xv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21524 Q=yv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21522 Q=yv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21520 Q=yv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21518 Q=yv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21516 Q=yv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21514 Q=yv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21512 Q=yv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21510 Q=yv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21508 Q=yv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21506 Q=yv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21504 Q=yv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21502 Q=yv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21500 Q=yv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21498 Q=yv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21496 Q=yv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21558 Q=yv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21494 Q=xv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21492 Q=xv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21490 Q=xv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21488 Q=xv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21486 Q=xv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21484 Q=xv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21482 Q=xv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21480 Q=xv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21478 Q=xv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21476 Q=xv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21474 Q=xv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21472 Q=xv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21470 Q=xv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21468 Q=xv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21466 Q=xv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21560 Q=xv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21464 Q=yv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21462 Q=yv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21460 Q=yv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21458 Q=yv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21456 Q=yv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21454 Q=yv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21452 Q=yv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21450 Q=yv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21448 Q=yv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21446 Q=yv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21444 Q=yv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21442 Q=yv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21440 Q=yv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21438 Q=yv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21436 Q=yv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21562 Q=yv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21564 Q=ph[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21396 Q=xv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21394 Q=xv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21392 Q=xv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21390 Q=xv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21388 Q=xv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21386 Q=xv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21384 Q=xv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21382 Q=xv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21380 Q=xv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21378 Q=xv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21376 Q=xv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21374 Q=xv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21372 Q=xv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21370 Q=xv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21368 Q=xv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21566 Q=xv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21366 Q=yv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21364 Q=yv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21362 Q=yv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21360 Q=yv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21358 Q=yv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21356 Q=yv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21354 Q=yv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21352 Q=yv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21350 Q=yv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21348 Q=yv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21346 Q=yv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21344 Q=yv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21342 Q=yv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21340 Q=yv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21338 Q=yv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21568 Q=yv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21336 Q=ph[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21334 Q=ph[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21332 Q=ph[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21330 Q=ph[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21328 Q=ph[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21326 Q=ph[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21324 Q=ph[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21322 Q=ph[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21320 Q=ph[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21318 Q=ph[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21316 Q=ph[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21314 Q=ph[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21312 Q=ph[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21310 Q=ph[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21308 Q=ph[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21306 Q=ph[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21304 Q=ph[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21302 Q=ph[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21300 Q=ph[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21570 Q=ph[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21298 Q=xv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21296 Q=xv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21294 Q=xv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21292 Q=xv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21290 Q=xv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21288 Q=xv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21286 Q=xv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21284 Q=xv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21282 Q=xv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21280 Q=xv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21278 Q=xv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21276 Q=xv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21274 Q=xv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21272 Q=xv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21270 Q=xv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21572 Q=xv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21268 Q=yv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21266 Q=yv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21264 Q=yv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21262 Q=yv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21260 Q=yv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21258 Q=yv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21256 Q=yv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21254 Q=yv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21252 Q=yv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21250 Q=yv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21248 Q=yv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21246 Q=yv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21244 Q=yv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21242 Q=yv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21240 Q=yv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21574 Q=yv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21238 Q=ph[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21236 Q=ph[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21234 Q=ph[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21232 Q=ph[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21230 Q=ph[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21228 Q=ph[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21226 Q=ph[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21224 Q=ph[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21222 Q=ph[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21220 Q=ph[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21218 Q=ph[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21216 Q=ph[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21214 Q=ph[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21212 Q=ph[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21210 Q=ph[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21208 Q=ph[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21206 Q=ph[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21204 Q=ph[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21202 Q=ph[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21576 Q=ph[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21200 Q=xv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21198 Q=xv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21196 Q=xv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21194 Q=xv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21192 Q=xv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21190 Q=xv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21188 Q=xv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21186 Q=xv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21184 Q=xv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21182 Q=xv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21180 Q=xv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21178 Q=xv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21176 Q=xv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21174 Q=xv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21172 Q=xv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21578 Q=xv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21170 Q=yv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21168 Q=yv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21166 Q=yv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21164 Q=yv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21162 Q=yv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21160 Q=yv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21158 Q=yv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21156 Q=yv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21154 Q=yv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21152 Q=yv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21150 Q=yv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21148 Q=yv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21146 Q=yv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21144 Q=yv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21142 Q=yv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21580 Q=yv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21140 Q=ph[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21138 Q=ph[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21136 Q=ph[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21134 Q=ph[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21132 Q=ph[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21130 Q=ph[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21128 Q=ph[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21126 Q=ph[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21124 Q=ph[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21122 Q=ph[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21120 Q=ph[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21118 Q=ph[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21116 Q=ph[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21114 Q=ph[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21112 Q=ph[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21110 Q=ph[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21108 Q=ph[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21106 Q=ph[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21104 Q=ph[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21582 Q=ph[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21102 Q=xv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21100 Q=xv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21098 Q=xv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21096 Q=xv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21094 Q=xv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21092 Q=xv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21090 Q=xv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21088 Q=xv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21086 Q=xv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21084 Q=xv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21082 Q=xv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21080 Q=xv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21078 Q=xv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21076 Q=xv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21074 Q=xv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21584 Q=xv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21072 Q=yv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21070 Q=yv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21068 Q=yv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21066 Q=yv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21064 Q=yv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21062 Q=yv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21060 Q=yv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21058 Q=yv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21056 Q=yv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21054 Q=yv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21052 Q=yv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21050 Q=yv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21048 Q=yv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21046 Q=yv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21044 Q=yv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21586 Q=yv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21042 Q=ph[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21040 Q=ph[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21038 Q=ph[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21036 Q=ph[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21034 Q=ph[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21032 Q=ph[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21030 Q=ph[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21028 Q=ph[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21026 Q=ph[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21024 Q=ph[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21022 Q=ph[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21020 Q=ph[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21018 Q=ph[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21016 Q=ph[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21014 Q=ph[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21012 Q=ph[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21010 Q=ph[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21008 Q=ph[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21006 Q=ph[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21588 Q=ph[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21004 Q=xv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21002 Q=xv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21000 Q=xv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20998 Q=xv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20996 Q=xv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20994 Q=xv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20992 Q=xv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20990 Q=xv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20988 Q=xv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20986 Q=xv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20984 Q=xv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20982 Q=xv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20980 Q=xv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20978 Q=xv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20976 Q=xv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21590 Q=xv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20974 Q=yv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20972 Q=yv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20970 Q=yv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20968 Q=yv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20966 Q=yv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20964 Q=yv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20962 Q=yv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20960 Q=yv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20958 Q=yv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20956 Q=yv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20954 Q=yv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20952 Q=yv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20950 Q=yv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20948 Q=yv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20946 Q=yv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21592 Q=yv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20944 Q=ph[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20942 Q=ph[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20940 Q=ph[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20938 Q=ph[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20936 Q=ph[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20934 Q=ph[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20932 Q=ph[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20930 Q=ph[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20928 Q=ph[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20926 Q=ph[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20924 Q=ph[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20922 Q=ph[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20920 Q=ph[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20918 Q=ph[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20916 Q=ph[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20914 Q=ph[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20912 Q=ph[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20910 Q=ph[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20908 Q=ph[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21594 Q=ph[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20906 Q=xv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20904 Q=xv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20902 Q=xv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20900 Q=xv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20898 Q=xv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20896 Q=xv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20894 Q=xv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20892 Q=xv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20890 Q=xv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20888 Q=xv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20886 Q=xv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20884 Q=xv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20882 Q=xv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20880 Q=xv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20878 Q=xv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21596 Q=xv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20876 Q=yv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20874 Q=yv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20872 Q=yv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20870 Q=yv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20868 Q=yv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20866 Q=yv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20864 Q=yv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20862 Q=yv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20860 Q=yv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20858 Q=yv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20856 Q=yv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20854 Q=yv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20852 Q=yv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20850 Q=yv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20848 Q=yv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21598 Q=yv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20846 Q=ph[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20844 Q=ph[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20842 Q=ph[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20840 Q=ph[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20838 Q=ph[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20836 Q=ph[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20834 Q=ph[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20832 Q=ph[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20830 Q=ph[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20828 Q=ph[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20826 Q=ph[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20824 Q=ph[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20822 Q=ph[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20820 Q=ph[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20818 Q=ph[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20816 Q=ph[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20814 Q=ph[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20812 Q=ph[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20810 Q=ph[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21600 Q=ph[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20808 Q=xv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20806 Q=xv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20804 Q=xv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20802 Q=xv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20800 Q=xv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20798 Q=xv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20796 Q=xv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20794 Q=xv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20792 Q=xv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20790 Q=xv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20788 Q=xv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20786 Q=xv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20784 Q=xv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20782 Q=xv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20780 Q=xv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21602 Q=xv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20778 Q=yv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20776 Q=yv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20774 Q=yv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20772 Q=yv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20770 Q=yv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20768 Q=yv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20766 Q=yv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20764 Q=yv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20762 Q=yv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20760 Q=yv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20758 Q=yv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20756 Q=yv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20754 Q=yv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20752 Q=yv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20750 Q=yv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21604 Q=yv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20748 Q=ph[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20746 Q=ph[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20744 Q=ph[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20742 Q=ph[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20740 Q=ph[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20738 Q=ph[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20736 Q=ph[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20734 Q=ph[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20732 Q=ph[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20730 Q=ph[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20728 Q=ph[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20726 Q=ph[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20724 Q=ph[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20722 Q=ph[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20720 Q=ph[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20718 Q=ph[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20716 Q=ph[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20714 Q=ph[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20712 Q=ph[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21606 Q=ph[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20710 Q=xv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20708 Q=xv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20706 Q=xv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20704 Q=xv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20702 Q=xv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20700 Q=xv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20698 Q=xv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20696 Q=xv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20694 Q=xv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20692 Q=xv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20690 Q=xv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20688 Q=xv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20686 Q=xv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20684 Q=xv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20682 Q=xv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21608 Q=xv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20680 Q=yv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20678 Q=yv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20676 Q=yv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20674 Q=yv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20672 Q=yv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20670 Q=yv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20668 Q=yv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20666 Q=yv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20664 Q=yv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20662 Q=yv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20660 Q=yv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20658 Q=yv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20656 Q=yv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20654 Q=yv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20652 Q=yv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21610 Q=yv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20650 Q=ph[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20648 Q=ph[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20646 Q=ph[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20644 Q=ph[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20642 Q=ph[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20640 Q=ph[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20638 Q=ph[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20636 Q=ph[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20634 Q=ph[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20632 Q=ph[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20630 Q=ph[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20628 Q=ph[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20626 Q=ph[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20624 Q=ph[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20622 Q=ph[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20620 Q=ph[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20618 Q=ph[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20616 Q=ph[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20614 Q=ph[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21612 Q=ph[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20612 Q=xv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20610 Q=xv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20608 Q=xv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20606 Q=xv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20604 Q=xv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20602 Q=xv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20600 Q=xv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20598 Q=xv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20596 Q=xv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20594 Q=xv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20592 Q=xv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20590 Q=xv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20588 Q=xv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20586 Q=xv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20584 Q=xv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21614 Q=xv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20582 Q=yv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20580 Q=yv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20578 Q=yv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20576 Q=yv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20574 Q=yv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20572 Q=yv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20570 Q=yv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20568 Q=yv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20566 Q=yv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20564 Q=yv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20562 Q=yv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20560 Q=yv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20558 Q=yv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20556 Q=yv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20554 Q=yv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21616 Q=yv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20552 Q=ph[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20550 Q=ph[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20548 Q=ph[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20546 Q=ph[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20544 Q=ph[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20542 Q=ph[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20540 Q=ph[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20538 Q=ph[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20536 Q=ph[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20534 Q=ph[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20532 Q=ph[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20530 Q=ph[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20528 Q=ph[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20526 Q=ph[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20524 Q=ph[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20522 Q=ph[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20520 Q=ph[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20518 Q=ph[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20516 Q=ph[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21618 Q=ph[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20514 Q=xv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20512 Q=xv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20510 Q=xv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20508 Q=xv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20506 Q=xv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20504 Q=xv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20502 Q=xv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20500 Q=xv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20498 Q=xv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20496 Q=xv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20494 Q=xv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20492 Q=xv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20490 Q=xv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20488 Q=xv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20486 Q=xv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21620 Q=xv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20484 Q=yv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20482 Q=yv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20480 Q=yv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20478 Q=yv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20476 Q=yv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20474 Q=yv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20472 Q=yv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20470 Q=yv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20468 Q=yv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20466 Q=yv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20464 Q=yv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20462 Q=yv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20460 Q=yv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20458 Q=yv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20456 Q=yv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21622 Q=yv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20454 Q=ph[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20452 Q=ph[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20450 Q=ph[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20448 Q=ph[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20446 Q=ph[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20444 Q=ph[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20442 Q=ph[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20440 Q=ph[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20438 Q=ph[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20436 Q=ph[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20434 Q=ph[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20432 Q=ph[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20430 Q=ph[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20428 Q=ph[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20426 Q=ph[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20424 Q=ph[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20422 Q=ph[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20420 Q=ph[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20418 Q=ph[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21624 Q=ph[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20416 Q=xv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20414 Q=xv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20412 Q=xv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20410 Q=xv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20408 Q=xv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20406 Q=xv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20404 Q=xv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20402 Q=xv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20400 Q=xv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20398 Q=xv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20396 Q=xv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20394 Q=xv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20392 Q=xv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20390 Q=xv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20388 Q=xv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21626 Q=xv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20386 Q=yv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20384 Q=yv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20382 Q=yv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20380 Q=yv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20378 Q=yv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20376 Q=yv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20374 Q=yv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20372 Q=yv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20370 Q=yv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20368 Q=yv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20366 Q=yv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20364 Q=yv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20362 Q=yv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20360 Q=yv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20358 Q=yv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21628 Q=yv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20356 Q=ph[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20354 Q=ph[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20352 Q=ph[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20350 Q=ph[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20348 Q=ph[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20346 Q=ph[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20344 Q=ph[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20342 Q=ph[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20340 Q=ph[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20338 Q=ph[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20336 Q=ph[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20334 Q=ph[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20332 Q=ph[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20330 Q=ph[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20328 Q=ph[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20326 Q=ph[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20324 Q=ph[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20322 Q=ph[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20320 Q=ph[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21630 Q=ph[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20318 Q=xv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20316 Q=xv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20314 Q=xv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20312 Q=xv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20310 Q=xv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20308 Q=xv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20306 Q=xv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20304 Q=xv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20302 Q=xv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20300 Q=xv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20298 Q=xv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20296 Q=xv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20294 Q=xv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20292 Q=xv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20290 Q=xv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21632 Q=xv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20288 Q=yv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20286 Q=yv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20284 Q=yv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20282 Q=yv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20280 Q=yv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20278 Q=yv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20276 Q=yv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20274 Q=yv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20272 Q=yv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20270 Q=yv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20268 Q=yv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20266 Q=yv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20264 Q=yv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20262 Q=yv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20260 Q=yv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21634 Q=yv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20258 Q=ph[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20256 Q=ph[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20254 Q=ph[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20252 Q=ph[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20250 Q=ph[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20248 Q=ph[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20246 Q=ph[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20244 Q=ph[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20242 Q=ph[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20240 Q=ph[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20238 Q=ph[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20236 Q=ph[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20234 Q=ph[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20232 Q=ph[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20230 Q=ph[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20228 Q=ph[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20226 Q=ph[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20224 Q=ph[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20222 Q=ph[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21636 Q=ph[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20220 Q=xv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20218 Q=xv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20216 Q=xv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20214 Q=xv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20212 Q=xv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20210 Q=xv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20208 Q=xv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20206 Q=xv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20204 Q=xv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20202 Q=xv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20200 Q=xv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20198 Q=xv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20196 Q=xv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20194 Q=xv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20192 Q=xv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21638 Q=xv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20190 Q=yv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20188 Q=yv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20186 Q=yv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20184 Q=yv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20182 Q=yv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20180 Q=yv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20178 Q=yv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20176 Q=yv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20174 Q=yv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20172 Q=yv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20170 Q=yv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20168 Q=yv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20166 Q=yv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20164 Q=yv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20162 Q=yv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21640 Q=yv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20160 Q=ph[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20158 Q=ph[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20156 Q=ph[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20154 Q=ph[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20152 Q=ph[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20150 Q=ph[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20148 Q=ph[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20146 Q=ph[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20144 Q=ph[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20142 Q=ph[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20140 Q=ph[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20138 Q=ph[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20136 Q=ph[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20134 Q=ph[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20132 Q=ph[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20130 Q=ph[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20128 Q=ph[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20126 Q=ph[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20124 Q=ph[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21642 Q=ph[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20122 Q=xv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20120 Q=xv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20118 Q=xv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20116 Q=xv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20114 Q=xv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20112 Q=xv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20110 Q=xv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20108 Q=xv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20106 Q=xv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20104 Q=xv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20102 Q=xv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20100 Q=xv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20098 Q=xv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20096 Q=xv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20094 Q=xv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21644 Q=xv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20092 Q=yv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20090 Q=yv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20088 Q=yv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20086 Q=yv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20084 Q=yv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20082 Q=yv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20080 Q=yv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20078 Q=yv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20076 Q=yv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20074 Q=yv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20072 Q=yv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20070 Q=yv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20068 Q=yv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20066 Q=yv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20064 Q=yv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21646 Q=yv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20062 Q=ph[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20060 Q=ph[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20058 Q=ph[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20056 Q=ph[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20054 Q=ph[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20052 Q=ph[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20050 Q=ph[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20048 Q=ph[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20046 Q=ph[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20044 Q=ph[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20042 Q=ph[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20040 Q=ph[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20038 Q=ph[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20036 Q=ph[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20034 Q=ph[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20032 Q=ph[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20030 Q=ph[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20028 Q=ph[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20026 Q=ph[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21648 Q=ph[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20024 Q=o_xval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20022 Q=o_xval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20020 Q=o_xval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20018 Q=o_xval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20016 Q=o_xval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20014 Q=o_xval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20012 Q=o_xval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20010 Q=o_xval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20008 Q=o_xval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20006 Q=o_xval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20004 Q=o_xval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20002 Q=o_xval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21650 Q=o_xval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$20000 Q=o_yval[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19998 Q=o_yval[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19996 Q=o_yval[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19994 Q=o_yval[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19992 Q=o_yval[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19990 Q=o_yval[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19988 Q=o_yval[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19986 Q=o_yval[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19984 Q=o_yval[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19982 Q=o_yval[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19980 Q=o_yval[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19978 Q=o_yval[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21652 Q=o_yval[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21654 Q=o_aux R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19976 Q=xv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19974 Q=xv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19972 Q=xv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19970 Q=xv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19968 Q=xv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19966 Q=xv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19964 Q=xv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19962 Q=xv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19960 Q=xv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19958 Q=xv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19956 Q=xv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19954 Q=xv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19952 Q=xv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19950 Q=xv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19948 Q=xv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21656 Q=xv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19946 Q=yv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19944 Q=yv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19942 Q=yv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19940 Q=yv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19938 Q=yv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19936 Q=yv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19934 Q=yv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19932 Q=yv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19930 Q=yv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19928 Q=yv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19926 Q=yv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19924 Q=yv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19922 Q=yv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19920 Q=yv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19918 Q=yv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21658 Q=yv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19916 Q=ph[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19914 Q=ph[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19912 Q=ph[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19910 Q=ph[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19908 Q=ph[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19906 Q=ph[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19904 Q=ph[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19902 Q=ph[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19900 Q=ph[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19898 Q=ph[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19896 Q=ph[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19894 Q=ph[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19892 Q=ph[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19890 Q=ph[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19888 Q=ph[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19886 Q=ph[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19884 Q=ph[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19882 Q=ph[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19880 Q=ph[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21660 Q=ph[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19878 Q=ax[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19876 Q=ax[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19874 Q=ax[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19872 Q=ax[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19870 Q=ax[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19868 Q=ax[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19866 Q=ax[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19864 Q=ax[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19862 Q=ax[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19860 Q=ax[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19858 Q=ax[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19856 Q=ax[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19854 Q=ax[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19852 Q=ax[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19850 Q=ax[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$19848 Q=ax[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$23348$auto$rtlil.cc:2693:MuxGate$21662 Q=ax[16] R=i_reset +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif new file mode 100644 index 00000000000..b9328ff6c7b --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/cordictanh.blif @@ -0,0 +1,19093 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model cordictanh +.inputs CLK EN z[-24] z[-23] z[-22] z[-21] z[-20] z[-19] z[-18] z[-17] z[-16] z[-15] z[-14] z[-13] z[-12] z[-11] z[-10] z[-9] z[-8] z[-7] z[-6] z[-5] z[-4] z[-3] z[-2] z[-1] z[0] z[1] z[2] z[3] z[4] z[5] z[6] z[7] +.outputs out[-24] out[-23] out[-22] out[-21] out[-20] out[-19] out[-18] out[-17] out[-16] out[-15] out[-14] out[-13] out[-12] out[-11] out[-10] out[-9] out[-8] out[-7] out[-6] out[-5] out[-4] out[-3] out[-2] out[-1] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] +.names $false +.names $true +1 +.names $undef +.names $abc$10488$new_n419 $abc$10488$new_n384 z[-13] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10002 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names z_[-13] $abc$10488$new_n416 z_[7] $abc$10488$new_n407 $abc$10488$new_n385 $abc$10488$new_n384 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$10488$new_n406 z_[-14] $abc$10488$new_n386 $abc$10488$new_n385 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n403 $abc$10488$new_n405 z_[-15] $abc$10488$new_n387 $abc$10488$new_n386 +0000 1 +0001 1 +0010 1 +0100 1 +1000 1 +1100 1 +.names z_[-16] $abc$10488$new_n402 $abc$10488$new_n388 $abc$10488$new_n387 +001 1 +100 1 +101 1 +111 1 +.names z_[-17] $abc$10488$new_n401 $abc$10488$new_n389 $abc$10488$new_n388 +000 1 +100 1 +101 1 +110 1 +.names $abc$10488$new_n400 z_[-18] $abc$10488$new_n390 $abc$10488$new_n389 +000 1 +100 1 +101 1 +110 1 +.names z_[-19] $abc$10488$new_n399 $abc$10488$new_n391 $abc$10488$new_n390 +001 1 +100 1 +101 1 +111 1 +.names z_[-20] $abc$10488$new_n398 $abc$10488$new_n392 $abc$10488$new_n391 +001 1 +100 1 +101 1 +111 1 +.names z_[-22] z_[-21] $abc$10488$new_n397 $abc$10488$new_n396 $abc$10488$new_n393 $abc$10488$new_n392 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names z_[-24] z_[-23] $abc$10488$new_n395 $abc$10488$new_n394 $abc$10488$new_n393 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n395 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n396 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[0] $abc$10488$new_n397 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n398 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n399 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n400 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n401 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] $abc$10488$new_n402 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n404 LOOKUP.index[4] $abc$10488$new_n403 +10 1 +.names LOOKUP.index[2] LOOKUP.index[3] $abc$10488$new_n404 +00 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n405 +11110 1 +.names LOOKUP.index[0] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n406 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-14] $abc$10488$new_n406 $abc$10488$new_n408 $abc$10488$new_n407 +000 1 +001 1 +011 1 +101 1 +.names z_[-15] $abc$10488$new_n405 $abc$10488$new_n403 $abc$10488$new_n409 $abc$10488$new_n408 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1101 1 +1111 1 +.names z_[-16] $abc$10488$new_n402 $abc$10488$new_n410 $abc$10488$new_n409 +000 1 +001 1 +011 1 +101 1 +.names z_[-17] $abc$10488$new_n401 $abc$10488$new_n411 $abc$10488$new_n410 +000 1 +001 1 +010 1 +100 1 +.names z_[-18] $abc$10488$new_n400 $abc$10488$new_n412 $abc$10488$new_n411 +010 1 +100 1 +110 1 +111 1 +.names z_[-19] $abc$10488$new_n399 $abc$10488$new_n413 $abc$10488$new_n412 +000 1 +001 1 +011 1 +101 1 +.names z_[-20] $abc$10488$new_n398 $abc$10488$new_n414 $abc$10488$new_n413 +000 1 +001 1 +011 1 +101 1 +.names z_[-22] $abc$10488$new_n397 z_[-21] $abc$10488$new_n396 $abc$10488$new_n415 $abc$10488$new_n414 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-24] $abc$10488$new_n395 z_[-23] $abc$10488$new_n394 $abc$10488$new_n415 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[0] $abc$10488$new_n418 $abc$10488$new_n403 $abc$10488$new_n417 $abc$10488$new_n416 +0000 1 +0010 1 +1000 1 +1001 1 +.names LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n417 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[3] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[4] $abc$10488$new_n418 +11100 1 +.names EN $abc$10488$new_n420 $abc$10488$new_n419 +00 1 +.names $abc$10488$new_n427 $abc$10488$new_n425 $abc$10488$new_n423 $abc$10488$new_n421 $abc$10488$new_n420 +1111 1 +.names $abc$10488$new_n422 z_[0] z_[1] z_[6] z_[-23] $abc$10488$new_n421 +10000 1 +.names z_[-4] z_[-3] z_[-2] z_[-1] $abc$10488$new_n422 +0000 1 +.names $abc$10488$new_n424 z_[-8] z_[-7] z_[-6] z_[-5] $abc$10488$new_n423 +10000 1 +.names z_[-12] z_[-11] z_[-10] z_[-9] $abc$10488$new_n424 +0000 1 +.names $abc$10488$new_n426 z_[2] z_[3] z_[-14] z_[-13] $abc$10488$new_n425 +10000 1 +.names z_[4] z_[5] z_[7] z_[-24] $abc$10488$new_n426 +0000 1 +.names $abc$10488$new_n428 z_[-22] z_[-21] z_[-20] z_[-19] $abc$10488$new_n427 +10000 1 +.names z_[-18] z_[-17] z_[-16] z_[-15] $abc$10488$new_n428 +0000 1 +.names $abc$10488$new_n430 z[-14] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10004 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-14] $abc$10488$new_n406 $abc$10488$new_n431 $abc$10488$new_n430 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n386 $abc$10488$new_n408 $abc$10488$new_n431 +000 1 +010 1 +110 1 +111 1 +.names $abc$10488$new_n419 $abc$10488$new_n433 z[-15] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10006 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n434 z_[7] $abc$10488$new_n409 $abc$10488$new_n387 $abc$10488$new_n433 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names z_[-15] $abc$10488$new_n405 $abc$10488$new_n403 $abc$10488$new_n434 +001 1 +010 1 +011 1 +100 1 +.names $abc$10488$new_n436 z[-16] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10008 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-16] $abc$10488$new_n402 $abc$10488$new_n437 $abc$10488$new_n436 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n388 $abc$10488$new_n410 $abc$10488$new_n437 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n439 z[-17] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10010 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-17] $abc$10488$new_n401 $abc$10488$new_n440 $abc$10488$new_n439 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n389 $abc$10488$new_n411 $abc$10488$new_n440 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n442 z[-18] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10012 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-18] $abc$10488$new_n400 $abc$10488$new_n443 $abc$10488$new_n442 +1000 1 +1011 1 +1101 1 +1110 1 +.names z_[7] $abc$10488$new_n390 $abc$10488$new_n412 $abc$10488$new_n443 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n445 z[-19] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10014 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-19] $abc$10488$new_n399 $abc$10488$new_n446 $abc$10488$new_n445 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n391 $abc$10488$new_n413 $abc$10488$new_n446 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n448 z[-20] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10016 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-20] $abc$10488$new_n398 $abc$10488$new_n449 $abc$10488$new_n448 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n392 $abc$10488$new_n414 $abc$10488$new_n449 +000 1 +010 1 +100 1 +101 1 +.names $abc$10488$new_n451 z[-21] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10018 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-21] $abc$10488$new_n396 $abc$10488$new_n452 $abc$10488$new_n451 +1000 1 +1011 1 +1101 1 +1110 1 +.names z_[7] z_[-22] $abc$10488$new_n397 $abc$10488$new_n415 $abc$10488$new_n393 $abc$10488$new_n452 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n454 z[-22] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10020 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-22] $abc$10488$new_n397 $abc$10488$new_n455 $abc$10488$new_n454 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n393 $abc$10488$new_n415 $abc$10488$new_n455 +001 1 +011 1 +110 1 +111 1 +.names EN z[-23] $abc$10488$new_n420 $abc$10488$new_n457 $abc$10488$auto$rtlil.cc:2693:MuxGate$10022 +0000 1 +0100 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names z_[-23] $abc$10488$new_n394 z_[7] z_[-24] $abc$10488$new_n395 $abc$10488$new_n457 +00000 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names EN $abc$10488$new_n395 z_[-24] $abc$10488$new_n420 z[-24] $abc$10488$auto$rtlil.cc:2693:MuxGate$10024 +00000 1 +00001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names EN $abc$10488$new_n419 z[7] $abc$10488$new_n460 $abc$10488$new_n485 $abc$10488$auto$rtlil.cc:2693:MuxGate$10026 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[6] $abc$10488$new_n461 z_[7] $abc$10488$new_n460 +001 1 +010 1 +011 1 +.names z_[2] z_[3] z_[4] z_[5] $abc$10488$new_n462 $abc$10488$new_n461 +00000 1 +.names z_[0] z_[1] $abc$10488$new_n417 $abc$10488$new_n405 $abc$10488$new_n463 $abc$10488$new_n462 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names z_[-2] $abc$10488$new_n484 z_[-1] $abc$10488$new_n483 $abc$10488$new_n464 $abc$10488$new_n463 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-4] $abc$10488$new_n482 z_[-3] $abc$10488$new_n479 $abc$10488$new_n465 $abc$10488$new_n464 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-6] $abc$10488$new_n478 z_[-5] $abc$10488$new_n477 $abc$10488$new_n466 $abc$10488$new_n465 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-8] $abc$10488$new_n476 z_[-7] $abc$10488$new_n475 $abc$10488$new_n467 $abc$10488$new_n466 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names z_[-10] $abc$10488$new_n474 z_[-9] $abc$10488$new_n473 $abc$10488$new_n468 $abc$10488$new_n467 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names z_[-11] $abc$10488$new_n472 $abc$10488$new_n469 $abc$10488$new_n468 +000 1 +001 1 +010 1 +100 1 +.names z_[-12] $abc$10488$new_n471 $abc$10488$new_n470 $abc$10488$new_n469 +011 1 +101 1 +110 1 +111 1 +.names z_[-13] $abc$10488$new_n416 $abc$10488$new_n407 $abc$10488$new_n470 +010 1 +100 1 +110 1 +111 1 +.names LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n471 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[3] $abc$10488$new_n472 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n473 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[1] LOOKUP.index[3] $abc$10488$new_n474 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n475 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names LOOKUP.index[2] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[3] $abc$10488$new_n476 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[4] LOOKUP.index[0] LOOKUP.index[2] $abc$10488$new_n477 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n478 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n481 $abc$10488$new_n403 $abc$10488$new_n480 $abc$10488$new_n479 +100 1 +101 1 +110 1 +.names LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n480 +11 1 +.names LOOKUP.index[4] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[0] $abc$10488$new_n481 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[2] $abc$10488$new_n482 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[1] $abc$10488$new_n403 $abc$10488$new_n481 $abc$10488$new_n483 +000 1 +001 1 +101 1 +110 1 +111 1 +.names LOOKUP.index[0] LOOKUP.index[4] LOOKUP.index[2] LOOKUP.index[3] LOOKUP.index[1] $abc$10488$new_n484 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names z_[7] z_[5] $abc$10488$new_n486 z_[4] $abc$10488$new_n485 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names z_[2] z_[3] $abc$10488$new_n487 $abc$10488$new_n486 +111 1 +.names z_[0] $abc$10488$new_n417 z_[1] $abc$10488$new_n405 $abc$10488$new_n488 $abc$10488$new_n487 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n484 z_[-2] z_[-1] $abc$10488$new_n483 $abc$10488$new_n489 $abc$10488$new_n488 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n482 z_[-4] z_[-3] $abc$10488$new_n479 $abc$10488$new_n490 $abc$10488$new_n489 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n478 z_[-6] z_[-5] $abc$10488$new_n477 $abc$10488$new_n491 $abc$10488$new_n490 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n476 z_[-8] z_[-7] $abc$10488$new_n475 $abc$10488$new_n492 $abc$10488$new_n491 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n474 z_[-10] z_[-9] $abc$10488$new_n473 $abc$10488$new_n493 $abc$10488$new_n492 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n472 z_[-11] $abc$10488$new_n494 $abc$10488$new_n493 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n471 z_[-12] $abc$10488$new_n495 $abc$10488$new_n494 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n416 z_[-13] $abc$10488$new_n385 $abc$10488$new_n495 +001 1 +100 1 +101 1 +111 1 +.names $abc$10488$new_n658 divider.x[7] $abc$10488$new_n497 $abc$10488$new_n671 $abc$10488$auto$rtlil.cc:2693:MuxGate$10028 +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$10488$new_n657 divider.y_[6] divider.y_[7] $abc$10488$new_n642 $abc$10488$new_n498 $abc$10488$new_n497 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11101 1 +11111 1 +.names $abc$10488$new_n641 $abc$10488$new_n638 $abc$10488$new_n639 $abc$10488$new_n499 $abc$10488$new_n636 $abc$10488$new_n498 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$10488$new_n634 divider.y_[2] $abc$10488$new_n635 $abc$10488$new_n500 $abc$10488$new_n632 $abc$10488$new_n499 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$10488$new_n631 divider.y_[0] divider.y_[1] $abc$10488$new_n630 $abc$10488$new_n501 $abc$10488$new_n500 +00001 1 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$abc$10488$new_n505 $abc$10488$new_n504 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names divider.y_[-10] divider.y_[-9] $abc$10488$new_n619 $abc$10488$new_n621 $abc$10488$new_n506 $abc$10488$new_n505 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n617 divider.y_[-12] divider.y_[-11] $abc$10488$new_n615 $abc$10488$new_n507 $abc$10488$new_n506 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n611 divider.y_[-14] divider.y_[-13] $abc$10488$new_n613 $abc$10488$new_n508 $abc$10488$new_n507 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names 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$abc$10488$new_n1026 $abc$10488$new_n1029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[5] divider.x[5] $abc$10488$new_n1029 $abc$10488$new_n1030 +001 1 +010 1 +100 1 +111 1 +.names divider.y[5] divider.x[5] divider.y[6] divider.x[6] $abc$10488$new_n1029 $abc$10488$new_n1031 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[4] $abc$10488$new_n1180 $abc$10488$new_n1035 z_[7] $abc$10488$new_n1034 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names $abc$10488$new_n1179 $abc$10488$new_n1177 $abc$10488$new_n1176 $abc$10488$new_n1203 $abc$10488$new_n1036 $abc$10488$new_n1035 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[0] $abc$10488$new_n1173 divider.y[1] $abc$10488$new_n1172 $abc$10488$new_n1037 $abc$10488$new_n1036 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n1166 $abc$10488$new_n1161 $abc$10488$new_n1170 $abc$10488$new_n1038 $abc$10488$new_n1171 $abc$10488$new_n1037 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[-6] $abc$10488$new_n1160 divider.y[-5] $abc$10488$new_n1159 $abc$10488$new_n1039 $abc$10488$new_n1038 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-8] $abc$10488$new_n1158 divider.y[-7] $abc$10488$new_n1157 $abc$10488$new_n1040 $abc$10488$new_n1039 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names divider.y[-10] divider.y[-9] $abc$10488$new_n1155 $abc$10488$new_n1154 $abc$10488$new_n1041 $abc$10488$new_n1040 +00010 1 +01000 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$10488$new_n1152 divider.y[-12] divider.y[-11] $abc$10488$new_n1150 $abc$10488$new_n1042 $abc$10488$new_n1041 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n1146 divider.y[-14] divider.y[-13] $abc$10488$new_n1148 $abc$10488$new_n1043 $abc$10488$new_n1042 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n1144 divider.y[-16] divider.y[-15] $abc$10488$new_n1142 $abc$10488$new_n1044 $abc$10488$new_n1043 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names divider.y[-18] $abc$10488$new_n1136 divider.y[-17] $abc$10488$new_n1131 $abc$10488$new_n1045 $abc$10488$new_n1044 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-20] $abc$10488$new_n1126 divider.y[-19] $abc$10488$new_n1121 $abc$10488$new_n1046 $abc$10488$new_n1045 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-22] $abc$10488$new_n1107 divider.y[-21] $abc$10488$new_n2217 $abc$10488$new_n1047 $abc$10488$new_n1046 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names $abc$10488$new_n2213 divider.y[-24] divider.y[-23] $abc$10488$new_n2210 $abc$10488$new_n1047 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names LOOKUP.index[2] $abc$10488$new_n1051 $abc$10488$new_n1053 $abc$10488$new_n1050 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1052 divider.x[-8] divider.x[-9] $abc$10488$new_n1051 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-10] divider.x[-11] $abc$10488$new_n1052 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1054 divider.x[-12] divider.x[-13] $abc$10488$new_n1053 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-14] divider.x[-15] $abc$10488$new_n1054 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1056 divider.x[-18] divider.x[-19] $abc$10488$new_n1055 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.x[-16] divider.x[-17] $abc$10488$new_n1056 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1059 $abc$10488$new_n1062 $abc$10488$new_n1058 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] $abc$10488$new_n1060 $abc$10488$new_n1061 $abc$10488$new_n1059 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.x[4] divider.x[3] $abc$10488$new_n1060 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[2] divider.x[1] $abc$10488$new_n1061 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] divider.x[7] divider.x[6] divider.x[5] $abc$10488$new_n1062 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] $abc$10488$new_n1064 $abc$10488$new_n1066 $abc$10488$new_n1063 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1065 divider.x[0] divider.x[-1] $abc$10488$new_n1064 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-2] divider.x[-3] $abc$10488$new_n1065 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1067 divider.x[-4] divider.x[-5] $abc$10488$new_n1066 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-6] divider.x[-7] $abc$10488$new_n1067 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1073 $abc$10488$new_n1075 $abc$10488$new_n1072 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1074 divider.x[-9] divider.x[-10] $abc$10488$new_n1073 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-11] divider.x[-12] $abc$10488$new_n1074 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1076 divider.x[-13] divider.x[-14] $abc$10488$new_n1075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-15] divider.x[-16] $abc$10488$new_n1076 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1079 $abc$10488$new_n1080 $abc$10488$new_n1078 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.x[-17] divider.x[-18] $abc$10488$new_n1079 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[-19] divider.x[-20] $abc$10488$new_n1080 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.x[-21] divider.x[-22] $abc$10488$new_n1082 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1085 $abc$10488$new_n1087 $abc$10488$new_n1084 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[7] divider.x[6] $abc$10488$new_n1085 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[5] divider.x[4] $abc$10488$new_n1086 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[3] divider.x[2] $abc$10488$new_n1087 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[1] divider.x[0] $abc$10488$new_n1088 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1090 $abc$10488$new_n1092 $abc$10488$new_n1089 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1091 divider.x[-1] divider.x[-2] $abc$10488$new_n1090 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-3] divider.x[-4] $abc$10488$new_n1091 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1093 divider.x[-5] divider.x[-6] $abc$10488$new_n1092 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.x[-7] divider.x[-8] $abc$10488$new_n1093 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1096 $abc$10488$new_n1099 divider.x[7] $abc$10488$new_n1095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1097 $abc$10488$new_n1098 $abc$10488$new_n1096 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1065 divider.x[-4] divider.x[-5] $abc$10488$new_n1097 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1061 divider.x[0] divider.x[-1] $abc$10488$new_n1098 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1060 divider.x[6] divider.x[5] $abc$10488$new_n1099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1102 $abc$10488$new_n1103 $abc$10488$new_n1101 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1067 divider.x[-8] divider.x[-9] $abc$10488$new_n1102 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1052 divider.x[-12] divider.x[-13] $abc$10488$new_n1103 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] $abc$10488$new_n1108 $abc$10488$new_n1115 $abc$10488$new_n1107 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1109 $abc$10488$new_n1112 $abc$10488$new_n1108 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1111 $abc$10488$new_n1109 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1086 divider.x[3] divider.x[2] $abc$10488$new_n1110 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[7] divider.x[6] $abc$10488$new_n1111 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1114 $abc$10488$new_n1112 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1091 divider.x[-5] divider.x[-6] $abc$10488$new_n1113 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1088 divider.x[-1] divider.x[-2] $abc$10488$new_n1114 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1116 $abc$10488$new_n1119 $abc$10488$new_n1120 $abc$10488$new_n1115 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1117 $abc$10488$new_n1118 $abc$10488$new_n1116 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1093 divider.x[-9] divider.x[-10] $abc$10488$new_n1117 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1074 divider.x[-13] divider.x[-14] $abc$10488$new_n1118 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] $abc$10488$new_n1076 $abc$10488$new_n1079 $abc$10488$new_n1119 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] $abc$10488$new_n1080 $abc$10488$new_n1082 $abc$10488$new_n1120 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1122 $abc$10488$new_n1124 $abc$10488$new_n403 $abc$10488$new_n1055 $abc$10488$new_n1121 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1123 $abc$10488$new_n1062 divider.x[7] $abc$10488$new_n1122 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1059 $abc$10488$new_n1064 $abc$10488$new_n1123 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1125 LOOKUP.index[2] $abc$10488$new_n1053 $abc$10488$new_n1124 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[2] $abc$10488$new_n1066 $abc$10488$new_n1051 $abc$10488$new_n1125 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1127 $abc$10488$new_n1129 $abc$10488$new_n1126 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1128 $abc$10488$new_n1085 divider.x[7] $abc$10488$new_n1127 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1087 $abc$10488$new_n1090 $abc$10488$new_n1128 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1130 $abc$10488$new_n1075 $abc$10488$new_n1078 $abc$10488$new_n1129 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1092 $abc$10488$new_n1073 $abc$10488$new_n1130 +001 1 +011 1 +110 1 +111 1 +.names $abc$10488$new_n1132 LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1135 divider.x[7] $abc$10488$new_n1131 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n1133 LOOKUP.index[1] $abc$10488$new_n403 $abc$10488$new_n1054 $abc$10488$new_n1056 $abc$10488$new_n1132 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1134 LOOKUP.index[2] $abc$10488$new_n1103 $abc$10488$new_n1133 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1097 $abc$10488$new_n1102 $abc$10488$new_n1134 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1099 $abc$10488$new_n1098 $abc$10488$new_n1135 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] $abc$10488$new_n1137 $abc$10488$new_n1139 $abc$10488$new_n1136 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1138 $abc$10488$new_n1118 $abc$10488$new_n1119 $abc$10488$new_n1137 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1113 $abc$10488$new_n1117 $abc$10488$new_n1138 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1140 $abc$10488$new_n1141 $abc$10488$new_n1139 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1110 $abc$10488$new_n1114 $abc$10488$new_n1140 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1111 divider.x[7] $abc$10488$new_n1141 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1143 $abc$10488$new_n1063 $abc$10488$new_n1050 $abc$10488$new_n1142 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1058 divider.x[7] $abc$10488$new_n1143 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1145 $abc$10488$new_n1089 $abc$10488$new_n1072 $abc$10488$new_n1144 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1084 divider.x[7] $abc$10488$new_n1145 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1147 $abc$10488$new_n1112 $abc$10488$new_n1116 $abc$10488$new_n1146 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1109 divider.x[7] $abc$10488$new_n1147 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1149 $abc$10488$new_n1096 $abc$10488$new_n1101 $abc$10488$new_n1148 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 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$abc$10488$new_n1085 $abc$10488$new_n1153 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1135 $abc$10488$new_n1134 $abc$10488$new_n1154 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1156 $abc$10488$new_n1138 $abc$10488$new_n1140 $abc$10488$new_n1155 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1141 divider.x[7] $abc$10488$new_n1156 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] divider.x[7] $abc$10488$new_n1058 $abc$10488$new_n1063 $abc$10488$new_n1157 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 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$abc$10488$new_n1163 divider.y[-1] $abc$10488$new_n1165 $abc$10488$new_n1167 $abc$10488$new_n1166 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names divider.y[-4] $abc$10488$new_n1169 divider.y[-3] $abc$10488$new_n1168 $abc$10488$new_n1167 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names LOOKUP.index[4] $abc$10488$new_n1122 divider.x[7] $abc$10488$new_n1168 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1127 divider.x[7] $abc$10488$new_n1169 +010 1 +011 1 +100 1 +110 1 +.names divider.y[-3] $abc$10488$new_n1168 $abc$10488$new_n1170 +00 1 +11 1 +.names divider.y[-4] $abc$10488$new_n1169 $abc$10488$new_n1171 +00 1 +11 1 +.names LOOKUP.index[4] $abc$10488$new_n1143 divider.x[7] $abc$10488$new_n1172 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1145 divider.x[7] $abc$10488$new_n1173 +010 1 +011 1 +100 1 +110 1 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1 +01110 1 +01111 1 +.names divider.y[4] $abc$10488$new_n1180 $abc$10488$new_n1204 $abc$10488$new_n1185 $abc$10488$new_n1205 $abc$10488$new_n1184 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$10488$new_n1186 $abc$10488$new_n1202 divider.y[1] $abc$10488$new_n1172 $abc$10488$new_n1203 $abc$10488$new_n1185 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$10488$new_n1201 $abc$10488$new_n1187 divider.y[-1] $abc$10488$new_n1165 $abc$10488$new_n1200 $abc$10488$new_n1186 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$10488$new_n1198 $abc$10488$new_n1162 $abc$10488$new_n1199 $abc$10488$new_n1188 $abc$10488$new_n1171 $abc$10488$new_n1187 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +.names divider.y[-6] divider.y[-5] $abc$10488$new_n1160 $abc$10488$new_n1159 $abc$10488$new_n1189 $abc$10488$new_n1188 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n1158 divider.y[-8] divider.y[-7] $abc$10488$new_n1157 $abc$10488$new_n1190 $abc$10488$new_n1189 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names divider.y[-10] $abc$10488$new_n1155 divider.y[-9] $abc$10488$new_n1154 $abc$10488$new_n1191 $abc$10488$new_n1190 +00100 1 +00101 1 +01001 1 +01100 1 +01101 1 +01111 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[-12] $abc$10488$new_n1152 divider.y[-11] $abc$10488$new_n1150 $abc$10488$new_n1192 $abc$10488$new_n1191 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[-14] $abc$10488$new_n1146 divider.y[-13] $abc$10488$new_n1148 $abc$10488$new_n1193 $abc$10488$new_n1192 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[-16] $abc$10488$new_n1144 divider.y[-15] $abc$10488$new_n1142 $abc$10488$new_n1194 $abc$10488$new_n1193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names divider.y[-18] divider.y[-17] $abc$10488$new_n1136 $abc$10488$new_n1131 $abc$10488$new_n1195 $abc$10488$new_n1194 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n1126 divider.y[-20] divider.y[-19] $abc$10488$new_n1121 $abc$10488$new_n1196 $abc$10488$new_n1195 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names divider.y[-22] divider.y[-21] $abc$10488$new_n1107 $abc$10488$new_n2217 $abc$10488$new_n1197 $abc$10488$new_n1196 +00010 1 +01000 1 +01010 1 +01011 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names divider.y[-24] $abc$10488$new_n2213 divider.y[-23] $abc$10488$new_n2210 $abc$10488$new_n1197 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$10488$new_n1168 divider.y[-3] $abc$10488$new_n1198 +10 1 +.names divider.y[-3] $abc$10488$new_n1168 divider.y[-4] $abc$10488$new_n1169 $abc$10488$new_n1199 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$10488$new_n1173 divider.y[0] $abc$10488$new_n1200 +10 1 +.names divider.y[-2] $abc$10488$new_n1163 $abc$10488$new_n1201 +10 1 +.names divider.y[0] $abc$10488$new_n1173 $abc$10488$new_n1202 +10 1 +.names divider.y[2] $abc$10488$new_n1175 $abc$10488$new_n1203 +01 1 +10 1 +.names divider.y[2] $abc$10488$new_n1175 divider.y[3] $abc$10488$new_n1178 $abc$10488$new_n1204 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$10488$new_n1178 divider.y[3] $abc$10488$new_n1205 +10 1 +.names z_[7] $abc$10488$new_n1207 $abc$10488$new_n1206 +00 1 +.names LOOKUP.index[4] divider.y[6] divider.x[7] $abc$10488$new_n1156 $abc$10488$new_n1207 +0001 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names divider.y[6] LOOKUP.index[4] z_[7] $abc$10488$new_n1156 divider.x[7] $abc$10488$new_n1208 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n1210 $abc$10488$new_n1211 $abc$10488$new_n1209 +10 1 +.names $abc$10488$new_n420 LOOKUP.index[3] $abc$10488$new_n480 LOOKUP.index[2] LOOKUP.index[4] $abc$10488$new_n1210 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names LOOKUP.index[3] LOOKUP.index[1] LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[4] $abc$10488$new_n1211 +11100 1 +.names LOOKUP.index[4] $abc$10488$new_n404 LOOKUP.index[0] LOOKUP.index[1] $abc$10488$new_n1212 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names divider.x[7] divider.y[7] $abc$10488$new_n1213 +00 1 +11 1 +.names LOOKUP.index[4] $abc$10488$new_n1216 $abc$10488$new_n480 LOOKUP.index[2] LOOKUP.index[3] $abc$10488$auto$rtlil.cc:2693:MuxGate$10036 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$10488$new_n1210 IS_FIRST13 $abc$10488$new_n418 IS_FIRST4 $abc$10488$new_n1217 $abc$10488$new_n1216 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names LOOKUP.index[2] LOOKUP.index[0] LOOKUP.index[1] LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n1217 +10000 1 +.names $abc$10488$new_n1030 $abc$10488$new_n1378 $abc$10488$new_n1379 $abc$10488$new_n1028 $abc$10488$new_n1221 $abc$10488$new_n1220 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n1027 $abc$10488$new_n1377 $abc$10488$new_n1376 $abc$10488$new_n1025 $abc$10488$new_n1222 $abc$10488$new_n1221 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n1024 $abc$10488$new_n1375 $abc$10488$new_n1374 $abc$10488$new_n1022 $abc$10488$new_n1223 $abc$10488$new_n1222 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n1372 $abc$10488$new_n1021 $abc$10488$new_n1373 $abc$10488$new_n1019 $abc$10488$new_n1224 $abc$10488$new_n1223 +00000 1 +00001 1 +00010 1 +00011 1 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divider.y[7] divider.y[-14] divider.y[-15] $abc$10488$new_n1276 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1278 $abc$10488$new_n1279 $abc$10488$new_n1277 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$10488$new_n756 LOOKUP.index[0] divider.y[7] divider.y[-8] divider.y[-9] $abc$10488$new_n1278 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n756 LOOKUP.index[0] divider.y[7] divider.y[-10] divider.y[-11] $abc$10488$new_n1279 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n759 $abc$10488$new_n1282 $abc$10488$new_n1283 $abc$10488$new_n758 $abc$10488$new_n1281 $abc$10488$new_n1280 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$10488$new_n756 LOOKUP.index[0] divider.y[7] divider.y[-20] divider.y[-21] $abc$10488$new_n1281 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[1] divider.y[-23] LOOKUP.index[0] $abc$10488$new_n1282 +110 1 +.names LOOKUP.index[0] divider.y[-22] LOOKUP.index[1] $abc$10488$new_n1283 +110 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1285 $abc$10488$new_n1286 $abc$10488$new_n1284 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$10488$new_n756 LOOKUP.index[0] divider.y[7] divider.y[-16] divider.y[-17] $abc$10488$new_n1285 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n756 LOOKUP.index[0] divider.y[7] divider.y[-18] divider.y[-19] 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$abc$10488$new_n1491 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-3] divider.y[-4] $abc$10488$new_n1492 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1494 $abc$10488$new_n1499 $abc$10488$new_n1502 $abc$10488$new_n1493 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1495 $abc$10488$new_n1497 $abc$10488$new_n1494 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1496 divider.y[-9] divider.y[-10] $abc$10488$new_n1495 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-7] divider.y[-8] $abc$10488$new_n1496 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1498 divider.y[-13] divider.y[-14] $abc$10488$new_n1497 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-11] divider.y[-12] $abc$10488$new_n1498 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1500 $abc$10488$new_n1501 $abc$10488$new_n1499 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.y[-15] divider.y[-16] $abc$10488$new_n1500 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-17] divider.y[-18] $abc$10488$new_n1501 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1503 divider.y[-19] divider.y[-20] $abc$10488$new_n1502 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] divider.y[-21] divider.y[-22] $abc$10488$new_n1503 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1507 $abc$10488$new_n1509 $abc$10488$new_n1506 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1508 divider.y[-10] divider.y[-11] $abc$10488$new_n1507 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-8] divider.y[-9] $abc$10488$new_n1508 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1510 $abc$10488$new_n1511 $abc$10488$new_n1509 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.y[-12] divider.y[-13] $abc$10488$new_n1510 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-14] divider.y[-15] $abc$10488$new_n1511 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] $abc$10488$new_n1513 $abc$10488$new_n1514 $abc$10488$new_n1512 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[0] divider.y[-16] divider.y[-17] $abc$10488$new_n1513 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-18] divider.y[-19] $abc$10488$new_n1514 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[0] divider.y[-20] divider.y[-21] $abc$10488$new_n1516 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[2] $abc$10488$new_n1519 $abc$10488$new_n1521 $abc$10488$new_n1518 +010 1 +011 1 +101 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1520 divider.y[2] divider.y[1] $abc$10488$new_n1519 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[4] divider.y[3] $abc$10488$new_n1520 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] divider.y[7] divider.y[6] divider.y[5] $abc$10488$new_n1521 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] $abc$10488$new_n1523 $abc$10488$new_n1525 $abc$10488$new_n1522 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1524 divider.y[-2] divider.y[-3] $abc$10488$new_n1523 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[0] divider.y[-1] $abc$10488$new_n1524 +000 1 +010 1 +100 1 +101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1526 divider.y[-6] divider.y[-7] $abc$10488$new_n1525 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[0] divider.y[-4] divider.y[-5] $abc$10488$new_n1526 +000 1 +010 1 +100 1 +101 1 +.names divider.x[-24] LOOKUP.index[4] $abc$10488$new_n1528 $abc$10488$new_n1535 $abc$10488$new_n1527 +1000 1 +1010 1 +1100 1 +1101 1 +.names LOOKUP.index[3] $abc$10488$new_n1529 $abc$10488$new_n1532 $abc$10488$new_n1528 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1530 $abc$10488$new_n1531 $abc$10488$new_n1529 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1486 divider.y[7] divider.y[6] $abc$10488$new_n1530 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1490 divider.y[3] divider.y[2] $abc$10488$new_n1531 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1533 $abc$10488$new_n1534 $abc$10488$new_n1532 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1492 divider.y[-1] divider.y[-2] $abc$10488$new_n1533 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1496 divider.y[-5] divider.y[-6] $abc$10488$new_n1534 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1536 $abc$10488$new_n1539 $abc$10488$new_n1540 $abc$10488$new_n1535 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1537 $abc$10488$new_n1538 $abc$10488$new_n1536 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1498 divider.y[-9] divider.y[-10] $abc$10488$new_n1537 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1500 divider.y[-13] divider.y[-14] $abc$10488$new_n1538 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1501 divider.y[-19] divider.y[-20] $abc$10488$new_n1539 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1503 divider.y[-23] divider.y[-24] $abc$10488$new_n1540 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] $abc$10488$new_n1544 $abc$10488$new_n1542 $abc$10488$new_n1539 $abc$10488$new_n404 $abc$10488$new_n1541 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1543 $abc$10488$new_n1530 divider.y[7] $abc$10488$new_n1542 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1531 $abc$10488$new_n1533 $abc$10488$new_n1543 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1545 LOOKUP.index[2] $abc$10488$new_n1538 $abc$10488$new_n1544 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names LOOKUP.index[2] $abc$10488$new_n1534 $abc$10488$new_n1537 $abc$10488$new_n1545 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1548 $abc$10488$new_n1551 divider.y[7] $abc$10488$new_n1547 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1549 $abc$10488$new_n1550 $abc$10488$new_n1548 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1524 divider.y[2] divider.y[1] $abc$10488$new_n1549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1526 divider.y[-2] divider.y[-3] $abc$10488$new_n1550 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1520 divider.y[6] divider.y[5] $abc$10488$new_n1551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] $abc$10488$new_n1554 $abc$10488$new_n1555 $abc$10488$new_n1553 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1508 divider.y[-6] divider.y[-7] $abc$10488$new_n1554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1510 divider.y[-10] divider.y[-11] $abc$10488$new_n1555 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[1] $abc$10488$new_n1511 $abc$10488$new_n1513 $abc$10488$new_n1556 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1491 $abc$10488$new_n1495 $abc$10488$new_n1561 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1485 $abc$10488$new_n1489 $abc$10488$new_n1562 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[2] $abc$10488$new_n1487 divider.y[7] $abc$10488$new_n1563 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1565 $abc$10488$new_n1567 $abc$10488$new_n1564 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1566 $abc$10488$new_n1521 divider.y[7] $abc$10488$new_n1565 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names LOOKUP.index[2] $abc$10488$new_n1519 $abc$10488$new_n1523 $abc$10488$new_n1566 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1568 $abc$10488$new_n1509 $abc$10488$new_n1512 $abc$10488$new_n1567 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1525 $abc$10488$new_n1507 $abc$10488$new_n1568 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1570 $abc$10488$new_n1532 $abc$10488$new_n1536 $abc$10488$new_n1569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1529 divider.y[7] $abc$10488$new_n1570 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] $abc$10488$new_n1572 $abc$10488$new_n1574 $abc$10488$new_n1571 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] $abc$10488$new_n1573 divider.y[7] $abc$10488$new_n1572 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[2] $abc$10488$new_n1551 $abc$10488$new_n1549 $abc$10488$new_n1573 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1575 $abc$10488$new_n1555 $abc$10488$new_n1556 $abc$10488$new_n1574 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[2] $abc$10488$new_n1550 $abc$10488$new_n1554 $abc$10488$new_n1575 +001 1 +011 1 +110 1 +111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1577 $abc$10488$new_n1488 $abc$10488$new_n1494 $abc$10488$new_n1576 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1484 divider.y[7] $abc$10488$new_n1577 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1579 $abc$10488$new_n1522 $abc$10488$new_n1506 $abc$10488$new_n1578 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1518 divider.y[7] $abc$10488$new_n1579 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1581 $abc$10488$new_n1543 $abc$10488$new_n1545 $abc$10488$new_n1580 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1530 $abc$10488$new_n1581 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1583 $abc$10488$new_n1548 $abc$10488$new_n1553 $abc$10488$new_n1582 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[2] LOOKUP.index[3] divider.y[7] $abc$10488$new_n1551 $abc$10488$new_n1583 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1585 $abc$10488$new_n1562 $abc$10488$new_n1561 $abc$10488$new_n1584 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[3] $abc$10488$new_n1563 divider.y[7] $abc$10488$new_n1585 +010 1 +011 1 +100 1 +110 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1587 $abc$10488$new_n1566 $abc$10488$new_n1568 $abc$10488$new_n1586 +00000 1 +00010 1 +00100 1 +00110 1 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divider.z_[-2] divider.y_[7] $abc$10488$new_n714 $abc$10488$new_n718 $abc$10488$new_n677 $abc$10488$new_n1639 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names divider.z_[-2] $abc$10488$new_n714 $abc$10488$new_n1641 $abc$10488$new_n659 $abc$10488$auto$rtlil.cc:2693:MuxGate$9716 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names divider.y_[7] $abc$10488$new_n677 $abc$10488$new_n718 $abc$10488$new_n1641 +000 1 +010 1 +110 1 +111 1 +.names divider.z_[-3] $abc$10488$new_n711 $abc$10488$new_n1643 $abc$10488$new_n659 $abc$10488$auto$rtlil.cc:2693:MuxGate$9718 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names divider.z_[-4] $abc$10488$new_n712 divider.y_[7] $abc$10488$new_n719 $abc$10488$new_n678 $abc$10488$new_n1643 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 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EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9988 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-6] $abc$10488$new_n478 $abc$10488$new_n2179 $abc$10488$new_n2178 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n466 $abc$10488$new_n491 $abc$10488$new_n2179 +000 1 +001 1 +101 1 +111 1 +.names $abc$10488$new_n2181 z[-7] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9990 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-7] $abc$10488$new_n475 $abc$10488$new_n2182 $abc$10488$new_n2181 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[-8] $abc$10488$new_n476 z_[7] $abc$10488$new_n492 $abc$10488$new_n467 $abc$10488$new_n2182 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$10488$new_n2184 z[-8] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9992 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-8] $abc$10488$new_n476 $abc$10488$new_n2185 $abc$10488$new_n2184 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n467 $abc$10488$new_n492 $abc$10488$new_n2185 +010 1 +011 1 +101 1 +111 1 +.names $abc$10488$new_n2187 z[-9] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9994 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-9] $abc$10488$new_n473 $abc$10488$new_n2188 $abc$10488$new_n2187 +1000 1 +1011 1 +1101 1 +1110 1 +.names z_[-10] z_[7] $abc$10488$new_n474 $abc$10488$new_n493 $abc$10488$new_n468 $abc$10488$new_n2188 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$10488$new_n2190 z[-10] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9996 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-10] $abc$10488$new_n474 $abc$10488$new_n2191 $abc$10488$new_n2190 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n468 $abc$10488$new_n493 $abc$10488$new_n2191 +000 1 +001 1 +101 1 +111 1 +.names $abc$10488$new_n2193 z[-11] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9998 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$10488$new_n419 z_[-11] $abc$10488$new_n472 $abc$10488$new_n2194 $abc$10488$new_n2193 +1001 1 +1010 1 +1100 1 +1111 1 +.names z_[7] $abc$10488$new_n469 $abc$10488$new_n494 $abc$10488$new_n2194 +010 1 +011 1 +101 1 +111 1 +.names $abc$10488$new_n419 $abc$10488$new_n2196 z[-12] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$10000 +0011 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names z_[7] z_[-12] $abc$10488$new_n471 $abc$10488$new_n495 $abc$10488$new_n470 $abc$10488$new_n2196 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names IS_Z_ZERO $abc$10488$new_n420 $abc$10488$auto$rtlil.cc:2693:MuxGate$10046 +01 1 +10 1 +11 1 +.names divider.i[4] divider.i[2] $abc$10488$new_n605 $abc$10488$new_n582 $abc$10488$new_n584 $abc$10488$new_n2198 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.i[3] divider.i[4] $abc$10488$new_n2198 $abc$10488$new_n603 $abc$10488$new_n606 $abc$10488$new_n2199 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1182 $abc$10488$new_n1034 divider.y[5] z_[7] $abc$10488$new_n2200 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1213 $abc$10488$new_n1183 $abc$10488$new_n2200 $abc$10488$new_n1181 $abc$10488$new_n2201 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names divider.y[7] $abc$10488$new_n1031 $abc$10488$new_n970 $abc$10488$new_n1209 $abc$10488$new_n2202 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$10488$new_n1209 $abc$10488$new_n1212 $abc$10488$new_n2201 $abc$10488$new_n2202 $abc$10488$new_n736 $abc$10488$auto$rtlil.cc:2693:MuxGate$10034 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n815 divider.x[-22] divider.x[-23] $abc$10488$new_n2204 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n759 $abc$10488$new_n764 $abc$10488$new_n2204 $abc$10488$new_n776 $abc$10488$new_n2205 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n779 $abc$10488$new_n835 $abc$10488$new_n2205 $abc$10488$new_n840 $abc$10488$new_n2206 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[-20] divider.x[-21] $abc$10488$new_n2207 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2207 LOOKUP.index[1] divider.x[-23] divider.x[-22] $abc$10488$new_n2208 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names LOOKUP.index[3] LOOKUP.index[2] $abc$10488$new_n1050 $abc$10488$new_n2208 $abc$10488$new_n1055 $abc$10488$new_n2209 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n2209 $abc$10488$new_n1058 $abc$10488$new_n1063 $abc$10488$new_n2210 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1082 divider.x[-23] divider.x[-24] $abc$10488$new_n2211 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1089 $abc$10488$new_n2211 $abc$10488$new_n1078 $abc$10488$new_n2212 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2212 $abc$10488$new_n1084 $abc$10488$new_n1072 $abc$10488$new_n2213 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[0] LOOKUP.index[1] divider.x[-18] divider.x[-19] $abc$10488$new_n2214 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2214 LOOKUP.index[2] LOOKUP.index[1] divider.x[-20] divider.x[-21] $abc$10488$new_n2215 +00001 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n2215 LOOKUP.index[2] $abc$10488$new_n1054 $abc$10488$new_n1056 $abc$10488$new_n2216 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1095 $abc$10488$new_n2216 $abc$10488$new_n1101 $abc$10488$new_n2217 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$10488$new_n1603 $abc$10488$new_n1605 $abc$10488$new_n1607 divider.x[5] divider.x[6] $abc$10488$new_n2218 +00011 1 +01001 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n1209 $abc$10488$new_n1212 divider.x[7] $abc$10488$new_n2390 $abc$10488$new_n2222 $abc$10488$auto$rtlil.cc:2693:MuxGate$10038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names divider.x[7] z_[7] $abc$10488$new_n1379 divider.y[6] divider.x[6] $abc$10488$new_n2221 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$10488$new_n2221 z_[7] $abc$10488$new_n1220 $abc$10488$new_n1031 $abc$10488$new_n1380 $abc$10488$new_n2222 +00010 1 +00011 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1258 $abc$10488$new_n1255 $abc$10488$new_n2223 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n2223 $abc$10488$new_n764 $abc$10488$new_n758 $abc$10488$new_n1250 $abc$10488$new_n1259 $abc$10488$new_n2224 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n779 $abc$10488$new_n1301 $abc$10488$new_n2224 $abc$10488$new_n1308 $abc$10488$new_n2225 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$10488$new_n759 $abc$10488$new_n758 $abc$10488$new_n1250 $abc$10488$new_n1259 $abc$10488$new_n2226 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$10488$new_n2226 $abc$10488$new_n758 $abc$10488$new_n1249 $abc$10488$new_n1258 $abc$10488$new_n2227 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$10488$new_n779 $abc$10488$new_n764 $abc$10488$new_n1322 $abc$10488$new_n2227 $abc$10488$new_n1325 $abc$10488$new_n2228 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names LOOKUP.index[1] LOOKUP.index[0] $abc$10488$new_n1516 divider.y[-22] divider.y[-23] $abc$10488$new_n2229 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1522 $abc$10488$new_n1512 $abc$10488$new_n2229 $abc$10488$new_n2230 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2230 $abc$10488$new_n1518 $abc$10488$new_n1506 $abc$10488$new_n2231 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names LOOKUP.index[2] LOOKUP.index[1] $abc$10488$new_n1556 $abc$10488$new_n1514 $abc$10488$new_n1516 $abc$10488$new_n2232 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[4] LOOKUP.index[3] $abc$10488$new_n1547 $abc$10488$new_n1553 $abc$10488$new_n2232 $abc$10488$new_n2233 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names LOOKUP.index[4] LOOKUP.index[2] $abc$10488$new_n1563 $abc$10488$new_n1497 $abc$10488$new_n1499 $abc$10488$new_n2234 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names LOOKUP.index[3] LOOKUP.index[4] $abc$10488$new_n2234 $abc$10488$new_n1562 $abc$10488$new_n1561 $abc$10488$new_n2235 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n683 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n536 divider.i[2] $abc$10488$new_n2236 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10111 1 +11111 1 +.names divider.z_[-13] $abc$10488$new_n2236 $abc$10488$new_n659 $abc$10488$new_n724 divider.y_[7] $abc$10488$auto$rtlil.cc:2693:MuxGate$9738 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$10488$new_n687 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n693 divider.i[2] $abc$10488$new_n2238 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10110 1 +11110 1 +.names divider.z_[-17] $abc$10488$new_n2238 $abc$10488$new_n659 $abc$10488$new_n728 divider.y_[7] $abc$10488$auto$rtlil.cc:2693:MuxGate$9746 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$10488$new_n691 divider.y_[7] $abc$10488$new_n697 $abc$10488$new_n693 divider.i[2] $abc$10488$new_n2240 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10111 1 +11111 1 +.names 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+001 1 +011 1 +110 1 +111 1 +.names z_[7] $abc$10488$new_n1126 $abc$10488$new_n1212 $abc$10488$new_n1196 $abc$10488$new_n1046 $abc$10488$new_n2374 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n2374 $abc$10488$new_n861 $abc$10488$new_n817 $abc$10488$new_n2123 $abc$10488$new_n2375 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n1209 $abc$10488$new_n2374 $abc$10488$new_n1212 divider.y[-20] $abc$10488$new_n2375 $abc$10488$auto$rtlil.cc:2693:MuxGate$9954 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names z_[7] $abc$10488$new_n1107 $abc$10488$new_n1212 $abc$10488$new_n1197 $abc$10488$new_n1047 $abc$10488$new_n2377 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n2377 $abc$10488$new_n860 $abc$10488$new_n846 $abc$10488$new_n2132 $abc$10488$new_n2378 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n1209 $abc$10488$new_n2377 $abc$10488$new_n1212 divider.y[-22] $abc$10488$new_n2378 $abc$10488$auto$rtlil.cc:2693:MuxGate$9958 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.names divider.y[-24] z_[7] $abc$10488$new_n1212 $abc$10488$new_n2210 $abc$10488$new_n2213 $abc$10488$new_n2380 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10111 1 +11100 1 +11101 1 +.names $abc$10488$new_n2206 $abc$10488$new_n2138 $abc$10488$new_n1212 $abc$10488$new_n2380 divider.x[-24] $abc$10488$new_n2381 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01110 1 +01111 1 +10000 1 +10110 1 +10111 1 +11011 1 +11110 1 +11111 1 +.names divider.y[-23] $abc$10488$new_n2381 $abc$10488$new_n1209 divider.x[-23] $abc$10488$new_n1212 $abc$10488$auto$rtlil.cc:2693:MuxGate$9960 +00110 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names z_[0] $abc$10488$new_n417 z_[7] $abc$10488$new_n488 $abc$10488$new_n463 $abc$10488$new_n2383 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n419 $abc$10488$new_n405 z_[1] $abc$10488$new_n2383 $abc$10488$new_n2384 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names $abc$10488$new_n2384 z[1] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9974 +000 1 +001 1 +010 1 +011 1 +111 1 +.names z_[-6] $abc$10488$new_n478 z_[7] $abc$10488$new_n466 $abc$10488$new_n491 $abc$10488$new_n2386 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$10488$new_n419 $abc$10488$new_n477 z_[-5] $abc$10488$new_n2386 $abc$10488$new_n2387 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names $abc$10488$new_n2387 z[-5] EN $abc$10488$auto$rtlil.cc:2693:MuxGate$9986 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$10488$new_n1603 $abc$10488$new_n1605 $abc$10488$new_n1468 divider.x[5] divider.x[6] $abc$10488$new_n2389 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names $abc$10488$new_n1213 z_[7] $abc$10488$new_n2389 $abc$10488$new_n2218 $abc$10488$new_n2390 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1698 $abc$10488$new_n1603 $abc$10488$new_n1695 $abc$10488$new_n1694 $abc$10488$new_n2391 +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$10488$new_n2391 $abc$10488$new_n1209 divider.x[6] $abc$10488$new_n1212 $abc$10488$auto$rtlil.cc:2693:MuxGate$9770 +0010 1 +0011 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names z_[7] $abc$10488$new_n1597 $abc$10488$new_n1212 $abc$10488$new_n1471 $abc$10488$new_n1610 $abc$10488$new_n2393 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n2393 $abc$10488$new_n1372 $abc$10488$new_n1449 divider.y[-1] $abc$10488$new_n1021 $abc$10488$new_n2394 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$10488$new_n2394 $abc$10488$new_n2393 $abc$10488$new_n1224 $abc$10488$new_n1384 $abc$10488$new_n2395 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$10488$new_n1212 divider.x[-1] $abc$10488$new_n1209 $abc$10488$new_n2393 $abc$10488$new_n2395 $abc$10488$auto$rtlil.cc:2693:MuxGate$9784 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names z_[7] $abc$10488$new_n1023 $abc$10488$new_n973 $abc$10488$new_n1997 $abc$10488$new_n947 $abc$10488$new_n2397 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$10488$new_n1212 $abc$10488$new_n1999 $abc$10488$new_n1172 $abc$10488$new_n950 divider.x[1] $abc$10488$new_n2398 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names divider.y[1] $abc$10488$new_n2398 $abc$10488$new_n1209 $abc$10488$new_n2397 $abc$10488$new_n1212 $abc$10488$auto$rtlil.cc:2693:MuxGate$9912 +00110 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +.names z_[7] $abc$10488$new_n1146 $abc$10488$new_n1212 $abc$10488$new_n1193 $abc$10488$new_n1043 $abc$10488$new_n2400 +00100 1 +00101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$10488$new_n2400 $abc$10488$new_n900 $abc$10488$new_n747 $abc$10488$new_n2085 $abc$10488$new_n2401 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$10488$new_n1209 $abc$10488$new_n2400 $abc$10488$new_n1212 divider.y[-14] $abc$10488$new_n2401 $abc$10488$auto$rtlil.cc:2693:MuxGate$9942 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10024 Q=z_[-24] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10022 Q=z_[-23] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10020 Q=z_[-22] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10018 Q=z_[-21] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10016 Q=z_[-20] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10014 Q=z_[-19] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10012 Q=z_[-18] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10010 Q=z_[-17] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10008 Q=z_[-16] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10006 Q=z_[-15] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10004 Q=z_[-14] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10002 Q=z_[-13] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10000 Q=z_[-12] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9998 Q=z_[-11] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9996 Q=z_[-10] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9994 Q=z_[-9] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9992 Q=z_[-8] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9990 Q=z_[-7] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9988 Q=z_[-6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9986 Q=z_[-5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9984 Q=z_[-4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9982 Q=z_[-3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9980 Q=z_[-2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9978 Q=z_[-1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9976 Q=z_[0] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9974 Q=z_[1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9972 Q=z_[2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9970 Q=z_[3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9968 Q=z_[4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9966 Q=z_[5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9964 Q=z_[6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10026 Q=z_[7] +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9962 Q=divider.y[-24] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9960 Q=divider.y[-23] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9958 Q=divider.y[-22] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9956 Q=divider.y[-21] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9954 Q=divider.y[-20] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9952 Q=divider.y[-19] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9950 Q=divider.y[-18] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9948 Q=divider.y[-17] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9946 Q=divider.y[-16] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9944 Q=divider.y[-15] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9942 Q=divider.y[-14] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9940 Q=divider.y[-13] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9938 Q=divider.y[-12] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9936 Q=divider.y[-11] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9934 Q=divider.y[-10] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9932 Q=divider.y[-9] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9930 Q=divider.y[-8] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9928 Q=divider.y[-7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9926 Q=divider.y[-6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9924 Q=divider.y[-5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9922 Q=divider.y[-4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9920 Q=divider.y[-3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9918 Q=divider.y[-2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9916 Q=divider.y[-1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9914 Q=divider.y[0] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9912 Q=divider.y[1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9910 Q=divider.y[2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9908 Q=divider.y[3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9906 Q=divider.y[4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9904 Q=divider.y[5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9902 Q=divider.y[6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10034 Q=divider.y[7] R=EN +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9900 Q=divider.y_[-24] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9898 Q=divider.y_[-23] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9896 Q=divider.y_[-22] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9894 Q=divider.y_[-21] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9892 Q=divider.y_[-20] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9890 Q=divider.y_[-19] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9888 Q=divider.y_[-18] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9886 Q=divider.y_[-17] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9884 Q=divider.y_[-16] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9882 Q=divider.y_[-15] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9880 Q=divider.y_[-14] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9878 Q=divider.y_[-13] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9876 Q=divider.y_[-12] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9874 Q=divider.y_[-11] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9872 Q=divider.y_[-10] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9870 Q=divider.y_[-9] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9868 Q=divider.y_[-8] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9866 Q=divider.y_[-7] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9864 Q=divider.y_[-6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9862 Q=divider.y_[-5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9860 Q=divider.y_[-4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9858 Q=divider.y_[-3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9856 Q=divider.y_[-2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9854 Q=divider.y_[-1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9852 Q=divider.y_[0] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9850 Q=divider.y_[1] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9848 Q=divider.y_[2] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9846 Q=divider.y_[3] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9844 Q=divider.y_[4] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9842 Q=divider.y_[5] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9840 Q=divider.y_[6] +.subckt dff C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10028 Q=divider.y_[7] +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9838 Q=LOOKUP.index[0] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9836 Q=LOOKUP.index[1] R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9834 Q=LOOKUP.index[2] S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9832 Q=LOOKUP.index[3] S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10036 Q=LOOKUP.index[4] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9830 Q=divider.x[-24] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9828 Q=divider.x[-23] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9826 Q=divider.x[-22] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9824 Q=divider.x[-21] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9822 Q=divider.x[-20] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9820 Q=divider.x[-19] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9818 Q=divider.x[-18] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9816 Q=divider.x[-17] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9814 Q=divider.x[-16] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9812 Q=divider.x[-15] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9810 Q=divider.x[-14] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9808 Q=divider.x[-13] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9806 Q=divider.x[-12] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9804 Q=divider.x[-11] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9802 Q=divider.x[-10] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9800 Q=divider.x[-9] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9798 Q=divider.x[-8] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9796 Q=divider.x[-7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9794 Q=divider.x[-6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9792 Q=divider.x[-5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9790 Q=divider.x[-4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9788 Q=divider.x[-3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9786 Q=divider.x[-2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9784 Q=divider.x[-1] R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9782 Q=divider.x[0] S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9780 Q=divider.x[1] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9778 Q=divider.x[2] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9776 Q=divider.x[3] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9774 Q=divider.x[4] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9772 Q=divider.x[5] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9770 Q=divider.x[6] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10038 Q=divider.x[7] R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10040 Q=div_en R=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10042 Q=IS_FIRST4 S=EN +.subckt sdffs C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10044 Q=IS_FIRST13 S=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10046 Q=IS_Z_ZERO R=EN +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9768 Q=divider.i[0] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9766 Q=divider.i[1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9764 Q=divider.i[2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9762 Q=divider.i[3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10032 Q=divider.i[4] R=div_en +.subckt sdffr C=CLK D=divider.z_[-24] Q=out[-24] R=div_en +.subckt sdffr C=CLK D=divider.z_[-23] Q=out[-23] R=div_en +.subckt sdffr C=CLK D=divider.z_[-22] Q=out[-22] R=div_en +.subckt sdffr C=CLK D=divider.z_[-21] Q=out[-21] R=div_en +.subckt sdffr C=CLK D=divider.z_[-20] Q=out[-20] R=div_en +.subckt sdffr C=CLK D=divider.z_[-19] Q=out[-19] R=div_en +.subckt sdffr C=CLK D=divider.z_[-18] Q=out[-18] R=div_en +.subckt sdffr C=CLK D=divider.z_[-17] Q=out[-17] R=div_en +.subckt sdffr C=CLK D=divider.z_[-16] Q=out[-16] R=div_en +.subckt sdffr C=CLK D=divider.z_[-15] Q=out[-15] R=div_en +.subckt sdffr C=CLK D=divider.z_[-14] Q=out[-14] R=div_en +.subckt sdffr C=CLK D=divider.z_[-13] Q=out[-13] R=div_en +.subckt sdffr C=CLK D=divider.z_[-12] Q=out[-12] R=div_en +.subckt sdffr C=CLK D=divider.z_[-11] Q=out[-11] R=div_en +.subckt sdffr C=CLK D=divider.z_[-10] Q=out[-10] R=div_en +.subckt sdffr C=CLK D=divider.z_[-9] Q=out[-9] R=div_en +.subckt sdffr C=CLK D=divider.z_[-8] Q=out[-8] R=div_en +.subckt sdffr C=CLK D=divider.z_[-7] Q=out[-7] R=div_en +.subckt sdffr C=CLK D=divider.z_[-6] Q=out[-6] R=div_en +.subckt sdffr C=CLK D=divider.z_[-5] Q=out[-5] R=div_en +.subckt sdffr C=CLK D=divider.z_[-4] Q=out[-4] R=div_en +.subckt sdffr C=CLK D=divider.z_[-3] Q=out[-3] R=div_en +.subckt sdffr C=CLK D=divider.z_[-2] Q=out[-2] R=div_en +.subckt sdffr C=CLK D=divider.z_[-1] Q=out[-1] R=div_en +.subckt sdffr C=CLK D=divider.z_[0] Q=out[0] R=div_en +.subckt sdffr C=CLK D=divider.z_[1] Q=out[1] R=div_en +.subckt sdffr C=CLK D=divider.z_[2] Q=out[2] R=div_en +.subckt sdffr C=CLK D=divider.z_[3] Q=out[3] R=div_en +.subckt sdffr C=CLK D=divider.z_[4] Q=out[4] R=div_en +.subckt sdffr C=CLK D=divider.z_[5] Q=out[5] R=div_en +.subckt sdffr C=CLK D=divider.z_[6] Q=out[6] R=div_en +.subckt sdffr C=CLK D=divider.z_[7] Q=out[7] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9760 Q=divider.z_[-24] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9758 Q=divider.z_[-23] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9756 Q=divider.z_[-22] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9754 Q=divider.z_[-21] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9752 Q=divider.z_[-20] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9750 Q=divider.z_[-19] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9748 Q=divider.z_[-18] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9746 Q=divider.z_[-17] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9744 Q=divider.z_[-16] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9742 Q=divider.z_[-15] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9740 Q=divider.z_[-14] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9738 Q=divider.z_[-13] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9736 Q=divider.z_[-12] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9734 Q=divider.z_[-11] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9732 Q=divider.z_[-10] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9730 Q=divider.z_[-9] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9728 Q=divider.z_[-8] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9726 Q=divider.z_[-7] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9724 Q=divider.z_[-6] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9722 Q=divider.z_[-5] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9720 Q=divider.z_[-4] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9718 Q=divider.z_[-3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9716 Q=divider.z_[-2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9714 Q=divider.z_[-1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9712 Q=divider.z_[0] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9710 Q=divider.z_[1] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9708 Q=divider.z_[2] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9706 Q=divider.z_[3] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9704 Q=divider.z_[4] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9702 Q=divider.z_[5] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$9700 Q=divider.z_[6] R=div_en +.subckt sdffr C=CLK D=$abc$10488$auto$rtlil.cc:2693:MuxGate$10030 Q=divider.z_[7] R=div_en +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif new file mode 100644 index 00000000000..dc494993029 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/music.blif @@ -0,0 +1,1170 @@ +# Generated by Yosys 0.38+46 (git sha1 074b50e9c, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model music +.inputs clk +.outputs speaker +.names $false +.names $true +1 +.names $undef +.names get_fullnote.address[7] $abc$2165$new_n111 $abc$2165$new_n116 get_fullnote.address[5] $abc$2165$new_n118 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n112 $abc$2165$new_n116 get_fullnote.address[6] get_fullnote.address[5] $abc$2165$new_n117 $abc$2165$new_n111 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[7] $abc$2165$new_n113 get_fullnote.address[6] $abc$2165$new_n115 get_fullnote.address[5] $abc$2165$new_n112 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[3] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[4] $abc$2165$new_n114 $abc$2165$new_n113 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names get_fullnote.address[0] get_fullnote.address[1] $abc$2165$new_n114 +11 1 +.names get_fullnote.address[2] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n115 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n116 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n117 +00001 1 +00011 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n118 +01000 1 +01001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[4] $abc$2165$new_n130 $abc$2165$new_n230 get_fullnote.address[7] get_fullnote.address[6] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$2165$new_n124 get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[0] $abc$2165$new_n123 +1001 1 +1011 1 +1110 1 +1111 1 +.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n124 +10 1 +.names get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n125 +11 1 +.names $abc$2165$new_n125 get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] $abc$2165$new_n126 +1100 1 +.names get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] get_fullnote.address[2] get_fullnote.address[1] $abc$2165$new_n127 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[0] $abc$2165$new_n129 +000 1 +010 1 +011 1 +.names get_fullnote.address[5] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[3] $abc$2165$new_n130 +00000 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n232 $abc$2165$new_n136 $abc$2165$new_n138 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names get_fullnote.address[4] get_fullnote.address[3] get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n134 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +.names get_fullnote.address[5] $abc$2165$new_n144 $abc$2165$new_n115 $abc$2165$new_n136 +000 1 +001 1 +011 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[5] $abc$2165$new_n138 +00001 1 +00011 1 +00101 1 +00111 1 +01101 1 +10001 1 +10011 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$2165$new_n143 get_fullnote.address[5] $abc$2165$new_n146 $abc$2165$new_n140 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n124 $abc$2165$new_n142 $abc$2165$new_n140 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n124 get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] $abc$2165$new_n141 +1000 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n142 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names get_fullnote.address[7] get_fullnote.address[6] $abc$2165$new_n145 $abc$2165$new_n144 $abc$2165$new_n143 +0000 1 +0001 1 +0100 1 +0101 1 +1001 1 +1011 1 +1100 1 +1101 1 +.names get_fullnote.address[4] get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[5] get_fullnote.address[3] $abc$2165$new_n144 +00000 1 +00001 1 +00011 1 +00100 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11110 1 +.names get_fullnote.address[2] get_fullnote.address[1] get_fullnote.address[3] get_fullnote.address[4] get_fullnote.address[5] $abc$2165$new_n145 +10000 1 +.names get_fullnote.address[4] get_fullnote.address[1] get_fullnote.address[0] get_fullnote.address[2] get_fullnote.address[3] $abc$2165$new_n146 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names get_fullnote.address[6] $abc$2165$new_n125 get_fullnote.address[7] $abc$2165$new_n141 $abc$2165$new_n142 $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names get_fullnote.address[6] $abc$2165$new_n142 $abc$2165$new_n125 get_fullnote.address[7] $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] +1110 1 +.names counter_note[0] $abc$2165$new_n153 $abc$2165$new_n155 $abc$2165$new_n150 fullnote[1] $0\counter_note[8:0][0] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +.names $abc$2165$new_n151 counter_note[8] counter_note[7] counter_note[6] counter_note[5] $abc$2165$new_n150 +10000 1 +.names $abc$2165$new_n152 counter_note[4] $abc$2165$new_n151 +10 1 +.names counter_note[0] counter_note[3] counter_note[2] counter_note[1] $abc$2165$new_n152 +0000 1 +.names fullnote[0] $abc$2165$new_n154 $abc$2165$new_n153 +10 1 +.names fullnote[4] fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n154 +0001 1 +0110 1 +1000 1 +1011 1 +1101 1 +.names fullnote[5] fullnote[3] fullnote[4] fullnote[2] $abc$2165$new_n155 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names counter_note[0] counter_note[1] $abc$2165$new_n157 $abc$2165$new_n150 $0\counter_note[8:0][1] +0000 1 +0001 1 +0010 1 +1100 1 +1101 1 +1110 1 +.names $abc$2165$new_n154 fullnote[0] fullnote[1] $abc$2165$new_n157 +100 1 +101 1 +111 1 +.names counter_note[2] $abc$2165$new_n159 counter_note[0] counter_note[1] $0\counter_note[8:0][2] +0000 1 +1001 1 +1010 1 +1011 1 +.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n154 $abc$2165$new_n159 +10000 1 +10001 1 +11011 1 +11100 1 +.names counter_note[3] $abc$2165$new_n161 counter_note[0] counter_note[2] counter_note[1] $0\counter_note[8:0][3] +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n155 $abc$2165$new_n154 $abc$2165$new_n161 +10000 1 +10001 1 +10011 1 +10110 1 +11010 1 +11111 1 +.names counter_note[4] $abc$2165$new_n152 $abc$2165$new_n163 $0\counter_note[8:0][4] +010 1 +100 1 +.names $abc$2165$new_n150 $abc$2165$new_n155 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n163 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names counter_note[5] $abc$2165$new_n151 $abc$2165$new_n165 $0\counter_note[8:0][5] +010 1 +100 1 +.names $abc$2165$new_n150 fullnote[1] $abc$2165$new_n154 fullnote[0] $abc$2165$new_n155 $abc$2165$new_n165 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names counter_note[6] $abc$2165$new_n167 $abc$2165$new_n151 counter_note[5] $0\counter_note[8:0][6] +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$2165$new_n150 fullnote[1] fullnote[0] $abc$2165$new_n154 $abc$2165$new_n155 $abc$2165$new_n167 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names counter_note[7] $abc$2165$new_n151 counter_note[6] counter_note[5] $abc$2165$new_n169 $0\counter_note[8:0][7] +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names counter_note[8] $abc$2165$new_n154 $abc$2165$new_n155 fullnote[0] fullnote[1] $abc$2165$new_n169 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names counter_note[8] $abc$2165$new_n151 counter_note[7] counter_note[6] counter_note[5] $0\counter_note[8:0][8] +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names speaker $abc$2165$new_n175 $abc$2165$new_n172 $abc$2165$new_n150 $0\speaker[0:0] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$2165$new_n173 tone[19] tone[18] tone[21] tone[20] $abc$2165$new_n172 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$2165$new_n174 fullnote[3] fullnote[2] fullnote[1] fullnote[0] $abc$2165$new_n173 +10000 1 +.names fullnote[5] fullnote[4] $abc$2165$new_n174 +00 1 +.names $abc$2165$new_n176 counter_octave[7] counter_octave[6] counter_octave[5] $abc$2165$new_n175 +1000 1 +.names $abc$2165$new_n177 counter_octave[4] $abc$2165$new_n176 +10 1 +.names counter_octave[0] counter_octave[3] counter_octave[1] counter_octave[2] $abc$2165$new_n177 +0000 1 +.names counter_octave[0] $abc$2165$new_n150 $0\counter_octave[7:0][0] +01 1 +10 1 +.names counter_octave[1] $abc$2165$new_n150 counter_octave[0] $0\counter_octave[7:0][1] +010 1 +100 1 +101 1 +111 1 +.names counter_octave[2] $abc$2165$new_n150 counter_octave[0] counter_octave[1] $0\counter_octave[7:0][2] +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$2165$new_n150 counter_octave[3] $abc$2165$new_n184 $abc$2165$new_n183 $abc$2165$new_n182 $0\counter_octave[7:0][3] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$2165$new_n175 fullnote[4] fullnote[5] $abc$2165$new_n182 +100 1 +101 1 +110 1 +.names counter_octave[3] $abc$2165$new_n175 counter_octave[0] counter_octave[1] counter_octave[2] $abc$2165$new_n183 +00000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$2165$new_n175 fullnote[2] fullnote[3] $abc$2165$new_n184 +100 1 +101 1 +110 1 +.names $abc$2165$new_n150 counter_octave[4] $abc$2165$new_n177 $abc$2165$new_n175 $abc$2165$new_n182 $0\counter_octave[7:0][4] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n176 $abc$2165$new_n187 $abc$2165$new_n175 $0\counter_octave[7:0][5] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$2165$new_n182 fullnote[5] fullnote[3] fullnote[2] $abc$2165$new_n187 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names counter_octave[6] $abc$2165$new_n176 $abc$2165$new_n150 counter_octave[5] $abc$2165$new_n189 $0\counter_octave[7:0][6] +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names counter_octave[7] fullnote[5] fullnote[4] fullnote[3] $abc$2165$new_n189 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$2165$new_n191 $abc$2165$new_n150 $abc$2165$new_n184 $abc$2165$new_n174 $0\counter_octave[7:0][7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names counter_octave[7] $abc$2165$new_n150 $abc$2165$new_n176 counter_octave[6] counter_octave[5] $abc$2165$new_n191 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] +01 1 +10 1 +.names tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] +011 1 +100 1 +101 1 +110 1 +.names tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[4] tone[3] tone[2] tone[1] tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] +01 1 +10 1 +.names tone[4] tone[3] tone[2] tone[1] tone[0] $abc$2165$new_n197 +11111 1 +.names tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] +011 1 +100 1 +101 1 +110 1 +.names tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] +01 1 +10 1 +.names tone[8] tone[7] tone[6] tone[5] $abc$2165$new_n197 $abc$2165$new_n202 +11111 1 +.names tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] +011 1 +100 1 +101 1 +110 1 +.names tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] +01 1 +10 1 +.names tone[12] tone[11] tone[10] tone[9] $abc$2165$new_n202 $abc$2165$new_n207 +11111 1 +.names tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] +011 1 +100 1 +101 1 +110 1 +.names tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] +01 1 +10 1 +.names tone[16] tone[15] tone[14] tone[13] $abc$2165$new_n207 $abc$2165$new_n212 +11111 1 +.names tone[18] tone[17] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] +011 1 +100 1 +101 1 +110 1 +.names tone[19] tone[17] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names tone[20] tone[17] tone[19] tone[18] $abc$2165$new_n212 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] +01 1 +10 1 +.names tone[17] tone[20] tone[19] tone[18] $abc$2165$new_n212 $abc$2165$new_n217 +11111 1 +.names get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] +011 1 +100 1 +101 1 +110 1 +.names get_fullnote.address[1] get_fullnote.address[0] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[2] get_fullnote.address[0] get_fullnote.address[1] tone[21] $abc$2165$new_n217 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] +01 1 +10 1 +.names get_fullnote.address[0] get_fullnote.address[1] get_fullnote.address[2] tone[21] $abc$2165$new_n217 $abc$2165$new_n222 +11111 1 +.names get_fullnote.address[4] get_fullnote.address[3] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] +011 1 +100 1 +101 1 +110 1 +.names get_fullnote.address[5] get_fullnote.address[3] get_fullnote.address[4] $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[6] get_fullnote.address[3] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names get_fullnote.address[7] get_fullnote.address[3] get_fullnote.address[6] $abc$2165$new_n125 $abc$2165$new_n222 $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names tone[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] +0 1 +.names get_fullnote.address[6] get_fullnote.address[7] $abc$2165$new_n127 $abc$2165$new_n126 $abc$2165$new_n228 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$2165$new_n228 get_fullnote.address[7] $abc$2165$new_n125 get_fullnote.address[3] $abc$2165$new_n129 $abc$2165$new_n229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +10100 1 +10110 1 +.names $abc$2165$new_n228 get_fullnote.address[5] $abc$2165$new_n123 $abc$2165$new_n229 $abc$2165$new_n230 +0001 1 +0101 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names get_fullnote.address[3] get_fullnote.address[2] get_fullnote.address[5] get_fullnote.address[4] get_fullnote.address[1] $abc$2165$new_n231 +01000 1 +01001 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names get_fullnote.address[5] get_fullnote.address[7] $abc$2165$new_n134 $abc$2165$new_n231 get_fullnote.address[6] $abc$2165$new_n232 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[0] fullnote[0] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[1] fullnote[1] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[2] fullnote[2] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[3] fullnote[3] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[4] fullnote[4] re clk 2 +.latch $$flatten\get_fullnote.$auto$proc_rom.cc:150:do_switch$26$rdreg[0]$d[5] fullnote[5] re clk 2 +.latch $0\speaker[0:0] speaker re clk 2 +.latch $0\counter_octave[7:0][0] counter_octave[0] re clk 2 +.latch $0\counter_octave[7:0][1] counter_octave[1] re clk 2 +.latch $0\counter_octave[7:0][2] counter_octave[2] re clk 2 +.latch $0\counter_octave[7:0][3] counter_octave[3] re clk 2 +.latch $0\counter_octave[7:0][4] counter_octave[4] re clk 2 +.latch $0\counter_octave[7:0][5] counter_octave[5] re clk 2 +.latch $0\counter_octave[7:0][6] counter_octave[6] re clk 2 +.latch $0\counter_octave[7:0][7] counter_octave[7] re clk 2 +.latch $0\counter_note[8:0][0] counter_note[0] re clk 2 +.latch $0\counter_note[8:0][1] counter_note[1] re clk 2 +.latch $0\counter_note[8:0][2] counter_note[2] re clk 2 +.latch $0\counter_note[8:0][3] counter_note[3] re clk 2 +.latch $0\counter_note[8:0][4] counter_note[4] re clk 2 +.latch $0\counter_note[8:0][5] counter_note[5] re clk 2 +.latch $0\counter_note[8:0][6] counter_note[6] re clk 2 +.latch $0\counter_note[8:0][7] counter_note[7] re clk 2 +.latch $0\counter_note[8:0][8] counter_note[8] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] tone[0] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[1] tone[1] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[2] tone[2] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[3] tone[3] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[4] tone[4] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[5] tone[5] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[6] tone[6] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[7] tone[7] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[8] tone[8] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[9] tone[9] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[10] tone[10] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[11] tone[11] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[12] tone[12] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[13] tone[13] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[14] tone[14] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[15] tone[15] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[16] tone[16] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[17] tone[17] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[18] tone[18] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[19] tone[19] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[20] tone[20] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[21] tone[21] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[22] get_fullnote.address[0] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[23] get_fullnote.address[1] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[24] get_fullnote.address[2] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[25] get_fullnote.address[3] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[26] get_fullnote.address[4] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[27] get_fullnote.address[5] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[28] get_fullnote.address[6] re clk 2 +.latch $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[29] get_fullnote.address[7] re clk 2 +.names $false fullnote[6] +1 1 +.names $false fullnote[7] +1 1 +.names tone[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[1] +1 1 +.names tone[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[2] +1 1 +.names tone[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[3] +1 1 +.names tone[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[4] +1 1 +.names tone[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[5] +1 1 +.names tone[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[6] +1 1 +.names tone[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[7] +1 1 +.names tone[8] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[8] +1 1 +.names tone[9] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[9] +1 1 +.names tone[10] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[10] +1 1 +.names tone[11] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[11] +1 1 +.names tone[12] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[12] +1 1 +.names tone[13] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[13] +1 1 +.names tone[14] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[14] +1 1 +.names tone[15] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[15] +1 1 +.names tone[16] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[16] +1 1 +.names tone[17] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[17] +1 1 +.names tone[18] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[18] +1 1 +.names tone[19] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[19] +1 1 +.names tone[20] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[20] +1 1 +.names tone[21] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[21] +1 1 +.names get_fullnote.address[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[22] +1 1 +.names get_fullnote.address[1] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[23] +1 1 +.names get_fullnote.address[2] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[24] +1 1 +.names get_fullnote.address[3] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[25] +1 1 +.names get_fullnote.address[4] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[26] +1 1 +.names get_fullnote.address[5] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[27] +1 1 +.names get_fullnote.address[6] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[28] +1 1 +.names get_fullnote.address[7] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[29] +1 1 +.names tone[30] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[30] +1 1 +.names $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.X[0] $techmap$add$./benchmark/music.v:15$2.$auto$alumacc.cc:485:replace_alu$997.Y[0] +1 1 +.names get_fullnote.address[0] tone[22] +1 1 +.names get_fullnote.address[1] tone[23] +1 1 +.names get_fullnote.address[2] tone[24] +1 1 +.names get_fullnote.address[3] tone[25] +1 1 +.names get_fullnote.address[4] tone[26] +1 1 +.names get_fullnote.address[5] tone[27] +1 1 +.names get_fullnote.address[6] tone[28] +1 1 +.names get_fullnote.address[7] tone[29] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif new file mode 100644 index 00000000000..56a80c9fc49 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/picorv32.blif @@ -0,0 +1,15942 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model picorv32 +.inputs clk resetn mem_ready mem_rdata[0] mem_rdata[1] mem_rdata[2] mem_rdata[3] mem_rdata[4] mem_rdata[5] mem_rdata[6] mem_rdata[7] mem_rdata[8] mem_rdata[9] mem_rdata[10] mem_rdata[11] mem_rdata[12] mem_rdata[13] mem_rdata[14] mem_rdata[15] mem_rdata[16] mem_rdata[17] mem_rdata[18] mem_rdata[19] mem_rdata[20] mem_rdata[21] mem_rdata[22] mem_rdata[23] mem_rdata[24] mem_rdata[25] mem_rdata[26] mem_rdata[27] mem_rdata[28] mem_rdata[29] mem_rdata[30] mem_rdata[31] pcpi_wr pcpi_rd[0] pcpi_rd[1] pcpi_rd[2] pcpi_rd[3] pcpi_rd[4] pcpi_rd[5] pcpi_rd[6] pcpi_rd[7] pcpi_rd[8] pcpi_rd[9] pcpi_rd[10] pcpi_rd[11] pcpi_rd[12] pcpi_rd[13] pcpi_rd[14] pcpi_rd[15] pcpi_rd[16] pcpi_rd[17] pcpi_rd[18] pcpi_rd[19] pcpi_rd[20] pcpi_rd[21] pcpi_rd[22] pcpi_rd[23] pcpi_rd[24] pcpi_rd[25] pcpi_rd[26] pcpi_rd[27] pcpi_rd[28] pcpi_rd[29] pcpi_rd[30] pcpi_rd[31] pcpi_wait pcpi_ready irq[0] irq[1] irq[2] irq[3] irq[4] irq[5] irq[6] irq[7] irq[8] irq[9] irq[10] irq[11] irq[12] irq[13] irq[14] irq[15] irq[16] irq[17] irq[18] irq[19] irq[20] irq[21] irq[22] irq[23] irq[24] irq[25] irq[26] irq[27] irq[28] irq[29] irq[30] irq[31] +.outputs trap mem_valid mem_instr mem_addr[0] mem_addr[1] mem_addr[2] mem_addr[3] mem_addr[4] mem_addr[5] mem_addr[6] mem_addr[7] mem_addr[8] mem_addr[9] mem_addr[10] mem_addr[11] mem_addr[12] mem_addr[13] mem_addr[14] mem_addr[15] mem_addr[16] mem_addr[17] mem_addr[18] mem_addr[19] mem_addr[20] mem_addr[21] mem_addr[22] mem_addr[23] mem_addr[24] mem_addr[25] mem_addr[26] mem_addr[27] mem_addr[28] mem_addr[29] mem_addr[30] mem_addr[31] mem_wdata[0] mem_wdata[1] mem_wdata[2] mem_wdata[3] mem_wdata[4] mem_wdata[5] mem_wdata[6] mem_wdata[7] mem_wdata[8] mem_wdata[9] mem_wdata[10] mem_wdata[11] mem_wdata[12] mem_wdata[13] mem_wdata[14] mem_wdata[15] mem_wdata[16] mem_wdata[17] mem_wdata[18] mem_wdata[19] mem_wdata[20] mem_wdata[21] mem_wdata[22] mem_wdata[23] mem_wdata[24] mem_wdata[25] mem_wdata[26] mem_wdata[27] mem_wdata[28] mem_wdata[29] mem_wdata[30] mem_wdata[31] mem_wstrb[0] mem_wstrb[1] mem_wstrb[2] mem_wstrb[3] mem_la_read mem_la_write mem_la_addr[0] mem_la_addr[1] mem_la_addr[2] mem_la_addr[3] mem_la_addr[4] mem_la_addr[5] mem_la_addr[6] mem_la_addr[7] mem_la_addr[8] mem_la_addr[9] mem_la_addr[10] mem_la_addr[11] mem_la_addr[12] mem_la_addr[13] mem_la_addr[14] mem_la_addr[15] mem_la_addr[16] mem_la_addr[17] mem_la_addr[18] mem_la_addr[19] mem_la_addr[20] mem_la_addr[21] mem_la_addr[22] mem_la_addr[23] mem_la_addr[24] mem_la_addr[25] mem_la_addr[26] mem_la_addr[27] mem_la_addr[28] mem_la_addr[29] mem_la_addr[30] mem_la_addr[31] mem_la_wdata[0] mem_la_wdata[1] mem_la_wdata[2] mem_la_wdata[3] mem_la_wdata[4] mem_la_wdata[5] mem_la_wdata[6] mem_la_wdata[7] mem_la_wdata[8] mem_la_wdata[9] mem_la_wdata[10] mem_la_wdata[11] mem_la_wdata[12] mem_la_wdata[13] mem_la_wdata[14] mem_la_wdata[15] mem_la_wdata[16] mem_la_wdata[17] mem_la_wdata[18] mem_la_wdata[19] mem_la_wdata[20] mem_la_wdata[21] mem_la_wdata[22] mem_la_wdata[23] mem_la_wdata[24] mem_la_wdata[25] mem_la_wdata[26] mem_la_wdata[27] mem_la_wdata[28] mem_la_wdata[29] mem_la_wdata[30] mem_la_wdata[31] mem_la_wstrb[0] mem_la_wstrb[1] mem_la_wstrb[2] mem_la_wstrb[3] pcpi_valid pcpi_insn[0] pcpi_insn[1] pcpi_insn[2] pcpi_insn[3] pcpi_insn[4] pcpi_insn[5] pcpi_insn[6] pcpi_insn[7] pcpi_insn[8] pcpi_insn[9] pcpi_insn[10] pcpi_insn[11] pcpi_insn[12] pcpi_insn[13] pcpi_insn[14] pcpi_insn[15] pcpi_insn[16] pcpi_insn[17] pcpi_insn[18] pcpi_insn[19] pcpi_insn[20] pcpi_insn[21] pcpi_insn[22] pcpi_insn[23] pcpi_insn[24] pcpi_insn[25] pcpi_insn[26] pcpi_insn[27] pcpi_insn[28] pcpi_insn[29] pcpi_insn[30] pcpi_insn[31] pcpi_rs1[0] pcpi_rs1[1] pcpi_rs1[2] pcpi_rs1[3] pcpi_rs1[4] pcpi_rs1[5] pcpi_rs1[6] pcpi_rs1[7] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs1[18] pcpi_rs1[19] pcpi_rs1[20] pcpi_rs1[21] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs1[30] pcpi_rs1[31] pcpi_rs2[0] pcpi_rs2[1] pcpi_rs2[2] pcpi_rs2[3] pcpi_rs2[4] pcpi_rs2[5] pcpi_rs2[6] pcpi_rs2[7] pcpi_rs2[8] pcpi_rs2[9] pcpi_rs2[10] pcpi_rs2[11] pcpi_rs2[12] pcpi_rs2[13] pcpi_rs2[14] pcpi_rs2[15] pcpi_rs2[16] pcpi_rs2[17] pcpi_rs2[18] pcpi_rs2[19] pcpi_rs2[20] pcpi_rs2[21] pcpi_rs2[22] pcpi_rs2[23] pcpi_rs2[24] pcpi_rs2[25] pcpi_rs2[26] pcpi_rs2[27] pcpi_rs2[28] pcpi_rs2[29] pcpi_rs2[30] pcpi_rs2[31] eoi[0] eoi[1] eoi[2] eoi[3] eoi[4] eoi[5] eoi[6] eoi[7] eoi[8] eoi[9] eoi[10] eoi[11] eoi[12] eoi[13] eoi[14] eoi[15] eoi[16] eoi[17] eoi[18] eoi[19] eoi[20] eoi[21] eoi[22] eoi[23] eoi[24] eoi[25] eoi[26] eoi[27] eoi[28] eoi[29] eoi[30] eoi[31] trace_valid trace_data[0] trace_data[1] trace_data[2] trace_data[3] trace_data[4] trace_data[5] trace_data[6] trace_data[7] trace_data[8] trace_data[9] trace_data[10] trace_data[11] trace_data[12] trace_data[13] trace_data[14] trace_data[15] trace_data[16] trace_data[17] trace_data[18] trace_data[19] trace_data[20] trace_data[21] trace_data[22] trace_data[23] trace_data[24] trace_data[25] trace_data[26] trace_data[27] trace_data[28] trace_data[29] trace_data[30] trace_data[31] trace_data[32] trace_data[33] trace_data[34] trace_data[35] +.names $false +.names $true +1 +.names $undef +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[30] mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[30] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[30] mem_wdata[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14337 +001 1 +011 1 +110 1 +111 1 +.names mem_la_write trap $abc$16053$new_n1410 +10 1 +.names resetn mem_do_wdata mem_state[1] mem_state[0] mem_la_write +1100 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[29] mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[29] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[29] mem_wdata[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14339 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[28] mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[28] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[28] mem_wdata[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14341 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[27] mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[27] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[27] mem_wdata[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14343 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[26] mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[26] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[26] mem_wdata[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14345 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[25] mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[25] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[25] mem_wdata[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14347 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[24] mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[24] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[24] mem_wdata[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14349 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[23] mem_la_wdata[7] mem_la_wdata[23] +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] $abc$16053$new_n1425 +00 1 +11 1 +.names $abc$16053$new_n1410 mem_la_wdata[23] mem_wdata[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14351 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[22] mem_la_wdata[6] mem_la_wdata[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[22] mem_wdata[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14353 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[21] mem_la_wdata[5] mem_la_wdata[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[21] mem_wdata[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14355 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[20] mem_la_wdata[4] mem_la_wdata[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[20] mem_wdata[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14357 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[19] mem_la_wdata[3] mem_la_wdata[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[19] mem_wdata[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14359 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[18] mem_la_wdata[2] mem_la_wdata[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[18] mem_wdata[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14361 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[17] mem_la_wdata[1] mem_la_wdata[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[17] mem_wdata[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14363 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1425 pcpi_rs2[16] mem_la_wdata[0] mem_la_wdata[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[16] mem_wdata[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14365 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[15] +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[1] mem_wordsize[0] $abc$16053$new_n1442 +10 1 +.names $abc$16053$new_n1410 mem_la_wdata[15] mem_wdata[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14367 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[6] pcpi_rs2[14] mem_la_wdata[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[14] mem_wdata[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14369 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[5] pcpi_rs2[13] mem_la_wdata[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[13] mem_wdata[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14371 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[4] pcpi_rs2[12] mem_la_wdata[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[12] mem_wdata[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14373 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[3] pcpi_rs2[11] mem_la_wdata[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[11] mem_wdata[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14375 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[2] pcpi_rs2[10] mem_la_wdata[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[10] mem_wdata[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14377 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[1] pcpi_rs2[9] mem_la_wdata[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[9] mem_wdata[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14379 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1442 mem_la_wdata[0] pcpi_rs2[8] mem_la_wdata[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[8] mem_wdata[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14381 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[7] mem_wdata[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14383 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[6] mem_wdata[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14385 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[5] mem_wdata[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14387 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[4] mem_wdata[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14389 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[3] mem_wdata[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14391 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[2] mem_wdata[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14393 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[1] mem_wdata[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14395 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1410 mem_la_wdata[0] mem_wdata[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14397 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1475 $abc$16053$new_n1467 mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$14401 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$16053$new_n1468 trap resetn $abc$16053$new_n1474 mem_do_rinst $abc$16053$new_n1467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n1473 $abc$16053$new_n1471 $abc$16053$new_n1469 $abc$16053$new_n1468 +110 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1470 mem_do_rdata $abc$16053$new_n1469 +0000 1 +0001 1 +0011 1 +.names mem_do_rinst mem_do_prefetch $abc$16053$new_n1470 +00 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1472 mem_do_wdata $abc$16053$new_n1471 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names mem_ready mem_valid $abc$16053$new_n1472 +11 1 +.names resetn trap $abc$16053$new_n1473 +10 1 +.names mem_state[1] mem_state[0] $abc$16053$new_n1474 +11 1 +.names $abc$16053$new_n1473 mem_state[1] mem_state[0] mem_do_rdata mem_do_rinst $abc$16053$new_n1475 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[30] $abc$16053$new_n1477 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14403 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[30] instr_jal decoded_imm_j[30] $abc$16053$new_n1477 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names instr_lui instr_auipc $abc$16053$new_n1478 +00 1 +.names decoder_trigger decoder_pseudo_trigger $abc$16053$new_n1479 +10 1 +.names is_beq_bne_blt_bge_bltu_bgeu instr_jalr is_lb_lh_lw_lbu_lhu is_sb_sh_sw is_alu_reg_imm $abc$16053$new_n1480 +00000 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[29] $abc$16053$new_n1482 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14405 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[29] instr_jal decoded_imm_j[29] $abc$16053$new_n1482 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[28] $abc$16053$new_n1484 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14407 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[28] instr_jal decoded_imm_j[28] $abc$16053$new_n1484 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[27] $abc$16053$new_n1486 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14409 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[27] instr_jal decoded_imm_j[27] $abc$16053$new_n1486 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[26] $abc$16053$new_n1488 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14411 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[26] instr_jal decoded_imm_j[26] $abc$16053$new_n1488 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[25] $abc$16053$new_n1490 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14413 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[25] instr_jal decoded_imm_j[25] $abc$16053$new_n1490 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[24] $abc$16053$new_n1492 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14415 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[24] instr_jal decoded_imm_j[24] $abc$16053$new_n1492 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[23] $abc$16053$new_n1494 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14417 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[23] instr_jal decoded_imm_j[23] $abc$16053$new_n1494 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[22] $abc$16053$new_n1496 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14419 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[22] instr_jal decoded_imm_j[22] $abc$16053$new_n1496 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[21] $abc$16053$new_n1498 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14421 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[21] instr_jal decoded_imm_j[21] $abc$16053$new_n1498 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[20] $abc$16053$new_n1500 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14423 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[20] instr_jal decoded_imm_j[20] $abc$16053$new_n1500 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[19] $abc$16053$new_n1502 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14425 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[19] instr_jal decoded_imm_j[19] $abc$16053$new_n1502 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[18] $abc$16053$new_n1504 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14427 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[18] instr_jal decoded_imm_j[18] $abc$16053$new_n1504 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[17] $abc$16053$new_n1506 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14429 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[17] instr_jal decoded_imm_j[17] $abc$16053$new_n1506 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[16] $abc$16053$new_n1508 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14431 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[16] instr_jal decoded_imm_j[16] $abc$16053$new_n1508 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[15] $abc$16053$new_n1510 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14433 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[15] instr_jal decoded_imm_j[15] $abc$16053$new_n1510 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[14] $abc$16053$new_n1512 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14435 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[14] instr_jal decoded_imm_j[14] $abc$16053$new_n1512 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[13] $abc$16053$new_n1514 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14437 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[13] instr_jal decoded_imm_j[13] $abc$16053$new_n1514 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1480 decoded_imm[12] $abc$16053$new_n1516 mem_rdata_q[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$14439 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1478 mem_rdata_q[12] instr_jal decoded_imm_j[12] $abc$16053$new_n1516 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1518 decoded_imm[11] $abc$16053$new_n1519 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14441 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[11] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1518 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[31] mem_rdata_q[7] $abc$16053$new_n1519 +0000 1 +0001 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1521 decoded_imm[10] mem_rdata_q[30] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14443 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[10] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1521 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1523 decoded_imm[9] mem_rdata_q[29] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14445 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[9] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1523 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1525 decoded_imm[8] mem_rdata_q[28] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14447 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[8] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1525 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1527 decoded_imm[7] mem_rdata_q[27] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14449 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[7] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1527 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1529 decoded_imm[6] mem_rdata_q[26] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14451 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[6] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1529 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1531 decoded_imm[5] mem_rdata_q[25] $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14453 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[5] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1531 +11111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1533 decoded_imm[4] $abc$16053$new_n1534 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14455 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[4] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1533 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[11] mem_rdata_q[24] $abc$16053$new_n1534 +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1536 decoded_imm[3] $abc$16053$new_n1537 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14457 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_jal decoded_imm_j[3] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1479 $abc$16053$new_n1536 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[10] mem_rdata_q[23] $abc$16053$new_n1537 +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 decoded_imm[2] $abc$16053$new_n1539 $abc$16053$new_n1540 $abc$16053$auto$rtlil.cc:2693:MuxGate$14459 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instr_jal decoded_imm_j[2] $abc$16053$new_n1478 $abc$16053$new_n1480 $abc$16053$new_n1539 +1111 1 +.names $abc$16053$new_n1480 is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[9] mem_rdata_q[22] $abc$16053$new_n1540 +00001 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$16053$new_n1479 $abc$16053$new_n1542 decoded_imm[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14461 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1480 $abc$16053$new_n1543 decoded_imm_j[1] $abc$16053$new_n1478 instr_jal $abc$16053$new_n1542 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names is_beq_bne_blt_bge_bltu_bgeu is_sb_sh_sw mem_rdata_q[8] mem_rdata_q[21] $abc$16053$new_n1543 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names $abc$16053$new_n1479 decoded_imm[0] $abc$16053$new_n1545 $abc$16053$new_n1480 $abc$16053$auto$rtlil.cc:2693:MuxGate$14463 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names is_sb_sh_sw mem_rdata_q[7] mem_rdata_q[20] is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1545 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$16053$new_n1472 mem_rdata[10] mem_rdata_q[10] mem_rdata_latched[10] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[10] decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14465 +001 1 +011 1 +110 1 +111 1 +.names mem_do_rinst $abc$16053$new_n1549 $abc$16053$new_n1548 +10 1 +.names resetn mem_do_rinst $abc$16053$new_n1550 $abc$16053$new_n1551 $abc$16053$new_n1474 $abc$16053$new_n1549 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$16053$new_n1472 mem_state[0] mem_state[1] $abc$16053$new_n1550 +101 1 +110 1 +111 1 +.names mem_do_wdata mem_do_rdata $abc$16053$new_n1551 +00 1 +.names $abc$16053$new_n1472 mem_rdata[9] mem_rdata_q[9] mem_rdata_latched[9] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[9] decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14467 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[8] mem_rdata_q[8] mem_rdata_latched[8] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[8] decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14469 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[7] mem_rdata_q[7] mem_rdata_latched[7] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[7] decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14471 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[31] mem_rdata_q[31] mem_rdata_latched[31] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14473 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14475 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14477 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14479 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14481 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14483 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14485 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14487 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14489 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14491 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14493 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[19] mem_rdata_q[19] mem_rdata_latched[19] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_imm_j[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14495 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[18] mem_rdata_q[18] mem_rdata_latched[18] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_imm_j[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14497 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[17] mem_rdata_q[17] mem_rdata_latched[17] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_imm_j[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14499 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[16] mem_rdata_q[16] mem_rdata_latched[16] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_imm_j[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14501 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[15] mem_rdata_q[15] mem_rdata_latched[15] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_imm_j[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14503 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[14] mem_rdata_q[14] mem_rdata_latched[14] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[14] decoded_imm_j[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14505 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[13] mem_rdata_q[13] mem_rdata_latched[13] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[13] decoded_imm_j[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14507 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[12] mem_rdata_q[12] mem_rdata_latched[12] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[12] decoded_imm_j[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14509 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[20] mem_rdata_q[20] mem_rdata_latched[20] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_imm_j[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14511 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[30] mem_rdata_q[30] mem_rdata_latched[30] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[30] decoded_imm_j[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14513 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[29] mem_rdata_q[29] mem_rdata_latched[29] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[29] decoded_imm_j[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14515 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[28] mem_rdata_q[28] mem_rdata_latched[28] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[28] decoded_imm_j[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14517 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[27] mem_rdata_q[27] mem_rdata_latched[27] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[27] decoded_imm_j[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14519 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[26] mem_rdata_q[26] mem_rdata_latched[26] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[26] decoded_imm_j[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14521 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[25] mem_rdata_q[25] mem_rdata_latched[25] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[25] decoded_imm_j[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14523 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[24] mem_rdata_q[24] mem_rdata_latched[24] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_imm_j[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14525 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[23] mem_rdata_q[23] mem_rdata_latched[23] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_imm_j[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14527 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[22] mem_rdata_q[22] mem_rdata_latched[22] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_imm_j[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14529 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[21] mem_rdata_q[21] mem_rdata_latched[21] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_imm_j[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14531 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1609 latched_rd[3] $abc$16053$new_n1612 decoded_rd[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14535 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names resetn $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1612 $abc$16053$new_n1609 +1001 1 +1011 1 +1110 1 +1111 1 +.names cpu_state[3] $abc$16053$new_n1611 cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1610 +11000 1 +.names cpu_state[7] cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$new_n1611 +0000 1 +.names $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1612 +11 1 +.names cpu_state[3] cpu_state[1] cpu_state[0] cpu_state[2] $abc$16053$new_n1613 +0000 1 +.names cpu_state[6] cpu_state[7] cpu_state[4] cpu_state[5] $abc$16053$new_n1614 +1000 1 +.names $abc$16053$new_n1609 latched_rd[2] $abc$16053$new_n1612 decoded_rd[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14539 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[1] $abc$16053$new_n1612 decoded_rd[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14543 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[0] $abc$16053$new_n1612 decoded_rd[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$14547 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[30] decoded_imm[30] $abc$16053$new_n1625 $abc$16053$auto$rtlil.cc:2693:MuxGate$14549 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names resetn $abc$16053$new_n1620 $abc$16053$new_n1619 +10 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1621 $abc$16053$new_n1620 +00 1 +.names cpu_state[4] $abc$16053$new_n1613 cpu_state[7] cpu_state[6] cpu_state[5] $abc$16053$new_n1621 +11000 1 +.names $abc$16053$new_n1613 cpu_state[5] cpu_state[7] cpu_state[6] cpu_state[4] $abc$16053$new_n1622 +11000 1 +.names $abc$16053$new_n1624 $abc$16053$new_n1621 $abc$16053$new_n1623 +00 1 +.names is_lui_auipc_jal is_jalr_addi_slti_sltiu_xori_ori_andi $abc$16053$new_n1624 +00 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] $abc$16053$new_n1625 +0001 1 +0011 1 +1010 1 +1011 1 +.names decoded_rs2[4] decoded_rs2[3] decoded_rs2[2] decoded_rs2[1] decoded_rs2[0] $abc$16053$new_n1626 +00000 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[29] decoded_imm[29] $abc$16053$new_n1628 $abc$16053$auto$rtlil.cc:2693:MuxGate$14551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] $abc$16053$new_n1628 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[28] decoded_imm[28] $abc$16053$new_n1630 $abc$16053$auto$rtlil.cc:2693:MuxGate$14553 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] $abc$16053$new_n1630 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[27] decoded_imm[27] $abc$16053$new_n1632 $abc$16053$auto$rtlil.cc:2693:MuxGate$14555 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] $abc$16053$new_n1632 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[26] decoded_imm[26] $abc$16053$new_n1634 $abc$16053$auto$rtlil.cc:2693:MuxGate$14557 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] $abc$16053$new_n1634 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[25] decoded_imm[25] $abc$16053$new_n1636 $abc$16053$auto$rtlil.cc:2693:MuxGate$14559 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] $abc$16053$new_n1636 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[24] decoded_imm[24] $abc$16053$new_n1638 $abc$16053$auto$rtlil.cc:2693:MuxGate$14561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] $abc$16053$new_n1638 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[23] decoded_imm[23] $abc$16053$new_n1640 $abc$16053$auto$rtlil.cc:2693:MuxGate$14563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] $abc$16053$new_n1640 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[22] decoded_imm[22] $abc$16053$new_n1642 $abc$16053$auto$rtlil.cc:2693:MuxGate$14565 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] $abc$16053$new_n1642 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[21] decoded_imm[21] $abc$16053$new_n1644 $abc$16053$auto$rtlil.cc:2693:MuxGate$14567 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] $abc$16053$new_n1644 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[20] decoded_imm[20] $abc$16053$new_n1646 $abc$16053$auto$rtlil.cc:2693:MuxGate$14569 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] $abc$16053$new_n1646 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[19] decoded_imm[19] $abc$16053$new_n1648 $abc$16053$auto$rtlil.cc:2693:MuxGate$14571 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] $abc$16053$new_n1648 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[18] decoded_imm[18] $abc$16053$new_n1650 $abc$16053$auto$rtlil.cc:2693:MuxGate$14573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] $abc$16053$new_n1650 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[17] decoded_imm[17] $abc$16053$new_n1652 $abc$16053$auto$rtlil.cc:2693:MuxGate$14575 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] $abc$16053$new_n1652 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[16] decoded_imm[16] $abc$16053$new_n1654 $abc$16053$auto$rtlil.cc:2693:MuxGate$14577 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] $abc$16053$new_n1654 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[15] decoded_imm[15] $abc$16053$new_n1656 $abc$16053$auto$rtlil.cc:2693:MuxGate$14579 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] $abc$16053$new_n1656 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[14] decoded_imm[14] $abc$16053$new_n1658 $abc$16053$auto$rtlil.cc:2693:MuxGate$14581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] $abc$16053$new_n1658 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[13] decoded_imm[13] $abc$16053$new_n1660 $abc$16053$auto$rtlil.cc:2693:MuxGate$14583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] $abc$16053$new_n1660 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[12] decoded_imm[12] $abc$16053$new_n1662 $abc$16053$auto$rtlil.cc:2693:MuxGate$14585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] $abc$16053$new_n1662 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[11] decoded_imm[11] $abc$16053$new_n1664 $abc$16053$auto$rtlil.cc:2693:MuxGate$14587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] $abc$16053$new_n1664 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[10] decoded_imm[10] $abc$16053$new_n1666 $abc$16053$auto$rtlil.cc:2693:MuxGate$14589 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] $abc$16053$new_n1666 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[9] decoded_imm[9] $abc$16053$new_n1668 $abc$16053$auto$rtlil.cc:2693:MuxGate$14591 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] $abc$16053$new_n1668 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[8] decoded_imm[8] $abc$16053$new_n1670 $abc$16053$auto$rtlil.cc:2693:MuxGate$14593 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] $abc$16053$new_n1670 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[7] decoded_imm[7] $abc$16053$new_n1672 $abc$16053$auto$rtlil.cc:2693:MuxGate$14595 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] $abc$16053$new_n1672 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[6] decoded_imm[6] $abc$16053$new_n1674 $abc$16053$auto$rtlil.cc:2693:MuxGate$14597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] $abc$16053$new_n1674 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[5] decoded_imm[5] $abc$16053$new_n1676 $abc$16053$auto$rtlil.cc:2693:MuxGate$14599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] $abc$16053$new_n1676 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[4] decoded_imm[4] $abc$16053$new_n1678 $abc$16053$auto$rtlil.cc:2693:MuxGate$14601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] $abc$16053$new_n1678 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[3] decoded_imm[3] $abc$16053$new_n1680 $abc$16053$auto$rtlil.cc:2693:MuxGate$14603 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] $abc$16053$new_n1680 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[2] decoded_imm[2] $abc$16053$new_n1682 $abc$16053$auto$rtlil.cc:2693:MuxGate$14605 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] $abc$16053$new_n1682 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[1] decoded_imm[1] $abc$16053$new_n1684 $abc$16053$auto$rtlil.cc:2693:MuxGate$14607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] $abc$16053$new_n1684 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 mem_la_wdata[0] decoded_imm[0] $abc$16053$new_n1686 $abc$16053$auto$rtlil.cc:2693:MuxGate$14609 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] $abc$16053$new_n1686 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n1747 $abc$16053$new_n1690 +100 1 +.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1743 $abc$16053$new_n1741 $abc$16053$new_n1739 $abc$16053$new_n1691 +10000 1 +.names $abc$16053$new_n1693 $abc$16053$new_n1737 $abc$16053$new_n1692 +10 1 +.names $abc$16053$new_n1694 $abc$16053$new_n1735 $abc$16053$new_n1693 +10 1 +.names $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n1731 $abc$16053$new_n1694 +100 1 +.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1728 $abc$16053$new_n1727 $abc$16053$new_n1725 $abc$16053$new_n1695 +10000 1 +.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1722 $abc$16053$new_n1721 $abc$16053$new_n1719 $abc$16053$new_n1696 +10000 1 +.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1717 $abc$16053$new_n1715 $abc$16053$new_n1697 +1000 1 +.names $abc$16053$new_n1699 $abc$16053$new_n1713 $abc$16053$new_n1698 +10 1 +.names $abc$16053$new_n1700 $abc$16053$new_n1711 $abc$16053$new_n1699 +10 1 +.names $abc$16053$new_n1701 $abc$16053$new_n1710 $abc$16053$new_n1700 +10 1 +.names $abc$16053$new_n1702 $abc$16053$new_n1708 $abc$16053$new_n1707 $abc$16053$new_n1701 +100 1 +.names $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1702 +00 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1705 reg_next_pc[3] $abc$16053$new_n1703 +000 1 +010 1 +110 1 +111 1 +.names latched_branch latched_store $abc$16053$new_n1704 +11 1 +.names latched_stalu alu_out_q[3] reg_out[3] $abc$16053$new_n1705 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[2] alu_out_q[2] reg_out[2] $abc$16053$new_n1706 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[5] alu_out_q[5] reg_out[5] $abc$16053$new_n1707 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1709 reg_next_pc[4] $abc$16053$new_n1708 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[4] reg_out[4] $abc$16053$new_n1709 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[6] alu_out_q[6] reg_out[6] $abc$16053$new_n1710 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1712 reg_next_pc[7] $abc$16053$new_n1711 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[7] reg_out[7] $abc$16053$new_n1712 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1714 reg_next_pc[8] $abc$16053$new_n1713 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[8] reg_out[8] $abc$16053$new_n1714 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1716 reg_next_pc[11] $abc$16053$new_n1715 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[11] reg_out[11] $abc$16053$new_n1716 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[10] alu_out_q[10] reg_out[10] $abc$16053$new_n1717 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[9] alu_out_q[9] reg_out[9] $abc$16053$new_n1718 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1720 reg_next_pc[15] $abc$16053$new_n1719 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[15] reg_out[15] $abc$16053$new_n1720 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[14] alu_out_q[14] reg_out[14] $abc$16053$new_n1721 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[13] alu_out_q[13] reg_out[13] $abc$16053$new_n1722 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1724 reg_next_pc[12] $abc$16053$new_n1723 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[12] reg_out[12] $abc$16053$new_n1724 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1726 reg_next_pc[19] $abc$16053$new_n1725 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[19] reg_out[19] $abc$16053$new_n1726 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[18] alu_out_q[18] reg_out[18] $abc$16053$new_n1727 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[17] alu_out_q[17] reg_out[17] $abc$16053$new_n1728 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1730 reg_next_pc[16] $abc$16053$new_n1729 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[16] reg_out[16] $abc$16053$new_n1730 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1732 reg_next_pc[21] $abc$16053$new_n1731 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[21] reg_out[21] $abc$16053$new_n1732 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1734 reg_next_pc[20] $abc$16053$new_n1733 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[20] reg_out[20] $abc$16053$new_n1734 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1736 reg_next_pc[22] $abc$16053$new_n1735 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[22] reg_out[22] $abc$16053$new_n1736 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1738 reg_next_pc[23] $abc$16053$new_n1737 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[23] reg_out[23] $abc$16053$new_n1738 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1740 reg_next_pc[27] $abc$16053$new_n1739 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[27] reg_out[27] $abc$16053$new_n1740 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1742 reg_next_pc[26] $abc$16053$new_n1741 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[26] reg_out[26] $abc$16053$new_n1742 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1744 reg_next_pc[25] $abc$16053$new_n1743 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[25] reg_out[25] $abc$16053$new_n1744 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1746 reg_next_pc[24] $abc$16053$new_n1745 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[24] reg_out[24] $abc$16053$new_n1746 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[29] alu_out_q[29] reg_out[29] $abc$16053$new_n1747 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1749 reg_next_pc[28] $abc$16053$new_n1748 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[28] reg_out[28] $abc$16053$new_n1749 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1704 latched_stalu reg_next_pc[30] alu_out_q[30] reg_out[30] $abc$16053$new_n1750 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n1748 decoded_imm_j[28] decoded_imm_j[29] $abc$16053$new_n1747 $abc$16053$new_n1752 $abc$16053$new_n1751 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1741 decoded_imm_j[26] decoded_imm_j[27] $abc$16053$new_n1739 $abc$16053$new_n1753 $abc$16053$new_n1752 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1745 decoded_imm_j[24] decoded_imm_j[25] $abc$16053$new_n1743 $abc$16053$new_n1754 $abc$16053$new_n1753 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1735 decoded_imm_j[22] decoded_imm_j[23] $abc$16053$new_n1737 $abc$16053$new_n1755 $abc$16053$new_n1754 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1733 decoded_imm_j[20] decoded_imm_j[21] $abc$16053$new_n1731 $abc$16053$new_n1756 $abc$16053$new_n1755 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1727 decoded_imm_j[18] decoded_imm_j[19] $abc$16053$new_n1725 $abc$16053$new_n1757 $abc$16053$new_n1756 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1729 decoded_imm_j[16] decoded_imm_j[17] $abc$16053$new_n1728 $abc$16053$new_n1758 $abc$16053$new_n1757 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1721 decoded_imm_j[14] decoded_imm_j[15] $abc$16053$new_n1719 $abc$16053$new_n1759 $abc$16053$new_n1758 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1723 decoded_imm_j[12] decoded_imm_j[13] $abc$16053$new_n1722 $abc$16053$new_n1760 $abc$16053$new_n1759 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1717 decoded_imm_j[10] decoded_imm_j[11] $abc$16053$new_n1715 $abc$16053$new_n1761 $abc$16053$new_n1760 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1713 decoded_imm_j[8] decoded_imm_j[9] $abc$16053$new_n1718 $abc$16053$new_n1762 $abc$16053$new_n1761 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1710 decoded_imm_j[6] decoded_imm_j[7] $abc$16053$new_n1711 $abc$16053$new_n1763 $abc$16053$new_n1762 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n1708 decoded_imm_j[4] decoded_imm_j[5] $abc$16053$new_n1707 $abc$16053$new_n1764 $abc$16053$new_n1763 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names decoded_imm_j[3] decoded_imm_j[2] $abc$16053$new_n1765 $abc$16053$new_n1706 $abc$16053$new_n1703 $abc$16053$new_n1764 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names decoded_imm_j[1] $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1765 +1001 1 +1011 1 +1100 1 +1101 1 +.names latched_stalu alu_out_q[1] reg_out[1] $abc$16053$new_n1766 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1748 decoded_imm_j[28] $abc$16053$new_n1752 $abc$16053$new_n1769 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1778 $abc$16053$new_n1743 $abc$16053$new_n1777 +10 1 +.names $abc$16053$new_n1692 $abc$16053$new_n1745 $abc$16053$new_n1778 +10 1 +.names decoded_imm_j[24] $abc$16053$new_n1745 $abc$16053$new_n1754 $abc$16053$new_n1787 +000 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1735 decoded_imm_j[22] $abc$16053$new_n1755 $abc$16053$new_n1793 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1733 decoded_imm_j[20] $abc$16053$new_n1756 $abc$16053$new_n1800 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1809 $abc$16053$new_n1728 $abc$16053$new_n1808 +10 1 +.names $abc$16053$new_n1696 $abc$16053$new_n1729 $abc$16053$new_n1809 +10 1 +.names decoded_imm_j[16] $abc$16053$new_n1729 $abc$16053$new_n1758 $abc$16053$new_n1818 +000 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1826 $abc$16053$new_n1722 $abc$16053$new_n1825 +10 1 +.names $abc$16053$new_n1697 $abc$16053$new_n1723 $abc$16053$new_n1826 +10 1 +.names $abc$16053$new_n1723 decoded_imm_j[12] $abc$16053$new_n1760 $abc$16053$new_n1835 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1698 $abc$16053$new_n1718 $abc$16053$new_n1842 +10 1 +.names $abc$16053$new_n1713 decoded_imm_j[8] $abc$16053$new_n1762 $abc$16053$new_n1851 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1858 +001 1 +100 1 +101 1 +111 1 +.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[6] $abc$16053$new_n1860 $abc$16053$new_n1710 $abc$16053$auto$rtlil.cc:2693:MuxGate$14659 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instr_jal $abc$16053$new_n1710 decoded_imm_j[6] $abc$16053$new_n1763 $abc$16053$new_n1701 $abc$16053$new_n1860 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 decoder_trigger reg_next_pc[4] $abc$16053$new_n1866 $abc$16053$new_n1708 $abc$16053$auto$rtlil.cc:2693:MuxGate$14663 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instr_jal $abc$16053$new_n1708 decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n1702 $abc$16053$new_n1866 +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1872 reg_next_pc[2] $abc$16053$new_n1706 decoder_trigger $abc$16053$auto$rtlil.cc:2693:MuxGate$14667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names decoder_trigger $abc$16053$new_n1706 decoded_imm_j[2] $abc$16053$new_n1765 instr_jal $abc$16053$new_n1872 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names $abc$16053$new_n1874 reg_next_pc[1] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14669 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1875 decoder_trigger instr_jal decoded_imm_j[1] $abc$16053$new_n1874 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11111 1 +.names $abc$16053$new_n1704 $abc$16053$new_n1766 reg_next_pc[1] $abc$16053$new_n1875 +000 1 +010 1 +110 1 +111 1 +.names reg_next_pc[0] $abc$16053$new_n1612 $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14671 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1750 reg_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14673 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1747 reg_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14675 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1748 reg_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14677 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1739 reg_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14679 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1741 reg_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14681 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1743 reg_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14683 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1745 reg_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14685 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1737 reg_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14687 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1735 reg_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14689 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1731 reg_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14691 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1733 reg_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14693 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1725 reg_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14695 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1727 reg_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14697 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1728 reg_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14699 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1729 reg_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14701 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1719 reg_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14703 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1721 reg_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14705 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1722 reg_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14707 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1723 reg_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14709 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1715 reg_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14711 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1717 reg_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14713 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1718 reg_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14715 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1713 reg_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14717 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1711 reg_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14719 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1710 reg_pc[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$14721 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1707 reg_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14723 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1708 reg_pc[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14725 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1703 reg_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14727 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1706 reg_pc[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14729 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1875 reg_pc[1] $abc$16053$auto$rtlil.cc:2693:MuxGate$14731 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1612 reg_pc[0] reg_next_pc[0] $abc$16053$new_n1704 $abc$16053$auto$rtlil.cc:2693:MuxGate$14733 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$14735 +01 1 +10 1 +.names count_instr[58] count_instr[59] count_instr[60] count_instr[61] $abc$16053$new_n1910 $abc$16053$new_n1909 +11111 1 +.names count_instr[54] count_instr[55] count_instr[56] count_instr[57] $abc$16053$new_n1911 $abc$16053$new_n1910 +11111 1 +.names count_instr[50] count_instr[51] count_instr[52] count_instr[53] $abc$16053$new_n1912 $abc$16053$new_n1911 +11111 1 +.names count_instr[46] count_instr[47] count_instr[48] count_instr[49] $abc$16053$new_n1913 $abc$16053$new_n1912 +11111 1 +.names count_instr[42] count_instr[43] count_instr[44] count_instr[45] $abc$16053$new_n1914 $abc$16053$new_n1913 +11111 1 +.names count_instr[38] count_instr[39] count_instr[40] count_instr[41] $abc$16053$new_n1915 $abc$16053$new_n1914 +11111 1 +.names count_instr[34] count_instr[35] count_instr[36] count_instr[37] $abc$16053$new_n1916 $abc$16053$new_n1915 +11111 1 +.names count_instr[30] count_instr[31] count_instr[32] count_instr[33] $abc$16053$new_n1917 $abc$16053$new_n1916 +11111 1 +.names count_instr[26] count_instr[27] count_instr[28] count_instr[29] $abc$16053$new_n1918 $abc$16053$new_n1917 +11111 1 +.names count_instr[22] count_instr[23] count_instr[24] count_instr[25] $abc$16053$new_n1919 $abc$16053$new_n1918 +11111 1 +.names count_instr[18] count_instr[19] count_instr[20] count_instr[21] $abc$16053$new_n1920 $abc$16053$new_n1919 +11111 1 +.names count_instr[14] count_instr[15] count_instr[16] count_instr[17] $abc$16053$new_n1921 $abc$16053$new_n1920 +11111 1 +.names count_instr[10] count_instr[11] count_instr[12] count_instr[13] $abc$16053$new_n1922 $abc$16053$new_n1921 +11111 1 +.names count_instr[6] count_instr[7] count_instr[8] count_instr[9] $abc$16053$new_n1923 $abc$16053$new_n1922 +11111 1 +.names count_instr[2] count_instr[3] count_instr[4] count_instr[5] $abc$16053$new_n1924 $abc$16053$new_n1923 +11111 1 +.names decoder_trigger count_instr[0] count_instr[1] $abc$16053$new_n1614 $abc$16053$new_n1613 $abc$16053$new_n1924 +11111 1 +.names count_instr[61] count_instr[58] count_instr[59] count_instr[60] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14737 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[60] count_instr[58] count_instr[59] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14739 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[59] count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14741 +011 1 +100 1 +101 1 +110 1 +.names count_instr[58] $abc$16053$new_n1910 $abc$16053$auto$rtlil.cc:2693:MuxGate$14743 +01 1 +10 1 +.names count_instr[57] count_instr[54] count_instr[55] count_instr[56] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14745 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[56] count_instr[54] count_instr[55] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14747 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[55] count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14749 +011 1 +100 1 +101 1 +110 1 +.names count_instr[54] $abc$16053$new_n1911 $abc$16053$auto$rtlil.cc:2693:MuxGate$14751 +01 1 +10 1 +.names count_instr[53] count_instr[50] count_instr[51] count_instr[52] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14753 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[52] count_instr[50] count_instr[51] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14755 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[51] count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14757 +011 1 +100 1 +101 1 +110 1 +.names count_instr[50] $abc$16053$new_n1912 $abc$16053$auto$rtlil.cc:2693:MuxGate$14759 +01 1 +10 1 +.names count_instr[49] count_instr[46] count_instr[47] count_instr[48] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14761 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[48] count_instr[46] count_instr[47] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14763 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[47] count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14765 +011 1 +100 1 +101 1 +110 1 +.names count_instr[46] $abc$16053$new_n1913 $abc$16053$auto$rtlil.cc:2693:MuxGate$14767 +01 1 +10 1 +.names count_instr[45] count_instr[42] count_instr[43] count_instr[44] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14769 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[44] count_instr[42] count_instr[43] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14771 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[43] count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14773 +011 1 +100 1 +101 1 +110 1 +.names count_instr[42] $abc$16053$new_n1914 $abc$16053$auto$rtlil.cc:2693:MuxGate$14775 +01 1 +10 1 +.names count_instr[41] count_instr[38] count_instr[39] count_instr[40] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14777 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[40] count_instr[38] count_instr[39] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14779 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[39] count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14781 +011 1 +100 1 +101 1 +110 1 +.names count_instr[38] $abc$16053$new_n1915 $abc$16053$auto$rtlil.cc:2693:MuxGate$14783 +01 1 +10 1 +.names count_instr[37] count_instr[34] count_instr[35] count_instr[36] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14785 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[36] count_instr[34] count_instr[35] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14787 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[35] count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14789 +011 1 +100 1 +101 1 +110 1 +.names count_instr[34] $abc$16053$new_n1916 $abc$16053$auto$rtlil.cc:2693:MuxGate$14791 +01 1 +10 1 +.names count_instr[33] count_instr[30] count_instr[31] count_instr[32] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14793 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[32] count_instr[30] count_instr[31] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14795 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[31] count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14797 +011 1 +100 1 +101 1 +110 1 +.names count_instr[30] $abc$16053$new_n1917 $abc$16053$auto$rtlil.cc:2693:MuxGate$14799 +01 1 +10 1 +.names count_instr[29] count_instr[26] count_instr[27] count_instr[28] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14801 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[28] count_instr[26] count_instr[27] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14803 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[27] count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14805 +011 1 +100 1 +101 1 +110 1 +.names count_instr[26] $abc$16053$new_n1918 $abc$16053$auto$rtlil.cc:2693:MuxGate$14807 +01 1 +10 1 +.names count_instr[25] count_instr[22] count_instr[23] count_instr[24] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14809 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[24] count_instr[22] count_instr[23] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14811 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[23] count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14813 +011 1 +100 1 +101 1 +110 1 +.names count_instr[22] $abc$16053$new_n1919 $abc$16053$auto$rtlil.cc:2693:MuxGate$14815 +01 1 +10 1 +.names count_instr[21] count_instr[18] count_instr[19] count_instr[20] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14817 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_instr[20] count_instr[18] count_instr[19] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14819 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[19] count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14821 +011 1 +100 1 +101 1 +110 1 +.names count_instr[18] $abc$16053$new_n1920 $abc$16053$auto$rtlil.cc:2693:MuxGate$14823 +01 1 +10 1 +.names count_instr[17] count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14825 +011 1 +100 1 +101 1 +110 1 +.names count_instr[14] count_instr[15] $abc$16053$new_n1921 $abc$16053$new_n1970 +111 1 +.names count_instr[16] $abc$16053$new_n1970 $abc$16053$auto$rtlil.cc:2693:MuxGate$14827 +01 1 +10 1 +.names count_instr[15] count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14829 +011 1 +100 1 +101 1 +110 1 +.names count_instr[14] $abc$16053$new_n1921 $abc$16053$auto$rtlil.cc:2693:MuxGate$14831 +01 1 +10 1 +.names count_instr[13] count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14833 +011 1 +100 1 +101 1 +110 1 +.names count_instr[10] count_instr[11] $abc$16053$new_n1922 $abc$16053$new_n1975 +111 1 +.names count_instr[12] $abc$16053$new_n1975 $abc$16053$auto$rtlil.cc:2693:MuxGate$14835 +01 1 +10 1 +.names count_instr[11] count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14837 +011 1 +100 1 +101 1 +110 1 +.names count_instr[10] $abc$16053$new_n1922 $abc$16053$auto$rtlil.cc:2693:MuxGate$14839 +01 1 +10 1 +.names count_instr[9] count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14841 +011 1 +100 1 +101 1 +110 1 +.names count_instr[6] count_instr[7] $abc$16053$new_n1923 $abc$16053$new_n1980 +111 1 +.names count_instr[8] $abc$16053$new_n1980 $abc$16053$auto$rtlil.cc:2693:MuxGate$14843 +01 1 +10 1 +.names count_instr[7] count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14845 +011 1 +100 1 +101 1 +110 1 +.names count_instr[6] $abc$16053$new_n1923 $abc$16053$auto$rtlil.cc:2693:MuxGate$14847 +01 1 +10 1 +.names count_instr[5] count_instr[3] count_instr[4] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14849 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[2] $abc$16053$new_n1924 $abc$16053$new_n1985 +11 1 +.names count_instr[4] count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14851 +011 1 +100 1 +101 1 +110 1 +.names count_instr[3] $abc$16053$new_n1985 $abc$16053$auto$rtlil.cc:2693:MuxGate$14853 +01 1 +10 1 +.names count_instr[2] $abc$16053$new_n1924 $abc$16053$auto$rtlil.cc:2693:MuxGate$14855 +01 1 +10 1 +.names count_instr[1] decoder_trigger count_instr[0] $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$14857 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_instr[0] $abc$16053$new_n1991 $abc$16053$auto$rtlil.cc:2693:MuxGate$14859 +01 1 +10 1 +.names decoder_trigger $abc$16053$new_n1612 $abc$16053$new_n1991 +11 1 +.names $abc$16053$new_n1472 mem_rdata[11] mem_rdata_q[11] mem_rdata_latched[11] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[6] mem_rdata_q[6] mem_rdata_latched[6] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[5] mem_rdata_q[5] mem_rdata_latched[5] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[4] mem_rdata_q[4] mem_rdata_latched[4] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[3] mem_rdata_q[3] mem_rdata_latched[3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[2] mem_rdata_q[2] mem_rdata_latched[2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[1] mem_rdata_q[1] mem_rdata_latched[1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1472 mem_rdata[0] mem_rdata_q[0] mem_rdata_latched[0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2001 pcpi_rs1[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14923 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2017 pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2019 $abc$16053$new_n2001 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[27] decoded_imm[27] pcpi_rs1[28] decoded_imm[28] $abc$16053$new_n2003 $abc$16053$new_n2002 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[25] decoded_imm[25] pcpi_rs1[26] decoded_imm[26] $abc$16053$new_n2004 $abc$16053$new_n2003 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[23] decoded_imm[23] pcpi_rs1[24] decoded_imm[24] $abc$16053$new_n2005 $abc$16053$new_n2004 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[21] decoded_imm[21] pcpi_rs1[22] decoded_imm[22] $abc$16053$new_n2006 $abc$16053$new_n2005 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[19] decoded_imm[19] pcpi_rs1[20] decoded_imm[20] $abc$16053$new_n2007 $abc$16053$new_n2006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[17] decoded_imm[17] pcpi_rs1[18] decoded_imm[18] $abc$16053$new_n2008 $abc$16053$new_n2007 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[15] decoded_imm[15] pcpi_rs1[16] decoded_imm[16] $abc$16053$new_n2009 $abc$16053$new_n2008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[13] decoded_imm[13] pcpi_rs1[14] decoded_imm[14] $abc$16053$new_n2010 $abc$16053$new_n2009 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[11] decoded_imm[11] pcpi_rs1[12] decoded_imm[12] $abc$16053$new_n2011 $abc$16053$new_n2010 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[9] decoded_imm[9] pcpi_rs1[10] decoded_imm[10] $abc$16053$new_n2012 $abc$16053$new_n2011 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[7] decoded_imm[7] pcpi_rs1[8] decoded_imm[8] $abc$16053$new_n2013 $abc$16053$new_n2012 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[5] decoded_imm[5] pcpi_rs1[6] decoded_imm[6] $abc$16053$new_n2014 $abc$16053$new_n2013 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[3] decoded_imm[3] pcpi_rs1[4] decoded_imm[4] $abc$16053$new_n2015 $abc$16053$new_n2014 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2015 +000 1 +001 1 +011 1 +101 1 +.names pcpi_rs1[0] decoded_imm[0] pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2016 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2023 $abc$16053$new_n2029 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[29] $abc$16053$new_n2017 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2018 +10 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2020 $abc$16053$new_n2019 +00 1 +.names $abc$16053$new_n1611 cpu_state[1] cpu_state[3] cpu_state[0] cpu_state[2] $abc$16053$new_n2020 +11000 1 +.names cpu_state[0] $abc$16053$new_n1611 cpu_state[3] cpu_state[1] cpu_state[2] $abc$16053$new_n2021 +11000 1 +.names $abc$16053$new_n1611 cpu_state[2] cpu_state[3] cpu_state[1] cpu_state[0] $abc$16053$new_n2022 +11000 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2024 $abc$16053$new_n2028 pcpi_rs1[25] $abc$16053$new_n2025 $abc$16053$new_n2023 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[28] pcpi_rs1[30] $abc$16053$new_n2024 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2026 instr_srl instr_srli $abc$16053$new_n2025 +100 1 +.names instr_sra instr_srai $abc$16053$new_n2026 +00 1 +.names reg_sh[3] reg_sh[2] reg_sh[4] $abc$16053$new_n2027 +000 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2026 pcpi_rs1[31] $abc$16053$new_n2028 +000 1 +010 1 +011 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] $abc$16053$new_n2029 +1001 1 +1011 1 +1110 1 +1111 1 +.names is_lui_auipc_jal $abc$16053$new_n2031 $abc$16053$new_n2030 +00 1 +.names decoded_rs1[4] decoded_rs1[3] decoded_rs1[2] decoded_rs1[1] decoded_rs1[0] $abc$16053$new_n2031 +00000 1 +.names is_lui_auipc_jal instr_lui $abc$16053$new_n2032 +10 1 +.names resetn $abc$16053$new_n2036 $abc$16053$new_n2034 $abc$16053$new_n2035 $abc$16053$new_n2021 $abc$16053$new_n2033 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2035 $abc$16053$new_n2020 mem_do_wdata mem_do_rdata $abc$16053$new_n2021 $abc$16053$new_n2034 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$new_n2035 +11 1 +.names $abc$16053$new_n2038 $abc$16053$new_n2018 $abc$16053$new_n2039 cpu_state[2] $abc$16053$new_n1622 $abc$16053$new_n2036 +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2027 reg_sh[0] reg_sh[1] $abc$16053$new_n2038 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2025 instr_sll instr_slli $abc$16053$new_n2039 +100 1 +.names $abc$16053$new_n2033 $abc$16053$new_n3156 pcpi_rs1[28] $abc$16053$new_n2041 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14925 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names pcpi_rs1[28] decoded_imm[28] pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2041 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2044 reg_pc[28] $abc$16053$new_n2032 $abc$16053$new_n2043 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] $abc$16053$new_n2044 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[27] $abc$16053$new_n2049 $abc$16053$new_n2048 $abc$16053$auto$rtlil.cc:2693:MuxGate$14927 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names pcpi_rs1[27] decoded_imm[27] $abc$16053$new_n2003 $abc$16053$new_n2019 $abc$16053$new_n2048 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2050 $abc$16053$new_n2052 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[27] $abc$16053$new_n2049 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2051 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[23] pcpi_rs1[31] $abc$16053$new_n2050 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[26] pcpi_rs1[28] $abc$16053$new_n2051 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] $abc$16053$new_n2052 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2055 pcpi_rs1[26] $abc$16053$new_n2054 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14929 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[26] decoded_imm[26] pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2054 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2056 $abc$16053$new_n2058 $abc$16053$new_n2055 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2057 pcpi_rs1[22] pcpi_rs1[30] $abc$16053$new_n2056 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2025 pcpi_rs1[25] pcpi_rs1[27] $abc$16053$new_n2057 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2059 $abc$16053$new_n2032 reg_pc[26] $abc$16053$new_n2058 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] $abc$16053$new_n2059 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[25] $abc$16053$new_n2061 $abc$16053$new_n2062 $abc$16053$auto$rtlil.cc:2693:MuxGate$14931 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[25] decoded_imm[25] $abc$16053$new_n2004 $abc$16053$new_n2019 $abc$16053$new_n2061 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2063 $abc$16053$new_n2065 $abc$16053$new_n2062 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2064 pcpi_rs1[24] pcpi_rs1[26] $abc$16053$new_n2063 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[29] $abc$16053$new_n2064 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2066 $abc$16053$new_n2032 reg_pc[25] $abc$16053$new_n2065 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] $abc$16053$new_n2066 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2069 pcpi_rs1[24] $abc$16053$new_n2068 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14933 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[24] decoded_imm[24] pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2068 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2070 $abc$16053$new_n2072 $abc$16053$new_n2069 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2071 pcpi_rs1[23] pcpi_rs1[25] $abc$16053$new_n2070 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[20] pcpi_rs1[28] $abc$16053$new_n2071 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2073 $abc$16053$new_n2032 reg_pc[24] $abc$16053$new_n2072 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] $abc$16053$new_n2073 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[23] $abc$16053$new_n2075 $abc$16053$new_n2076 $abc$16053$auto$rtlil.cc:2693:MuxGate$14935 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[23] decoded_imm[23] $abc$16053$new_n2005 $abc$16053$new_n2019 $abc$16053$new_n2075 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2077 $abc$16053$new_n2079 $abc$16053$new_n2076 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2078 pcpi_rs1[22] pcpi_rs1[24] $abc$16053$new_n2077 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[19] pcpi_rs1[27] $abc$16053$new_n2078 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2080 $abc$16053$new_n2032 reg_pc[23] $abc$16053$new_n2079 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] $abc$16053$new_n2080 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2084 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2086 $abc$16053$new_n2032 reg_pc[22] $abc$16053$new_n2085 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] $abc$16053$new_n2086 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2090 pcpi_rs1[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14939 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2091 pcpi_rs1[21] decoded_imm[21] $abc$16053$new_n2006 $abc$16053$new_n2019 $abc$16053$new_n2090 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2092 $abc$16053$new_n2094 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[21] $abc$16053$new_n2091 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2093 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[17] pcpi_rs1[25] $abc$16053$new_n2092 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[20] pcpi_rs1[22] $abc$16053$new_n2093 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] $abc$16053$new_n2094 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2097 pcpi_rs1[20] $abc$16053$new_n2096 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[20] decoded_imm[20] pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2096 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2098 $abc$16053$new_n2100 $abc$16053$new_n2097 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2099 pcpi_rs1[19] pcpi_rs1[21] $abc$16053$new_n2098 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[16] pcpi_rs1[24] $abc$16053$new_n2099 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2101 $abc$16053$new_n2032 reg_pc[20] $abc$16053$new_n2100 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] $abc$16053$new_n2101 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[19] $abc$16053$new_n2106 $abc$16053$new_n2104 $abc$16053$new_n2103 $abc$16053$auto$rtlil.cc:2693:MuxGate$14943 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[19] decoded_imm[19] $abc$16053$new_n2007 $abc$16053$new_n2019 $abc$16053$new_n2103 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2105 reg_pc[19] $abc$16053$new_n2032 $abc$16053$new_n2104 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] $abc$16053$new_n2105 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2107 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[18] pcpi_rs1[20] $abc$16053$new_n2106 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[15] pcpi_rs1[23] $abc$16053$new_n2107 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2110 pcpi_rs1[18] $abc$16053$new_n2109 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14945 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[18] decoded_imm[18] pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2109 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2111 $abc$16053$new_n2113 $abc$16053$new_n2110 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2112 pcpi_rs1[17] pcpi_rs1[19] $abc$16053$new_n2111 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[14] pcpi_rs1[22] $abc$16053$new_n2112 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2114 $abc$16053$new_n2032 reg_pc[18] $abc$16053$new_n2113 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] $abc$16053$new_n2114 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[17] $abc$16053$new_n2116 $abc$16053$new_n2117 $abc$16053$auto$rtlil.cc:2693:MuxGate$14947 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[17] decoded_imm[17] $abc$16053$new_n2008 $abc$16053$new_n2019 $abc$16053$new_n2116 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2118 $abc$16053$new_n2120 $abc$16053$new_n2117 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2119 pcpi_rs1[16] pcpi_rs1[18] $abc$16053$new_n2118 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[21] $abc$16053$new_n2119 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2121 $abc$16053$new_n2032 reg_pc[17] $abc$16053$new_n2120 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] $abc$16053$new_n2121 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2124 pcpi_rs1[16] $abc$16053$new_n2123 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[16] decoded_imm[16] pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2123 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2125 $abc$16053$new_n2128 $abc$16053$new_n2127 $abc$16053$new_n2124 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2126 $abc$16053$new_n2032 reg_pc[16] $abc$16053$new_n2125 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] $abc$16053$new_n2126 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[17] $abc$16053$new_n2127 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[20] $abc$16053$new_n2128 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2033 pcpi_rs1[15] $abc$16053$new_n2130 $abc$16053$new_n2131 $abc$16053$auto$rtlil.cc:2693:MuxGate$14951 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[15] decoded_imm[15] $abc$16053$new_n2009 $abc$16053$new_n2019 $abc$16053$new_n2130 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2132 $abc$16053$new_n2134 $abc$16053$new_n2131 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2133 pcpi_rs1[14] pcpi_rs1[16] $abc$16053$new_n2132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[19] $abc$16053$new_n2133 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2135 $abc$16053$new_n2032 reg_pc[15] $abc$16053$new_n2134 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] $abc$16053$new_n2135 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2139 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2141 $abc$16053$new_n2032 reg_pc[14] $abc$16053$new_n2140 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] $abc$16053$new_n2141 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[13] $abc$16053$new_n2146 $abc$16053$new_n2145 $abc$16053$auto$rtlil.cc:2693:MuxGate$14955 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names pcpi_rs1[13] decoded_imm[13] $abc$16053$new_n2010 $abc$16053$new_n2019 $abc$16053$new_n2145 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2147 $abc$16053$new_n2149 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[13] $abc$16053$new_n2146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2148 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[9] pcpi_rs1[17] $abc$16053$new_n2147 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[12] pcpi_rs1[14] $abc$16053$new_n2148 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] $abc$16053$new_n2149 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2153 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2155 $abc$16053$new_n2032 reg_pc[12] $abc$16053$new_n2154 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] $abc$16053$new_n2155 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[11] $abc$16053$new_n2162 $abc$16053$new_n2160 $abc$16053$new_n2159 $abc$16053$auto$rtlil.cc:2693:MuxGate$14959 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[11] decoded_imm[11] $abc$16053$new_n2011 $abc$16053$new_n2019 $abc$16053$new_n2159 +0000 1 +0110 1 +1010 1 +1100 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2161 reg_pc[11] $abc$16053$new_n2032 $abc$16053$new_n2160 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] $abc$16053$new_n2161 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2163 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[15] $abc$16053$new_n2162 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[10] pcpi_rs1[12] $abc$16053$new_n2163 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2166 pcpi_rs1[10] $abc$16053$new_n2165 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[10] decoded_imm[10] pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2165 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2167 $abc$16053$new_n2169 $abc$16053$new_n2166 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2168 pcpi_rs1[9] pcpi_rs1[11] $abc$16053$new_n2167 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[6] pcpi_rs1[14] $abc$16053$new_n2168 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2170 $abc$16053$new_n2032 reg_pc[10] $abc$16053$new_n2169 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] $abc$16053$new_n2170 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 pcpi_rs1[9] $abc$16053$new_n2173 $abc$16053$new_n2172 $abc$16053$auto$rtlil.cc:2693:MuxGate$14963 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names pcpi_rs1[9] decoded_imm[9] $abc$16053$new_n2012 $abc$16053$new_n2019 $abc$16053$new_n2172 +0010 1 +0100 1 +1000 1 +1110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2174 $abc$16053$new_n2176 $abc$16053$new_n2173 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2175 pcpi_rs1[8] pcpi_rs1[10] $abc$16053$new_n2174 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[13] $abc$16053$new_n2175 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2177 $abc$16053$new_n2032 reg_pc[9] $abc$16053$new_n2176 +1000 1 +1001 1 +1010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] $abc$16053$new_n2177 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2179 pcpi_rs1[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14965 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2181 $abc$16053$new_n2183 $abc$16053$new_n2180 $abc$16053$new_n2019 $abc$16053$new_n2179 +0000 1 +0001 1 +0011 1 +.names pcpi_rs1[8] decoded_imm[8] pcpi_rs1[7] decoded_imm[7] $abc$16053$new_n2013 $abc$16053$new_n2180 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2182 reg_pc[8] $abc$16053$new_n2032 $abc$16053$new_n2181 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] $abc$16053$new_n2182 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2184 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[12] $abc$16053$new_n2183 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[7] pcpi_rs1[9] $abc$16053$new_n2184 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 $abc$16053$new_n2189 pcpi_rs1[6] pcpi_rs1[8] $abc$16053$new_n2188 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[11] $abc$16053$new_n2189 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2191 $abc$16053$new_n2032 reg_pc[7] $abc$16053$new_n2190 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] $abc$16053$new_n2191 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2193 pcpi_rs1[6] $abc$16053$new_n2197 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$16053$new_n2194 $abc$16053$new_n2196 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[6] $abc$16053$new_n2193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2195 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[2] pcpi_rs1[10] $abc$16053$new_n2194 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[5] pcpi_rs1[7] $abc$16053$new_n2195 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] $abc$16053$new_n2196 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[6] decoded_imm[6] pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2197 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2199 pcpi_rs1[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14971 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2200 pcpi_rs1[5] decoded_imm[5] $abc$16053$new_n2014 $abc$16053$new_n2019 $abc$16053$new_n2199 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2201 $abc$16053$new_n2203 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[5] $abc$16053$new_n2200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$16053$new_n2202 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[4] pcpi_rs1[6] $abc$16053$new_n2201 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[1] pcpi_rs1[9] $abc$16053$new_n2202 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] $abc$16053$new_n2203 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2205 pcpi_rs1[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$14973 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2206 $abc$16053$new_n2210 $abc$16053$new_n2208 $abc$16053$new_n2205 +00010 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2207 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[0] pcpi_rs1[8] $abc$16053$new_n2206 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[3] pcpi_rs1[5] $abc$16053$new_n2207 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2209 $abc$16053$new_n2032 reg_pc[4] $abc$16053$new_n2208 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] $abc$16053$new_n2209 +1001 1 +1011 1 +1110 1 +1111 1 +.names pcpi_rs1[4] decoded_imm[4] pcpi_rs1[3] decoded_imm[3] $abc$16053$new_n2015 $abc$16053$new_n2210 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2213 reg_pc[3] $abc$16053$new_n2032 $abc$16053$new_n2212 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] $abc$16053$new_n2213 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2218 pcpi_rs1[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$14977 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2222 $abc$16053$new_n2221 $abc$16053$new_n2219 $abc$16053$new_n2218 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2220 $abc$16053$new_n2032 reg_pc[2] $abc$16053$new_n2219 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] $abc$16053$new_n2220 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[3] pcpi_rs1[6] $abc$16053$new_n2221 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs1[2] decoded_imm[2] $abc$16053$new_n2016 $abc$16053$new_n2222 +000 1 +011 1 +101 1 +110 1 +.names $abc$16053$new_n2226 $abc$16053$new_n2227 $abc$16053$new_n2018 $abc$16053$new_n2032 reg_pc[1] $abc$16053$new_n2225 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names pcpi_rs1[1] decoded_imm[1] $abc$16053$new_n2019 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2226 +00011 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +11011 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] $abc$16053$new_n2227 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2230 $abc$16053$new_n2033 pcpi_rs1[0] decoded_imm[0] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14981 +00100 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2232 $abc$16053$new_n2231 reg_pc[0] $abc$16053$new_n2032 $abc$16053$new_n2230 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$16053$new_n2018 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] $abc$16053$new_n2231 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[1] pcpi_rs1[4] $abc$16053$new_n2232 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[30] reg_out[30] reg_next_pc[30] mem_la_addr[30] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[30] mem_addr[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14983 +001 1 +011 1 +110 1 +111 1 +.names trap mem_la_read mem_la_write $abc$16053$new_n2235 +001 1 +010 1 +011 1 +.names resetn $abc$16053$new_n1469 mem_la_read +11 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[29] reg_out[29] reg_next_pc[29] mem_la_addr[29] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[29] mem_addr[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14985 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[28] reg_out[28] reg_next_pc[28] mem_la_addr[28] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[28] mem_addr[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14987 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[27] reg_out[27] reg_next_pc[27] mem_la_addr[27] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[27] mem_addr[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14989 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[26] reg_out[26] reg_next_pc[26] mem_la_addr[26] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[26] mem_addr[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14991 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[25] reg_out[25] reg_next_pc[25] mem_la_addr[25] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[25] mem_addr[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14993 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[24] reg_out[24] reg_next_pc[24] mem_la_addr[24] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[24] mem_addr[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14995 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[23] reg_out[23] reg_next_pc[23] mem_la_addr[23] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[23] mem_addr[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14997 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[22] reg_out[22] reg_next_pc[22] mem_la_addr[22] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[22] mem_addr[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14999 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[21] reg_out[21] reg_next_pc[21] mem_la_addr[21] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[21] mem_addr[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$15001 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[20] reg_out[20] reg_next_pc[20] mem_la_addr[20] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[20] mem_addr[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$15003 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[19] reg_out[19] reg_next_pc[19] mem_la_addr[19] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[19] mem_addr[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$15005 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[18] reg_out[18] reg_next_pc[18] mem_la_addr[18] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[18] mem_addr[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$15007 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[17] reg_out[17] reg_next_pc[17] mem_la_addr[17] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[17] mem_addr[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$15009 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[16] reg_out[16] reg_next_pc[16] mem_la_addr[16] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[16] mem_addr[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$15011 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[15] reg_out[15] reg_next_pc[15] mem_la_addr[15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[15] mem_addr[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$15013 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[14] reg_out[14] reg_next_pc[14] mem_la_addr[14] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[14] mem_addr[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$15015 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[13] reg_out[13] reg_next_pc[13] mem_la_addr[13] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[13] mem_addr[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$15017 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[12] reg_out[12] reg_next_pc[12] mem_la_addr[12] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[12] mem_addr[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15019 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[11] reg_out[11] reg_next_pc[11] mem_la_addr[11] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[11] mem_addr[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$15021 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[10] reg_out[10] reg_next_pc[10] mem_la_addr[10] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[10] mem_addr[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$15023 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[9] reg_out[9] reg_next_pc[9] mem_la_addr[9] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[9] mem_addr[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$15025 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[8] reg_out[8] reg_next_pc[8] mem_la_addr[8] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[8] mem_addr[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$15027 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[7] reg_out[7] reg_next_pc[7] mem_la_addr[7] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[7] mem_addr[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$15029 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[6] reg_out[6] reg_next_pc[6] mem_la_addr[6] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[6] mem_addr[6] $abc$16053$auto$rtlil.cc:2693:MuxGate$15031 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[5] reg_out[5] reg_next_pc[5] mem_la_addr[5] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[5] mem_addr[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$15033 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[4] reg_out[4] reg_next_pc[4] mem_la_addr[4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[4] mem_addr[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15035 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[3] reg_out[3] reg_next_pc[3] mem_la_addr[3] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[3] mem_addr[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$15037 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[2] reg_out[2] reg_next_pc[2] mem_la_addr[2] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[2] mem_addr[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15039 +001 1 +011 1 +110 1 +111 1 +.names mem_wordsize[0] mem_wordsize[1] pcpi_rs2[31] mem_la_wdata[7] pcpi_rs2[15] mem_la_wdata[31] +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1410 mem_la_wdata[31] mem_wdata[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15045 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_instr mem_do_wdata $abc$16053$new_n1470 $abc$16053$auto$rtlil.cc:2693:MuxGate$15049 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$16053$new_n1548 is_alu_reg_reg $abc$16053$new_n2299 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15051 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2298 mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2297 +100 1 +.names mem_rdata_latched[0] mem_rdata_latched[1] $abc$16053$new_n2298 +11 1 +.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2299 +10 1 +.names $abc$16053$new_n1548 is_alu_reg_imm $abc$16053$new_n2301 $abc$16053$new_n2297 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15053 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_latched[5] mem_rdata_latched[6] $abc$16053$new_n2301 +00 1 +.names $abc$16053$new_n1479 is_sll_srl_sra $abc$16053$new_n2303 is_alu_reg_reg $abc$16053$auto$rtlil.cc:2693:MuxGate$15055 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n2306 $abc$16053$new_n2304 mem_rdata_q[30] mem_rdata_q[14] $abc$16053$new_n2303 +1100 1 +1101 1 +1111 1 +.names $abc$16053$new_n2305 mem_rdata_q[31] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2304 +10000 1 +.names mem_rdata_q[28] mem_rdata_q[29] $abc$16053$new_n2305 +00 1 +.names mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2306 +10 1 +.names $abc$16053$new_n1548 is_sb_sh_sw $abc$16053$new_n2297 $abc$16053$new_n2299 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15057 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n1479 instr_jalr is_jalr_addi_slti_sltiu_xori_ori_andi is_alu_reg_imm $abc$16053$new_n2306 $abc$16053$auto$rtlil.cc:2693:MuxGate$15059 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1479 is_slli_srli_srai $abc$16053$new_n2303 is_alu_reg_imm $abc$16053$auto$rtlil.cc:2693:MuxGate$15061 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2297 $abc$16053$new_n2301 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15063 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n1479 $abc$16053$new_n2312 decoded_imm[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15065 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1478 $abc$16053$new_n1480 mem_rdata_q[31] decoded_imm_j[31] instr_jal $abc$16053$new_n2312 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n1548 mem_rdata_latched[11] decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15067 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2322 $abc$16053$new_n2315 instr_rdinstrh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15069 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2316 mem_rdata_q[21] mem_rdata_q[20] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2315 +11000 1 +.names $abc$16053$new_n2321 $abc$16053$new_n2320 $abc$16053$new_n1479 $abc$16053$new_n2318 $abc$16053$new_n2317 $abc$16053$new_n2316 +11111 1 +.names $abc$16053$new_n2305 mem_rdata_q[30] mem_rdata_q[17] mem_rdata_q[18] mem_rdata_q[19] $abc$16053$new_n2317 +11000 1 +.names mem_rdata_q[31] mem_rdata_q[4] $abc$16053$new_n2319 mem_rdata_q[2] mem_rdata_q[3] $abc$16053$new_n2318 +11100 1 +.names mem_rdata_q[5] mem_rdata_q[6] mem_rdata_q[15] mem_rdata_q[16] $abc$16053$new_n2319 +1100 1 +.names mem_rdata_q[13] mem_rdata_q[12] mem_rdata_q[14] $abc$16053$new_n2320 +100 1 +.names mem_rdata_q[0] mem_rdata_q[1] $abc$16053$new_n2321 +11 1 +.names mem_rdata_q[27] mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] $abc$16053$new_n2322 +1000 1 +.names $abc$16053$new_n2324 $abc$16053$new_n2315 instr_rdinstr $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15071 +0010 1 +0110 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names mem_rdata_q[24] mem_rdata_q[25] mem_rdata_q[26] mem_rdata_q[27] $abc$16053$new_n2324 +0000 1 +.names $abc$16053$new_n2326 instr_rdcycleh $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15073 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2316 $abc$16053$new_n2322 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2326 +11000 1 +.names $abc$16053$new_n2328 instr_rdcycle $abc$16053$new_n1479 $abc$16053$auto$rtlil.cc:2693:MuxGate$15075 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2316 $abc$16053$new_n2324 mem_rdata_q[21] mem_rdata_q[22] mem_rdata_q[23] $abc$16053$new_n2328 +11000 1 +.names $abc$16053$new_n1479 instr_srai $abc$16053$new_n2331 is_alu_reg_imm $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15077 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_q[30] $abc$16053$new_n1479 $abc$16053$new_n2304 $abc$16053$new_n2330 +111 1 +.names mem_rdata_q[14] $abc$16053$new_n2306 $abc$16053$new_n2331 +11 1 +.names $abc$16053$new_n1479 instr_srli is_alu_reg_imm $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15079 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2304 mem_rdata_q[30] $abc$16053$new_n2333 +10 1 +.names $abc$16053$new_n1479 instr_slli is_alu_reg_imm $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15081 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n2306 mem_rdata_q[14] $abc$16053$new_n2335 +10 1 +.names $abc$16053$new_n1479 instr_sw is_sb_sh_sw $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15083 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sh $abc$16053$new_n2335 is_sb_sh_sw $abc$16053$auto$rtlil.cc:2693:MuxGate$15085 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sb is_sb_sh_sw $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15087 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2339 +000 1 +.names $abc$16053$new_n1479 instr_lhu $abc$16053$new_n2331 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15089 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lbu is_lb_lh_lw_lbu_lhu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15091 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[14] mem_rdata_q[12] mem_rdata_q[13] $abc$16053$new_n2342 +100 1 +.names $abc$16053$new_n1479 instr_lw is_lb_lh_lw_lbu_lhu $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15093 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lh $abc$16053$new_n2335 is_lb_lh_lw_lbu_lhu $abc$16053$auto$rtlil.cc:2693:MuxGate$15095 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_lb is_lb_lh_lw_lbu_lhu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15097 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 instr_jalr $abc$16053$new_n2347 $abc$16053$new_n2349 mem_rdata_latched[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$15099 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$16053$new_n2348 mem_rdata_latched[13] mem_rdata_latched[14] $abc$16053$new_n2347 +100 1 +.names mem_rdata_latched[6] mem_rdata_latched[5] mem_rdata_latched[4] $abc$16053$new_n2348 +110 1 +.names mem_rdata_latched[2] $abc$16053$new_n2298 mem_rdata_latched[3] $abc$16053$new_n2349 +110 1 +.names $abc$16053$new_n1548 instr_jal $abc$16053$new_n2348 $abc$16053$new_n2298 $abc$16053$new_n2351 $abc$16053$auto$rtlil.cc:2693:MuxGate$15101 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_latched[2] mem_rdata_latched[3] $abc$16053$new_n2351 +11 1 +.names $abc$16053$new_n1548 instr_auipc $abc$16053$new_n2301 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15103 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1548 instr_lui $abc$16053$new_n2299 $abc$16053$new_n2349 mem_rdata_latched[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15105 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1619 $abc$16053$new_n1623 pcpi_rs2[31] decoded_imm[31] $abc$16053$new_n2355 $abc$16053$auto$rtlil.cc:2693:MuxGate$15107 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$auto$mem.cc:1172:emulate_transparency$4913 $abc$16053$new_n1626 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] $abc$16053$new_n2355 +0001 1 +0011 1 +1010 1 +1011 1 +.names pcpi_rs1[29] decoded_imm[29] pcpi_rs1[30] decoded_imm[30] $abc$16053$new_n2002 $abc$16053$new_n2358 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2362 $abc$16053$new_n2361 $abc$16053$new_n2022 $abc$16053$new_n2032 reg_pc[31] $abc$16053$new_n2360 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] $abc$16053$new_n2361 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[30] pcpi_rs1[27] $abc$16053$new_n2362 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n2365 pcpi_rs1[30] $abc$16053$new_n2364 $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$15111 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names pcpi_rs1[30] decoded_imm[30] pcpi_rs1[29] decoded_imm[29] $abc$16053$new_n2002 $abc$16053$new_n2364 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2366 $abc$16053$new_n2368 $abc$16053$new_n2369 $abc$16053$new_n2365 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2367 $abc$16053$new_n2032 reg_pc[30] $abc$16053$new_n2366 +000 1 +001 1 +010 1 +.names $abc$16053$new_n2030 $abc$16053$auto$mem.cc:1172:emulate_transparency$4923 $abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] $abc$16053$new_n2367 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[29] pcpi_rs1[31] $abc$16053$new_n2368 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n2028 $abc$16053$new_n2025 pcpi_rs1[26] $abc$16053$new_n2369 +100 1 +101 1 +110 1 +.names count_instr[63] count_instr[62] $abc$16053$new_n1909 $abc$16053$auto$rtlil.cc:2693:MuxGate$15113 +011 1 +100 1 +101 1 +110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n2372 reg_pc[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15115 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n1704 $abc$16053$new_n2373 reg_next_pc[31] $abc$16053$new_n2372 +000 1 +010 1 +110 1 +111 1 +.names latched_stalu alu_out_q[31] reg_out[31] $abc$16053$new_n2373 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n2378 reg_next_pc[31] $abc$16053$new_n2375 $abc$16053$new_n2377 $abc$16053$auto$rtlil.cc:2693:MuxGate$15117 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names instr_jal $abc$16053$new_n2376 $abc$16053$new_n1750 decoded_imm_j[30] $abc$16053$new_n1751 $abc$16053$new_n2375 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names decoded_imm_j[31] $abc$16053$new_n2372 $abc$16053$new_n2376 +01 1 +10 1 +.names $abc$16053$new_n2372 instr_jal $abc$16053$new_n1690 $abc$16053$new_n1750 decoder_trigger $abc$16053$new_n2377 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2372 decoder_trigger $abc$16053$new_n2378 +10 1 +.names mem_do_prefetch resetn $abc$16053$new_n2380 $abc$16053$new_n1612 instr_jalr $abc$16053$auto$rtlil.cc:2693:MuxGate$15119 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names decoder_trigger instr_jal $abc$16053$new_n2380 +10 1 +.names $abc$16053$new_n2399 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$new_n2382 mem_do_rinst $abc$16053$auto$rtlil.cc:2693:MuxGate$15121 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n2022 $abc$16053$new_n1621 mem_do_prefetch $abc$16053$new_n2383 $abc$16053$new_n2398 $abc$16053$new_n2382 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1622 $abc$16053$new_n2384 $abc$16053$new_n2380 $abc$16053$new_n2383 +000 1 +010 1 +110 1 +111 1 +.names $abc$16053$new_n2385 mem_do_prefetch is_lb_lh_lw_lbu_lhu $abc$16053$new_n2398 $abc$16053$new_n2384 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1624 $abc$16053$new_n2394 is_slli_srli_srai $abc$16053$new_n2386 $abc$16053$new_n2385 +1100 1 +.names $abc$16053$new_n2397 $abc$16053$new_n2396 $abc$16053$new_n2387 $0\is_lui_auipc_jal[0:0] $abc$16053$new_n2386 +1110 1 +.names $abc$16053$new_n2394 $abc$16053$new_n2393 $abc$16053$new_n2391 $abc$16053$new_n2389 $abc$16053$new_n2388 $abc$16053$new_n2387 +11111 1 +.names $abc$16053$new_n2025 instr_lb instr_lbu instr_sh instr_sw $abc$16053$new_n2388 +10000 1 +.names $abc$16053$new_n2390 instr_fence instr_xor instr_sub instr_add $abc$16053$new_n2389 +10000 1 +.names instr_xori instr_addi instr_bgeu instr_bltu $abc$16053$new_n2390 +0000 1 +.names $abc$16053$new_n2392 instr_bge instr_blt instr_bne instr_beq $abc$16053$new_n2391 +10000 1 +.names instr_sll instr_jalr instr_sb instr_slli $abc$16053$new_n2392 +0000 1 +.names instr_and instr_or instr_andi instr_ori $abc$16053$new_n2393 +0000 1 +.names instr_rdcycle instr_rdcycleh instr_rdinstr instr_rdinstrh $abc$16053$new_n2394 +0000 1 +.names $abc$16053$new_n1478 instr_jal $0\is_lui_auipc_jal[0:0] +00 1 +01 1 +11 1 +.names instr_sltu instr_slt instr_sltiu instr_slti $abc$16053$new_n2396 +0000 1 +.names instr_lh instr_lw instr_lhu $abc$16053$new_n2397 +000 1 +.names is_sll_srl_sra mem_do_rinst mem_do_prefetch is_sb_sh_sw $abc$16053$new_n2398 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2038 $abc$16053$new_n1621 $abc$16053$new_n2400 $abc$16053$new_n2022 $abc$16053$new_n2399 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1624 $abc$16053$new_n2385 resetn $abc$16053$new_n1612 $abc$16053$new_n2400 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names resetn $abc$16053$new_n1549 $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] +00 1 +01 1 +10 1 +.names mem_do_rdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15123 +10 1 +.names mem_do_wdata $abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] $abc$16053$auto$rtlil.cc:2693:MuxGate$15125 +10 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2452 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$auto$rtlil.cc:2693:MuxGate$15127 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2450 instr_bgeu $abc$16053$new_n2406 is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2405 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instr_bge instr_bne $abc$16053$new_n2448 $abc$16053$new_n2407 $abc$16053$new_n2406 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$16053$new_n2408 pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2407 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$16053$new_n2444 $abc$16053$new_n2929 $abc$16053$new_n2440 $abc$16053$new_n2408 +000 1 +001 1 +010 1 +.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2416 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2424 $abc$16053$new_n2416 $abc$16053$new_n2423 $abc$16053$new_n2422 $abc$16053$new_n2419 $abc$16053$new_n2418 +11111 1 +.names $abc$16053$new_n2420 pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2419 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n2421 pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2420 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2421 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2422 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2423 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2424 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2438 $abc$16053$new_n2436 $abc$16053$new_n2435 +11 1 +.names $abc$16053$new_n2437 pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2436 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2437 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2439 pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2438 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2439 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2441 pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2440 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2441 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$16053$new_n2443 pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2442 +10000 1 +10011 1 +11100 1 +11111 1 +.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2443 +0000 1 +0011 1 +1100 1 +1111 1 +.names pcpi_rs1[31] pcpi_rs2[31] pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2445 $abc$16053$new_n2444 +00001 1 +00010 1 +00011 1 +00111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2445 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$16053$new_n2440 $abc$16053$new_n2449 $abc$16053$new_n2435 $abc$16053$new_n2418 $abc$16053$new_n2448 +1111 1 +.names $abc$16053$new_n2442 pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2449 +10000 1 +10011 1 +11100 1 +11111 1 +.names is_sltiu_bltu_sltu is_slti_blt_slt $abc$16053$new_n2451 $abc$16053$new_n2407 instr_bgeu $abc$16053$new_n2450 +00001 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2408 pcpi_rs2[31] pcpi_rs1[31] $abc$16053$new_n2451 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$16053$new_n1622 latched_store $abc$16053$new_n2453 $abc$16053$new_n2394 $abc$16053$new_n1612 $abc$16053$new_n2452 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2454 $abc$16053$new_n1610 $abc$16053$new_n2453 +10 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2454 +00 1 +.names $abc$16053$new_n1612 latched_stalu $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$auto$rtlil.cc:2693:MuxGate$15129 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n1610 $abc$16053$new_n1612 $abc$16053$new_n2458 $abc$16053$new_n2457 latched_branch $abc$16053$auto$rtlil.cc:2693:MuxGate$15131 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2405 $abc$16053$new_n2457 +10 1 +.names $abc$16053$new_n1610 instr_jalr is_beq_bne_blt_bge_bltu_bgeu decoder_trigger instr_jal $abc$16053$new_n2458 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2460 instr_lh latched_is_lh $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15133 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2021 mem_do_rdata $abc$16053$new_n2035 $abc$16053$new_n2460 +100 1 +.names $abc$16053$new_n2460 instr_lb latched_is_lb $abc$16053$new_n1612 $abc$16053$auto$rtlil.cc:2693:MuxGate$15135 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1479 instr_beq is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15137 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bne is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2335 $abc$16053$auto$rtlil.cc:2693:MuxGate$15139 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_blt is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15141 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bge is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2331 $abc$16053$auto$rtlil.cc:2693:MuxGate$15143 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_bltu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15145 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[14] mem_rdata_q[13] mem_rdata_q[12] $abc$16053$new_n2467 +110 1 +.names $abc$16053$new_n1479 instr_bgeu is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15147 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2469 +111 1 +.names $abc$16053$new_n1479 instr_addi is_alu_reg_imm $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15149 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_slti is_alu_reg_imm $abc$16053$new_n2320 $abc$16053$auto$rtlil.cc:2693:MuxGate$15151 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_sltiu is_alu_reg_imm $abc$16053$new_n2473 $abc$16053$auto$rtlil.cc:2693:MuxGate$15153 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names mem_rdata_q[12] mem_rdata_q[13] mem_rdata_q[14] $abc$16053$new_n2473 +110 1 +.names $abc$16053$new_n1479 instr_xori is_alu_reg_imm $abc$16053$new_n2342 $abc$16053$auto$rtlil.cc:2693:MuxGate$15155 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_ori is_alu_reg_imm $abc$16053$new_n2467 $abc$16053$auto$rtlil.cc:2693:MuxGate$15157 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_andi is_alu_reg_imm $abc$16053$new_n2469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15159 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1479 instr_add is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15161 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sub $abc$16053$new_n2330 is_alu_reg_reg $abc$16053$new_n2339 $abc$16053$auto$rtlil.cc:2693:MuxGate$15163 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sll is_alu_reg_reg $abc$16053$new_n2335 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15165 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_slt is_alu_reg_reg $abc$16053$new_n2320 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15167 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sltu is_alu_reg_reg $abc$16053$new_n2473 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15169 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_xor is_alu_reg_reg $abc$16053$new_n2342 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15171 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_srl is_alu_reg_reg $abc$16053$new_n2331 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15173 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_sra $abc$16053$new_n2331 is_alu_reg_reg $abc$16053$new_n2330 $abc$16053$auto$rtlil.cc:2693:MuxGate$15175 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_or is_alu_reg_reg $abc$16053$new_n2467 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15177 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_and is_alu_reg_reg $abc$16053$new_n2469 $abc$16053$new_n2333 $abc$16053$auto$rtlil.cc:2693:MuxGate$15179 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names $abc$16053$new_n1479 instr_fence $abc$16053$new_n2339 $abc$16053$new_n2321 $abc$16053$new_n2488 $abc$16053$auto$rtlil.cc:2693:MuxGate$15181 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11111 1 +.names mem_rdata_q[2] mem_rdata_q[3] mem_rdata_q[4] mem_rdata_q[5] mem_rdata_q[6] $abc$16053$new_n2488 +11000 1 +.names $abc$16053$new_n1548 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n2348 $abc$16053$new_n2297 $abc$16053$auto$rtlil.cc:2693:MuxGate$15183 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[31] decoded_imm_j[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15185 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_valid $abc$16053$new_n2492 $abc$16053$new_n1468 $abc$16053$auto$rtlil.cc:2693:MuxGate$15189 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1473 $abc$16053$new_n1474 resetn mem_ready $abc$16053$new_n2492 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$16053$new_n1467 $abc$16053$new_n1475 mem_state[1] mem_state[0] mem_do_wdata $abc$16053$auto$rtlil.cc:2693:MuxGate$15193 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2495 $abc$16053$new_n2498 mem_wordsize[1] $abc$16053$new_n2397 $abc$16053$new_n2021 $abc$16053$auto$rtlil.cc:2693:MuxGate$15197 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2501 $abc$16053$new_n2034 $abc$16053$new_n2496 $abc$16053$new_n2495 +111 1 +.names $abc$16053$new_n2498 instr_sb $abc$16053$new_n2500 $abc$16053$new_n2460 $abc$16053$new_n2496 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names mem_do_wdata $abc$16053$new_n2035 $abc$16053$new_n2497 +00 1 +.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2498 +10 1 +.names $abc$16053$new_n2020 instr_sw $abc$16053$new_n2499 +10 1 +.names $abc$16053$new_n2397 instr_lb instr_lbu $abc$16053$new_n2500 +100 1 +.names resetn $abc$16053$new_n1612 $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$new_n2501 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1609 latched_rd[4] $abc$16053$new_n1612 decoded_rd[4] $abc$16053$auto$rtlil.cc:2693:MuxGate$15201 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$16053$new_n1470 $abc$16053$new_n1704 pcpi_rs1[31] reg_out[31] reg_next_pc[31] mem_la_addr[31] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2235 mem_la_addr[31] mem_addr[31] $abc$16053$auto$rtlil.cc:2693:MuxGate$15203 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2495 $abc$16053$new_n2506 mem_wordsize[0] $abc$16053$auto$rtlil.cc:2693:MuxGate$15207 +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2499 instr_sh $abc$16053$new_n2021 instr_lw $abc$16053$new_n2397 $abc$16053$new_n2506 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n2235 mem_wstrb[2] mem_la_wstrb[2] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14331 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[2] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2235 mem_wstrb[1] mem_la_wstrb[1] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14333 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[1] +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2513 $abc$16053$new_n1442 $abc$16053$new_n2512 +00 1 +.names mem_wordsize[0] pcpi_rs1[1] mem_wordsize[1] $abc$16053$new_n2513 +110 1 +.names $abc$16053$new_n2235 mem_wstrb[0] mem_la_wstrb[0] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$14335 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$16053$new_n2512 pcpi_rs1[0] pcpi_rs1[1] mem_la_wstrb[0] +000 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2235 mem_wstrb[3] mem_la_wstrb[3] $abc$16053$new_n1469 $abc$16053$auto$rtlil.cc:2693:MuxGate$15043 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names mem_wordsize[1] mem_wordsize[0] pcpi_rs1[1] pcpi_rs1[0] mem_la_wstrb[3] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instr_slt instr_slti instr_blt $0\is_slti_blt_slt[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names instr_sltu instr_sltiu instr_bltu $0\is_sltiu_bltu_sltu[0:0] +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2396 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y +00 1 +01 1 +11 1 +.names resetn $abc$16053$new_n2019 $abc$16053$new_n2035 $abc$16053$auto$opt_dff.cc:253:combine_resets$4218 +100 1 +.names cpu_state[7] $abc$16053$new_n1613 cpu_state[6] cpu_state[4] cpu_state[5] $abc$16053$procmux$1608_CMP +11000 1 +.names resetn $abc$16053$new_n1479 $abc$16053$auto$opt_dff.cc:253:combine_resets$4160 +00 1 +01 1 +11 1 +.names resetn $abc$16053$new_n1612 $abc$16053$new_n2527 latched_store latched_branch $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +11001 1 +11010 1 +11011 1 +.names latched_rd[4] latched_rd[0] latched_rd[1] latched_rd[2] latched_rd[3] $abc$16053$new_n2527 +00000 1 +.names mem_do_prefetch $abc$16053$new_n1549 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y +00 1 +.names resetn mem_do_rinst reg_pc[1] reg_pc[0] $abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2022 reg_sh[0] $abc$16053$new_n2027 $abc$16053$new_n2531 $0\reg_sh[4:0][0] +0000 1 +0010 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2532 decoded_rs2[0] $abc$16053$new_n1686 $abc$16053$new_n2531 +000 1 +010 1 +100 1 +101 1 +.names is_slli_srli_srai $abc$16053$new_n1621 $abc$16053$new_n2532 +10 1 +.names $abc$16053$new_n2022 reg_sh[1] $abc$16053$new_n2027 reg_sh[0] $abc$16053$new_n2534 $0\reg_sh[4:0][1] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2532 decoded_rs2[1] $abc$16053$new_n1684 $abc$16053$new_n2534 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2536 $abc$16053$new_n2038 reg_sh[2] $abc$16053$new_n2027 $0\reg_sh[4:0][2] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[2] $abc$16053$new_n1682 $abc$16053$new_n2536 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2538 reg_sh[3] reg_sh[2] $abc$16053$new_n2038 reg_sh[4] $0\reg_sh[4:0][3] +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[3] $abc$16053$new_n1680 $abc$16053$new_n2538 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2540 reg_sh[4] $abc$16053$new_n2038 reg_sh[2] reg_sh[3] $0\reg_sh[4:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2532 $abc$16053$new_n2022 decoded_rs2[4] $abc$16053$new_n1678 $abc$16053$new_n2540 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2542 $abc$16053$new_n2546 pcpi_rs1[0] $0\reg_out[31:0][0] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2543 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[16] mem_rdata[0] $abc$16053$new_n2542 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2544 mem_rdata[0] mem_la_wstrb[0] mem_rdata[24] $abc$16053$new_n2545 $abc$16053$new_n2543 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[16] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[8] $abc$16053$new_n2544 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names pcpi_rs1[0] pcpi_rs1[1] $abc$16053$new_n2545 +11 1 +.names $abc$16053$new_n1610 reg_pc[0] decoded_imm[0] $abc$16053$new_n2547 $abc$16053$new_n2546 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instr_rdinstrh instr_rdinstr count_instr[32] $abc$16053$new_n2548 count_instr[0] $abc$16053$new_n2547 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[32] count_cycle[0] $abc$16053$new_n2548 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1610 reg_pc[1] decoded_imm[1] $abc$16053$new_n2556 $abc$16053$new_n2554 $abc$16053$new_n2553 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instr_rdinstrh instr_rdinstr count_instr[33] $abc$16053$new_n2555 count_instr[1] $abc$16053$new_n2554 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[33] count_cycle[1] $abc$16053$new_n2555 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[0] decoded_imm[0] $abc$16053$new_n2556 +11 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2559 $abc$16053$new_n2562 pcpi_rs1[2] $0\reg_out[31:0][2] +00000 1 +00001 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2560 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[18] mem_rdata[2] $abc$16053$new_n2559 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2561 mem_rdata[2] mem_la_wstrb[0] mem_rdata[26] $abc$16053$new_n2545 $abc$16053$new_n2560 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[18] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[10] $abc$16053$new_n2561 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2563 $abc$16053$new_n2562 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names instr_rdinstrh instr_rdinstr count_instr[34] $abc$16053$new_n2564 count_instr[2] $abc$16053$new_n2563 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[34] count_cycle[2] $abc$16053$new_n2564 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[0] decoded_imm[0] reg_pc[1] decoded_imm[1] $abc$16053$new_n2565 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2568 $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[19] mem_rdata[3] $abc$16053$new_n2567 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2569 mem_rdata[3] mem_la_wstrb[0] mem_rdata[27] $abc$16053$new_n2545 $abc$16053$new_n2568 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[19] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[11] $abc$16053$new_n2569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names reg_pc[3] decoded_imm[3] reg_pc[2] decoded_imm[2] $abc$16053$new_n2565 $abc$16053$new_n2571 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2575 $abc$16053$new_n2578 $abc$16053$new_n2512 mem_rdata[4] $0\reg_out[31:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2576 $abc$16053$new_n2513 mem_rdata[20] $abc$16053$new_n2575 +000 1 +001 1 +011 1 +.names $abc$16053$new_n2577 mem_rdata[4] mem_la_wstrb[0] mem_rdata[28] $abc$16053$new_n2545 $abc$16053$new_n2576 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names pcpi_rs1[1] mem_rdata[20] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[12] $abc$16053$new_n2577 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n1610 pcpi_rs1[4] $abc$16053$new_n2579 $abc$16053$new_n2581 $abc$16053$new_n2578 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2579 +000 1 +011 1 +101 1 +110 1 +.names reg_pc[2] decoded_imm[2] reg_pc[3] decoded_imm[3] $abc$16053$new_n2565 $abc$16053$new_n2580 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[36] $abc$16053$new_n2582 count_instr[4] $abc$16053$new_n2581 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[36] count_cycle[4] $abc$16053$new_n2582 +000 1 +010 1 +100 1 +101 1 +.names reg_pc[5] decoded_imm[5] reg_pc[4] decoded_imm[4] $abc$16053$new_n2580 $abc$16053$new_n2585 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names pcpi_rs1[0] pcpi_rs1[1] mem_rdata[29] mem_rdata[13] $abc$16053$new_n2590 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$16053$new_n1610 reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2593 $0\reg_out[31:0][6] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2594 $abc$16053$new_n2598 $abc$16053$new_n2453 $abc$16053$new_n2022 pcpi_rs1[6] $abc$16053$new_n2593 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$16053$new_n2595 mem_la_wstrb[0] $abc$16053$new_n2596 mem_rdata[6] $abc$16053$new_n2594 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2513 mem_rdata[22] $abc$16053$new_n2595 +100 1 +101 1 +111 1 +.names $abc$16053$new_n2597 $abc$16053$new_n2545 mem_rdata[30] $abc$16053$new_n2596 +100 1 +101 1 +110 1 +.names pcpi_rs1[1] mem_rdata[22] pcpi_rs1[0] $abc$16053$new_n1442 mem_rdata[14] $abc$16053$new_n2597 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names instr_rdinstrh instr_rdinstr count_instr[38] $abc$16053$new_n2599 count_instr[6] $abc$16053$new_n2598 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[38] count_cycle[6] $abc$16053$new_n2599 +001 1 +011 1 +110 1 +111 1 +.names reg_pc[4] decoded_imm[4] reg_pc[5] decoded_imm[5] $abc$16053$new_n2580 $abc$16053$new_n2600 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2021 $abc$16053$new_n2606 pcpi_rs1[7] $abc$16053$new_n2602 $0\reg_out[31:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2604 $abc$16053$new_n2602 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[6] decoded_imm[6] $abc$16053$new_n2600 $abc$16053$new_n2603 +000 1 +001 1 +011 1 +101 1 +.names instr_rdinstrh instr_rdinstr count_instr[39] $abc$16053$new_n2605 count_instr[7] $abc$16053$new_n2604 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[39] count_cycle[7] $abc$16053$new_n2605 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n2607 mem_rdata[23] mem_rdata[7] $abc$16053$new_n2606 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2608 pcpi_rs1[1] pcpi_rs1[0] mem_rdata[15] mem_rdata[31] $abc$16053$new_n2607 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names pcpi_rs1[1] pcpi_rs1[0] mem_rdata[23] mem_rdata[7] $abc$16053$new_n2608 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2613 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[8] $abc$16053$new_n2611 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2606 latched_is_lb $abc$16053$new_n2612 +100 1 +110 1 +111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[24] mem_rdata[8] $abc$16053$new_n2613 +1001 1 +1011 1 +1110 1 +1111 1 +.names latched_is_lb $abc$16053$new_n1442 $abc$16053$new_n2614 +00 1 +.names reg_pc[7] decoded_imm[7] $abc$16053$new_n2603 $abc$16053$new_n2617 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2623 $abc$16053$new_n2619 $abc$16053$new_n2021 pcpi_rs1[9] $0\reg_out[31:0][9] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2621 $abc$16053$new_n2619 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[7] decoded_imm[7] reg_pc[8] decoded_imm[8] $abc$16053$new_n2603 $abc$16053$new_n2620 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[41] $abc$16053$new_n2622 count_instr[9] $abc$16053$new_n2621 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[41] count_cycle[9] $abc$16053$new_n2622 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[25] mem_rdata[9] $abc$16053$new_n2623 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n2626 $abc$16053$new_n1610 $abc$16053$new_n2625 $abc$16053$new_n2453 $abc$16053$new_n2628 $0\reg_out[31:0][10] +00010 1 +00110 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[10] decoded_imm[10] reg_pc[9] decoded_imm[9] $abc$16053$new_n2620 $abc$16053$new_n2625 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2627 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[10] $abc$16053$new_n2626 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[26] mem_rdata[10] $abc$16053$new_n2627 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[42] $abc$16053$new_n2629 count_instr[10] $abc$16053$new_n2628 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[42] count_cycle[10] $abc$16053$new_n2629 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2635 $abc$16053$new_n2021 $abc$16053$new_n2631 pcpi_rs1[11] $0\reg_out[31:0][11] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2633 $abc$16053$new_n2631 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[9] decoded_imm[9] reg_pc[10] decoded_imm[10] $abc$16053$new_n2620 $abc$16053$new_n2632 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[43] $abc$16053$new_n2634 count_instr[11] $abc$16053$new_n2633 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdcycleh count_cycle[43] count_cycle[11] $abc$16053$new_n2634 +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[27] mem_rdata[11] $abc$16053$new_n2635 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n2638 $abc$16053$new_n1610 $abc$16053$new_n2637 $abc$16053$new_n2453 $abc$16053$new_n2640 $0\reg_out[31:0][12] +00010 1 +00110 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[12] decoded_imm[12] reg_pc[11] decoded_imm[11] $abc$16053$new_n2632 $abc$16053$new_n2637 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2639 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[12] $abc$16053$new_n2638 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[28] mem_rdata[12] $abc$16053$new_n2639 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[44] $abc$16053$new_n2641 count_instr[12] $abc$16053$new_n2640 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[44] count_cycle[12] $abc$16053$new_n2641 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2647 $abc$16053$new_n2021 $abc$16053$new_n2643 pcpi_rs1[13] $0\reg_out[31:0][13] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2645 $abc$16053$new_n2643 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[11] decoded_imm[11] reg_pc[12] decoded_imm[12] $abc$16053$new_n2632 $abc$16053$new_n2644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[45] $abc$16053$new_n2646 count_instr[13] $abc$16053$new_n2645 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[45] count_cycle[13] $abc$16053$new_n2646 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2513 $abc$16053$new_n2614 mem_rdata[29] mem_rdata[13] $abc$16053$new_n2647 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2650 $abc$16053$new_n2649 $abc$16053$new_n2454 $abc$16053$new_n2652 $0\reg_out[31:0][14] +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[14] decoded_imm[14] reg_pc[13] decoded_imm[13] $abc$16053$new_n2644 $abc$16053$new_n2649 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2651 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[14] $abc$16053$new_n2650 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2614 $abc$16053$new_n2513 mem_rdata[30] mem_rdata[14] $abc$16053$new_n2651 +1001 1 +1011 1 +1110 1 +1111 1 +.names instr_rdinstrh instr_rdinstr count_instr[46] $abc$16053$new_n2653 count_instr[14] $abc$16053$new_n2652 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[46] count_cycle[14] $abc$16053$new_n2653 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2659 $abc$16053$new_n2021 $abc$16053$new_n2655 pcpi_rs1[15] $0\reg_out[31:0][15] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2657 $abc$16053$new_n2655 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[13] decoded_imm[13] reg_pc[14] decoded_imm[14] $abc$16053$new_n2644 $abc$16053$new_n2656 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[47] $abc$16053$new_n2658 count_instr[15] $abc$16053$new_n2657 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[47] count_cycle[15] $abc$16053$new_n2658 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2660 latched_is_lb $abc$16053$new_n2659 +100 1 +101 1 +111 1 +.names $abc$16053$new_n2513 $abc$16053$new_n1442 mem_rdata[31] mem_rdata[15] $abc$16053$new_n2660 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$16053$new_n2663 $abc$16053$new_n1610 $abc$16053$new_n2662 $abc$16053$new_n2453 $abc$16053$new_n2667 $0\reg_out[31:0][16] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[16] decoded_imm[16] reg_pc[15] decoded_imm[15] $abc$16053$new_n2656 $abc$16053$new_n2662 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2664 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[16] $abc$16053$new_n2663 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[16] $abc$16053$new_n2666 $abc$16053$new_n2664 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names latched_is_lh $abc$16053$new_n2660 $abc$16053$new_n2665 +11 1 +.names $abc$16053$new_n1425 latched_is_lh $abc$16053$new_n2666 +10 1 +.names instr_rdinstrh $abc$16053$new_n2668 count_instr[48] count_instr[16] instr_rdinstr $abc$16053$new_n2667 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[48] count_cycle[16] $abc$16053$new_n2668 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2674 $abc$16053$new_n2670 $abc$16053$new_n2021 pcpi_rs1[17] $0\reg_out[31:0][17] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2672 $abc$16053$new_n2670 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[15] decoded_imm[15] reg_pc[16] decoded_imm[16] $abc$16053$new_n2656 $abc$16053$new_n2671 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[49] $abc$16053$new_n2673 count_instr[17] $abc$16053$new_n2672 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[49] count_cycle[17] $abc$16053$new_n2673 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[17] $abc$16053$new_n2674 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2677 $abc$16053$new_n1610 $abc$16053$new_n2676 $abc$16053$new_n2453 $abc$16053$new_n2679 $0\reg_out[31:0][18] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[18] decoded_imm[18] reg_pc[17] decoded_imm[17] $abc$16053$new_n2671 $abc$16053$new_n2676 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2678 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[18] $abc$16053$new_n2677 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[18] $abc$16053$new_n2666 $abc$16053$new_n2678 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2680 count_instr[50] count_instr[18] instr_rdinstr $abc$16053$new_n2679 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[50] count_cycle[18] $abc$16053$new_n2680 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2686 $abc$16053$new_n2021 $abc$16053$new_n2682 pcpi_rs1[19] $0\reg_out[31:0][19] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2684 $abc$16053$new_n2682 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[17] decoded_imm[17] reg_pc[18] decoded_imm[18] $abc$16053$new_n2671 $abc$16053$new_n2683 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[51] $abc$16053$new_n2685 count_instr[19] $abc$16053$new_n2684 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[51] count_cycle[19] $abc$16053$new_n2685 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[19] $abc$16053$new_n2686 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[19] decoded_imm[19] $abc$16053$new_n2683 $abc$16053$new_n2688 +010 1 +100 1 +110 1 +111 1 +.names $abc$16053$new_n2691 $abc$16053$new_n2021 pcpi_rs1[20] $abc$16053$new_n2022 $abc$16053$new_n2690 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[20] $abc$16053$new_n2691 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2699 $abc$16053$new_n2021 $abc$16053$new_n2695 pcpi_rs1[21] $0\reg_out[31:0][21] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2697 $abc$16053$new_n2695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[19] decoded_imm[19] reg_pc[20] decoded_imm[20] $abc$16053$new_n2683 $abc$16053$new_n2696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[53] $abc$16053$new_n2698 count_instr[21] $abc$16053$new_n2697 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[53] count_cycle[21] $abc$16053$new_n2698 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[21] $abc$16053$new_n2699 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2702 $abc$16053$new_n1610 $abc$16053$new_n2701 $abc$16053$new_n2453 $abc$16053$new_n2704 $0\reg_out[31:0][22] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[22] decoded_imm[22] reg_pc[21] decoded_imm[21] $abc$16053$new_n2696 $abc$16053$new_n2701 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2703 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[22] $abc$16053$new_n2702 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[22] $abc$16053$new_n2666 $abc$16053$new_n2703 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2705 count_instr[54] count_instr[22] instr_rdinstr $abc$16053$new_n2704 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[54] count_cycle[22] $abc$16053$new_n2705 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2711 $abc$16053$new_n2707 $abc$16053$new_n2021 pcpi_rs1[23] $0\reg_out[31:0][23] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2709 $abc$16053$new_n2707 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[21] decoded_imm[21] reg_pc[22] decoded_imm[22] $abc$16053$new_n2696 $abc$16053$new_n2708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[55] $abc$16053$new_n2710 count_instr[23] $abc$16053$new_n2709 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[55] count_cycle[23] $abc$16053$new_n2710 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[23] $abc$16053$new_n2711 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2714 $abc$16053$new_n1610 $abc$16053$new_n2713 $abc$16053$new_n2453 $abc$16053$new_n2716 $0\reg_out[31:0][24] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[24] decoded_imm[24] reg_pc[23] decoded_imm[23] $abc$16053$new_n2708 $abc$16053$new_n2713 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2715 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[24] $abc$16053$new_n2714 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[24] $abc$16053$new_n2666 $abc$16053$new_n2715 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2717 count_instr[56] count_instr[24] instr_rdinstr $abc$16053$new_n2716 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[56] count_cycle[24] $abc$16053$new_n2717 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2723 $abc$16053$new_n2719 $abc$16053$new_n2021 pcpi_rs1[25] $0\reg_out[31:0][25] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2721 $abc$16053$new_n2719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[23] decoded_imm[23] reg_pc[24] decoded_imm[24] $abc$16053$new_n2708 $abc$16053$new_n2720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[57] $abc$16053$new_n2722 count_instr[25] $abc$16053$new_n2721 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[57] count_cycle[25] $abc$16053$new_n2722 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[25] $abc$16053$new_n2723 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2726 $abc$16053$new_n1610 $abc$16053$new_n2725 $abc$16053$new_n2453 $abc$16053$new_n2728 $0\reg_out[31:0][26] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[26] decoded_imm[26] reg_pc[25] decoded_imm[25] $abc$16053$new_n2720 $abc$16053$new_n2725 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2727 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[26] $abc$16053$new_n2726 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[26] $abc$16053$new_n2666 $abc$16053$new_n2727 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2729 count_instr[58] count_instr[26] instr_rdinstr $abc$16053$new_n2728 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[58] count_cycle[26] $abc$16053$new_n2729 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2454 $abc$16053$new_n2735 $abc$16053$new_n2731 $abc$16053$new_n2021 pcpi_rs1[27] $0\reg_out[31:0][27] +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$16053$new_n1610 reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2733 $abc$16053$new_n2731 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[25] decoded_imm[25] reg_pc[26] decoded_imm[26] $abc$16053$new_n2720 $abc$16053$new_n2732 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[59] $abc$16053$new_n2734 count_instr[27] $abc$16053$new_n2733 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[59] count_cycle[27] $abc$16053$new_n2734 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[27] $abc$16053$new_n2735 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2738 $abc$16053$new_n1610 $abc$16053$new_n2737 $abc$16053$new_n2453 $abc$16053$new_n2740 $0\reg_out[31:0][28] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names reg_pc[28] decoded_imm[28] reg_pc[27] decoded_imm[27] $abc$16053$new_n2732 $abc$16053$new_n2737 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2739 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[28] $abc$16053$new_n2738 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[28] $abc$16053$new_n2666 $abc$16053$new_n2739 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2741 count_instr[60] count_instr[28] instr_rdinstr $abc$16053$new_n2740 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[60] count_cycle[28] $abc$16053$new_n2741 +00000 1 +00010 1 +10000 1 +10001 1 +.names $abc$16053$new_n2745 $abc$16053$new_n2743 $abc$16053$new_n2453 $abc$16053$new_n2747 $0\reg_out[31:0][29] +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n1610 reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2743 +1000 1 +1011 1 +1101 1 +1110 1 +.names reg_pc[27] decoded_imm[27] reg_pc[28] decoded_imm[28] $abc$16053$new_n2732 $abc$16053$new_n2744 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2746 $abc$16053$new_n2612 $abc$16053$new_n2022 pcpi_rs1[29] $abc$16053$new_n2745 +00011 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names latched_is_lb $abc$16053$new_n2665 mem_rdata[29] $abc$16053$new_n2666 $abc$16053$new_n2746 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names instr_rdinstrh $abc$16053$new_n2748 count_instr[61] count_instr[29] instr_rdinstr $abc$16053$new_n2747 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instr_rdcycleh instr_rdinstrh instr_rdinstr count_cycle[61] count_cycle[29] $abc$16053$new_n2748 +00000 1 +00010 1 +10000 1 +10001 1 +.names reg_pc[29] decoded_imm[29] $abc$16053$new_n2744 $abc$16053$new_n2750 +000 1 +001 1 +011 1 +101 1 +.names $abc$16053$new_n2753 $abc$16053$new_n2021 pcpi_rs1[30] $abc$16053$new_n2022 $abc$16053$new_n2752 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[30] $abc$16053$new_n2753 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2761 $abc$16053$new_n2021 $abc$16053$new_n2757 pcpi_rs1[31] $0\reg_out[31:0][31] +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$16053$new_n1610 reg_pc[31] decoded_imm[31] $abc$16053$new_n2758 $abc$16053$new_n2759 $abc$16053$new_n2757 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names reg_pc[29] decoded_imm[29] reg_pc[30] decoded_imm[30] $abc$16053$new_n2744 $abc$16053$new_n2758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names instr_rdinstrh instr_rdinstr count_instr[63] $abc$16053$new_n2760 count_instr[31] $abc$16053$new_n2759 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instr_rdcycleh count_cycle[63] count_cycle[31] $abc$16053$new_n2760 +000 1 +010 1 +100 1 +101 1 +.names $abc$16053$new_n2612 $abc$16053$new_n2665 latched_is_lb $abc$16053$new_n2666 mem_rdata[31] $abc$16053$new_n2761 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2453 $abc$16053$new_n2497 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_wdata[0:0] +11100 1 +.names resetn $abc$16053$new_n1620 $abc$16053$new_n2763 +11 1 +.names resetn $abc$16053$new_n2460 $0\set_mem_do_rdata[0:0] +11 1 +.names $abc$16053$new_n2018 $abc$16053$new_n2457 $abc$16053$new_n2763 $abc$16053$procmux$1608_CMP $abc$16053$new_n1612 $0\set_mem_do_rinst[0:0] +11100 1 +.names $abc$16053$new_n2767 $abc$16053$new_n1548 $abc$16053$new_n1610 $abc$16053$new_n2457 $0\decoder_trigger[0:0] +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2019 $abc$16053$new_n2767 +10 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2770 cpu_state[0] $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$procmux$2235_Y[0] +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names is_lb_lh_lw_lbu_lhu $abc$16053$new_n2386 $abc$16053$new_n2769 +10 1 +.names $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2453 $abc$16053$new_n2770 +10 1 +.names $abc$16053$new_n1622 $abc$16053$new_n1624 is_slli_srli_srai $abc$16053$new_n2771 +110 1 +.names resetn $abc$16053$new_n2773 $abc$16053$new_n2772 +10 1 +.names resetn $abc$16053$new_n2774 mem_wordsize[1] $abc$16053$new_n1551 $abc$16053$new_n2773 +1100 1 +.names pcpi_rs1[0] pcpi_rs1[1] mem_wordsize[0] $abc$16053$new_n2774 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2020 $abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y $abc$16053$new_n2776 $abc$16053$procmux$2235_Y[1] +1000 1 +1010 1 +1100 1 +1101 1 +.names cpu_state[1] is_sb_sh_sw is_sll_srl_sra $abc$16053$new_n1620 $abc$16053$new_n2777 $abc$16053$new_n2776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n1621 $abc$16053$new_n2385 is_lb_lh_lw_lbu_lhu $abc$16053$new_n2777 +000 1 +001 1 +011 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2779 $abc$16053$new_n2038 cpu_state[2] $abc$16053$new_n2018 $abc$16053$procmux$2235_Y[2] +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1620 is_sll_srl_sra $abc$16053$new_n2777 $abc$16053$new_n1624 $abc$16053$new_n2532 $abc$16053$new_n2779 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names $abc$16053$new_n2782 $abc$16053$new_n2781 cpu_state[3] $abc$16053$procmux$2235_Y[3] +101 1 +110 1 +111 1 +.names $abc$16053$new_n1620 $abc$16053$new_n1623 is_sll_srl_sra $abc$16053$new_n2777 is_sb_sh_sw $abc$16053$new_n2781 +00000 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2772 $abc$16053$new_n2018 $abc$16053$new_n1610 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n2782 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names cpu_state[4] $abc$16053$new_n2772 $abc$16053$new_n1620 $abc$16053$procmux$2235_Y[4] +111 1 +.names $abc$16053$new_n1620 $abc$16053$new_n2772 cpu_state[5] $abc$16053$new_n1991 instr_jal $abc$16053$procmux$2235_Y[5] +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names resetn cpu_state[6] $abc$16053$new_n1612 $abc$16053$new_n2380 $abc$16053$new_n2789 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names resetn $abc$16053$new_n2773 cpu_state[7] $abc$16053$new_n2771 $abc$16053$new_n2386 $abc$16053$procmux$2235_Y[7] +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2792 $abc$16053$new_n2793 pcpi_rs1[0] mem_la_wdata[0] $abc$16053$new_n2794 alu_out[0] +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names is_compare $abc$16053$new_n2393 instr_xor instr_xori $abc$16053$new_n2405 $abc$16053$new_n2792 +11000 1 +.names $abc$16053$new_n2393 pcpi_rs1[0] instr_and instr_andi mem_la_wdata[0] $abc$16053$new_n2793 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names $abc$16053$new_n2393 is_compare instr_xor instr_xori $abc$16053$new_n2794 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$16053$new_n2794 pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2797 $abc$16053$new_n2796 alu_out[1] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[1] instr_and instr_andi mem_la_wdata[1] $abc$16053$new_n2796 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names mem_la_wdata[0] instr_sub pcpi_rs1[0] instr_xor instr_xori $abc$16053$new_n2797 +10100 1 +11000 1 +.names $abc$16053$new_n2794 pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2799 $abc$16053$new_n2802 alu_out[2] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2800 $abc$16053$new_n2801 $abc$16053$new_n2799 +00000 1 +00010 1 +10000 1 +10001 1 +.names mem_la_wdata[0] pcpi_rs1[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2800 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names pcpi_rs1[0] mem_la_wdata[0] pcpi_rs1[1] mem_la_wdata[1] $abc$16053$new_n2801 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$16053$new_n2393 pcpi_rs1[2] instr_and instr_andi mem_la_wdata[2] $abc$16053$new_n2802 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2794 $abc$16053$new_n2804 $abc$16053$new_n2806 alu_out[3] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2805 $abc$16053$new_n2804 +000 1 +.names instr_sub pcpi_rs1[2] mem_la_wdata[2] $abc$16053$new_n2801 $abc$16053$new_n2800 $abc$16053$new_n2805 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[3] mem_la_wdata[3] instr_and instr_andi $abc$16053$new_n2806 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2808 $abc$16053$new_n2811 alu_out[4] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2809 $abc$16053$new_n2810 $abc$16053$new_n2808 +00000 1 +00001 1 +10001 1 +10011 1 +.names pcpi_rs1[2] mem_la_wdata[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2801 $abc$16053$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names mem_la_wdata[2] pcpi_rs1[2] pcpi_rs1[3] mem_la_wdata[3] $abc$16053$new_n2800 $abc$16053$new_n2810 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names $abc$16053$new_n2393 pcpi_rs1[4] instr_and instr_andi mem_la_wdata[4] $abc$16053$new_n2811 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2794 $abc$16053$new_n3203 $abc$16053$new_n2816 alu_out[5] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[5] mem_la_wdata[5] instr_and instr_andi $abc$16053$new_n2816 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2818 $abc$16053$new_n2821 alu_out[6] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2819 $abc$16053$new_n2820 $abc$16053$new_n2818 +00000 1 +00001 1 +10001 1 +10011 1 +.names pcpi_rs1[4] mem_la_wdata[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2809 $abc$16053$new_n2819 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names mem_la_wdata[4] pcpi_rs1[4] pcpi_rs1[5] mem_la_wdata[5] $abc$16053$new_n2810 $abc$16053$new_n2820 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[6] instr_and instr_andi mem_la_wdata[6] $abc$16053$new_n2821 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2794 $abc$16053$new_n3205 $abc$16053$new_n2826 alu_out[7] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[7] mem_la_wdata[7] instr_and instr_andi $abc$16053$new_n2826 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2828 $abc$16053$new_n2831 alu_out[8] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2829 $abc$16053$new_n2830 $abc$16053$new_n2828 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[6] mem_la_wdata[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2819 $abc$16053$new_n2829 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names mem_la_wdata[6] pcpi_rs1[6] pcpi_rs1[7] mem_la_wdata[7] $abc$16053$new_n2820 $abc$16053$new_n2830 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[8] instr_and instr_andi pcpi_rs2[8] $abc$16053$new_n2831 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2794 $abc$16053$new_n3207 $abc$16053$new_n2835 alu_out[9] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[9] pcpi_rs2[9] instr_and instr_andi $abc$16053$new_n2835 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2837 $abc$16053$new_n2840 alu_out[10] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2838 $abc$16053$new_n2839 $abc$16053$new_n2837 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[8] pcpi_rs2[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2829 $abc$16053$new_n2838 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[8] pcpi_rs1[8] pcpi_rs1[9] pcpi_rs2[9] $abc$16053$new_n2830 $abc$16053$new_n2839 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[10] instr_and instr_andi pcpi_rs2[10] $abc$16053$new_n2840 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2794 $abc$16053$new_n3209 $abc$16053$new_n2845 alu_out[11] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[11] pcpi_rs2[11] instr_and instr_andi $abc$16053$new_n2845 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2847 $abc$16053$new_n2850 alu_out[12] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2848 $abc$16053$new_n2849 $abc$16053$new_n2847 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[10] pcpi_rs2[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2838 $abc$16053$new_n2848 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[10] pcpi_rs1[10] pcpi_rs1[11] pcpi_rs2[11] $abc$16053$new_n2839 $abc$16053$new_n2849 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[12] instr_and instr_andi pcpi_rs2[12] $abc$16053$new_n2850 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2794 $abc$16053$new_n3211 $abc$16053$new_n2855 alu_out[13] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[13] pcpi_rs2[13] instr_and instr_andi $abc$16053$new_n2855 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2857 $abc$16053$new_n2860 alu_out[14] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2858 $abc$16053$new_n2859 $abc$16053$new_n2857 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[12] pcpi_rs2[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2848 $abc$16053$new_n2858 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[12] pcpi_rs1[12] pcpi_rs1[13] pcpi_rs2[13] $abc$16053$new_n2849 $abc$16053$new_n2859 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[14] instr_and instr_andi pcpi_rs2[14] $abc$16053$new_n2860 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2794 $abc$16053$new_n3213 $abc$16053$new_n2864 alu_out[15] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[15] pcpi_rs2[15] instr_and instr_andi $abc$16053$new_n2864 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2866 $abc$16053$new_n2869 alu_out[16] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2867 $abc$16053$new_n2868 $abc$16053$new_n2866 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[14] pcpi_rs2[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2858 $abc$16053$new_n2867 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[14] pcpi_rs1[14] pcpi_rs1[15] pcpi_rs2[15] $abc$16053$new_n2859 $abc$16053$new_n2868 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[16] instr_and instr_andi pcpi_rs2[16] $abc$16053$new_n2869 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2794 $abc$16053$new_n3215 $abc$16053$new_n2873 alu_out[17] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[17] pcpi_rs2[17] instr_and instr_andi $abc$16053$new_n2873 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2875 $abc$16053$new_n2878 alu_out[18] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_sub instr_xor instr_xori $abc$16053$new_n2876 $abc$16053$new_n2877 $abc$16053$new_n2875 +00010 1 +00011 1 +10001 1 +10011 1 +.names pcpi_rs1[16] pcpi_rs2[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2867 $abc$16053$new_n2876 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pcpi_rs2[16] pcpi_rs1[16] pcpi_rs1[17] pcpi_rs2[17] $abc$16053$new_n2868 $abc$16053$new_n2877 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[18] instr_and instr_andi pcpi_rs2[18] $abc$16053$new_n2878 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2794 $abc$16053$new_n3217 $abc$16053$new_n2883 alu_out[19] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[19] pcpi_rs2[19] instr_and instr_andi $abc$16053$new_n2883 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[20] pcpi_rs2[20] $abc$16053$new_n2885 $abc$16053$new_n2889 alu_out[20] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2887 instr_xori $abc$16053$new_n2886 instr_sub $abc$16053$new_n2885 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[18] pcpi_rs2[18] pcpi_rs1[19] pcpi_rs2[19] $abc$16053$new_n2876 $abc$16053$new_n2886 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2888 $abc$16053$new_n2439 $abc$16053$new_n2877 $abc$16053$new_n2887 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pcpi_rs1[18] pcpi_rs1[19] pcpi_rs2[18] pcpi_rs2[19] $abc$16053$new_n2888 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2393 pcpi_rs1[20] instr_and instr_andi pcpi_rs2[20] $abc$16053$new_n2889 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2794 $abc$16053$new_n2891 $abc$16053$new_n2893 alu_out[21] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2892 pcpi_rs1[20] $abc$16053$new_n2886 instr_sub pcpi_rs2[20] $abc$16053$new_n2891 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2887 pcpi_rs2[20] pcpi_rs1[20] $abc$16053$new_n2892 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[21] pcpi_rs2[21] instr_and instr_andi $abc$16053$new_n2893 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[22] pcpi_rs2[22] $abc$16053$new_n2895 $abc$16053$new_n2899 alu_out[22] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2897 instr_xor instr_xori $abc$16053$new_n2896 instr_sub $abc$16053$new_n2895 +10001 1 +10010 1 +10011 1 +.names pcpi_rs1[20] pcpi_rs2[20] pcpi_rs1[21] pcpi_rs2[21] $abc$16053$new_n2886 $abc$16053$new_n2896 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2437 $abc$16053$new_n2887 instr_sub $abc$16053$new_n2898 $abc$16053$new_n2897 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names pcpi_rs1[20] pcpi_rs1[21] pcpi_rs2[20] pcpi_rs2[21] $abc$16053$new_n2898 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$16053$new_n2393 pcpi_rs1[22] instr_and instr_andi pcpi_rs2[22] $abc$16053$new_n2899 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2794 $abc$16053$new_n2901 $abc$16053$new_n2903 alu_out[23] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2902 pcpi_rs1[22] $abc$16053$new_n2896 instr_sub pcpi_rs2[22] $abc$16053$new_n2901 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2897 pcpi_rs2[22] pcpi_rs1[22] $abc$16053$new_n2902 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2393 pcpi_rs1[23] pcpi_rs2[23] instr_and instr_andi $abc$16053$new_n2903 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[24] pcpi_rs2[24] $abc$16053$new_n2905 $abc$16053$new_n2910 alu_out[24] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2907 instr_xori $abc$16053$new_n2906 instr_sub $abc$16053$new_n2905 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[22] pcpi_rs2[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2896 $abc$16053$new_n2906 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2908 $abc$16053$new_n2907 +10 1 +.names $abc$16053$new_n2909 $abc$16053$new_n2888 $abc$16053$new_n2436 $abc$16053$new_n2877 $abc$16053$new_n2439 $abc$16053$new_n2908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pcpi_rs2[22] pcpi_rs1[22] pcpi_rs1[23] pcpi_rs2[23] $abc$16053$new_n2898 $abc$16053$new_n2909 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[24] instr_and instr_andi pcpi_rs2[24] $abc$16053$new_n2910 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2794 $abc$16053$new_n2912 $abc$16053$new_n2914 alu_out[25] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2913 pcpi_rs1[24] $abc$16053$new_n2906 instr_sub pcpi_rs2[24] $abc$16053$new_n2912 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2907 pcpi_rs2[24] pcpi_rs1[24] $abc$16053$new_n2913 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[25] pcpi_rs2[25] instr_and instr_andi $abc$16053$new_n2914 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2794 pcpi_rs1[26] pcpi_rs2[26] $abc$16053$new_n2916 $abc$16053$new_n2920 alu_out[26] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2918 instr_xori $abc$16053$new_n2917 instr_sub $abc$16053$new_n2916 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[24] pcpi_rs2[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2906 $abc$16053$new_n2917 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2919 $abc$16053$new_n2918 +10 1 +.names pcpi_rs2[24] pcpi_rs1[24] pcpi_rs1[25] pcpi_rs2[25] $abc$16053$new_n2908 $abc$16053$new_n2919 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[26] instr_and instr_andi pcpi_rs2[26] $abc$16053$new_n2920 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +.names pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2794 $abc$16053$new_n2922 $abc$16053$new_n2924 alu_out[27] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2923 pcpi_rs1[26] $abc$16053$new_n2917 instr_sub pcpi_rs2[26] $abc$16053$new_n2922 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2918 pcpi_rs2[26] pcpi_rs1[26] $abc$16053$new_n2923 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[27] pcpi_rs2[27] instr_and instr_andi $abc$16053$new_n2924 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[28] pcpi_rs2[28] $abc$16053$new_n2794 $abc$16053$new_n2926 $abc$16053$new_n2930 alu_out[28] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instr_xor $abc$16053$new_n2928 instr_xori $abc$16053$new_n2927 instr_sub $abc$16053$new_n2926 +00001 1 +00010 1 +00011 1 +.names pcpi_rs1[26] pcpi_rs2[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2917 $abc$16053$new_n2927 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_sub $abc$16053$new_n2929 $abc$16053$new_n2928 +10 1 +.names pcpi_rs2[26] pcpi_rs1[26] pcpi_rs1[27] pcpi_rs2[27] $abc$16053$new_n2919 $abc$16053$new_n2929 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[28] pcpi_rs2[28] instr_and instr_andi $abc$16053$new_n2930 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2794 $abc$16053$new_n2932 $abc$16053$new_n2934 alu_out[29] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2933 pcpi_rs1[28] $abc$16053$new_n2927 instr_sub pcpi_rs2[28] $abc$16053$new_n2932 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2928 pcpi_rs2[28] pcpi_rs1[28] $abc$16053$new_n2933 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +.names $abc$16053$new_n2393 pcpi_rs1[29] pcpi_rs2[29] instr_and instr_andi $abc$16053$new_n2934 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[30] pcpi_rs2[30] $abc$16053$new_n2794 $abc$16053$new_n2936 $abc$16053$new_n2940 alu_out[30] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2938 instr_xor instr_xori $abc$16053$new_n2937 instr_sub $abc$16053$new_n2936 +10000 1 +10001 1 +10011 1 +.names pcpi_rs1[28] pcpi_rs2[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2927 $abc$16053$new_n2937 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names instr_sub $abc$16053$new_n2939 $abc$16053$new_n2938 +00 1 +01 1 +11 1 +.names pcpi_rs2[28] pcpi_rs1[28] pcpi_rs1[29] pcpi_rs2[29] $abc$16053$new_n2929 $abc$16053$new_n2939 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2393 pcpi_rs1[30] pcpi_rs2[30] instr_and instr_andi $abc$16053$new_n2940 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names pcpi_rs1[31] pcpi_rs2[31] $abc$16053$new_n2794 $abc$16053$new_n2942 $abc$16053$new_n2944 alu_out[31] +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2943 pcpi_rs1[30] instr_sub $abc$16053$new_n2937 pcpi_rs2[30] $abc$16053$new_n2942 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instr_xor instr_xori $abc$16053$new_n2938 pcpi_rs2[30] pcpi_rs1[30] $abc$16053$new_n2943 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2393 pcpi_rs1[31] pcpi_rs2[31] instr_and instr_andi $abc$16053$new_n2944 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2946 latched_stalu reg_pc[0] alu_out_q[0] reg_out[0] cpuregs_wrdata[0] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names latched_store latched_branch $abc$16053$new_n2946 +10 1 +.names $abc$16053$new_n2946 $abc$16053$new_n1766 reg_pc[1] cpuregs_wrdata[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$16053$new_n2946 latched_stalu reg_pc[2] alu_out_q[2] reg_out[2] cpuregs_wrdata[2] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n2946 reg_pc[2] reg_pc[3] $abc$16053$new_n1705 cpuregs_wrdata[3] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names $abc$16053$new_n2946 reg_pc[4] reg_pc[2] reg_pc[3] $abc$16053$new_n1709 cpuregs_wrdata[4] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2952 alu_out_q[5] reg_out[5] cpuregs_wrdata[5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[5] reg_pc[2] reg_pc[3] reg_pc[4] $abc$16053$new_n2952 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2954 alu_out_q[6] reg_out[6] cpuregs_wrdata[6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[6] reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] $abc$16053$new_n2954 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1712 cpuregs_wrdata[7] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[2] reg_pc[3] reg_pc[4] reg_pc[5] reg_pc[6] $abc$16053$new_n2956 +11111 1 +.names $abc$16053$new_n2946 reg_pc[8] reg_pc[7] $abc$16053$new_n2956 $abc$16053$new_n1714 cpuregs_wrdata[8] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2959 alu_out_q[9] reg_out[9] cpuregs_wrdata[9] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[9] reg_pc[7] reg_pc[8] $abc$16053$new_n2956 $abc$16053$new_n2959 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2961 alu_out_q[10] reg_out[10] cpuregs_wrdata[10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[10] reg_pc[7] reg_pc[8] reg_pc[9] $abc$16053$new_n2956 $abc$16053$new_n2961 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1716 cpuregs_wrdata[11] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[7] reg_pc[8] reg_pc[9] reg_pc[10] $abc$16053$new_n2956 $abc$16053$new_n2963 +11111 1 +.names $abc$16053$new_n2946 reg_pc[12] reg_pc[11] $abc$16053$new_n2963 $abc$16053$new_n1724 cpuregs_wrdata[12] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2966 alu_out_q[13] reg_out[13] cpuregs_wrdata[13] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[13] reg_pc[11] reg_pc[12] $abc$16053$new_n2963 $abc$16053$new_n2966 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2968 alu_out_q[14] reg_out[14] cpuregs_wrdata[14] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[14] reg_pc[11] reg_pc[12] reg_pc[13] $abc$16053$new_n2963 $abc$16053$new_n2968 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1720 cpuregs_wrdata[15] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[11] reg_pc[12] reg_pc[13] reg_pc[14] $abc$16053$new_n2963 $abc$16053$new_n2970 +11111 1 +.names $abc$16053$new_n2946 reg_pc[16] reg_pc[15] $abc$16053$new_n2970 $abc$16053$new_n1730 cpuregs_wrdata[16] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2973 alu_out_q[17] reg_out[17] cpuregs_wrdata[17] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[17] reg_pc[15] reg_pc[16] $abc$16053$new_n2970 $abc$16053$new_n2973 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2975 alu_out_q[18] reg_out[18] cpuregs_wrdata[18] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[18] reg_pc[15] reg_pc[16] reg_pc[17] $abc$16053$new_n2970 $abc$16053$new_n2975 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1726 cpuregs_wrdata[19] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[15] reg_pc[16] reg_pc[17] reg_pc[18] $abc$16053$new_n2970 $abc$16053$new_n2977 +11111 1 +.names $abc$16053$new_n2946 reg_pc[20] reg_pc[19] $abc$16053$new_n2977 $abc$16053$new_n1734 cpuregs_wrdata[20] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1732 cpuregs_wrdata[21] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[19] reg_pc[20] $abc$16053$new_n2977 $abc$16053$new_n2980 +111 1 +.names $abc$16053$new_n2946 reg_pc[22] reg_pc[21] $abc$16053$new_n2980 $abc$16053$new_n1736 cpuregs_wrdata[22] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1738 cpuregs_wrdata[23] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[21] reg_pc[22] $abc$16053$new_n2980 $abc$16053$new_n2983 +111 1 +.names $abc$16053$new_n2946 reg_pc[24] reg_pc[23] $abc$16053$new_n2983 $abc$16053$new_n1746 cpuregs_wrdata[24] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1744 cpuregs_wrdata[25] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[23] reg_pc[24] $abc$16053$new_n2983 $abc$16053$new_n2986 +111 1 +.names $abc$16053$new_n2946 reg_pc[26] reg_pc[25] $abc$16053$new_n2986 $abc$16053$new_n1742 cpuregs_wrdata[26] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1740 cpuregs_wrdata[27] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[25] reg_pc[26] $abc$16053$new_n2986 $abc$16053$new_n2989 +111 1 +.names $abc$16053$new_n2946 reg_pc[28] reg_pc[27] $abc$16053$new_n2989 $abc$16053$new_n1749 cpuregs_wrdata[28] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2992 alu_out_q[29] reg_out[29] cpuregs_wrdata[29] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[29] reg_pc[27] reg_pc[28] $abc$16053$new_n2989 $abc$16053$new_n2992 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$16053$new_n2946 latched_stalu $abc$16053$new_n2994 alu_out_q[30] reg_out[30] cpuregs_wrdata[30] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names reg_pc[30] reg_pc[27] reg_pc[28] reg_pc[29] $abc$16053$new_n2989 $abc$16053$new_n2994 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2946 reg_pc[31] $abc$16053$new_n2996 $abc$16053$new_n2373 cpuregs_wrdata[31] +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1010 1 +1100 1 +1110 1 +.names reg_pc[27] reg_pc[28] reg_pc[29] reg_pc[30] $abc$16053$new_n2989 $abc$16053$new_n2996 +11111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[19] decoded_rs1[4] $0\decoded_rs1[4:0][4] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[15] decoded_rs1[0] $0\decoded_rs1[4:0][0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[16] decoded_rs1[1] $0\decoded_rs1[4:0][1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[17] decoded_rs1[2] $0\decoded_rs1[4:0][2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[18] decoded_rs1[3] $0\decoded_rs1[4:0][3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[20] decoded_rs2[0] $0\decoded_rs2[4:0][0] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[21] decoded_rs2[1] $0\decoded_rs2[4:0][1] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[22] decoded_rs2[2] $0\decoded_rs2[4:0][2] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[23] decoded_rs2[3] $0\decoded_rs2[4:0][3] +001 1 +011 1 +110 1 +111 1 +.names $abc$16053$new_n1548 mem_rdata_latched[24] decoded_rs2[4] $0\decoded_rs2[4:0][4] +001 1 +011 1 +110 1 +111 1 +.names count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[1] +01 1 +10 1 +.names count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[2] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[5] +01 1 +10 1 +.names count_cycle[4] count_cycle[3] count_cycle[2] count_cycle[1] count_cycle[0] $abc$16053$new_n3012 +11111 1 +.names count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[6] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[7] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $auto$alumacc.cc:485:replace_alu$4638.Y[8] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[9] +01 1 +10 1 +.names count_cycle[8] count_cycle[7] count_cycle[6] count_cycle[5] $abc$16053$new_n3012 $abc$16053$new_n3017 +11111 1 +.names count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[10] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[11] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $auto$alumacc.cc:485:replace_alu$4638.Y[12] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[13] +01 1 +10 1 +.names count_cycle[12] count_cycle[11] count_cycle[10] count_cycle[9] $abc$16053$new_n3017 $abc$16053$new_n3022 +11111 1 +.names count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[14] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[15] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $auto$alumacc.cc:485:replace_alu$4638.Y[16] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[17] $abc$16053$new_n3027 $auto$alumacc.cc:485:replace_alu$4638.Y[17] +01 1 +10 1 +.names count_cycle[16] count_cycle[15] count_cycle[14] count_cycle[13] $abc$16053$new_n3022 $abc$16053$new_n3027 +11111 1 +.names count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[18] +01 1 +10 1 +.names count_cycle[17] $abc$16053$new_n3027 $abc$16053$new_n3029 +11 1 +.names count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[19] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $auto$alumacc.cc:485:replace_alu$4638.Y[20] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[21] +01 1 +10 1 +.names count_cycle[20] count_cycle[19] count_cycle[18] $abc$16053$new_n3029 $abc$16053$new_n3033 +1111 1 +.names count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[22] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $auto$alumacc.cc:485:replace_alu$4638.Y[23] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[24] +01 1 +10 1 +.names count_cycle[23] count_cycle[22] count_cycle[21] $abc$16053$new_n3033 $abc$16053$new_n3037 +1111 1 +.names count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[25] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[26] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $auto$alumacc.cc:485:replace_alu$4638.Y[27] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[28] +01 1 +10 1 +.names count_cycle[27] count_cycle[26] count_cycle[25] count_cycle[24] $abc$16053$new_n3037 $abc$16053$new_n3042 +11111 1 +.names count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[29] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[30] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $auto$alumacc.cc:485:replace_alu$4638.Y[31] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[32] $abc$16053$new_n3047 $auto$alumacc.cc:485:replace_alu$4638.Y[32] +01 1 +10 1 +.names count_cycle[31] count_cycle[30] count_cycle[29] count_cycle[28] $abc$16053$new_n3042 $abc$16053$new_n3047 +11111 1 +.names count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[33] +01 1 +10 1 +.names count_cycle[32] $abc$16053$new_n3047 $abc$16053$new_n3049 +11 1 +.names count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[34] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[35] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $auto$alumacc.cc:485:replace_alu$4638.Y[36] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[37] +01 1 +10 1 +.names count_cycle[36] count_cycle[35] count_cycle[34] count_cycle[33] $abc$16053$new_n3049 $abc$16053$new_n3054 +11111 1 +.names count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[38] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[39] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $auto$alumacc.cc:485:replace_alu$4638.Y[40] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[41] +01 1 +10 1 +.names count_cycle[40] count_cycle[39] count_cycle[38] count_cycle[37] $abc$16053$new_n3054 $abc$16053$new_n3059 +11111 1 +.names count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[42] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[43] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $auto$alumacc.cc:485:replace_alu$4638.Y[44] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[45] +01 1 +10 1 +.names count_cycle[44] count_cycle[43] count_cycle[42] count_cycle[41] $abc$16053$new_n3059 $abc$16053$new_n3064 +11111 1 +.names count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[46] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[47] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $auto$alumacc.cc:485:replace_alu$4638.Y[48] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[49] +01 1 +10 1 +.names count_cycle[48] count_cycle[47] count_cycle[46] count_cycle[45] $abc$16053$new_n3064 $abc$16053$new_n3069 +11111 1 +.names count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[50] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[51] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $auto$alumacc.cc:485:replace_alu$4638.Y[52] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[53] +01 1 +10 1 +.names count_cycle[52] count_cycle[51] count_cycle[50] count_cycle[49] $abc$16053$new_n3069 $abc$16053$new_n3074 +11111 1 +.names count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[54] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[55] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $auto$alumacc.cc:485:replace_alu$4638.Y[56] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[57] +01 1 +10 1 +.names count_cycle[56] count_cycle[55] count_cycle[54] count_cycle[53] $abc$16053$new_n3074 $abc$16053$new_n3079 +11111 1 +.names count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[58] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[59] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $auto$alumacc.cc:485:replace_alu$4638.Y[60] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[61] +01 1 +10 1 +.names count_cycle[60] count_cycle[59] count_cycle[58] count_cycle[57] $abc$16053$new_n3079 $abc$16053$new_n3084 +11111 1 +.names count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[62] +011 1 +100 1 +101 1 +110 1 +.names count_cycle[63] count_cycle[62] count_cycle[61] $abc$16053$new_n3084 $auto$alumacc.cc:485:replace_alu$4638.Y[63] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs1[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs1[4:0][1] $abc$16053$new_n3091 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0\decoded_rs2[4:0][2] latched_rd[2] latched_rd[1] $0\decoded_rs2[4:0][1] $abc$16053$new_n3096 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names count_cycle[0] $auto$alumacc.cc:485:replace_alu$4638.X[0] +0 1 +.names decoder_trigger instr_jal $abc$16053$new_n1751 decoded_imm_j[30] $abc$16053$new_n1690 $abc$16053$new_n3098 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1750 $abc$16053$new_n3098 reg_next_pc[30] $abc$16053$auto$rtlil.cc:2693:MuxGate$14611 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names instr_jal $abc$16053$new_n1769 decoded_imm_j[29] $abc$16053$new_n1691 $abc$16053$new_n1748 $abc$16053$new_n3100 +00010 1 +00110 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1747 decoder_trigger $abc$16053$new_n3100 reg_next_pc[29] $abc$16053$auto$rtlil.cc:2693:MuxGate$14613 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1752 decoded_imm_j[28] $abc$16053$new_n1691 $abc$16053$new_n3102 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1748 $abc$16053$new_n3102 reg_next_pc[28] $abc$16053$auto$rtlil.cc:2693:MuxGate$14615 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[27] $abc$16053$new_n1741 instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n3104 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1739 decoder_trigger $abc$16053$new_n3104 $abc$16053$new_n1777 instr_jal $abc$16053$new_n3105 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3105 reg_next_pc[27] $abc$16053$auto$rtlil.cc:2693:MuxGate$14617 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[26] $abc$16053$new_n1753 $abc$16053$new_n1777 $abc$16053$new_n3107 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1741 $abc$16053$new_n3107 reg_next_pc[26] $abc$16053$auto$rtlil.cc:2693:MuxGate$14619 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1787 decoded_imm_j[25] $abc$16053$new_n1778 $abc$16053$new_n3109 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1743 $abc$16053$new_n3109 reg_next_pc[25] $abc$16053$auto$rtlil.cc:2693:MuxGate$14621 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1754 decoded_imm_j[24] $abc$16053$new_n1692 $abc$16053$new_n3111 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1745 $abc$16053$new_n3111 reg_next_pc[24] $abc$16053$auto$rtlil.cc:2693:MuxGate$14623 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1793 decoded_imm_j[23] $abc$16053$new_n1693 $abc$16053$new_n3113 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1737 $abc$16053$new_n3113 reg_next_pc[23] $abc$16053$auto$rtlil.cc:2693:MuxGate$14625 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1755 decoded_imm_j[22] $abc$16053$new_n1694 $abc$16053$new_n3115 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1735 $abc$16053$new_n3115 reg_next_pc[22] $abc$16053$auto$rtlil.cc:2693:MuxGate$14627 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names instr_jal $abc$16053$new_n1800 decoded_imm_j[21] $abc$16053$new_n1695 $abc$16053$new_n1733 $abc$16053$new_n3117 +00010 1 +00110 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1731 decoder_trigger $abc$16053$new_n3117 reg_next_pc[21] $abc$16053$auto$rtlil.cc:2693:MuxGate$14629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1756 decoded_imm_j[20] $abc$16053$new_n1695 $abc$16053$new_n3119 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1733 $abc$16053$new_n3119 reg_next_pc[20] $abc$16053$auto$rtlil.cc:2693:MuxGate$14631 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[19] $abc$16053$new_n1727 instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n3121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1725 decoder_trigger $abc$16053$new_n3121 $abc$16053$new_n1808 instr_jal $abc$16053$new_n3122 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3122 reg_next_pc[19] $abc$16053$auto$rtlil.cc:2693:MuxGate$14633 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[18] $abc$16053$new_n1757 $abc$16053$new_n1808 $abc$16053$new_n3124 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1727 $abc$16053$new_n3124 reg_next_pc[18] $abc$16053$auto$rtlil.cc:2693:MuxGate$14635 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1818 decoded_imm_j[17] $abc$16053$new_n1809 $abc$16053$new_n3126 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1728 $abc$16053$new_n3126 reg_next_pc[17] $abc$16053$auto$rtlil.cc:2693:MuxGate$14637 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1758 decoded_imm_j[16] $abc$16053$new_n1696 $abc$16053$new_n3128 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1729 $abc$16053$new_n3128 reg_next_pc[16] $abc$16053$auto$rtlil.cc:2693:MuxGate$14639 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[15] $abc$16053$new_n1721 instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n3130 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1719 decoder_trigger $abc$16053$new_n3130 $abc$16053$new_n1825 instr_jal $abc$16053$new_n3131 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3131 reg_next_pc[15] $abc$16053$auto$rtlil.cc:2693:MuxGate$14641 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[14] $abc$16053$new_n1759 $abc$16053$new_n1825 $abc$16053$new_n3133 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1721 $abc$16053$new_n3133 reg_next_pc[14] $abc$16053$auto$rtlil.cc:2693:MuxGate$14643 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1835 decoded_imm_j[13] $abc$16053$new_n1826 $abc$16053$new_n3135 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1722 $abc$16053$new_n3135 reg_next_pc[13] $abc$16053$auto$rtlil.cc:2693:MuxGate$14645 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1760 decoded_imm_j[12] $abc$16053$new_n1697 $abc$16053$new_n3137 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1723 $abc$16053$new_n3137 reg_next_pc[12] $abc$16053$auto$rtlil.cc:2693:MuxGate$14647 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[11] $abc$16053$new_n1717 instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n3139 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1715 decoder_trigger $abc$16053$new_n3139 $abc$16053$new_n1842 instr_jal $abc$16053$new_n3140 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3140 reg_next_pc[11] $abc$16053$auto$rtlil.cc:2693:MuxGate$14649 +001 1 +011 1 +110 1 +111 1 +.names decoder_trigger instr_jal decoded_imm_j[10] $abc$16053$new_n1761 $abc$16053$new_n1842 $abc$16053$new_n3142 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1717 $abc$16053$new_n3142 reg_next_pc[10] $abc$16053$auto$rtlil.cc:2693:MuxGate$14651 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1851 decoded_imm_j[9] $abc$16053$new_n1698 $abc$16053$new_n3144 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1718 $abc$16053$new_n3144 reg_next_pc[9] $abc$16053$auto$rtlil.cc:2693:MuxGate$14653 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1762 decoded_imm_j[8] $abc$16053$new_n1699 $abc$16053$new_n3146 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1713 $abc$16053$new_n3146 reg_next_pc[8] $abc$16053$auto$rtlil.cc:2693:MuxGate$14655 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoder_trigger instr_jal $abc$16053$new_n1858 decoded_imm_j[7] $abc$16053$new_n1700 $abc$16053$new_n3148 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1711 $abc$16053$new_n3148 reg_next_pc[7] $abc$16053$auto$rtlil.cc:2693:MuxGate$14657 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names decoded_imm_j[5] $abc$16053$new_n1708 instr_jal decoded_imm_j[4] $abc$16053$new_n1764 $abc$16053$new_n3150 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n1707 decoder_trigger $abc$16053$new_n3150 $abc$16053$new_n1702 instr_jal $abc$16053$new_n3151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1612 $abc$16053$new_n3151 reg_next_pc[5] $abc$16053$auto$rtlil.cc:2693:MuxGate$14661 +001 1 +011 1 +110 1 +111 1 +.names decoded_imm_j[3] $abc$16053$new_n1706 instr_jal $abc$16053$new_n1765 decoded_imm_j[2] $abc$16053$new_n3153 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n1612 $abc$16053$new_n1703 decoder_trigger $abc$16053$new_n3153 reg_next_pc[3] $abc$16053$auto$rtlil.cc:2693:MuxGate$14665 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2022 $abc$16053$new_n2025 $abc$16053$new_n2027 pcpi_rs1[29] pcpi_rs1[27] $abc$16053$new_n3155 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2043 $abc$16053$new_n2028 $abc$16053$new_n3155 pcpi_rs1[24] $abc$16053$new_n2025 $abc$16053$new_n3156 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names pcpi_rs1[22] $abc$16053$new_n2084 decoded_imm[22] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3157 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[21] pcpi_rs1[18] $abc$16053$new_n3158 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3158 $abc$16053$new_n2025 pcpi_rs1[23] pcpi_rs1[26] $abc$16053$new_n3159 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3157 $abc$16053$new_n2033 $abc$16053$new_n3159 $abc$16053$new_n2085 $abc$16053$auto$rtlil.cc:2693:MuxGate$14937 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names pcpi_rs1[14] $abc$16053$new_n2139 decoded_imm[14] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3161 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[10] $abc$16053$new_n3162 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3162 $abc$16053$new_n2025 pcpi_rs1[15] pcpi_rs1[18] $abc$16053$new_n3163 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3161 $abc$16053$new_n2033 $abc$16053$new_n3163 $abc$16053$new_n2140 $abc$16053$auto$rtlil.cc:2693:MuxGate$14953 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names pcpi_rs1[12] $abc$16053$new_n2153 decoded_imm[12] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3165 +00001 1 +00011 1 +00111 1 +01011 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[11] pcpi_rs1[8] $abc$16053$new_n3166 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$16053$new_n2022 $abc$16053$new_n3166 $abc$16053$new_n2025 pcpi_rs1[13] pcpi_rs1[16] $abc$16053$new_n3167 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$16053$new_n3165 $abc$16053$new_n2033 $abc$16053$new_n3167 $abc$16053$new_n2154 $abc$16053$auto$rtlil.cc:2693:MuxGate$14957 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$16053$new_n2019 $abc$16053$new_n2022 $abc$16053$new_n2013 $abc$16053$new_n2188 $abc$16053$new_n2190 $abc$16053$new_n3169 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n3169 pcpi_rs1[7] $abc$16053$new_n2033 decoded_imm[7] $abc$16053$new_n2019 $abc$16053$auto$rtlil.cc:2693:MuxGate$14967 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names pcpi_rs1[3] $abc$16053$new_n2015 decoded_imm[3] $abc$16053$new_n2019 $abc$16053$new_n2033 $abc$16053$new_n3171 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[7] pcpi_rs1[4] pcpi_rs1[2] $abc$16053$new_n3172 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n3171 $abc$16053$new_n2033 $abc$16053$new_n2212 $abc$16053$new_n3172 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14975 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2027 $abc$16053$new_n2025 pcpi_rs1[5] pcpi_rs1[2] pcpi_rs1[0] $abc$16053$new_n3174 +00100 1 +00101 1 +00110 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$16053$new_n2033 pcpi_rs1[1] $abc$16053$new_n2225 $abc$16053$new_n3174 $abc$16053$new_n2022 $abc$16053$auto$rtlil.cc:2693:MuxGate$14979 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$16053$new_n2358 decoded_imm[31] $abc$16053$new_n2019 $abc$16053$new_n2038 $abc$16053$new_n2026 $abc$16053$new_n3176 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2033 $abc$16053$new_n3176 pcpi_rs1[31] $abc$16053$new_n2019 $abc$16053$new_n2360 $abc$16053$auto$rtlil.cc:2693:MuxGate$15109 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11110 1 +.names pcpi_rs1[0] mem_rdata[9] mem_rdata[1] $abc$16053$new_n3178 +001 1 +011 1 +110 1 +111 1 +.names pcpi_rs1[1] pcpi_rs1[0] $abc$16053$new_n3178 mem_rdata[25] mem_rdata[17] $abc$16053$new_n3179 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$16053$new_n1442 $abc$16053$new_n2513 $abc$16053$new_n3179 mem_rdata[17] mem_rdata[1] $abc$16053$new_n3180 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n3180 pcpi_rs1[1] $abc$16053$new_n2553 $0\reg_out[31:0][1] +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[3] count_cycle[35] count_cycle[3] $abc$16053$new_n3182 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2571 count_instr[35] $abc$16053$new_n3182 $abc$16053$new_n3183 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n2022 $abc$16053$new_n2567 $abc$16053$new_n3183 pcpi_rs1[3] $0\reg_out[31:0][3] +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[5] count_cycle[37] count_cycle[5] $abc$16053$new_n3185 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1610 instr_rdinstrh $abc$16053$new_n2585 count_instr[37] $abc$16053$new_n3185 $abc$16053$new_n3186 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n3189 $abc$16053$new_n2454 $abc$16053$new_n3186 $abc$16053$new_n2022 pcpi_rs1[5] $0\reg_out[31:0][5] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n1442 mem_rdata[5] $abc$16053$new_n2513 pcpi_rs1[1] mem_rdata[21] $abc$16053$new_n3188 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$16053$new_n2021 $abc$16053$new_n1442 $abc$16053$new_n3188 pcpi_rs1[0] $abc$16053$new_n2590 $abc$16053$new_n3189 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instr_rdinstr instr_rdcycleh count_instr[8] count_cycle[40] count_cycle[8] $abc$16053$new_n3190 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2611 instr_rdinstrh $abc$16053$new_n2453 count_instr[40] $abc$16053$new_n3190 $abc$16053$new_n3191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2617 reg_pc[8] decoded_imm[8] $abc$16053$new_n3191 $0\reg_out[31:0][8] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names instr_rdinstr instr_rdcycleh count_instr[20] count_cycle[52] count_cycle[20] $abc$16053$new_n3193 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2690 instr_rdinstrh $abc$16053$new_n2453 count_instr[52] $abc$16053$new_n3193 $abc$16053$new_n3194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2688 reg_pc[20] decoded_imm[20] $abc$16053$new_n3194 $0\reg_out[31:0][20] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names instr_rdinstr instr_rdcycleh count_instr[30] count_cycle[62] count_cycle[30] $abc$16053$new_n3196 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$16053$new_n2752 instr_rdinstrh $abc$16053$new_n2453 count_instr[62] $abc$16053$new_n3196 $abc$16053$new_n3197 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$16053$new_n1610 $abc$16053$new_n2750 reg_pc[30] decoded_imm[30] $abc$16053$new_n3197 $0\reg_out[31:0][30] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$16053$new_n2038 $abc$16053$new_n1610 $abc$16053$new_n2022 is_beq_bne_blt_bge_bltu_bgeu $abc$16053$new_n1549 $abc$16053$new_n3199 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$16053$new_n2789 $abc$16053$new_n2767 $abc$16053$new_n2394 $abc$16053$new_n2769 $abc$16053$new_n2771 $abc$16053$new_n3200 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names $abc$16053$new_n2773 $abc$16053$new_n3200 $abc$16053$new_n3199 $abc$16053$new_n2019 $abc$16053$procmux$2235_Y[6] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names instr_sub pcpi_rs1[4] mem_la_wdata[4] $abc$16053$new_n2810 $abc$16053$new_n2809 $abc$16053$new_n3202 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3202 instr_xor instr_xori $abc$16053$new_n3203 +100 1 +.names instr_sub pcpi_rs1[6] mem_la_wdata[6] $abc$16053$new_n2820 $abc$16053$new_n2819 $abc$16053$new_n3204 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3204 instr_xor instr_xori $abc$16053$new_n3205 +100 1 +.names instr_sub pcpi_rs1[8] pcpi_rs2[8] $abc$16053$new_n2830 $abc$16053$new_n2829 $abc$16053$new_n3206 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3206 instr_xor instr_xori $abc$16053$new_n3207 +100 1 +.names instr_sub pcpi_rs1[10] pcpi_rs2[10] $abc$16053$new_n2839 $abc$16053$new_n2838 $abc$16053$new_n3208 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3208 instr_xor instr_xori $abc$16053$new_n3209 +100 1 +.names instr_sub pcpi_rs1[12] pcpi_rs2[12] $abc$16053$new_n2849 $abc$16053$new_n2848 $abc$16053$new_n3210 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3210 instr_xor instr_xori $abc$16053$new_n3211 +100 1 +.names instr_sub pcpi_rs1[14] pcpi_rs2[14] $abc$16053$new_n2859 $abc$16053$new_n2858 $abc$16053$new_n3212 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3212 instr_xor instr_xori $abc$16053$new_n3213 +100 1 +.names instr_sub pcpi_rs1[16] pcpi_rs2[16] $abc$16053$new_n2868 $abc$16053$new_n2867 $abc$16053$new_n3214 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3214 instr_xor instr_xori $abc$16053$new_n3215 +100 1 +.names instr_sub pcpi_rs1[18] pcpi_rs2[18] $abc$16053$new_n2877 $abc$16053$new_n2876 $abc$16053$new_n3216 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$16053$new_n3216 instr_xor instr_xori $abc$16053$new_n3217 +100 1 +.names $abc$16053$new_n3091 latched_rd[4] $0\decoded_rs1[4:0][4] $0\decoded_rs1[4:0][0] latched_rd[0] $abc$16053$new_n3218 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n3218 $0\decoded_rs1[4:0][3] latched_rd[3] $0\decoded_rs1[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4922 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$16053$new_n3096 $0\decoded_rs2[4:0][4] latched_rd[4] $0\decoded_rs2[4:0][0] latched_rd[0] $abc$16053$new_n3220 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$16053$new_n3220 $0\decoded_rs2[4:0][3] latched_rd[3] $0\decoded_rs2[4:0][1] latched_rd[1] $abc$16053$auto$rtlil.cc:2515:And$4912 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.subckt dff C=clk D=cpuregs_wrdata[0] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[0] +.subckt dff C=clk D=cpuregs_wrdata[1] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[1] +.subckt dff C=clk D=cpuregs_wrdata[2] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[2] +.subckt dff C=clk D=cpuregs_wrdata[3] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[3] +.subckt dff C=clk D=cpuregs_wrdata[4] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[4] +.subckt dff C=clk D=cpuregs_wrdata[5] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[5] +.subckt dff C=clk D=cpuregs_wrdata[6] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[6] +.subckt dff C=clk D=cpuregs_wrdata[7] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[7] +.subckt dff C=clk D=cpuregs_wrdata[8] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[8] +.subckt dff C=clk D=cpuregs_wrdata[9] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[9] +.subckt dff C=clk D=cpuregs_wrdata[10] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[10] +.subckt dff C=clk D=cpuregs_wrdata[11] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[11] +.subckt dff C=clk D=cpuregs_wrdata[12] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[12] +.subckt dff C=clk D=cpuregs_wrdata[13] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[13] +.subckt dff C=clk D=cpuregs_wrdata[14] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[14] +.subckt dff C=clk D=cpuregs_wrdata[15] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[15] +.subckt dff C=clk D=cpuregs_wrdata[16] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[16] +.subckt dff C=clk D=cpuregs_wrdata[17] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[17] +.subckt dff C=clk D=cpuregs_wrdata[18] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[18] +.subckt dff C=clk D=cpuregs_wrdata[19] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[19] +.subckt dff C=clk D=cpuregs_wrdata[20] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[20] +.subckt dff C=clk D=cpuregs_wrdata[21] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[21] +.subckt dff C=clk D=cpuregs_wrdata[22] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[22] +.subckt dff C=clk D=cpuregs_wrdata[23] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[23] +.subckt dff C=clk D=cpuregs_wrdata[24] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[24] +.subckt dff C=clk D=cpuregs_wrdata[25] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[25] +.subckt dff C=clk D=cpuregs_wrdata[26] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[26] +.subckt dff C=clk D=cpuregs_wrdata[27] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[27] +.subckt dff C=clk D=cpuregs_wrdata[28] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[28] +.subckt dff C=clk D=cpuregs_wrdata[29] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[29] +.subckt dff C=clk D=cpuregs_wrdata[30] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[30] +.subckt dff C=clk D=cpuregs_wrdata[31] Q=$abc$16053$auto$mem.cc:1145:emulate_transparency$4906[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4922 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4923 +.subckt sdffrn C=clk D=$abc$16053$logic_and$./benchmark/picorv32.v:1871$636_Y Q=decoder_pseudo_trigger RN=$abc$16053$auto$opt_dff.cc:253:combine_resets$4218 +.subckt sdffr C=clk D=$abc$16053$reduce_or$./benchmark/picorv32.v:863$175_Y Q=is_compare R=$abc$16053$auto$opt_dff.cc:253:combine_resets$4160 +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15039 Q=mem_addr[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15037 Q=mem_addr[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15035 Q=mem_addr[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15033 Q=mem_addr[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15031 Q=mem_addr[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15029 Q=mem_addr[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15027 Q=mem_addr[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15025 Q=mem_addr[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15023 Q=mem_addr[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15021 Q=mem_addr[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15019 Q=mem_addr[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15017 Q=mem_addr[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15015 Q=mem_addr[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15013 Q=mem_addr[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15011 Q=mem_addr[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15009 Q=mem_addr[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15007 Q=mem_addr[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15005 Q=mem_addr[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15003 Q=mem_addr[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15001 Q=mem_addr[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14999 Q=mem_addr[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14997 Q=mem_addr[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14995 Q=mem_addr[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14993 Q=mem_addr[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14991 Q=mem_addr[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14989 Q=mem_addr[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14987 Q=mem_addr[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14985 Q=mem_addr[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14983 Q=mem_addr[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15203 Q=mem_addr[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2515:And$4912 Q=$abc$16053$auto$mem.cc:1172:emulate_transparency$4913 +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14981 Q=pcpi_rs1[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14979 Q=pcpi_rs1[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14977 Q=pcpi_rs1[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14975 Q=pcpi_rs1[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14973 Q=pcpi_rs1[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14971 Q=pcpi_rs1[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14969 Q=pcpi_rs1[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14967 Q=pcpi_rs1[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14965 Q=pcpi_rs1[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14963 Q=pcpi_rs1[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14961 Q=pcpi_rs1[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14959 Q=pcpi_rs1[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14957 Q=pcpi_rs1[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14955 Q=pcpi_rs1[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14953 Q=pcpi_rs1[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14951 Q=pcpi_rs1[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14949 Q=pcpi_rs1[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14947 Q=pcpi_rs1[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14945 Q=pcpi_rs1[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14943 Q=pcpi_rs1[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14941 Q=pcpi_rs1[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14939 Q=pcpi_rs1[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14937 Q=pcpi_rs1[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14935 Q=pcpi_rs1[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14933 Q=pcpi_rs1[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14931 Q=pcpi_rs1[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14929 Q=pcpi_rs1[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14927 Q=pcpi_rs1[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14925 Q=pcpi_rs1[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14923 Q=pcpi_rs1[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15111 Q=pcpi_rs1[30] +.subckt dff C=clk D=mem_rdata_latched[0] Q=mem_rdata_q[0] +.subckt dff C=clk D=mem_rdata_latched[1] Q=mem_rdata_q[1] +.subckt dff C=clk D=mem_rdata_latched[2] Q=mem_rdata_q[2] +.subckt dff C=clk D=mem_rdata_latched[3] Q=mem_rdata_q[3] +.subckt dff C=clk D=mem_rdata_latched[4] Q=mem_rdata_q[4] +.subckt dff C=clk D=mem_rdata_latched[5] Q=mem_rdata_q[5] +.subckt dff C=clk D=mem_rdata_latched[6] Q=mem_rdata_q[6] +.subckt dff C=clk D=mem_rdata_latched[7] Q=mem_rdata_q[7] +.subckt dff C=clk D=mem_rdata_latched[8] Q=mem_rdata_q[8] +.subckt dff C=clk D=mem_rdata_latched[9] Q=mem_rdata_q[9] +.subckt dff C=clk D=mem_rdata_latched[10] Q=mem_rdata_q[10] +.subckt dff C=clk D=mem_rdata_latched[11] Q=mem_rdata_q[11] +.subckt dff C=clk D=mem_rdata_latched[12] Q=mem_rdata_q[12] +.subckt dff C=clk D=mem_rdata_latched[13] Q=mem_rdata_q[13] +.subckt dff C=clk D=mem_rdata_latched[14] Q=mem_rdata_q[14] +.subckt dff C=clk D=mem_rdata_latched[15] Q=mem_rdata_q[15] +.subckt dff C=clk D=mem_rdata_latched[16] Q=mem_rdata_q[16] +.subckt dff C=clk D=mem_rdata_latched[17] Q=mem_rdata_q[17] +.subckt dff C=clk D=mem_rdata_latched[18] Q=mem_rdata_q[18] +.subckt dff C=clk D=mem_rdata_latched[19] Q=mem_rdata_q[19] +.subckt dff C=clk D=mem_rdata_latched[20] Q=mem_rdata_q[20] +.subckt dff C=clk D=mem_rdata_latched[21] Q=mem_rdata_q[21] +.subckt dff C=clk D=mem_rdata_latched[22] Q=mem_rdata_q[22] +.subckt dff C=clk D=mem_rdata_latched[23] Q=mem_rdata_q[23] +.subckt dff C=clk D=mem_rdata_latched[24] Q=mem_rdata_q[24] +.subckt dff C=clk D=mem_rdata_latched[25] Q=mem_rdata_q[25] +.subckt dff C=clk D=mem_rdata_latched[26] Q=mem_rdata_q[26] +.subckt dff C=clk D=mem_rdata_latched[27] Q=mem_rdata_q[27] +.subckt dff C=clk D=mem_rdata_latched[28] Q=mem_rdata_q[28] +.subckt dff C=clk D=mem_rdata_latched[29] Q=mem_rdata_q[29] +.subckt dff C=clk D=mem_rdata_latched[30] Q=mem_rdata_q[30] +.subckt dff C=clk D=mem_rdata_latched[31] Q=mem_rdata_q[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15189 Q=mem_valid +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14859 Q=count_instr[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14857 Q=count_instr[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14855 Q=count_instr[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14853 Q=count_instr[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14851 Q=count_instr[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14849 Q=count_instr[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14847 Q=count_instr[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14845 Q=count_instr[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14843 Q=count_instr[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14841 Q=count_instr[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14839 Q=count_instr[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14837 Q=count_instr[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14835 Q=count_instr[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14833 Q=count_instr[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14831 Q=count_instr[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14829 Q=count_instr[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14827 Q=count_instr[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14825 Q=count_instr[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14823 Q=count_instr[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14821 Q=count_instr[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14819 Q=count_instr[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14817 Q=count_instr[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14815 Q=count_instr[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14813 Q=count_instr[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14811 Q=count_instr[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14809 Q=count_instr[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14807 Q=count_instr[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14805 Q=count_instr[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14803 Q=count_instr[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14801 Q=count_instr[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14799 Q=count_instr[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14797 Q=count_instr[31] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14795 Q=count_instr[32] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14793 Q=count_instr[33] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14791 Q=count_instr[34] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14789 Q=count_instr[35] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14787 Q=count_instr[36] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14785 Q=count_instr[37] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14783 Q=count_instr[38] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14781 Q=count_instr[39] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14779 Q=count_instr[40] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14777 Q=count_instr[41] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14775 Q=count_instr[42] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14773 Q=count_instr[43] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14771 Q=count_instr[44] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14769 Q=count_instr[45] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14767 Q=count_instr[46] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14765 Q=count_instr[47] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14763 Q=count_instr[48] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14761 Q=count_instr[49] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14759 Q=count_instr[50] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14757 Q=count_instr[51] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14755 Q=count_instr[52] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14753 Q=count_instr[53] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14751 Q=count_instr[54] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14749 Q=count_instr[55] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14747 Q=count_instr[56] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14745 Q=count_instr[57] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14743 Q=count_instr[58] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14741 Q=count_instr[59] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14739 Q=count_instr[60] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14737 Q=count_instr[61] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14735 Q=count_instr[62] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15113 Q=count_instr[63] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$procmux$1608_CMP Q=trap RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.X[0] Q=count_cycle[0] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[1] Q=count_cycle[1] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[2] Q=count_cycle[2] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[3] Q=count_cycle[3] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[4] Q=count_cycle[4] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[5] Q=count_cycle[5] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[6] Q=count_cycle[6] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[7] Q=count_cycle[7] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[8] Q=count_cycle[8] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[9] Q=count_cycle[9] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[10] Q=count_cycle[10] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[11] Q=count_cycle[11] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[12] Q=count_cycle[12] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[13] Q=count_cycle[13] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[14] Q=count_cycle[14] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[15] Q=count_cycle[15] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[16] Q=count_cycle[16] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[17] Q=count_cycle[17] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[18] Q=count_cycle[18] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[19] Q=count_cycle[19] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[20] Q=count_cycle[20] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[21] Q=count_cycle[21] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[22] Q=count_cycle[22] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[23] Q=count_cycle[23] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[24] Q=count_cycle[24] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[25] Q=count_cycle[25] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[26] Q=count_cycle[26] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[27] Q=count_cycle[27] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[28] Q=count_cycle[28] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[29] Q=count_cycle[29] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[30] Q=count_cycle[30] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[31] Q=count_cycle[31] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[32] Q=count_cycle[32] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[33] Q=count_cycle[33] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[34] Q=count_cycle[34] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[35] Q=count_cycle[35] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[36] Q=count_cycle[36] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[37] Q=count_cycle[37] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[38] Q=count_cycle[38] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[39] Q=count_cycle[39] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[40] Q=count_cycle[40] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[41] Q=count_cycle[41] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[42] Q=count_cycle[42] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[43] Q=count_cycle[43] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[44] Q=count_cycle[44] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[45] Q=count_cycle[45] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[46] Q=count_cycle[46] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[47] Q=count_cycle[47] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[48] Q=count_cycle[48] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[49] Q=count_cycle[49] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[50] Q=count_cycle[50] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[51] Q=count_cycle[51] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[52] Q=count_cycle[52] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[53] Q=count_cycle[53] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[54] Q=count_cycle[54] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[55] Q=count_cycle[55] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[56] Q=count_cycle[56] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[57] Q=count_cycle[57] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[58] Q=count_cycle[58] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[59] Q=count_cycle[59] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[60] Q=count_cycle[60] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[61] Q=count_cycle[61] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[62] Q=count_cycle[62] RN=resetn +.subckt sdffrn C=clk D=$auto$alumacc.cc:485:replace_alu$4638.Y[63] Q=count_cycle[63] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14733 Q=reg_pc[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14731 Q=reg_pc[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14729 Q=reg_pc[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14727 Q=reg_pc[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14725 Q=reg_pc[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14723 Q=reg_pc[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14721 Q=reg_pc[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14719 Q=reg_pc[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14717 Q=reg_pc[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14715 Q=reg_pc[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14713 Q=reg_pc[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14711 Q=reg_pc[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14709 Q=reg_pc[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14707 Q=reg_pc[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14705 Q=reg_pc[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14703 Q=reg_pc[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14701 Q=reg_pc[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14699 Q=reg_pc[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14697 Q=reg_pc[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14695 Q=reg_pc[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14693 Q=reg_pc[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14691 Q=reg_pc[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14689 Q=reg_pc[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14687 Q=reg_pc[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14685 Q=reg_pc[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14683 Q=reg_pc[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14681 Q=reg_pc[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14679 Q=reg_pc[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14677 Q=reg_pc[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14675 Q=reg_pc[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14673 Q=reg_pc[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15115 Q=reg_pc[31] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14671 Q=reg_next_pc[0] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14669 Q=reg_next_pc[1] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14667 Q=reg_next_pc[2] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14665 Q=reg_next_pc[3] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14663 Q=reg_next_pc[4] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14661 Q=reg_next_pc[5] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14659 Q=reg_next_pc[6] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14657 Q=reg_next_pc[7] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14655 Q=reg_next_pc[8] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14653 Q=reg_next_pc[9] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14651 Q=reg_next_pc[10] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14649 Q=reg_next_pc[11] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14647 Q=reg_next_pc[12] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14645 Q=reg_next_pc[13] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14643 Q=reg_next_pc[14] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14641 Q=reg_next_pc[15] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14639 Q=reg_next_pc[16] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14637 Q=reg_next_pc[17] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14635 Q=reg_next_pc[18] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14633 Q=reg_next_pc[19] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14631 Q=reg_next_pc[20] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14629 Q=reg_next_pc[21] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14627 Q=reg_next_pc[22] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14625 Q=reg_next_pc[23] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14623 Q=reg_next_pc[24] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14621 Q=reg_next_pc[25] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14619 Q=reg_next_pc[26] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14617 Q=reg_next_pc[27] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14615 Q=reg_next_pc[28] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14613 Q=reg_next_pc[29] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14611 Q=reg_next_pc[30] RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15117 Q=reg_next_pc[31] RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15109 Q=pcpi_rs1[31] +.subckt dff C=clk D=$0\reg_out[31:0][0] Q=reg_out[0] +.subckt dff C=clk D=$0\reg_out[31:0][1] Q=reg_out[1] +.subckt dff C=clk D=$0\reg_out[31:0][2] Q=reg_out[2] +.subckt dff C=clk D=$0\reg_out[31:0][3] Q=reg_out[3] +.subckt dff C=clk D=$0\reg_out[31:0][4] Q=reg_out[4] +.subckt dff C=clk D=$0\reg_out[31:0][5] Q=reg_out[5] +.subckt dff C=clk D=$0\reg_out[31:0][6] Q=reg_out[6] +.subckt dff C=clk D=$0\reg_out[31:0][7] Q=reg_out[7] +.subckt dff C=clk D=$0\reg_out[31:0][8] Q=reg_out[8] +.subckt dff C=clk D=$0\reg_out[31:0][9] Q=reg_out[9] +.subckt dff C=clk D=$0\reg_out[31:0][10] Q=reg_out[10] +.subckt dff C=clk D=$0\reg_out[31:0][11] Q=reg_out[11] +.subckt dff C=clk D=$0\reg_out[31:0][12] Q=reg_out[12] +.subckt dff C=clk D=$0\reg_out[31:0][13] Q=reg_out[13] +.subckt dff C=clk D=$0\reg_out[31:0][14] Q=reg_out[14] +.subckt dff C=clk D=$0\reg_out[31:0][15] Q=reg_out[15] +.subckt dff C=clk D=$0\reg_out[31:0][16] Q=reg_out[16] +.subckt dff C=clk D=$0\reg_out[31:0][17] Q=reg_out[17] +.subckt dff C=clk D=$0\reg_out[31:0][18] Q=reg_out[18] +.subckt dff C=clk D=$0\reg_out[31:0][19] Q=reg_out[19] +.subckt dff C=clk D=$0\reg_out[31:0][20] Q=reg_out[20] +.subckt dff C=clk D=$0\reg_out[31:0][21] Q=reg_out[21] +.subckt dff C=clk D=$0\reg_out[31:0][22] Q=reg_out[22] +.subckt dff C=clk D=$0\reg_out[31:0][23] Q=reg_out[23] +.subckt dff C=clk D=$0\reg_out[31:0][24] Q=reg_out[24] +.subckt dff C=clk D=$0\reg_out[31:0][25] Q=reg_out[25] +.subckt dff C=clk D=$0\reg_out[31:0][26] Q=reg_out[26] +.subckt dff C=clk D=$0\reg_out[31:0][27] Q=reg_out[27] +.subckt dff C=clk D=$0\reg_out[31:0][28] Q=reg_out[28] +.subckt dff C=clk D=$0\reg_out[31:0][29] Q=reg_out[29] +.subckt dff C=clk D=$0\reg_out[31:0][30] Q=reg_out[30] +.subckt dff C=clk D=$0\reg_out[31:0][31] Q=reg_out[31] +.subckt dff C=clk D=$0\reg_sh[4:0][0] Q=reg_sh[0] +.subckt dff C=clk D=$0\reg_sh[4:0][1] Q=reg_sh[1] +.subckt dff C=clk D=$0\reg_sh[4:0][2] Q=reg_sh[2] +.subckt dff C=clk D=$0\reg_sh[4:0][3] Q=reg_sh[3] +.subckt dff C=clk D=$0\reg_sh[4:0][4] Q=reg_sh[4] +.subckt sdffr C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15119 Q=mem_do_prefetch R=$abc$16053$auto$simplemap.cc:240:simplemap_eqne$5791[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14609 Q=mem_la_wdata[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14607 Q=mem_la_wdata[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14605 Q=mem_la_wdata[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14603 Q=mem_la_wdata[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14601 Q=mem_la_wdata[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14599 Q=mem_la_wdata[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14597 Q=mem_la_wdata[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14595 Q=mem_la_wdata[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14593 Q=pcpi_rs2[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14591 Q=pcpi_rs2[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14589 Q=pcpi_rs2[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14587 Q=pcpi_rs2[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14585 Q=pcpi_rs2[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14583 Q=pcpi_rs2[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14581 Q=pcpi_rs2[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14579 Q=pcpi_rs2[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14577 Q=pcpi_rs2[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14575 Q=pcpi_rs2[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14573 Q=pcpi_rs2[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14571 Q=pcpi_rs2[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14569 Q=pcpi_rs2[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14567 Q=pcpi_rs2[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14565 Q=pcpi_rs2[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14563 Q=pcpi_rs2[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14561 Q=pcpi_rs2[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14559 Q=pcpi_rs2[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14557 Q=pcpi_rs2[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14555 Q=pcpi_rs2[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14553 Q=pcpi_rs2[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14551 Q=pcpi_rs2[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14549 Q=pcpi_rs2[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15107 Q=pcpi_rs2[31] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15121 Q=mem_do_rinst S=$0\set_mem_do_rinst[0:0] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15123 Q=mem_do_rdata S=$0\set_mem_do_rdata[0:0] +.subckt sdffs C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15125 Q=mem_do_wdata S=$0\set_mem_do_wdata[0:0] +.subckt dff C=clk D=$0\decoder_trigger[0:0] Q=decoder_trigger +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15127 Q=latched_store RN=resetn +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[0] Q=cpu_state[0] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[1] Q=cpu_state[1] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[2] Q=cpu_state[2] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[3] Q=cpu_state[3] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[4] Q=cpu_state[4] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[5] Q=cpu_state[5] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffr C=clk D=$abc$16053$procmux$2235_Y[6] Q=cpu_state[6] R=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffs C=clk D=$abc$16053$procmux$2235_Y[7] Q=cpu_state[7] S=$abc$16053$logic_and$./benchmark/picorv32.v:1937$665_Y +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15129 Q=latched_stalu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15131 Q=latched_branch RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14547 Q=latched_rd[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14543 Q=latched_rd[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14539 Q=latched_rd[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14535 Q=latched_rd[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15201 Q=latched_rd[4] +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15133 Q=latched_is_lh RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15135 Q=latched_is_lb RN=resetn +.subckt dff C=clk D=alu_out[0] Q=alu_out_q[0] +.subckt dff C=clk D=alu_out[1] Q=alu_out_q[1] +.subckt dff C=clk D=alu_out[2] Q=alu_out_q[2] +.subckt dff C=clk D=alu_out[3] Q=alu_out_q[3] +.subckt dff C=clk D=alu_out[4] Q=alu_out_q[4] +.subckt dff C=clk D=alu_out[5] Q=alu_out_q[5] +.subckt dff C=clk D=alu_out[6] Q=alu_out_q[6] +.subckt dff C=clk D=alu_out[7] Q=alu_out_q[7] +.subckt dff C=clk D=alu_out[8] Q=alu_out_q[8] +.subckt dff C=clk D=alu_out[9] Q=alu_out_q[9] +.subckt dff C=clk D=alu_out[10] Q=alu_out_q[10] +.subckt dff C=clk D=alu_out[11] Q=alu_out_q[11] +.subckt dff C=clk D=alu_out[12] Q=alu_out_q[12] +.subckt dff C=clk D=alu_out[13] Q=alu_out_q[13] +.subckt dff C=clk D=alu_out[14] Q=alu_out_q[14] +.subckt dff C=clk D=alu_out[15] Q=alu_out_q[15] +.subckt dff C=clk D=alu_out[16] Q=alu_out_q[16] +.subckt dff C=clk D=alu_out[17] Q=alu_out_q[17] +.subckt dff C=clk D=alu_out[18] Q=alu_out_q[18] +.subckt dff C=clk D=alu_out[19] Q=alu_out_q[19] +.subckt dff C=clk D=alu_out[20] Q=alu_out_q[20] +.subckt dff C=clk D=alu_out[21] Q=alu_out_q[21] +.subckt dff C=clk D=alu_out[22] Q=alu_out_q[22] +.subckt dff C=clk D=alu_out[23] Q=alu_out_q[23] +.subckt dff C=clk D=alu_out[24] Q=alu_out_q[24] +.subckt dff C=clk D=alu_out[25] Q=alu_out_q[25] +.subckt dff C=clk D=alu_out[26] Q=alu_out_q[26] +.subckt dff C=clk D=alu_out[27] Q=alu_out_q[27] +.subckt dff C=clk D=alu_out[28] Q=alu_out_q[28] +.subckt dff C=clk D=alu_out[29] Q=alu_out_q[29] +.subckt dff C=clk D=alu_out[30] Q=alu_out_q[30] +.subckt dff C=clk D=alu_out[31] Q=alu_out_q[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15105 Q=instr_lui +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15103 Q=instr_auipc +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15101 Q=instr_jal +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15137 Q=instr_beq RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15139 Q=instr_bne RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15141 Q=instr_blt RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15143 Q=instr_bge RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15145 Q=instr_bltu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15147 Q=instr_bgeu RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15099 Q=instr_jalr +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15097 Q=instr_lb +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15095 Q=instr_lh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15093 Q=instr_lw +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15091 Q=instr_lbu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15089 Q=instr_lhu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15087 Q=instr_sb +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15085 Q=instr_sh +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15149 Q=instr_addi RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15151 Q=instr_slti RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15153 Q=instr_sltiu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15155 Q=instr_xori RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15157 Q=instr_ori RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15159 Q=instr_andi RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15083 Q=instr_sw +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15081 Q=instr_slli +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15079 Q=instr_srli +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15161 Q=instr_add RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15163 Q=instr_sub RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15165 Q=instr_sll RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15167 Q=instr_slt RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15169 Q=instr_sltu RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15171 Q=instr_xor RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15173 Q=instr_srl RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15175 Q=instr_sra RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15177 Q=instr_or RN=resetn +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15179 Q=instr_and RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15077 Q=instr_srai +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15075 Q=instr_rdcycle +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15073 Q=instr_rdcycleh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15071 Q=instr_rdinstr +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15181 Q=instr_fence RN=resetn +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15069 Q=instr_rdinstrh +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14531 Q=decoded_imm_j[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14529 Q=decoded_imm_j[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14527 Q=decoded_imm_j[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14525 Q=decoded_imm_j[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14523 Q=decoded_imm_j[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14521 Q=decoded_imm_j[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14519 Q=decoded_imm_j[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14517 Q=decoded_imm_j[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14515 Q=decoded_imm_j[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14513 Q=decoded_imm_j[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14511 Q=decoded_imm_j[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14509 Q=decoded_imm_j[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14507 Q=decoded_imm_j[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14505 Q=decoded_imm_j[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14503 Q=decoded_imm_j[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14501 Q=decoded_imm_j[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14499 Q=decoded_imm_j[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14497 Q=decoded_imm_j[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14495 Q=decoded_imm_j[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14493 Q=decoded_imm_j[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14491 Q=decoded_imm_j[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14489 Q=decoded_imm_j[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14487 Q=decoded_imm_j[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14485 Q=decoded_imm_j[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14483 Q=decoded_imm_j[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14481 Q=decoded_imm_j[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14479 Q=decoded_imm_j[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14477 Q=decoded_imm_j[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14475 Q=decoded_imm_j[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14473 Q=decoded_imm_j[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15185 Q=decoded_imm_j[31] +.subckt dff C=clk D=$0\decoded_rs1[4:0][0] Q=decoded_rs1[0] +.subckt dff C=clk D=$0\decoded_rs1[4:0][1] Q=decoded_rs1[1] +.subckt dff C=clk D=$0\decoded_rs1[4:0][2] Q=decoded_rs1[2] +.subckt dff C=clk D=$0\decoded_rs1[4:0][3] Q=decoded_rs1[3] +.subckt dff C=clk D=$0\decoded_rs1[4:0][4] Q=decoded_rs1[4] +.subckt dff C=clk D=$0\decoded_rs2[4:0][0] Q=decoded_rs2[0] +.subckt dff C=clk D=$0\decoded_rs2[4:0][1] Q=decoded_rs2[1] +.subckt dff C=clk D=$0\decoded_rs2[4:0][2] Q=decoded_rs2[2] +.subckt dff C=clk D=$0\decoded_rs2[4:0][3] Q=decoded_rs2[3] +.subckt dff C=clk D=$0\decoded_rs2[4:0][4] Q=decoded_rs2[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14471 Q=decoded_rd[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14469 Q=decoded_rd[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14467 Q=decoded_rd[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14465 Q=decoded_rd[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15067 Q=decoded_rd[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14463 Q=decoded_imm[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14461 Q=decoded_imm[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14459 Q=decoded_imm[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14457 Q=decoded_imm[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14455 Q=decoded_imm[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14453 Q=decoded_imm[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14451 Q=decoded_imm[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14449 Q=decoded_imm[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14447 Q=decoded_imm[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14445 Q=decoded_imm[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14443 Q=decoded_imm[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14441 Q=decoded_imm[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14439 Q=decoded_imm[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14437 Q=decoded_imm[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14435 Q=decoded_imm[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14433 Q=decoded_imm[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14431 Q=decoded_imm[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14429 Q=decoded_imm[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14427 Q=decoded_imm[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14425 Q=decoded_imm[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14423 Q=decoded_imm[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14421 Q=decoded_imm[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14419 Q=decoded_imm[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14417 Q=decoded_imm[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14415 Q=decoded_imm[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14413 Q=decoded_imm[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14411 Q=decoded_imm[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14409 Q=decoded_imm[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14407 Q=decoded_imm[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14405 Q=decoded_imm[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14403 Q=decoded_imm[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15065 Q=decoded_imm[31] +.subckt dff C=clk D=$0\is_lui_auipc_jal[0:0] Q=is_lui_auipc_jal +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15063 Q=is_lb_lh_lw_lbu_lhu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15061 Q=is_slli_srli_srai +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15059 Q=is_jalr_addi_slti_sltiu_xori_ori_andi +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15057 Q=is_sb_sh_sw +.subckt sdffrn C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15183 Q=is_beq_bne_blt_bge_bltu_bgeu RN=resetn +.subckt dff C=clk D=$0\is_slti_blt_slt[0:0] Q=is_slti_blt_slt +.subckt dff C=clk D=$0\is_sltiu_bltu_sltu[0:0] Q=is_sltiu_bltu_sltu +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15055 Q=is_sll_srl_sra +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15053 Q=is_alu_reg_imm +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15051 Q=is_alu_reg_reg +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15049 Q=mem_instr +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14401 Q=mem_state[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15193 Q=mem_state[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14397 Q=mem_wdata[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14395 Q=mem_wdata[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14393 Q=mem_wdata[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14391 Q=mem_wdata[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14389 Q=mem_wdata[4] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14387 Q=mem_wdata[5] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14385 Q=mem_wdata[6] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14383 Q=mem_wdata[7] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14381 Q=mem_wdata[8] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14379 Q=mem_wdata[9] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14377 Q=mem_wdata[10] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14375 Q=mem_wdata[11] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14373 Q=mem_wdata[12] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14371 Q=mem_wdata[13] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14369 Q=mem_wdata[14] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14367 Q=mem_wdata[15] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14365 Q=mem_wdata[16] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14363 Q=mem_wdata[17] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14361 Q=mem_wdata[18] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14359 Q=mem_wdata[19] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14357 Q=mem_wdata[20] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14355 Q=mem_wdata[21] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14353 Q=mem_wdata[22] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14351 Q=mem_wdata[23] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14349 Q=mem_wdata[24] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14347 Q=mem_wdata[25] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14345 Q=mem_wdata[26] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14343 Q=mem_wdata[27] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14341 Q=mem_wdata[28] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14339 Q=mem_wdata[29] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14337 Q=mem_wdata[30] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15045 Q=mem_wdata[31] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14335 Q=mem_wstrb[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14333 Q=mem_wstrb[1] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$14331 Q=mem_wstrb[2] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15043 Q=mem_wstrb[3] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15207 Q=mem_wordsize[0] +.subckt dff C=clk D=$abc$16053$auto$rtlil.cc:2693:MuxGate$15197 Q=mem_wordsize[1] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4910[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4926[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4926[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4926[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4926[35] raddr_i[7]=$0\decoded_rs2[4:0][0] raddr_i[6]=$0\decoded_rs2[4:0][1] raddr_i[5]=$0\decoded_rs2[4:0][2] raddr_i[4]=$0\decoded_rs2[4:0][3] raddr_i[3]=$0\decoded_rs2[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +.subckt dpram256x36 bwen_ni[35]=$true bwen_ni[34]=$false bwen_ni[33]=$false bwen_ni[32]=$false bwen_ni[31]=$false bwen_ni[30]=$false bwen_ni[29]=$false bwen_ni[28]=$false bwen_ni[27]=$false bwen_ni[26]=$false bwen_ni[25]=$false bwen_ni[24]=$false bwen_ni[23]=$false bwen_ni[22]=$false bwen_ni[21]=$false bwen_ni[20]=$false bwen_ni[19]=$false bwen_ni[18]=$false bwen_ni[17]=$false bwen_ni[16]=$false bwen_ni[15]=$false bwen_ni[14]=$false bwen_ni[13]=$false bwen_ni[12]=$false bwen_ni[11]=$false bwen_ni[10]=$false bwen_ni[9]=$false bwen_ni[8]=$false bwen_ni[7]=$false bwen_ni[6]=$false bwen_ni[5]=$false bwen_ni[4]=$false bwen_ni[3]=$false bwen_ni[2]=$false bwen_ni[1]=$false bwen_ni[0]=$false data_i[35]=cpuregs_wrdata[0] data_i[34]=cpuregs_wrdata[1] data_i[33]=cpuregs_wrdata[2] data_i[32]=cpuregs_wrdata[3] data_i[31]=cpuregs_wrdata[4] data_i[30]=cpuregs_wrdata[5] data_i[29]=cpuregs_wrdata[6] data_i[28]=cpuregs_wrdata[7] data_i[27]=cpuregs_wrdata[8] data_i[26]=cpuregs_wrdata[9] data_i[25]=cpuregs_wrdata[10] data_i[24]=cpuregs_wrdata[11] data_i[23]=cpuregs_wrdata[12] data_i[22]=cpuregs_wrdata[13] data_i[21]=cpuregs_wrdata[14] data_i[20]=cpuregs_wrdata[15] data_i[19]=cpuregs_wrdata[16] data_i[18]=cpuregs_wrdata[17] data_i[17]=cpuregs_wrdata[18] data_i[16]=cpuregs_wrdata[19] data_i[15]=cpuregs_wrdata[20] data_i[14]=cpuregs_wrdata[21] data_i[13]=cpuregs_wrdata[22] data_i[12]=cpuregs_wrdata[23] data_i[11]=cpuregs_wrdata[24] data_i[10]=cpuregs_wrdata[25] data_i[9]=cpuregs_wrdata[26] data_i[8]=cpuregs_wrdata[27] data_i[7]=cpuregs_wrdata[28] data_i[6]=cpuregs_wrdata[29] data_i[5]=cpuregs_wrdata[30] data_i[4]=cpuregs_wrdata[31] data_i[3]=$undef data_i[2]=$undef data_i[1]=$undef data_i[0]=$undef q_o[35]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[0] q_o[34]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[1] q_o[33]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[2] q_o[32]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[3] q_o[31]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[4] q_o[30]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[5] q_o[29]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[6] q_o[28]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[7] q_o[27]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[8] q_o[26]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[9] q_o[25]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[10] q_o[24]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[11] q_o[23]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[12] q_o[22]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[13] q_o[21]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[14] q_o[20]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[15] q_o[19]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[16] q_o[18]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[17] q_o[17]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[18] q_o[16]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[19] q_o[15]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[20] q_o[14]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] q_o[13]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] q_o[12]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] q_o[11]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] q_o[10]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] q_o[9]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] q_o[8]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] q_o[7]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] q_o[6]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] q_o[5]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] q_o[4]=$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] q_o[3]=$auto$memory_bram.cc:844:replace_memory$4927[32] q_o[2]=$auto$memory_bram.cc:844:replace_memory$4927[33] q_o[1]=$auto$memory_bram.cc:844:replace_memory$4927[34] q_o[0]=$auto$memory_bram.cc:844:replace_memory$4927[35] raddr_i[7]=$0\decoded_rs1[4:0][0] raddr_i[6]=$0\decoded_rs1[4:0][1] raddr_i[5]=$0\decoded_rs1[4:0][2] raddr_i[4]=$0\decoded_rs1[4:0][3] raddr_i[3]=$0\decoded_rs1[4:0][4] raddr_i[2]=$false raddr_i[1]=$false raddr_i[0]=$false rclk_i=clk ren_ni=$true waddr_i[7]=latched_rd[0] waddr_i[6]=latched_rd[1] waddr_i[5]=latched_rd[2] waddr_i[4]=latched_rd[3] waddr_i[3]=latched_rd[4] waddr_i[2]=$false waddr_i[1]=$false waddr_i[0]=$false wclk_i=clk wen_ni=$0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[0] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[1] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[2] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[3] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[4] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[5] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[6] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[7] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[8] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[9] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[10] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[11] +1 1 +.names $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[31] $0$memwr$\cpuregs$./benchmark/picorv32.v:1343$17_EN[31:0]$487[12] +1 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$abc$16053$auto$mem.cc:1162:emulate_transparency$4920[21] $auto$memory_bram.cc:844:replace_memory$4927[21] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[22] $auto$memory_bram.cc:844:replace_memory$4927[22] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[23] $auto$memory_bram.cc:844:replace_memory$4927[23] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[24] $auto$memory_bram.cc:844:replace_memory$4927[24] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[25] $auto$memory_bram.cc:844:replace_memory$4927[25] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[26] $auto$memory_bram.cc:844:replace_memory$4927[26] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[27] $auto$memory_bram.cc:844:replace_memory$4927[27] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[28] $auto$memory_bram.cc:844:replace_memory$4927[28] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[29] $auto$memory_bram.cc:844:replace_memory$4927[29] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[30] $auto$memory_bram.cc:844:replace_memory$4927[30] +1 1 +.names $abc$16053$auto$mem.cc:1162:emulate_transparency$4920[31] $auto$memory_bram.cc:844:replace_memory$4927[31] +1 1 +.names $false decoded_imm_j[0] +1 1 +.names $false eoi[0] +1 1 +.names $false eoi[1] +1 1 +.names $false eoi[2] +1 1 +.names $false eoi[3] +1 1 +.names $false eoi[4] +1 1 +.names $false eoi[5] +1 1 +.names $false eoi[6] +1 1 +.names $false eoi[7] +1 1 +.names $false eoi[8] +1 1 +.names $false eoi[9] +1 1 +.names $false eoi[10] +1 1 +.names $false eoi[11] +1 1 +.names $false eoi[12] +1 1 +.names $false eoi[13] +1 1 +.names $false eoi[14] +1 1 +.names $false eoi[15] +1 1 +.names $false eoi[16] +1 1 +.names $false eoi[17] +1 1 +.names $false eoi[18] +1 1 +.names $false eoi[19] +1 1 +.names $false eoi[20] +1 1 +.names $false eoi[21] +1 1 +.names $false eoi[22] +1 1 +.names $false eoi[23] +1 1 +.names $false eoi[24] +1 1 +.names $false eoi[25] +1 1 +.names $false eoi[26] +1 1 +.names $false eoi[27] +1 1 +.names $false eoi[28] +1 1 +.names $false eoi[29] +1 1 +.names $false eoi[30] +1 1 +.names $false eoi[31] +1 1 +.names $false mem_addr[0] +1 1 +.names $false mem_addr[1] +1 1 +.names $false mem_la_addr[0] +1 1 +.names $false mem_la_addr[1] +1 1 +.names $undef pcpi_insn[0] +1 1 +.names $undef pcpi_insn[1] +1 1 +.names $undef pcpi_insn[2] +1 1 +.names $undef pcpi_insn[3] +1 1 +.names $undef pcpi_insn[4] +1 1 +.names $undef pcpi_insn[5] +1 1 +.names $undef pcpi_insn[6] +1 1 +.names $undef pcpi_insn[7] +1 1 +.names $undef pcpi_insn[8] +1 1 +.names $undef pcpi_insn[9] +1 1 +.names $undef pcpi_insn[10] +1 1 +.names $undef pcpi_insn[11] +1 1 +.names $undef pcpi_insn[12] +1 1 +.names $undef pcpi_insn[13] +1 1 +.names $undef pcpi_insn[14] +1 1 +.names $undef pcpi_insn[15] +1 1 +.names $undef pcpi_insn[16] +1 1 +.names $undef pcpi_insn[17] +1 1 +.names $undef pcpi_insn[18] +1 1 +.names $undef pcpi_insn[19] +1 1 +.names $undef pcpi_insn[20] +1 1 +.names $undef pcpi_insn[21] +1 1 +.names $undef pcpi_insn[22] +1 1 +.names $undef pcpi_insn[23] +1 1 +.names $undef pcpi_insn[24] +1 1 +.names $undef pcpi_insn[25] +1 1 +.names $undef pcpi_insn[26] +1 1 +.names $undef pcpi_insn[27] +1 1 +.names $undef pcpi_insn[28] +1 1 +.names $undef pcpi_insn[29] +1 1 +.names $undef pcpi_insn[30] +1 1 +.names $undef pcpi_insn[31] +1 1 +.names mem_la_wdata[0] pcpi_rs2[0] +1 1 +.names mem_la_wdata[1] pcpi_rs2[1] +1 1 +.names mem_la_wdata[2] pcpi_rs2[2] +1 1 +.names mem_la_wdata[3] pcpi_rs2[3] +1 1 +.names mem_la_wdata[4] pcpi_rs2[4] +1 1 +.names mem_la_wdata[5] pcpi_rs2[5] +1 1 +.names mem_la_wdata[6] pcpi_rs2[6] +1 1 +.names mem_la_wdata[7] pcpi_rs2[7] +1 1 +.names $false pcpi_valid +1 1 +.names $undef trace_data[0] +1 1 +.names $undef trace_data[1] +1 1 +.names $undef trace_data[2] +1 1 +.names $undef trace_data[3] +1 1 +.names $undef trace_data[4] +1 1 +.names $undef trace_data[5] +1 1 +.names $undef trace_data[6] +1 1 +.names $undef trace_data[7] +1 1 +.names $undef trace_data[8] +1 1 +.names $undef trace_data[9] +1 1 +.names $undef trace_data[10] +1 1 +.names $undef trace_data[11] +1 1 +.names $undef trace_data[12] +1 1 +.names $undef trace_data[13] +1 1 +.names $undef trace_data[14] +1 1 +.names $undef trace_data[15] +1 1 +.names $undef trace_data[16] +1 1 +.names $undef trace_data[17] +1 1 +.names $undef trace_data[18] +1 1 +.names $undef trace_data[19] +1 1 +.names $undef trace_data[20] +1 1 +.names $undef trace_data[21] +1 1 +.names $undef trace_data[22] +1 1 +.names $undef trace_data[23] +1 1 +.names $undef trace_data[24] +1 1 +.names $undef trace_data[25] +1 1 +.names $undef trace_data[26] +1 1 +.names $undef trace_data[27] +1 1 +.names $undef trace_data[28] +1 1 +.names $undef trace_data[29] +1 1 +.names $undef trace_data[30] +1 1 +.names $undef trace_data[31] +1 1 +.names $undef trace_data[32] +1 1 +.names $undef trace_data[33] +1 1 +.names $undef trace_data[34] +1 1 +.names $undef trace_data[35] +1 1 +.names $false trace_valid +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif new file mode 100644 index 00000000000..6944f7510e3 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/pong.blif @@ -0,0 +1,1394 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model pong +.inputs clk quadA quadB +.outputs vga_h_sync vga_v_sync vga_R vga_G vga_B +.names $false +.names $true +1 +.names $undef +.names ballY[7] ball_dirY ballY[6] $abc$3008$new_n130 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2661 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[5] $abc$3008$new_n131 ball_dirY ballY[4] $abc$3008$new_n130 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names ballY[4] ball_dirY ballY[3] $abc$3008$new_n132 $abc$3008$new_n131 +0100 1 +0110 1 +0111 1 +1010 1 +.names ball_dirY ballY[0] ballY[1] ballY[2] $abc$3008$new_n132 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names ResetCollision CollisionY2 CollisionY1 $abc$3008$new_n133 +100 1 +101 1 +110 1 +.names ballY[6] ball_dirY $abc$3008$new_n130 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2663 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballY[5] ball_dirY $abc$3008$new_n131 $abc$3008$new_n133 ballY[4] $abc$3008$auto$rtlil.cc:2693:MuxGate$2665 +00110 1 +00111 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[4] ball_dirY ballY[3] $abc$3008$new_n132 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2667 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[3] ball_dirY $abc$3008$new_n132 $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2669 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballY[2] ball_dirY ballY[0] ballY[1] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2671 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballY[1] ball_dirY ballY[0] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2673 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names ballY[0] $abc$3008$new_n133 $abc$3008$auto$rtlil.cc:2693:MuxGate$2675 +01 1 +10 1 +.names ballX[8] ball_dirX $abc$3008$new_n142 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2677 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$3008$new_n146 ball_dirX ballX[6] ballX[7] $abc$3008$new_n143 $abc$3008$new_n142 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names ball_dirX ballX[4] ballX[5] $abc$3008$new_n144 $abc$3008$new_n143 +0110 1 +1000 1 +.names ball_dirX ballX[3] $abc$3008$new_n145 $abc$3008$new_n144 +000 1 +001 1 +011 1 +101 1 +.names ball_dirX ballX[0] ballX[1] ballX[2] $abc$3008$new_n145 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names ball_dirX ballX[5] ballX[4] $abc$3008$new_n146 +000 1 +001 1 +010 1 +011 1 +100 1 +.names ResetCollision CollisionX2 CollisionX1 $abc$3008$new_n147 +100 1 +101 1 +110 1 +.names ballX[7] ball_dirX ballX[6] $abc$3008$new_n149 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2679 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n146 $abc$3008$new_n143 $abc$3008$new_n149 +10 1 +.names ballX[6] ball_dirX $abc$3008$new_n149 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2681 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[5] ball_dirX ballX[4] $abc$3008$new_n144 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2683 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballX[4] ball_dirX $abc$3008$new_n144 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2685 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[3] ball_dirX $abc$3008$new_n145 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2687 +0001 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ballX[2] ball_dirX ballX[0] ballX[1] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2689 +00111 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ballX[1] ball_dirX ballX[0] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2691 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names ballX[0] $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2693 +01 1 +10 1 +.names CounterY[7] CounterY[4] CounterY[5] CounterY[6] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2695 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterY[0] CounterY[1] CounterY[2] CounterY[3] syncgen.CounterXmaxed $abc$3008$new_n158 +11111 1 +.names CounterX[7] $abc$3008$new_n162 $abc$3008$new_n160 syncgen.CounterXmaxed +111 1 +.names CounterX[6] CounterX[4] CounterX[5] $abc$3008$new_n161 $abc$3008$new_n160 +1111 1 +.names CounterX[1] CounterX[0] CounterX[2] CounterX[3] $abc$3008$new_n161 +1111 1 +.names CounterX[9] CounterX[8] $abc$3008$new_n162 +10 1 +.names CounterY[6] CounterY[4] CounterY[5] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2697 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterY[5] CounterY[4] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2699 +011 1 +100 1 +101 1 +110 1 +.names CounterY[4] $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2701 +01 1 +10 1 +.names CounterY[3] CounterY[0] CounterY[1] CounterY[2] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2703 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterY[2] CounterY[0] CounterY[1] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2705 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterY[1] CounterY[0] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2707 +011 1 +100 1 +101 1 +110 1 +.names CounterY[0] syncgen.CounterXmaxed $abc$3008$auto$rtlil.cc:2693:MuxGate$2709 +01 1 +10 1 +.names PaddlePosition[7] $abc$3008$new_n171 $abc$3008$new_n172 $abc$3008$new_n181 $abc$3008$new_n179 $abc$3008$auto$rtlil.cc:2693:MuxGate$2711 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names $abc$3008$new_n176 PaddlePosition[7] $abc$3008$new_n172 PaddlePosition[8] $abc$3008$new_n171 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$3008$new_n175 $abc$3008$new_n173 $abc$3008$new_n172 +11 1 +.names PaddlePosition[5] PaddlePosition[6] $abc$3008$new_n174 $abc$3008$new_n173 +111 1 +.names PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n174 +11 1 +.names PaddlePosition[1] PaddlePosition[2] PaddlePosition[0] quadBr[1] quadAr[2] $abc$3008$new_n175 +11101 1 +11110 1 +.names quadBr[2] quadAr[1] quadBr[1] quadAr[2] $abc$3008$new_n177 $abc$3008$new_n176 +00000 1 +00001 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$3008$new_n178 PaddlePosition[8] PaddlePosition[0] PaddlePosition[1] PaddlePosition[2] $abc$3008$new_n177 +10000 1 +.names PaddlePosition[3] PaddlePosition[4] PaddlePosition[5] PaddlePosition[6] PaddlePosition[7] $abc$3008$new_n178 +00000 1 +.names $abc$3008$new_n180 PaddlePosition[5] PaddlePosition[6] $abc$3008$new_n179 +100 1 +.names PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n180 +00 1 +.names quadBr[1] quadAr[2] PaddlePosition[0] PaddlePosition[1] PaddlePosition[2] $abc$3008$new_n181 +00000 1 +11000 1 +.names PaddlePosition[6] $abc$3008$new_n171 $abc$3008$new_n183 $abc$3008$auto$rtlil.cc:2693:MuxGate$2713 +010 1 +100 1 +101 1 +111 1 +.names PaddlePosition[3] PaddlePosition[4] PaddlePosition[5] $abc$3008$new_n175 $abc$3008$new_n181 $abc$3008$new_n183 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names PaddlePosition[5] $abc$3008$new_n185 $abc$3008$auto$rtlil.cc:2693:MuxGate$2715 +01 1 +10 1 +.names $abc$3008$new_n171 PaddlePosition[3] PaddlePosition[4] $abc$3008$new_n175 $abc$3008$new_n181 $abc$3008$new_n185 +10001 1 +10011 1 +11110 1 +11111 1 +.names PaddlePosition[4] PaddlePosition[3] $abc$3008$new_n171 $abc$3008$new_n181 $abc$3008$new_n175 $abc$3008$auto$rtlil.cc:2693:MuxGate$2717 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names PaddlePosition[3] $abc$3008$new_n171 $abc$3008$new_n181 $abc$3008$new_n175 $abc$3008$auto$rtlil.cc:2693:MuxGate$2719 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names PaddlePosition[2] $abc$3008$new_n189 $abc$3008$auto$rtlil.cc:2693:MuxGate$2721 +01 1 +10 1 +.names $abc$3008$new_n171 quadBr[1] quadAr[2] PaddlePosition[0] PaddlePosition[1] $abc$3008$new_n189 +10000 1 +10111 1 +11011 1 +11100 1 +.names PaddlePosition[1] quadBr[1] quadAr[2] PaddlePosition[0] $abc$3008$new_n171 $abc$3008$auto$rtlil.cc:2693:MuxGate$2723 +00001 1 +00111 1 +01011 1 +01101 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names PaddlePosition[0] $abc$3008$new_n171 $abc$3008$auto$rtlil.cc:2693:MuxGate$2725 +01 1 +10 1 +.names PaddlePosition[8] $abc$3008$new_n193 $abc$3008$auto$rtlil.cc:2693:MuxGate$2727 +01 1 +10 1 +.names $abc$3008$new_n171 $abc$3008$new_n194 quadBr[1] quadAr[2] PaddlePosition[7] $abc$3008$new_n193 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names $abc$3008$new_n172 $abc$3008$new_n178 PaddlePosition[1] PaddlePosition[2] PaddlePosition[0] $abc$3008$new_n194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names ball_dirY ResetCollision CollisionY2 CollisionY1 $abc$3008$auto$rtlil.cc:2693:MuxGate$2731 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names ball_dirX ResetCollision CollisionX2 CollisionX1 $abc$3008$auto$rtlil.cc:2693:MuxGate$2735 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names ballX[9] ball_dirX ballX[8] $abc$3008$new_n142 $abc$3008$new_n147 $abc$3008$auto$rtlil.cc:2693:MuxGate$2739 +00101 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterY[8] $abc$3008$new_n203 $abc$3008$new_n158 $abc$3008$auto$rtlil.cc:2693:MuxGate$2741 +011 1 +100 1 +101 1 +110 1 +.names CounterY[4] CounterY[5] CounterY[6] CounterY[7] $abc$3008$new_n203 +1111 1 +.names CollisionY2 $abc$3008$new_n205 $abc$3008$new_n250 $abc$3008$auto$rtlil.cc:2693:MuxGate$2743 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n231 $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n206 $abc$3008$new_n220 $abc$3008$new_n205 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$3008$new_n219 CounterX[7] $abc$3008$new_n208 $abc$3008$new_n207 $abc$3008$new_n218 $abc$3008$new_n206 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$3008$new_n179 PaddlePosition[7] $abc$3008$new_n207 +00 1 +11 1 +.names $abc$3008$new_n216 $abc$3008$new_n217 $abc$3008$new_n215 $abc$3008$new_n209 $abc$3008$new_n211 $abc$3008$new_n208 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names PaddlePosition[2] CounterX[2] CounterX[3] PaddlePosition[3] $abc$3008$new_n210 $abc$3008$new_n209 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names PaddlePosition[0] CounterX[0] CounterX[1] PaddlePosition[1] $abc$3008$new_n210 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$3008$new_n214 $abc$3008$new_n212 $abc$3008$new_n213 CounterX[0] PaddlePosition[0] $abc$3008$new_n211 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +.names CounterX[3] CounterX[2] PaddlePosition[2] PaddlePosition[3] $abc$3008$new_n212 +0001 1 +0111 1 +1000 1 +1110 1 +.names CounterX[1] PaddlePosition[1] $abc$3008$new_n213 +00 1 +11 1 +.names PaddlePosition[4] PaddlePosition[3] CounterX[4] $abc$3008$new_n214 +000 1 +110 1 +.names $abc$3008$new_n180 PaddlePosition[5] PaddlePosition[6] CounterX[6] CounterX[5] $abc$3008$new_n215 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names CounterX[6] PaddlePosition[6] $abc$3008$new_n180 PaddlePosition[5] $abc$3008$new_n216 +1000 1 +1001 1 +1011 1 +1110 1 +.names PaddlePosition[3] PaddlePosition[4] CounterX[5] PaddlePosition[5] CounterX[4] $abc$3008$new_n217 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01110 1 +10000 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names CounterX[8] PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n179 $abc$3008$new_n218 +1000 1 +1001 1 +1011 1 +1110 1 +.names PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n179 CounterX[8] CounterX[9] $abc$3008$new_n219 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$3008$new_n226 $abc$3008$new_n223 $abc$3008$new_n225 $abc$3008$new_n221 $abc$3008$new_n227 $abc$3008$new_n220 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$3008$new_n222 PaddlePosition[3] PaddlePosition[4] CounterX[4] $abc$3008$new_n209 $abc$3008$new_n221 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +.names CounterX[5] PaddlePosition[5] $abc$3008$new_n174 $abc$3008$new_n222 +100 1 +111 1 +.names PaddlePosition[6] $abc$3008$new_n224 CounterX[7] PaddlePosition[7] CounterX[6] $abc$3008$new_n223 +00000 1 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +.names PaddlePosition[5] $abc$3008$new_n174 $abc$3008$new_n224 +11 1 +.names PaddlePosition[7] $abc$3008$new_n173 PaddlePosition[8] CounterX[8] CounterX[7] $abc$3008$new_n225 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterX[9] PaddlePosition[8] $abc$3008$new_n173 CounterX[8] $abc$3008$new_n226 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names PaddlePosition[5] $abc$3008$new_n174 PaddlePosition[6] CounterX[6] CounterX[5] $abc$3008$new_n227 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01111 1 +10001 1 +10011 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n230 $abc$3008$new_n229 $abc$3008$new_n228 +11 1 +.names CounterX[9] PaddlePosition[8] PaddlePosition[7] $abc$3008$new_n173 $abc$3008$new_n179 $abc$3008$new_n229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +11100 1 +11110 1 +.names CounterY[8] CounterY[4] CounterY[5] CounterY[7] CounterY[6] $abc$3008$new_n230 +11110 1 +.names $abc$3008$new_n243 $abc$3008$new_n232 $abc$3008$new_n244 $abc$3008$new_n278 $abc$3008$new_n239 $abc$3008$new_n231 +11100 1 +.names $abc$3008$new_n235 $abc$3008$new_n237 ballX[3] CounterX[3] $abc$3008$new_n280 $abc$3008$new_n232 +11010 1 +11011 1 +11100 1 +.names ballX[4] ballX[5] ballX[6] ballX[7] $abc$3008$new_n234 +1111 1 +.names $abc$3008$new_n236 CounterX[1] ballX[1] $abc$3008$new_n235 +100 1 +111 1 +.names CounterX[0] ballX[0] CounterX[2] ballX[2] $abc$3008$new_n236 +0000 1 +0011 1 +1100 1 +1111 1 +.names ballX[3] $abc$3008$new_n238 CounterX[8] ballX[8] $abc$3008$new_n234 $abc$3008$new_n237 +01000 1 +01001 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +.names CounterX[4] ballX[4] $abc$3008$new_n238 +00 1 +11 1 +.names $abc$3008$new_n240 ballX[3] ballX[4] ballX[5] ballX[6] $abc$3008$new_n239 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +11111 1 +.names CounterX[7] ballX[7] $abc$3008$new_n240 +00 1 +11 1 +.names CounterX[6] ballX[6] ballX[3] ballX[4] ballX[5] $abc$3008$new_n243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names CounterX[5] ballX[5] ballX[3] ballX[4] $abc$3008$new_n244 +0000 1 +0001 1 +0010 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[8] CounterX[7] $abc$3008$new_n246 +00 1 +.names CounterX[6] CounterX[4] CounterX[5] CounterX[3] CounterX[9] $abc$3008$new_n247 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$3008$new_n251 $abc$3008$new_n260 $abc$3008$new_n257 $abc$3008$new_n259 $abc$3008$new_n250 +1001 1 +1110 1 +1111 1 +.names $abc$3008$new_n252 $abc$3008$new_n255 CounterY[8] ballY[8] $abc$3008$new_n256 $abc$3008$new_n251 +11000 1 +11101 1 +11110 1 +.names $abc$3008$new_n253 CounterY[3] ballY[3] $abc$3008$new_n252 +100 1 +111 1 +.names $abc$3008$new_n254 CounterY[0] ballY[0] $abc$3008$new_n253 +100 1 +111 1 +.names CounterY[1] ballY[1] CounterY[2] ballY[2] $abc$3008$new_n254 +0000 1 +0011 1 +1100 1 +1111 1 +.names CounterY[4] CounterY[5] ballY[4] ballY[5] $abc$3008$new_n255 +0011 1 +0110 1 +1000 1 +1101 1 +.names ballY[4] ballY[5] ballY[6] ballY[7] $abc$3008$new_n256 +1111 1 +.names $abc$3008$new_n258 CounterY[7] ballY[7] $abc$3008$new_n259 $abc$3008$new_n257 +0000 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ballY[6] CounterY[6] $abc$3008$new_n258 +10 1 +.names ballY[4] ballY[5] $abc$3008$new_n259 +11 1 +.names CounterY[7] ballY[7] CounterY[6] ballY[6] $abc$3008$new_n260 +0000 1 +0001 1 +0011 1 +1100 1 +1101 1 +1111 1 +.names CollisionY1 $abc$3008$new_n205 $abc$3008$new_n262 $abc$3008$auto$rtlil.cc:2693:MuxGate$2745 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n252 $abc$3008$new_n263 CounterY[8] ballY[8] $abc$3008$new_n258 $abc$3008$new_n262 +11000 1 +11110 1 +.names $abc$3008$new_n260 CounterY[4] ballY[4] CounterY[5] ballY[5] $abc$3008$new_n263 +10000 1 +10011 1 +11100 1 +11111 1 +.names CollisionX2 $abc$3008$new_n324 $abc$3008$new_n326 $abc$3008$auto$rtlil.cc:2693:MuxGate$2747 +011 1 +100 1 +101 1 +110 1 +111 1 +.names CounterY[8] ballY[8] CounterY[4] ballY[4] $abc$3008$new_n258 $abc$3008$new_n271 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$3008$new_n255 CounterY[5] ballY[5] ballY[3] $abc$3008$new_n272 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names $abc$3008$new_n235 CounterX[3] ballX[3] $abc$3008$new_n274 +100 1 +111 1 +.names ballX[9] CounterX[9] ballX[8] CounterX[8] $abc$3008$new_n278 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names CounterX[4] CounterX[5] ballX[4] ballX[5] $abc$3008$new_n279 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names $abc$3008$new_n234 CounterX[9] ballX[9] CounterX[8] ballX[8] $abc$3008$new_n280 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11111 1 +.names CollisionX1 $abc$3008$new_n324 $abc$3008$new_n283 $abc$3008$auto$rtlil.cc:2693:MuxGate$2749 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$3008$new_n284 $abc$3008$new_n274 $abc$3008$new_n238 CounterX[9] ballX[9] $abc$3008$new_n283 +11100 1 +11111 1 +.names $abc$3008$new_n285 $abc$3008$new_n240 CounterX[5] ballX[5] $abc$3008$new_n284 +1100 1 +1111 1 +.names ballX[6] CounterX[6] CounterX[8] ballX[8] $abc$3008$new_n285 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$3008$new_n287 $abc$3008$new_n203 $abc$3008$eq$./benchmark/pong.v:56$43_Y +11 1 +.names CounterY[8] CounterY[2] CounterY[0] CounterY[1] CounterY[3] $abc$3008$new_n287 +11000 1 +.names CounterX[7] CounterX[6] CounterX[4] $abc$3008$new_n162 CounterX[5] $abc$3008$flatten\syncgen.$0\vga_HS[0:0] +11110 1 +.names inDisplayArea CounterX[7] $abc$3008$new_n162 $abc$3008$new_n160 $abc$3008$new_n290 $abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names CounterY[8] CounterY[5] CounterY[6] CounterY[7] $abc$3008$new_n290 +1111 1 +.names ball_inY $abc$3008$new_n250 $abc$3008$new_n262 $0\ball_inY[0:0] +001 1 +011 1 +100 1 +101 1 +.names ball_inX $abc$3008$new_n326 ball_inY $abc$3008$new_n283 $0\ball_inX[0:0] +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$3008$new_n294 $abc$3008$eq$./benchmark/pong.v:56$43_Y $0\ResetCollision[0:0] +11 1 +.names $abc$3008$new_n246 $abc$3008$new_n295 CounterX[1] CounterX[0] CounterX[2] $abc$3008$new_n294 +11000 1 +.names CounterX[6] CounterX[4] CounterX[5] CounterX[3] CounterX[9] $abc$3008$new_n295 +00000 1 +.names inDisplayArea $abc$3008$new_n297 $abc$3008$new_n298 ball_inX ball_inY $0\vga_R[0:0] +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n206 $abc$3008$new_n220 $abc$3008$new_n297 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names CounterX[3] CounterY[3] $abc$3008$new_n298 +00 1 +11 1 +.names inDisplayArea $abc$3008$new_n297 ball_inX ball_inY $0\vga_B[0:0] +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[1] +01 1 +10 1 +.names CounterX[2] CounterX[1] CounterX[0] $auto$alumacc.cc:485:replace_alu$666.Y[2] +011 1 +100 1 +101 1 +110 1 +.names CounterX[3] CounterX[1] CounterX[0] CounterX[2] $auto$alumacc.cc:485:replace_alu$666.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[4] +01 1 +10 1 +.names CounterX[5] CounterX[4] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[5] +011 1 +100 1 +101 1 +110 1 +.names CounterX[6] CounterX[4] CounterX[5] $abc$3008$new_n161 $auto$alumacc.cc:485:replace_alu$666.Y[6] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[7] +01 1 +10 1 +.names CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[8] +011 1 +100 1 +101 1 +110 1 +.names CounterX[9] CounterX[8] CounterX[7] $abc$3008$new_n160 $auto$alumacc.cc:485:replace_alu$666.Y[9] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names CounterX[0] $auto$alumacc.cc:485:replace_alu$666.X[0] +0 1 +.names syncgen.vga_VS vga_v_sync +0 1 +.names syncgen.vga_HS vga_h_sync +0 1 +.names $abc$3008$new_n133 ball_dirY ballY[5] ballY[6] ballY[7] $abc$3008$new_n312 +10111 1 +11000 1 +.names ballY[8] $abc$3008$new_n131 $abc$3008$new_n312 ballY[4] ballY[7] $abc$3008$auto$rtlil.cc:2693:MuxGate$2737 +00100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names CounterY[8] CounterY[3] CounterY[4] CounterY[6] CounterY[7] $abc$3008$new_n314 +00000 1 +11111 1 +.names $abc$3008$new_n314 CounterY[5] $abc$3008$new_n246 $abc$3008$new_n247 $abc$3008$new_n315 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names ballY[3] CounterY[3] CounterY[8] ballY[8] $abc$3008$new_n256 $abc$3008$new_n316 +01000 1 +01001 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10101 1 +10110 1 +.names $abc$3008$new_n240 CounterX[6] ballX[6] ballX[4] ballX[5] $abc$3008$new_n319 +00111 1 +10000 1 +10001 1 +10010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ballY[3] $abc$3008$new_n260 $abc$3008$new_n257 $abc$3008$new_n271 $abc$3008$new_n259 $abc$3008$new_n322 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$3008$new_n316 $abc$3008$new_n322 $abc$3008$new_n253 $abc$3008$new_n272 $abc$3008$new_n323 +1110 1 +.names $abc$3008$new_n323 $abc$3008$new_n315 $abc$3008$new_n228 $abc$3008$new_n220 $abc$3008$new_n206 $abc$3008$new_n324 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names CounterX[8] $abc$3008$new_n234 CounterX[9] ballX[9] ballX[8] $abc$3008$new_n325 +00000 1 +00110 1 +01101 1 +10001 1 +10111 1 +11000 1 +11110 1 +.names $abc$3008$new_n319 $abc$3008$new_n325 $abc$3008$new_n274 $abc$3008$new_n279 $abc$3008$new_n326 +1110 1 +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2743 Q=CollisionY2 R=ResetCollision +.subckt dff C=clk D=$abc$3008$eq$./benchmark/pong.v:56$43_Y Q=syncgen.vga_VS +.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\vga_HS[0:0] Q=syncgen.vga_HS +.subckt dff C=clk D=$abc$3008$flatten\syncgen.$0\inDisplayArea[0:0] Q=inDisplayArea +.subckt dff C=clk D=$0\vga_R[0:0] Q=vga_R +.subckt dff C=clk D=$0\vga_B[0:0] Q=vga_B +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2709 Q=CounterY[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2707 Q=CounterY[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2705 Q=CounterY[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2703 Q=CounterY[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2701 Q=CounterY[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2699 Q=CounterY[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2697 Q=CounterY[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2695 Q=CounterY[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2741 Q=CounterY[8] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2693 Q=ballX[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2691 Q=ballX[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2689 Q=ballX[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2687 Q=ballX[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2685 Q=ballX[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2683 Q=ballX[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2681 Q=ballX[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2679 Q=ballX[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2677 Q=ballX[8] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2739 Q=ballX[9] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2735 Q=ball_dirX +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2731 Q=ball_dirY +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.X[0] Q=CounterX[0] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[1] Q=CounterX[1] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[2] Q=CounterX[2] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[3] Q=CounterX[3] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[4] Q=CounterX[4] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[5] Q=CounterX[5] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[6] Q=CounterX[6] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[7] Q=CounterX[7] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[8] Q=CounterX[8] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$auto$alumacc.cc:485:replace_alu$666.Y[9] Q=CounterX[9] R=syncgen.CounterXmaxed +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2745 Q=CollisionY1 R=ResetCollision +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2747 Q=CollisionX2 R=ResetCollision +.subckt sdffr C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2749 Q=CollisionX1 R=ResetCollision +.subckt dff C=clk D=$0\ResetCollision[0:0] Q=ResetCollision +.subckt dff C=clk D=$0\ball_inY[0:0] Q=ball_inY +.subckt dff C=clk D=$0\ball_inX[0:0] Q=ball_inX +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2675 Q=ballY[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2673 Q=ballY[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2671 Q=ballY[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2669 Q=ballY[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2667 Q=ballY[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2665 Q=ballY[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2663 Q=ballY[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2661 Q=ballY[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2737 Q=ballY[8] +.subckt dff C=clk D=quadB Q=quadBr[0] +.subckt dff C=clk D=quadBr[0] Q=quadBr[1] +.subckt dff C=clk D=quadBr[1] Q=quadBr[2] +.subckt dff C=clk D=quadA Q=quadAr[0] +.subckt dff C=clk D=quadAr[0] Q=quadAr[1] +.subckt dff C=clk D=quadAr[1] Q=quadAr[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2725 Q=PaddlePosition[0] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2723 Q=PaddlePosition[1] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2721 Q=PaddlePosition[2] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2719 Q=PaddlePosition[3] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2717 Q=PaddlePosition[4] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2715 Q=PaddlePosition[5] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2713 Q=PaddlePosition[6] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2711 Q=PaddlePosition[7] +.subckt dff C=clk D=$abc$3008$auto$rtlil.cc:2693:MuxGate$2727 Q=PaddlePosition[8] +.names $auto$alumacc.cc:485:replace_alu$666.X[0] $auto$alumacc.cc:485:replace_alu$666.Y[0] +1 1 +.names CounterX[1] $auto$alumacc.cc:485:replace_alu$666.X[1] +1 1 +.names CounterX[2] $auto$alumacc.cc:485:replace_alu$666.X[2] +1 1 +.names CounterX[3] $auto$alumacc.cc:485:replace_alu$666.X[3] +1 1 +.names CounterX[4] $auto$alumacc.cc:485:replace_alu$666.X[4] +1 1 +.names CounterX[5] $auto$alumacc.cc:485:replace_alu$666.X[5] +1 1 +.names CounterX[6] $auto$alumacc.cc:485:replace_alu$666.X[6] +1 1 +.names CounterX[7] $auto$alumacc.cc:485:replace_alu$666.X[7] +1 1 +.names CounterX[8] $auto$alumacc.cc:485:replace_alu$666.X[8] +1 1 +.names CounterX[9] $auto$alumacc.cc:485:replace_alu$666.X[9] +1 1 +.names vga_B vga_G +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif new file mode 100644 index 00000000000..c6ffa8f4984 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/quad.blif @@ -0,0 +1,135 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model quad +.inputs clk quadA quadB +.outputs count[0] count[1] count[2] count[3] count[4] count[5] count[6] count[7] +.names $false +.names $true +1 +.names $undef +.names count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$715 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names count[3] count[4] count[5] $abc$833$new_n24 $abc$833$new_n23 +1111 1 +.names count[1] count[2] count[0] quadB_delayed[2] quadA_delayed[1] $abc$833$new_n24 +11101 1 +11110 1 +.names $abc$833$new_n26 count[3] count[4] count[5] $abc$833$new_n25 +1000 1 +.names quadB_delayed[2] quadA_delayed[1] count[0] count[1] count[2] $abc$833$new_n26 +00000 1 +11000 1 +.names quadB_delayed[2] quadB_delayed[1] quadA_delayed[2] quadA_delayed[1] $abc$833$new_n27 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names count[5] $abc$833$new_n29 $abc$833$auto$rtlil.cc:2693:MuxGate$717 +01 1 +10 1 +.names $abc$833$new_n27 count[3] count[4] $abc$833$new_n24 $abc$833$new_n26 $abc$833$new_n29 +10001 1 +10011 1 +11110 1 +11111 1 +.names count[4] count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$719 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names count[3] $abc$833$new_n27 $abc$833$new_n26 $abc$833$new_n24 $abc$833$auto$rtlil.cc:2693:MuxGate$721 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names count[2] count[0] count[1] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$723 +00011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names quadB_delayed[2] quadA_delayed[1] $abc$833$new_n33 +00 1 +11 1 +.names count[1] count[0] $abc$833$new_n33 $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$725 +0011 1 +0101 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names count[0] $abc$833$new_n27 $abc$833$auto$rtlil.cc:2693:MuxGate$727 +01 1 +10 1 +.names count[7] count[6] $abc$833$new_n27 $abc$833$new_n25 $abc$833$new_n23 $abc$833$auto$rtlil.cc:2693:MuxGate$729 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$727 Q=count[0] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$725 Q=count[1] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$723 Q=count[2] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$721 Q=count[3] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$719 Q=count[4] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$717 Q=count[5] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$715 Q=count[6] +.subckt dff C=clk D=$abc$833$auto$rtlil.cc:2693:MuxGate$729 Q=count[7] +.subckt dff C=clk D=quadB Q=quadB_delayed[0] +.subckt dff C=clk D=quadB_delayed[0] Q=quadB_delayed[1] +.subckt dff C=clk D=quadB_delayed[1] Q=quadB_delayed[2] +.subckt dff C=clk D=quadA Q=quadA_delayed[0] +.subckt dff C=clk D=quadA_delayed[0] Q=quadA_delayed[1] +.subckt dff C=clk D=quadA_delayed[1] Q=quadA_delayed[2] +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif new file mode 100644 index 00000000000..51d0c4d3cdb --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqcordic.blif @@ -0,0 +1,4862 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model seqcordic +.inputs i_clk i_reset i_stb i_aux i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_phase[0] i_phase[1] i_phase[2] i_phase[3] i_phase[4] i_phase[5] i_phase[6] i_phase[7] i_phase[8] i_phase[9] i_phase[10] i_phase[11] i_phase[12] i_phase[13] i_phase[14] i_phase[15] i_phase[16] i_phase[17] i_phase[18] i_phase[19] +.outputs o_busy o_done o_xval[0] o_xval[1] o_xval[2] o_xval[3] o_xval[4] o_xval[5] o_xval[6] o_xval[7] o_xval[8] o_xval[9] o_xval[10] o_xval[11] o_xval[12] o_yval[0] o_yval[1] o_yval[2] o_yval[3] o_yval[4] o_yval[5] o_yval[6] o_yval[7] o_yval[8] o_yval[9] o_yval[10] o_yval[11] o_yval[12] o_aux +.names $false +.names $true +1 +.names $undef +.names state[1] state[3] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.CO[3] +1111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[14] $abc$4039$new_n329 o_yval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3820 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[13] yv[12] $abc$4039$new_n330 $abc$4039$new_n329 +111 1 +.names yv[11] yv[10] $abc$4039$new_n331 $abc$4039$new_n330 +111 1 +.names yv[9] yv[8] $abc$4039$new_n332 $abc$4039$new_n331 +111 1 +.names yv[7] $abc$4039$new_n333 $abc$4039$new_n332 +11 1 +.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n333 +1111 1 +.names yv[2] yv[3] $abc$4039$new_n334 +11 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[13] yv[12] $abc$4039$new_n330 o_yval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3822 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[12] $abc$4039$new_n330 o_yval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3824 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[11] yv[10] $abc$4039$new_n331 o_yval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3826 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[10] $abc$4039$new_n331 o_yval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3828 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[9] yv[8] $abc$4039$new_n332 o_yval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3830 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[8] $abc$4039$new_n332 o_yval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3832 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[7] $abc$4039$new_n333 o_yval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3834 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n343 o_yval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3836 +001 1 +011 1 +110 1 +111 1 +.names yv[6] yv[5] yv[4] $abc$4039$new_n334 $abc$4039$new_n343 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[5] yv[4] $abc$4039$new_n334 o_yval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3838 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[4] $abc$4039$new_n334 o_yval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3840 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n347 o_yval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3842 +001 1 +011 1 +110 1 +111 1 +.names yv[2] yv[3] yv[0] yv[1] $abc$4039$new_n347 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[14] xv[13] $abc$4039$new_n349 o_xval[11] $abc$4039$auto$rtlil.cc:2693:MuxGate$3844 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12] xv[11] $abc$4039$new_n350 $abc$4039$new_n349 +111 1 +.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n350 +11111 1 +.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n351 +11111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[13] $abc$4039$new_n349 o_xval[10] $abc$4039$auto$rtlil.cc:2693:MuxGate$3846 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[12] xv[11] $abc$4039$new_n350 o_xval[9] $abc$4039$auto$rtlil.cc:2693:MuxGate$3848 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[11] $abc$4039$new_n350 o_xval[8] $abc$4039$auto$rtlil.cc:2693:MuxGate$3850 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n356 o_xval[7] $abc$4039$auto$rtlil.cc:2693:MuxGate$3852 +001 1 +011 1 +110 1 +111 1 +.names xv[10] xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n356 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n358 o_xval[6] $abc$4039$auto$rtlil.cc:2693:MuxGate$3854 +001 1 +011 1 +110 1 +111 1 +.names xv[9] xv[8] xv[7] $abc$4039$new_n351 $abc$4039$new_n358 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[8] xv[7] $abc$4039$new_n351 o_xval[5] $abc$4039$auto$rtlil.cc:2693:MuxGate$3856 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[7] $abc$4039$new_n351 o_xval[4] $abc$4039$auto$rtlil.cc:2693:MuxGate$3858 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n362 o_xval[3] $abc$4039$auto$rtlil.cc:2693:MuxGate$3860 +001 1 +011 1 +110 1 +111 1 +.names xv[6] xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n362 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n364 o_xval[2] $abc$4039$auto$rtlil.cc:2693:MuxGate$3862 +001 1 +011 1 +110 1 +111 1 +.names xv[5] xv[4] xv[2] xv[3] $abc$4039$new_n364 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] xv[4] xv[2] xv[3] o_xval[1] $abc$4039$auto$rtlil.cc:2693:MuxGate$3864 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n367 o_xval[0] $abc$4039$auto$rtlil.cc:2693:MuxGate$3866 +001 1 +011 1 +110 1 +111 1 +.names xv[2] xv[3] xv[0] xv[1] $abc$4039$new_n367 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] aux o_aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3868 +001 1 +011 1 +110 1 +111 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] yv[15] yv[14] $abc$4039$new_n329 o_yval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3870 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$new_n371 o_xval[12] $abc$4039$auto$rtlil.cc:2693:MuxGate$3872 +001 1 +011 1 +110 1 +111 1 +.names xv[15] xv[14] xv[13] $abc$4039$new_n349 $abc$4039$new_n371 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_stb $auto$alumacc.cc:485:replace_alu$688.CO[3] idle $abc$4039$auto$rtlil.cc:2693:MuxGate$3874 +001 1 +010 1 +011 1 +.names i_stb idle $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y +11 1 +.names $abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y i_aux aux $abc$4039$auto$rtlil.cc:2693:MuxGate$3876 +001 1 +011 1 +110 1 +111 1 +.names state[3] state[2] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 +01 1 +10 1 +11 1 +.names state[1] $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$auto$opt_dff.cc:253:combine_resets$907 +00 1 +01 1 +11 1 +.names i_reset idle $auto$alumacc.cc:485:replace_alu$688.CO[3] $abc$4039$auto$opt_dff.cc:253:combine_resets$636 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$auto$rtlil.cc:2516:Or$645 +000 1 +101 1 +110 1 +111 1 +.names $abc$4039$new_n381 $abc$4039$new_n380 i_xval[0] i_yval[0] $0\prex[15:0][2] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n380 +000 1 +111 1 +.names i_phase[18] i_phase[17] i_phase[19] $abc$4039$new_n381 +001 1 +110 1 +.names $abc$4039$new_n383 i_xval[1] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[1] $0\prex[15:0][3] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] $abc$4039$new_n384 $abc$4039$new_n383 +00010 1 +00011 1 +00100 1 +00101 1 +10001 1 +10011 1 +10101 1 +10111 1 +.names i_xval[1] i_xval[0] $abc$4039$new_n384 +01 1 +10 1 +.names i_phase[19] i_phase[18] i_phase[17] $abc$4039$new_n385 +101 1 +110 1 +.names $abc$4039$new_n387 i_xval[2] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[2] $0\prex[15:0][4] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n388 $abc$4039$new_n389 $abc$4039$new_n387 +0001 1 +0011 1 +1010 1 +1011 1 +.names i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n388 +001 1 +010 1 +011 1 +100 1 +.names i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n389 +001 1 +010 1 +011 1 +100 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n391 $abc$4039$new_n393 $abc$4039$new_n392 $0\prex[15:0][5] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_xval[3] $abc$4039$new_n380 i_yval[3] $abc$4039$new_n385 $abc$4039$new_n391 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n392 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n393 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$4039$new_n381 $abc$4039$new_n395 $abc$4039$new_n397 $abc$4039$new_n396 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][6] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[4] $abc$4039$new_n380 i_yval[4] $abc$4039$new_n385 $abc$4039$new_n395 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n396 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n397 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names $abc$4039$new_n399 i_xval[5] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[5] $0\prex[15:0][7] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 $abc$4039$new_n400 $abc$4039$new_n399 +00000 1 +00001 1 +00110 1 +00111 1 +10001 1 +10011 1 +10101 1 +10111 1 +.names i_xval[5] $abc$4039$new_n401 $abc$4039$new_n400 +00 1 +11 1 +.names i_xval[4] i_xval[3] i_xval[2] i_xval[1] i_xval[0] $abc$4039$new_n401 +00000 1 +.names i_yval[4] i_yval[3] i_yval[2] i_yval[1] i_yval[0] $abc$4039$new_n402 +00000 1 +.names $abc$4039$new_n381 $abc$4039$new_n405 $abc$4039$new_n406 $abc$4039$new_n404 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[6] $abc$4039$new_n402 i_yval[5] $abc$4039$new_n404 +000 1 +001 1 +011 1 +110 1 +.names i_xval[6] $abc$4039$new_n380 i_yval[6] $abc$4039$new_n385 $abc$4039$new_n405 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[6] $abc$4039$new_n401 i_xval[5] $abc$4039$new_n406 +000 1 +001 1 +011 1 +110 1 +.names $abc$4039$new_n381 $abc$4039$new_n409 $abc$4039$new_n410 $abc$4039$new_n408 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[7] $abc$4039$new_n402 i_yval[6] i_yval[5] $abc$4039$new_n408 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[7] $abc$4039$new_n380 i_yval[7] $abc$4039$new_n385 $abc$4039$new_n409 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[7] $abc$4039$new_n401 i_xval[6] i_xval[5] $abc$4039$new_n410 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$4039$new_n381 $abc$4039$new_n413 $abc$4039$new_n414 $abc$4039$new_n412 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[8] $abc$4039$new_n402 i_yval[7] i_yval[6] i_yval[5] $abc$4039$new_n412 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[8] $abc$4039$new_n380 i_yval[8] $abc$4039$new_n385 $abc$4039$new_n413 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names i_xval[8] $abc$4039$new_n401 i_xval[7] i_xval[6] i_xval[5] $abc$4039$new_n414 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$4039$new_n416 i_xval[9] $abc$4039$new_n380 $abc$4039$new_n385 i_yval[9] $0\prex[15:0][11] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_xval[9] $abc$4039$new_n419 $abc$4039$new_n417 $abc$4039$new_n416 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names i_yval[9] $abc$4039$new_n418 $abc$4039$new_n417 +00 1 +11 1 +.names $abc$4039$new_n402 i_yval[8] i_yval[7] i_yval[6] i_yval[5] $abc$4039$new_n418 +10000 1 +.names $abc$4039$new_n401 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$4039$new_n419 +10000 1 +.names $abc$4039$new_n381 $abc$4039$new_n423 $abc$4039$new_n422 $abc$4039$new_n421 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[10] $abc$4039$new_n418 i_yval[9] $abc$4039$new_n421 +000 1 +001 1 +011 1 +110 1 +.names i_xval[10] $abc$4039$new_n419 i_xval[9] $abc$4039$new_n422 +000 1 +001 1 +011 1 +110 1 +.names i_xval[10] $abc$4039$new_n380 i_yval[10] $abc$4039$new_n385 $abc$4039$new_n423 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$new_n427 $abc$4039$new_n426 $abc$4039$new_n425 $abc$4039$auto$rtlil.cc:2516:Or$645 $0\prex[15:0][13] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[11] $abc$4039$new_n418 i_yval[10] i_yval[9] $abc$4039$new_n425 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[11] $abc$4039$new_n419 i_xval[10] i_xval[9] $abc$4039$new_n426 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[11] $abc$4039$new_n380 i_yval[11] $abc$4039$new_n385 $abc$4039$new_n427 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n433 i_yval[12] $abc$4039$new_n432 $abc$4039$new_n381 $abc$4039$new_n429 $0\prex[15:0][14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n430 $abc$4039$new_n431 $abc$4039$new_n429 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names i_xval[12] $abc$4039$new_n419 i_xval[10] i_xval[9] i_xval[11] $abc$4039$new_n430 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_xval[12] $abc$4039$new_n419 i_xval[11] i_xval[10] i_xval[9] $abc$4039$new_n431 +11000 1 +.names $abc$4039$new_n418 i_yval[11] i_yval[10] i_yval[9] $abc$4039$new_n432 +1000 1 +.names i_xval[12] $abc$4039$new_n380 i_yval[12] $abc$4039$new_n385 $abc$4039$new_n433 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n433 $abc$4039$new_n435 $abc$4039$new_n430 $0\prex[15:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[12] $abc$4039$new_n432 $abc$4039$new_n435 +00 1 +.names $abc$4039$new_n381 $abc$4039$new_n380 i_yval[0] i_xval[0] $0\prey[15:0][2] +0001 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n380 $abc$4039$new_n438 i_yval[1] $abc$4039$new_n384 $0\prey[15:0][3] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[1] i_yval[0] i_xval[1] $abc$4039$new_n438 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n381 $abc$4039$new_n440 $abc$4039$new_n389 i_xval[2] $0\prey[15:0][4] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n380 i_yval[2] $abc$4039$new_n388 $abc$4039$new_n440 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n442 $abc$4039$new_n392 i_xval[3] $0\prey[15:0][5] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[3] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n393 $abc$4039$new_n442 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n444 $abc$4039$new_n396 i_xval[4] $0\prey[15:0][6] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_yval[4] $abc$4039$new_n380 $abc$4039$new_n385 $abc$4039$new_n397 $abc$4039$new_n444 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n446 $abc$4039$new_n385 $abc$4039$new_n400 $abc$4039$new_n380 i_yval[5] $0\prey[15:0][7] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 i_yval[5] $abc$4039$new_n402 i_xval[5] $abc$4039$new_n446 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n448 $abc$4039$new_n404 i_xval[6] $0\prey[15:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n406 i_yval[6] $abc$4039$new_n380 $abc$4039$new_n448 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n450 $abc$4039$new_n408 i_xval[7] $0\prey[15:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n410 i_yval[7] $abc$4039$new_n380 $abc$4039$new_n450 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n452 $abc$4039$new_n412 i_xval[8] $0\prey[15:0][10] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n414 i_yval[8] $abc$4039$new_n380 $abc$4039$new_n452 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n454 $abc$4039$new_n417 i_xval[9] $0\prey[15:0][11] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n419 i_xval[9] i_yval[9] $abc$4039$new_n380 $abc$4039$new_n454 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n456 $abc$4039$new_n421 i_xval[10] $0\prey[15:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n422 i_yval[10] $abc$4039$new_n380 $abc$4039$new_n456 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n458 $abc$4039$new_n385 $abc$4039$new_n426 $abc$4039$new_n380 i_yval[11] $0\prey[15:0][13] +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_phase[18] i_phase[17] i_phase[19] i_xval[11] $abc$4039$new_n425 $abc$4039$new_n458 +00101 1 +00111 1 +01010 1 +01011 1 +10010 1 +10011 1 +11001 1 +11011 1 +.names $abc$4039$new_n462 $0\prey[15:0][15] $0\prey[15:0][14] +00 1 +01 1 +11 1 +.names $abc$4039$new_n381 $abc$4039$auto$rtlil.cc:2516:Or$645 $abc$4039$new_n461 $abc$4039$new_n435 i_xval[12] $0\prey[15:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n385 $abc$4039$new_n430 i_yval[12] $abc$4039$new_n380 $abc$4039$new_n461 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$4039$new_n431 $abc$4039$new_n385 $abc$4039$new_n381 i_yval[12] $abc$4039$new_n432 $abc$4039$new_n462 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] +10 1 +.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] +000 1 +010 1 +110 1 +111 1 +.names state[2] state[0] state[1] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] +000 1 +010 1 +100 1 +101 1 +.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] +000 1 +001 1 +011 1 +101 1 +.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] +00 1 +.names state[1] state[2] state[0] $abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] +001 1 +010 1 +100 1 +.names state[1] state[0] $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] +00 1 +11 1 +.names pre_valid ph[0] cangle[0] preph[0] $0\ph[19:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names pre_valid $abc$4039$new_n472 preph[1] $0\ph[19:0][1] +010 1 +011 1 +101 1 +111 1 +.names ph[1] cangle[1] ph[0] ph[19] cangle[0] $abc$4039$new_n472 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names pre_valid ph[2] cangle[2] $abc$4039$new_n474 preph[2] $0\ph[19:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n475 $abc$4039$new_n476 $abc$4039$new_n474 +000 1 +001 1 +101 1 +111 1 +.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n475 +0001 1 +0101 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names cangle[0] ph[0] ph[1] cangle[1] $abc$4039$new_n476 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names pre_valid ph[3] cangle[3] $abc$4039$new_n478 preph[3] $0\ph[19:0][3] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[2] ph[19] cangle[2] $abc$4039$new_n476 $abc$4039$new_n475 $abc$4039$new_n478 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names pre_valid $abc$4039$new_n480 preph[4] $0\ph[19:0][4] +010 1 +011 1 +101 1 +111 1 +.names ph[19] ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n480 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[2] ph[2] ph[3] cangle[3] $abc$4039$new_n475 $abc$4039$new_n481 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names ph[2] cangle[2] ph[3] cangle[3] $abc$4039$new_n476 $abc$4039$new_n482 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pre_valid ph[5] cangle[5] $abc$4039$new_n484 preph[5] $0\ph[19:0][5] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[4] ph[19] cangle[4] $abc$4039$new_n482 $abc$4039$new_n481 $abc$4039$new_n484 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names pre_valid ph[6] cangle[6] $abc$4039$new_n486 preph[6] $0\ph[19:0][6] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] ph[5] cangle[5] $abc$4039$new_n487 $abc$4039$new_n488 $abc$4039$new_n486 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names ph[4] cangle[4] $abc$4039$new_n482 $abc$4039$new_n487 +000 1 +001 1 +011 1 +101 1 +.names cangle[4] ph[4] ph[5] cangle[5] $abc$4039$new_n481 $abc$4039$new_n488 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[7] cangle[7] $abc$4039$new_n490 preph[7] $0\ph[19:0][7] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] ph[6] cangle[6] $abc$4039$new_n488 $abc$4039$new_n491 $abc$4039$new_n490 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[5] cangle[5] ph[6] cangle[6] $abc$4039$new_n487 $abc$4039$new_n491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names pre_valid $abc$4039$new_n493 preph[8] $0\ph[19:0][8] +000 1 +001 1 +101 1 +111 1 +.names ph[8] cangle[8] ph[19] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n493 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names ph[7] cangle[7] $abc$4039$new_n491 $abc$4039$new_n494 +000 1 +001 1 +011 1 +101 1 +.names cangle[6] ph[6] ph[7] cangle[7] $abc$4039$new_n488 $abc$4039$new_n495 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[9] cangle[9] $abc$4039$new_n497 preph[9] $0\ph[19:0][9] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[8] ph[19] cangle[8] $abc$4039$new_n495 $abc$4039$new_n494 $abc$4039$new_n497 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names pre_valid $abc$4039$new_n499 preph[10] $0\ph[19:0][10] +010 1 +011 1 +101 1 +111 1 +.names ph[10] cangle[10] ph[19] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n499 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names ph[8] cangle[8] ph[9] cangle[9] $abc$4039$new_n494 $abc$4039$new_n500 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[8] ph[9] cangle[8] cangle[9] $abc$4039$new_n495 $abc$4039$new_n501 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names pre_valid ph[11] cangle[11] $abc$4039$new_n503 preph[11] $0\ph[19:0][11] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[10] ph[19] cangle[10] $abc$4039$new_n501 $abc$4039$new_n500 $abc$4039$new_n503 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names pre_valid $abc$4039$new_n505 preph[12] $0\ph[19:0][12] +010 1 +011 1 +101 1 +111 1 +.names ph[12] cangle[12] ph[19] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n505 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10] cangle[10] ph[11] cangle[11] $abc$4039$new_n500 $abc$4039$new_n506 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names cangle[10] ph[10] ph[11] cangle[11] $abc$4039$new_n501 $abc$4039$new_n507 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names pre_valid ph[13] cangle[13] $abc$4039$new_n509 preph[13] $0\ph[19:0][13] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[12] ph[19] cangle[12] $abc$4039$new_n507 $abc$4039$new_n506 $abc$4039$new_n509 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names pre_valid $abc$4039$new_n511 preph[14] $0\ph[19:0][14] +010 1 +011 1 +101 1 +111 1 +.names ph[14] cangle[14] ph[19] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n511 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names ph[12] cangle[12] ph[13] cangle[13] $abc$4039$new_n506 $abc$4039$new_n512 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names cangle[12] ph[12] ph[13] cangle[13] $abc$4039$new_n507 $abc$4039$new_n513 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[15] cangle[15] $abc$4039$new_n515 preph[15] $0\ph[19:0][15] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[14] ph[19] cangle[14] $abc$4039$new_n513 $abc$4039$new_n512 $abc$4039$new_n515 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names pre_valid ph[16] cangle[16] $abc$4039$new_n517 preph[16] $0\ph[19:0][16] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n518 $abc$4039$new_n519 $abc$4039$new_n517 +000 1 +010 1 +110 1 +111 1 +.names ph[14] cangle[14] ph[15] cangle[15] $abc$4039$new_n512 $abc$4039$new_n518 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names cangle[14] ph[14] ph[15] cangle[15] $abc$4039$new_n513 $abc$4039$new_n519 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names pre_valid ph[17] $abc$4039$new_n521 preph[17] $0\ph[19:0][17] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[16] cangle[16] ph[19] $abc$4039$new_n519 $abc$4039$new_n518 $abc$4039$new_n521 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid ph[18] $abc$4039$new_n524 $abc$4039$new_n523 preph[18] $0\ph[19:0][18] +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[17] ph[16] cangle[16] $abc$4039$new_n518 ph[19] $abc$4039$new_n523 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[17] cangle[16] ph[16] $abc$4039$new_n519 ph[19] $abc$4039$new_n524 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n523 preph[19] $abc$4039$new_n524 ph[18] $0\ph[19:0][19] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid yv[0] $abc$4039$new_n527 prey[0] $0\yv[15:0][0] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4039$new_n533 $abc$4039$new_n536 $abc$4039$new_n528 state[3] $abc$4039$new_n527 +0000 1 +0010 1 +0011 1 +.names state[2] $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n532 $abc$4039$new_n531 $abc$4039$new_n528 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] xv[9] xv[8] $abc$4039$new_n529 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] xv[11] xv[10] $abc$4039$new_n530 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] xv[13] xv[12] $abc$4039$new_n531 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n532 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[2] state[1] state[3] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n533 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] xv[5] xv[4] $abc$4039$new_n534 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[7] xv[6] $abc$4039$new_n535 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n538 state[1] $abc$4039$new_n537 $abc$4039$new_n536 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names state[0] xv[3] xv[2] $abc$4039$new_n537 +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] xv[1] xv[0] $abc$4039$new_n538 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4039$new_n540 prey[1] $0\yv[15:0][1] +010 1 +011 1 +101 1 +111 1 +.names yv[1] $abc$4039$new_n541 yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n540 +00000 1 +00001 1 +00011 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n542 $abc$4039$new_n546 $abc$4039$new_n548 $abc$4039$new_n541 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n545 $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n542 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[10] xv[9] $abc$4039$new_n543 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[12] xv[11] $abc$4039$new_n544 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] xv[15] xv[14] xv[13] $abc$4039$new_n545 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4039$new_n547 xv[8] xv[7] $abc$4039$new_n546 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[6] xv[5] $abc$4039$new_n547 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4039$new_n549 xv[2] xv[1] $abc$4039$new_n548 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[4] xv[3] $abc$4039$new_n549 +000 1 +010 1 +100 1 +101 1 +.names pre_valid yv[2] $abc$4039$new_n552 $abc$4039$new_n551 prey[2] $0\yv[15:0][2] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[1] yv[0] ph[19] $abc$4039$new_n527 $abc$4039$new_n541 $abc$4039$new_n551 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] $abc$4039$new_n557 $abc$4039$new_n553 $abc$4039$new_n558 state[2] $abc$4039$new_n552 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n556 $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n553 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[11] xv[10] $abc$4039$new_n554 +000 1 +010 1 +100 1 +101 1 +.names state[0] xv[13] xv[12] $abc$4039$new_n555 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] xv[15] xv[14] $abc$4039$new_n556 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] state[2] $abc$4039$new_n534 $abc$4039$new_n537 $abc$4039$new_n557 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n535 xv[9] xv[8] $abc$4039$new_n558 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid yv[3] $abc$4039$new_n565 $abc$4039$new_n560 prey[3] $0\yv[15:0][3] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n561 $abc$4039$new_n563 $abc$4039$new_n560 +000 1 +001 1 +101 1 +111 1 +.names $abc$4039$new_n541 yv[1] yv[2] $abc$4039$new_n552 $abc$4039$new_n562 $abc$4039$new_n561 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n562 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[1] $abc$4039$new_n541 yv[2] $abc$4039$new_n552 $abc$4039$new_n564 $abc$4039$new_n563 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names yv[0] $abc$4039$new_n533 $abc$4039$new_n536 state[3] $abc$4039$new_n528 $abc$4039$new_n564 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names state[3] $abc$4039$new_n566 $abc$4039$new_n568 $abc$4039$new_n565 +001 1 +011 1 +110 1 +111 1 +.names state[2] $abc$4039$new_n567 xv[15] $abc$4039$new_n566 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4039$new_n544 xv[14] xv[13] $abc$4039$new_n567 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[2] state[1] $abc$4039$new_n569 $abc$4039$new_n547 $abc$4039$new_n549 $abc$4039$new_n568 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4039$new_n543 xv[8] xv[7] $abc$4039$new_n569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid yv[4] $abc$4039$new_n572 $abc$4039$new_n571 prey[4] $0\yv[15:0][4] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[3] ph[19] $abc$4039$new_n565 $abc$4039$new_n563 $abc$4039$new_n561 $abc$4039$new_n571 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names state[3] state[2] $abc$4039$new_n575 $abc$4039$new_n573 $abc$4039$new_n574 $abc$4039$new_n572 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n530 $abc$4039$new_n529 $abc$4039$new_n573 +00 1 +.names state[1] $abc$4039$new_n534 $abc$4039$new_n535 $abc$4039$new_n574 +010 1 +011 1 +101 1 +111 1 +.names state[2] xv[15] $abc$4039$new_n531 $abc$4039$new_n532 $abc$4039$new_n575 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names pre_valid $abc$4039$new_n577 prey[5] $0\yv[15:0][5] +010 1 +011 1 +101 1 +111 1 +.names ph[19] yv[5] $abc$4039$new_n580 $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n577 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$4039$new_n561 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n578 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4039$new_n563 yv[3] yv[4] $abc$4039$new_n572 $abc$4039$new_n565 $abc$4039$new_n579 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names state[3] state[2] $abc$4039$new_n582 $abc$4039$new_n581 $abc$4039$new_n546 $abc$4039$new_n580 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n543 $abc$4039$new_n544 $abc$4039$new_n581 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n545 xv[15] $abc$4039$new_n582 +010 1 +011 1 +100 1 +110 1 +.names state[3] state[2] $abc$4039$new_n589 $abc$4039$new_n588 $abc$4039$new_n558 $abc$4039$new_n587 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n554 $abc$4039$new_n555 $abc$4039$new_n588 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n556 xv[15] $abc$4039$new_n589 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n591 prey[7] $0\yv[15:0][7] +010 1 +011 1 +101 1 +111 1 +.names yv[7] $abc$4039$new_n594 ph[19] $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n591 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names yv[5] $abc$4039$new_n580 yv[6] $abc$4039$new_n587 $abc$4039$new_n579 $abc$4039$new_n592 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4039$new_n580 yv[5] yv[6] $abc$4039$new_n587 $abc$4039$new_n578 $abc$4039$new_n593 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] state[2] xv[15] $abc$4039$new_n567 $abc$4039$new_n569 $abc$4039$new_n594 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[8] $abc$4039$new_n597 $abc$4039$new_n596 prey[8] $0\yv[15:0][8] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[7] ph[19] $abc$4039$new_n594 $abc$4039$new_n593 $abc$4039$new_n592 $abc$4039$new_n596 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11001 1 +11011 1 +.names state[3] $abc$4039$new_n528 xv[15] $abc$4039$new_n597 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n599 prey[9] $0\yv[15:0][9] +010 1 +011 1 +101 1 +111 1 +.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n601 $abc$4039$new_n600 $abc$4039$new_n599 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[7] $abc$4039$new_n594 yv[8] $abc$4039$new_n597 $abc$4039$new_n592 $abc$4039$new_n600 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n594 yv[7] yv[8] $abc$4039$new_n597 $abc$4039$new_n593 $abc$4039$new_n601 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] $abc$4039$new_n542 xv[15] $abc$4039$new_n602 +010 1 +011 1 +100 1 +110 1 +.names state[3] $abc$4039$new_n553 xv[15] $abc$4039$new_n607 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n609 prey[11] $0\yv[15:0][11] +010 1 +011 1 +101 1 +111 1 +.names yv[11] $abc$4039$new_n612 ph[19] $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n609 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names yv[9] $abc$4039$new_n602 yv[10] $abc$4039$new_n607 $abc$4039$new_n600 $abc$4039$new_n610 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names yv[9] yv[10] $abc$4039$new_n602 $abc$4039$new_n607 $abc$4039$new_n601 $abc$4039$new_n611 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names state[3] $abc$4039$new_n566 xv[15] $abc$4039$new_n612 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[12] $abc$4039$new_n615 $abc$4039$new_n614 prey[12] $0\yv[15:0][12] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[11] ph[19] $abc$4039$new_n612 $abc$4039$new_n611 $abc$4039$new_n610 $abc$4039$new_n614 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names state[3] $abc$4039$new_n575 xv[15] $abc$4039$new_n615 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[13] $abc$4039$new_n620 $abc$4039$new_n617 prey[13] $0\yv[15:0][13] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n618 $abc$4039$new_n619 $abc$4039$new_n617 +000 1 +010 1 +100 1 +101 1 +.names yv[11] $abc$4039$new_n612 yv[12] $abc$4039$new_n615 $abc$4039$new_n610 $abc$4039$new_n618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names yv[11] yv[12] $abc$4039$new_n612 $abc$4039$new_n615 $abc$4039$new_n611 $abc$4039$new_n619 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[3] $abc$4039$new_n582 xv[15] $abc$4039$new_n620 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n623 $abc$4039$new_n622 prey[14] $0\yv[15:0][14] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[13] $abc$4039$new_n620 ph[19] $abc$4039$new_n619 $abc$4039$new_n618 $abc$4039$new_n622 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[14] $abc$4039$new_n624 $abc$4039$new_n623 +01 1 +10 1 +.names state[3] $abc$4039$new_n589 xv[15] $abc$4039$new_n624 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n631 $abc$4039$new_n628 $abc$4039$new_n626 prey[15] $0\yv[15:0][15] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n627 $abc$4039$new_n620 yv[13] $abc$4039$new_n619 $abc$4039$new_n623 $abc$4039$new_n626 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n627 +000 1 +010 1 +011 1 +.names $abc$4039$new_n630 yv[13] $abc$4039$new_n620 $abc$4039$new_n618 $abc$4039$new_n623 $abc$4039$new_n628 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[19] $abc$4039$new_n624 yv[14] $abc$4039$new_n630 +101 1 +110 1 +111 1 +.names yv[15] xv[15] $abc$4039$new_n631 +00 1 +11 1 +.names pre_valid xv[0] $abc$4039$new_n633 prex[0] $0\xv[15:0][0] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4039$new_n639 $abc$4039$new_n642 $abc$4039$new_n634 state[3] $abc$4039$new_n633 +0000 1 +0010 1 +0011 1 +.names state[2] $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n638 $abc$4039$new_n637 $abc$4039$new_n634 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] yv[9] yv[8] $abc$4039$new_n635 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[11] yv[10] $abc$4039$new_n636 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] yv[13] yv[12] $abc$4039$new_n637 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n638 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[2] state[1] state[3] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n639 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] yv[5] yv[4] $abc$4039$new_n640 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[7] yv[6] $abc$4039$new_n641 +000 1 +010 1 +100 1 +101 1 +.names $abc$4039$auto$opt_dff.cc:253:combine_resets$910 $abc$4039$new_n644 state[1] $abc$4039$new_n643 $abc$4039$new_n642 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names state[0] yv[3] yv[2] $abc$4039$new_n643 +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] yv[1] yv[0] $abc$4039$new_n644 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4039$new_n646 prex[1] $0\xv[15:0][1] +010 1 +011 1 +101 1 +111 1 +.names xv[1] $abc$4039$new_n769 xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n646 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01110 1 +10000 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n651 $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n648 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[10] yv[9] $abc$4039$new_n649 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[12] yv[11] $abc$4039$new_n650 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] yv[15] yv[14] yv[13] $abc$4039$new_n651 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4039$new_n653 yv[8] yv[7] $abc$4039$new_n652 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[6] yv[5] $abc$4039$new_n653 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[4] yv[3] $abc$4039$new_n655 +000 1 +010 1 +100 1 +101 1 +.names pre_valid xv[2] $abc$4039$new_n659 $abc$4039$new_n658 prex[2] $0\xv[15:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[1] xv[0] ph[19] $abc$4039$new_n633 $abc$4039$new_n769 $abc$4039$new_n658 +00000 1 +00001 1 +00010 1 +01000 1 +01010 1 +01100 1 +10000 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +.names state[3] $abc$4039$new_n664 $abc$4039$new_n660 $abc$4039$new_n665 state[2] $abc$4039$new_n659 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] state[1] $abc$4039$new_n663 $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n660 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[11] yv[10] $abc$4039$new_n661 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[13] yv[12] $abc$4039$new_n662 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] yv[15] yv[14] $abc$4039$new_n663 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] state[2] $abc$4039$new_n640 $abc$4039$new_n643 $abc$4039$new_n664 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n641 yv[9] yv[8] $abc$4039$new_n665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4039$new_n667 prex[3] $0\xv[15:0][3] +010 1 +011 1 +101 1 +111 1 +.names ph[19] xv[3] $abc$4039$new_n668 $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n667 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names state[3] $abc$4039$new_n671 $abc$4039$new_n669 $abc$4039$new_n672 state[2] $abc$4039$new_n668 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4039$new_n670 yv[15] $abc$4039$new_n669 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4039$new_n650 yv[14] yv[13] $abc$4039$new_n670 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[2] $abc$4039$new_n653 $abc$4039$new_n655 $abc$4039$new_n671 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[1] state[0] $abc$4039$new_n649 yv[8] yv[7] $abc$4039$new_n672 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1] $abc$4039$new_n769 xv[2] $abc$4039$new_n659 $abc$4039$new_n674 $abc$4039$new_n673 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n674 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$4039$new_n769 xv[1] xv[2] $abc$4039$new_n659 $abc$4039$new_n676 $abc$4039$new_n675 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0] $abc$4039$new_n639 $abc$4039$new_n642 state[3] $abc$4039$new_n634 $abc$4039$new_n676 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid xv[4] $abc$4039$new_n679 $abc$4039$new_n678 prex[4] $0\xv[15:0][4] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[3] $abc$4039$new_n668 ph[19] $abc$4039$new_n675 $abc$4039$new_n673 $abc$4039$new_n678 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n682 $abc$4039$new_n680 $abc$4039$new_n681 $abc$4039$new_n679 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n636 $abc$4039$new_n635 $abc$4039$new_n680 +00 1 +.names state[1] $abc$4039$new_n640 $abc$4039$new_n641 $abc$4039$new_n681 +010 1 +011 1 +101 1 +111 1 +.names state[2] yv[15] $abc$4039$new_n637 $abc$4039$new_n638 $abc$4039$new_n682 +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names pre_valid $abc$4039$new_n684 prex[5] $0\xv[15:0][5] +000 1 +001 1 +101 1 +111 1 +.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n684 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$4039$new_n675 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n685 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4039$new_n673 xv[3] xv[4] $abc$4039$new_n679 $abc$4039$new_n668 $abc$4039$new_n686 +00000 1 +00001 1 +00010 1 +00100 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11100 1 +.names state[3] state[2] $abc$4039$new_n689 $abc$4039$new_n688 $abc$4039$new_n652 $abc$4039$new_n687 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n649 $abc$4039$new_n650 $abc$4039$new_n688 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n651 yv[15] $abc$4039$new_n689 +010 1 +011 1 +100 1 +110 1 +.names state[3] state[2] $abc$4039$new_n696 $abc$4039$new_n695 $abc$4039$new_n665 $abc$4039$new_n694 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] $abc$4039$new_n661 $abc$4039$new_n662 $abc$4039$new_n695 +010 1 +011 1 +101 1 +111 1 +.names state[2] $abc$4039$new_n663 yv[15] $abc$4039$new_n696 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n698 prex[7] $0\xv[15:0][7] +000 1 +001 1 +101 1 +111 1 +.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n698 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$4039$new_n687 xv[5] xv[6] $abc$4039$new_n694 $abc$4039$new_n685 $abc$4039$new_n699 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[5] $abc$4039$new_n687 xv[6] $abc$4039$new_n694 $abc$4039$new_n686 $abc$4039$new_n700 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names state[3] state[2] yv[15] $abc$4039$new_n670 $abc$4039$new_n672 $abc$4039$new_n701 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n705 +001 1 +100 1 +101 1 +111 1 +.names xv[8] $abc$4039$new_n707 $abc$4039$new_n706 +01 1 +10 1 +.names state[3] $abc$4039$new_n634 yv[15] $abc$4039$new_n707 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[9] $abc$4039$new_n712 $abc$4039$new_n709 prex[9] $0\xv[15:0][9] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n710 $abc$4039$new_n711 $abc$4039$new_n706 $abc$4039$new_n705 $abc$4039$new_n709 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[7] $abc$4039$new_n701 xv[8] $abc$4039$new_n707 $abc$4039$new_n700 $abc$4039$new_n710 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[8] $abc$4039$new_n707 $abc$4039$new_n711 +10 1 +.names state[3] $abc$4039$new_n648 yv[15] $abc$4039$new_n712 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[10] $abc$4039$new_n717 $abc$4039$new_n714 prex[10] $0\xv[15:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[9] ph[19] $abc$4039$new_n712 $abc$4039$new_n710 $abc$4039$new_n715 $abc$4039$new_n714 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n716 $abc$4039$new_n701 xv[7] $abc$4039$new_n699 $abc$4039$new_n706 $abc$4039$new_n715 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n711 $abc$4039$new_n712 xv[9] $abc$4039$new_n716 +000 1 +010 1 +011 1 +.names state[3] $abc$4039$new_n660 yv[15] $abc$4039$new_n717 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n719 prex[11] $0\xv[15:0][11] +010 1 +011 1 +101 1 +111 1 +.names xv[11] $abc$4039$new_n723 ph[19] $abc$4039$new_n722 $abc$4039$new_n720 $abc$4039$new_n719 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n720 +0000 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names $abc$4039$new_n712 xv[9] $abc$4039$new_n721 +10 1 +.names xv[9] $abc$4039$new_n712 xv[10] $abc$4039$new_n717 $abc$4039$new_n710 $abc$4039$new_n722 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names state[3] $abc$4039$new_n669 yv[15] $abc$4039$new_n723 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n730 $abc$4039$new_n725 prex[12] $0\xv[15:0][12] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[19] $abc$4039$new_n726 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n725 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[11] $abc$4039$new_n723 $abc$4039$new_n722 $abc$4039$new_n726 +010 1 +100 1 +110 1 +111 1 +.names xv[10] $abc$4039$new_n715 $abc$4039$new_n721 $abc$4039$new_n717 $abc$4039$new_n728 $abc$4039$new_n727 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names xv[11] $abc$4039$new_n723 $abc$4039$new_n728 +10 1 +.names $abc$4039$new_n723 xv[11] $abc$4039$new_n729 +10 1 +.names xv[12] $abc$4039$new_n731 $abc$4039$new_n730 +01 1 +10 1 +.names state[3] $abc$4039$new_n682 yv[15] $abc$4039$new_n731 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n733 $abc$4039$new_n735 prex[13] $0\xv[15:0][13] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names xv[12] ph[19] $abc$4039$new_n731 $abc$4039$new_n726 $abc$4039$new_n734 $abc$4039$new_n733 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n734 +000 1 +.names xv[13] $abc$4039$new_n736 $abc$4039$new_n735 +01 1 +10 1 +.names state[3] $abc$4039$new_n689 yv[15] $abc$4039$new_n736 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n738 $abc$4039$new_n742 prex[14] $0\xv[15:0][14] +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names ph[19] xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n740 $abc$4039$new_n738 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[11] $abc$4039$new_n723 xv[12] $abc$4039$new_n731 $abc$4039$new_n722 $abc$4039$new_n739 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4039$new_n741 $abc$4039$new_n730 $abc$4039$new_n729 $abc$4039$new_n727 $abc$4039$new_n735 $abc$4039$new_n740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names xv[12] xv[13] $abc$4039$new_n731 $abc$4039$new_n736 $abc$4039$new_n741 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names xv[14] $abc$4039$new_n743 $abc$4039$new_n742 +00 1 +11 1 +.names state[3] $abc$4039$new_n696 yv[15] $abc$4039$new_n743 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4039$new_n631 $abc$4039$new_n747 $abc$4039$new_n745 prex[15] $0\xv[15:0][15] +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4039$new_n746 xv[13] $abc$4039$new_n736 $abc$4039$new_n739 $abc$4039$new_n742 $abc$4039$new_n745 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[19] $abc$4039$new_n743 xv[14] $abc$4039$new_n746 +000 1 +001 1 +010 1 +.names ph[19] xv[14] $abc$4039$new_n743 $abc$4039$new_n740 $abc$4039$new_n747 +1001 1 +1100 1 +1101 1 +1111 1 +.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[0] +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names state[1] state[2] state[0] state[3] $\cordic_angle$rdreg[0]$d[1] +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names state[2] state[3] state[1] state[0] $\cordic_angle$rdreg[0]$d[2] +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names state[2] state[1] state[3] state[0] $\cordic_angle$rdreg[0]$d[3] +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[4] +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1100 1 +.names state[0] state[2] state[1] state[3] $\cordic_angle$rdreg[0]$d[5] +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names state[3] state[0] state[2] state[1] $\cordic_angle$rdreg[0]$d[6] +0000 1 +0010 1 +1000 1 +1001 1 +.names state[0] state[1] state[2] state[3] $\cordic_angle$rdreg[0]$d[7] +1000 1 +1001 1 +1100 1 +1110 1 +.names state[3] state[0] state[1] state[2] $\cordic_angle$rdreg[0]$d[8] +0010 1 +0011 1 +0100 1 +1000 1 +.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[2] +011 1 +100 1 +101 1 +110 1 +.names state[3] state[1] state[2] state[0] $auto$alumacc.cc:485:replace_alu$688.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$688.Y[0] +0 1 +.names idle o_busy +0 1 +.names $abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] $auto$alumacc.cc:485:replace_alu$688.Y[1] +0 1 +.names yv[5] $abc$4039$new_n580 ph[19] $abc$4039$new_n579 $abc$4039$new_n578 $abc$4039$new_n764 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4039$new_n587 yv[6] $abc$4039$new_n764 prey[6] $0\yv[15:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[9] $abc$4039$new_n602 ph[19] $abc$4039$new_n600 $abc$4039$new_n601 $abc$4039$new_n766 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4039$new_n607 yv[10] $abc$4039$new_n766 prey[10] $0\yv[15:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[1] state[0] $abc$4039$new_n655 yv[2] yv[1] $abc$4039$new_n768 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] $abc$4039$new_n648 $abc$4039$new_n768 $abc$4039$new_n652 $abc$4039$new_n769 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5] $abc$4039$new_n687 ph[19] $abc$4039$new_n686 $abc$4039$new_n685 $abc$4039$new_n770 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n694 xv[6] $abc$4039$new_n770 prex[6] $0\xv[15:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[7] $abc$4039$new_n701 ph[19] $abc$4039$new_n700 $abc$4039$new_n699 $abc$4039$new_n772 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4039$new_n706 $abc$4039$new_n772 prex[8] $0\xv[15:0][8] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3868 Q=o_aux +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[13] Q=cangle[13] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][1][0]$a$861[15] Q=cangle[15] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[6] Q=cangle[16] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$910 +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[2] Q=cangle[2] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[3] Q=cangle[3] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[4] Q=cangle[4] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[5] Q=cangle[5] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[6] Q=cangle[6] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[7] Q=cangle[7] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[8] Q=cangle[8] +.subckt dff C=i_clk D=$0\prex[15:0][2] Q=prex[2] +.subckt dff C=i_clk D=$0\prex[15:0][3] Q=prex[3] +.subckt dff C=i_clk D=$0\prex[15:0][4] Q=prex[4] +.subckt dff C=i_clk D=$0\prex[15:0][5] Q=prex[5] +.subckt dff C=i_clk D=$0\prex[15:0][6] Q=prex[6] +.subckt dff C=i_clk D=$0\prex[15:0][7] Q=prex[7] +.subckt dff C=i_clk D=$0\prex[15:0][8] Q=prex[8] +.subckt dff C=i_clk D=$0\prex[15:0][9] Q=prex[9] +.subckt dff C=i_clk D=$0\prex[15:0][10] Q=prex[10] +.subckt dff C=i_clk D=$0\prex[15:0][11] Q=prex[11] +.subckt dff C=i_clk D=$0\prex[15:0][12] Q=prex[12] +.subckt dff C=i_clk D=$0\prex[15:0][13] Q=prex[13] +.subckt dff C=i_clk D=$0\prex[15:0][14] Q=prex[14] +.subckt dff C=i_clk D=$0\prex[15:0][15] Q=prex[15] +.subckt sdffr C=i_clk D=$false Q=prex[0] R=$abc$4039$auto$rtlil.cc:2516:Or$645 +.subckt sdffr C=i_clk D=$false Q=prex[1] R=$abc$4039$auto$rtlil.cc:2516:Or$645 +.subckt sdffs C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3874 Q=idle S=i_reset +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3866 Q=o_xval[0] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3864 Q=o_xval[1] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3862 Q=o_xval[2] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3860 Q=o_xval[3] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3858 Q=o_xval[4] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3856 Q=o_xval[5] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3854 Q=o_xval[6] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3852 Q=o_xval[7] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3850 Q=o_xval[8] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3848 Q=o_xval[9] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3846 Q=o_xval[10] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3844 Q=o_xval[11] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3872 Q=o_xval[12] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3842 Q=o_yval[0] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3840 Q=o_yval[1] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3838 Q=o_yval[2] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3836 Q=o_yval[3] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3834 Q=o_yval[4] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3832 Q=o_yval[5] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3830 Q=o_yval[6] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3828 Q=o_yval[7] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3826 Q=o_yval[8] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3824 Q=o_yval[9] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3822 Q=o_yval[10] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3820 Q=o_yval[11] +.subckt dff C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3870 Q=o_yval[12] +.subckt dff C=i_clk D=$0\xv[15:0][0] Q=xv[0] +.subckt dff C=i_clk D=$0\xv[15:0][1] Q=xv[1] +.subckt dff C=i_clk D=$0\xv[15:0][2] Q=xv[2] +.subckt dff C=i_clk D=$0\xv[15:0][3] Q=xv[3] +.subckt dff C=i_clk D=$0\xv[15:0][4] Q=xv[4] +.subckt dff C=i_clk D=$0\xv[15:0][5] Q=xv[5] +.subckt dff C=i_clk D=$0\xv[15:0][6] Q=xv[6] +.subckt dff C=i_clk D=$0\xv[15:0][7] Q=xv[7] +.subckt dff C=i_clk D=$0\xv[15:0][8] Q=xv[8] +.subckt dff C=i_clk D=$0\xv[15:0][9] Q=xv[9] +.subckt dff C=i_clk D=$0\xv[15:0][10] Q=xv[10] +.subckt dff C=i_clk D=$0\xv[15:0][11] Q=xv[11] +.subckt dff C=i_clk D=$0\xv[15:0][12] Q=xv[12] +.subckt dff C=i_clk D=$0\xv[15:0][13] Q=xv[13] +.subckt dff C=i_clk D=$0\xv[15:0][14] Q=xv[14] +.subckt dff C=i_clk D=$0\xv[15:0][15] Q=xv[15] +.subckt dff C=i_clk D=$0\yv[15:0][0] Q=yv[0] +.subckt dff C=i_clk D=$0\yv[15:0][1] Q=yv[1] +.subckt dff C=i_clk D=$0\yv[15:0][2] Q=yv[2] +.subckt dff C=i_clk D=$0\yv[15:0][3] Q=yv[3] +.subckt dff C=i_clk D=$0\yv[15:0][4] Q=yv[4] +.subckt dff C=i_clk D=$0\yv[15:0][5] Q=yv[5] +.subckt dff C=i_clk D=$0\yv[15:0][6] Q=yv[6] +.subckt dff C=i_clk D=$0\yv[15:0][7] Q=yv[7] +.subckt dff C=i_clk D=$0\yv[15:0][8] Q=yv[8] +.subckt dff C=i_clk D=$0\yv[15:0][9] Q=yv[9] +.subckt dff C=i_clk D=$0\yv[15:0][10] Q=yv[10] +.subckt dff C=i_clk D=$0\yv[15:0][11] Q=yv[11] +.subckt dff C=i_clk D=$0\yv[15:0][12] Q=yv[12] +.subckt dff C=i_clk D=$0\yv[15:0][13] Q=yv[13] +.subckt dff C=i_clk D=$0\yv[15:0][14] Q=yv[14] +.subckt dff C=i_clk D=$0\yv[15:0][15] Q=yv[15] +.subckt dff C=i_clk D=$0\ph[19:0][0] Q=ph[0] +.subckt dff C=i_clk D=$0\ph[19:0][1] Q=ph[1] +.subckt dff C=i_clk D=$0\ph[19:0][2] Q=ph[2] +.subckt dff C=i_clk D=$0\ph[19:0][3] Q=ph[3] +.subckt dff C=i_clk D=$0\ph[19:0][4] Q=ph[4] +.subckt dff C=i_clk D=$0\ph[19:0][5] Q=ph[5] +.subckt dff C=i_clk D=$0\ph[19:0][6] Q=ph[6] +.subckt dff C=i_clk D=$0\ph[19:0][7] Q=ph[7] +.subckt dff C=i_clk D=$0\ph[19:0][8] Q=ph[8] +.subckt dff C=i_clk D=$0\ph[19:0][9] Q=ph[9] +.subckt dff C=i_clk D=$0\ph[19:0][10] Q=ph[10] +.subckt dff C=i_clk D=$0\ph[19:0][11] Q=ph[11] +.subckt dff C=i_clk D=$0\ph[19:0][12] Q=ph[12] +.subckt dff C=i_clk D=$0\ph[19:0][13] Q=ph[13] +.subckt dff C=i_clk D=$0\ph[19:0][14] Q=ph[14] +.subckt dff C=i_clk D=$0\ph[19:0][15] Q=ph[15] +.subckt dff C=i_clk D=$0\ph[19:0][16] Q=ph[16] +.subckt dff C=i_clk D=$0\ph[19:0][17] Q=ph[17] +.subckt dff C=i_clk D=$0\ph[19:0][18] Q=ph[18] +.subckt dff C=i_clk D=$0\ph[19:0][19] Q=ph[19] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.CO[3] Q=o_done R=i_reset +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[9] Q=cangle[9] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[10] Q=cangle[10] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[11] Q=cangle[11] R=state[3] +.subckt sdffr C=i_clk D=$abc$4039$memory\cordic_angle$rdmux[0][0][0]$a$858[12] Q=cangle[12] R=state[3] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=state[0] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[1] Q=state[1] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[2] Q=state[2] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[3] Q=state[3] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$636 +.subckt sdffr C=i_clk D=$abc$4039$logic_and$./benchmark/seqcordic.v:112$19_Y Q=pre_valid R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$688.Y[0] Q=cangle[14] R=$abc$4039$auto$opt_dff.cc:253:combine_resets$907 +.subckt dff C=i_clk D=$false Q=prey[0] +.subckt dff C=i_clk D=$false Q=prey[1] +.subckt dff C=i_clk D=$0\prey[15:0][2] Q=prey[2] +.subckt dff C=i_clk D=$0\prey[15:0][3] Q=prey[3] +.subckt dff C=i_clk D=$0\prey[15:0][4] Q=prey[4] +.subckt dff C=i_clk D=$0\prey[15:0][5] Q=prey[5] +.subckt dff C=i_clk D=$0\prey[15:0][6] Q=prey[6] +.subckt dff C=i_clk D=$0\prey[15:0][7] Q=prey[7] +.subckt dff C=i_clk D=$0\prey[15:0][8] Q=prey[8] +.subckt dff C=i_clk D=$0\prey[15:0][9] Q=prey[9] +.subckt dff C=i_clk D=$0\prey[15:0][10] Q=prey[10] +.subckt dff C=i_clk D=$0\prey[15:0][11] Q=prey[11] +.subckt dff C=i_clk D=$0\prey[15:0][12] Q=prey[12] +.subckt dff C=i_clk D=$0\prey[15:0][13] Q=prey[13] +.subckt dff C=i_clk D=$0\prey[15:0][14] Q=prey[14] +.subckt dff C=i_clk D=$0\prey[15:0][15] Q=prey[15] +.subckt dff C=i_clk D=i_phase[0] Q=preph[0] +.subckt dff C=i_clk D=i_phase[1] Q=preph[1] +.subckt dff C=i_clk D=i_phase[2] Q=preph[2] +.subckt dff C=i_clk D=i_phase[3] Q=preph[3] +.subckt dff C=i_clk D=i_phase[4] Q=preph[4] +.subckt dff C=i_clk D=i_phase[5] Q=preph[5] +.subckt dff C=i_clk D=i_phase[6] Q=preph[6] +.subckt dff C=i_clk D=i_phase[7] Q=preph[7] +.subckt dff C=i_clk D=i_phase[8] Q=preph[8] +.subckt dff C=i_clk D=i_phase[9] Q=preph[9] +.subckt dff C=i_clk D=i_phase[10] Q=preph[10] +.subckt dff C=i_clk D=i_phase[11] Q=preph[11] +.subckt dff C=i_clk D=i_phase[12] Q=preph[12] +.subckt dff C=i_clk D=i_phase[13] Q=preph[13] +.subckt dff C=i_clk D=i_phase[14] Q=preph[14] +.subckt dff C=i_clk D=i_phase[15] Q=preph[15] +.subckt dff C=i_clk D=i_phase[16] Q=preph[16] +.subckt dff C=i_clk D=i_phase[17] Q=preph[17] +.subckt dff C=i_clk D=i_phase[17] Q=preph[18] +.subckt dff C=i_clk D=i_phase[17] Q=preph[19] +.subckt sdffr C=i_clk D=$abc$4039$auto$rtlil.cc:2693:MuxGate$3876 Q=aux R=i_reset +.names $false $0\prex[15:0][0] +1 1 +.names $false $0\prex[15:0][1] +1 1 +.names $false $0\prey[15:0][0] +1 1 +.names $false $0\prey[15:0][1] +1 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$688.CO[0] +1 1 +.names $false cangle[17] +1 1 +.names $false cangle[18] +1 1 +.names $false cangle[19] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif new file mode 100644 index 00000000000..fd71bc8657f --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/seqpolar.blif @@ -0,0 +1,6314 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model seqpolar +.inputs i_clk i_reset i_stb i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux +.outputs o_busy o_done o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux +.names $false +.names $true +1 +.names $undef +.names state[4] $abc$4719$new_n362 state[1] state[0] last_state +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[3] state[2] $abc$4719$new_n362 +00 1 +.names last_state ph[19] o_phase[19] $abc$4719$auto$rtlil.cc:2693:MuxGate$4488 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[18] o_phase[18] $abc$4719$auto$rtlil.cc:2693:MuxGate$4490 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[17] o_phase[17] $abc$4719$auto$rtlil.cc:2693:MuxGate$4492 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[16] o_phase[16] $abc$4719$auto$rtlil.cc:2693:MuxGate$4494 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[15] o_phase[15] $abc$4719$auto$rtlil.cc:2693:MuxGate$4496 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[14] o_phase[14] $abc$4719$auto$rtlil.cc:2693:MuxGate$4498 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[13] o_phase[13] $abc$4719$auto$rtlil.cc:2693:MuxGate$4500 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[12] o_phase[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4502 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[11] o_phase[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4504 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[10] o_phase[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4506 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[9] o_phase[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4508 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[8] o_phase[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4510 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[7] o_phase[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4512 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[6] o_phase[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4514 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[5] o_phase[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4516 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[4] o_phase[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4518 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[3] o_phase[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4520 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[2] o_phase[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4522 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[1] o_phase[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4524 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[0] o_phase[0] $abc$4719$auto$rtlil.cc:2693:MuxGate$4526 +001 1 +011 1 +110 1 +111 1 +.names last_state xv[19] xv[18] $abc$4719$new_n384 o_mag[11] $abc$4719$auto$rtlil.cc:2693:MuxGate$4528 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17] xv[16] $abc$4719$new_n385 $abc$4719$new_n384 +111 1 +.names xv[15] xv[14] $abc$4719$new_n386 $abc$4719$new_n385 +111 1 +.names xv[13] xv[12] $abc$4719$new_n387 $abc$4719$new_n386 +111 1 +.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n387 +11111 1 +.names last_state xv[18] $abc$4719$new_n384 o_mag[10] $abc$4719$auto$rtlil.cc:2693:MuxGate$4530 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[17] xv[16] $abc$4719$new_n385 o_mag[9] $abc$4719$auto$rtlil.cc:2693:MuxGate$4532 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[16] $abc$4719$new_n385 o_mag[8] $abc$4719$auto$rtlil.cc:2693:MuxGate$4534 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[15] xv[14] $abc$4719$new_n386 o_mag[7] $abc$4719$auto$rtlil.cc:2693:MuxGate$4536 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[14] $abc$4719$new_n386 o_mag[6] $abc$4719$auto$rtlil.cc:2693:MuxGate$4538 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state xv[13] xv[12] $abc$4719$new_n387 o_mag[5] $abc$4719$auto$rtlil.cc:2693:MuxGate$4540 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[12] $abc$4719$new_n387 o_mag[4] $abc$4719$auto$rtlil.cc:2693:MuxGate$4542 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names last_state $abc$4719$new_n396 o_mag[3] $abc$4719$auto$rtlil.cc:2693:MuxGate$4544 +001 1 +011 1 +110 1 +111 1 +.names xv[11] xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n396 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names last_state $abc$4719$new_n398 o_mag[2] $abc$4719$auto$rtlil.cc:2693:MuxGate$4546 +001 1 +011 1 +110 1 +111 1 +.names xv[10] xv[9] xv[7] xv[8] $abc$4719$new_n398 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names last_state xv[9] xv[7] xv[8] o_mag[1] $abc$4719$auto$rtlil.cc:2693:MuxGate$4548 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names last_state xv[7] xv[8] o_mag[0] $abc$4719$new_n401 $abc$4719$auto$rtlil.cc:2693:MuxGate$4550 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$4719$new_n402 xv[2] xv[1] xv[0] $abc$4719$new_n401 +1000 1 +.names xv[6] xv[5] xv[4] xv[3] $abc$4719$new_n402 +0000 1 +.names last_state aux o_aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4552 +001 1 +011 1 +110 1 +111 1 +.names last_state ph[20] o_phase[20] $abc$4719$auto$rtlil.cc:2693:MuxGate$4554 +001 1 +011 1 +110 1 +111 1 +.names last_state xv[20] $abc$4719$new_n406 o_mag[12] $abc$4719$auto$rtlil.cc:2693:MuxGate$4556 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[19] xv[18] $abc$4719$new_n384 $abc$4719$new_n406 +111 1 +.names i_stb last_state idle $abc$4719$auto$rtlil.cc:2693:MuxGate$4558 +001 1 +010 1 +011 1 +.names i_stb idle $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y +11 1 +.names $abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y i_aux aux $abc$4719$auto$rtlil.cc:2693:MuxGate$4560 +001 1 +011 1 +110 1 +111 1 +.names i_reset idle last_state $abc$4719$auto$opt_dff.cc:253:combine_resets$656 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +111 1 +.names state[1] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 $abc$4719$auto$opt_dff.cc:253:combine_resets$901 +00 1 +01 1 +11 1 +.names $abc$4719$new_n362 state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$904 +00 1 +01 1 +11 1 +.names state[3] state[4] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 +01 1 +10 1 +11 1 +.names i_xval[0] i_yval[0] $0\prex[20:0][6] +01 1 +10 1 +.names i_xval[12] i_xval[0] i_yval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prey[20:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n418 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$4719$new_n419 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$4719$new_n421 $abc$4719$new_n434 $abc$4719$new_n432 $0\prey[20:0][8] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n427 $abc$4719$new_n430 $abc$4719$new_n421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n426 $abc$4719$new_n423 $abc$4719$new_n422 +00 1 +11 1 +.names i_yval[2] $abc$4719$new_n424 $abc$4719$new_n423 +00 1 +11 1 +.names i_xval[2] $abc$4719$new_n425 $abc$4719$new_n424 +00 1 +11 1 +.names i_xval[1] i_xval[0] $abc$4719$new_n425 +00 1 +.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n426 +0001 1 +0100 1 +0101 1 +1101 1 +1110 1 +1111 1 +.names $abc$4719$new_n429 i_xval[1] i_yval[1] $abc$4719$new_n428 $abc$4719$new_n427 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[0] i_xval[0] $abc$4719$new_n428 +10 1 +.names i_yval[2] i_xval[2] $abc$4719$new_n429 +00 1 +11 1 +.names $abc$4719$new_n431 $abc$4719$new_n429 $abc$4719$new_n430 +01 1 +10 1 +.names i_xval[0] i_yval[0] i_yval[1] i_xval[1] $abc$4719$new_n431 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$4719$new_n433 $abc$4719$new_n423 $abc$4719$new_n432 +00 1 +11 1 +.names i_xval[1] i_yval[1] i_xval[0] i_yval[0] $abc$4719$new_n433 +0011 1 +0110 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n434 +00 1 +.names $abc$4719$new_n445 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n436 $0\prey[20:0][9] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n437 $abc$4719$new_n440 $abc$4719$new_n442 $abc$4719$new_n436 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n438 i_yval[2] $abc$4719$new_n426 $abc$4719$new_n424 $abc$4719$new_n437 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n438 +00 1 +11 1 +.names i_xval[3] $abc$4719$new_n425 i_xval[2] $abc$4719$new_n439 +000 1 +001 1 +011 1 +110 1 +.names $abc$4719$new_n441 $abc$4719$new_n438 $abc$4719$new_n440 +01 1 +10 1 +.names i_yval[2] $abc$4719$new_n433 $abc$4719$new_n424 $abc$4719$new_n441 +000 1 +001 1 +010 1 +100 1 +.names i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n442 +001 1 +010 1 +100 1 +111 1 +.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$4719$new_n428 $abc$4719$new_n443 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[2] i_xval[2] $abc$4719$new_n431 $abc$4719$new_n444 +000 1 +001 1 +011 1 +101 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n445 +10 1 +.names $abc$4719$new_n447 $abc$4719$new_n445 $abc$4719$new_n455 $0\prey[20:0][10] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n453 $abc$4719$new_n447 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n448 +000 1 +011 1 +101 1 +110 1 +.names i_yval[3] $abc$4719$new_n439 $abc$4719$new_n441 $abc$4719$new_n449 +000 1 +001 1 +011 1 +101 1 +.names i_xval[4] $abc$4719$new_n425 i_xval[3] i_xval[2] $abc$4719$new_n450 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n451 +001 1 +010 1 +100 1 +111 1 +.names i_yval[2] $abc$4719$new_n426 i_yval[3] $abc$4719$new_n439 $abc$4719$new_n424 $abc$4719$new_n452 +00100 1 +00101 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n443 $abc$4719$new_n453 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[4] i_xval[4] $abc$4719$new_n454 +00 1 +11 1 +.names $abc$4719$new_n454 i_xval[3] i_yval[3] $abc$4719$new_n444 $abc$4719$new_n455 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$4719$new_n457 $abc$4719$new_n445 $abc$4719$new_n466 $0\prey[20:0][11] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n464 $abc$4719$new_n457 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n458 +000 1 +011 1 +101 1 +110 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n449 $abc$4719$new_n459 +000 1 +001 1 +011 1 +101 1 +.names i_xval[5] $abc$4719$new_n461 $abc$4719$new_n460 +00 1 +11 1 +.names $abc$4719$new_n425 i_xval[4] i_xval[3] i_xval[2] $abc$4719$new_n461 +1000 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n462 +001 1 +010 1 +100 1 +111 1 +.names i_yval[4] $abc$4719$new_n450 $abc$4719$new_n452 $abc$4719$new_n463 +001 1 +100 1 +101 1 +111 1 +.names i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n464 +001 1 +010 1 +100 1 +111 1 +.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$4719$new_n443 $abc$4719$new_n465 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n466 +000 1 +011 1 +101 1 +110 1 +.names i_xval[3] i_yval[3] i_yval[4] i_xval[4] $abc$4719$new_n444 $abc$4719$new_n467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n469 i_xval[12] $abc$4719$new_n474 i_yval[12] $0\prey[20:0][12] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1110 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n470 $abc$4719$new_n472 $abc$4719$new_n473 $abc$4719$new_n469 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[6] i_xval[6] $abc$4719$new_n471 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n470 +00010 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01110 1 +10000 1 +10001 1 +10011 1 +10110 1 +11010 1 +11100 1 +11101 1 +11111 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n459 $abc$4719$new_n471 +000 1 +001 1 +011 1 +101 1 +.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n467 $abc$4719$new_n472 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[6] i_xval[6] i_xval[5] i_yval[5] $abc$4719$new_n465 $abc$4719$new_n473 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_yval[6] i_xval[6] $abc$4719$new_n475 $abc$4719$new_n461 i_xval[5] $abc$4719$new_n474 +00000 1 +00001 1 +00011 1 +00110 1 +01010 1 +01100 1 +01101 1 +01111 1 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11110 1 +.names i_yval[5] $abc$4719$new_n460 $abc$4719$new_n463 $abc$4719$new_n475 +001 1 +100 1 +101 1 +111 1 +.names $abc$4719$new_n477 $abc$4719$new_n445 $abc$4719$new_n485 $0\prey[20:0][13] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n483 $abc$4719$new_n477 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n479 $abc$4719$new_n478 +000 1 +011 1 +101 1 +110 1 +.names i_xval[6] $abc$4719$new_n461 i_xval[5] i_yval[6] $abc$4719$new_n471 $abc$4719$new_n479 +00001 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_xval[7] $abc$4719$new_n461 i_xval[6] i_xval[5] $abc$4719$new_n480 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n482 $abc$4719$new_n481 +001 1 +010 1 +100 1 +111 1 +.names i_xval[6] $abc$4719$new_n461 i_yval[6] i_xval[5] $abc$4719$new_n475 $abc$4719$new_n482 +00101 1 +00111 1 +01001 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$4719$new_n484 $abc$4719$new_n483 +001 1 +010 1 +100 1 +111 1 +.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$4719$new_n465 $abc$4719$new_n484 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$4719$new_n486 $abc$4719$new_n485 +000 1 +011 1 +101 1 +110 1 +.names i_xval[5] i_yval[5] i_yval[6] i_xval[6] $abc$4719$new_n467 $abc$4719$new_n486 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n488 $abc$4719$new_n445 $abc$4719$new_n495 $0\prey[20:0][14] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n494 $abc$4719$new_n488 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n490 $abc$4719$new_n489 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n479 $abc$4719$new_n490 +000 1 +001 1 +011 1 +101 1 +.names i_xval[8] $abc$4719$new_n461 i_xval[7] i_xval[6] i_xval[5] $abc$4719$new_n491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n493 $abc$4719$new_n492 +001 1 +010 1 +100 1 +111 1 +.names i_yval[7] $abc$4719$new_n480 $abc$4719$new_n482 $abc$4719$new_n493 +001 1 +100 1 +101 1 +111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$4719$new_n484 $abc$4719$new_n494 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$4719$new_n486 $abc$4719$new_n495 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n499 $abc$4719$new_n498 +000 1 +011 1 +101 1 +110 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n490 $abc$4719$new_n499 +000 1 +001 1 +011 1 +101 1 +.names i_xval[9] $abc$4719$new_n501 $abc$4719$new_n500 +00 1 +11 1 +.names $abc$4719$new_n461 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$4719$new_n501 +10000 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n503 $abc$4719$new_n502 +001 1 +010 1 +100 1 +111 1 +.names i_yval[8] $abc$4719$new_n491 $abc$4719$new_n493 $abc$4719$new_n503 +001 1 +100 1 +101 1 +111 1 +.names i_yval[9] i_xval[9] $abc$4719$new_n505 $abc$4719$new_n504 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] i_xval[7] i_yval[8] i_xval[8] $abc$4719$new_n486 $abc$4719$new_n505 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$4719$new_n484 $abc$4719$new_n507 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n509 $abc$4719$new_n445 $abc$4719$new_n517 $0\prey[20:0][16] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n516 $abc$4719$new_n509 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n512 $abc$4719$new_n511 $abc$4719$new_n510 +01 1 +10 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n499 $abc$4719$new_n511 +000 1 +001 1 +011 1 +101 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n512 +00 1 +11 1 +.names i_xval[10] $abc$4719$new_n501 i_xval[9] $abc$4719$new_n513 +000 1 +001 1 +011 1 +110 1 +.names $abc$4719$new_n512 $abc$4719$new_n515 $abc$4719$new_n514 +00 1 +11 1 +.names i_yval[9] $abc$4719$new_n500 $abc$4719$new_n503 $abc$4719$new_n515 +001 1 +100 1 +101 1 +111 1 +.names i_xval[10] i_yval[10] i_yval[9] i_xval[9] $abc$4719$new_n507 $abc$4719$new_n516 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_xval[10] i_yval[10] i_yval[9] i_xval[9] $abc$4719$new_n505 $abc$4719$new_n517 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$4719$new_n523 $abc$4719$new_n434 $abc$4719$new_n519 $0\prey[20:0][17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$4719$new_n521 $abc$4719$new_n520 $abc$4719$new_n519 +01 1 +10 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n511 $abc$4719$new_n520 +000 1 +001 1 +011 1 +101 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n521 +00 1 +11 1 +.names i_xval[11] $abc$4719$new_n501 i_xval[10] i_xval[9] $abc$4719$new_n522 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n528 $abc$4719$new_n523 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$4719$new_n521 $abc$4719$new_n525 $abc$4719$new_n524 +00 1 +11 1 +.names i_yval[10] $abc$4719$new_n513 $abc$4719$new_n515 $abc$4719$new_n525 +001 1 +100 1 +101 1 +111 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n526 +000 1 +011 1 +101 1 +110 1 +.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n505 $abc$4719$new_n527 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n529 $abc$4719$new_n528 +001 1 +010 1 +100 1 +111 1 +.names i_yval[9] i_xval[9] i_xval[10] i_yval[10] $abc$4719$new_n507 $abc$4719$new_n529 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names i_xval[12] $abc$4719$new_n535 $abc$4719$new_n537 i_yval[12] $abc$4719$new_n967 $0\prey[20:0][18] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n520 $abc$4719$new_n533 +000 1 +001 1 +011 1 +101 1 +.names i_yval[11] i_xval[11] $abc$4719$new_n527 $abc$4719$new_n534 +000 1 +001 1 +011 1 +101 1 +.names $abc$4719$new_n501 i_xval[11] i_xval[10] i_xval[9] $abc$4719$new_n535 +1000 1 +.names i_yval[11] $abc$4719$new_n522 $abc$4719$new_n525 $abc$4719$new_n537 +001 1 +100 1 +101 1 +111 1 +.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][19] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +.names state[1] state[3] state[2] state[4] state[0] $\cordic_angle$rdreg[0]$d[0] +00001 1 +00011 1 +01000 1 +01001 1 +10001 1 +10100 1 +10101 1 +11001 1 +11101 1 +.names state[4] state[0] state[3] state[1] state[2] $\cordic_angle$rdreg[0]$d[1] +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +.names state[1] state[2] state[0] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] +0010 1 +0011 1 +0110 1 +0111 1 +1100 1 +1110 1 +1111 1 +.names state[3] state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] +0001 1 +0011 1 +0101 1 +1000 1 +1001 1 +1101 1 +.names state[2] state[0] state[1] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[4] +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names state[0] state[1] state[2] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[5] +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1100 1 +.names state[0] state[2] state[1] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[6] +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names state[1] state[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] +00 1 +.names state[3] state[0] state[2] state[1] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[7] +0000 1 +0010 1 +1000 1 +1001 1 +.names state[0] state[1] state[2] state[3] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[8] +1000 1 +1001 1 +1100 1 +1110 1 +.names state[0] state[3] state[1] state[2] $abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[9] +0010 1 +0011 1 +0100 1 +1000 1 +.names state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] +10 1 +.names state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] +000 1 +010 1 +110 1 +111 1 +.names state[2] state[0] state[1] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] +000 1 +010 1 +100 1 +101 1 +.names state[0] state[1] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] +000 1 +100 1 +101 1 +110 1 +.names state[1] state[0] state[2] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] +001 1 +010 1 +100 1 +.names cangle[0] ph[0] $abc$4719$procmux$562_Y[0] +01 1 +10 1 +.names cangle[1] ph[1] yv[20] ph[0] cangle[0] $abc$4719$procmux$562_Y[1] +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names yv[20] cangle[2] ph[2] $abc$4719$new_n559 $abc$4719$new_n558 $abc$4719$procmux$562_Y[2] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ph[0] cangle[0] cangle[1] ph[1] $abc$4719$new_n558 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names cangle[0] cangle[1] ph[0] ph[1] $abc$4719$new_n559 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[20] cangle[3] ph[3] $abc$4719$new_n562 $abc$4719$new_n561 $abc$4719$procmux$562_Y[3] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[2] ph[2] $abc$4719$new_n558 $abc$4719$new_n561 +000 1 +001 1 +011 1 +101 1 +.names ph[2] cangle[2] $abc$4719$new_n559 $abc$4719$new_n562 +001 1 +100 1 +101 1 +111 1 +.names yv[20] cangle[4] ph[4] $abc$4719$new_n565 $abc$4719$new_n564 $abc$4719$procmux$562_Y[4] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[3] ph[3] $abc$4719$new_n561 $abc$4719$new_n564 +000 1 +001 1 +011 1 +101 1 +.names cangle[3] ph[3] $abc$4719$new_n562 $abc$4719$new_n565 +000 1 +100 1 +101 1 +110 1 +.names cangle[5] ph[5] $abc$4719$new_n567 $abc$4719$procmux$562_Y[5] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[4] ph[4] $abc$4719$new_n565 $abc$4719$new_n564 $abc$4719$new_n567 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[6] ph[6] $abc$4719$new_n570 $abc$4719$new_n569 $abc$4719$procmux$562_Y[6] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[4] ph[4] cangle[5] ph[5] $abc$4719$new_n564 $abc$4719$new_n569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[4] cangle[5] ph[4] ph[5] $abc$4719$new_n565 $abc$4719$new_n570 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names cangle[7] ph[7] $abc$4719$new_n572 $abc$4719$procmux$562_Y[7] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[6] ph[6] $abc$4719$new_n570 $abc$4719$new_n569 $abc$4719$new_n572 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[8] ph[8] $abc$4719$new_n575 $abc$4719$new_n574 $abc$4719$procmux$562_Y[8] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[6] ph[6] cangle[7] ph[7] $abc$4719$new_n569 $abc$4719$new_n574 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[6] cangle[7] ph[6] ph[7] $abc$4719$new_n570 $abc$4719$new_n575 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names cangle[9] ph[9] $abc$4719$new_n577 $abc$4719$procmux$562_Y[9] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[8] ph[8] $abc$4719$new_n575 $abc$4719$new_n574 $abc$4719$new_n577 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[20] cangle[10] ph[10] $abc$4719$new_n582 $abc$4719$new_n579 $abc$4719$procmux$562_Y[10] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$4719$new_n581 $abc$4719$new_n580 $abc$4719$new_n579 +10 1 +.names cangle[9] cangle[8] ph[8] ph[9] $abc$4719$new_n574 $abc$4719$new_n580 +00110 1 +01010 1 +10100 1 +11000 1 +.names ph[8] cangle[8] cangle[9] ph[9] $abc$4719$new_n581 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names ph[8] cangle[8] cangle[9] ph[9] $abc$4719$new_n575 $abc$4719$new_n582 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names cangle[11] ph[11] $abc$4719$new_n584 $abc$4719$procmux$562_Y[11] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[10] ph[10] $abc$4719$new_n582 $abc$4719$new_n579 $abc$4719$new_n584 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[20] cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n586 $abc$4719$procmux$562_Y[12] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$4719$new_n588 $abc$4719$new_n587 $abc$4719$new_n586 +10 1 +.names $abc$4719$new_n580 cangle[11] cangle[10] ph[10] ph[11] $abc$4719$new_n587 +10011 1 +10101 1 +11010 1 +11100 1 +.names cangle[10] ph[10] cangle[11] ph[11] $abc$4719$new_n581 $abc$4719$new_n588 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[10] cangle[11] ph[10] ph[11] $abc$4719$new_n582 $abc$4719$new_n589 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[20] cangle[13] ph[13] $abc$4719$new_n592 $abc$4719$new_n591 $abc$4719$procmux$562_Y[13] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[12] ph[12] $abc$4719$new_n586 $abc$4719$new_n591 +000 1 +001 1 +011 1 +101 1 +.names cangle[12] ph[12] $abc$4719$new_n589 $abc$4719$new_n592 +001 1 +100 1 +101 1 +111 1 +.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$procmux$562_Y[14] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names cangle[13] ph[13] $abc$4719$new_n591 $abc$4719$new_n594 +000 1 +001 1 +011 1 +101 1 +.names ph[13] cangle[13] $abc$4719$new_n592 $abc$4719$new_n595 +000 1 +100 1 +101 1 +110 1 +.names cangle[15] ph[15] $abc$4719$new_n597 $abc$4719$procmux$562_Y[15] +001 1 +010 1 +100 1 +111 1 +.names yv[20] cangle[14] ph[14] $abc$4719$new_n595 $abc$4719$new_n594 $abc$4719$new_n597 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[20] cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n599 $abc$4719$procmux$562_Y[16] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[14] ph[14] cangle[15] ph[15] $abc$4719$new_n594 $abc$4719$new_n599 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names cangle[14] cangle[15] ph[14] ph[15] $abc$4719$new_n595 $abc$4719$new_n600 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[20] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$procmux$562_Y[17] +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names cangle[16] ph[16] $abc$4719$new_n599 $abc$4719$new_n602 +000 1 +001 1 +011 1 +101 1 +.names cangle[16] ph[16] $abc$4719$new_n600 $abc$4719$new_n603 +001 1 +100 1 +101 1 +111 1 +.names ph[18] $abc$4719$new_n605 $abc$4719$procmux$562_Y[18] +00 1 +11 1 +.names yv[20] ph[17] cangle[17] $abc$4719$new_n603 $abc$4719$new_n602 $abc$4719$new_n605 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names pre_valid ph[19] $abc$4719$new_n608 $abc$4719$new_n607 preph[19] $0\ph[20:0][19] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names ph[18] yv[20] cangle[17] ph[17] $abc$4719$new_n602 $abc$4719$new_n607 +10010 1 +10100 1 +10110 1 +10111 1 +.names yv[20] ph[18] cangle[17] ph[17] $abc$4719$new_n603 $abc$4719$new_n608 +10001 1 +10100 1 +10101 1 +10111 1 +.names pre_valid $abc$4719$new_n610 preph[20] $0\ph[20:0][20] +010 1 +011 1 +101 1 +111 1 +.names ph[20] ph[19] $abc$4719$new_n608 $abc$4719$new_n607 $abc$4719$new_n610 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names pre_valid yv[0] $abc$4719$new_n612 prey[0] $0\yv[20:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4719$new_n613 $abc$4719$new_n619 state[4] $abc$4719$new_n616 $abc$4719$new_n612 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names state[4] state[3] state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n613 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n615 xv[19] xv[18] $abc$4719$new_n614 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[17] xv[16] $abc$4719$new_n615 +000 1 +010 1 +100 1 +101 1 +.names state[2] state[3] $abc$4719$new_n617 $abc$4719$new_n616 +100 1 +.names state[1] state[0] $abc$4719$new_n618 xv[5] xv[4] $abc$4719$new_n617 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[7] xv[6] $abc$4719$new_n618 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n624 state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n619 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names state[1] state[0] $abc$4719$new_n621 xv[11] xv[10] $abc$4719$new_n620 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[9] xv[8] $abc$4719$new_n621 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n623 xv[15] xv[14] $abc$4719$new_n622 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[13] xv[12] $abc$4719$new_n623 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n362 $abc$4719$new_n625 xv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n624 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[1] state[0] xv[3] xv[1] xv[2] $abc$4719$new_n625 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n627 prey[1] $0\yv[20:0][1] +010 1 +011 1 +101 1 +111 1 +.names yv[1] $abc$4719$new_n1009 yv[0] yv[20] $abc$4719$new_n612 $abc$4719$new_n627 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n631 xv[20] xv[19] $abc$4719$new_n630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[18] xv[17] $abc$4719$new_n631 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n634 xv[12] xv[11] $abc$4719$new_n633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[10] xv[9] $abc$4719$new_n634 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n636 xv[16] xv[15] $abc$4719$new_n635 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] xv[14] xv[13] $abc$4719$new_n636 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n639 xv[6] xv[5] $abc$4719$new_n638 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[8] xv[7] $abc$4719$new_n639 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n642 xv[2] xv[1] $abc$4719$new_n641 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] xv[4] xv[3] $abc$4719$new_n642 +000 1 +010 1 +100 1 +101 1 +.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n646 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names yv[0] $abc$4719$new_n613 $abc$4719$new_n616 $abc$4719$new_n619 state[4] $abc$4719$new_n648 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n649 +000 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n653 $abc$4719$new_n652 $abc$4719$new_n651 state[2] $abc$4719$new_n650 +00000 1 +00010 1 +00011 1 +.names state[1] $abc$4719$new_n621 $abc$4719$new_n618 $abc$4719$new_n651 +001 1 +011 1 +110 1 +111 1 +.names state[0] state[2] state[1] xv[3] xv[2] $abc$4719$new_n652 +00001 1 +00011 1 +10010 1 +10011 1 +.names state[1] state[0] state[2] xv[5] xv[4] $abc$4719$new_n653 +10001 1 +10011 1 +11010 1 +11011 1 +.names state[3] state[2] state[4] $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n654 +10010 1 +10011 1 +11001 1 +11011 1 +.names state[1] state[0] $abc$4719$new_n623 xv[11] xv[10] $abc$4719$new_n655 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n615 xv[15] xv[14] $abc$4719$new_n656 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] state[3] state[2] xv[20] $abc$4719$new_n658 $abc$4719$new_n657 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] xv[20] xv[19] xv[18] $abc$4719$new_n658 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[3] $abc$4719$new_n976 $abc$4719$new_n660 prey[3] $0\yv[20:0][3] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n661 $abc$4719$new_n974 $abc$4719$new_n660 +000 1 +010 1 +100 1 +101 1 +.names yv[1] $abc$4719$new_n1009 yv[2] $abc$4719$new_n649 $abc$4719$new_n648 $abc$4719$new_n661 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names state[4] state[3] $abc$4719$new_n667 $abc$4719$new_n670 xv[20] $abc$4719$new_n666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[2] $abc$4719$new_n668 $abc$4719$new_n669 $abc$4719$new_n667 +010 1 +011 1 +101 1 +111 1 +.names state[1] state[0] $abc$4719$new_n636 xv[12] xv[11] $abc$4719$new_n668 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n631 xv[16] xv[15] $abc$4719$new_n669 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4719$new_n671 xv[20] $abc$4719$new_n670 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] xv[20] xv[19] $abc$4719$new_n671 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] $abc$4719$new_n634 $abc$4719$new_n639 $abc$4719$new_n672 +001 1 +011 1 +110 1 +111 1 +.names pre_valid yv[4] $abc$4719$new_n677 $abc$4719$new_n676 prey[4] $0\yv[20:0][4] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[3] yv[20] $abc$4719$new_n976 $abc$4719$new_n974 $abc$4719$new_n661 $abc$4719$new_n676 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names state[4] $abc$4719$new_n678 $abc$4719$new_n679 xv[20] $abc$4719$new_n677 +0010 1 +0011 1 +1000 1 +1010 1 +.names state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n678 +10000 1 +10010 1 +11000 1 +11001 1 +.names state[2] state[3] $abc$4719$new_n620 $abc$4719$new_n617 $abc$4719$new_n679 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4719$new_n681 prey[5] $0\yv[20:0][5] +000 1 +001 1 +101 1 +111 1 +.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n681 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$4719$new_n661 yv[3] yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n682 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3] $abc$4719$new_n974 yv[4] $abc$4719$new_n677 $abc$4719$new_n976 $abc$4719$new_n683 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] $abc$4719$new_n686 xv[20] $abc$4719$new_n685 state[3] $abc$4719$new_n684 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n630 $abc$4719$new_n635 $abc$4719$new_n685 +001 1 +011 1 +110 1 +111 1 +.names state[2] state[3] $abc$4719$new_n633 $abc$4719$new_n638 $abc$4719$new_n686 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[6] $abc$4719$new_n692 $abc$4719$new_n691 +01 1 +10 1 +.names state[4] $abc$4719$new_n694 xv[20] $abc$4719$new_n693 state[3] $abc$4719$new_n692 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n656 $abc$4719$new_n658 $abc$4719$new_n693 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n651 $abc$4719$new_n655 $abc$4719$new_n694 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid yv[7] $abc$4719$new_n700 $abc$4719$new_n696 prey[7] $0\yv[20:0][7] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n697 $abc$4719$new_n699 $abc$4719$new_n698 $abc$4719$new_n696 +0000 1 +0001 1 +0010 1 +0011 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[5] $abc$4719$new_n684 yv[6] $abc$4719$new_n692 $abc$4719$new_n683 $abc$4719$new_n697 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n691 yv[5] $abc$4719$new_n684 $abc$4719$new_n682 $abc$4719$new_n698 +0000 1 +0100 1 +0101 1 +0110 1 +.names yv[6] $abc$4719$new_n692 $abc$4719$new_n699 +10 1 +.names state[4] $abc$4719$new_n702 xv[20] $abc$4719$new_n701 state[3] $abc$4719$new_n700 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n669 $abc$4719$new_n671 $abc$4719$new_n701 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n672 $abc$4719$new_n668 $abc$4719$new_n702 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid yv[8] $abc$4719$new_n707 $abc$4719$new_n704 prey[8] $0\yv[20:0][8] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[7] yv[20] $abc$4719$new_n696 $abc$4719$new_n700 $abc$4719$new_n704 +0001 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names $abc$4719$new_n699 $abc$4719$new_n700 yv[7] $abc$4719$new_n706 +000 1 +010 1 +011 1 +.names $abc$4719$new_n708 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n620 $abc$4719$new_n622 $abc$4719$new_n707 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n614 $abc$4719$new_n708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n710 prey[9] $0\yv[20:0][9] +010 1 +011 1 +101 1 +111 1 +.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n710 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[8] $abc$4719$new_n707 $abc$4719$new_n706 $abc$4719$new_n698 $abc$4719$new_n712 $abc$4719$new_n711 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n700 yv[7] $abc$4719$new_n712 +10 1 +.names yv[7] $abc$4719$new_n700 yv[8] $abc$4719$new_n707 $abc$4719$new_n697 $abc$4719$new_n713 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n715 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n633 $abc$4719$new_n635 $abc$4719$new_n714 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n715 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n721 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n655 $abc$4719$new_n656 $abc$4719$new_n720 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n658 $abc$4719$new_n721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n723 prey[11] $0\yv[20:0][11] +010 1 +011 1 +101 1 +111 1 +.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n723 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n714 yv[9] yv[10] $abc$4719$new_n720 $abc$4719$new_n711 $abc$4719$new_n724 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9] $abc$4719$new_n714 yv[10] $abc$4719$new_n720 $abc$4719$new_n713 $abc$4719$new_n725 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[4] state[3] xv[20] $abc$4719$new_n667 $abc$4719$new_n670 $abc$4719$new_n726 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid yv[12] $abc$4719$new_n729 $abc$4719$new_n728 prey[12] $0\yv[20:0][12] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[11] $abc$4719$new_n726 yv[20] $abc$4719$new_n725 $abc$4719$new_n724 $abc$4719$new_n728 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 state[2] xv[20] $abc$4719$new_n614 $abc$4719$new_n622 $abc$4719$new_n729 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n731 prey[13] $0\yv[20:0][13] +000 1 +001 1 +101 1 +111 1 +.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n731 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$4719$new_n726 yv[11] yv[12] $abc$4719$new_n729 $abc$4719$new_n724 $abc$4719$new_n732 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11] $abc$4719$new_n726 yv[12] $abc$4719$new_n729 $abc$4719$new_n725 $abc$4719$new_n733 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n685 xv[20] $abc$4719$new_n734 +010 1 +011 1 +100 1 +110 1 +.names yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n737 +000 1 +100 1 +101 1 +110 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n693 xv[20] $abc$4719$new_n739 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[15] $abc$4719$new_n745 $abc$4719$new_n741 prey[15] $0\yv[20:0][15] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n742 $abc$4719$new_n743 $abc$4719$new_n744 $abc$4719$new_n737 $abc$4719$new_n741 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[13] $abc$4719$new_n734 yv[14] $abc$4719$new_n739 $abc$4719$new_n733 $abc$4719$new_n742 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names $abc$4719$new_n739 yv[14] $abc$4719$new_n743 +10 1 +.names yv[14] $abc$4719$new_n739 $abc$4719$new_n744 +10 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n701 xv[20] $abc$4719$new_n745 +010 1 +011 1 +100 1 +110 1 +.names pre_valid yv[16] $abc$4719$new_n750 $abc$4719$new_n747 prey[16] $0\yv[20:0][16] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[15] yv[20] $abc$4719$new_n745 $abc$4719$new_n742 $abc$4719$new_n748 $abc$4719$new_n747 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n749 yv[13] $abc$4719$new_n734 $abc$4719$new_n732 $abc$4719$new_n744 $abc$4719$new_n748 +10000 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n743 $abc$4719$new_n745 yv[15] $abc$4719$new_n749 +000 1 +001 1 +011 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n614 $abc$4719$new_n750 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[17] $abc$4719$new_n755 $abc$4719$new_n752 prey[17] $0\yv[20:0][17] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n753 $abc$4719$new_n754 $abc$4719$new_n752 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n748 yv[16] $abc$4719$new_n750 yv[15] $abc$4719$new_n745 $abc$4719$new_n753 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names yv[15] $abc$4719$new_n745 yv[16] $abc$4719$new_n750 $abc$4719$new_n742 $abc$4719$new_n754 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n630 $abc$4719$new_n755 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[18] $abc$4719$new_n758 $abc$4719$new_n757 prey[18] $0\yv[20:0][18] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[17] $abc$4719$new_n755 yv[20] $abc$4719$new_n754 $abc$4719$new_n753 $abc$4719$new_n757 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[20] state[3] state[2] state[4] $abc$4719$new_n658 $abc$4719$new_n758 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +.names pre_valid yv[19] $abc$4719$new_n763 $abc$4719$new_n760 prey[19] $0\yv[20:0][19] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n761 $abc$4719$new_n762 $abc$4719$new_n760 +000 1 +001 1 +100 1 +110 1 +.names yv[17] $abc$4719$new_n755 yv[18] $abc$4719$new_n758 $abc$4719$new_n754 $abc$4719$new_n761 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n755 yv[17] yv[18] $abc$4719$new_n758 $abc$4719$new_n753 $abc$4719$new_n762 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[3] state[4] xv[20] $abc$4719$new_n670 $abc$4719$new_n763 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[20] $abc$4719$new_n765 prey[20] $0\yv[20:0][20] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] $abc$4719$new_n763 yv[19] $abc$4719$new_n762 $abc$4719$new_n761 $abc$4719$new_n765 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names pre_valid xv[0] $abc$4719$new_n767 prex[0] $0\xv[20:0][0] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n767 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names state[2] $abc$4719$new_n769 yv[20] $abc$4719$new_n768 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] $abc$4719$new_n770 yv[19] yv[18] $abc$4719$new_n769 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[17] yv[16] $abc$4719$new_n770 +000 1 +010 1 +100 1 +101 1 +.names $abc$4719$new_n777 state[4] $abc$4719$new_n779 $abc$4719$new_n772 state[3] $abc$4719$new_n771 +00000 1 +00010 1 +00011 1 +.names state[2] $abc$4719$new_n774 $abc$4719$new_n773 $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n772 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10100 1 +11000 1 +11100 1 +.names state[0] state[1] yv[9] yv[8] $abc$4719$new_n773 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[11] yv[10] $abc$4719$new_n774 +1001 1 +1011 1 +1110 1 +1111 1 +.names state[0] state[1] yv[13] yv[12] $abc$4719$new_n775 +0001 1 +0011 1 +1010 1 +1011 1 +.names state[1] state[0] yv[15] yv[14] $abc$4719$new_n776 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$4719$new_n362 $abc$4719$new_n778 yv[0] $abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] $abc$4719$new_n777 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names state[1] state[0] yv[3] yv[1] yv[2] $abc$4719$new_n778 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] state[1] state[3] $abc$4719$new_n780 $abc$4719$new_n781 $abc$4719$new_n779 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[0] yv[5] yv[4] $abc$4719$new_n780 +000 1 +010 1 +100 1 +101 1 +.names state[0] yv[7] yv[6] $abc$4719$new_n781 +000 1 +010 1 +100 1 +101 1 +.names state[4] state[3] yv[20] $abc$4719$new_n782 +100 1 +101 1 +110 1 +.names pre_valid $abc$4719$new_n784 prex[1] $0\xv[20:0][1] +010 1 +011 1 +101 1 +111 1 +.names xv[1] $abc$4719$new_n984 xv[0] yv[20] $abc$4719$new_n767 $abc$4719$new_n784 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n788 yv[12] yv[11] $abc$4719$new_n787 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[10] yv[9] $abc$4719$new_n788 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n790 yv[16] yv[15] $abc$4719$new_n789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[14] yv[13] $abc$4719$new_n790 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n793 yv[6] yv[5] $abc$4719$new_n792 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[8] yv[7] $abc$4719$new_n793 +000 1 +010 1 +100 1 +101 1 +.names state[4] state[3] state[2] yv[20] $abc$4719$new_n795 $abc$4719$new_n794 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[1] state[0] $abc$4719$new_n796 yv[20] yv[19] $abc$4719$new_n795 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[0] yv[18] yv[17] $abc$4719$new_n796 +000 1 +010 1 +100 1 +101 1 +.names state[4] $abc$4719$new_n798 $abc$4719$new_n362 $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] yv[2] $abc$4719$new_n797 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names state[1] state[0] yv[4] yv[3] yv[1] $abc$4719$new_n798 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid xv[2] $abc$4719$new_n801 $abc$4719$new_n800 prex[2] $0\xv[20:0][2] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[1] $abc$4719$new_n767 xv[0] yv[20] $abc$4719$new_n984 $abc$4719$new_n800 +00011 1 +00111 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$4719$new_n810 $abc$4719$new_n986 $abc$4719$new_n802 $abc$4719$new_n801 +000 1 +.names state[3] state[2] state[4] $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n802 +10000 1 +10001 1 +11000 1 +11010 1 +.names state[1] state[0] $abc$4719$new_n804 yv[11] yv[10] $abc$4719$new_n803 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[0] yv[13] yv[12] $abc$4719$new_n804 +000 1 +010 1 +100 1 +101 1 +.names state[1] state[0] $abc$4719$new_n770 yv[15] yv[14] $abc$4719$new_n805 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n781 yv[9] yv[8] $abc$4719$new_n807 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names state[4] state[3] state[2] yv[20] $abc$4719$new_n811 $abc$4719$new_n810 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[1] state[0] yv[20] yv[19] yv[18] $abc$4719$new_n811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n813 prex[3] $0\xv[20:0][3] +010 1 +011 1 +101 1 +111 1 +.names yv[20] xv[3] $abc$4719$new_n992 $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n813 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n815 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$4719$new_n984 xv[1] xv[2] $abc$4719$new_n801 $abc$4719$new_n819 $abc$4719$new_n818 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names xv[0] $abc$4719$new_n771 $abc$4719$new_n782 state[3] $abc$4719$new_n768 $abc$4719$new_n819 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names state[2] $abc$4719$new_n823 yv[20] $abc$4719$new_n822 +010 1 +011 1 +100 1 +110 1 +.names state[1] state[0] yv[20] yv[19] $abc$4719$new_n823 +0000 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names state[1] $abc$4719$new_n788 $abc$4719$new_n793 $abc$4719$new_n825 +001 1 +011 1 +110 1 +111 1 +.names state[2] $abc$4719$new_n829 $abc$4719$new_n830 $abc$4719$new_n828 +010 1 +011 1 +101 1 +111 1 +.names state[1] state[0] $abc$4719$new_n790 yv[12] yv[11] $abc$4719$new_n829 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[1] state[0] $abc$4719$new_n796 yv[16] yv[15] $abc$4719$new_n830 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid xv[4] $abc$4719$new_n995 $abc$4719$new_n832 prex[4] $0\xv[20:0][4] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[3] $abc$4719$new_n992 yv[20] $abc$4719$new_n818 $abc$4719$new_n988 $abc$4719$new_n832 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[2] $abc$4719$new_n769 $abc$4719$new_n835 $abc$4719$new_n834 +001 1 +011 1 +110 1 +111 1 +.names $abc$4719$new_n776 $abc$4719$new_n775 $abc$4719$new_n835 +00 1 +.names pre_valid $abc$4719$new_n840 prex[5] $0\xv[20:0][5] +000 1 +001 1 +101 1 +111 1 +.names yv[20] xv[5] $abc$4719$new_n843 $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n840 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[3] $abc$4719$new_n992 xv[4] $abc$4719$new_n995 $abc$4719$new_n988 $abc$4719$new_n841 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names $abc$4719$new_n992 xv[3] xv[4] $abc$4719$new_n995 $abc$4719$new_n818 $abc$4719$new_n842 +00000 1 +00001 1 +00011 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names state[4] $abc$4719$new_n845 yv[20] $abc$4719$new_n844 state[3] $abc$4719$new_n843 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n789 $abc$4719$new_n795 $abc$4719$new_n844 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n787 $abc$4719$new_n792 $abc$4719$new_n845 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[4] $abc$4719$new_n852 yv[20] $abc$4719$new_n851 state[3] $abc$4719$new_n850 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n805 $abc$4719$new_n811 $abc$4719$new_n851 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n803 $abc$4719$new_n807 $abc$4719$new_n852 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names pre_valid $abc$4719$new_n854 prex[7] $0\xv[20:0][7] +010 1 +011 1 +101 1 +111 1 +.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n856 $abc$4719$new_n855 $abc$4719$new_n854 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names xv[5] $abc$4719$new_n843 xv[6] $abc$4719$new_n850 $abc$4719$new_n842 $abc$4719$new_n855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$4719$new_n843 xv[5] xv[6] $abc$4719$new_n850 $abc$4719$new_n841 $abc$4719$new_n856 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names state[4] $abc$4719$new_n859 yv[20] $abc$4719$new_n858 state[3] $abc$4719$new_n857 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[2] $abc$4719$new_n830 $abc$4719$new_n823 $abc$4719$new_n858 +010 1 +011 1 +101 1 +111 1 +.names state[2] state[3] $abc$4719$new_n825 $abc$4719$new_n829 $abc$4719$new_n859 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names state[4] state[3] yv[20] $abc$4719$new_n768 $abc$4719$new_n772 $abc$4719$new_n864 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid $abc$4719$new_n866 prex[9] $0\xv[20:0][9] +010 1 +011 1 +101 1 +111 1 +.names xv[9] $abc$4719$new_n869 yv[20] $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n866 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[7] $abc$4719$new_n857 xv[8] $abc$4719$new_n864 $abc$4719$new_n855 $abc$4719$new_n867 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7] xv[8] $abc$4719$new_n857 $abc$4719$new_n864 $abc$4719$new_n856 $abc$4719$new_n868 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$4719$new_n870 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n787 $abc$4719$new_n789 $abc$4719$new_n869 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] yv[20] $abc$4719$new_n795 $abc$4719$new_n870 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid xv[10] $abc$4719$new_n873 $abc$4719$new_n872 prex[10] $0\xv[20:0][10] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[9] yv[20] $abc$4719$new_n869 $abc$4719$new_n868 $abc$4719$new_n867 $abc$4719$new_n872 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$4719$new_n874 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n803 $abc$4719$new_n805 $abc$4719$new_n873 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] yv[20] $abc$4719$new_n811 $abc$4719$new_n874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pre_valid $abc$4719$new_n876 prex[11] $0\xv[20:0][11] +010 1 +011 1 +101 1 +111 1 +.names xv[11] $abc$4719$new_n879 yv[20] $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n876 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names xv[9] $abc$4719$new_n869 xv[10] $abc$4719$new_n873 $abc$4719$new_n867 $abc$4719$new_n877 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9] xv[10] $abc$4719$new_n869 $abc$4719$new_n873 $abc$4719$new_n868 $abc$4719$new_n878 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names state[4] state[3] yv[20] $abc$4719$new_n828 $abc$4719$new_n822 $abc$4719$new_n879 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names pre_valid xv[12] $abc$4719$new_n882 $abc$4719$new_n881 prex[12] $0\xv[20:0][12] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[11] yv[20] $abc$4719$new_n879 $abc$4719$new_n878 $abc$4719$new_n877 $abc$4719$new_n881 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n834 yv[20] $abc$4719$new_n882 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4719$new_n884 prex[13] $0\xv[20:0][13] +000 1 +001 1 +101 1 +111 1 +.names xv[13] $abc$4719$new_n887 yv[20] $abc$4719$new_n886 $abc$4719$new_n885 $abc$4719$new_n884 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[11] $abc$4719$new_n879 xv[12] $abc$4719$new_n882 $abc$4719$new_n877 $abc$4719$new_n885 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11] xv[12] $abc$4719$new_n879 $abc$4719$new_n882 $abc$4719$new_n878 $abc$4719$new_n886 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n844 yv[20] $abc$4719$new_n887 +010 1 +011 1 +100 1 +110 1 +.names pre_valid $abc$4719$new_n889 prex[14] $0\xv[20:0][14] +000 1 +001 1 +101 1 +111 1 +.names $abc$4719$new_n892 yv[20] $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n889 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n890 +010 1 +100 1 +110 1 +111 1 +.names xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n891 +001 1 +100 1 +101 1 +111 1 +.names xv[14] $abc$4719$new_n893 $abc$4719$new_n892 +01 1 +10 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n851 yv[20] $abc$4719$new_n893 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[15] $abc$4719$new_n896 $abc$4719$new_n895 prex[15] $0\xv[20:0][15] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[14] yv[20] $abc$4719$new_n893 $abc$4719$new_n891 $abc$4719$new_n890 $abc$4719$new_n895 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n858 yv[20] $abc$4719$new_n896 +010 1 +011 1 +100 1 +110 1 +.names $abc$4719$new_n892 xv[13] $abc$4719$new_n887 $abc$4719$new_n886 $abc$4719$new_n900 +0001 1 +0100 1 +0101 1 +0111 1 +.names $abc$4719$new_n896 xv[15] $abc$4719$new_n901 +10 1 +.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n902 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$4719$new_n906 xv[13] $abc$4719$new_n887 $abc$4719$new_n885 $abc$4719$new_n892 $abc$4719$new_n904 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14] $abc$4719$new_n893 xv[15] $abc$4719$new_n896 $abc$4719$new_n906 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n768 yv[20] $abc$4719$new_n907 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[17] $abc$4719$new_n912 $abc$4719$new_n909 prex[17] $0\xv[20:0][17] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n910 $abc$4719$new_n911 $abc$4719$new_n909 +010 1 +011 1 +100 1 +110 1 +.names xv[16] $abc$4719$new_n907 $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n901 $abc$4719$new_n910 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$4719$new_n904 xv[16] $abc$4719$new_n907 xv[15] $abc$4719$new_n896 $abc$4719$new_n911 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n795 $abc$4719$new_n912 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[18] $abc$4719$new_n915 $abc$4719$new_n914 prex[18] $0\xv[20:0][18] +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[17] yv[20] $abc$4719$new_n912 $abc$4719$new_n911 $abc$4719$new_n910 $abc$4719$new_n914 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 yv[20] $abc$4719$new_n811 $abc$4719$new_n915 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names pre_valid xv[19] $abc$4719$new_n920 $abc$4719$new_n917 prex[19] $0\xv[20:0][19] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[20] $abc$4719$new_n918 $abc$4719$new_n919 $abc$4719$new_n917 +001 1 +011 1 +110 1 +111 1 +.names xv[17] $abc$4719$new_n912 xv[18] $abc$4719$new_n915 $abc$4719$new_n911 $abc$4719$new_n918 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n912 xv[17] xv[18] $abc$4719$new_n915 $abc$4719$new_n910 $abc$4719$new_n919 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n822 yv[20] $abc$4719$new_n920 +010 1 +011 1 +100 1 +110 1 +.names pre_valid xv[20] $abc$4719$new_n922 prex[20] $0\xv[20:0][20] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] xv[19] $abc$4719$new_n920 $abc$4719$new_n919 $abc$4719$new_n918 $abc$4719$new_n922 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $0\preph[20:0][19] +01 1 +10 1 +.names state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[1] +01 1 +10 1 +.names i_yval[12] i_xval[0] i_xval[12] $abc$4719$new_n418 $abc$4719$new_n419 $0\prex[20:0][7] +00000 1 +00010 1 +00100 1 +00110 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$4719$new_n928 $abc$4719$new_n434 $abc$4719$new_n430 $0\prex[20:0][8] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n422 $abc$4719$new_n432 $abc$4719$new_n427 $abc$4719$new_n928 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4719$new_n933 $abc$4719$new_n445 $abc$4719$new_n453 $0\prex[20:0][10] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n448 $abc$4719$new_n451 $abc$4719$new_n455 $abc$4719$new_n933 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n935 $abc$4719$new_n445 $abc$4719$new_n464 $0\prex[20:0][11] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n458 $abc$4719$new_n462 $abc$4719$new_n466 $abc$4719$new_n935 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n937 $abc$4719$new_n445 $abc$4719$new_n473 $0\prex[20:0][12] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n470 $abc$4719$new_n474 $abc$4719$new_n472 $abc$4719$new_n937 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n939 $abc$4719$new_n445 $abc$4719$new_n483 $0\prex[20:0][13] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n478 $abc$4719$new_n481 $abc$4719$new_n485 $abc$4719$new_n939 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n941 $abc$4719$new_n445 $abc$4719$new_n494 $0\prex[20:0][14] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n489 $abc$4719$new_n492 $abc$4719$new_n495 $abc$4719$new_n941 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n445 i_yval[9] i_xval[9] $abc$4719$new_n507 $abc$4719$new_n943 $0\prex[20:0][15] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n498 $abc$4719$new_n502 $abc$4719$new_n504 $abc$4719$new_n943 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n945 $abc$4719$new_n445 $abc$4719$new_n516 $0\prex[20:0][16] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n510 $abc$4719$new_n514 $abc$4719$new_n517 $abc$4719$new_n945 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$4719$new_n947 $abc$4719$new_n445 $abc$4719$new_n528 $0\prex[20:0][17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n519 $abc$4719$new_n524 $abc$4719$new_n526 $abc$4719$new_n947 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n535 $abc$4719$new_n537 $0\prex[20:0][19] +1110 1 +.names state[2] state[1] state[0] $auto$alumacc.cc:485:replace_alu$735.Y[2] +011 1 +100 1 +101 1 +110 1 +.names state[3] state[1] state[0] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names state[4] state[1] state[0] state[3] state[2] $auto$alumacc.cc:485:replace_alu$735.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names idle o_busy +0 1 +.names state[0] $auto$alumacc.cc:485:replace_alu$735.X[0] +0 1 +.names $auto$alumacc.cc:485:replace_alu$735.Y[1] $abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] +0 1 +.names $abc$4719$new_n967 i_xval[12] $abc$4719$new_n537 i_yval[12] $abc$4719$new_n535 $0\prey[20:0][20] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11100 1 +.names i_yval[12] $abc$4719$new_n507 i_yval[9] i_xval[9] $abc$4719$new_n502 $abc$4719$new_n964 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$4719$new_n964 $abc$4719$new_n504 $abc$4719$new_n498 $0\prey[20:0][15] +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n966 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$4719$new_n966 $abc$4719$new_n533 $abc$4719$new_n534 $abc$4719$new_n967 +00000 1 +00001 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[3] state[2] $abc$4719$new_n635 $abc$4719$new_n638 $abc$4719$new_n633 $abc$4719$new_n968 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[1] $abc$4719$new_n1009 yv[20] $abc$4719$new_n648 $abc$4719$new_n646 $abc$4719$new_n971 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n649 yv[2] $abc$4719$new_n971 prey[2] $0\yv[20:0][2] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$4719$new_n657 $abc$4719$new_n654 $abc$4719$new_n650 $abc$4719$new_n973 +000 1 +.names $abc$4719$new_n1009 $abc$4719$new_n646 $abc$4719$new_n973 yv[2] yv[1] $abc$4719$new_n974 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01111 1 +10001 1 +10010 1 +10011 1 +10111 1 +11010 1 +11011 1 +.names state[1] state[0] $abc$4719$new_n642 xv[6] xv[5] $abc$4719$new_n975 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$4719$new_n666 state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n672 $abc$4719$new_n975 $abc$4719$new_n976 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[5] $abc$4719$new_n684 yv[20] $abc$4719$new_n683 $abc$4719$new_n682 $abc$4719$new_n977 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n691 $abc$4719$new_n977 prey[6] $0\yv[20:0][6] +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[9] $abc$4719$new_n714 yv[20] $abc$4719$new_n713 $abc$4719$new_n711 $abc$4719$new_n979 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n720 yv[10] $abc$4719$new_n979 prey[10] $0\yv[20:0][10] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names yv[13] $abc$4719$new_n734 yv[20] $abc$4719$new_n733 $abc$4719$new_n732 $abc$4719$new_n981 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n739 yv[14] $abc$4719$new_n981 prey[14] $0\yv[20:0][14] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names state[3] state[2] $abc$4719$new_n789 $abc$4719$new_n792 $abc$4719$new_n787 $abc$4719$new_n983 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n794 $abc$4719$new_n983 $abc$4719$new_n797 $abc$4719$new_n984 +000 1 +001 1 +010 1 +.names state[1] state[0] $abc$4719$new_n780 yv[3] yv[2] $abc$4719$new_n985 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names state[2] $abc$4719$auto$opt_dff.cc:253:combine_resets$907 $abc$4719$new_n807 $abc$4719$new_n985 $abc$4719$new_n986 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$4719$new_n986 $abc$4719$new_n810 $abc$4719$new_n802 $abc$4719$new_n987 +000 1 +.names $abc$4719$new_n987 $abc$4719$new_n984 $abc$4719$new_n815 xv[2] xv[1] $abc$4719$new_n988 +00000 1 +00001 1 +00100 1 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +.names state[1] state[0] yv[6] yv[4] $abc$4719$new_n989 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$4719$new_n989 state[3] state[0] yv[5] yv[3] $abc$4719$new_n990 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names state[4] state[3] state[2] $abc$4719$new_n825 $abc$4719$new_n990 $abc$4719$new_n991 +00001 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names state[3] $abc$4719$new_n782 $abc$4719$new_n991 $abc$4719$new_n822 $abc$4719$new_n828 $abc$4719$new_n992 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +.names state[2] state[0] state[1] yv[9] yv[8] $abc$4719$new_n993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$4719$new_n993 state[2] $abc$4719$new_n774 $abc$4719$new_n781 $abc$4719$new_n780 $abc$4719$new_n994 +00001 1 +00011 1 +00101 1 +00111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names state[4] state[3] yv[20] $abc$4719$new_n994 $abc$4719$new_n834 $abc$4719$new_n995 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names xv[5] $abc$4719$new_n843 yv[20] $abc$4719$new_n842 $abc$4719$new_n841 $abc$4719$new_n996 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n850 xv[6] $abc$4719$new_n996 prex[6] $0\xv[20:0][6] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names xv[7] $abc$4719$new_n857 yv[20] $abc$4719$new_n855 $abc$4719$new_n856 $abc$4719$new_n998 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10101 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names pre_valid $abc$4719$new_n864 xv[8] $abc$4719$new_n998 prex[8] $0\xv[20:0][8] +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names pre_valid $abc$4719$new_n907 xv[16] prex[16] $abc$4719$new_n1000 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names yv[20] $abc$4719$new_n896 xv[15] $abc$4719$new_n902 $abc$4719$new_n900 $abc$4719$new_n1001 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$4719$new_n1000 $abc$4719$new_n1001 pre_valid yv[20] $abc$4719$new_n904 $0\xv[20:0][16] +00010 1 +00011 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[3] i_xval[12] $abc$4719$new_n444 $abc$4719$new_n443 $abc$4719$new_n1003 +00000 1 +00001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n1003 i_yval[3] $abc$4719$new_n437 $abc$4719$new_n440 $0\prex[20:0][9] +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_xval[12] $abc$4719$new_n529 i_yval[11] i_xval[11] $abc$4719$new_n535 $abc$4719$new_n1005 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_xval[12] $abc$4719$new_n533 $abc$4719$new_n1005 $abc$4719$new_n534 $abc$4719$new_n1006 +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_yval[12] $abc$4719$new_n1005 i_xval[12] $abc$4719$new_n537 $abc$4719$new_n1006 $0\prex[20:0][18] +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names state[3] state[2] state[4] xv[20] $abc$4719$new_n630 $abc$4719$new_n1008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01110 1 +01111 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$4719$new_n1008 state[4] $abc$4719$new_n968 $abc$4719$new_n641 $abc$4719$new_n1009 +0000 1 +0001 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4552 Q=o_aux +.subckt dff C=i_clk D=$0\preph[20:0][19] Q=preph[19] +.subckt dff C=i_clk D=i_yval[12] Q=preph[20] +.subckt sdffrn C=i_clk D=$false Q=prex[0] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[1] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[2] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[3] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[4] RN=i_xval[12] +.subckt sdffrn C=i_clk D=$false Q=prex[5] RN=i_xval[12] +.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prex[6] +.subckt dff C=i_clk D=$0\prex[20:0][7] Q=prex[7] +.subckt dff C=i_clk D=$0\prex[20:0][8] Q=prex[8] +.subckt dff C=i_clk D=$0\prex[20:0][9] Q=prex[9] +.subckt dff C=i_clk D=$0\prex[20:0][10] Q=prex[10] +.subckt dff C=i_clk D=$0\prex[20:0][11] Q=prex[11] +.subckt dff C=i_clk D=$0\prex[20:0][12] Q=prex[12] +.subckt dff C=i_clk D=$0\prex[20:0][13] Q=prex[13] +.subckt dff C=i_clk D=$0\prex[20:0][14] Q=prex[14] +.subckt dff C=i_clk D=$0\prex[20:0][15] Q=prex[15] +.subckt dff C=i_clk D=$0\prex[20:0][16] Q=prex[16] +.subckt dff C=i_clk D=$0\prex[20:0][17] Q=prex[17] +.subckt dff C=i_clk D=$0\prex[20:0][18] Q=prex[18] +.subckt dff C=i_clk D=$0\prex[20:0][19] Q=prex[19] +.subckt dff C=i_clk D=$false Q=prex[20] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[14] Q=cangle[14] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][2][0]$a$813[16] Q=cangle[16] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[7] Q=cangle[17] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$904 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[10] Q=cangle[10] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[11] Q=cangle[11] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[12] Q=cangle[12] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][1][0]$a$807[13] Q=cangle[13] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$907 +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[2] Q=cangle[2] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[3] Q=cangle[3] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[4] Q=cangle[4] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[5] Q=cangle[5] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[6] Q=cangle[6] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[7] Q=cangle[7] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[8] Q=cangle[8] R=state[4] +.subckt sdffr C=i_clk D=$abc$4719$memory\cordic_angle$rdmux[0][0][0]$a$804[9] Q=cangle[9] R=state[4] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[0] Q=cangle[0] +.subckt dff C=i_clk D=$\cordic_angle$rdreg[0]$d[1] Q=cangle[1] +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[0] Q=ph[0] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[1] Q=ph[1] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[2] Q=ph[2] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[3] Q=ph[3] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[4] Q=ph[4] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[5] Q=ph[5] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[6] Q=ph[6] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[7] Q=ph[7] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[8] Q=ph[8] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[9] Q=ph[9] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[10] Q=ph[10] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[11] Q=ph[11] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[12] Q=ph[12] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[13] Q=ph[13] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[14] Q=ph[14] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[15] Q=ph[15] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[16] Q=ph[16] R=pre_valid +.subckt sdffr C=i_clk D=$abc$4719$procmux$562_Y[17] Q=ph[17] R=pre_valid +.subckt sdffs C=i_clk D=$abc$4719$procmux$562_Y[18] Q=ph[18] S=pre_valid +.subckt sdffs C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4558 Q=idle S=i_reset +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4550 Q=o_mag[0] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4548 Q=o_mag[1] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4546 Q=o_mag[2] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4544 Q=o_mag[3] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4542 Q=o_mag[4] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4540 Q=o_mag[5] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4538 Q=o_mag[6] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4536 Q=o_mag[7] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4534 Q=o_mag[8] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4532 Q=o_mag[9] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4530 Q=o_mag[10] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4528 Q=o_mag[11] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4556 Q=o_mag[12] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4526 Q=o_phase[0] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4524 Q=o_phase[1] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4522 Q=o_phase[2] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4520 Q=o_phase[3] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4518 Q=o_phase[4] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4516 Q=o_phase[5] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4514 Q=o_phase[6] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4512 Q=o_phase[7] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4510 Q=o_phase[8] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4508 Q=o_phase[9] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4506 Q=o_phase[10] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4504 Q=o_phase[11] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4502 Q=o_phase[12] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4500 Q=o_phase[13] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4498 Q=o_phase[14] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4496 Q=o_phase[15] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4494 Q=o_phase[16] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4492 Q=o_phase[17] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4490 Q=o_phase[18] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4488 Q=o_phase[19] +.subckt dff C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4554 Q=o_phase[20] +.subckt dff C=i_clk D=$0\xv[20:0][0] Q=xv[0] +.subckt dff C=i_clk D=$0\xv[20:0][1] Q=xv[1] +.subckt dff C=i_clk D=$0\xv[20:0][2] Q=xv[2] +.subckt dff C=i_clk D=$0\xv[20:0][3] Q=xv[3] +.subckt dff C=i_clk D=$0\xv[20:0][4] Q=xv[4] +.subckt dff C=i_clk D=$0\xv[20:0][5] Q=xv[5] +.subckt dff C=i_clk D=$0\xv[20:0][6] Q=xv[6] +.subckt dff C=i_clk D=$0\xv[20:0][7] Q=xv[7] +.subckt dff C=i_clk D=$0\xv[20:0][8] Q=xv[8] +.subckt dff C=i_clk D=$0\xv[20:0][9] Q=xv[9] +.subckt dff C=i_clk D=$0\xv[20:0][10] Q=xv[10] +.subckt dff C=i_clk D=$0\xv[20:0][11] Q=xv[11] +.subckt dff C=i_clk D=$0\xv[20:0][12] Q=xv[12] +.subckt dff C=i_clk D=$0\xv[20:0][13] Q=xv[13] +.subckt dff C=i_clk D=$0\xv[20:0][14] Q=xv[14] +.subckt dff C=i_clk D=$0\xv[20:0][15] Q=xv[15] +.subckt dff C=i_clk D=$0\xv[20:0][16] Q=xv[16] +.subckt dff C=i_clk D=$0\xv[20:0][17] Q=xv[17] +.subckt dff C=i_clk D=$0\xv[20:0][18] Q=xv[18] +.subckt dff C=i_clk D=$0\xv[20:0][19] Q=xv[19] +.subckt dff C=i_clk D=$0\xv[20:0][20] Q=xv[20] +.subckt dff C=i_clk D=$0\yv[20:0][0] Q=yv[0] +.subckt dff C=i_clk D=$0\yv[20:0][1] Q=yv[1] +.subckt dff C=i_clk D=$0\yv[20:0][2] Q=yv[2] +.subckt dff C=i_clk D=$0\yv[20:0][3] Q=yv[3] +.subckt dff C=i_clk D=$0\yv[20:0][4] Q=yv[4] +.subckt dff C=i_clk D=$0\yv[20:0][5] Q=yv[5] +.subckt dff C=i_clk D=$0\yv[20:0][6] Q=yv[6] +.subckt dff C=i_clk D=$0\yv[20:0][7] Q=yv[7] +.subckt dff C=i_clk D=$0\yv[20:0][8] Q=yv[8] +.subckt dff C=i_clk D=$0\yv[20:0][9] Q=yv[9] +.subckt dff C=i_clk D=$0\yv[20:0][10] Q=yv[10] +.subckt dff C=i_clk D=$0\yv[20:0][11] Q=yv[11] +.subckt dff C=i_clk D=$0\yv[20:0][12] Q=yv[12] +.subckt dff C=i_clk D=$0\yv[20:0][13] Q=yv[13] +.subckt dff C=i_clk D=$0\yv[20:0][14] Q=yv[14] +.subckt dff C=i_clk D=$0\yv[20:0][15] Q=yv[15] +.subckt dff C=i_clk D=$0\yv[20:0][16] Q=yv[16] +.subckt dff C=i_clk D=$0\yv[20:0][17] Q=yv[17] +.subckt dff C=i_clk D=$0\yv[20:0][18] Q=yv[18] +.subckt dff C=i_clk D=$0\yv[20:0][19] Q=yv[19] +.subckt dff C=i_clk D=$0\yv[20:0][20] Q=yv[20] +.subckt sdffr C=i_clk D=last_state Q=o_done R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=state[0] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[1] Q=state[1] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[2] Q=state[2] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[3] Q=state[3] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.Y[4] Q=state[4] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$656 +.subckt sdffr C=i_clk D=$abc$4719$logic_and$./benchmark/seqpolar.v:114$35_Y Q=pre_valid R=i_reset +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$735.X[0] Q=cangle[15] R=$abc$4719$auto$opt_dff.cc:253:combine_resets$901 +.subckt dff C=i_clk D=$false Q=prey[0] +.subckt dff C=i_clk D=$false Q=prey[1] +.subckt dff C=i_clk D=$false Q=prey[2] +.subckt dff C=i_clk D=$false Q=prey[3] +.subckt dff C=i_clk D=$false Q=prey[4] +.subckt dff C=i_clk D=$false Q=prey[5] +.subckt dff C=i_clk D=$0\prex[20:0][6] Q=prey[6] +.subckt dff C=i_clk D=$0\prey[20:0][7] Q=prey[7] +.subckt dff C=i_clk D=$0\prey[20:0][8] Q=prey[8] +.subckt dff C=i_clk D=$0\prey[20:0][9] Q=prey[9] +.subckt dff C=i_clk D=$0\prey[20:0][10] Q=prey[10] +.subckt dff C=i_clk D=$0\prey[20:0][11] Q=prey[11] +.subckt dff C=i_clk D=$0\prey[20:0][12] Q=prey[12] +.subckt dff C=i_clk D=$0\prey[20:0][13] Q=prey[13] +.subckt dff C=i_clk D=$0\prey[20:0][14] Q=prey[14] +.subckt dff C=i_clk D=$0\prey[20:0][15] Q=prey[15] +.subckt dff C=i_clk D=$0\prey[20:0][16] Q=prey[16] +.subckt dff C=i_clk D=$0\prey[20:0][17] Q=prey[17] +.subckt dff C=i_clk D=$0\prey[20:0][18] Q=prey[18] +.subckt dff C=i_clk D=$0\prey[20:0][19] Q=prey[19] +.subckt dff C=i_clk D=$0\prey[20:0][20] Q=prey[20] +.subckt dff C=i_clk D=$0\ph[20:0][19] Q=ph[19] +.subckt dff C=i_clk D=$0\ph[20:0][20] Q=ph[20] +.subckt sdffr C=i_clk D=$abc$4719$auto$rtlil.cc:2693:MuxGate$4560 Q=aux R=i_reset +.names $false $0\preph[20:0][0] +1 1 +.names $false $0\preph[20:0][1] +1 1 +.names $false $0\preph[20:0][2] +1 1 +.names $false $0\preph[20:0][3] +1 1 +.names $false $0\preph[20:0][4] +1 1 +.names $false $0\preph[20:0][5] +1 1 +.names $false $0\preph[20:0][6] +1 1 +.names $false $0\preph[20:0][7] +1 1 +.names $false $0\preph[20:0][8] +1 1 +.names $false $0\preph[20:0][9] +1 1 +.names $false $0\preph[20:0][10] +1 1 +.names $false $0\preph[20:0][11] +1 1 +.names $false $0\preph[20:0][12] +1 1 +.names $false $0\preph[20:0][13] +1 1 +.names $false $0\preph[20:0][14] +1 1 +.names $false $0\preph[20:0][15] +1 1 +.names $false $0\preph[20:0][16] +1 1 +.names $false $0\preph[20:0][17] +1 1 +.names $true $0\preph[20:0][18] +1 1 +.names i_yval[12] $0\preph[20:0][20] +1 1 +.names $false $0\prex[20:0][0] +1 1 +.names $false $0\prex[20:0][1] +1 1 +.names $false $0\prex[20:0][2] +1 1 +.names $false $0\prex[20:0][3] +1 1 +.names $false $0\prex[20:0][4] +1 1 +.names $false $0\prex[20:0][5] +1 1 +.names $false $0\prex[20:0][20] +1 1 +.names $false $0\prey[20:0][0] +1 1 +.names $false $0\prey[20:0][1] +1 1 +.names $false $0\prey[20:0][2] +1 1 +.names $false $0\prey[20:0][3] +1 1 +.names $false $0\prey[20:0][4] +1 1 +.names $false $0\prey[20:0][5] +1 1 +.names $0\prex[20:0][6] $0\prey[20:0][6] +1 1 +.names state[1] $auto$alumacc.cc:485:replace_alu$735.X[1] +1 1 +.names state[2] $auto$alumacc.cc:485:replace_alu$735.X[2] +1 1 +.names state[3] $auto$alumacc.cc:485:replace_alu$735.X[3] +1 1 +.names state[4] $auto$alumacc.cc:485:replace_alu$735.X[4] +1 1 +.names $auto$alumacc.cc:485:replace_alu$735.X[0] $auto$alumacc.cc:485:replace_alu$735.Y[0] +1 1 +.names $false cangle[18] +1 1 +.names $false cangle[19] +1 1 +.names $false cangle[20] +1 1 +.names $false preph[0] +1 1 +.names $false preph[1] +1 1 +.names $false preph[2] +1 1 +.names $false preph[3] +1 1 +.names $false preph[4] +1 1 +.names $false preph[5] +1 1 +.names $false preph[6] +1 1 +.names $false preph[7] +1 1 +.names $false preph[8] +1 1 +.names $false preph[9] +1 1 +.names $false preph[10] +1 1 +.names $false preph[11] +1 1 +.names $false preph[12] +1 1 +.names $false preph[13] +1 1 +.names $false preph[14] +1 1 +.names $false preph[15] +1 1 +.names $false preph[16] +1 1 +.names $false preph[17] +1 1 +.names $true preph[18] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif new file mode 100644 index 00000000000..4f7f6ef8200 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/smplfir.blif @@ -0,0 +1,525 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model smplfir +.inputs i_clk i_ce i_val[0] i_val[1] i_val[2] i_val[3] i_val[4] i_val[5] i_val[6] i_val[7] i_val[8] i_val[9] i_val[10] i_val[11] i_val[12] i_val[13] i_val[14] +.outputs o_val[0] o_val[1] o_val[2] o_val[3] o_val[4] o_val[5] o_val[6] o_val[7] o_val[8] o_val[9] o_val[10] o_val[11] o_val[12] o_val[13] o_val[14] o_val[15] +.names $false +.names $true +1 +.names $undef +.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[14] $abc$921$auto$rtlil.cc:2693:MuxGate$752 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[12] delayed[12] i_val[13] delayed[13] $abc$921$new_n82 $abc$921$new_n81 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[10] delayed[10] i_val[11] delayed[11] $abc$921$new_n83 $abc$921$new_n82 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[8] delayed[8] i_val[9] delayed[9] $abc$921$new_n84 $abc$921$new_n83 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[6] delayed[6] i_val[7] delayed[7] $abc$921$new_n85 $abc$921$new_n84 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[4] delayed[4] i_val[5] delayed[5] $abc$921$new_n86 $abc$921$new_n85 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[2] delayed[2] i_val[3] delayed[3] $abc$921$new_n87 $abc$921$new_n86 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_val[0] delayed[0] i_val[1] delayed[1] $abc$921$new_n87 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce i_val[13] delayed[13] $abc$921$new_n89 o_val[13] $abc$921$auto$rtlil.cc:2693:MuxGate$754 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[12] delayed[12] $abc$921$new_n82 $abc$921$new_n89 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[12] delayed[12] $abc$921$new_n82 o_val[12] $abc$921$auto$rtlil.cc:2693:MuxGate$756 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[11] delayed[11] $abc$921$new_n92 o_val[11] $abc$921$auto$rtlil.cc:2693:MuxGate$758 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[10] delayed[10] $abc$921$new_n83 $abc$921$new_n92 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[10] delayed[10] $abc$921$new_n83 o_val[10] $abc$921$auto$rtlil.cc:2693:MuxGate$760 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[9] delayed[9] $abc$921$new_n95 o_val[9] $abc$921$auto$rtlil.cc:2693:MuxGate$762 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[8] delayed[8] $abc$921$new_n84 $abc$921$new_n95 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[8] delayed[8] $abc$921$new_n84 o_val[8] $abc$921$auto$rtlil.cc:2693:MuxGate$764 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$921$new_n98 o_val[7] $abc$921$auto$rtlil.cc:2693:MuxGate$766 +001 1 +011 1 +110 1 +111 1 +.names i_val[7] delayed[7] i_val[6] delayed[6] $abc$921$new_n85 $abc$921$new_n98 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_ce i_val[6] delayed[6] $abc$921$new_n85 o_val[6] $abc$921$auto$rtlil.cc:2693:MuxGate$768 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[5] delayed[5] $abc$921$new_n101 o_val[5] $abc$921$auto$rtlil.cc:2693:MuxGate$770 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[4] delayed[4] $abc$921$new_n86 $abc$921$new_n101 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[4] delayed[4] $abc$921$new_n86 o_val[4] $abc$921$auto$rtlil.cc:2693:MuxGate$772 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[3] delayed[3] $abc$921$new_n104 o_val[3] $abc$921$auto$rtlil.cc:2693:MuxGate$774 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_val[2] delayed[2] $abc$921$new_n87 $abc$921$new_n104 +000 1 +001 1 +011 1 +101 1 +.names i_ce i_val[2] delayed[2] $abc$921$new_n87 o_val[2] $abc$921$auto$rtlil.cc:2693:MuxGate$776 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce i_val[1] delayed[1] $abc$921$new_n107 o_val[1] $abc$921$auto$rtlil.cc:2693:MuxGate$778 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_val[0] delayed[0] $abc$921$new_n107 +11 1 +.names i_ce i_val[0] delayed[0] o_val[0] $abc$921$auto$rtlil.cc:2693:MuxGate$780 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce i_val[13] delayed[13] $abc$921$auto$rtlil.cc:2693:MuxGate$782 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[12] delayed[12] $abc$921$auto$rtlil.cc:2693:MuxGate$784 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[11] delayed[11] $abc$921$auto$rtlil.cc:2693:MuxGate$786 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[10] delayed[10] $abc$921$auto$rtlil.cc:2693:MuxGate$788 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[9] delayed[9] $abc$921$auto$rtlil.cc:2693:MuxGate$790 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[8] delayed[8] $abc$921$auto$rtlil.cc:2693:MuxGate$792 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[7] delayed[7] $abc$921$auto$rtlil.cc:2693:MuxGate$794 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[6] delayed[6] $abc$921$auto$rtlil.cc:2693:MuxGate$796 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[5] delayed[5] $abc$921$auto$rtlil.cc:2693:MuxGate$798 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[4] delayed[4] $abc$921$auto$rtlil.cc:2693:MuxGate$800 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[3] delayed[3] $abc$921$auto$rtlil.cc:2693:MuxGate$802 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[2] delayed[2] $abc$921$auto$rtlil.cc:2693:MuxGate$804 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[1] delayed[1] $abc$921$auto$rtlil.cc:2693:MuxGate$806 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[0] delayed[0] $abc$921$auto$rtlil.cc:2693:MuxGate$808 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[14] delayed[14] $abc$921$auto$rtlil.cc:2693:MuxGate$810 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_val[14] delayed[14] $abc$921$new_n81 o_val[15] $abc$921$auto$rtlil.cc:2693:MuxGate$812 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$808 Q=delayed[0] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$806 Q=delayed[1] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$804 Q=delayed[2] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$802 Q=delayed[3] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$800 Q=delayed[4] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$798 Q=delayed[5] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$796 Q=delayed[6] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$794 Q=delayed[7] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$792 Q=delayed[8] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$790 Q=delayed[9] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$788 Q=delayed[10] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$786 Q=delayed[11] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$784 Q=delayed[12] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$782 Q=delayed[13] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$810 Q=delayed[14] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$780 Q=o_val[0] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$778 Q=o_val[1] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$776 Q=o_val[2] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$774 Q=o_val[3] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$772 Q=o_val[4] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$770 Q=o_val[5] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$768 Q=o_val[6] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$766 Q=o_val[7] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$764 Q=o_val[8] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$762 Q=o_val[9] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$760 Q=o_val[10] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$758 Q=o_val[11] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$756 Q=o_val[12] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$754 Q=o_val[13] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$752 Q=o_val[14] +.subckt dff C=i_clk D=$abc$921$auto$rtlil.cc:2693:MuxGate$812 Q=o_val[15] +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif new file mode 100644 index 00000000000..eadfe9f56b9 --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/topolar.blif @@ -0,0 +1,36396 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model topolar +.inputs i_clk i_reset i_ce i_xval[0] i_xval[1] i_xval[2] i_xval[3] i_xval[4] i_xval[5] i_xval[6] i_xval[7] i_xval[8] i_xval[9] i_xval[10] i_xval[11] i_xval[12] i_yval[0] i_yval[1] i_yval[2] i_yval[3] i_yval[4] i_yval[5] i_yval[6] i_yval[7] i_yval[8] i_yval[9] i_yval[10] i_yval[11] i_yval[12] i_aux +.outputs o_mag[0] o_mag[1] o_mag[2] o_mag[3] o_mag[4] o_mag[5] o_mag[6] o_mag[7] o_mag[8] o_mag[9] o_mag[10] o_mag[11] o_mag[12] o_phase[0] o_phase[1] o_phase[2] o_phase[3] o_phase[4] o_phase[5] o_phase[6] o_phase[7] o_phase[8] o_phase[9] o_phase[10] o_phase[11] o_phase[12] o_phase[13] o_phase[14] o_phase[15] o_phase[16] o_phase[17] o_phase[18] o_phase[19] o_phase[20] o_aux +.names $false +.names $true +1 +.names $undef +.names i_ce ax[17] ax[16] $abc$30358$auto$rtlil.cc:2693:MuxGate$25855 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[16] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25857 +010 1 +011 1 +101 1 +111 1 +.names i_ce ax[14] ax[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25859 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[13] ax[14] $abc$30358$auto$rtlil.cc:2693:MuxGate$25861 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[12] ax[13] $abc$30358$auto$rtlil.cc:2693:MuxGate$25863 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[11] ax[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$25865 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[10] ax[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$25867 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[9] ax[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$25869 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[8] ax[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25871 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[7] ax[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25873 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[6] ax[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25875 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[5] ax[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25877 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[4] ax[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$25879 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[3] ax[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$25881 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[2] ax[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$25883 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[1] ax[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$25885 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[0] ax[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$25887 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_aux ax[0] $abc$30358$auto$rtlil.cc:2693:MuxGate$25889 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n6162 yv[0][19] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25891 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2425 +000 1 +001 1 +011 1 +101 1 +.names i_yval[8] $abc$30358$new_n2440 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2427 $abc$30358$new_n2426 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[6] $abc$30358$new_n2437 i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2428 $abc$30358$new_n2427 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2429 $abc$30358$new_n2428 +0001 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2430 $abc$30358$new_n2429 +000 1 +001 1 +011 1 +101 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2431 $abc$30358$new_n2430 +000 1 +001 1 +011 1 +101 1 +.names i_xval[2] i_xval[0] i_xval[1] i_yval[2] $abc$30358$new_n2432 $abc$30358$new_n2431 +00000 1 +00001 1 +00011 1 +00101 1 +01001 1 +01101 1 +10001 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_xval[1] i_xval[0] i_yval[0] i_yval[1] $abc$30358$new_n2432 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names i_xval[3] i_xval[0] i_xval[2] i_xval[1] $abc$30358$new_n2433 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names i_xval[4] i_xval[0] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2434 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names i_xval[0] i_xval[4] i_xval[3] i_xval[2] i_xval[1] $abc$30358$new_n2435 +00000 1 +.names i_xval[7] $abc$30358$new_n2435 i_xval[6] i_xval[5] $abc$30358$new_n2436 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_xval[6] $abc$30358$new_n2435 i_xval[5] $abc$30358$new_n2437 +000 1 +001 1 +011 1 +110 1 +.names i_xval[9] $abc$30358$new_n2439 $abc$30358$new_n2438 +00 1 +11 1 +.names $abc$30358$new_n2435 i_xval[8] i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2439 +10000 1 +.names i_xval[8] $abc$30358$new_n2435 i_xval[7] i_xval[6] i_xval[5] $abc$30358$new_n2440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names i_xval[10] $abc$30358$new_n2439 i_xval[9] $abc$30358$new_n2441 +000 1 +001 1 +011 1 +110 1 +.names $abc$30358$new_n2439 i_xval[10] i_xval[9] $abc$30358$new_n2442 +100 1 +.names $abc$30358$new_n2453 i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2444 +10000 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names i_yval[9] $abc$30358$new_n2438 i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2446 $abc$30358$new_n2445 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names i_yval[7] i_yval[8] $abc$30358$new_n2436 $abc$30358$new_n2440 $abc$30358$new_n2447 $abc$30358$new_n2446 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2448 $abc$30358$new_n2447 +001 1 +100 1 +101 1 +111 1 +.names i_xval[5] $abc$30358$new_n2435 i_yval[5] $abc$30358$new_n2449 $abc$30358$new_n2448 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2450 $abc$30358$new_n2449 +001 1 +100 1 +101 1 +111 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2451 $abc$30358$new_n2450 +001 1 +100 1 +101 1 +111 1 +.names i_xval[2] i_yval[2] i_xval[0] i_xval[1] $abc$30358$new_n2452 $abc$30358$new_n2451 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[0] i_yval[1] i_xval[1] i_yval[0] $abc$30358$new_n2452 +0001 1 +0100 1 +0101 1 +0111 1 +1110 1 +1111 1 +.names $abc$30358$new_n2455 $abc$30358$new_n2454 $abc$30358$new_n2453 +10 1 +.names $abc$30358$new_n2442 i_xval[11] $abc$30358$new_n2454 +10 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2455 +10 1 +.names i_xval[11] $abc$30358$new_n2442 $abc$30358$new_n2456 +00 1 +11 1 +.names $abc$30358$new_n2441 i_yval[10] $abc$30358$new_n2457 +10 1 +.names i_yval[9] i_yval[10] i_xval[9] i_xval[10] $abc$30358$new_n2461 $abc$30358$new_n2460 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[7] i_yval[8] i_xval[7] i_xval[8] $abc$30358$new_n2462 $abc$30358$new_n2461 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[5] i_yval[6] i_xval[5] i_xval[6] $abc$30358$new_n2463 $abc$30358$new_n2462 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[3] i_yval[4] i_xval[3] i_xval[4] $abc$30358$new_n2464 $abc$30358$new_n2463 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[1] i_yval[2] i_xval[1] i_xval[2] $abc$30358$new_n2465 $abc$30358$new_n2464 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_yval[0] i_xval[0] $abc$30358$new_n2465 +10 1 +.names i_yval[9] i_xval[9] i_yval[10] i_xval[10] $abc$30358$new_n2468 $abc$30358$new_n2467 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[7] i_xval[7] i_yval[8] i_xval[8] $abc$30358$new_n2469 $abc$30358$new_n2468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[5] i_xval[5] i_yval[6] i_xval[6] $abc$30358$new_n2470 $abc$30358$new_n2469 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[3] i_xval[3] i_yval[4] i_xval[4] $abc$30358$new_n2471 $abc$30358$new_n2470 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_yval[1] i_xval[1] i_yval[2] i_xval[2] $abc$30358$new_n2472 $abc$30358$new_n2471 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names i_yval[0] i_xval[0] $abc$30358$new_n2472 +11 1 +.names i_ce yv[0][18] $abc$30358$new_n2475 $abc$30358$new_n6162 $abc$30358$auto$rtlil.cc:2693:MuxGate$25893 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_xval[12] $abc$30358$new_n2454 $abc$30358$new_n2476 i_yval[12] $abc$30358$new_n2475 +1010 1 +1100 1 +.names i_yval[11] $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2456 $abc$30358$new_n2476 +0000 1 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2478 yv[0][17] $abc$30358$new_n2483 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25895 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2479 $abc$30358$new_n2481 $abc$30358$new_n2482 $abc$30358$new_n2478 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$30358$new_n2480 $abc$30358$new_n2425 $abc$30358$new_n2479 +01 1 +10 1 +.names i_yval[11] $abc$30358$new_n2456 $abc$30358$new_n2480 +01 1 +10 1 +.names i_yval[11] i_xval[11] $abc$30358$new_n2467 $abc$30358$new_n2481 +000 1 +011 1 +101 1 +110 1 +.names i_yval[11] i_xval[11] $abc$30358$new_n2460 $abc$30358$new_n2482 +000 1 +011 1 +101 1 +110 1 +.names $abc$30358$new_n2480 $abc$30358$new_n2457 $abc$30358$new_n2445 $abc$30358$new_n2483 +000 1 +101 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n2485 yv[0][16] $abc$30358$new_n2489 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25897 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2486 $abc$30358$new_n2487 $abc$30358$new_n2488 $abc$30358$new_n2485 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[10] $abc$30358$new_n2441 $abc$30358$new_n2426 $abc$30358$new_n2486 +000 1 +011 1 +101 1 +110 1 +.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2487 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[10] i_xval[10] i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2488 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[10] $abc$30358$new_n2441 i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2489 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2492 yv[0][15] $abc$30358$new_n2491 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[9] $abc$30358$new_n2438 $abc$30358$new_n2446 $abc$30358$new_n2491 +001 1 +010 1 +100 1 +111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2493 $abc$30358$new_n2494 $abc$30358$new_n2495 $abc$30358$new_n2492 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_yval[9] $abc$30358$new_n2438 i_yval[8] $abc$30358$new_n2440 $abc$30358$new_n2427 $abc$30358$new_n2493 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[9] i_xval[9] $abc$30358$new_n2468 $abc$30358$new_n2494 +001 1 +010 1 +100 1 +111 1 +.names i_yval[9] i_xval[9] $abc$30358$new_n2461 $abc$30358$new_n2495 +000 1 +011 1 +101 1 +110 1 +.names i_ce $abc$30358$new_n2497 yv[0][14] $abc$30358$new_n2501 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25901 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2498 $abc$30358$new_n2499 $abc$30358$new_n2500 $abc$30358$new_n2497 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[8] $abc$30358$new_n2440 $abc$30358$new_n2427 $abc$30358$new_n2498 +000 1 +011 1 +101 1 +110 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$30358$new_n2469 $abc$30358$new_n2499 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[8] i_xval[8] i_yval[7] i_xval[7] $abc$30358$new_n2462 $abc$30358$new_n2500 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[8] $abc$30358$new_n2440 i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2447 $abc$30358$new_n2501 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2504 yv[0][13] $abc$30358$new_n2503 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25903 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[7] $abc$30358$new_n2436 $abc$30358$new_n2447 $abc$30358$new_n2503 +001 1 +010 1 +100 1 +111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2505 $abc$30358$new_n2506 $abc$30358$new_n2507 $abc$30358$new_n2504 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_yval[7] $abc$30358$new_n2436 i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2428 $abc$30358$new_n2505 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[7] i_xval[7] $abc$30358$new_n2469 $abc$30358$new_n2506 +000 1 +011 1 +101 1 +110 1 +.names i_yval[7] i_xval[7] $abc$30358$new_n2462 $abc$30358$new_n2507 +000 1 +011 1 +101 1 +110 1 +.names i_ce $abc$30358$new_n2509 yv[0][12] $abc$30358$new_n2513 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25905 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2510 $abc$30358$new_n2511 $abc$30358$new_n2512 $abc$30358$new_n2509 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2428 $abc$30358$new_n2510 +000 1 +011 1 +101 1 +110 1 +.names i_yval[6] i_xval[6] i_yval[5] i_xval[5] $abc$30358$new_n2470 $abc$30358$new_n2511 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[6] i_xval[6] i_yval[5] i_xval[5] $abc$30358$new_n2463 $abc$30358$new_n2512 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[6] $abc$30358$new_n2437 $abc$30358$new_n2448 $abc$30358$new_n2513 +001 1 +010 1 +100 1 +111 1 +.names i_ce $abc$30358$new_n2515 yv[0][11] $abc$30358$new_n2519 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25907 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2516 $abc$30358$new_n2517 $abc$30358$new_n2518 $abc$30358$new_n2515 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2435 $abc$30358$new_n2429 $abc$30358$new_n2516 +0001 1 +0010 1 +0100 1 +0111 1 +1000 1 +1011 1 +1101 1 +1110 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2435 $abc$30358$new_n2449 $abc$30358$new_n2517 +0000 1 +0011 1 +0101 1 +0110 1 +1001 1 +1010 1 +1100 1 +1111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2470 $abc$30358$new_n2518 +001 1 +010 1 +100 1 +111 1 +.names i_yval[5] i_xval[5] $abc$30358$new_n2463 $abc$30358$new_n2519 +001 1 +010 1 +100 1 +111 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2520 +11 1 +.names i_ce $abc$30358$new_n2522 yv[0][10] $abc$30358$new_n2526 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2523 $abc$30358$new_n2524 $abc$30358$new_n2525 $abc$30358$new_n2522 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2430 $abc$30358$new_n2523 +000 1 +011 1 +101 1 +110 1 +.names i_yval[4] i_xval[4] i_yval[3] i_xval[3] $abc$30358$new_n2471 $abc$30358$new_n2524 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names i_yval[4] i_xval[4] i_yval[3] i_xval[3] $abc$30358$new_n2464 $abc$30358$new_n2525 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names i_yval[4] $abc$30358$new_n2434 $abc$30358$new_n2450 $abc$30358$new_n2526 +001 1 +010 1 +100 1 +111 1 +.names $abc$30358$new_n2532 $abc$30358$new_n2471 $abc$30358$new_n2531 +00 1 +11 1 +.names i_yval[3] i_xval[3] $abc$30358$new_n2532 +00 1 +11 1 +.names $abc$30358$new_n2534 $abc$30358$new_n2431 $abc$30358$new_n2533 +01 1 +10 1 +.names i_yval[3] $abc$30358$new_n2433 $abc$30358$new_n2534 +00 1 +11 1 +.names $abc$30358$new_n2451 $abc$30358$new_n2534 $abc$30358$new_n2535 +00 1 +11 1 +.names $abc$30358$new_n2537 i_ce yv[0][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25913 +001 1 +010 1 +011 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2538 $abc$30358$new_n2542 $abc$30358$new_n2543 $abc$30358$new_n2537 +00100 1 +00110 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_yval[12] i_xval[12] i_ce $abc$30358$new_n2539 $abc$30358$new_n2541 $abc$30358$new_n2538 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2452 $abc$30358$new_n2540 $abc$30358$new_n2539 +00 1 +11 1 +.names i_yval[2] i_xval[2] i_xval[0] i_xval[1] $abc$30358$new_n2540 +0000 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names i_yval[2] i_xval[2] i_yval[1] i_xval[1] $abc$30358$new_n2472 $abc$30358$new_n2541 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_yval[2] i_xval[2] i_yval[1] i_xval[1] $abc$30358$new_n2465 $abc$30358$new_n2542 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n2540 $abc$30358$new_n2432 $abc$30358$new_n2543 +01 1 +10 1 +.names i_ce yv[0][7] $abc$30358$new_n2548 $abc$30358$new_n2546 $abc$30358$new_n2545 $abc$30358$auto$rtlil.cc:2693:MuxGate$25915 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2455 i_yval[1] i_xval[1] i_yval[0] i_xval[0] $abc$30358$new_n2545 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2520 $abc$30358$new_n2465 $abc$30358$new_n2547 $abc$30358$new_n2546 +100 1 +111 1 +.names i_yval[1] i_xval[1] $abc$30358$new_n2547 +00 1 +11 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2472 $abc$30358$new_n2547 $abc$30358$new_n2549 $abc$30358$new_n2548 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names i_yval[1] i_xval[1] i_xval[0] i_yval[0] $abc$30358$new_n2549 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names i_ce i_yval[0] i_xval[0] yv[0][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25917 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[0][5] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25919 +10 1 +.names yv[0][4] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25921 +10 1 +.names yv[0][3] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25923 +10 1 +.names yv[0][2] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25925 +10 1 +.names yv[0][1] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25927 +10 1 +.names yv[0][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25929 +10 1 +.names $abc$30358$new_n2558 xv[0][19] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25931 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_xval[12] i_yval[12] i_ce $abc$30358$new_n2454 $abc$30358$new_n2476 $abc$30358$new_n2558 +11110 1 +.names i_xval[11] i_yval[11] $abc$30358$new_n2442 $abc$30358$new_n2425 $abc$30358$new_n2455 $abc$30358$new_n2563 +00001 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10101 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2565 xv[0][17] $abc$30358$new_n2455 $abc$30358$new_n2479 $abc$30358$auto$rtlil.cc:2693:MuxGate$25935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2483 $abc$30358$new_n2481 $abc$30358$new_n2482 $abc$30358$new_n2565 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2568 xv[0][16] $abc$30358$new_n2489 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25937 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2486 $abc$30358$new_n2487 $abc$30358$new_n2488 $abc$30358$new_n2568 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2570 xv[0][15] $abc$30358$new_n2491 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25939 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2493 $abc$30358$new_n2494 $abc$30358$new_n2495 $abc$30358$new_n2570 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2572 xv[0][14] $abc$30358$new_n2498 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2501 $abc$30358$new_n2499 $abc$30358$new_n2500 $abc$30358$new_n2572 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2574 xv[0][13] $abc$30358$new_n2503 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25943 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2505 $abc$30358$new_n2506 $abc$30358$new_n2507 $abc$30358$new_n2574 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2576 xv[0][12] $abc$30358$new_n2513 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25945 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2510 $abc$30358$new_n2511 $abc$30358$new_n2512 $abc$30358$new_n2576 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2578 xv[0][11] $abc$30358$new_n2517 $abc$30358$new_n2520 $abc$30358$auto$rtlil.cc:2693:MuxGate$25947 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2516 $abc$30358$new_n2519 $abc$30358$new_n2518 $abc$30358$new_n2578 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2580 xv[0][10] $abc$30358$new_n2523 $abc$30358$new_n2455 $abc$30358$auto$rtlil.cc:2693:MuxGate$25949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2526 $abc$30358$new_n2524 $abc$30358$new_n2525 $abc$30358$new_n2580 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$30358$new_n2583 $abc$30358$new_n2582 xv[0][9] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25951 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names i_ce i_xval[12] i_yval[12] $abc$30358$new_n2531 $abc$30358$new_n2533 $abc$30358$new_n2582 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[12] i_xval[12] $abc$30358$new_n2532 $abc$30358$new_n2464 $abc$30358$new_n2535 $abc$30358$new_n2583 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$30358$new_n2585 i_ce xv[0][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25953 +001 1 +010 1 +011 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2586 $abc$30358$new_n2542 $abc$30358$new_n2543 $abc$30358$new_n2585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] i_ce $abc$30358$new_n2539 $abc$30358$new_n2541 $abc$30358$new_n2586 +00100 1 +00110 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce i_yval[0] i_xval[0] xv[0][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25957 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[0][5] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25959 +10 1 +.names xv[0][4] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25961 +10 1 +.names xv[0][3] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25963 +10 1 +.names xv[0][2] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25965 +10 1 +.names xv[0][1] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25967 +10 1 +.names xv[0][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$25969 +10 1 +.names i_ce ph[18][19] o_phase[19] $abc$30358$auto$rtlil.cc:2693:MuxGate$25971 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][18] o_phase[18] $abc$30358$auto$rtlil.cc:2693:MuxGate$25973 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][17] o_phase[17] $abc$30358$auto$rtlil.cc:2693:MuxGate$25975 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][16] o_phase[16] $abc$30358$auto$rtlil.cc:2693:MuxGate$25977 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][15] o_phase[15] $abc$30358$auto$rtlil.cc:2693:MuxGate$25979 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][14] o_phase[14] $abc$30358$auto$rtlil.cc:2693:MuxGate$25981 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][13] o_phase[13] $abc$30358$auto$rtlil.cc:2693:MuxGate$25983 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][12] o_phase[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$25985 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][11] o_phase[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$25987 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][10] o_phase[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$25989 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][9] o_phase[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25991 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][8] o_phase[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$25993 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][7] o_phase[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25995 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][6] o_phase[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$25997 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][5] o_phase[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$25999 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][4] o_phase[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26001 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][3] o_phase[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26003 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][2] o_phase[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26005 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][1] o_phase[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26007 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[18][0] o_phase[0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26009 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[18][19] xv[18][18] $abc$30358$new_n2619 o_mag[11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[18][16] xv[18][17] $abc$30358$new_n2620 $abc$30358$new_n2619 +111 1 +.names xv[18][14] xv[18][15] $abc$30358$new_n2621 $abc$30358$new_n2620 +111 1 +.names xv[18][12] xv[18][13] $abc$30358$new_n2622 $abc$30358$new_n2621 +111 1 +.names xv[18][7] xv[18][8] xv[18][9] xv[18][10] xv[18][11] $abc$30358$new_n2622 +11111 1 +.names i_ce xv[18][18] $abc$30358$new_n2619 o_mag[10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26013 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][17] xv[18][16] $abc$30358$new_n2620 o_mag[9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26015 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][16] $abc$30358$new_n2620 o_mag[8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26017 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][15] xv[18][14] $abc$30358$new_n2621 o_mag[7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][14] $abc$30358$new_n2621 o_mag[6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26021 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[18][13] xv[18][12] $abc$30358$new_n2622 o_mag[5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][12] $abc$30358$new_n2622 o_mag[4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26025 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2631 o_mag[3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26027 +001 1 +011 1 +110 1 +111 1 +.names xv[18][11] xv[18][7] xv[18][8] xv[18][9] xv[18][10] $abc$30358$new_n2631 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n2633 o_mag[2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26029 +001 1 +011 1 +110 1 +111 1 +.names xv[18][10] xv[18][7] xv[18][8] xv[18][9] $abc$30358$new_n2633 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[18][9] xv[18][7] xv[18][8] o_mag[1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26031 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[18][7] xv[18][8] o_mag[0] $abc$30358$new_n2636 $abc$30358$auto$rtlil.cc:2693:MuxGate$26033 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$30358$new_n2637 xv[18][4] xv[18][5] xv[18][6] $abc$30358$new_n2636 +1000 1 +.names xv[18][0] xv[18][1] xv[18][2] xv[18][3] $abc$30358$new_n2637 +0000 1 +.names i_ce xv[0][20] yv[0][19] $abc$30358$new_n2639 yv[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26035 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][19] yv[0][18] $abc$30358$new_n2640 $abc$30358$new_n2649 $abc$30358$new_n2639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][17] yv[0][16] xv[0][18] yv[0][17] $abc$30358$new_n2641 $abc$30358$new_n2640 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[0][15] yv[0][14] xv[0][16] yv[0][15] $abc$30358$new_n2642 $abc$30358$new_n2641 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][13] yv[0][12] xv[0][14] yv[0][13] $abc$30358$new_n2643 $abc$30358$new_n2642 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][11] yv[0][10] xv[0][12] yv[0][11] $abc$30358$new_n2644 $abc$30358$new_n2643 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][9] yv[0][8] xv[0][10] yv[0][9] $abc$30358$new_n2645 $abc$30358$new_n2644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][7] yv[0][6] xv[0][8] yv[0][7] $abc$30358$new_n2646 $abc$30358$new_n2645 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][5] yv[0][4] xv[0][6] yv[0][5] $abc$30358$new_n2647 $abc$30358$new_n2646 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][3] yv[0][2] xv[0][4] yv[0][3] $abc$30358$new_n2648 $abc$30358$new_n2647 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][1] yv[0][0] xv[0][2] yv[0][1] $abc$30358$new_n2648 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[0][18] xv[0][19] yv[0][17] yv[0][18] $abc$30358$new_n2650 $abc$30358$new_n2649 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][16] xv[0][17] yv[0][15] yv[0][16] $abc$30358$new_n2651 $abc$30358$new_n2650 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][14] xv[0][15] yv[0][13] yv[0][14] $abc$30358$new_n2652 $abc$30358$new_n2651 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][13] yv[0][12] $abc$30358$new_n2665 $abc$30358$new_n2653 $abc$30358$new_n2664 $abc$30358$new_n2652 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][10] $abc$30358$new_n2654 $abc$30358$new_n2663 yv[0][9] $abc$30358$new_n2662 $abc$30358$new_n2653 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2659 $abc$30358$new_n2658 $abc$30358$new_n2661 $abc$30358$new_n2655 $abc$30358$new_n2660 $abc$30358$new_n2654 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[0][5] xv[0][6] yv[0][4] yv[0][5] $abc$30358$new_n2656 $abc$30358$new_n2655 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][3] xv[0][4] yv[0][2] yv[0][3] $abc$30358$new_n2657 $abc$30358$new_n2656 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[0][1] xv[0][2] yv[0][0] yv[0][1] $abc$30358$new_n2657 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[0][9] yv[0][8] $abc$30358$new_n2658 +01 1 +10 1 +.names xv[0][8] yv[0][7] $abc$30358$new_n2659 +10 1 +.names xv[0][7] yv[0][6] $abc$30358$new_n2660 +01 1 +10 1 +.names yv[0][7] xv[0][8] yv[0][6] xv[0][7] $abc$30358$new_n2661 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[0][11] yv[0][10] $abc$30358$new_n2662 +01 1 +10 1 +.names yv[0][8] xv[0][9] $abc$30358$new_n2663 +10 1 +.names xv[0][12] yv[0][11] $abc$30358$new_n2664 +10 1 +.names yv[0][11] xv[0][12] yv[0][10] xv[0][11] $abc$30358$new_n2665 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[0][19] yv[0][18] $abc$30358$new_n2667 yv[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26037 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][18] yv[0][17] $abc$30358$new_n2650 $abc$30358$new_n2668 $abc$30358$new_n2667 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][17] yv[0][16] $abc$30358$new_n2641 $abc$30358$new_n2668 +011 1 +101 1 +110 1 +111 1 +.names i_ce xv[0][18] yv[0][17] $abc$30358$new_n2670 yv[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26039 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2668 $abc$30358$new_n2650 $abc$30358$new_n2670 +000 1 +010 1 +100 1 +101 1 +.names i_ce xv[0][17] yv[0][16] $abc$30358$new_n2672 yv[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26041 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][15] xv[0][16] $abc$30358$new_n2651 $abc$30358$new_n2673 $abc$30358$new_n2672 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[0][15] yv[0][14] $abc$30358$new_n2642 $abc$30358$new_n2673 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n2675 yv[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26043 +001 1 +011 1 +110 1 +111 1 +.names xv[0][16] yv[0][15] yv[0][20] $abc$30358$new_n2651 $abc$30358$new_n2673 $abc$30358$new_n2675 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][15] yv[0][14] $abc$30358$new_n2677 yv[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26045 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] xv[0][14] yv[0][13] $abc$30358$new_n2652 $abc$30358$new_n2642 $abc$30358$new_n2677 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[0][14] yv[0][13] $abc$30358$new_n2679 yv[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26047 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] xv[0][13] yv[0][12] $abc$30358$new_n2643 $abc$30358$new_n2652 $abc$30358$new_n2679 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[0][13] yv[0][12] $abc$30358$new_n2681 yv[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26049 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2664 $abc$30358$new_n2643 $abc$30358$new_n2653 $abc$30358$new_n2665 $abc$30358$new_n2681 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[0][12] yv[0][11] $abc$30358$new_n2683 yv[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26051 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][10] xv[0][11] $abc$30358$new_n2644 $abc$30358$new_n2653 $abc$30358$new_n2683 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2662 $abc$30358$new_n2685 yv[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26053 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[0][20] xv[0][10] yv[0][9] $abc$30358$new_n2687 $abc$30358$new_n2686 $abc$30358$new_n2685 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][9] yv[0][8] $abc$30358$new_n2645 $abc$30358$new_n2686 +000 1 +001 1 +011 1 +101 1 +.names $abc$30358$new_n2663 $abc$30358$new_n2654 $abc$30358$new_n2687 +00 1 +.names i_ce $abc$30358$new_n2689 yv[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26055 +001 1 +011 1 +110 1 +111 1 +.names xv[0][10] yv[0][9] yv[0][20] $abc$30358$new_n2687 $abc$30358$new_n2686 $abc$30358$new_n2689 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n2691 yv[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26057 +001 1 +011 1 +100 1 +101 1 +.names $abc$30358$new_n2658 yv[0][20] $abc$30358$new_n2692 $abc$30358$new_n2645 $abc$30358$new_n2691 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n2659 $abc$30358$new_n2661 $abc$30358$new_n2655 $abc$30358$new_n2660 $abc$30358$new_n2692 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[0][8] yv[0][7] $abc$30358$new_n2694 yv[1][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][6] xv[0][7] $abc$30358$new_n2655 $abc$30358$new_n2646 $abc$30358$new_n2694 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2696 yv[1][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26061 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n2660 yv[0][20] $abc$30358$new_n2655 $abc$30358$new_n2646 $abc$30358$new_n2696 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce xv[0][6] yv[0][5] $abc$30358$new_n2698 yv[1][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26063 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][4] xv[0][5] $abc$30358$new_n2656 $abc$30358$new_n2647 $abc$30358$new_n2698 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][5] yv[0][4] $abc$30358$new_n2700 yv[1][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2647 $abc$30358$new_n2656 $abc$30358$new_n2700 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[0][4] yv[0][3] $abc$30358$new_n2702 yv[1][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26067 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] yv[0][2] xv[0][3] $abc$30358$new_n2657 $abc$30358$new_n2648 $abc$30358$new_n2702 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[0][3] yv[0][2] $abc$30358$new_n2704 yv[1][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26069 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2648 $abc$30358$new_n2657 $abc$30358$new_n2704 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][2] yv[0][1] $abc$30358$new_n2706 yv[1][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26071 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[0][1] yv[0][20] yv[0][0] $abc$30358$new_n2706 +100 1 +111 1 +.names i_ce xv[0][1] yv[0][0] yv[1][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26073 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2709 xv[0][19] xv[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26075 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[0][20] yv[0][19] xv[0][18] $abc$30358$new_n2719 $abc$30358$new_n2710 $abc$30358$new_n2709 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[0][17] xv[0][16] xv[0][17] yv[0][18] $abc$30358$new_n2711 $abc$30358$new_n2710 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[0][14] xv[0][15] yv[0][15] yv[0][16] $abc$30358$new_n2712 $abc$30358$new_n2711 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[0][13] xv[0][12] xv[0][13] yv[0][14] $abc$30358$new_n2713 $abc$30358$new_n2712 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][11] xv[0][10] xv[0][11] yv[0][12] $abc$30358$new_n2714 $abc$30358$new_n2713 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][9] xv[0][8] xv[0][9] yv[0][10] $abc$30358$new_n2715 $abc$30358$new_n2714 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][7] xv[0][6] xv[0][7] yv[0][8] $abc$30358$new_n2716 $abc$30358$new_n2715 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][5] xv[0][4] xv[0][5] yv[0][6] $abc$30358$new_n2717 $abc$30358$new_n2716 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[0][3] xv[0][2] xv[0][3] yv[0][4] $abc$30358$new_n2718 $abc$30358$new_n2717 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[0][1] xv[0][0] xv[0][1] yv[0][2] $abc$30358$new_n2718 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[0][16] yv[0][17] xv[0][17] yv[0][18] $abc$30358$new_n2720 $abc$30358$new_n2719 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][14] yv[0][15] xv[0][15] yv[0][16] $abc$30358$new_n2721 $abc$30358$new_n2720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][12] yv[0][13] xv[0][13] yv[0][14] $abc$30358$new_n2722 $abc$30358$new_n2721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][10] yv[0][11] xv[0][11] yv[0][12] $abc$30358$new_n2723 $abc$30358$new_n2722 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][8] yv[0][9] xv[0][9] yv[0][10] $abc$30358$new_n2724 $abc$30358$new_n2723 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][6] yv[0][7] xv[0][7] yv[0][8] $abc$30358$new_n2725 $abc$30358$new_n2724 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][4] yv[0][5] xv[0][5] yv[0][6] $abc$30358$new_n2726 $abc$30358$new_n2725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][2] yv[0][3] xv[0][3] yv[0][4] $abc$30358$new_n2727 $abc$30358$new_n2726 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[0][0] yv[0][1] xv[0][1] yv[0][2] $abc$30358$new_n2727 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[0][18] yv[0][19] $abc$30358$new_n2729 xv[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26077 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2710 $abc$30358$new_n2719 $abc$30358$new_n2729 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[0][17] yv[0][18] $abc$30358$new_n2731 xv[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26079 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][17] xv[0][16] $abc$30358$new_n2720 $abc$30358$new_n2711 $abc$30358$new_n2731 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][16] yv[0][17] $abc$30358$new_n2733 xv[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26081 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] $abc$30358$new_n2711 $abc$30358$new_n2720 $abc$30358$new_n2733 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][15] yv[0][16] $abc$30358$new_n2735 xv[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26083 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][15] xv[0][14] $abc$30358$new_n2721 $abc$30358$new_n2712 $abc$30358$new_n2735 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2737 xv[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26085 +001 1 +011 1 +110 1 +111 1 +.names xv[0][14] yv[0][15] yv[0][20] $abc$30358$new_n2721 $abc$30358$new_n2712 $abc$30358$new_n2737 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[0][13] yv[0][14] $abc$30358$new_n2739 xv[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26087 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[0][20] xv[0][12] yv[0][13] $abc$30358$new_n2722 $abc$30358$new_n2713 $abc$30358$new_n2739 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][12] yv[0][13] $abc$30358$new_n2741 xv[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26089 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2713 $abc$30358$new_n2722 $abc$30358$new_n2741 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][11] yv[0][12] $abc$30358$new_n2743 xv[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26091 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][11] xv[0][10] $abc$30358$new_n2723 $abc$30358$new_n2714 $abc$30358$new_n2743 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][10] yv[0][11] $abc$30358$new_n2745 xv[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26093 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2714 $abc$30358$new_n2723 $abc$30358$new_n2745 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][9] yv[0][10] $abc$30358$new_n2747 xv[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26095 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][9] xv[0][8] $abc$30358$new_n2724 $abc$30358$new_n2715 $abc$30358$new_n2747 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][8] yv[0][9] $abc$30358$new_n2749 xv[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26097 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2715 $abc$30358$new_n2724 $abc$30358$new_n2749 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][7] yv[0][8] $abc$30358$new_n2751 xv[1][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26099 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][7] xv[0][6] $abc$30358$new_n2725 $abc$30358$new_n2716 $abc$30358$new_n2751 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][6] yv[0][7] $abc$30358$new_n2753 xv[1][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26101 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2716 $abc$30358$new_n2725 $abc$30358$new_n2753 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][5] yv[0][6] $abc$30358$new_n2755 xv[1][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26103 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][5] xv[0][4] $abc$30358$new_n2726 $abc$30358$new_n2717 $abc$30358$new_n2755 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[0][4] yv[0][5] $abc$30358$new_n2757 xv[1][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26105 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2717 $abc$30358$new_n2726 $abc$30358$new_n2757 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[0][3] yv[0][4] $abc$30358$new_n2759 xv[1][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26107 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] yv[0][3] xv[0][2] $abc$30358$new_n2727 $abc$30358$new_n2718 $abc$30358$new_n2759 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[0][2] yv[0][3] $abc$30358$new_n2761 xv[1][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26109 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[0][20] $abc$30358$new_n2718 $abc$30358$new_n2727 $abc$30358$new_n2761 +000 1 +010 1 +100 1 +101 1 +.names i_ce $abc$30358$new_n2763 xv[1][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26111 +001 1 +011 1 +110 1 +111 1 +.names xv[0][1] yv[0][2] yv[0][20] xv[0][0] yv[0][1] $abc$30358$new_n2763 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[0][0] yv[0][1] xv[1][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26113 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][19] $abc$30358$new_n2766 ph[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26115 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[1][18] $abc$30358$new_n2767 $abc$30358$new_n2770 $abc$30358$new_n2766 +000 1 +010 1 +100 1 +101 1 +.names ph[1][17] yv[1][20] ph[1][16] ph[1][15] $abc$30358$new_n2768 $abc$30358$new_n2767 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names ph[1][14] $abc$30358$new_n2769 ph[1][13] $abc$30358$new_n2768 +100 1 +101 1 +111 1 +.names ph[1][8] ph[1][9] ph[1][10] ph[1][11] ph[1][12] $abc$30358$new_n2769 +00000 1 +.names yv[1][20] ph[1][17] ph[1][16] $abc$30358$new_n2771 ph[1][15] $abc$30358$new_n2770 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +.names ph[1][14] ph[1][12] $abc$30358$new_n2772 ph[1][11] $abc$30358$new_n2771 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[1][7] ph[1][8] ph[1][9] ph[1][10] ph[1][13] $abc$30358$new_n2772 +11111 1 +.names i_ce ph[1][18] $abc$30358$new_n2770 $abc$30358$new_n2767 ph[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26117 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[1][17] $abc$30358$new_n2775 ph[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26119 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[1][20] ph[1][16] ph[1][15] $abc$30358$new_n2768 $abc$30358$new_n2771 $abc$30358$new_n2775 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2777 ph[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26121 +001 1 +011 1 +110 1 +111 1 +.names ph[1][16] ph[1][15] yv[1][20] $abc$30358$new_n2771 $abc$30358$new_n2768 $abc$30358$new_n2777 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2779 ph[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26123 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] ph[1][15] $abc$30358$new_n2771 $abc$30358$new_n2768 $abc$30358$new_n2779 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[1][14] $abc$30358$new_n2781 ph[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26125 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[1][11] ph[1][12] ph[1][13] $abc$30358$new_n2782 $abc$30358$new_n2783 $abc$30358$new_n2781 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[1][8] ph[1][9] ph[1][10] yv[1][20] $abc$30358$new_n2782 +0000 1 +.names ph[1][7] ph[1][8] ph[1][9] ph[1][10] yv[1][20] $abc$30358$new_n2783 +11111 1 +.names i_ce $abc$30358$new_n2785 ph[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26127 +001 1 +011 1 +110 1 +111 1 +.names ph[1][11] ph[1][13] ph[1][12] $abc$30358$new_n2783 $abc$30358$new_n2782 $abc$30358$new_n2785 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2787 ph[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26129 +001 1 +011 1 +100 1 +101 1 +.names ph[1][11] ph[1][12] $abc$30358$new_n2783 $abc$30358$new_n2782 $abc$30358$new_n2787 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[1][11] $abc$30358$new_n2783 $abc$30358$new_n2782 ph[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2790 ph[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26133 +001 1 +011 1 +110 1 +111 1 +.names ph[1][8] ph[1][10] ph[1][9] yv[1][20] ph[1][7] $abc$30358$new_n2790 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n2792 ph[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26135 +001 1 +011 1 +100 1 +101 1 +.names ph[1][8] ph[1][9] yv[1][20] ph[1][7] $abc$30358$new_n2792 +0010 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1010 1 +1111 1 +.names i_ce ph[1][8] yv[1][20] ph[1][7] ph[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26137 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce ph[1][7] yv[1][20] ph[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26139 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[1][20] ph[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26141 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26143 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26145 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[1][20] ph[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26147 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[1][20] ph[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26149 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[1][20] ph[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26151 +001 1 +011 1 +100 1 +101 1 +.names ph[2][0] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26153 +01 1 +10 1 +11 1 +.names i_ce xv[1][20] yv[1][19] $abc$30358$new_n2803 yv[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26155 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][20] yv[1][18] $abc$30358$new_n2821 $abc$30358$new_n2804 $abc$30358$new_n2803 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][19] yv[1][17] $abc$30358$new_n2805 $abc$30358$new_n2804 +001 1 +100 1 +101 1 +111 1 +.names xv[1][17] xv[1][18] yv[1][15] yv[1][16] $abc$30358$new_n2806 $abc$30358$new_n2805 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][15] xv[1][16] yv[1][13] yv[1][14] $abc$30358$new_n2807 $abc$30358$new_n2806 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][14] yv[1][12] $abc$30358$new_n2820 $abc$30358$new_n2808 $abc$30358$new_n2819 $abc$30358$new_n2807 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][11] $abc$30358$new_n2809 $abc$30358$new_n2818 yv[1][9] $abc$30358$new_n2817 $abc$30358$new_n2808 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2814 $abc$30358$new_n2813 $abc$30358$new_n2816 $abc$30358$new_n2810 $abc$30358$new_n2815 $abc$30358$new_n2809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[1][6] xv[1][7] yv[1][4] yv[1][5] $abc$30358$new_n2811 $abc$30358$new_n2810 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][4] xv[1][5] yv[1][2] yv[1][3] $abc$30358$new_n2812 $abc$30358$new_n2811 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[1][2] xv[1][3] yv[1][0] yv[1][1] $abc$30358$new_n2812 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[1][10] yv[1][8] $abc$30358$new_n2813 +01 1 +10 1 +.names xv[1][9] yv[1][7] $abc$30358$new_n2814 +10 1 +.names xv[1][8] yv[1][6] $abc$30358$new_n2815 +01 1 +10 1 +.names yv[1][7] xv[1][9] yv[1][6] xv[1][8] $abc$30358$new_n2816 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[1][12] yv[1][10] $abc$30358$new_n2817 +01 1 +10 1 +.names yv[1][8] xv[1][10] $abc$30358$new_n2818 +10 1 +.names xv[1][13] yv[1][11] $abc$30358$new_n2819 +10 1 +.names yv[1][11] xv[1][13] yv[1][10] xv[1][12] $abc$30358$new_n2820 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[1][18] yv[1][16] xv[1][19] yv[1][17] $abc$30358$new_n2822 $abc$30358$new_n2821 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][16] yv[1][14] xv[1][17] yv[1][15] $abc$30358$new_n2823 $abc$30358$new_n2822 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][14] yv[1][12] xv[1][15] yv[1][13] $abc$30358$new_n2824 $abc$30358$new_n2823 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][10] xv[1][13] yv[1][11] $abc$30358$new_n2825 $abc$30358$new_n2824 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][8] xv[1][11] yv[1][9] $abc$30358$new_n2826 $abc$30358$new_n2825 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][6] xv[1][9] yv[1][7] $abc$30358$new_n2827 $abc$30358$new_n2826 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][4] xv[1][7] yv[1][5] $abc$30358$new_n2828 $abc$30358$new_n2827 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][2] xv[1][5] yv[1][3] $abc$30358$new_n2829 $abc$30358$new_n2828 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][2] yv[1][0] xv[1][3] yv[1][1] $abc$30358$new_n2829 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[1][20] yv[1][18] $abc$30358$new_n2831 yv[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26157 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2804 $abc$30358$new_n2821 $abc$30358$new_n2831 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][19] yv[1][17] $abc$30358$new_n2833 yv[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26159 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][18] yv[1][16] $abc$30358$new_n2822 $abc$30358$new_n2805 $abc$30358$new_n2833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce xv[1][18] yv[1][16] $abc$30358$new_n2835 yv[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26161 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][15] xv[1][17] $abc$30358$new_n2806 $abc$30358$new_n2822 $abc$30358$new_n2835 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[1][17] yv[1][15] $abc$30358$new_n2837 yv[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26163 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][16] yv[1][14] $abc$30358$new_n2823 $abc$30358$new_n2806 $abc$30358$new_n2837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][16] yv[1][14] $abc$30358$new_n2839 yv[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26165 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][15] yv[1][13] $abc$30358$new_n2807 $abc$30358$new_n2823 $abc$30358$new_n2839 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[1][15] yv[1][13] $abc$30358$new_n2841 yv[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26167 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] xv[1][14] yv[1][12] $abc$30358$new_n2824 $abc$30358$new_n2842 $abc$30358$new_n2841 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2819 $abc$30358$new_n2808 $abc$30358$new_n2820 $abc$30358$new_n2842 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n2844 yv[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26169 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][14] yv[1][12] $abc$30358$new_n2824 $abc$30358$new_n2842 $abc$30358$new_n2844 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][13] yv[1][11] $abc$30358$new_n2846 yv[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26171 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][10] xv[1][12] $abc$30358$new_n2825 $abc$30358$new_n2808 $abc$30358$new_n2846 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2817 $abc$30358$new_n2848 yv[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26173 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[1][20] xv[1][11] yv[1][9] $abc$30358$new_n2850 $abc$30358$new_n2849 $abc$30358$new_n2848 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2818 $abc$30358$new_n2809 $abc$30358$new_n2849 +00 1 +.names xv[1][10] yv[1][8] $abc$30358$new_n2826 $abc$30358$new_n2850 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n2852 yv[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26175 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][11] yv[1][9] $abc$30358$new_n2850 $abc$30358$new_n2849 $abc$30358$new_n2852 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2854 yv[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26177 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] $abc$30358$new_n2813 $abc$30358$new_n2826 $abc$30358$new_n2855 $abc$30358$new_n2854 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n2814 $abc$30358$new_n2816 $abc$30358$new_n2810 $abc$30358$new_n2815 $abc$30358$new_n2855 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[1][9] yv[1][7] $abc$30358$new_n2857 yv[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26179 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][6] xv[1][8] $abc$30358$new_n2827 $abc$30358$new_n2810 $abc$30358$new_n2857 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2859 yv[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26181 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] $abc$30358$new_n2815 $abc$30358$new_n2827 $abc$30358$new_n2810 $abc$30358$new_n2859 +0001 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[1][7] yv[1][5] $abc$30358$new_n2861 yv[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26183 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][4] xv[1][6] $abc$30358$new_n2828 $abc$30358$new_n2811 $abc$30358$new_n2861 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2863 yv[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26185 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][6] yv[1][4] $abc$30358$new_n2828 $abc$30358$new_n2811 $abc$30358$new_n2863 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][5] yv[1][3] $abc$30358$new_n2865 yv[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26187 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] yv[1][2] xv[1][4] $abc$30358$new_n2829 $abc$30358$new_n2812 $abc$30358$new_n2865 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[1][4] yv[1][2] $abc$30358$new_n2867 yv[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26189 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2812 $abc$30358$new_n2829 $abc$30358$new_n2867 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][3] yv[1][1] $abc$30358$new_n2869 yv[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26191 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[1][2] yv[1][20] yv[1][0] $abc$30358$new_n2869 +100 1 +111 1 +.names i_ce xv[1][2] yv[1][0] yv[2][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26193 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2872 xv[2][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26195 +001 1 +011 1 +110 1 +111 1 +.names xv[1][19] yv[1][20] xv[1][18] $abc$30358$new_n2882 $abc$30358$new_n2873 $abc$30358$new_n2872 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[1][16] yv[1][18] xv[1][17] yv[1][19] $abc$30358$new_n2874 $abc$30358$new_n2873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][14] yv[1][16] xv[1][15] yv[1][17] $abc$30358$new_n2875 $abc$30358$new_n2874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][12] yv[1][14] xv[1][13] yv[1][15] $abc$30358$new_n2876 $abc$30358$new_n2875 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][10] yv[1][12] xv[1][11] yv[1][13] $abc$30358$new_n2877 $abc$30358$new_n2876 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][8] yv[1][10] xv[1][9] yv[1][11] $abc$30358$new_n2878 $abc$30358$new_n2877 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][6] yv[1][8] xv[1][7] yv[1][9] $abc$30358$new_n2879 $abc$30358$new_n2878 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[1][4] yv[1][6] xv[1][5] yv[1][7] $abc$30358$new_n2880 $abc$30358$new_n2879 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[1][2] yv[1][4] xv[1][3] yv[1][5] $abc$30358$new_n2881 $abc$30358$new_n2880 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[1][0] yv[1][2] xv[1][1] yv[1][3] $abc$30358$new_n2881 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[1][18] xv[1][16] xv[1][17] yv[1][19] $abc$30358$new_n2883 $abc$30358$new_n2882 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[1][14] xv[1][15] yv[1][16] yv[1][17] $abc$30358$new_n2884 $abc$30358$new_n2883 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[1][14] xv[1][12] xv[1][13] yv[1][15] $abc$30358$new_n2885 $abc$30358$new_n2884 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][12] xv[1][10] xv[1][11] yv[1][13] $abc$30358$new_n2886 $abc$30358$new_n2885 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][10] xv[1][8] xv[1][9] yv[1][11] $abc$30358$new_n2887 $abc$30358$new_n2886 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][8] xv[1][6] xv[1][7] yv[1][9] $abc$30358$new_n2888 $abc$30358$new_n2887 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][6] xv[1][4] xv[1][5] yv[1][7] $abc$30358$new_n2889 $abc$30358$new_n2888 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[1][4] xv[1][2] xv[1][3] yv[1][5] $abc$30358$new_n2890 $abc$30358$new_n2889 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[1][2] xv[1][0] xv[1][1] yv[1][3] $abc$30358$new_n2890 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n2899 xv[2][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26201 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][16] yv[1][18] $abc$30358$new_n2883 $abc$30358$new_n2874 $abc$30358$new_n2899 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][15] yv[1][17] $abc$30358$new_n2901 xv[2][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26203 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][14] yv[1][16] $abc$30358$new_n2884 $abc$30358$new_n2875 $abc$30358$new_n2901 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2903 xv[2][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26205 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][14] yv[1][16] $abc$30358$new_n2884 $abc$30358$new_n2875 $abc$30358$new_n2903 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[1][13] yv[1][15] $abc$30358$new_n2905 xv[2][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26207 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][14] xv[1][12] $abc$30358$new_n2885 $abc$30358$new_n2876 $abc$30358$new_n2905 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2907 xv[2][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26209 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][12] yv[1][14] $abc$30358$new_n2885 $abc$30358$new_n2876 $abc$30358$new_n2907 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][11] yv[1][13] $abc$30358$new_n2909 xv[2][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26211 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][12] xv[1][10] $abc$30358$new_n2886 $abc$30358$new_n2877 $abc$30358$new_n2909 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][10] yv[1][12] $abc$30358$new_n2911 xv[2][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26213 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2877 $abc$30358$new_n2886 $abc$30358$new_n2911 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][9] yv[1][11] $abc$30358$new_n2913 xv[2][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26215 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][10] xv[1][8] $abc$30358$new_n2887 $abc$30358$new_n2878 $abc$30358$new_n2913 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][8] yv[1][10] $abc$30358$new_n2915 xv[2][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26217 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2878 $abc$30358$new_n2887 $abc$30358$new_n2915 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][7] yv[1][9] $abc$30358$new_n2917 xv[2][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26219 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][8] xv[1][6] $abc$30358$new_n2888 $abc$30358$new_n2879 $abc$30358$new_n2917 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][6] yv[1][8] $abc$30358$new_n2919 xv[2][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26221 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] $abc$30358$new_n2879 $abc$30358$new_n2888 $abc$30358$new_n2919 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[1][5] yv[1][7] $abc$30358$new_n2921 xv[2][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26223 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[1][20] yv[1][6] xv[1][4] $abc$30358$new_n2889 $abc$30358$new_n2880 $abc$30358$new_n2921 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2923 xv[2][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26225 +001 1 +011 1 +100 1 +101 1 +.names yv[1][20] xv[1][4] yv[1][6] $abc$30358$new_n2889 $abc$30358$new_n2880 $abc$30358$new_n2923 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[1][3] yv[1][5] $abc$30358$new_n2925 xv[2][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26227 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] xv[1][2] yv[1][4] $abc$30358$new_n2890 $abc$30358$new_n2881 $abc$30358$new_n2925 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[1][2] yv[1][4] $abc$30358$new_n2927 xv[2][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26229 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[1][20] $abc$30358$new_n2881 $abc$30358$new_n2890 $abc$30358$new_n2927 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n2929 xv[2][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26231 +001 1 +011 1 +110 1 +111 1 +.names xv[1][1] yv[1][3] yv[1][20] xv[1][0] yv[1][2] $abc$30358$new_n2929 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[1][0] yv[1][2] xv[2][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26233 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n2932 ph[2][19] ph[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26235 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[2][18] $abc$30358$new_n2933 $abc$30358$new_n2940 $abc$30358$new_n2932 +000 1 +001 1 +100 1 +110 1 +.names yv[2][20] $abc$30358$new_n2934 ph[2][17] $abc$30358$new_n2933 +110 1 +.names ph[2][16] $abc$30358$new_n2935 $abc$30358$new_n2934 +00 1 +.names ph[2][15] $abc$30358$new_n2936 ph[2][14] $abc$30358$new_n2935 +101 1 +110 1 +111 1 +.names ph[2][13] $abc$30358$new_n2937 ph[2][11] ph[2][12] $abc$30358$new_n2936 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[2][10] $abc$30358$new_n2938 $abc$30358$new_n2937 +00 1 +.names ph[2][9] ph[2][8] $abc$30358$new_n2939 ph[2][6] ph[2][7] $abc$30358$new_n2938 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[2][5] ph[2][3] ph[2][4] ph[2][1] ph[2][2] $abc$30358$new_n2939 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n2941 ph[2][17] yv[2][20] $abc$30358$new_n2940 +110 1 +.names ph[2][16] $abc$30358$new_n2942 $abc$30358$new_n2941 +10 1 +.names ph[2][15] $abc$30358$new_n2943 ph[2][14] $abc$30358$new_n2942 +000 1 +010 1 +011 1 +.names ph[2][13] ph[2][12] $abc$30358$new_n2944 ph[2][11] $abc$30358$new_n2943 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names ph[2][10] $abc$30358$new_n2945 $abc$30358$new_n2944 +10 1 +.names ph[2][9] ph[2][7] ph[2][8] ph[2][6] $abc$30358$new_n2946 $abc$30358$new_n2945 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[2][5] ph[2][3] ph[2][4] ph[2][1] ph[2][2] $abc$30358$new_n2946 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce ph[2][18] $abc$30358$new_n2940 $abc$30358$new_n2933 ph[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n2949 ph[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26239 +001 1 +011 1 +110 1 +111 1 +.names ph[2][17] yv[2][20] $abc$30358$new_n2941 $abc$30358$new_n2934 $abc$30358$new_n2949 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n2951 ph[3][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26241 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[2][16] yv[2][20] $abc$30358$new_n2942 $abc$30358$new_n2935 $abc$30358$new_n2951 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n2953 ph[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26243 +001 1 +011 1 +110 1 +111 1 +.names ph[2][14] ph[2][15] $abc$30358$new_n2955 $abc$30358$new_n2954 $abc$30358$new_n2953 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[2][20] $abc$30358$new_n2936 $abc$30358$new_n2954 +10 1 +.names yv[2][20] $abc$30358$new_n2943 $abc$30358$new_n2955 +00 1 +.names i_ce ph[2][14] $abc$30358$new_n2955 $abc$30358$new_n2954 ph[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26245 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[2][13] $abc$30358$new_n2958 ph[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26247 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[2][11] ph[2][12] yv[2][20] $abc$30358$new_n2937 $abc$30358$new_n2944 $abc$30358$new_n2958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2960 ph[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26249 +001 1 +011 1 +100 1 +101 1 +.names ph[2][12] yv[2][20] ph[2][11] $abc$30358$new_n2944 $abc$30358$new_n2937 $abc$30358$new_n2960 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n2962 ph[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26251 +001 1 +011 1 +110 1 +111 1 +.names ph[2][11] yv[2][20] $abc$30358$new_n2944 $abc$30358$new_n2937 $abc$30358$new_n2962 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2964 ph[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26253 +001 1 +011 1 +100 1 +101 1 +.names ph[2][10] yv[2][20] $abc$30358$new_n2945 $abc$30358$new_n2938 $abc$30358$new_n2964 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n2966 ph[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26255 +001 1 +011 1 +100 1 +101 1 +.names ph[2][9] ph[2][8] $abc$30358$new_n2968 ph[2][7] $abc$30358$new_n2967 $abc$30358$new_n2966 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names ph[2][7] ph[2][6] yv[2][20] $abc$30358$new_n2946 $abc$30358$new_n2967 +1100 1 +.names yv[2][20] ph[2][6] $abc$30358$new_n2939 $abc$30358$new_n2968 +100 1 +.names i_ce $abc$30358$new_n2970 ph[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26257 +001 1 +011 1 +110 1 +111 1 +.names ph[2][8] $abc$30358$new_n2967 $abc$30358$new_n2968 ph[2][7] $abc$30358$new_n2970 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names i_ce $abc$30358$new_n2972 ph[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26259 +001 1 +011 1 +100 1 +101 1 +.names ph[2][7] yv[2][20] ph[2][6] $abc$30358$new_n2946 $abc$30358$new_n2939 $abc$30358$new_n2972 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n2974 ph[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26261 +001 1 +011 1 +100 1 +101 1 +.names ph[2][6] yv[2][20] $abc$30358$new_n2946 $abc$30358$new_n2939 $abc$30358$new_n2974 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[2][5] $abc$30358$new_n2976 ph[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26263 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] ph[2][1] ph[2][2] ph[2][3] ph[2][4] $abc$30358$new_n2976 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2978 ph[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26265 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] ph[2][4] ph[2][1] ph[2][2] ph[2][3] $abc$30358$new_n2978 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n2980 ph[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26267 +001 1 +011 1 +100 1 +101 1 +.names ph[2][3] yv[2][20] ph[2][1] ph[2][2] $abc$30358$new_n2980 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[2][20] ph[2][1] ph[2][2] ph[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[2][1] ph[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26271 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[2][0] ph[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26273 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[2][20] yv[2][19] $abc$30358$new_n2985 yv[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26275 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][20] yv[2][18] $abc$30358$new_n3003 $abc$30358$new_n2986 $abc$30358$new_n2985 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][20] yv[2][17] $abc$30358$new_n2987 $abc$30358$new_n2986 +001 1 +100 1 +101 1 +111 1 +.names xv[2][18] xv[2][19] yv[2][15] yv[2][16] $abc$30358$new_n2988 $abc$30358$new_n2987 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][16] xv[2][17] yv[2][13] yv[2][14] $abc$30358$new_n2989 $abc$30358$new_n2988 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][15] yv[2][12] $abc$30358$new_n3002 $abc$30358$new_n2990 $abc$30358$new_n3001 $abc$30358$new_n2989 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][12] $abc$30358$new_n2991 $abc$30358$new_n3000 yv[2][9] $abc$30358$new_n2999 $abc$30358$new_n2990 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n2996 $abc$30358$new_n2995 $abc$30358$new_n2998 $abc$30358$new_n2992 $abc$30358$new_n2997 $abc$30358$new_n2991 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[2][7] xv[2][8] yv[2][4] yv[2][5] $abc$30358$new_n2993 $abc$30358$new_n2992 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][5] xv[2][6] yv[2][2] yv[2][3] $abc$30358$new_n2994 $abc$30358$new_n2993 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][3] xv[2][4] yv[2][0] yv[2][1] $abc$30358$new_n2994 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[2][11] yv[2][8] $abc$30358$new_n2995 +01 1 +10 1 +.names xv[2][10] yv[2][7] $abc$30358$new_n2996 +10 1 +.names xv[2][9] yv[2][6] $abc$30358$new_n2997 +01 1 +10 1 +.names yv[2][7] xv[2][10] yv[2][6] xv[2][9] $abc$30358$new_n2998 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[2][13] yv[2][10] $abc$30358$new_n2999 +01 1 +10 1 +.names yv[2][8] xv[2][11] $abc$30358$new_n3000 +10 1 +.names xv[2][14] yv[2][11] $abc$30358$new_n3001 +10 1 +.names yv[2][11] xv[2][14] yv[2][10] xv[2][13] $abc$30358$new_n3002 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[2][19] yv[2][16] xv[2][20] yv[2][17] $abc$30358$new_n3004 $abc$30358$new_n3003 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][17] yv[2][14] xv[2][18] yv[2][15] $abc$30358$new_n3005 $abc$30358$new_n3004 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][15] yv[2][12] xv[2][16] yv[2][13] $abc$30358$new_n3006 $abc$30358$new_n3005 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][13] yv[2][10] xv[2][14] yv[2][11] $abc$30358$new_n3007 $abc$30358$new_n3006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][11] yv[2][8] xv[2][12] yv[2][9] $abc$30358$new_n3008 $abc$30358$new_n3007 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][9] yv[2][6] xv[2][10] yv[2][7] $abc$30358$new_n3009 $abc$30358$new_n3008 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][7] yv[2][4] xv[2][8] yv[2][5] $abc$30358$new_n3010 $abc$30358$new_n3009 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][5] yv[2][2] xv[2][6] yv[2][3] $abc$30358$new_n3011 $abc$30358$new_n3010 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][3] yv[2][0] xv[2][4] yv[2][1] $abc$30358$new_n3011 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[2][20] yv[2][18] $abc$30358$new_n3013 yv[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26277 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n2986 $abc$30358$new_n3003 $abc$30358$new_n3013 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[2][20] yv[2][17] $abc$30358$new_n3015 yv[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26279 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][16] xv[2][19] $abc$30358$new_n3004 $abc$30358$new_n3016 $abc$30358$new_n3015 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names xv[2][18] yv[2][15] $abc$30358$new_n2988 $abc$30358$new_n3016 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3018 yv[3][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26281 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][19] yv[2][16] $abc$30358$new_n3004 $abc$30358$new_n3016 $abc$30358$new_n3018 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][18] yv[2][15] $abc$30358$new_n3020 yv[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26283 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][17] yv[2][14] $abc$30358$new_n3005 $abc$30358$new_n2988 $abc$30358$new_n3020 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][17] yv[2][14] $abc$30358$new_n3022 yv[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26285 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][16] yv[2][13] $abc$30358$new_n2989 $abc$30358$new_n3005 $abc$30358$new_n3022 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[2][16] yv[2][13] $abc$30358$new_n3024 yv[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26287 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][15] yv[2][12] $abc$30358$new_n3006 $abc$30358$new_n2989 $abc$30358$new_n3024 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[2][15] yv[2][12] $abc$30358$new_n3026 yv[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26289 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3006 $abc$30358$new_n3001 $abc$30358$new_n3002 $abc$30358$new_n2990 $abc$30358$new_n3026 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[2][14] yv[2][11] $abc$30358$new_n3028 yv[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26291 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][10] xv[2][13] $abc$30358$new_n3007 $abc$30358$new_n2990 $abc$30358$new_n3028 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n2999 $abc$30358$new_n3030 yv[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26293 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] xv[2][12] yv[2][9] $abc$30358$new_n3032 $abc$30358$new_n3031 $abc$30358$new_n3030 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3000 $abc$30358$new_n2991 $abc$30358$new_n3031 +00 1 +.names xv[2][11] yv[2][8] $abc$30358$new_n3008 $abc$30358$new_n3032 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3034 yv[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26295 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][9] $abc$30358$new_n3032 $abc$30358$new_n3031 $abc$30358$new_n3034 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n2995 $abc$30358$new_n3036 yv[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26297 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] $abc$30358$new_n3037 $abc$30358$new_n3008 $abc$30358$new_n3036 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n2996 $abc$30358$new_n2998 $abc$30358$new_n2992 $abc$30358$new_n2997 $abc$30358$new_n3037 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[2][10] yv[2][7] $abc$30358$new_n3039 yv[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26299 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][6] xv[2][9] $abc$30358$new_n3009 $abc$30358$new_n2992 $abc$30358$new_n3039 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3041 $abc$30358$new_n2997 yv[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26301 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[2][20] $abc$30358$new_n2992 $abc$30358$new_n3009 $abc$30358$new_n3041 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][8] yv[2][5] $abc$30358$new_n3043 yv[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26303 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][4] xv[2][7] $abc$30358$new_n3010 $abc$30358$new_n2993 $abc$30358$new_n3043 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3045 yv[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26305 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][7] yv[2][4] $abc$30358$new_n3010 $abc$30358$new_n2993 $abc$30358$new_n3045 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][6] yv[2][3] $abc$30358$new_n3047 yv[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26307 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] yv[2][2] xv[2][5] $abc$30358$new_n3011 $abc$30358$new_n2994 $abc$30358$new_n3047 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[2][5] yv[2][2] $abc$30358$new_n3049 yv[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26309 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n2994 $abc$30358$new_n3011 $abc$30358$new_n3049 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3051 yv[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26311 +001 1 +011 1 +110 1 +111 1 +.names xv[2][4] yv[2][1] yv[2][20] yv[2][0] xv[2][3] $abc$30358$new_n3051 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[2][3] yv[2][0] yv[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26313 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[2][19] $abc$30358$new_n3054 xv[3][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26315 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[2][18] yv[2][20] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n3054 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[2][17] xv[2][16] yv[2][19] $abc$30358$new_n3056 $abc$30358$new_n3055 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[2][14] yv[2][17] xv[2][15] yv[2][18] $abc$30358$new_n3057 $abc$30358$new_n3056 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][12] yv[2][15] xv[2][13] yv[2][16] $abc$30358$new_n3058 $abc$30358$new_n3057 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][10] yv[2][13] xv[2][11] yv[2][14] $abc$30358$new_n3059 $abc$30358$new_n3058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][8] yv[2][11] xv[2][9] yv[2][12] $abc$30358$new_n3060 $abc$30358$new_n3059 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][6] yv[2][9] xv[2][7] yv[2][10] $abc$30358$new_n3061 $abc$30358$new_n3060 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[2][4] yv[2][7] xv[2][5] yv[2][8] $abc$30358$new_n3062 $abc$30358$new_n3061 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[2][2] yv[2][5] xv[2][3] yv[2][6] $abc$30358$new_n3063 $abc$30358$new_n3062 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[2][0] yv[2][3] xv[2][1] yv[2][4] $abc$30358$new_n3063 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[2][17] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3064 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[2][17] xv[2][14] xv[2][15] yv[2][18] $abc$30358$new_n3066 $abc$30358$new_n3065 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[2][12] xv[2][13] yv[2][15] yv[2][16] $abc$30358$new_n3067 $abc$30358$new_n3066 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[2][10] xv[2][11] yv[2][13] yv[2][14] $abc$30358$new_n3068 $abc$30358$new_n3067 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[2][11] xv[2][8] xv[2][9] yv[2][12] $abc$30358$new_n3069 $abc$30358$new_n3068 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][9] xv[2][6] xv[2][7] yv[2][10] $abc$30358$new_n3070 $abc$30358$new_n3069 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][7] xv[2][4] xv[2][5] yv[2][8] $abc$30358$new_n3071 $abc$30358$new_n3070 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[2][5] xv[2][2] xv[2][3] yv[2][6] $abc$30358$new_n3072 $abc$30358$new_n3071 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[2][3] xv[2][0] xv[2][1] yv[2][4] $abc$30358$new_n3072 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[2][17] $abc$30358$new_n3077 xv[3][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26319 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[2][20] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3056 $abc$30358$new_n3077 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3079 xv[3][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26321 +001 1 +011 1 +100 1 +101 1 +.names yv[2][20] xv[2][16] yv[2][19] $abc$30358$new_n3065 $abc$30358$new_n3056 $abc$30358$new_n3079 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][15] yv[2][18] $abc$30358$new_n3081 xv[3][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26323 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][17] xv[2][14] $abc$30358$new_n3066 $abc$30358$new_n3057 $abc$30358$new_n3081 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][14] yv[2][17] $abc$30358$new_n3083 xv[3][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26325 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n3057 $abc$30358$new_n3066 $abc$30358$new_n3083 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3089 xv[3][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26329 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][15] $abc$30358$new_n3067 $abc$30358$new_n3058 $abc$30358$new_n3089 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[2][10] yv[2][13] $abc$30358$new_n3095 xv[3][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26333 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3059 $abc$30358$new_n3068 $abc$30358$new_n3095 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][9] yv[2][12] $abc$30358$new_n3097 xv[3][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26335 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][11] xv[2][8] $abc$30358$new_n3069 $abc$30358$new_n3060 $abc$30358$new_n3097 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][8] yv[2][11] $abc$30358$new_n3099 xv[3][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26337 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3060 $abc$30358$new_n3069 $abc$30358$new_n3099 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][7] yv[2][10] $abc$30358$new_n3101 xv[3][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26339 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][9] xv[2][6] $abc$30358$new_n3070 $abc$30358$new_n3061 $abc$30358$new_n3101 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][6] yv[2][9] $abc$30358$new_n3103 xv[3][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26341 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] $abc$30358$new_n3061 $abc$30358$new_n3070 $abc$30358$new_n3103 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[2][5] yv[2][8] $abc$30358$new_n3105 xv[3][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26343 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] yv[2][7] xv[2][4] $abc$30358$new_n3071 $abc$30358$new_n3062 $abc$30358$new_n3105 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3107 xv[3][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26345 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][4] yv[2][7] $abc$30358$new_n3071 $abc$30358$new_n3062 $abc$30358$new_n3107 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[2][3] yv[2][6] $abc$30358$new_n3109 xv[3][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26347 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] xv[2][2] yv[2][5] $abc$30358$new_n3072 $abc$30358$new_n3063 $abc$30358$new_n3109 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[2][2] yv[2][5] $abc$30358$new_n3111 xv[3][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26349 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[2][20] $abc$30358$new_n3063 $abc$30358$new_n3072 $abc$30358$new_n3111 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3113 xv[3][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26351 +001 1 +011 1 +110 1 +111 1 +.names xv[2][1] yv[2][4] yv[2][20] xv[2][0] yv[2][3] $abc$30358$new_n3113 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[2][0] yv[2][3] xv[3][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26353 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[3][19] $abc$30358$new_n3122 $abc$30358$new_n3116 ph[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26355 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n3117 ph[3][16] ph[3][17] ph[3][18] yv[3][20] $abc$30358$new_n3116 +11110 1 +.names ph[3][15] ph[3][14] ph[3][13] $abc$30358$new_n3118 $abc$30358$new_n3117 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[3][12] ph[3][10] ph[3][11] ph[3][9] $abc$30358$new_n3119 $abc$30358$new_n3118 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[3][8] $abc$30358$new_n3120 $abc$30358$new_n3119 +00 1 +.names ph[3][7] ph[3][6] $abc$30358$new_n3121 ph[3][5] $abc$30358$new_n3120 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[3][0] ph[3][1] ph[3][2] ph[3][3] ph[3][4] $abc$30358$new_n3121 +11111 1 +.names yv[3][20] $abc$30358$new_n3123 ph[3][16] ph[3][17] ph[3][18] $abc$30358$new_n3122 +11000 1 +.names ph[3][15] ph[3][14] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3123 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[3][12] ph[3][11] $abc$30358$new_n3125 ph[3][9] ph[3][10] $abc$30358$new_n3124 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[3][8] $abc$30358$new_n3126 $abc$30358$new_n3125 +10 1 +.names ph[3][7] ph[3][5] ph[3][6] $abc$30358$new_n3127 $abc$30358$new_n3126 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names ph[3][0] ph[3][1] ph[3][2] ph[3][3] ph[3][4] $abc$30358$new_n3127 +00000 1 +.names i_ce $abc$30358$new_n3129 ph[3][18] ph[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26357 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] ph[3][17] ph[3][16] $abc$30358$new_n3117 $abc$30358$new_n3123 $abc$30358$new_n3129 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3131 ph[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26359 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][17] ph[3][16] $abc$30358$new_n3123 $abc$30358$new_n3117 $abc$30358$new_n3131 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3133 ph[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26361 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][16] $abc$30358$new_n3123 $abc$30358$new_n3117 $abc$30358$new_n3133 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3138 ph[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26365 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] ph[3][14] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3118 $abc$30358$new_n3138 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3140 ph[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26367 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][13] $abc$30358$new_n3124 $abc$30358$new_n3118 $abc$30358$new_n3140 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3142 ph[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26369 +001 1 +011 1 +100 1 +101 1 +.names ph[3][10] ph[3][12] ph[3][11] $abc$30358$new_n3145 $abc$30358$new_n3143 $abc$30358$new_n3142 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[3][9] $abc$30358$new_n3144 $abc$30358$new_n3143 +11 1 +.names yv[3][20] $abc$30358$new_n3119 $abc$30358$new_n3144 +00 1 +.names $abc$30358$new_n3146 ph[3][9] $abc$30358$new_n3145 +10 1 +.names yv[3][20] $abc$30358$new_n3125 $abc$30358$new_n3146 +10 1 +.names i_ce $abc$30358$new_n3148 ph[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26371 +001 1 +011 1 +110 1 +111 1 +.names ph[3][11] ph[3][10] $abc$30358$new_n3145 $abc$30358$new_n3143 $abc$30358$new_n3148 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[3][10] $abc$30358$new_n3145 $abc$30358$new_n3143 ph[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26373 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[3][9] $abc$30358$new_n3146 $abc$30358$new_n3144 ph[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26375 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3152 ph[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26377 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][8] $abc$30358$new_n3126 $abc$30358$new_n3120 $abc$30358$new_n3152 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3154 ph[3][7] ph[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26379 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] ph[3][5] ph[3][6] $abc$30358$new_n3121 $abc$30358$new_n3127 $abc$30358$new_n3154 +00000 1 +00001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3156 ph[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26381 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] ph[3][6] ph[3][5] $abc$30358$new_n3127 $abc$30358$new_n3121 $abc$30358$new_n3156 +00000 1 +00010 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3158 ph[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26383 +001 1 +011 1 +100 1 +101 1 +.names ph[3][3] ph[3][5] ph[3][4] $abc$30358$new_n3160 $abc$30358$new_n3159 $abc$30358$new_n3158 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[3][2] ph[3][0] ph[3][1] yv[3][20] $abc$30358$new_n3159 +1110 1 +.names yv[3][20] ph[3][0] ph[3][1] ph[3][2] $abc$30358$new_n3160 +1000 1 +.names i_ce $abc$30358$new_n3162 ph[3][4] ph[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26385 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[3][3] $abc$30358$new_n3159 $abc$30358$new_n3160 $abc$30358$new_n3162 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[3][3] $abc$30358$new_n3160 $abc$30358$new_n3159 ph[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26387 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3165 ph[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26389 +001 1 +011 1 +100 1 +101 1 +.names ph[3][2] yv[3][20] ph[3][0] ph[3][1] $abc$30358$new_n3165 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[3][20] ph[3][0] ph[3][1] ph[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26391 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[3][0] ph[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26393 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[3][20] yv[3][19] $abc$30358$new_n3169 yv[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26395 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][18] xv[3][20] $abc$30358$new_n3189 $abc$30358$new_n3170 $abc$30358$new_n3169 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n3171 xv[3][20] yv[3][16] yv[3][17] $abc$30358$new_n3170 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names $abc$30358$new_n3187 $abc$30358$new_n3188 yv[3][15] xv[3][19] $abc$30358$new_n3172 $abc$30358$new_n3171 +10000 1 +10100 1 +10101 1 +10110 1 +.names xv[3][17] xv[3][18] yv[3][13] yv[3][14] $abc$30358$new_n3173 $abc$30358$new_n3172 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][16] yv[3][12] $abc$30358$new_n3186 $abc$30358$new_n3174 $abc$30358$new_n3185 $abc$30358$new_n3173 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][13] $abc$30358$new_n3175 $abc$30358$new_n3184 yv[3][9] $abc$30358$new_n3183 $abc$30358$new_n3174 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$30358$new_n3180 $abc$30358$new_n3179 $abc$30358$new_n3182 $abc$30358$new_n3176 $abc$30358$new_n3181 $abc$30358$new_n3175 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names xv[3][8] xv[3][9] yv[3][4] yv[3][5] $abc$30358$new_n3177 $abc$30358$new_n3176 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][6] xv[3][7] yv[3][2] yv[3][3] $abc$30358$new_n3178 $abc$30358$new_n3177 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[3][4] xv[3][5] yv[3][0] yv[3][1] $abc$30358$new_n3178 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[3][12] yv[3][8] $abc$30358$new_n3179 +01 1 +10 1 +.names xv[3][11] yv[3][7] $abc$30358$new_n3180 +10 1 +.names xv[3][10] yv[3][6] $abc$30358$new_n3181 +01 1 +10 1 +.names yv[3][7] xv[3][11] yv[3][6] xv[3][10] $abc$30358$new_n3182 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[3][14] yv[3][10] $abc$30358$new_n3183 +01 1 +10 1 +.names yv[3][8] xv[3][12] $abc$30358$new_n3184 +10 1 +.names xv[3][15] yv[3][11] $abc$30358$new_n3185 +10 1 +.names yv[3][11] xv[3][15] yv[3][10] xv[3][14] $abc$30358$new_n3186 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[3][20] yv[3][17] $abc$30358$new_n3187 +00 1 +11 1 +.names xv[3][20] yv[3][16] $abc$30358$new_n3188 +01 1 +10 1 +.names xv[3][20] yv[3][16] yv[3][17] $abc$30358$new_n3190 $abc$30358$new_n3189 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[3][18] yv[3][14] xv[3][19] yv[3][15] $abc$30358$new_n3191 $abc$30358$new_n3190 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][16] yv[3][12] xv[3][17] yv[3][13] $abc$30358$new_n3192 $abc$30358$new_n3191 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][14] yv[3][10] xv[3][15] yv[3][11] $abc$30358$new_n3193 $abc$30358$new_n3192 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][12] yv[3][8] xv[3][13] yv[3][9] $abc$30358$new_n3194 $abc$30358$new_n3193 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][10] yv[3][6] xv[3][11] yv[3][7] $abc$30358$new_n3195 $abc$30358$new_n3194 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][4] xv[3][9] yv[3][5] $abc$30358$new_n3196 $abc$30358$new_n3195 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][2] xv[3][7] yv[3][3] $abc$30358$new_n3197 $abc$30358$new_n3196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][0] xv[3][5] yv[3][1] $abc$30358$new_n3197 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce $abc$30358$new_n3199 yv[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26397 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][20] yv[3][18] $abc$30358$new_n3189 $abc$30358$new_n3170 $abc$30358$new_n3199 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3201 $abc$30358$new_n3187 yv[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26399 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[3][20] xv[3][20] yv[3][16] $abc$30358$new_n3190 $abc$30358$new_n3202 $abc$30358$new_n3201 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][19] yv[3][15] $abc$30358$new_n3172 $abc$30358$new_n3202 +001 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3204 yv[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26401 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3188 $abc$30358$new_n3190 $abc$30358$new_n3202 $abc$30358$new_n3204 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][19] yv[3][15] $abc$30358$new_n3206 yv[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26403 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][18] yv[3][14] $abc$30358$new_n3191 $abc$30358$new_n3172 $abc$30358$new_n3206 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[3][18] yv[3][14] $abc$30358$new_n3208 yv[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26405 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][17] yv[3][13] $abc$30358$new_n3173 $abc$30358$new_n3191 $abc$30358$new_n3208 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[3][17] yv[3][13] $abc$30358$new_n3210 yv[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26407 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] xv[3][16] yv[3][12] $abc$30358$new_n3192 $abc$30358$new_n3173 $abc$30358$new_n3210 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][16] yv[3][12] $abc$30358$new_n3212 yv[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26409 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3192 $abc$30358$new_n3185 $abc$30358$new_n3186 $abc$30358$new_n3174 $abc$30358$new_n3212 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[3][15] yv[3][11] $abc$30358$new_n3214 yv[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26411 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][10] xv[3][14] $abc$30358$new_n3193 $abc$30358$new_n3174 $abc$30358$new_n3214 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3183 $abc$30358$new_n3216 yv[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26413 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[3][20] xv[3][13] yv[3][9] $abc$30358$new_n3218 $abc$30358$new_n3217 $abc$30358$new_n3216 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3184 $abc$30358$new_n3175 $abc$30358$new_n3217 +00 1 +.names xv[3][12] yv[3][8] $abc$30358$new_n3194 $abc$30358$new_n3218 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3220 yv[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26415 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][13] yv[3][9] $abc$30358$new_n3218 $abc$30358$new_n3217 $abc$30358$new_n3220 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3222 yv[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26417 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3179 $abc$30358$new_n3194 $abc$30358$new_n3223 $abc$30358$new_n3222 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n3180 $abc$30358$new_n3182 $abc$30358$new_n3176 $abc$30358$new_n3181 $abc$30358$new_n3223 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce xv[3][11] yv[3][7] $abc$30358$new_n3225 yv[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][6] xv[3][10] $abc$30358$new_n3195 $abc$30358$new_n3176 $abc$30358$new_n3225 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3227 yv[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26421 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] $abc$30358$new_n3181 $abc$30358$new_n3195 $abc$30358$new_n3176 $abc$30358$new_n3227 +0001 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[3][9] yv[3][5] $abc$30358$new_n3229 yv[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][4] xv[3][8] $abc$30358$new_n3196 $abc$30358$new_n3177 $abc$30358$new_n3229 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3231 yv[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26425 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][8] yv[3][4] $abc$30358$new_n3196 $abc$30358$new_n3177 $abc$30358$new_n3231 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][7] yv[3][3] $abc$30358$new_n3233 yv[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26427 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] yv[3][2] xv[3][6] $abc$30358$new_n3197 $abc$30358$new_n3178 $abc$30358$new_n3233 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[3][6] yv[3][2] $abc$30358$new_n3235 yv[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26429 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3178 $abc$30358$new_n3197 $abc$30358$new_n3235 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3237 yv[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26431 +001 1 +011 1 +110 1 +111 1 +.names xv[3][5] yv[3][1] yv[3][20] yv[3][0] xv[3][4] $abc$30358$new_n3237 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[3][4] yv[3][0] yv[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26433 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][19] $abc$30358$new_n3249 $abc$30358$new_n3240 xv[4][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26435 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[3][20] xv[3][17] xv[3][18] $abc$30358$new_n3241 xv[3][16] $abc$30358$new_n3240 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names xv[3][14] yv[3][18] xv[3][15] yv[3][19] $abc$30358$new_n3242 $abc$30358$new_n3241 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][12] yv[3][16] xv[3][13] yv[3][17] $abc$30358$new_n3243 $abc$30358$new_n3242 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][10] yv[3][14] xv[3][11] yv[3][15] $abc$30358$new_n3244 $abc$30358$new_n3243 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][8] yv[3][12] xv[3][9] yv[3][13] $abc$30358$new_n3245 $abc$30358$new_n3244 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][6] yv[3][10] xv[3][7] yv[3][11] $abc$30358$new_n3246 $abc$30358$new_n3245 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[3][4] yv[3][8] xv[3][5] yv[3][9] $abc$30358$new_n3247 $abc$30358$new_n3246 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[3][2] yv[3][6] xv[3][3] yv[3][7] $abc$30358$new_n3248 $abc$30358$new_n3247 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[3][0] yv[3][4] xv[3][1] yv[3][5] $abc$30358$new_n3248 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[3][20] xv[3][16] xv[3][17] xv[3][18] $abc$30358$new_n3250 $abc$30358$new_n3249 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names yv[3][18] xv[3][14] xv[3][15] yv[3][19] $abc$30358$new_n3251 $abc$30358$new_n3250 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][16] xv[3][12] xv[3][13] yv[3][17] $abc$30358$new_n3252 $abc$30358$new_n3251 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[3][10] xv[3][11] yv[3][14] yv[3][15] $abc$30358$new_n3253 $abc$30358$new_n3252 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[3][12] xv[3][8] xv[3][9] yv[3][13] $abc$30358$new_n3254 $abc$30358$new_n3253 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][10] xv[3][6] xv[3][7] yv[3][11] $abc$30358$new_n3255 $abc$30358$new_n3254 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][8] xv[3][4] xv[3][5] yv[3][9] $abc$30358$new_n3256 $abc$30358$new_n3255 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[3][6] xv[3][2] xv[3][3] yv[3][7] $abc$30358$new_n3257 $abc$30358$new_n3256 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[3][4] xv[3][0] xv[3][1] yv[3][5] $abc$30358$new_n3257 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[3][17] xv[3][16] $abc$30358$new_n3262 xv[4][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26439 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3241 $abc$30358$new_n3250 $abc$30358$new_n3262 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[3][16] $abc$30358$new_n3262 xv[4][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26441 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[3][15] yv[3][19] $abc$30358$new_n3265 xv[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26443 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][18] xv[3][14] $abc$30358$new_n3251 $abc$30358$new_n3242 $abc$30358$new_n3265 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3267 xv[4][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26445 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][14] yv[3][18] $abc$30358$new_n3251 $abc$30358$new_n3242 $abc$30358$new_n3267 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][13] yv[3][17] $abc$30358$new_n3269 xv[4][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26447 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][16] xv[3][12] $abc$30358$new_n3252 $abc$30358$new_n3243 $abc$30358$new_n3269 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][12] yv[3][16] $abc$30358$new_n3271 xv[4][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26449 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3243 $abc$30358$new_n3252 $abc$30358$new_n3271 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3277 xv[4][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26453 +001 1 +011 1 +110 1 +111 1 +.names yv[3][20] xv[3][10] yv[3][14] $abc$30358$new_n3253 $abc$30358$new_n3244 $abc$30358$new_n3277 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[3][9] yv[3][13] $abc$30358$new_n3279 xv[4][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][12] xv[3][8] $abc$30358$new_n3254 $abc$30358$new_n3245 $abc$30358$new_n3279 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3281 xv[4][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26457 +001 1 +011 1 +100 1 +101 1 +.names yv[3][20] xv[3][8] yv[3][12] $abc$30358$new_n3254 $abc$30358$new_n3245 $abc$30358$new_n3281 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[3][7] yv[3][11] $abc$30358$new_n3283 xv[4][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26459 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][10] xv[3][6] $abc$30358$new_n3255 $abc$30358$new_n3246 $abc$30358$new_n3283 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][6] yv[3][10] $abc$30358$new_n3285 xv[4][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26461 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3246 $abc$30358$new_n3255 $abc$30358$new_n3285 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[3][5] yv[3][9] $abc$30358$new_n3287 xv[4][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26463 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] yv[3][8] xv[3][4] $abc$30358$new_n3256 $abc$30358$new_n3247 $abc$30358$new_n3287 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][4] yv[3][8] $abc$30358$new_n3289 xv[4][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26465 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] $abc$30358$new_n3247 $abc$30358$new_n3256 $abc$30358$new_n3289 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[3][3] yv[3][7] $abc$30358$new_n3291 xv[4][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26467 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] xv[3][2] yv[3][6] $abc$30358$new_n3257 $abc$30358$new_n3248 $abc$30358$new_n3291 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[3][2] yv[3][6] $abc$30358$new_n3293 xv[4][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26469 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[3][20] $abc$30358$new_n3248 $abc$30358$new_n3257 $abc$30358$new_n3293 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3295 xv[4][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26471 +001 1 +011 1 +110 1 +111 1 +.names xv[3][1] yv[3][5] yv[3][20] xv[3][0] yv[3][4] $abc$30358$new_n3295 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[3][0] yv[3][4] xv[4][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26473 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3298 ph[4][19] ph[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26475 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[4][18] $abc$30358$new_n3299 ph[4][17] $abc$30358$new_n3307 $abc$30358$new_n3298 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names yv[4][20] $abc$30358$new_n3300 ph[4][17] $abc$30358$new_n3299 +110 1 +.names $abc$30358$new_n3301 ph[4][16] $abc$30358$new_n3300 +10 1 +.names $abc$30358$new_n3302 ph[4][15] $abc$30358$new_n3301 +10 1 +.names ph[4][14] ph[4][13] ph[4][12] $abc$30358$new_n3303 $abc$30358$new_n3302 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[4][11] ph[4][10] $abc$30358$new_n3304 ph[4][8] ph[4][9] $abc$30358$new_n3303 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[4][7] ph[4][6] ph[4][5] $abc$30358$new_n3305 $abc$30358$new_n3304 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][4] $abc$30358$new_n3306 $abc$30358$new_n3305 +11 1 +.names ph[4][3] ph[4][2] ph[4][1] $abc$30358$new_n3306 +101 1 +110 1 +111 1 +.names $abc$30358$new_n3308 ph[4][16] yv[4][20] $abc$30358$new_n3307 +110 1 +.names ph[4][15] $abc$30358$new_n3309 $abc$30358$new_n3308 +11 1 +.names ph[4][14] ph[4][13] ph[4][12] $abc$30358$new_n3310 $abc$30358$new_n3309 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[4][11] ph[4][9] ph[4][10] ph[4][8] $abc$30358$new_n3311 $abc$30358$new_n3310 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[4][7] ph[4][6] $abc$30358$new_n3312 ph[4][5] $abc$30358$new_n3311 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n3313 ph[4][4] $abc$30358$new_n3312 +10 1 +.names ph[4][3] ph[4][2] ph[4][1] $abc$30358$new_n3313 +000 1 +001 1 +010 1 +.names i_ce $abc$30358$new_n3315 ph[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26477 +001 1 +011 1 +110 1 +111 1 +.names ph[4][18] $abc$30358$new_n3299 ph[4][17] $abc$30358$new_n3307 $abc$30358$new_n3315 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names i_ce $abc$30358$new_n3317 ph[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26479 +001 1 +011 1 +110 1 +111 1 +.names ph[4][17] $abc$30358$new_n3307 yv[4][20] $abc$30358$new_n3300 $abc$30358$new_n3317 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$30358$new_n3319 ph[5][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26481 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[4][16] yv[4][20] $abc$30358$new_n3308 $abc$30358$new_n3301 $abc$30358$new_n3319 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3321 ph[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26483 +001 1 +011 1 +110 1 +111 1 +.names ph[4][15] yv[4][20] $abc$30358$new_n3309 $abc$30358$new_n3302 $abc$30358$new_n3321 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n3323 ph[4][14] ph[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26485 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[4][20] ph[4][13] ph[4][12] $abc$30358$new_n3303 $abc$30358$new_n3310 $abc$30358$new_n3323 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3325 ph[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26487 +001 1 +011 1 +110 1 +111 1 +.names ph[4][13] yv[4][20] ph[4][12] $abc$30358$new_n3310 $abc$30358$new_n3303 $abc$30358$new_n3325 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3327 ph[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26489 +001 1 +011 1 +110 1 +111 1 +.names ph[4][12] yv[4][20] $abc$30358$new_n3310 $abc$30358$new_n3303 $abc$30358$new_n3327 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3329 ph[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26491 +001 1 +011 1 +110 1 +111 1 +.names ph[4][10] ph[4][11] $abc$30358$new_n3331 $abc$30358$new_n3330 $abc$30358$new_n3329 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[4][20] ph[4][8] ph[4][9] $abc$30358$new_n3304 $abc$30358$new_n3330 +1000 1 +.names ph[4][9] ph[4][8] yv[4][20] $abc$30358$new_n3311 $abc$30358$new_n3331 +1100 1 +.names i_ce ph[4][10] $abc$30358$new_n3331 $abc$30358$new_n3330 ph[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26493 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3334 ph[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26495 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] ph[4][9] ph[4][8] $abc$30358$new_n3311 $abc$30358$new_n3304 $abc$30358$new_n3334 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3336 ph[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26497 +001 1 +011 1 +100 1 +101 1 +.names ph[4][8] yv[4][20] $abc$30358$new_n3311 $abc$30358$new_n3304 $abc$30358$new_n3336 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[4][7] $abc$30358$new_n3338 ph[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26499 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] ph[4][5] ph[4][6] $abc$30358$new_n3305 $abc$30358$new_n3312 $abc$30358$new_n3338 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3340 ph[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26501 +001 1 +011 1 +110 1 +111 1 +.names ph[4][6] yv[4][20] ph[4][5] $abc$30358$new_n3312 $abc$30358$new_n3305 $abc$30358$new_n3340 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names i_ce ph[4][5] $abc$30358$new_n3342 ph[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26503 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] ph[4][4] $abc$30358$new_n3306 $abc$30358$new_n3313 $abc$30358$new_n3342 +0001 1 +0011 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n3344 ph[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26505 +001 1 +011 1 +110 1 +111 1 +.names ph[4][4] yv[4][20] $abc$30358$new_n3313 $abc$30358$new_n3306 $abc$30358$new_n3344 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n3346 ph[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26507 +001 1 +011 1 +110 1 +111 1 +.names ph[4][3] yv[4][20] ph[4][1] ph[4][2] $abc$30358$new_n3346 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[4][20] ph[4][1] ph[4][2] ph[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26509 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[4][1] ph[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26511 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[4][0] ph[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26513 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[4][20] yv[4][19] $abc$30358$new_n3351 yv[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26515 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][18] xv[4][20] $abc$30358$new_n3363 $abc$30358$new_n3352 $abc$30358$new_n3351 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[4][20] $abc$30358$new_n3353 yv[4][15] yv[4][16] yv[4][17] $abc$30358$new_n3352 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][18] xv[4][19] yv[4][13] yv[4][14] $abc$30358$new_n3354 $abc$30358$new_n3353 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][17] yv[4][12] $abc$30358$new_n3362 $abc$30358$new_n3355 $abc$30358$new_n3361 $abc$30358$new_n3354 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][14] yv[4][9] xv[4][15] yv[4][10] $abc$30358$new_n3356 $abc$30358$new_n3355 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names xv[4][13] yv[4][8] $abc$30358$new_n3357 $abc$30358$new_n3356 +000 1 +100 1 +101 1 +110 1 +.names yv[4][6] xv[4][11] xv[4][12] yv[4][7] $abc$30358$new_n3358 $abc$30358$new_n3357 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[4][9] xv[4][10] yv[4][4] yv[4][5] $abc$30358$new_n3359 $abc$30358$new_n3358 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][7] xv[4][8] yv[4][2] yv[4][3] $abc$30358$new_n3360 $abc$30358$new_n3359 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][5] xv[4][6] yv[4][0] yv[4][1] $abc$30358$new_n3360 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[4][16] yv[4][11] $abc$30358$new_n3361 +10 1 +.names yv[4][11] xv[4][16] yv[4][10] xv[4][15] $abc$30358$new_n3362 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names xv[4][20] $abc$30358$new_n3364 yv[4][15] yv[4][16] yv[4][17] $abc$30358$new_n3363 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[4][19] yv[4][14] $abc$30358$new_n3365 $abc$30358$new_n3364 +000 1 +001 1 +011 1 +101 1 +.names xv[4][17] yv[4][12] xv[4][18] yv[4][13] $abc$30358$new_n3366 $abc$30358$new_n3365 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][15] yv[4][10] xv[4][16] yv[4][11] $abc$30358$new_n3367 $abc$30358$new_n3366 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][13] yv[4][8] xv[4][14] yv[4][9] $abc$30358$new_n3368 $abc$30358$new_n3367 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][11] yv[4][6] xv[4][12] yv[4][7] $abc$30358$new_n3369 $abc$30358$new_n3368 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][9] yv[4][4] xv[4][10] yv[4][5] $abc$30358$new_n3370 $abc$30358$new_n3369 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][7] yv[4][2] xv[4][8] yv[4][3] $abc$30358$new_n3371 $abc$30358$new_n3370 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][5] yv[4][0] xv[4][6] yv[4][1] $abc$30358$new_n3371 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[4][20] yv[4][18] $abc$30358$new_n3373 yv[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26517 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3352 $abc$30358$new_n3363 $abc$30358$new_n3373 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[4][20] yv[4][17] $abc$30358$new_n3375 yv[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26519 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][16] yv[4][20] $abc$30358$new_n3379 xv[4][20] $abc$30358$new_n3375 +0000 1 +0001 1 +0011 1 +0101 1 +1001 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[4][20] yv[4][16] $abc$30358$new_n3379 yv[5][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26521 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][15] xv[4][20] $abc$30358$new_n3364 $abc$30358$new_n3353 $abc$30358$new_n3379 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3381 yv[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26523 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][20] yv[4][15] $abc$30358$new_n3364 $abc$30358$new_n3353 $abc$30358$new_n3381 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n3383 yv[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26525 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][19] yv[4][14] $abc$30358$new_n3365 $abc$30358$new_n3384 $abc$30358$new_n3383 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[4][18] yv[4][13] $abc$30358$new_n3354 $abc$30358$new_n3384 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[4][18] yv[4][13] $abc$30358$new_n3386 yv[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26527 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][17] yv[4][12] $abc$30358$new_n3366 $abc$30358$new_n3387 $abc$30358$new_n3386 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3361 $abc$30358$new_n3355 $abc$30358$new_n3362 $abc$30358$new_n3387 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n3389 yv[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26529 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][17] yv[4][12] $abc$30358$new_n3366 $abc$30358$new_n3387 $abc$30358$new_n3389 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][16] yv[4][11] $abc$30358$new_n3391 yv[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26531 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][10] xv[4][15] $abc$30358$new_n3367 $abc$30358$new_n3355 $abc$30358$new_n3391 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][15] yv[4][10] $abc$30358$new_n3393 yv[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26533 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][14] yv[4][9] $abc$30358$new_n3356 $abc$30358$new_n3367 $abc$30358$new_n3393 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce xv[4][14] yv[4][9] $abc$30358$new_n3395 yv[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26535 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][8] xv[4][13] $abc$30358$new_n3368 $abc$30358$new_n3357 $abc$30358$new_n3395 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3397 yv[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26537 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][13] yv[4][8] $abc$30358$new_n3368 $abc$30358$new_n3357 $abc$30358$new_n3397 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][12] yv[4][7] $abc$30358$new_n3399 yv[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26539 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][6] xv[4][11] $abc$30358$new_n3369 $abc$30358$new_n3358 $abc$30358$new_n3399 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3401 yv[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26541 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][11] yv[4][6] $abc$30358$new_n3369 $abc$30358$new_n3358 $abc$30358$new_n3401 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][10] yv[4][5] $abc$30358$new_n3403 yv[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26543 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][4] xv[4][9] $abc$30358$new_n3370 $abc$30358$new_n3359 $abc$30358$new_n3403 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3405 yv[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26545 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][9] yv[4][4] $abc$30358$new_n3370 $abc$30358$new_n3359 $abc$30358$new_n3405 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][8] yv[4][3] $abc$30358$new_n3407 yv[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26547 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] yv[4][2] xv[4][7] $abc$30358$new_n3371 $abc$30358$new_n3360 $abc$30358$new_n3407 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[4][7] yv[4][2] $abc$30358$new_n3409 yv[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26549 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3360 $abc$30358$new_n3371 $abc$30358$new_n3409 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3411 yv[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26551 +001 1 +011 1 +110 1 +111 1 +.names xv[4][6] yv[4][1] yv[4][20] yv[4][0] xv[4][5] $abc$30358$new_n3411 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[4][5] yv[4][0] yv[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26553 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[4][19] $abc$30358$new_n3414 xv[5][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26555 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3415 $abc$30358$new_n3424 yv[4][20] $abc$30358$new_n3414 +000 1 +010 1 +011 1 +.names yv[4][20] xv[4][16] xv[4][17] xv[4][18] $abc$30358$new_n3416 $abc$30358$new_n3415 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names xv[4][15] xv[4][14] yv[4][19] $abc$30358$new_n3417 $abc$30358$new_n3416 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1101 1 +.names xv[4][12] yv[4][17] xv[4][13] yv[4][18] $abc$30358$new_n3418 $abc$30358$new_n3417 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][10] yv[4][15] xv[4][11] yv[4][16] $abc$30358$new_n3419 $abc$30358$new_n3418 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][8] yv[4][13] xv[4][9] yv[4][14] $abc$30358$new_n3420 $abc$30358$new_n3419 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][6] yv[4][11] xv[4][7] yv[4][12] $abc$30358$new_n3421 $abc$30358$new_n3420 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[4][4] yv[4][9] xv[4][5] yv[4][10] $abc$30358$new_n3422 $abc$30358$new_n3421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names xv[4][2] yv[4][7] xv[4][3] yv[4][8] $abc$30358$new_n3423 $abc$30358$new_n3422 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[4][0] yv[4][5] xv[4][1] yv[4][6] $abc$30358$new_n3423 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[4][18] xv[4][16] xv[4][17] $abc$30358$new_n3425 $abc$30358$new_n3424 +1110 1 +.names xv[4][15] xv[4][14] yv[4][19] $abc$30358$new_n3426 $abc$30358$new_n3425 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +1110 1 +.names xv[4][12] xv[4][13] yv[4][17] yv[4][18] $abc$30358$new_n3427 $abc$30358$new_n3426 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[4][10] xv[4][11] yv[4][15] yv[4][16] $abc$30358$new_n3428 $abc$30358$new_n3427 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[4][13] xv[4][8] xv[4][9] yv[4][14] $abc$30358$new_n3429 $abc$30358$new_n3428 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][11] xv[4][6] xv[4][7] yv[4][12] $abc$30358$new_n3430 $abc$30358$new_n3429 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][9] xv[4][4] xv[4][5] yv[4][10] $abc$30358$new_n3431 $abc$30358$new_n3430 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[4][7] xv[4][2] xv[4][3] yv[4][8] $abc$30358$new_n3432 $abc$30358$new_n3431 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[4][5] xv[4][0] xv[4][1] yv[4][6] $abc$30358$new_n3432 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce xv[4][17] xv[4][16] $abc$30358$new_n3437 xv[5][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26559 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3416 $abc$30358$new_n3425 $abc$30358$new_n3437 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[4][16] $abc$30358$new_n3437 xv[5][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26561 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[4][20] xv[4][15] $abc$30358$new_n3440 xv[5][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26563 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][19] xv[4][14] $abc$30358$new_n3426 $abc$30358$new_n3417 $abc$30358$new_n3440 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][14] yv[4][19] $abc$30358$new_n3442 xv[5][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26565 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3417 $abc$30358$new_n3426 $abc$30358$new_n3442 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[4][12] yv[4][17] $abc$30358$new_n3448 xv[5][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26569 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3418 $abc$30358$new_n3427 $abc$30358$new_n3448 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3454 xv[5][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26573 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][10] yv[4][15] $abc$30358$new_n3428 $abc$30358$new_n3419 $abc$30358$new_n3454 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][9] yv[4][14] $abc$30358$new_n3456 xv[5][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26575 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][13] xv[4][8] $abc$30358$new_n3429 $abc$30358$new_n3420 $abc$30358$new_n3456 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3458 xv[5][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26577 +001 1 +011 1 +100 1 +101 1 +.names yv[4][20] xv[4][8] yv[4][13] $abc$30358$new_n3429 $abc$30358$new_n3420 $abc$30358$new_n3458 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[4][7] yv[4][12] $abc$30358$new_n3460 xv[5][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26579 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][11] xv[4][6] $abc$30358$new_n3430 $abc$30358$new_n3421 $abc$30358$new_n3460 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3462 xv[5][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26581 +001 1 +011 1 +110 1 +111 1 +.names yv[4][20] xv[4][6] yv[4][11] $abc$30358$new_n3430 $abc$30358$new_n3421 $abc$30358$new_n3462 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[4][5] yv[4][10] $abc$30358$new_n3464 xv[5][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26583 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] yv[4][9] xv[4][4] $abc$30358$new_n3431 $abc$30358$new_n3422 $abc$30358$new_n3464 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][4] yv[4][9] $abc$30358$new_n3466 xv[5][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26585 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] $abc$30358$new_n3422 $abc$30358$new_n3431 $abc$30358$new_n3466 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[4][3] yv[4][8] $abc$30358$new_n3468 xv[5][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26587 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] xv[4][2] yv[4][7] $abc$30358$new_n3432 $abc$30358$new_n3423 $abc$30358$new_n3468 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[4][2] yv[4][7] $abc$30358$new_n3470 xv[5][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26589 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[4][20] $abc$30358$new_n3423 $abc$30358$new_n3432 $abc$30358$new_n3470 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3472 xv[5][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26591 +001 1 +011 1 +110 1 +111 1 +.names xv[4][1] yv[4][6] yv[4][20] xv[4][0] yv[4][5] $abc$30358$new_n3472 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[4][0] yv[4][5] xv[5][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26593 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[5][19] $abc$30358$new_n3475 ph[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26595 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[5][18] $abc$30358$new_n3476 $abc$30358$new_n3484 $abc$30358$new_n3475 +010 1 +011 1 +101 1 +111 1 +.names yv[5][20] $abc$30358$new_n3477 ph[5][17] $abc$30358$new_n3476 +110 1 +.names $abc$30358$new_n3478 ph[5][16] $abc$30358$new_n3477 +10 1 +.names $abc$30358$new_n3479 ph[5][15] $abc$30358$new_n3478 +10 1 +.names ph[5][13] ph[5][14] $abc$30358$new_n3480 $abc$30358$new_n3479 +000 1 +.names ph[5][12] $abc$30358$new_n3481 ph[5][11] $abc$30358$new_n3480 +101 1 +110 1 +111 1 +.names ph[5][10] $abc$30358$new_n3482 ph[5][9] $abc$30358$new_n3481 +100 1 +101 1 +111 1 +.names ph[5][8] ph[5][7] $abc$30358$new_n3483 ph[5][6] $abc$30358$new_n3482 +0000 1 +0010 1 +0011 1 +.names ph[5][5] ph[5][3] ph[5][4] ph[5][1] ph[5][2] $abc$30358$new_n3483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[5][17] $abc$30358$new_n3485 $abc$30358$new_n3484 +11 1 +.names $abc$30358$new_n3486 ph[5][16] yv[5][20] $abc$30358$new_n3485 +110 1 +.names ph[5][14] $abc$30358$new_n3487 $abc$30358$new_n3486 +11 1 +.names ph[5][13] ph[5][15] ph[5][12] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3487 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[5][10] $abc$30358$new_n3489 ph[5][9] $abc$30358$new_n3488 +000 1 +001 1 +010 1 +.names ph[5][8] ph[5][7] $abc$30358$new_n3490 ph[5][6] $abc$30358$new_n3489 +1101 1 +1110 1 +1111 1 +.names ph[5][5] ph[5][3] ph[5][4] ph[5][1] ph[5][2] $abc$30358$new_n3490 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[5][18] $abc$30358$new_n3484 $abc$30358$new_n3476 ph[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26597 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3493 ph[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26599 +001 1 +011 1 +110 1 +111 1 +.names ph[5][17] $abc$30358$new_n3485 yv[5][20] $abc$30358$new_n3477 $abc$30358$new_n3493 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$30358$new_n3495 ph[6][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26601 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[5][16] yv[5][20] $abc$30358$new_n3486 $abc$30358$new_n3478 $abc$30358$new_n3495 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3497 ph[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26603 +001 1 +011 1 +110 1 +111 1 +.names ph[5][14] ph[5][15] $abc$30358$new_n3500 $abc$30358$new_n3498 $abc$30358$new_n3497 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3499 ph[5][13] $abc$30358$new_n3498 +10 1 +.names yv[5][20] $abc$30358$new_n3480 $abc$30358$new_n3499 +10 1 +.names ph[5][13] $abc$30358$new_n3501 $abc$30358$new_n3500 +11 1 +.names yv[5][20] ph[5][12] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3501 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[5][14] $abc$30358$new_n3500 $abc$30358$new_n3498 ph[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26605 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[5][13] $abc$30358$new_n3501 $abc$30358$new_n3499 ph[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26607 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3505 ph[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26609 +001 1 +011 1 +110 1 +111 1 +.names ph[5][12] yv[5][20] ph[5][11] $abc$30358$new_n3488 $abc$30358$new_n3481 $abc$30358$new_n3505 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3507 ph[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26611 +001 1 +011 1 +110 1 +111 1 +.names ph[5][11] yv[5][20] $abc$30358$new_n3488 $abc$30358$new_n3481 $abc$30358$new_n3507 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3509 ph[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26613 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][10] ph[5][9] $abc$30358$new_n3511 $abc$30358$new_n3510 $abc$30358$new_n3509 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] ph[5][7] $abc$30358$new_n3483 ph[5][6] $abc$30358$new_n3510 +1000 1 +1010 1 +1011 1 +.names ph[5][7] yv[5][20] $abc$30358$new_n3490 ph[5][6] $abc$30358$new_n3511 +1001 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n3513 ph[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26615 +001 1 +011 1 +100 1 +101 1 +.names ph[5][8] ph[5][9] $abc$30358$new_n3511 $abc$30358$new_n3510 $abc$30358$new_n3513 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[5][8] $abc$30358$new_n3511 $abc$30358$new_n3510 ph[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26617 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3516 ph[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26619 +001 1 +011 1 +110 1 +111 1 +.names ph[5][7] yv[5][20] ph[5][6] $abc$30358$new_n3490 $abc$30358$new_n3483 $abc$30358$new_n3516 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3518 ph[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26621 +001 1 +011 1 +100 1 +101 1 +.names ph[5][6] yv[5][20] $abc$30358$new_n3490 $abc$30358$new_n3483 $abc$30358$new_n3518 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[5][5] $abc$30358$new_n3520 ph[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26623 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[5][20] ph[5][1] ph[5][2] ph[5][3] ph[5][4] $abc$30358$new_n3520 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3522 ph[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26625 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] ph[5][4] ph[5][1] ph[5][2] ph[5][3] $abc$30358$new_n3522 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3524 ph[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26627 +001 1 +011 1 +100 1 +101 1 +.names ph[5][3] yv[5][20] ph[5][1] ph[5][2] $abc$30358$new_n3524 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[5][20] ph[5][1] ph[5][2] ph[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[5][1] ph[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26631 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[5][0] ph[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26633 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[5][20] yv[5][19] $abc$30358$new_n3529 yv[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][18] xv[5][20] $abc$30358$new_n3539 $abc$30358$new_n3530 $abc$30358$new_n3529 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[5][20] $abc$30358$new_n3531 yv[5][16] yv[5][17] $abc$30358$new_n3530 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][20] $abc$30358$new_n3532 yv[5][14] yv[5][15] $abc$30358$new_n3531 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][18] xv[5][19] yv[5][12] yv[5][13] $abc$30358$new_n3533 $abc$30358$new_n3532 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][16] xv[5][17] yv[5][10] yv[5][11] $abc$30358$new_n3534 $abc$30358$new_n3533 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[5][8] xv[5][14] xv[5][15] yv[5][9] $abc$30358$new_n3535 $abc$30358$new_n3534 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][6] xv[5][12] xv[5][13] yv[5][7] $abc$30358$new_n3536 $abc$30358$new_n3535 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[5][10] xv[5][11] yv[5][4] yv[5][5] $abc$30358$new_n3537 $abc$30358$new_n3536 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][2] yv[5][3] $abc$30358$new_n3538 $abc$30358$new_n3537 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[5][6] xv[5][7] yv[5][0] yv[5][1] $abc$30358$new_n3538 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[5][20] yv[5][16] yv[5][17] $abc$30358$new_n3540 $abc$30358$new_n3539 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[5][20] yv[5][14] yv[5][15] $abc$30358$new_n3541 $abc$30358$new_n3540 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[5][18] yv[5][12] xv[5][19] yv[5][13] $abc$30358$new_n3542 $abc$30358$new_n3541 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][16] yv[5][10] xv[5][17] yv[5][11] $abc$30358$new_n3543 $abc$30358$new_n3542 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][14] yv[5][8] xv[5][15] yv[5][9] $abc$30358$new_n3544 $abc$30358$new_n3543 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][12] yv[5][6] xv[5][13] yv[5][7] $abc$30358$new_n3545 $abc$30358$new_n3544 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][10] yv[5][4] xv[5][11] yv[5][5] $abc$30358$new_n3546 $abc$30358$new_n3545 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][8] yv[5][2] xv[5][9] yv[5][3] $abc$30358$new_n3547 $abc$30358$new_n3546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][6] yv[5][0] xv[5][7] yv[5][1] $abc$30358$new_n3547 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[5][20] yv[5][18] $abc$30358$new_n3549 yv[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26637 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3530 $abc$30358$new_n3539 $abc$30358$new_n3549 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[5][20] yv[5][17] $abc$30358$new_n3551 yv[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][20] yv[5][16] $abc$30358$new_n3540 $abc$30358$new_n3531 $abc$30358$new_n3551 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3553 yv[6][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26641 +001 1 +011 1 +100 1 +101 1 +.names yv[5][20] xv[5][20] yv[5][16] $abc$30358$new_n3540 $abc$30358$new_n3531 $abc$30358$new_n3553 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][20] yv[5][15] $abc$30358$new_n3555 yv[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26643 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][20] yv[5][14] $abc$30358$new_n3541 $abc$30358$new_n3532 $abc$30358$new_n3555 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3557 yv[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26645 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][20] yv[5][14] $abc$30358$new_n3541 $abc$30358$new_n3532 $abc$30358$new_n3557 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][19] yv[5][13] $abc$30358$new_n3559 yv[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26647 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][12] xv[5][18] $abc$30358$new_n3542 $abc$30358$new_n3533 $abc$30358$new_n3559 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][18] yv[5][12] $abc$30358$new_n3561 yv[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26649 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3533 $abc$30358$new_n3542 $abc$30358$new_n3561 +010 1 +011 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n3567 yv[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26653 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][16] yv[5][10] $abc$30358$new_n3543 $abc$30358$new_n3534 $abc$30358$new_n3567 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][15] yv[5][9] $abc$30358$new_n3569 yv[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26655 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][8] xv[5][14] $abc$30358$new_n3544 $abc$30358$new_n3535 $abc$30358$new_n3569 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3571 yv[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26657 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][14] yv[5][8] $abc$30358$new_n3544 $abc$30358$new_n3535 $abc$30358$new_n3571 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][13] yv[5][7] $abc$30358$new_n3573 yv[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26659 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][6] xv[5][12] $abc$30358$new_n3545 $abc$30358$new_n3536 $abc$30358$new_n3573 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3575 yv[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26661 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][12] yv[5][6] $abc$30358$new_n3545 $abc$30358$new_n3536 $abc$30358$new_n3575 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][11] yv[5][5] $abc$30358$new_n3577 yv[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26663 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][4] xv[5][10] $abc$30358$new_n3546 $abc$30358$new_n3537 $abc$30358$new_n3577 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3579 yv[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26665 +001 1 +011 1 +110 1 +111 1 +.names yv[5][20] xv[5][10] yv[5][4] $abc$30358$new_n3546 $abc$30358$new_n3537 $abc$30358$new_n3579 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][9] yv[5][3] $abc$30358$new_n3581 yv[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26667 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] yv[5][2] xv[5][8] $abc$30358$new_n3547 $abc$30358$new_n3538 $abc$30358$new_n3581 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[5][8] yv[5][2] $abc$30358$new_n3583 yv[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26669 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3538 $abc$30358$new_n3547 $abc$30358$new_n3583 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3585 yv[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26671 +001 1 +011 1 +110 1 +111 1 +.names xv[5][7] yv[5][1] yv[5][20] yv[5][0] xv[5][6] $abc$30358$new_n3585 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[5][6] yv[5][0] yv[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26673 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[5][14] xv[5][15] $abc$30358$new_n3590 $abc$30358$new_n3589 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[5][12] yv[5][18] xv[5][13] yv[5][19] $abc$30358$new_n3591 $abc$30358$new_n3590 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][10] yv[5][16] xv[5][11] yv[5][17] $abc$30358$new_n3592 $abc$30358$new_n3591 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][9] yv[5][15] $abc$30358$new_n3593 $abc$30358$new_n3592 +000 1 +001 1 +011 1 +101 1 +.names xv[5][7] yv[5][13] xv[5][8] yv[5][14] $abc$30358$new_n3594 $abc$30358$new_n3593 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][5] yv[5][11] xv[5][6] yv[5][12] $abc$30358$new_n3595 $abc$30358$new_n3594 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][3] yv[5][9] xv[5][4] yv[5][10] $abc$30358$new_n3596 $abc$30358$new_n3595 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[5][2] yv[5][8] $abc$30358$new_n3597 $abc$30358$new_n3596 +000 1 +001 1 +011 1 +101 1 +.names xv[5][0] yv[5][6] xv[5][1] yv[5][7] $abc$30358$new_n3597 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$30358$new_n3611 xv[5][14] xv[5][15] $abc$30358$new_n3600 $abc$30358$new_n3599 +1110 1 +.names $abc$30358$new_n3608 $abc$30358$new_n3601 $abc$30358$new_n3600 +10 1 +.names $abc$30358$new_n3602 xv[5][12] yv[5][18] xv[5][13] yv[5][19] $abc$30358$new_n3601 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$30358$new_n3603 xv[5][10] yv[5][16] xv[5][11] yv[5][17] $abc$30358$new_n3602 +10000 1 +10011 1 +11100 1 +11111 1 +.names xv[5][8] yv[5][14] xv[5][9] yv[5][15] $abc$30358$new_n3604 $abc$30358$new_n3603 +00000 1 +00110 1 +11000 1 +11110 1 +.names yv[5][12] xv[5][6] xv[5][7] yv[5][13] $abc$30358$new_n3605 $abc$30358$new_n3604 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][10] xv[5][4] xv[5][5] yv[5][11] $abc$30358$new_n3606 $abc$30358$new_n3605 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][8] xv[5][2] xv[5][3] yv[5][9] $abc$30358$new_n3607 $abc$30358$new_n3606 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[5][6] xv[5][0] xv[5][1] yv[5][7] $abc$30358$new_n3607 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[5][18] xv[5][12] xv[5][13] yv[5][19] $abc$30358$new_n3609 $abc$30358$new_n3608 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[5][16] xv[5][10] xv[5][11] yv[5][17] $abc$30358$new_n3610 $abc$30358$new_n3609 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[5][8] xv[5][9] yv[5][14] yv[5][15] $abc$30358$new_n3610 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[5][20] xv[5][16] xv[5][17] $abc$30358$new_n3611 +000 1 +111 1 +.names i_ce $abc$30358$new_n3616 xv[6][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26679 +001 1 +011 1 +110 1 +111 1 +.names xv[5][17] yv[5][20] xv[5][16] $abc$30358$new_n3617 $abc$30358$new_n3589 $abc$30358$new_n3616 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[5][14] xv[5][15] $abc$30358$new_n3600 $abc$30358$new_n3617 +110 1 +.names $abc$30358$new_n3619 i_ce xv[6][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26681 +001 1 +010 1 +011 1 +.names i_ce yv[5][20] xv[5][16] $abc$30358$new_n3617 $abc$30358$new_n3589 $abc$30358$new_n3619 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3621 xv[6][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26683 +001 1 +011 1 +110 1 +111 1 +.names xv[5][15] yv[5][20] xv[5][14] $abc$30358$new_n3600 $abc$30358$new_n3590 $abc$30358$new_n3621 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n3623 i_ce xv[6][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26685 +001 1 +010 1 +011 1 +.names i_ce yv[5][20] xv[5][14] $abc$30358$new_n3600 $abc$30358$new_n3590 $abc$30358$new_n3623 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][13] yv[5][19] $abc$30358$new_n3625 xv[6][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26687 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][18] xv[5][12] $abc$30358$new_n3626 $abc$30358$new_n3591 $abc$30358$new_n3625 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n3609 $abc$30358$new_n3602 $abc$30358$new_n3626 +10 1 +.names i_ce $abc$30358$new_n3628 xv[6][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26689 +001 1 +011 1 +100 1 +101 1 +.names yv[5][20] xv[5][12] yv[5][18] $abc$30358$new_n3626 $abc$30358$new_n3591 $abc$30358$new_n3628 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][11] yv[5][17] $abc$30358$new_n3630 xv[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26691 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[5][10] yv[5][20] $abc$30358$new_n3631 yv[5][16] $abc$30358$new_n3592 $abc$30358$new_n3630 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names yv[5][20] $abc$30358$new_n3603 $abc$30358$new_n3610 $abc$30358$new_n3631 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3633 xv[6][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26693 +001 1 +011 1 +110 1 +111 1 +.names xv[5][10] yv[5][16] $abc$30358$new_n3631 yv[5][20] $abc$30358$new_n3592 $abc$30358$new_n3633 +00000 1 +00010 1 +00011 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names i_ce xv[5][9] yv[5][15] $abc$30358$new_n3635 xv[6][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] xv[5][8] yv[5][14] $abc$30358$new_n3604 $abc$30358$new_n3593 $abc$30358$new_n3635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[5][8] yv[5][14] $abc$30358$new_n3637 xv[6][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26697 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][7] yv[5][13] $abc$30358$new_n3594 $abc$30358$new_n3604 $abc$30358$new_n3637 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][7] yv[5][13] $abc$30358$new_n3639 xv[6][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26699 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][12] xv[5][6] $abc$30358$new_n3605 $abc$30358$new_n3594 $abc$30358$new_n3639 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][6] yv[5][12] $abc$30358$new_n3641 xv[6][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26701 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][5] yv[5][11] $abc$30358$new_n3595 $abc$30358$new_n3605 $abc$30358$new_n3641 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][5] yv[5][11] $abc$30358$new_n3643 xv[6][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26703 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] yv[5][10] xv[5][4] $abc$30358$new_n3606 $abc$30358$new_n3595 $abc$30358$new_n3643 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][4] yv[5][10] $abc$30358$new_n3645 xv[6][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26705 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][3] yv[5][9] $abc$30358$new_n3596 $abc$30358$new_n3606 $abc$30358$new_n3645 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[5][3] yv[5][9] $abc$30358$new_n3647 xv[6][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26707 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] xv[5][2] yv[5][8] $abc$30358$new_n3607 $abc$30358$new_n3597 $abc$30358$new_n3647 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[5][2] yv[5][8] $abc$30358$new_n3649 xv[6][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26709 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3597 $abc$30358$new_n3607 $abc$30358$new_n3649 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3651 xv[6][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26711 +001 1 +011 1 +110 1 +111 1 +.names xv[5][1] yv[5][7] yv[5][20] xv[5][0] yv[5][6] $abc$30358$new_n3651 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[5][0] yv[5][6] xv[6][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26713 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3654 ph[6][19] ph[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26715 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[6][17] ph[6][18] $abc$30358$new_n3655 $abc$30358$new_n3663 $abc$30358$new_n3654 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names yv[6][20] $abc$30358$new_n3656 ph[6][16] $abc$30358$new_n3655 +110 1 +.names $abc$30358$new_n3657 ph[6][15] $abc$30358$new_n3656 +10 1 +.names $abc$30358$new_n3658 ph[6][14] $abc$30358$new_n3657 +10 1 +.names ph[6][12] ph[6][13] $abc$30358$new_n3659 $abc$30358$new_n3658 +000 1 +.names ph[6][11] $abc$30358$new_n3660 ph[6][10] $abc$30358$new_n3659 +101 1 +110 1 +111 1 +.names ph[6][9] $abc$30358$new_n3661 ph[6][8] $abc$30358$new_n3660 +100 1 +101 1 +111 1 +.names ph[6][7] ph[6][6] $abc$30358$new_n3662 ph[6][5] $abc$30358$new_n3661 +0000 1 +0010 1 +0011 1 +.names ph[6][4] ph[6][2] ph[6][3] ph[6][0] ph[6][1] $abc$30358$new_n3662 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names ph[6][16] $abc$30358$new_n3664 $abc$30358$new_n3663 +11 1 +.names $abc$30358$new_n3665 ph[6][15] yv[6][20] $abc$30358$new_n3664 +110 1 +.names ph[6][13] $abc$30358$new_n3666 $abc$30358$new_n3665 +11 1 +.names ph[6][12] ph[6][14] ph[6][11] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3666 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[6][9] $abc$30358$new_n3668 ph[6][8] $abc$30358$new_n3667 +000 1 +001 1 +010 1 +.names ph[6][7] ph[6][6] $abc$30358$new_n3669 ph[6][5] $abc$30358$new_n3668 +1101 1 +1110 1 +1111 1 +.names ph[6][4] ph[6][2] ph[6][3] ph[6][0] ph[6][1] $abc$30358$new_n3669 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3671 ph[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26717 +001 1 +011 1 +110 1 +111 1 +.names ph[6][17] ph[6][18] $abc$30358$new_n3663 $abc$30358$new_n3655 $abc$30358$new_n3671 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][17] $abc$30358$new_n3663 $abc$30358$new_n3655 ph[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3674 ph[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26721 +001 1 +011 1 +100 1 +101 1 +.names ph[6][16] $abc$30358$new_n3664 yv[6][20] $abc$30358$new_n3656 $abc$30358$new_n3674 +0000 1 +0001 1 +0010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3676 ph[7][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26723 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[6][15] yv[6][20] $abc$30358$new_n3665 $abc$30358$new_n3657 $abc$30358$new_n3676 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3678 ph[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26725 +001 1 +011 1 +110 1 +111 1 +.names ph[6][13] ph[6][14] $abc$30358$new_n3681 $abc$30358$new_n3679 $abc$30358$new_n3678 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n3680 ph[6][12] $abc$30358$new_n3679 +10 1 +.names yv[6][20] $abc$30358$new_n3659 $abc$30358$new_n3680 +10 1 +.names ph[6][12] $abc$30358$new_n3682 $abc$30358$new_n3681 +11 1 +.names yv[6][20] ph[6][11] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3682 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_ce ph[6][13] $abc$30358$new_n3681 $abc$30358$new_n3679 ph[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26727 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[6][12] $abc$30358$new_n3682 $abc$30358$new_n3680 ph[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26729 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3686 ph[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26731 +001 1 +011 1 +110 1 +111 1 +.names ph[6][11] yv[6][20] ph[6][10] $abc$30358$new_n3667 $abc$30358$new_n3660 $abc$30358$new_n3686 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3688 ph[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26733 +001 1 +011 1 +110 1 +111 1 +.names ph[6][10] yv[6][20] $abc$30358$new_n3667 $abc$30358$new_n3660 $abc$30358$new_n3688 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3690 ph[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26735 +001 1 +011 1 +100 1 +101 1 +.names ph[6][7] ph[6][9] ph[6][8] $abc$30358$new_n3692 $abc$30358$new_n3691 $abc$30358$new_n3690 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] ph[6][6] $abc$30358$new_n3662 ph[6][5] $abc$30358$new_n3691 +1000 1 +1010 1 +1011 1 +.names ph[6][6] yv[6][20] $abc$30358$new_n3669 ph[6][5] $abc$30358$new_n3692 +1001 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n3694 ph[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26737 +001 1 +011 1 +110 1 +111 1 +.names ph[6][7] ph[6][8] $abc$30358$new_n3692 $abc$30358$new_n3691 $abc$30358$new_n3694 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[6][7] $abc$30358$new_n3692 $abc$30358$new_n3691 ph[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26739 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3697 ph[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26741 +001 1 +011 1 +110 1 +111 1 +.names ph[6][6] yv[6][20] ph[6][5] $abc$30358$new_n3669 $abc$30358$new_n3662 $abc$30358$new_n3697 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3699 ph[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26743 +001 1 +011 1 +110 1 +111 1 +.names ph[6][5] yv[6][20] $abc$30358$new_n3669 $abc$30358$new_n3662 $abc$30358$new_n3699 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[6][4] $abc$30358$new_n3701 ph[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26745 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] ph[6][0] ph[6][1] ph[6][2] ph[6][3] $abc$30358$new_n3701 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3703 ph[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26747 +001 1 +011 1 +110 1 +111 1 +.names yv[6][20] ph[6][3] ph[6][0] ph[6][1] ph[6][2] $abc$30358$new_n3703 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_ce $abc$30358$new_n3705 ph[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26749 +001 1 +011 1 +100 1 +101 1 +.names ph[6][2] yv[6][20] ph[6][0] ph[6][1] $abc$30358$new_n3705 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[6][20] ph[6][0] ph[6][1] ph[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26751 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[6][0] ph[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26753 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][20] yv[6][19] $abc$30358$new_n3709 yv[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26755 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][18] yv[6][20] $abc$30358$new_n3710 xv[6][20] $abc$30358$new_n3719 $abc$30358$new_n3709 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[6][20] xv[6][20] yv[6][16] yv[6][17] $abc$30358$new_n3711 $abc$30358$new_n3710 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][20] yv[6][14] yv[6][15] $abc$30358$new_n3712 $abc$30358$new_n3711 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][19] yv[6][12] xv[6][20] yv[6][13] $abc$30358$new_n3713 $abc$30358$new_n3712 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][17] yv[6][10] xv[6][18] yv[6][11] $abc$30358$new_n3714 $abc$30358$new_n3713 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][15] yv[6][8] xv[6][16] yv[6][9] $abc$30358$new_n3715 $abc$30358$new_n3714 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][13] yv[6][6] xv[6][14] yv[6][7] $abc$30358$new_n3716 $abc$30358$new_n3715 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][11] yv[6][4] xv[6][12] yv[6][5] $abc$30358$new_n3717 $abc$30358$new_n3716 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][9] yv[6][2] xv[6][10] yv[6][3] $abc$30358$new_n3718 $abc$30358$new_n3717 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][7] yv[6][0] xv[6][8] yv[6][1] $abc$30358$new_n3718 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[6][20] $abc$30358$new_n3720 yv[6][16] yv[6][17] $abc$30358$new_n3719 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[6][20] $abc$30358$new_n3721 yv[6][13] yv[6][14] yv[6][15] $abc$30358$new_n3720 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][18] xv[6][19] yv[6][11] yv[6][12] $abc$30358$new_n3722 $abc$30358$new_n3721 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][17] yv[6][10] $abc$30358$new_n3723 $abc$30358$new_n3722 +000 1 +100 1 +101 1 +110 1 +.names yv[6][8] xv[6][15] xv[6][16] yv[6][9] $abc$30358$new_n3724 $abc$30358$new_n3723 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][6] xv[6][13] xv[6][14] yv[6][7] $abc$30358$new_n3725 $abc$30358$new_n3724 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[6][11] xv[6][12] yv[6][4] yv[6][5] $abc$30358$new_n3726 $abc$30358$new_n3725 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][9] xv[6][10] yv[6][2] yv[6][3] $abc$30358$new_n3727 $abc$30358$new_n3726 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[6][7] xv[6][8] yv[6][0] yv[6][1] $abc$30358$new_n3727 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n3729 yv[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26757 +001 1 +011 1 +110 1 +111 1 +.names xv[6][20] yv[6][18] $abc$30358$new_n3710 $abc$30358$new_n3719 yv[6][20] $abc$30358$new_n3729 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[6][20] yv[6][17] $abc$30358$new_n3731 yv[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26759 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][20] yv[6][16] $abc$30358$new_n3720 $abc$30358$new_n3711 $abc$30358$new_n3731 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3733 yv[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26761 +001 1 +011 1 +110 1 +111 1 +.names xv[6][20] yv[6][16] yv[6][20] $abc$30358$new_n3720 $abc$30358$new_n3711 $abc$30358$new_n3733 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[6][20] $abc$30358$new_n3721 yv[6][13] yv[6][14] $abc$30358$new_n3737 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[6][20] yv[6][14] $abc$30358$new_n3739 yv[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26765 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][20] yv[6][13] $abc$30358$new_n3721 $abc$30358$new_n3740 $abc$30358$new_n3739 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][19] yv[6][12] $abc$30358$new_n3713 $abc$30358$new_n3740 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n3742 yv[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26767 +001 1 +011 1 +100 1 +101 1 +.names xv[6][20] yv[6][13] yv[6][20] $abc$30358$new_n3721 $abc$30358$new_n3740 $abc$30358$new_n3742 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[6][19] yv[6][12] $abc$30358$new_n3744 yv[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26769 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][11] xv[6][18] $abc$30358$new_n3722 $abc$30358$new_n3713 $abc$30358$new_n3744 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][18] yv[6][11] $abc$30358$new_n3746 yv[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26771 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][17] yv[6][10] $abc$30358$new_n3723 $abc$30358$new_n3714 $abc$30358$new_n3746 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3748 yv[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26773 +001 1 +011 1 +110 1 +111 1 +.names xv[6][17] yv[6][10] yv[6][20] $abc$30358$new_n3723 $abc$30358$new_n3714 $abc$30358$new_n3748 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[6][16] yv[6][9] $abc$30358$new_n3750 yv[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26775 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][8] xv[6][15] $abc$30358$new_n3724 $abc$30358$new_n3715 $abc$30358$new_n3750 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3752 yv[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26777 +001 1 +011 1 +110 1 +111 1 +.names xv[6][15] yv[6][8] yv[6][20] $abc$30358$new_n3724 $abc$30358$new_n3715 $abc$30358$new_n3752 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[6][14] yv[6][7] $abc$30358$new_n3754 yv[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26779 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][6] xv[6][13] $abc$30358$new_n3725 $abc$30358$new_n3716 $abc$30358$new_n3754 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[6][13] yv[6][6] $abc$30358$new_n3756 yv[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26781 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] $abc$30358$new_n3716 $abc$30358$new_n3725 $abc$30358$new_n3756 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[6][12] yv[6][5] $abc$30358$new_n3758 yv[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26783 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][4] xv[6][11] $abc$30358$new_n3726 $abc$30358$new_n3717 $abc$30358$new_n3758 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3760 yv[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26785 +001 1 +011 1 +110 1 +111 1 +.names xv[6][11] yv[6][4] yv[6][20] $abc$30358$new_n3726 $abc$30358$new_n3717 $abc$30358$new_n3760 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[6][10] yv[6][3] $abc$30358$new_n3762 yv[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26787 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] yv[6][2] xv[6][9] $abc$30358$new_n3727 $abc$30358$new_n3718 $abc$30358$new_n3762 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[6][9] yv[6][2] $abc$30358$new_n3764 yv[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26789 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3718 $abc$30358$new_n3727 $abc$30358$new_n3764 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3766 yv[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26791 +001 1 +011 1 +110 1 +111 1 +.names xv[6][8] yv[6][1] yv[6][20] yv[6][0] xv[6][7] $abc$30358$new_n3766 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[6][7] yv[6][0] yv[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26793 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][15] xv[6][13] xv[6][14] $abc$30358$new_n3771 $abc$30358$new_n3770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[6][12] yv[6][19] $abc$30358$new_n3772 $abc$30358$new_n3771 +000 1 +001 1 +010 1 +100 1 +.names xv[6][10] yv[6][17] xv[6][11] yv[6][18] $abc$30358$new_n3773 $abc$30358$new_n3772 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][9] yv[6][16] $abc$30358$new_n3774 $abc$30358$new_n3773 +000 1 +001 1 +011 1 +101 1 +.names xv[6][7] yv[6][14] xv[6][8] yv[6][15] $abc$30358$new_n3775 $abc$30358$new_n3774 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][5] yv[6][12] xv[6][6] yv[6][13] $abc$30358$new_n3776 $abc$30358$new_n3775 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][3] yv[6][10] xv[6][4] yv[6][11] $abc$30358$new_n3777 $abc$30358$new_n3776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[6][2] yv[6][9] $abc$30358$new_n3778 $abc$30358$new_n3777 +000 1 +001 1 +011 1 +101 1 +.names xv[6][0] yv[6][7] xv[6][1] yv[6][8] $abc$30358$new_n3778 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[6][16] xv[6][17] $abc$30358$new_n3781 $abc$30358$new_n3780 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n3792 $abc$30358$new_n3790 $abc$30358$new_n3791 $abc$30358$new_n3782 $abc$30358$new_n3788 $abc$30358$new_n3781 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$30358$new_n3783 xv[6][10] yv[6][17] xv[6][11] yv[6][18] $abc$30358$new_n3782 +10000 1 +10011 1 +11100 1 +11111 1 +.names xv[6][8] yv[6][15] xv[6][9] yv[6][16] $abc$30358$new_n3784 $abc$30358$new_n3783 +00000 1 +00110 1 +11000 1 +11110 1 +.names yv[6][13] xv[6][6] xv[6][7] yv[6][14] $abc$30358$new_n3785 $abc$30358$new_n3784 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][11] xv[6][4] xv[6][5] yv[6][12] $abc$30358$new_n3786 $abc$30358$new_n3785 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[6][9] xv[6][2] xv[6][3] yv[6][10] $abc$30358$new_n3787 $abc$30358$new_n3786 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[6][7] xv[6][0] xv[6][1] yv[6][8] $abc$30358$new_n3787 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[6][17] xv[6][10] xv[6][11] yv[6][18] $abc$30358$new_n3789 $abc$30358$new_n3788 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names xv[6][8] xv[6][9] yv[6][15] yv[6][16] $abc$30358$new_n3789 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names yv[6][20] xv[6][13] xv[6][12] yv[6][19] $abc$30358$new_n3790 +0000 1 +0011 1 +1100 1 +1111 1 +.names xv[6][12] yv[6][19] yv[6][20] xv[6][13] $abc$30358$new_n3791 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[6][20] xv[6][14] xv[6][15] $abc$30358$new_n3792 +000 1 +111 1 +.names i_ce xv[6][17] $abc$30358$new_n3798 xv[7][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26799 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][16] yv[6][20] $abc$30358$new_n3770 $abc$30358$new_n3781 $abc$30358$new_n3798 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$30358$new_n3800 i_ce xv[7][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26801 +001 1 +010 1 +011 1 +.names i_ce yv[6][20] xv[6][16] $abc$30358$new_n3781 $abc$30358$new_n3770 $abc$30358$new_n3800 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][15] $abc$30358$new_n3802 xv[7][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26803 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[6][14] yv[6][20] $abc$30358$new_n3803 $abc$30358$new_n3804 $abc$30358$new_n3802 +1000 1 +1001 1 +1100 1 +1110 1 +.names xv[6][13] $abc$30358$new_n3771 $abc$30358$new_n3803 +00 1 +01 1 +11 1 +.names $abc$30358$new_n3791 $abc$30358$new_n3790 $abc$30358$new_n3788 $abc$30358$new_n3782 $abc$30358$new_n3804 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$30358$new_n3806 i_ce xv[7][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26805 +001 1 +010 1 +011 1 +.names i_ce yv[6][20] xv[6][14] $abc$30358$new_n3804 $abc$30358$new_n3803 $abc$30358$new_n3806 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][13] $abc$30358$new_n3808 xv[7][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26807 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] xv[6][12] yv[6][19] $abc$30358$new_n3809 $abc$30358$new_n3772 $abc$30358$new_n3808 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n3788 $abc$30358$new_n3782 $abc$30358$new_n3809 +10 1 +.names i_ce $abc$30358$new_n3811 xv[7][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26809 +001 1 +011 1 +110 1 +111 1 +.names yv[6][20] xv[6][12] yv[6][19] $abc$30358$new_n3809 $abc$30358$new_n3772 $abc$30358$new_n3811 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[6][11] yv[6][18] $abc$30358$new_n3813 xv[7][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26811 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[6][10] yv[6][20] $abc$30358$new_n3814 yv[6][17] $abc$30358$new_n3773 $abc$30358$new_n3813 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names yv[6][20] $abc$30358$new_n3783 $abc$30358$new_n3789 $abc$30358$new_n3814 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3816 xv[7][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26813 +001 1 +011 1 +110 1 +111 1 +.names xv[6][10] yv[6][17] $abc$30358$new_n3814 yv[6][20] $abc$30358$new_n3773 $abc$30358$new_n3816 +00000 1 +00010 1 +00011 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +.names i_ce xv[6][9] yv[6][16] $abc$30358$new_n3818 xv[7][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26815 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] xv[6][8] yv[6][15] $abc$30358$new_n3784 $abc$30358$new_n3774 $abc$30358$new_n3818 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[6][8] yv[6][15] $abc$30358$new_n3820 xv[7][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26817 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][7] yv[6][14] $abc$30358$new_n3775 $abc$30358$new_n3784 $abc$30358$new_n3820 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][7] yv[6][14] $abc$30358$new_n3822 xv[7][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26819 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] yv[6][13] xv[6][6] $abc$30358$new_n3785 $abc$30358$new_n3775 $abc$30358$new_n3822 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][6] yv[6][13] $abc$30358$new_n3824 xv[7][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26821 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][5] yv[6][12] $abc$30358$new_n3776 $abc$30358$new_n3785 $abc$30358$new_n3824 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][5] yv[6][12] $abc$30358$new_n3826 xv[7][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26823 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] yv[6][11] xv[6][4] $abc$30358$new_n3786 $abc$30358$new_n3776 $abc$30358$new_n3826 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][4] yv[6][11] $abc$30358$new_n3828 xv[7][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26825 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[6][20] xv[6][3] yv[6][10] $abc$30358$new_n3777 $abc$30358$new_n3786 $abc$30358$new_n3828 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[6][3] yv[6][10] $abc$30358$new_n3830 xv[7][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26827 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] xv[6][2] yv[6][9] $abc$30358$new_n3787 $abc$30358$new_n3778 $abc$30358$new_n3830 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[6][2] yv[6][9] $abc$30358$new_n3832 xv[7][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26829 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3778 $abc$30358$new_n3787 $abc$30358$new_n3832 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n3834 xv[7][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26831 +001 1 +011 1 +110 1 +111 1 +.names xv[6][1] yv[6][8] yv[6][20] xv[6][0] yv[6][7] $abc$30358$new_n3834 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[6][0] yv[6][7] xv[7][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26833 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3837 ph[7][19] ph[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26835 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[7][18] $abc$30358$new_n3838 ph[7][17] $abc$30358$new_n3844 ph[7][16] $abc$30358$new_n3837 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[7][20] $abc$30358$new_n3839 ph[7][16] ph[7][17] $abc$30358$new_n3838 +1100 1 +.names $abc$30358$new_n3840 ph[7][15] $abc$30358$new_n3839 +10 1 +.names $abc$30358$new_n3841 ph[7][12] ph[7][13] ph[7][14] $abc$30358$new_n3840 +1000 1 +.names ph[7][11] ph[7][10] ph[7][9] $abc$30358$new_n3842 $abc$30358$new_n3841 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[7][8] ph[7][7] $abc$30358$new_n3843 ph[7][5] ph[7][6] $abc$30358$new_n3842 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[7][4] ph[7][3] ph[7][1] ph[7][2] ph[7][0] $abc$30358$new_n3843 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n3845 yv[7][20] $abc$30358$new_n3844 +10 1 +.names ph[7][15] $abc$30358$new_n3846 $abc$30358$new_n3845 +11 1 +.names ph[7][12] ph[7][13] ph[7][14] $abc$30358$new_n3847 $abc$30358$new_n3846 +1111 1 +.names ph[7][11] ph[7][10] ph[7][9] $abc$30358$new_n3848 $abc$30358$new_n3847 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[7][8] ph[7][6] ph[7][7] ph[7][5] $abc$30358$new_n3849 $abc$30358$new_n3848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names ph[7][4] ph[7][3] ph[7][1] ph[7][2] ph[7][0] $abc$30358$new_n3849 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +.names i_ce $abc$30358$new_n3851 ph[7][18] ph[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26837 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n3838 ph[7][17] $abc$30358$new_n3844 ph[7][16] $abc$30358$new_n3851 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names i_ce $abc$30358$new_n3853 ph[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26839 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] ph[7][17] ph[7][16] $abc$30358$new_n3845 $abc$30358$new_n3839 $abc$30358$new_n3853 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3855 ph[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26841 +001 1 +011 1 +100 1 +101 1 +.names ph[7][16] yv[7][20] $abc$30358$new_n3845 $abc$30358$new_n3839 $abc$30358$new_n3855 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$30358$new_n3857 ph[8][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26843 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[7][15] yv[7][20] $abc$30358$new_n3846 $abc$30358$new_n3840 $abc$30358$new_n3857 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[7][14] $abc$30358$new_n3859 ph[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26845 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[7][12] ph[7][13] yv[7][20] $abc$30358$new_n3841 $abc$30358$new_n3847 $abc$30358$new_n3859 +00110 1 +00111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3864 ph[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26849 +001 1 +011 1 +110 1 +111 1 +.names ph[7][12] yv[7][20] $abc$30358$new_n3847 $abc$30358$new_n3841 $abc$30358$new_n3864 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[7][11] $abc$30358$new_n3866 ph[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26851 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][9] ph[7][10] $abc$30358$new_n3842 $abc$30358$new_n3848 $abc$30358$new_n3866 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n3868 ph[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26853 +001 1 +011 1 +110 1 +111 1 +.names ph[7][10] yv[7][20] ph[7][9] $abc$30358$new_n3848 $abc$30358$new_n3842 $abc$30358$new_n3868 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n3870 ph[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26855 +001 1 +011 1 +110 1 +111 1 +.names ph[7][9] yv[7][20] $abc$30358$new_n3848 $abc$30358$new_n3842 $abc$30358$new_n3870 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3872 ph[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26857 +001 1 +011 1 +100 1 +101 1 +.names ph[7][6] ph[7][8] ph[7][7] $abc$30358$new_n3874 $abc$30358$new_n3873 $abc$30358$new_n3872 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] ph[7][5] $abc$30358$new_n3843 $abc$30358$new_n3873 +100 1 +.names ph[7][5] yv[7][20] $abc$30358$new_n3849 $abc$30358$new_n3874 +100 1 +.names i_ce $abc$30358$new_n3876 ph[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26859 +001 1 +011 1 +110 1 +111 1 +.names ph[7][6] ph[7][7] $abc$30358$new_n3874 $abc$30358$new_n3873 $abc$30358$new_n3876 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[7][6] $abc$30358$new_n3874 $abc$30358$new_n3873 ph[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26861 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n3879 ph[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26863 +001 1 +011 1 +110 1 +111 1 +.names ph[7][5] yv[7][20] $abc$30358$new_n3849 $abc$30358$new_n3843 $abc$30358$new_n3879 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[7][4] $abc$30358$new_n3881 ph[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26865 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][0] ph[7][1] ph[7][2] ph[7][3] $abc$30358$new_n3881 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3883 ph[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26867 +001 1 +011 1 +110 1 +111 1 +.names ph[7][3] yv[7][20] ph[7][0] ph[7][1] ph[7][2] $abc$30358$new_n3883 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11111 1 +.names i_ce $abc$30358$new_n3885 ph[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26869 +001 1 +011 1 +100 1 +101 1 +.names ph[7][2] yv[7][20] ph[7][0] ph[7][1] $abc$30358$new_n3885 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +1111 1 +.names i_ce yv[7][20] ph[7][0] ph[7][1] ph[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26871 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[7][0] ph[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26873 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[7][20] yv[7][19] $abc$30358$new_n3889 yv[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26875 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][18] yv[7][20] $abc$30358$new_n3890 xv[7][20] $abc$30358$new_n3903 $abc$30358$new_n3889 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[7][20] xv[7][20] yv[7][16] yv[7][17] $abc$30358$new_n3891 $abc$30358$new_n3890 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[7][13] $abc$30358$new_n3900 $abc$30358$new_n3902 $abc$30358$new_n3901 $abc$30358$new_n3892 $abc$30358$new_n3891 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][19] yv[7][11] $abc$30358$new_n3893 $abc$30358$new_n3892 +000 1 +001 1 +011 1 +101 1 +.names xv[7][17] yv[7][9] xv[7][18] yv[7][10] $abc$30358$new_n3894 $abc$30358$new_n3893 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][16] yv[7][8] $abc$30358$new_n3895 $abc$30358$new_n3894 +000 1 +001 1 +011 1 +101 1 +.names xv[7][14] yv[7][6] xv[7][15] yv[7][7] $abc$30358$new_n3896 $abc$30358$new_n3895 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][12] yv[7][4] xv[7][13] yv[7][5] $abc$30358$new_n3897 $abc$30358$new_n3896 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][10] yv[7][2] xv[7][11] yv[7][3] $abc$30358$new_n3898 $abc$30358$new_n3897 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][8] yv[7][0] xv[7][9] yv[7][1] $abc$30358$new_n3898 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[7][20] yv[7][13] $abc$30358$new_n3900 +01 1 +10 1 +.names xv[7][20] yv[7][12] $abc$30358$new_n3901 +01 1 +10 1 +.names xv[7][20] yv[7][14] yv[7][15] $abc$30358$new_n3902 +011 1 +100 1 +.names xv[7][20] $abc$30358$new_n3904 yv[7][16] yv[7][17] $abc$30358$new_n3903 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[7][13] $abc$30358$new_n3900 $abc$30358$new_n3913 $abc$30358$new_n3905 $abc$30358$new_n3901 $abc$30358$new_n3904 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names xv[7][19] yv[7][11] yv[7][10] xv[7][18] $abc$30358$new_n3906 $abc$30358$new_n3905 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][17] yv[7][9] xv[7][18] yv[7][10] $abc$30358$new_n3907 $abc$30358$new_n3906 +00000 1 +00110 1 +01000 1 +01001 1 +01110 1 +01111 1 +11000 1 +11110 1 +.names xv[7][16] yv[7][8] $abc$30358$new_n3908 $abc$30358$new_n3907 +000 1 +100 1 +101 1 +110 1 +.names yv[7][6] xv[7][14] xv[7][15] yv[7][7] $abc$30358$new_n3909 $abc$30358$new_n3908 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[7][12] xv[7][13] yv[7][4] yv[7][5] $abc$30358$new_n3910 $abc$30358$new_n3909 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][10] xv[7][11] yv[7][2] yv[7][3] $abc$30358$new_n3911 $abc$30358$new_n3910 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[7][8] xv[7][9] yv[7][0] yv[7][1] $abc$30358$new_n3911 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[7][20] yv[7][14] yv[7][15] $abc$30358$new_n3913 +000 1 +111 1 +.names i_ce xv[7][20] yv[7][18] $abc$30358$new_n3915 yv[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26877 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n3890 $abc$30358$new_n3903 yv[7][20] $abc$30358$new_n3915 +000 1 +001 1 +011 1 +.names i_ce xv[7][20] yv[7][17] $abc$30358$new_n3917 yv[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26879 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][20] yv[7][16] $abc$30358$new_n3904 $abc$30358$new_n3891 $abc$30358$new_n3917 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3919 yv[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26881 +001 1 +011 1 +100 1 +101 1 +.names xv[7][20] yv[7][16] yv[7][20] $abc$30358$new_n3904 $abc$30358$new_n3891 $abc$30358$new_n3919 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[7][20] yv[7][15] $abc$30358$new_n3921 yv[8][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26883 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][14] xv[7][20] $abc$30358$new_n3923 $abc$30358$new_n3922 $abc$30358$new_n3921 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[7][20] $abc$30358$new_n3892 yv[7][12] yv[7][13] $abc$30358$new_n3922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[7][20] yv[7][12] yv[7][13] $abc$30358$new_n3905 $abc$30358$new_n3923 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n3925 yv[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26885 +001 1 +011 1 +110 1 +111 1 +.names xv[7][20] yv[7][14] yv[7][20] $abc$30358$new_n3923 $abc$30358$new_n3922 $abc$30358$new_n3925 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3900 $abc$30358$new_n3927 yv[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26887 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] xv[7][20] yv[7][12] $abc$30358$new_n3905 $abc$30358$new_n3892 $abc$30358$new_n3927 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3929 yv[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26889 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n3901 yv[7][20] $abc$30358$new_n3905 $abc$30358$new_n3892 $abc$30358$new_n3929 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[7][19] yv[7][11] $abc$30358$new_n3931 yv[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26891 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3893 $abc$30358$new_n3906 yv[7][10] xv[7][18] $abc$30358$new_n3931 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[7][18] yv[7][10] $abc$30358$new_n3933 yv[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26893 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][17] yv[7][9] $abc$30358$new_n3907 $abc$30358$new_n3894 $abc$30358$new_n3933 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n3935 yv[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26895 +001 1 +011 1 +110 1 +111 1 +.names xv[7][17] yv[7][9] yv[7][20] $abc$30358$new_n3907 $abc$30358$new_n3894 $abc$30358$new_n3935 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n3937 yv[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26897 +001 1 +011 1 +110 1 +111 1 +.names xv[7][16] yv[7][8] yv[7][20] $abc$30358$new_n3908 $abc$30358$new_n3895 $abc$30358$new_n3937 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[7][15] yv[7][7] $abc$30358$new_n3939 yv[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26899 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][6] xv[7][14] $abc$30358$new_n3909 $abc$30358$new_n3896 $abc$30358$new_n3939 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3941 yv[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26901 +001 1 +011 1 +110 1 +111 1 +.names xv[7][14] yv[7][6] yv[7][20] $abc$30358$new_n3909 $abc$30358$new_n3896 $abc$30358$new_n3941 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[7][13] yv[7][5] $abc$30358$new_n3943 yv[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26903 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][4] xv[7][12] $abc$30358$new_n3910 $abc$30358$new_n3897 $abc$30358$new_n3943 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n3945 yv[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26905 +001 1 +011 1 +110 1 +111 1 +.names xv[7][12] yv[7][4] yv[7][20] $abc$30358$new_n3910 $abc$30358$new_n3897 $abc$30358$new_n3945 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[7][11] yv[7][3] $abc$30358$new_n3947 yv[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26907 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] yv[7][2] xv[7][10] $abc$30358$new_n3911 $abc$30358$new_n3898 $abc$30358$new_n3947 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[7][10] yv[7][2] $abc$30358$new_n3949 yv[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26909 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3898 $abc$30358$new_n3911 $abc$30358$new_n3949 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n3951 yv[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26911 +001 1 +011 1 +110 1 +111 1 +.names xv[7][9] yv[7][1] yv[7][20] yv[7][0] xv[7][8] $abc$30358$new_n3951 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[7][8] yv[7][0] yv[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26913 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[7][19] $abc$30358$new_n3969 $abc$30358$new_n3954 xv[8][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26915 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[7][20] $abc$30358$new_n3955 xv[7][18] $abc$30358$new_n3954 +000 1 +001 1 +010 1 +.names xv[7][16] xv[7][17] $abc$30358$new_n3956 $abc$30358$new_n3955 +110 1 +.names $abc$30358$new_n3968 $abc$30358$new_n3966 $abc$30358$new_n3967 $abc$30358$new_n3957 $abc$30358$new_n3956 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names xv[7][11] yv[7][19] $abc$30358$new_n3958 $abc$30358$new_n3957 +000 1 +001 1 +011 1 +101 1 +.names xv[7][9] yv[7][17] xv[7][10] yv[7][18] $abc$30358$new_n3959 $abc$30358$new_n3958 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][7] yv[7][15] xv[7][8] yv[7][16] $abc$30358$new_n3960 $abc$30358$new_n3959 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][5] yv[7][13] xv[7][6] yv[7][14] $abc$30358$new_n3961 $abc$30358$new_n3960 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][3] yv[7][11] xv[7][4] yv[7][12] $abc$30358$new_n3962 $abc$30358$new_n3961 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[7][2] yv[7][10] $abc$30358$new_n3963 $abc$30358$new_n3962 +000 1 +001 1 +011 1 +101 1 +.names xv[7][0] yv[7][8] xv[7][1] yv[7][9] $abc$30358$new_n3963 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[7][20] xv[7][12] xv[7][13] $abc$30358$new_n3966 +011 1 +100 1 +.names yv[7][20] xv[7][15] $abc$30358$new_n3967 +00 1 +11 1 +.names yv[7][20] xv[7][14] $abc$30358$new_n3968 +01 1 +10 1 +.names yv[7][20] xv[7][16] xv[7][17] xv[7][18] $abc$30358$new_n3970 $abc$30358$new_n3969 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n3971 xv[7][14] xv[7][15] $abc$30358$new_n3970 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n3972 xv[7][12] xv[7][13] $abc$30358$new_n3971 +111 1 +.names xv[7][10] xv[7][11] yv[7][18] yv[7][19] $abc$30358$new_n3973 $abc$30358$new_n3972 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +10000 1 +10001 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names yv[7][16] xv[7][8] xv[7][9] yv[7][17] $abc$30358$new_n3974 $abc$30358$new_n3973 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][14] xv[7][6] xv[7][7] yv[7][15] $abc$30358$new_n3975 $abc$30358$new_n3974 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][12] xv[7][4] xv[7][5] yv[7][13] $abc$30358$new_n3976 $abc$30358$new_n3975 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[7][10] xv[7][2] xv[7][3] yv[7][11] $abc$30358$new_n3977 $abc$30358$new_n3976 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[7][8] xv[7][0] xv[7][1] yv[7][9] $abc$30358$new_n3977 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$30358$new_n3971 $abc$30358$new_n3967 $abc$30358$new_n3968 $abc$30358$new_n3984 +110 1 +.names $abc$30358$new_n3986 i_ce xv[8][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26921 +001 1 +010 1 +011 1 +.names i_ce yv[7][20] xv[7][16] $abc$30358$new_n3984 $abc$30358$new_n3956 $abc$30358$new_n3986 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[7][15] xv[7][14] $abc$30358$new_n3988 xv[8][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26923 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[7][13] $abc$30358$new_n3989 $abc$30358$new_n3988 +00 1 +01 1 +10 1 +.names xv[7][12] yv[7][20] $abc$30358$new_n3957 $abc$30358$new_n3972 $abc$30358$new_n3989 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n3988 xv[7][14] xv[8][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26925 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[7][13] $abc$30358$new_n3989 xv[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26927 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n3993 xv[8][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26929 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] xv[7][12] $abc$30358$new_n3972 $abc$30358$new_n3957 $abc$30358$new_n3993 +0000 1 +0010 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[7][11] yv[7][19] $abc$30358$new_n3995 xv[8][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26931 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] xv[7][10] yv[7][18] $abc$30358$new_n3973 $abc$30358$new_n3958 $abc$30358$new_n3995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[7][10] yv[7][18] $abc$30358$new_n3997 xv[8][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26933 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][9] yv[7][17] $abc$30358$new_n3959 $abc$30358$new_n3973 $abc$30358$new_n3997 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][9] yv[7][17] $abc$30358$new_n3999 xv[8][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26935 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][16] xv[7][8] $abc$30358$new_n3974 $abc$30358$new_n3959 $abc$30358$new_n3999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][8] yv[7][16] $abc$30358$new_n4001 xv[8][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26937 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][7] yv[7][15] $abc$30358$new_n3960 $abc$30358$new_n3974 $abc$30358$new_n4001 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][7] yv[7][15] $abc$30358$new_n4003 xv[8][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26939 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][14] xv[7][6] $abc$30358$new_n3975 $abc$30358$new_n3960 $abc$30358$new_n4003 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][6] yv[7][14] $abc$30358$new_n4005 xv[8][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26941 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][5] yv[7][13] $abc$30358$new_n3961 $abc$30358$new_n3975 $abc$30358$new_n4005 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][5] yv[7][13] $abc$30358$new_n4007 xv[8][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26943 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] yv[7][12] xv[7][4] $abc$30358$new_n3976 $abc$30358$new_n3961 $abc$30358$new_n4007 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][4] yv[7][12] $abc$30358$new_n4009 xv[8][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26945 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[7][20] xv[7][3] yv[7][11] $abc$30358$new_n3962 $abc$30358$new_n3976 $abc$30358$new_n4009 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[7][3] yv[7][11] $abc$30358$new_n4011 xv[8][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26947 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] xv[7][2] yv[7][10] $abc$30358$new_n3977 $abc$30358$new_n3963 $abc$30358$new_n4011 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[7][2] yv[7][10] $abc$30358$new_n4013 xv[8][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26949 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[7][20] $abc$30358$new_n3963 $abc$30358$new_n3977 $abc$30358$new_n4013 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4015 xv[8][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26951 +001 1 +011 1 +110 1 +111 1 +.names xv[7][1] yv[7][9] yv[7][20] xv[7][0] yv[7][8] $abc$30358$new_n4015 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[7][0] yv[7][8] xv[8][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26953 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[8][19] $abc$30358$new_n4018 ph[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26955 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[8][18] $abc$30358$new_n4019 $abc$30358$new_n4027 $abc$30358$new_n4018 +010 1 +011 1 +101 1 +111 1 +.names yv[8][20] $abc$30358$new_n4020 ph[8][16] ph[8][17] $abc$30358$new_n4019 +1100 1 +.names $abc$30358$new_n4021 ph[8][14] ph[8][15] $abc$30358$new_n4020 +100 1 +.names $abc$30358$new_n4022 ph[8][13] $abc$30358$new_n4021 +10 1 +.names ph[8][10] ph[8][11] ph[8][12] $abc$30358$new_n4023 $abc$30358$new_n4022 +0000 1 +.names ph[8][9] $abc$30358$new_n4024 $abc$30358$new_n4023 +10 1 +.names ph[8][8] ph[8][7] $abc$30358$new_n4025 ph[8][6] $abc$30358$new_n4024 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n4026 ph[8][5] $abc$30358$new_n4025 +10 1 +.names ph[8][4] ph[8][2] ph[8][3] ph[8][1] ph[8][0] $abc$30358$new_n4026 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names $abc$30358$new_n4028 ph[8][16] ph[8][17] yv[8][20] $abc$30358$new_n4027 +1110 1 +.names ph[8][14] ph[8][15] $abc$30358$new_n4029 $abc$30358$new_n4028 +111 1 +.names ph[8][13] $abc$30358$new_n4030 $abc$30358$new_n4029 +11 1 +.names ph[8][11] ph[8][12] $abc$30358$new_n4031 $abc$30358$new_n4030 +111 1 +.names ph[8][10] $abc$30358$new_n4032 ph[8][9] $abc$30358$new_n4031 +101 1 +110 1 +111 1 +.names ph[8][8] ph[8][7] ph[8][6] $abc$30358$new_n4033 $abc$30358$new_n4032 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[8][5] $abc$30358$new_n4034 $abc$30358$new_n4033 +11 1 +.names ph[8][4] ph[8][2] ph[8][3] ph[8][1] ph[8][0] $abc$30358$new_n4034 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce ph[8][18] $abc$30358$new_n4027 $abc$30358$new_n4019 ph[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26957 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4037 ph[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26959 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][17] ph[8][16] $abc$30358$new_n4028 $abc$30358$new_n4020 $abc$30358$new_n4037 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4039 ph[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$26961 +001 1 +011 1 +110 1 +111 1 +.names ph[8][16] yv[8][20] $abc$30358$new_n4028 $abc$30358$new_n4020 $abc$30358$new_n4039 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n4044 ph[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$26965 +001 1 +011 1 +110 1 +111 1 +.names ph[8][14] yv[8][20] $abc$30358$new_n4029 $abc$30358$new_n4021 $abc$30358$new_n4044 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n4046 ph[9][13] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$26967 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[8][13] yv[8][20] $abc$30358$new_n4030 $abc$30358$new_n4022 $abc$30358$new_n4046 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4048 ph[8][12] ph[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$26969 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][11] $abc$30358$new_n4031 ph[8][10] $abc$30358$new_n4023 $abc$30358$new_n4048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4050 ph[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26971 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][11] ph[8][10] $abc$30358$new_n4023 $abc$30358$new_n4031 $abc$30358$new_n4050 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4052 ph[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$26973 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][10] ph[8][9] $abc$30358$new_n4032 $abc$30358$new_n4024 $abc$30358$new_n4052 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n4054 ph[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$26975 +001 1 +011 1 +100 1 +101 1 +.names ph[8][9] yv[8][20] $abc$30358$new_n4032 $abc$30358$new_n4024 $abc$30358$new_n4054 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n4056 ph[8][8] ph[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$26977 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][7] ph[8][6] $abc$30358$new_n4025 $abc$30358$new_n4033 $abc$30358$new_n4056 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4058 ph[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$26979 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][7] ph[8][6] $abc$30358$new_n4033 $abc$30358$new_n4025 $abc$30358$new_n4058 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4060 ph[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$26981 +001 1 +011 1 +110 1 +111 1 +.names ph[8][5] ph[8][6] $abc$30358$new_n4062 $abc$30358$new_n4061 $abc$30358$new_n4060 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] $abc$30358$new_n4026 $abc$30358$new_n4061 +11 1 +.names $abc$30358$new_n4034 yv[8][20] $abc$30358$new_n4062 +10 1 +.names i_ce ph[8][5] $abc$30358$new_n4062 $abc$30358$new_n4061 ph[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$26983 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4065 ph[8][4] ph[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$26985 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[8][20] ph[8][3] ph[8][0] ph[8][1] ph[8][2] $abc$30358$new_n4065 +00000 1 +00001 1 +00010 1 +00100 1 +00110 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4067 ph[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$26987 +001 1 +011 1 +110 1 +111 1 +.names ph[8][3] yv[8][20] ph[8][2] ph[8][0] ph[8][1] $abc$30358$new_n4067 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +.names i_ce $abc$30358$new_n4069 ph[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$26989 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] ph[8][2] ph[8][0] ph[8][1] $abc$30358$new_n4069 +0000 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce yv[8][20] ph[8][0] ph[8][1] ph[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$26991 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[8][0] ph[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$26993 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[8][20] yv[8][19] $abc$30358$new_n4073 yv[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][18] xv[8][20] $abc$30358$new_n4087 $abc$30358$new_n4074 $abc$30358$new_n4073 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[8][20] $abc$30358$new_n4075 yv[8][16] yv[8][17] $abc$30358$new_n4074 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[8][13] $abc$30358$new_n4084 $abc$30358$new_n4086 $abc$30358$new_n4076 $abc$30358$new_n4085 $abc$30358$new_n4075 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names yv[8][10] xv[8][19] xv[8][20] yv[8][11] $abc$30358$new_n4077 $abc$30358$new_n4076 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[8][18] yv[8][9] $abc$30358$new_n4078 $abc$30358$new_n4077 +001 1 +100 1 +101 1 +111 1 +.names xv[8][17] yv[8][8] $abc$30358$new_n4079 $abc$30358$new_n4078 +000 1 +100 1 +101 1 +110 1 +.names yv[8][6] xv[8][15] xv[8][16] yv[8][7] $abc$30358$new_n4080 $abc$30358$new_n4079 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[8][13] xv[8][14] yv[8][4] yv[8][5] $abc$30358$new_n4081 $abc$30358$new_n4080 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][11] xv[8][12] yv[8][2] yv[8][3] $abc$30358$new_n4082 $abc$30358$new_n4081 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[8][9] xv[8][10] yv[8][0] yv[8][1] $abc$30358$new_n4082 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[8][20] yv[8][13] $abc$30358$new_n4084 +01 1 +10 1 +.names xv[8][20] yv[8][12] $abc$30358$new_n4085 +01 1 +10 1 +.names xv[8][20] yv[8][14] yv[8][15] $abc$30358$new_n4086 +000 1 +111 1 +.names xv[8][20] $abc$30358$new_n4088 yv[8][16] yv[8][17] $abc$30358$new_n4087 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[8][20] $abc$30358$new_n4097 $abc$30358$new_n4084 $abc$30358$new_n4085 $abc$30358$new_n4089 $abc$30358$new_n4088 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11111 1 +.names xv[8][19] yv[8][10] xv[8][20] yv[8][11] $abc$30358$new_n4090 $abc$30358$new_n4089 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][18] yv[8][9] $abc$30358$new_n4091 $abc$30358$new_n4090 +000 1 +001 1 +011 1 +101 1 +.names xv[8][17] yv[8][8] $abc$30358$new_n4092 $abc$30358$new_n4091 +000 1 +001 1 +011 1 +101 1 +.names xv[8][15] yv[8][6] xv[8][16] yv[8][7] $abc$30358$new_n4093 $abc$30358$new_n4092 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][13] yv[8][4] xv[8][14] yv[8][5] $abc$30358$new_n4094 $abc$30358$new_n4093 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][11] yv[8][2] xv[8][12] yv[8][3] $abc$30358$new_n4095 $abc$30358$new_n4094 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][9] yv[8][0] xv[8][10] yv[8][1] $abc$30358$new_n4095 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[8][20] yv[8][14] yv[8][15] $abc$30358$new_n4097 +011 1 +100 1 +.names i_ce $abc$30358$new_n4099 yv[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26997 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][20] yv[8][18] $abc$30358$new_n4087 $abc$30358$new_n4074 $abc$30358$new_n4099 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][20] yv[8][17] $abc$30358$new_n4101 yv[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26999 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][20] yv[8][16] $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n4101 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4103 yv[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27001 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][20] yv[8][16] $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n4103 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][20] yv[8][15] $abc$30358$new_n4105 yv[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27003 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][14] yv[8][20] $abc$30358$new_n4106 xv[8][20] $abc$30358$new_n4107 $abc$30358$new_n4105 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[8][20] xv[8][20] yv[8][12] yv[8][13] $abc$30358$new_n4089 $abc$30358$new_n4106 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[8][20] yv[8][12] yv[8][13] $abc$30358$new_n4076 $abc$30358$new_n4107 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce $abc$30358$new_n4109 yv[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27005 +001 1 +011 1 +110 1 +111 1 +.names xv[8][20] yv[8][14] $abc$30358$new_n4106 $abc$30358$new_n4107 yv[8][20] $abc$30358$new_n4109 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4084 $abc$30358$new_n4111 yv[9][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27007 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] xv[8][20] yv[8][12] $abc$30358$new_n4089 $abc$30358$new_n4076 $abc$30358$new_n4111 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4113 yv[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27009 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] $abc$30358$new_n4085 $abc$30358$new_n4089 $abc$30358$new_n4076 $abc$30358$new_n4113 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[8][20] yv[8][11] $abc$30358$new_n4115 yv[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][10] xv[8][19] $abc$30358$new_n4090 $abc$30358$new_n4077 $abc$30358$new_n4115 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4117 yv[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27013 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][19] yv[8][10] $abc$30358$new_n4090 $abc$30358$new_n4077 $abc$30358$new_n4117 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4119 yv[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27015 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][18] yv[8][9] $abc$30358$new_n4091 $abc$30358$new_n4078 $abc$30358$new_n4119 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n4121 yv[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27017 +001 1 +011 1 +100 1 +101 1 +.names yv[8][20] xv[8][17] yv[8][8] $abc$30358$new_n4092 $abc$30358$new_n4079 $abc$30358$new_n4121 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][16] yv[8][7] $abc$30358$new_n4123 yv[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][6] xv[8][15] $abc$30358$new_n4093 $abc$30358$new_n4080 $abc$30358$new_n4123 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4125 yv[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27021 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][15] yv[8][6] $abc$30358$new_n4093 $abc$30358$new_n4080 $abc$30358$new_n4125 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][14] yv[8][5] $abc$30358$new_n4127 yv[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][4] xv[8][13] $abc$30358$new_n4094 $abc$30358$new_n4081 $abc$30358$new_n4127 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4129 yv[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27025 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] xv[8][13] yv[8][4] $abc$30358$new_n4094 $abc$30358$new_n4081 $abc$30358$new_n4129 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][12] yv[8][3] $abc$30358$new_n4131 yv[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27027 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] yv[8][2] xv[8][11] $abc$30358$new_n4095 $abc$30358$new_n4082 $abc$30358$new_n4131 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[8][11] yv[8][2] $abc$30358$new_n4133 yv[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27029 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] $abc$30358$new_n4082 $abc$30358$new_n4095 $abc$30358$new_n4133 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4135 yv[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27031 +001 1 +011 1 +110 1 +111 1 +.names xv[8][10] yv[8][1] yv[8][20] yv[8][0] xv[8][9] $abc$30358$new_n4135 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[8][9] yv[8][0] yv[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27033 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[8][14] xv[8][15] $abc$30358$new_n4140 $abc$30358$new_n4139 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[8][13] xv[8][12] $abc$30358$new_n4141 $abc$30358$new_n4140 +111 1 +.names xv[8][10] yv[8][19] $abc$30358$new_n4142 yv[8][20] xv[8][11] $abc$30358$new_n4141 +01001 1 +01010 1 +01011 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names xv[8][9] yv[8][18] $abc$30358$new_n4143 $abc$30358$new_n4142 +000 1 +001 1 +011 1 +101 1 +.names xv[8][7] yv[8][16] xv[8][8] yv[8][17] $abc$30358$new_n4144 $abc$30358$new_n4143 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][5] yv[8][14] xv[8][6] yv[8][15] $abc$30358$new_n4145 $abc$30358$new_n4144 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][3] yv[8][12] xv[8][4] yv[8][13] $abc$30358$new_n4146 $abc$30358$new_n4145 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[8][2] yv[8][11] $abc$30358$new_n4147 $abc$30358$new_n4146 +000 1 +001 1 +011 1 +101 1 +.names xv[8][0] yv[8][9] xv[8][1] yv[8][10] $abc$30358$new_n4147 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[8][14] xv[8][15] $abc$30358$new_n4151 $abc$30358$new_n4150 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[8][13] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4151 +111 1 +.names yv[8][19] xv[8][10] $abc$30358$new_n4153 yv[8][20] xv[8][11] $abc$30358$new_n4152 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[8][18] xv[8][9] $abc$30358$new_n4154 $abc$30358$new_n4153 +001 1 +100 1 +101 1 +111 1 +.names yv[8][17] xv[8][8] $abc$30358$new_n4155 $abc$30358$new_n4154 +001 1 +100 1 +101 1 +111 1 +.names yv[8][15] xv[8][6] xv[8][7] yv[8][16] $abc$30358$new_n4156 $abc$30358$new_n4155 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][13] xv[8][4] xv[8][5] yv[8][14] $abc$30358$new_n4157 $abc$30358$new_n4156 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[8][11] xv[8][2] xv[8][3] yv[8][12] $abc$30358$new_n4158 $abc$30358$new_n4157 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[8][9] xv[8][0] xv[8][1] yv[8][10] $abc$30358$new_n4158 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4163 xv[9][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27039 +001 1 +011 1 +110 1 +111 1 +.names xv[8][17] yv[8][20] xv[8][16] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n4163 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n4166 i_ce xv[9][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27041 +001 1 +010 1 +011 1 +.names i_ce xv[8][16] yv[8][20] $abc$30358$new_n4139 $abc$30358$new_n4150 $abc$30358$new_n4166 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4169 xv[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27043 +001 1 +011 1 +110 1 +111 1 +.names xv[8][15] yv[8][20] xv[8][14] $abc$30358$new_n4151 $abc$30358$new_n4140 $abc$30358$new_n4169 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4171 i_ce xv[9][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27045 +001 1 +010 1 +011 1 +.names i_ce yv[8][20] xv[8][14] $abc$30358$new_n4151 $abc$30358$new_n4140 $abc$30358$new_n4171 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4173 xv[9][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27047 +001 1 +011 1 +100 1 +101 1 +.names xv[8][13] yv[8][20] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4141 $abc$30358$new_n4173 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10101 1 +10111 1 +11110 1 +11111 1 +.names $abc$30358$new_n4175 i_ce xv[9][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27049 +001 1 +010 1 +011 1 +.names i_ce yv[8][20] xv[8][12] $abc$30358$new_n4152 $abc$30358$new_n4141 $abc$30358$new_n4175 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[8][11] $abc$30358$new_n4177 xv[9][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27051 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[8][20] xv[8][10] yv[8][19] $abc$30358$new_n4153 $abc$30358$new_n4142 $abc$30358$new_n4177 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[8][10] yv[8][19] $abc$30358$new_n4179 xv[9][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27053 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4142 $abc$30358$new_n4153 $abc$30358$new_n4179 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][9] yv[8][18] $abc$30358$new_n4181 xv[9][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27055 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4143 $abc$30358$new_n4154 $abc$30358$new_n4181 +000 1 +001 1 +101 1 +111 1 +.names i_ce xv[8][8] yv[8][17] $abc$30358$new_n4183 xv[9][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27057 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][7] yv[8][16] $abc$30358$new_n4144 $abc$30358$new_n4155 $abc$30358$new_n4183 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][7] yv[8][16] $abc$30358$new_n4185 xv[9][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] yv[8][15] xv[8][6] $abc$30358$new_n4156 $abc$30358$new_n4144 $abc$30358$new_n4185 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][6] yv[8][15] $abc$30358$new_n4187 xv[9][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27061 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][5] yv[8][14] $abc$30358$new_n4145 $abc$30358$new_n4156 $abc$30358$new_n4187 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][5] yv[8][14] $abc$30358$new_n4189 xv[9][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27063 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] yv[8][13] xv[8][4] $abc$30358$new_n4157 $abc$30358$new_n4145 $abc$30358$new_n4189 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][4] yv[8][13] $abc$30358$new_n4191 xv[9][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] xv[8][3] yv[8][12] $abc$30358$new_n4146 $abc$30358$new_n4157 $abc$30358$new_n4191 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[8][3] yv[8][12] $abc$30358$new_n4193 xv[9][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27067 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[8][20] xv[8][2] yv[8][11] $abc$30358$new_n4158 $abc$30358$new_n4147 $abc$30358$new_n4193 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[8][2] yv[8][11] $abc$30358$new_n4195 xv[9][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27069 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[8][20] $abc$30358$new_n4147 $abc$30358$new_n4158 $abc$30358$new_n4195 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4197 xv[9][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27071 +001 1 +011 1 +110 1 +111 1 +.names xv[8][1] yv[8][10] yv[8][20] xv[8][0] yv[8][9] $abc$30358$new_n4197 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[8][0] yv[8][9] xv[9][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27073 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4200 ph[9][19] ph[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27075 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[9][18] $abc$30358$new_n4201 $abc$30358$new_n4210 $abc$30358$new_n4200 +000 1 +010 1 +100 1 +101 1 +.names ph[9][17] $abc$30358$new_n4219 yv[9][20] $abc$30358$new_n4201 +100 1 +.names ph[9][14] ph[9][15] $abc$30358$new_n4204 $abc$30358$new_n4203 +111 1 +.names ph[9][13] $abc$30358$new_n4209 $abc$30358$new_n4205 $abc$30358$new_n4204 +111 1 +.names ph[9][9] $abc$30358$new_n4206 ph[9][8] $abc$30358$new_n4205 +101 1 +110 1 +111 1 +.names ph[9][7] ph[9][6] ph[9][5] $abc$30358$new_n4207 $abc$30358$new_n4206 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[9][4] $abc$30358$new_n4208 $abc$30358$new_n4207 +11 1 +.names ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4208 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[9][10] ph[9][11] ph[9][12] $abc$30358$new_n4209 +111 1 +.names yv[9][20] $abc$30358$new_n4211 ph[9][16] ph[9][17] $abc$30358$new_n4210 +1100 1 +.names $abc$30358$new_n4212 ph[9][14] ph[9][15] $abc$30358$new_n4211 +100 1 +.names $abc$30358$new_n4213 ph[9][12] ph[9][13] $abc$30358$new_n4212 +100 1 +.names ph[9][11] ph[9][9] ph[9][10] $abc$30358$new_n4214 ph[9][8] $abc$30358$new_n4213 +00000 1 +00010 1 +00011 1 +.names ph[9][7] ph[9][6] $abc$30358$new_n4215 ph[9][5] $abc$30358$new_n4214 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$30358$new_n4216 ph[9][4] $abc$30358$new_n4215 +10 1 +.names ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4216 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names i_ce ph[9][18] $abc$30358$new_n4210 $abc$30358$new_n4201 ph[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27077 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4219 ph[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27079 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] ph[9][17] ph[9][16] $abc$30358$new_n4211 $abc$30358$new_n4203 $abc$30358$new_n4219 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4221 ph[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27081 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] ph[9][16] $abc$30358$new_n4211 $abc$30358$new_n4203 $abc$30358$new_n4221 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4226 ph[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27085 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][14] $abc$30358$new_n4212 $abc$30358$new_n4204 $abc$30358$new_n4226 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4231 ph[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27089 +001 1 +011 1 +110 1 +111 1 +.names ph[9][10] ph[9][12] ph[9][11] $abc$30358$new_n4234 $abc$30358$new_n4232 $abc$30358$new_n4231 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[9][9] $abc$30358$new_n4233 $abc$30358$new_n4232 +11 1 +.names yv[9][20] $abc$30358$new_n4206 ph[9][8] $abc$30358$new_n4233 +001 1 +010 1 +011 1 +.names $abc$30358$new_n4235 ph[9][9] $abc$30358$new_n4234 +10 1 +.names yv[9][20] $abc$30358$new_n4214 ph[9][8] $abc$30358$new_n4235 +100 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4237 ph[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27091 +001 1 +011 1 +110 1 +111 1 +.names ph[9][11] ph[9][10] $abc$30358$new_n4234 $abc$30358$new_n4232 $abc$30358$new_n4237 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[9][10] $abc$30358$new_n4234 $abc$30358$new_n4232 ph[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27093 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[9][9] $abc$30358$new_n4235 $abc$30358$new_n4233 ph[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27095 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4241 ph[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27097 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][8] $abc$30358$new_n4214 $abc$30358$new_n4206 $abc$30358$new_n4241 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[9][7] $abc$30358$new_n4243 ph[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27099 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] ph[9][5] ph[9][6] $abc$30358$new_n4207 $abc$30358$new_n4215 $abc$30358$new_n4243 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4245 ph[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27101 +001 1 +011 1 +100 1 +101 1 +.names ph[9][4] ph[9][6] ph[9][5] $abc$30358$new_n4247 $abc$30358$new_n4246 $abc$30358$new_n4245 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$30358$new_n4208 yv[9][20] $abc$30358$new_n4246 +10 1 +.names yv[9][20] $abc$30358$new_n4216 $abc$30358$new_n4247 +11 1 +.names i_ce $abc$30358$new_n4249 ph[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27103 +001 1 +011 1 +110 1 +111 1 +.names ph[9][5] ph[9][4] $abc$30358$new_n4247 $abc$30358$new_n4246 $abc$30358$new_n4249 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[9][4] $abc$30358$new_n4247 $abc$30358$new_n4246 ph[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27105 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4252 ph[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27107 +001 1 +011 1 +100 1 +101 1 +.names yv[9][20] ph[9][3] ph[9][2] ph[9][0] ph[9][1] $abc$30358$new_n4252 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4254 ph[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27109 +001 1 +011 1 +110 1 +111 1 +.names ph[9][2] yv[9][20] ph[9][0] ph[9][1] $abc$30358$new_n4254 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[9][20] ph[9][0] ph[9][1] ph[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27111 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[9][0] ph[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27113 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[9][20] yv[9][19] $abc$30358$new_n4258 yv[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27115 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][18] yv[9][20] $abc$30358$new_n4259 xv[9][20] $abc$30358$new_n4269 $abc$30358$new_n4258 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[9][20] xv[9][20] yv[9][16] yv[9][17] $abc$30358$new_n4260 $abc$30358$new_n4259 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][20] yv[9][14] yv[9][15] $abc$30358$new_n4261 $abc$30358$new_n4268 $abc$30358$new_n4260 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[9][12] yv[9][13] xv[9][20] yv[9][11] $abc$30358$new_n4262 $abc$30358$new_n4261 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[9][20] yv[9][10] $abc$30358$new_n4263 $abc$30358$new_n4262 +000 1 +001 1 +011 1 +101 1 +.names xv[9][18] yv[9][8] xv[9][19] yv[9][9] $abc$30358$new_n4264 $abc$30358$new_n4263 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][16] yv[9][6] xv[9][17] yv[9][7] $abc$30358$new_n4265 $abc$30358$new_n4264 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][14] yv[9][4] xv[9][15] yv[9][5] $abc$30358$new_n4266 $abc$30358$new_n4265 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][12] yv[9][2] xv[9][13] yv[9][3] $abc$30358$new_n4267 $abc$30358$new_n4266 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][10] yv[9][0] xv[9][11] yv[9][1] $abc$30358$new_n4267 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][12] yv[9][13] $abc$30358$new_n4268 +00 1 +.names xv[9][20] $abc$30358$new_n4270 yv[9][16] yv[9][17] $abc$30358$new_n4269 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[9][20] yv[9][14] yv[9][15] $abc$30358$new_n4271 $abc$30358$new_n4268 $abc$30358$new_n4270 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[9][20] yv[9][12] yv[9][13] $abc$30358$new_n4272 $abc$30358$new_n4271 +0000 1 +1110 1 +.names xv[9][20] yv[9][10] yv[9][11] $abc$30358$new_n4273 $abc$30358$new_n4272 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[9][8] xv[9][18] xv[9][19] yv[9][9] $abc$30358$new_n4274 $abc$30358$new_n4273 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][6] xv[9][16] xv[9][17] yv[9][7] $abc$30358$new_n4275 $abc$30358$new_n4274 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[9][14] xv[9][15] yv[9][4] yv[9][5] $abc$30358$new_n4276 $abc$30358$new_n4275 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][12] xv[9][13] yv[9][2] yv[9][3] $abc$30358$new_n4277 $abc$30358$new_n4276 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[9][10] xv[9][11] yv[9][0] yv[9][1] $abc$30358$new_n4277 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[9][20] yv[9][18] $abc$30358$new_n4279 yv[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27117 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4259 $abc$30358$new_n4269 yv[9][20] $abc$30358$new_n4279 +000 1 +001 1 +011 1 +.names i_ce xv[9][20] yv[9][17] $abc$30358$new_n4281 yv[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27119 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][16] $abc$30358$new_n4270 $abc$30358$new_n4260 $abc$30358$new_n4281 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4283 yv[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27121 +001 1 +011 1 +100 1 +101 1 +.names xv[9][20] yv[9][16] yv[9][20] $abc$30358$new_n4270 $abc$30358$new_n4260 $abc$30358$new_n4283 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][20] yv[9][15] $abc$30358$new_n4285 yv[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27123 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][14] xv[9][20] $abc$30358$new_n4287 $abc$30358$new_n4286 $abc$30358$new_n4285 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n4271 $abc$30358$new_n4268 xv[9][20] $abc$30358$new_n4286 +001 1 +010 1 +011 1 +.names $abc$30358$new_n4261 $abc$30358$new_n4268 xv[9][20] $abc$30358$new_n4287 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n4289 yv[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27125 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] xv[9][20] yv[9][14] $abc$30358$new_n4287 $abc$30358$new_n4286 $abc$30358$new_n4289 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][20] yv[9][13] $abc$30358$new_n4291 yv[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27127 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][12] $abc$30358$new_n4272 $abc$30358$new_n4292 $abc$30358$new_n4291 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][20] yv[9][11] $abc$30358$new_n4262 $abc$30358$new_n4292 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n4294 yv[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27129 +001 1 +011 1 +100 1 +101 1 +.names xv[9][20] yv[9][12] yv[9][20] $abc$30358$new_n4272 $abc$30358$new_n4292 $abc$30358$new_n4294 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][20] yv[9][11] $abc$30358$new_n4296 yv[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][20] yv[9][10] $abc$30358$new_n4273 $abc$30358$new_n4263 $abc$30358$new_n4296 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4298 yv[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27133 +001 1 +011 1 +110 1 +111 1 +.names xv[9][20] yv[9][10] yv[9][20] $abc$30358$new_n4273 $abc$30358$new_n4263 $abc$30358$new_n4298 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[9][19] yv[9][9] $abc$30358$new_n4300 yv[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27135 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][8] xv[9][18] $abc$30358$new_n4274 $abc$30358$new_n4264 $abc$30358$new_n4300 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4302 yv[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27137 +001 1 +011 1 +100 1 +101 1 +.names xv[9][18] yv[9][8] yv[9][20] $abc$30358$new_n4274 $abc$30358$new_n4264 $abc$30358$new_n4302 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][17] yv[9][7] $abc$30358$new_n4304 yv[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27139 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][6] xv[9][16] $abc$30358$new_n4275 $abc$30358$new_n4265 $abc$30358$new_n4304 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4306 yv[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27141 +001 1 +011 1 +110 1 +111 1 +.names xv[9][16] yv[9][6] yv[9][20] $abc$30358$new_n4275 $abc$30358$new_n4265 $abc$30358$new_n4306 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[9][15] yv[9][5] $abc$30358$new_n4308 yv[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27143 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][4] xv[9][14] $abc$30358$new_n4276 $abc$30358$new_n4266 $abc$30358$new_n4308 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4310 yv[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27145 +001 1 +011 1 +100 1 +101 1 +.names xv[9][14] yv[9][4] yv[9][20] $abc$30358$new_n4276 $abc$30358$new_n4266 $abc$30358$new_n4310 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[9][13] yv[9][3] $abc$30358$new_n4312 yv[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27147 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] yv[9][2] xv[9][12] $abc$30358$new_n4277 $abc$30358$new_n4267 $abc$30358$new_n4312 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[9][12] yv[9][2] $abc$30358$new_n4314 yv[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27149 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] $abc$30358$new_n4267 $abc$30358$new_n4277 $abc$30358$new_n4314 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4316 yv[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27151 +001 1 +011 1 +110 1 +111 1 +.names xv[9][11] yv[9][1] yv[9][20] yv[9][0] xv[9][10] $abc$30358$new_n4316 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[9][10] yv[9][0] yv[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27153 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4319 xv[10][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27155 +001 1 +011 1 +110 1 +111 1 +.names xv[9][19] $abc$30358$new_n4330 yv[9][20] xv[9][18] $abc$30358$new_n4320 $abc$30358$new_n4319 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[9][16] xv[9][17] $abc$30358$new_n4321 $abc$30358$new_n4320 +111 1 +.names $abc$30358$new_n4322 xv[9][13] xv[9][14] xv[9][15] $abc$30358$new_n4321 +1111 1 +.names xv[9][12] yv[9][20] xv[9][10] xv[9][11] $abc$30358$new_n4323 $abc$30358$new_n4322 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[9][9] yv[9][19] $abc$30358$new_n4324 $abc$30358$new_n4323 +000 1 +001 1 +011 1 +101 1 +.names xv[9][7] yv[9][17] xv[9][8] yv[9][18] $abc$30358$new_n4325 $abc$30358$new_n4324 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][5] yv[9][15] xv[9][6] yv[9][16] $abc$30358$new_n4326 $abc$30358$new_n4325 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][3] yv[9][13] xv[9][4] yv[9][14] $abc$30358$new_n4327 $abc$30358$new_n4326 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[9][2] yv[9][12] $abc$30358$new_n4328 $abc$30358$new_n4327 +000 1 +001 1 +011 1 +101 1 +.names xv[9][0] yv[9][10] xv[9][1] yv[9][11] $abc$30358$new_n4328 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[9][20] xv[9][16] xv[9][17] xv[9][18] $abc$30358$new_n4331 $abc$30358$new_n4330 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$30358$new_n4332 xv[9][14] $abc$30358$new_n4331 +00 1 +01 1 +10 1 +.names yv[9][20] xv[9][12] xv[9][13] xv[9][15] $abc$30358$new_n4333 $abc$30358$new_n4332 +00000 1 +11110 1 +.names yv[9][20] $abc$30358$new_n4334 xv[9][10] xv[9][11] $abc$30358$new_n4333 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[9][18] xv[9][8] xv[9][9] yv[9][19] $abc$30358$new_n4335 $abc$30358$new_n4334 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][16] xv[9][6] xv[9][7] yv[9][17] $abc$30358$new_n4336 $abc$30358$new_n4335 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][14] xv[9][4] xv[9][5] yv[9][15] $abc$30358$new_n4337 $abc$30358$new_n4336 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[9][12] xv[9][2] xv[9][3] yv[9][13] $abc$30358$new_n4338 $abc$30358$new_n4337 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[9][10] xv[9][0] xv[9][1] yv[9][11] $abc$30358$new_n4338 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4343 xv[10][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27159 +001 1 +011 1 +110 1 +111 1 +.names xv[9][17] yv[9][20] xv[9][16] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n4343 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n4345 i_ce xv[10][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27161 +001 1 +010 1 +011 1 +.names i_ce yv[9][20] xv[9][16] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n4345 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][15] $abc$30358$new_n4347 xv[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27163 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][14] $abc$30358$new_n4348 yv[9][20] $abc$30358$new_n4322 $abc$30358$new_n4347 +1001 1 +1010 1 +1011 1 +.names xv[9][13] xv[9][12] $abc$30358$new_n4333 $abc$30358$new_n4348 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4359 xv[10][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27171 +001 1 +011 1 +100 1 +101 1 +.names xv[9][11] yv[9][20] xv[9][10] $abc$30358$new_n4334 $abc$30358$new_n4323 $abc$30358$new_n4359 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names $abc$30358$new_n4361 i_ce xv[10][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27173 +001 1 +010 1 +011 1 +.names i_ce yv[9][20] xv[9][10] $abc$30358$new_n4334 $abc$30358$new_n4323 $abc$30358$new_n4361 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][9] yv[9][19] $abc$30358$new_n4363 xv[10][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27175 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][18] xv[9][8] $abc$30358$new_n4335 $abc$30358$new_n4324 $abc$30358$new_n4363 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][8] yv[9][18] $abc$30358$new_n4365 xv[10][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27177 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][7] yv[9][17] $abc$30358$new_n4325 $abc$30358$new_n4335 $abc$30358$new_n4365 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][7] yv[9][17] $abc$30358$new_n4367 xv[10][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27179 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][16] xv[9][6] $abc$30358$new_n4336 $abc$30358$new_n4325 $abc$30358$new_n4367 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][6] yv[9][16] $abc$30358$new_n4369 xv[10][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27181 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][5] yv[9][15] $abc$30358$new_n4326 $abc$30358$new_n4336 $abc$30358$new_n4369 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][5] yv[9][15] $abc$30358$new_n4371 xv[10][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27183 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][14] xv[9][4] $abc$30358$new_n4337 $abc$30358$new_n4326 $abc$30358$new_n4371 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[9][4] yv[9][14] $abc$30358$new_n4373 xv[10][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27185 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] xv[9][3] yv[9][13] $abc$30358$new_n4327 $abc$30358$new_n4337 $abc$30358$new_n4373 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[9][3] yv[9][13] $abc$30358$new_n4375 xv[10][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27187 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] yv[9][12] xv[9][2] $abc$30358$new_n4338 $abc$30358$new_n4328 $abc$30358$new_n4375 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[9][2] yv[9][12] $abc$30358$new_n4377 xv[10][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27189 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[9][20] $abc$30358$new_n4328 $abc$30358$new_n4338 $abc$30358$new_n4377 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4379 xv[10][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27191 +001 1 +011 1 +110 1 +111 1 +.names xv[9][1] yv[9][11] yv[9][20] xv[9][0] yv[9][10] $abc$30358$new_n4379 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[9][0] yv[9][10] xv[10][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27193 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4382 ph[10][19] ph[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27195 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[10][17] ph[10][18] yv[10][20] $abc$30358$new_n4383 $abc$30358$new_n4389 $abc$30358$new_n4382 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4384 ph[10][16] $abc$30358$new_n4383 +10 1 +.names $abc$30358$new_n4385 ph[10][14] ph[10][15] $abc$30358$new_n4384 +100 1 +.names $abc$30358$new_n4386 ph[10][10] ph[10][11] ph[10][12] ph[10][13] $abc$30358$new_n4385 +10000 1 +.names ph[10][9] ph[10][8] $abc$30358$new_n4387 ph[10][7] $abc$30358$new_n4386 +0000 1 +0010 1 +0011 1 +.names ph[10][6] $abc$30358$new_n4388 $abc$30358$new_n4387 +00 1 +.names ph[10][5] ph[10][3] ph[10][4] ph[10][1] ph[10][2] $abc$30358$new_n4388 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[10][16] $abc$30358$new_n4390 $abc$30358$new_n4389 +11 1 +.names ph[10][14] ph[10][15] $abc$30358$new_n4391 $abc$30358$new_n4390 +111 1 +.names ph[10][10] ph[10][11] ph[10][12] ph[10][13] $abc$30358$new_n4392 $abc$30358$new_n4391 +11111 1 +.names ph[10][9] ph[10][8] $abc$30358$new_n4393 ph[10][7] $abc$30358$new_n4392 +1101 1 +1110 1 +1111 1 +.names ph[10][6] $abc$30358$new_n4394 $abc$30358$new_n4393 +10 1 +.names ph[10][5] ph[10][3] ph[10][4] ph[10][1] ph[10][2] $abc$30358$new_n4394 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce $abc$30358$new_n4396 ph[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27197 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][18] ph[10][17] $abc$30358$new_n4389 $abc$30358$new_n4383 $abc$30358$new_n4396 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4398 ph[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27199 +001 1 +011 1 +110 1 +111 1 +.names ph[10][17] yv[10][20] $abc$30358$new_n4389 $abc$30358$new_n4383 $abc$30358$new_n4398 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n4400 ph[11][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27201 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][16] yv[10][20] $abc$30358$new_n4390 $abc$30358$new_n4384 $abc$30358$new_n4400 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4402 ph[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27203 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][15] ph[10][14] $abc$30358$new_n4391 $abc$30358$new_n4385 $abc$30358$new_n4402 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4404 ph[11][14] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27205 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[10][14] yv[10][20] $abc$30358$new_n4391 $abc$30358$new_n4385 $abc$30358$new_n4404 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4406 ph[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27207 +001 1 +011 1 +110 1 +111 1 +.names ph[10][11] ph[10][13] ph[10][12] $abc$30358$new_n4409 $abc$30358$new_n4407 $abc$30358$new_n4406 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[10][10] $abc$30358$new_n4408 $abc$30358$new_n4407 +11 1 +.names $abc$30358$new_n4392 yv[10][20] $abc$30358$new_n4408 +10 1 +.names $abc$30358$new_n4410 ph[10][10] $abc$30358$new_n4409 +10 1 +.names yv[10][20] $abc$30358$new_n4386 $abc$30358$new_n4410 +11 1 +.names i_ce $abc$30358$new_n4412 ph[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27209 +001 1 +011 1 +110 1 +111 1 +.names ph[10][12] ph[10][11] $abc$30358$new_n4409 $abc$30358$new_n4407 $abc$30358$new_n4412 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][11] $abc$30358$new_n4409 $abc$30358$new_n4407 ph[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27211 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][10] $abc$30358$new_n4410 $abc$30358$new_n4408 ph[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27213 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[10][9] $abc$30358$new_n4416 ph[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27215 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] ph[10][8] ph[10][7] $abc$30358$new_n4387 $abc$30358$new_n4393 $abc$30358$new_n4416 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_ce $abc$30358$new_n4418 ph[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27217 +001 1 +011 1 +110 1 +111 1 +.names ph[10][8] yv[10][20] ph[10][7] $abc$30358$new_n4393 $abc$30358$new_n4387 $abc$30358$new_n4418 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4420 ph[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27219 +001 1 +011 1 +100 1 +101 1 +.names yv[10][20] ph[10][7] ph[10][6] $abc$30358$new_n4394 $abc$30358$new_n4388 $abc$30358$new_n4420 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4422 ph[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27221 +001 1 +011 1 +100 1 +101 1 +.names ph[10][6] yv[10][20] $abc$30358$new_n4394 $abc$30358$new_n4388 $abc$30358$new_n4422 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[10][5] $abc$30358$new_n4424 ph[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27223 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] ph[10][1] ph[10][2] ph[10][3] ph[10][4] $abc$30358$new_n4424 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4426 ph[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27225 +001 1 +011 1 +110 1 +111 1 +.names yv[10][20] ph[10][4] ph[10][1] ph[10][2] ph[10][3] $abc$30358$new_n4426 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4428 ph[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27227 +001 1 +011 1 +100 1 +101 1 +.names ph[10][3] yv[10][20] ph[10][1] ph[10][2] $abc$30358$new_n4428 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[10][20] ph[10][1] ph[10][2] ph[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27229 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[10][1] ph[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27231 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[10][0] ph[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27233 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[10][20] yv[10][19] $abc$30358$new_n4433 yv[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27235 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][18] yv[10][20] $abc$30358$new_n4434 xv[10][20] $abc$30358$new_n4449 $abc$30358$new_n4433 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names yv[10][20] xv[10][20] yv[10][16] yv[10][17] $abc$30358$new_n4435 $abc$30358$new_n4434 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4443 $abc$30358$new_n4446 $abc$30358$new_n4436 $abc$30358$new_n4448 $abc$30358$new_n4447 $abc$30358$new_n4435 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names yv[10][12] xv[10][20] yv[10][10] yv[10][11] $abc$30358$new_n4437 $abc$30358$new_n4436 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[10][19] yv[10][8] xv[10][20] yv[10][9] $abc$30358$new_n4438 $abc$30358$new_n4437 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][17] yv[10][6] xv[10][18] yv[10][7] $abc$30358$new_n4439 $abc$30358$new_n4438 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][16] yv[10][5] $abc$30358$new_n4440 $abc$30358$new_n4439 +000 1 +001 1 +011 1 +101 1 +.names xv[10][14] yv[10][3] xv[10][15] yv[10][4] $abc$30358$new_n4441 $abc$30358$new_n4440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][13] yv[10][2] $abc$30358$new_n4442 $abc$30358$new_n4441 +000 1 +001 1 +011 1 +101 1 +.names xv[10][11] yv[10][0] xv[10][12] yv[10][1] $abc$30358$new_n4442 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][20] $abc$30358$new_n4444 $abc$30358$new_n4443 +10 1 +.names $abc$30358$new_n4445 yv[10][14] yv[10][15] $abc$30358$new_n4444 +100 1 +.names yv[10][12] yv[10][13] $abc$30358$new_n4445 +00 1 +.names xv[10][20] yv[10][13] $abc$30358$new_n4446 +01 1 +10 1 +.names xv[10][20] yv[10][14] $abc$30358$new_n4447 +01 1 +10 1 +.names xv[10][20] yv[10][15] $abc$30358$new_n4448 +01 1 +10 1 +.names xv[10][20] yv[10][16] yv[10][17] $abc$30358$new_n4450 $abc$30358$new_n4444 $abc$30358$new_n4449 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4458 xv[10][20] yv[10][12] yv[10][13] $abc$30358$new_n4451 $abc$30358$new_n4450 +10000 1 +11110 1 +.names xv[10][20] $abc$30358$new_n4452 yv[10][9] yv[10][10] yv[10][11] $abc$30358$new_n4451 +01000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[10][19] yv[10][8] $abc$30358$new_n4453 $abc$30358$new_n4452 +000 1 +100 1 +101 1 +110 1 +.names yv[10][6] xv[10][17] xv[10][18] yv[10][7] $abc$30358$new_n4454 $abc$30358$new_n4453 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[10][16] yv[10][5] $abc$30358$new_n4455 $abc$30358$new_n4454 +001 1 +100 1 +101 1 +111 1 +.names xv[10][14] xv[10][15] yv[10][3] yv[10][4] $abc$30358$new_n4456 $abc$30358$new_n4455 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[10][13] yv[10][2] $abc$30358$new_n4457 $abc$30358$new_n4456 +001 1 +100 1 +101 1 +111 1 +.names xv[10][11] xv[10][12] yv[10][0] yv[10][1] $abc$30358$new_n4457 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$30358$new_n4448 $abc$30358$new_n4447 $abc$30358$new_n4458 +00 1 +.names i_ce xv[10][20] yv[10][18] $abc$30358$new_n4460 yv[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4434 $abc$30358$new_n4449 yv[10][20] $abc$30358$new_n4460 +000 1 +001 1 +011 1 +.names i_ce xv[10][20] yv[10][17] $abc$30358$new_n4462 yv[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27239 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][20] yv[10][16] $abc$30358$new_n4435 $abc$30358$new_n4463 $abc$30358$new_n4462 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4450 $abc$30358$new_n4444 xv[10][20] $abc$30358$new_n4463 +001 1 +010 1 +011 1 +.names i_ce xv[10][20] yv[10][16] $abc$30358$new_n4465 yv[11][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27241 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4463 $abc$30358$new_n4435 $abc$30358$new_n4465 +000 1 +001 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4467 $abc$30358$new_n4448 yv[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27243 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[10][20] yv[10][14] xv[10][20] $abc$30358$new_n4470 $abc$30358$new_n4468 $abc$30358$new_n4467 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[10][20] yv[10][12] yv[10][13] $abc$30358$new_n4469 $abc$30358$new_n4468 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[10][20] yv[10][10] yv[10][11] $abc$30358$new_n4437 $abc$30358$new_n4469 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[10][20] $abc$30358$new_n4451 yv[10][12] yv[10][13] $abc$30358$new_n4470 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4446 $abc$30358$new_n4475 yv[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27247 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[10][20] xv[10][20] yv[10][12] $abc$30358$new_n4451 $abc$30358$new_n4469 $abc$30358$new_n4475 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10101 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4477 yv[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27249 +001 1 +011 1 +100 1 +101 1 +.names xv[10][20] yv[10][12] yv[10][20] $abc$30358$new_n4451 $abc$30358$new_n4469 $abc$30358$new_n4477 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[10][20] yv[10][11] $abc$30358$new_n4479 yv[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27251 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][10] xv[10][20] $abc$30358$new_n4437 $abc$30358$new_n4480 $abc$30358$new_n4479 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[10][20] yv[10][9] $abc$30358$new_n4452 $abc$30358$new_n4480 +001 1 +100 1 +101 1 +111 1 +.names i_ce xv[10][20] yv[10][10] $abc$30358$new_n4482 yv[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27253 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] $abc$30358$new_n4480 $abc$30358$new_n4437 $abc$30358$new_n4482 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[10][20] yv[10][9] $abc$30358$new_n4484 yv[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27255 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][8] xv[10][19] $abc$30358$new_n4453 $abc$30358$new_n4438 $abc$30358$new_n4484 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4486 yv[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27257 +001 1 +011 1 +100 1 +101 1 +.names xv[10][19] yv[10][8] yv[10][20] $abc$30358$new_n4453 $abc$30358$new_n4438 $abc$30358$new_n4486 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][18] yv[10][7] $abc$30358$new_n4488 yv[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27259 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][6] xv[10][17] $abc$30358$new_n4454 $abc$30358$new_n4439 $abc$30358$new_n4488 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4490 yv[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27261 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] yv[10][6] yv[10][20] $abc$30358$new_n4454 $abc$30358$new_n4439 $abc$30358$new_n4490 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4492 yv[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27263 +001 1 +011 1 +100 1 +101 1 +.names xv[10][16] yv[10][5] yv[10][20] $abc$30358$new_n4455 $abc$30358$new_n4440 $abc$30358$new_n4492 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[10][15] yv[10][4] $abc$30358$new_n4494 yv[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27265 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] yv[10][3] xv[10][14] $abc$30358$new_n4456 $abc$30358$new_n4441 $abc$30358$new_n4494 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[10][14] yv[10][3] $abc$30358$new_n4496 yv[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27267 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4441 $abc$30358$new_n4456 $abc$30358$new_n4496 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[10][13] yv[10][2] $abc$30358$new_n4498 yv[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27269 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4442 $abc$30358$new_n4457 $abc$30358$new_n4498 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4500 yv[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27271 +001 1 +011 1 +110 1 +111 1 +.names xv[10][12] yv[10][1] yv[10][20] yv[10][0] xv[10][11] $abc$30358$new_n4500 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[10][11] yv[10][0] yv[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27273 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][19] $abc$30358$new_n4514 $abc$30358$new_n4503 xv[11][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27275 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[10][18] xv[10][16] xv[10][17] $abc$30358$new_n4504 $abc$30358$new_n4503 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[10][14] xv[10][15] $abc$30358$new_n4505 $abc$30358$new_n4504 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[10][12] xv[10][13] $abc$30358$new_n4506 $abc$30358$new_n4505 +110 1 +.names yv[10][20] $abc$30358$new_n4507 xv[10][9] xv[10][10] xv[10][11] $abc$30358$new_n4506 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[10][7] yv[10][18] xv[10][8] yv[10][19] $abc$30358$new_n4508 $abc$30358$new_n4507 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][5] yv[10][16] xv[10][6] yv[10][17] $abc$30358$new_n4509 $abc$30358$new_n4508 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][3] yv[10][14] xv[10][4] yv[10][15] $abc$30358$new_n4510 $abc$30358$new_n4509 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[10][2] yv[10][13] $abc$30358$new_n4511 $abc$30358$new_n4510 +000 1 +001 1 +011 1 +101 1 +.names xv[10][0] yv[10][11] xv[10][1] yv[10][12] $abc$30358$new_n4511 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[10][14] xv[10][15] $abc$30358$new_n4515 $abc$30358$new_n4514 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n4516 xv[10][12] xv[10][13] $abc$30358$new_n4515 +111 1 +.names yv[10][20] xv[10][10] xv[10][11] $abc$30358$new_n4517 xv[10][9] $abc$30358$new_n4516 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +11111 1 +.names yv[10][19] xv[10][8] $abc$30358$new_n4518 yv[10][20] xv[10][9] $abc$30358$new_n4517 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[10][17] xv[10][6] xv[10][7] yv[10][18] $abc$30358$new_n4519 $abc$30358$new_n4518 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][15] xv[10][4] xv[10][5] yv[10][16] $abc$30358$new_n4520 $abc$30358$new_n4519 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[10][13] xv[10][2] xv[10][3] yv[10][14] $abc$30358$new_n4521 $abc$30358$new_n4520 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[10][11] xv[10][0] xv[10][1] yv[10][12] $abc$30358$new_n4521 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4526 xv[11][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27279 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] xv[10][16] $abc$30358$new_n4527 $abc$30358$new_n4514 $abc$30358$new_n4526 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n4505 xv[10][14] xv[10][15] $abc$30358$new_n4527 +111 1 +.names i_ce $abc$30358$new_n4531 xv[11][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27283 +001 1 +011 1 +100 1 +101 1 +.names xv[10][15] xv[10][14] $abc$30358$new_n4505 $abc$30358$new_n4515 $abc$30358$new_n4531 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1111 1 +.names i_ce xv[10][13] $abc$30358$new_n4536 xv[11][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27287 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][12] $abc$30358$new_n4516 $abc$30358$new_n4506 $abc$30358$new_n4536 +110 1 +.names i_ce xv[10][11] $abc$30358$new_n4540 xv[11][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27291 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][10] yv[10][20] $abc$30358$new_n4541 $abc$30358$new_n4517 $abc$30358$new_n4540 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[10][9] $abc$30358$new_n4507 $abc$30358$new_n4541 +10 1 +.names $abc$30358$new_n4543 i_ce xv[11][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27293 +001 1 +010 1 +011 1 +.names i_ce yv[10][20] xv[10][10] $abc$30358$new_n4517 $abc$30358$new_n4541 $abc$30358$new_n4543 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4545 xv[10][9] xv[11][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27295 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[10][20] yv[10][19] xv[10][8] $abc$30358$new_n4518 $abc$30358$new_n4507 $abc$30358$new_n4545 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][8] yv[10][19] $abc$30358$new_n4547 xv[11][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27297 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][7] yv[10][18] $abc$30358$new_n4508 $abc$30358$new_n4518 $abc$30358$new_n4547 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][7] yv[10][18] $abc$30358$new_n4549 xv[11][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27299 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] yv[10][17] xv[10][6] $abc$30358$new_n4519 $abc$30358$new_n4508 $abc$30358$new_n4549 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][6] yv[10][17] $abc$30358$new_n4551 xv[11][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27301 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][5] yv[10][16] $abc$30358$new_n4509 $abc$30358$new_n4519 $abc$30358$new_n4551 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][5] yv[10][16] $abc$30358$new_n4553 xv[11][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27303 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] yv[10][15] xv[10][4] $abc$30358$new_n4520 $abc$30358$new_n4509 $abc$30358$new_n4553 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][4] yv[10][15] $abc$30358$new_n4555 xv[11][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27305 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[10][20] xv[10][3] yv[10][14] $abc$30358$new_n4510 $abc$30358$new_n4520 $abc$30358$new_n4555 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[10][3] yv[10][14] $abc$30358$new_n4557 xv[11][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27307 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] xv[10][2] yv[10][13] $abc$30358$new_n4521 $abc$30358$new_n4511 $abc$30358$new_n4557 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][2] yv[10][13] $abc$30358$new_n4559 xv[11][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27309 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[10][20] $abc$30358$new_n4511 $abc$30358$new_n4521 $abc$30358$new_n4559 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4561 xv[11][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27311 +001 1 +011 1 +110 1 +111 1 +.names xv[10][1] yv[10][12] yv[10][20] xv[10][0] yv[10][11] $abc$30358$new_n4561 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[10][0] yv[10][11] xv[11][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27313 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4564 ph[11][19] ph[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27315 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[11][18] $abc$30358$new_n4565 $abc$30358$new_n4571 $abc$30358$new_n4564 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n4566 ph[11][16] ph[11][17] $abc$30358$new_n4565 +100 1 +.names yv[11][20] $abc$30358$new_n4567 ph[11][15] $abc$30358$new_n4566 +110 1 +.names $abc$30358$new_n4568 ph[11][13] ph[11][14] $abc$30358$new_n4567 +100 1 +.names $abc$30358$new_n4569 ph[11][9] ph[11][10] ph[11][11] ph[11][12] $abc$30358$new_n4568 +10000 1 +.names ph[11][7] ph[11][8] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4569 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names ph[11][4] ph[11][2] ph[11][3] ph[11][0] ph[11][1] $abc$30358$new_n4570 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[11][16] ph[11][17] $abc$30358$new_n4572 $abc$30358$new_n4571 +111 1 +.names $abc$30358$new_n4573 ph[11][15] yv[11][20] $abc$30358$new_n4572 +110 1 +.names $abc$30358$new_n4574 ph[11][6] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4573 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names ph[11][10] ph[11][11] ph[11][12] $abc$30358$new_n4575 $abc$30358$new_n4574 +1111 1 +.names ph[11][7] ph[11][8] ph[11][9] ph[11][13] ph[11][14] $abc$30358$new_n4575 +11111 1 +.names ph[11][4] ph[11][2] ph[11][3] ph[11][0] ph[11][1] $abc$30358$new_n4576 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_ce ph[11][18] $abc$30358$new_n4571 $abc$30358$new_n4565 ph[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27317 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4579 i_ce ph[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27319 +001 1 +010 1 +011 1 +.names i_ce ph[11][16] ph[11][17] $abc$30358$new_n4572 $abc$30358$new_n4566 $abc$30358$new_n4579 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[11][16] $abc$30358$new_n4572 $abc$30358$new_n4566 ph[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27321 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4582 ph[12][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27323 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[11][15] yv[11][20] $abc$30358$new_n4573 $abc$30358$new_n4567 $abc$30358$new_n4582 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4584 ph[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27325 +001 1 +011 1 +100 1 +101 1 +.names ph[11][14] ph[11][12] ph[11][13] $abc$30358$new_n4590 $abc$30358$new_n4585 $abc$30358$new_n4584 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11101 1 +11111 1 +.names ph[11][11] $abc$30358$new_n4586 $abc$30358$new_n4585 +11 1 +.names ph[11][10] $abc$30358$new_n4587 $abc$30358$new_n4586 +11 1 +.names ph[11][9] $abc$30358$new_n4588 $abc$30358$new_n4587 +11 1 +.names ph[11][8] $abc$30358$new_n4589 $abc$30358$new_n4588 +11 1 +.names ph[11][7] yv[11][20] ph[11][6] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4589 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$30358$new_n4591 ph[11][11] $abc$30358$new_n4590 +10 1 +.names $abc$30358$new_n4592 ph[11][10] $abc$30358$new_n4591 +10 1 +.names $abc$30358$new_n4593 ph[11][9] $abc$30358$new_n4592 +10 1 +.names $abc$30358$new_n4594 ph[11][8] $abc$30358$new_n4593 +10 1 +.names yv[11][20] ph[11][7] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4594 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names i_ce $abc$30358$new_n4596 ph[11][13] ph[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27327 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[11][12] $abc$30358$new_n4585 $abc$30358$new_n4590 $abc$30358$new_n4596 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[11][12] $abc$30358$new_n4590 $abc$30358$new_n4585 ph[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27329 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][11] $abc$30358$new_n4591 $abc$30358$new_n4586 ph[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27331 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][10] $abc$30358$new_n4592 $abc$30358$new_n4587 ph[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27333 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][9] $abc$30358$new_n4593 $abc$30358$new_n4588 ph[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27335 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[11][8] $abc$30358$new_n4594 $abc$30358$new_n4589 ph[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27337 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4603 ph[11][7] ph[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27339 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] ph[11][6] ph[11][5] $abc$30358$new_n4570 $abc$30358$new_n4576 $abc$30358$new_n4603 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4605 ph[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27341 +001 1 +011 1 +110 1 +111 1 +.names ph[11][6] yv[11][20] ph[11][5] $abc$30358$new_n4576 $abc$30358$new_n4570 $abc$30358$new_n4605 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11010 1 +.names i_ce $abc$30358$new_n4607 ph[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27343 +001 1 +011 1 +110 1 +111 1 +.names ph[11][5] yv[11][20] $abc$30358$new_n4576 $abc$30358$new_n4570 $abc$30358$new_n4607 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[11][4] $abc$30358$new_n4609 ph[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27345 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[11][20] ph[11][0] ph[11][1] ph[11][2] ph[11][3] $abc$30358$new_n4609 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4611 ph[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27347 +001 1 +011 1 +110 1 +111 1 +.names yv[11][20] ph[11][3] ph[11][0] ph[11][1] ph[11][2] $abc$30358$new_n4611 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4613 ph[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27349 +001 1 +011 1 +100 1 +101 1 +.names ph[11][2] yv[11][20] ph[11][0] ph[11][1] $abc$30358$new_n4613 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[11][20] ph[11][0] ph[11][1] ph[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27351 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[11][0] ph[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27353 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[11][20] yv[11][19] $abc$30358$new_n4617 yv[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27355 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][18] xv[11][20] $abc$30358$new_n4633 $abc$30358$new_n4618 $abc$30358$new_n4617 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[11][20] $abc$30358$new_n4619 yv[11][16] yv[11][17] $abc$30358$new_n4618 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][20] $abc$30358$new_n4628 $abc$30358$new_n4620 yv[11][12] $abc$30358$new_n4619 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[11][20] $abc$30358$new_n4662 yv[11][10] yv[11][11] $abc$30358$new_n4620 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[11][19] yv[11][7] $abc$30358$new_n4623 $abc$30358$new_n4622 +000 1 +001 1 +011 1 +101 1 +.names xv[11][17] yv[11][5] xv[11][18] yv[11][6] $abc$30358$new_n4624 $abc$30358$new_n4623 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][15] yv[11][3] xv[11][16] yv[11][4] $abc$30358$new_n4625 $abc$30358$new_n4624 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][14] yv[11][2] $abc$30358$new_n4626 $abc$30358$new_n4625 +000 1 +001 1 +011 1 +101 1 +.names xv[11][12] yv[11][0] xv[11][13] yv[11][1] $abc$30358$new_n4626 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names $abc$30358$new_n4631 $abc$30358$new_n4630 $abc$30358$new_n4629 $abc$30358$new_n4628 +111 1 +.names xv[11][20] yv[11][13] $abc$30358$new_n4629 +01 1 +10 1 +.names xv[11][20] yv[11][15] $abc$30358$new_n4630 +01 1 +10 1 +.names xv[11][20] yv[11][14] $abc$30358$new_n4631 +01 1 +10 1 +.names xv[11][20] $abc$30358$new_n6046 yv[11][16] yv[11][17] $abc$30358$new_n4633 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] yv[11][8] yv[11][9] $abc$30358$new_n4637 $abc$30358$new_n4636 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[11][6] xv[11][18] xv[11][19] yv[11][7] $abc$30358$new_n4638 $abc$30358$new_n4637 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[11][17] yv[11][5] $abc$30358$new_n4639 $abc$30358$new_n4638 +001 1 +100 1 +101 1 +111 1 +.names xv[11][15] xv[11][16] yv[11][3] yv[11][4] $abc$30358$new_n4640 $abc$30358$new_n4639 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[11][14] yv[11][2] $abc$30358$new_n4641 $abc$30358$new_n4640 +001 1 +100 1 +101 1 +111 1 +.names xv[11][12] xv[11][13] yv[11][0] yv[11][1] $abc$30358$new_n4641 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[11][20] yv[11][18] $abc$30358$new_n4644 yv[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27357 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] $abc$30358$new_n4618 $abc$30358$new_n4633 $abc$30358$new_n4644 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[11][20] yv[11][17] $abc$30358$new_n4646 yv[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27359 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][16] xv[11][20] $abc$30358$new_n6046 $abc$30358$new_n4619 $abc$30358$new_n4646 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4648 yv[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27361 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][16] yv[11][20] $abc$30358$new_n6046 $abc$30358$new_n4619 $abc$30358$new_n4648 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n4650 $abc$30358$new_n4630 yv[12][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27363 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] yv[11][14] xv[11][20] $abc$30358$new_n4652 $abc$30358$new_n4651 $abc$30358$new_n4650 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names xv[11][20] yv[11][12] yv[11][13] $abc$30358$new_n4620 $abc$30358$new_n4651 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] $abc$30358$new_n4653 yv[11][12] yv[11][13] $abc$30358$new_n4652 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[11][20] $abc$30358$new_n4636 yv[11][10] yv[11][11] $abc$30358$new_n4653 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4655 yv[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27365 +001 1 +011 1 +100 1 +101 1 +.names $abc$30358$new_n4631 yv[11][20] $abc$30358$new_n4652 $abc$30358$new_n4651 $abc$30358$new_n4655 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n4657 $abc$30358$new_n4629 yv[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27367 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[11][20] yv[11][12] xv[11][20] $abc$30358$new_n4653 $abc$30358$new_n4620 $abc$30358$new_n4657 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4659 yv[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27369 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][12] yv[11][20] $abc$30358$new_n4653 $abc$30358$new_n4620 $abc$30358$new_n4659 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[11][20] yv[11][11] $abc$30358$new_n4661 yv[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27371 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][10] xv[11][20] $abc$30358$new_n4662 $abc$30358$new_n4636 $abc$30358$new_n4661 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[11][20] $abc$30358$new_n4622 yv[11][8] yv[11][9] $abc$30358$new_n4662 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$30358$new_n4664 yv[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27373 +001 1 +011 1 +110 1 +111 1 +.names yv[11][20] xv[11][20] yv[11][10] $abc$30358$new_n4662 $abc$30358$new_n4636 $abc$30358$new_n4664 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][20] yv[11][9] $abc$30358$new_n4666 yv[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27375 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][8] xv[11][20] $abc$30358$new_n4637 $abc$30358$new_n4622 $abc$30358$new_n4666 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n4668 yv[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27377 +001 1 +011 1 +100 1 +101 1 +.names xv[11][20] yv[11][8] yv[11][20] $abc$30358$new_n4637 $abc$30358$new_n4622 $abc$30358$new_n4668 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01110 1 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][19] yv[11][7] $abc$30358$new_n4670 yv[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27379 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] yv[11][6] xv[11][18] $abc$30358$new_n4638 $abc$30358$new_n4623 $abc$30358$new_n4670 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][18] yv[11][6] $abc$30358$new_n4672 yv[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27381 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][17] yv[11][5] $abc$30358$new_n4639 $abc$30358$new_n4624 $abc$30358$new_n4672 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4674 yv[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27383 +001 1 +011 1 +110 1 +111 1 +.names xv[11][17] yv[11][5] yv[11][20] $abc$30358$new_n4639 $abc$30358$new_n4624 $abc$30358$new_n4674 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[11][16] yv[11][4] $abc$30358$new_n4676 yv[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27385 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][15] yv[11][3] $abc$30358$new_n4640 $abc$30358$new_n4625 $abc$30358$new_n4676 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[11][15] yv[11][3] $abc$30358$new_n4678 yv[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27387 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4625 $abc$30358$new_n4640 $abc$30358$new_n4678 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[11][14] yv[11][2] $abc$30358$new_n4680 yv[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27389 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4626 $abc$30358$new_n4641 $abc$30358$new_n4680 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4682 yv[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27391 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][1] yv[11][20] yv[11][0] xv[11][12] $abc$30358$new_n4682 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[11][12] yv[11][0] yv[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27393 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4685 xv[12][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27395 +001 1 +011 1 +110 1 +111 1 +.names xv[11][19] $abc$30358$new_n4697 yv[11][20] xv[11][18] $abc$30358$new_n4686 $abc$30358$new_n4685 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][16] xv[11][17] $abc$30358$new_n4687 $abc$30358$new_n4686 +111 1 +.names $abc$30358$new_n4695 xv[11][12] xv[11][13] $abc$30358$new_n4688 $abc$30358$new_n4687 +1110 1 +.names xv[11][11] $abc$30358$new_n4689 yv[11][20] xv[11][10] $abc$30358$new_n4688 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +1000 1 +1001 1 +.names xv[11][10] yv[11][20] xv[11][8] xv[11][9] $abc$30358$new_n4690 $abc$30358$new_n4689 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[11][7] yv[11][19] $abc$30358$new_n4691 $abc$30358$new_n4690 +000 1 +001 1 +011 1 +101 1 +.names xv[11][5] yv[11][17] xv[11][6] yv[11][18] $abc$30358$new_n4692 $abc$30358$new_n4691 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][3] yv[11][15] xv[11][4] yv[11][16] $abc$30358$new_n4693 $abc$30358$new_n4692 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[11][2] yv[11][14] $abc$30358$new_n4694 $abc$30358$new_n4693 +000 1 +001 1 +011 1 +101 1 +.names xv[11][0] yv[11][12] xv[11][1] yv[11][13] $abc$30358$new_n4694 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[11][20] xv[11][14] xv[11][15] $abc$30358$new_n4695 +011 1 +100 1 +.names yv[11][20] xv[11][17] $abc$30358$new_n4699 xv[11][18] xv[11][16] $abc$30358$new_n4697 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n4700 yv[11][20] xv[11][13] xv[11][14] xv[11][15] $abc$30358$new_n4699 +10000 1 +11111 1 +.names yv[11][20] xv[11][12] $abc$30358$new_n4701 $abc$30358$new_n4700 +000 1 +110 1 +.names yv[11][20] $abc$30358$new_n4707 $abc$30358$new_n4702 xv[11][8] $abc$30358$new_n4701 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[11][18] xv[11][6] xv[11][7] yv[11][19] $abc$30358$new_n4703 $abc$30358$new_n4702 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11][16] xv[11][4] xv[11][5] yv[11][17] $abc$30358$new_n4704 $abc$30358$new_n4703 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[11][14] xv[11][2] xv[11][3] yv[11][15] $abc$30358$new_n4705 $abc$30358$new_n4704 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[11][12] xv[11][0] xv[11][1] yv[11][13] $abc$30358$new_n4705 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[11][20] xv[11][9] xv[11][10] xv[11][11] $abc$30358$new_n4707 +0000 1 +1111 1 +.names i_ce $abc$30358$new_n4712 xv[12][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27399 +001 1 +011 1 +110 1 +111 1 +.names xv[11][17] yv[11][20] xv[11][16] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n4712 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4714 i_ce xv[12][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27401 +001 1 +010 1 +011 1 +.names i_ce yv[11][20] xv[11][16] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n4714 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4716 xv[12][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27403 +001 1 +011 1 +110 1 +111 1 +.names xv[11][15] xv[11][14] $abc$30358$new_n4717 $abc$30358$new_n4718 $abc$30358$new_n4716 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names xv[11][12] xv[11][13] $abc$30358$new_n4688 $abc$30358$new_n4717 +110 1 +.names yv[11][20] $abc$30358$new_n4701 xv[11][12] xv[11][13] $abc$30358$new_n4718 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4722 xv[12][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27407 +001 1 +011 1 +110 1 +111 1 +.names xv[11][13] yv[11][20] $abc$30358$new_n4700 $abc$30358$new_n4688 $abc$30358$new_n4722 +0000 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][11] xv[11][10] $abc$30358$new_n4726 xv[12][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27411 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[11][9] $abc$30358$new_n4728 $abc$30358$new_n4727 $abc$30358$new_n4726 +100 1 +.names yv[11][20] $abc$30358$new_n4690 xv[11][8] $abc$30358$new_n4727 +000 1 +010 1 +011 1 +.names yv[11][20] $abc$30358$new_n4702 xv[11][8] $abc$30358$new_n4728 +100 1 +110 1 +111 1 +.names i_ce xv[11][10] $abc$30358$new_n4726 xv[12][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27413 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][9] $abc$30358$new_n4728 $abc$30358$new_n4727 xv[12][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27415 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4732 i_ce xv[12][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27417 +001 1 +010 1 +011 1 +.names i_ce yv[11][20] xv[11][8] $abc$30358$new_n4702 $abc$30358$new_n4690 $abc$30358$new_n4732 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[11][7] yv[11][19] $abc$30358$new_n4734 xv[12][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] yv[11][18] xv[11][6] $abc$30358$new_n4703 $abc$30358$new_n4691 $abc$30358$new_n4734 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][6] yv[11][18] $abc$30358$new_n4736 xv[12][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27421 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][5] yv[11][17] $abc$30358$new_n4692 $abc$30358$new_n4703 $abc$30358$new_n4736 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][5] yv[11][17] $abc$30358$new_n4738 xv[12][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] yv[11][16] xv[11][4] $abc$30358$new_n4704 $abc$30358$new_n4692 $abc$30358$new_n4738 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][4] yv[11][16] $abc$30358$new_n4740 xv[12][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27425 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[11][20] xv[11][3] yv[11][15] $abc$30358$new_n4693 $abc$30358$new_n4704 $abc$30358$new_n4740 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[11][3] yv[11][15] $abc$30358$new_n4742 xv[12][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27427 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] xv[11][2] yv[11][14] $abc$30358$new_n4705 $abc$30358$new_n4694 $abc$30358$new_n4742 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][2] yv[11][14] $abc$30358$new_n4744 xv[12][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27429 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[11][20] $abc$30358$new_n4694 $abc$30358$new_n4705 $abc$30358$new_n4744 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4746 xv[12][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27431 +001 1 +011 1 +110 1 +111 1 +.names xv[11][1] yv[11][13] yv[11][20] xv[11][0] yv[11][12] $abc$30358$new_n4746 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[11][0] yv[11][12] xv[12][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27433 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[12][19] $abc$30358$new_n4749 ph[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27435 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[12][18] yv[12][20] $abc$30358$new_n4750 $abc$30358$new_n4754 $abc$30358$new_n4749 +0110 1 +0111 1 +1001 1 +1011 1 +.names $abc$30358$new_n4751 ph[12][15] ph[12][16] ph[12][17] $abc$30358$new_n4750 +1000 1 +.names $abc$30358$new_n4752 ph[12][11] ph[12][12] ph[12][13] ph[12][14] $abc$30358$new_n4751 +10000 1 +.names $abc$30358$new_n4753 ph[12][7] ph[12][8] ph[12][9] ph[12][10] $abc$30358$new_n4752 +10000 1 +.names ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4753 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[12][15] ph[12][16] $abc$30358$new_n4757 $abc$30358$new_n4755 $abc$30358$new_n4754 +1111 1 +.names $abc$30358$new_n4756 ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4755 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[12][7] ph[12][8] ph[12][9] ph[12][14] ph[12][17] $abc$30358$new_n4756 +11111 1 +.names ph[12][10] ph[12][11] ph[12][12] ph[12][13] $abc$30358$new_n4757 +1111 1 +.names $abc$30358$new_n4759 ph[13][18] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27437 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[12][18] yv[12][20] $abc$30358$new_n4754 $abc$30358$new_n4750 $abc$30358$new_n4759 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4761 ph[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27439 +001 1 +011 1 +110 1 +111 1 +.names ph[12][17] ph[12][16] $abc$30358$new_n4767 ph[12][15] $abc$30358$new_n4762 $abc$30358$new_n4761 +00100 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names ph[12][15] $abc$30358$new_n4763 $abc$30358$new_n4762 +11 1 +.names ph[12][14] $abc$30358$new_n4757 $abc$30358$new_n4764 $abc$30358$new_n4763 +111 1 +.names ph[12][9] $abc$30358$new_n4765 $abc$30358$new_n4764 +11 1 +.names ph[12][7] ph[12][8] $abc$30358$new_n4766 $abc$30358$new_n4765 +111 1 +.names ph[12][6] yv[12][20] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4766 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$30358$new_n4768 ph[12][12] ph[12][13] ph[12][14] $abc$30358$new_n4767 +1000 1 +.names $abc$30358$new_n4769 ph[12][9] ph[12][10] ph[12][11] $abc$30358$new_n4768 +1000 1 +.names $abc$30358$new_n4770 ph[12][7] ph[12][8] $abc$30358$new_n4769 +100 1 +.names yv[12][20] $abc$30358$new_n4753 $abc$30358$new_n4770 +11 1 +.names i_ce $abc$30358$new_n4772 ph[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27441 +001 1 +011 1 +100 1 +101 1 +.names ph[12][16] $abc$30358$new_n4762 $abc$30358$new_n4767 ph[12][15] $abc$30358$new_n4772 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[12][15] $abc$30358$new_n4763 $abc$30358$new_n4767 ph[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27443 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4775 ph[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27445 +001 1 +011 1 +110 1 +111 1 +.names ph[12][12] ph[12][14] ph[12][13] $abc$30358$new_n4768 $abc$30358$new_n4776 $abc$30358$new_n4775 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[12][10] ph[12][11] $abc$30358$new_n4764 $abc$30358$new_n4776 +111 1 +.names i_ce $abc$30358$new_n4778 ph[12][13] ph[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27447 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][12] $abc$30358$new_n4776 $abc$30358$new_n4768 $abc$30358$new_n4778 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[12][12] $abc$30358$new_n4768 $abc$30358$new_n4776 ph[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27449 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][11] $abc$30358$new_n4768 $abc$30358$new_n4781 $abc$30358$auto$rtlil.cc:2693:MuxGate$27451 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[12][10] ph[12][11] $abc$30358$new_n4764 $abc$30358$new_n4769 ph[12][9] $abc$30358$new_n4781 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4783 ph[12][10] ph[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27453 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[12][9] $abc$30358$new_n4769 $abc$30358$new_n4765 $abc$30358$new_n4783 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[12][9] $abc$30358$new_n4765 $abc$30358$new_n4769 ph[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27455 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4786 ph[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27457 +001 1 +011 1 +100 1 +101 1 +.names ph[12][7] ph[12][8] $abc$30358$new_n4766 $abc$30358$new_n4770 $abc$30358$new_n4786 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce ph[12][7] $abc$30358$new_n4766 $abc$30358$new_n4770 ph[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27459 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4789 ph[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27461 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] ph[12][6] ph[12][5] ph[12][3] ph[12][4] $abc$30358$new_n4789 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4791 ph[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27463 +001 1 +011 1 +110 1 +111 1 +.names ph[12][5] yv[12][20] ph[12][3] ph[12][4] $abc$30358$new_n4791 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[12][20] ph[12][3] ph[12][4] ph[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27465 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[12][3] ph[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27467 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[12][2] ph[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27469 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][1] ph[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27471 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[12][0] ph[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27473 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][20] yv[12][19] $abc$30358$new_n4798 yv[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27475 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][18] xv[12][20] $abc$30358$new_n4813 $abc$30358$new_n4799 $abc$30358$new_n4798 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[12][20] $abc$30358$new_n6052 yv[12][16] yv[12][17] $abc$30358$new_n4799 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][20] yv[12][8] yv[12][9] $abc$30358$new_n4803 $abc$30358$new_n4802 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names yv[12][6] xv[12][19] xv[12][20] yv[12][7] $abc$30358$new_n4804 $abc$30358$new_n4803 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names xv[12][18] yv[12][5] $abc$30358$new_n4805 $abc$30358$new_n4804 +001 1 +100 1 +101 1 +111 1 +.names xv[12][16] xv[12][17] yv[12][3] yv[12][4] $abc$30358$new_n4806 $abc$30358$new_n4805 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[12][15] yv[12][2] $abc$30358$new_n4807 $abc$30358$new_n4806 +001 1 +100 1 +101 1 +111 1 +.names xv[12][13] xv[12][14] yv[12][0] yv[12][1] $abc$30358$new_n4807 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[12][20] yv[12][13] $abc$30358$new_n4810 +01 1 +10 1 +.names xv[12][20] yv[12][15] $abc$30358$new_n4811 +01 1 +10 1 +.names xv[12][20] yv[12][14] $abc$30358$new_n4812 +01 1 +10 1 +.names xv[12][20] $abc$30358$new_n4814 yv[12][16] yv[12][17] $abc$30358$new_n4813 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[12][20] $abc$30358$new_n4822 $abc$30358$new_n4815 yv[12][12] $abc$30358$new_n4814 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[12][20] yv[12][10] yv[12][11] $abc$30358$new_n4816 $abc$30358$new_n4821 $abc$30358$new_n4815 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names yv[12][8] yv[12][9] xv[12][20] yv[12][7] $abc$30358$new_n4817 $abc$30358$new_n4816 +00100 1 +00110 1 +00111 1 +11010 1 +.names xv[12][18] yv[12][5] xv[12][19] yv[12][6] $abc$30358$new_n4818 $abc$30358$new_n4817 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][16] yv[12][3] xv[12][17] yv[12][4] $abc$30358$new_n4819 $abc$30358$new_n4818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][15] yv[12][2] $abc$30358$new_n4820 $abc$30358$new_n4819 +000 1 +001 1 +011 1 +101 1 +.names xv[12][13] yv[12][0] xv[12][14] yv[12][1] $abc$30358$new_n4820 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[12][8] yv[12][9] $abc$30358$new_n4821 +00 1 +.names $abc$30358$new_n4812 $abc$30358$new_n4811 $abc$30358$new_n4810 $abc$30358$new_n4822 +111 1 +.names i_ce xv[12][20] yv[12][18] $abc$30358$new_n4824 yv[13][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27477 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] $abc$30358$new_n4799 $abc$30358$new_n4813 $abc$30358$new_n4824 +010 1 +011 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n4829 yv[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27481 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][16] $abc$30358$new_n4814 $abc$30358$new_n6052 $abc$30358$new_n4829 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4831 $abc$30358$new_n4811 yv[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27483 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[12][14] yv[12][20] $abc$30358$new_n4834 xv[12][20] $abc$30358$new_n4832 $abc$30358$new_n4831 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names xv[12][20] $abc$30358$new_n4833 yv[12][12] yv[12][13] $abc$30358$new_n4832 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[12][20] $abc$30358$new_n4802 yv[12][10] yv[12][11] $abc$30358$new_n4833 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names yv[12][20] xv[12][20] yv[12][12] yv[12][13] $abc$30358$new_n4815 $abc$30358$new_n4834 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4836 yv[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27485 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4812 $abc$30358$new_n4834 yv[12][20] $abc$30358$new_n4832 $abc$30358$new_n4836 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n4838 $abc$30358$new_n4810 yv[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27487 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[12][20] yv[12][12] xv[12][20] $abc$30358$new_n4815 $abc$30358$new_n4833 $abc$30358$new_n4838 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n4840 yv[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27489 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][12] $abc$30358$new_n4815 $abc$30358$new_n4833 $abc$30358$new_n4840 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][20] yv[12][11] $abc$30358$new_n4842 yv[13][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27491 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][10] xv[12][20] $abc$30358$new_n4843 $abc$30358$new_n4802 $abc$30358$new_n4842 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n4816 $abc$30358$new_n4821 xv[12][20] $abc$30358$new_n4843 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n4845 yv[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27493 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][20] yv[12][10] $abc$30358$new_n4843 $abc$30358$new_n4802 $abc$30358$new_n4845 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[12][20] yv[12][9] $abc$30358$new_n4847 yv[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27495 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][8] xv[12][20] $abc$30358$new_n4803 $abc$30358$new_n4848 $abc$30358$new_n4847 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[12][20] yv[12][7] $abc$30358$new_n4817 $abc$30358$new_n4848 +000 1 +001 1 +011 1 +101 1 +.names i_ce $abc$30358$new_n4850 yv[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27497 +001 1 +011 1 +110 1 +111 1 +.names xv[12][20] yv[12][8] yv[12][20] $abc$30358$new_n4803 $abc$30358$new_n4848 $abc$30358$new_n4850 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[12][20] yv[12][7] $abc$30358$new_n4852 yv[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27499 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] yv[12][6] xv[12][19] $abc$30358$new_n4804 $abc$30358$new_n4817 $abc$30358$new_n4852 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][19] yv[12][6] $abc$30358$new_n4854 yv[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27501 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][18] yv[12][5] $abc$30358$new_n4805 $abc$30358$new_n4818 $abc$30358$new_n4854 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4856 yv[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27503 +001 1 +011 1 +110 1 +111 1 +.names xv[12][18] yv[12][5] yv[12][20] $abc$30358$new_n4805 $abc$30358$new_n4818 $abc$30358$new_n4856 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[12][17] yv[12][4] $abc$30358$new_n4858 yv[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27505 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][16] yv[12][3] $abc$30358$new_n4806 $abc$30358$new_n4819 $abc$30358$new_n4858 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[12][16] yv[12][3] $abc$30358$new_n4860 yv[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27507 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4819 $abc$30358$new_n4806 $abc$30358$new_n4860 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[12][15] yv[12][2] $abc$30358$new_n4862 yv[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27509 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4820 $abc$30358$new_n4807 $abc$30358$new_n4862 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n4864 yv[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27511 +001 1 +011 1 +110 1 +111 1 +.names xv[12][14] yv[12][1] yv[12][20] yv[12][0] xv[12][13] $abc$30358$new_n4864 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[12][13] yv[12][0] yv[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27513 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[12][19] $abc$30358$new_n4867 xv[13][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27515 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[12][18] yv[12][20] $abc$30358$new_n4878 $abc$30358$new_n4889 $abc$30358$new_n4869 $abc$30358$new_n4867 +10011 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n4870 xv[12][14] xv[12][15] $abc$30358$new_n4869 +111 1 +.names yv[12][20] xv[12][12] xv[12][13] $abc$30358$new_n4871 $abc$30358$new_n4870 +0110 1 +1000 1 +.names yv[12][20] $abc$30358$new_n4872 xv[12][10] xv[12][11] $abc$30358$new_n4871 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[12][20] $abc$30358$new_n4873 xv[12][7] xv[12][8] xv[12][9] $abc$30358$new_n4872 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[12][5] yv[12][18] xv[12][6] yv[12][19] $abc$30358$new_n4874 $abc$30358$new_n4873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][3] yv[12][16] xv[12][4] yv[12][17] $abc$30358$new_n4875 $abc$30358$new_n4874 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[12][2] yv[12][15] $abc$30358$new_n4876 $abc$30358$new_n4875 +000 1 +001 1 +011 1 +101 1 +.names xv[12][0] yv[12][13] xv[12][1] yv[12][14] $abc$30358$new_n4876 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[12][16] xv[12][17] $abc$30358$new_n4879 $abc$30358$new_n4878 +111 1 +.names $abc$30358$new_n4888 $abc$30358$new_n6056 $abc$30358$new_n4879 +10 1 +.names yv[12][20] xv[12][8] xv[12][7] $abc$30358$new_n4883 $abc$30358$new_n4882 +0000 1 +0010 1 +0011 1 +1110 1 +.names yv[12][19] xv[12][6] $abc$30358$new_n4884 $abc$30358$new_n4883 +001 1 +100 1 +101 1 +111 1 +.names yv[12][17] xv[12][4] xv[12][5] yv[12][18] $abc$30358$new_n4885 $abc$30358$new_n4884 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[12][15] xv[12][2] xv[12][3] yv[12][16] $abc$30358$new_n4886 $abc$30358$new_n4885 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[12][13] xv[12][0] xv[12][1] yv[12][14] $abc$30358$new_n4886 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[12][20] xv[12][12] xv[12][13] xv[12][14] xv[12][15] $abc$30358$new_n4888 +00000 1 +11111 1 +.names yv[12][20] xv[12][16] xv[12][17] $abc$30358$new_n4889 +011 1 +100 1 +.names i_ce xv[12][17] $abc$30358$new_n4894 xv[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27519 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[12][16] yv[12][20] $abc$30358$new_n4869 $abc$30358$new_n4879 $abc$30358$new_n4894 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$30358$new_n4896 i_ce xv[13][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27521 +001 1 +010 1 +011 1 +.names i_ce yv[12][20] xv[12][16] $abc$30358$new_n4879 $abc$30358$new_n4869 $abc$30358$new_n4896 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n4898 xv[13][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27523 +001 1 +011 1 +110 1 +111 1 +.names xv[12][15] yv[12][20] xv[12][14] $abc$30358$new_n4870 $abc$30358$new_n4899 $abc$30358$new_n4898 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[12][13] xv[12][12] $abc$30358$new_n6056 $abc$30358$new_n4899 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n4901 i_ce xv[13][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27525 +001 1 +010 1 +011 1 +.names i_ce xv[12][14] yv[12][20] $abc$30358$new_n4870 $abc$30358$new_n4899 $abc$30358$new_n4901 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n4903 xv[13][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27527 +001 1 +011 1 +110 1 +111 1 +.names xv[12][13] xv[12][12] $abc$30358$new_n4871 $abc$30358$new_n6056 $abc$30358$new_n4903 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[12][11] xv[12][10] $abc$30358$new_n4907 xv[13][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27531 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[12][9] $abc$30358$new_n4908 $abc$30358$new_n4882 yv[12][20] $abc$30358$new_n4907 +1000 1 +1010 1 +1011 1 +.names yv[12][20] xv[12][8] xv[12][7] $abc$30358$new_n4873 $abc$30358$new_n4908 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names i_ce xv[12][10] $abc$30358$new_n4907 xv[13][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27533 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4911 xv[13][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27535 +001 1 +011 1 +110 1 +111 1 +.names xv[12][9] $abc$30358$new_n4908 yv[12][20] $abc$30358$new_n4882 $abc$30358$new_n4911 +0000 1 +0001 1 +0011 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n4916 xv[13][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27539 +001 1 +011 1 +100 1 +101 1 +.names yv[12][20] xv[12][7] $abc$30358$new_n4883 $abc$30358$new_n4873 $abc$30358$new_n4916 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[12][6] yv[12][19] $abc$30358$new_n4918 xv[13][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27541 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][5] yv[12][18] $abc$30358$new_n4874 $abc$30358$new_n4884 $abc$30358$new_n4918 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][5] yv[12][18] $abc$30358$new_n4920 xv[13][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27543 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] yv[12][17] xv[12][4] $abc$30358$new_n4885 $abc$30358$new_n4874 $abc$30358$new_n4920 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][4] yv[12][17] $abc$30358$new_n4922 xv[13][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27545 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][3] yv[12][16] $abc$30358$new_n4875 $abc$30358$new_n4885 $abc$30358$new_n4922 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[12][3] yv[12][16] $abc$30358$new_n4924 xv[13][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27547 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] xv[12][2] yv[12][15] $abc$30358$new_n4886 $abc$30358$new_n4876 $abc$30358$new_n4924 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[12][2] yv[12][15] $abc$30358$new_n4926 xv[13][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27549 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[12][20] $abc$30358$new_n4876 $abc$30358$new_n4886 $abc$30358$new_n4926 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n4928 xv[13][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27551 +001 1 +011 1 +110 1 +111 1 +.names xv[12][1] yv[12][14] yv[12][20] xv[12][0] yv[12][13] $abc$30358$new_n4928 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[12][0] yv[12][13] xv[13][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27553 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n4931 ph[13][19] ph[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27555 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[13][18] $abc$30358$new_n4932 $abc$30358$new_n4938 $abc$30358$new_n4931 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n4933 ph[13][17] $abc$30358$new_n4932 +10 1 +.names $abc$30358$new_n4937 $abc$30358$new_n4934 ph[13][13] ph[13][16] $abc$30358$new_n4933 +1100 1 +.names $abc$30358$new_n4952 ph[13][14] ph[13][15] $abc$30358$new_n4934 +100 1 +.names ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4935 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[13][9] ph[13][10] ph[13][11] ph[13][12] $abc$30358$new_n4937 +0000 1 +.names ph[13][17] $abc$30358$new_n4939 $abc$30358$new_n4938 +11 1 +.names $abc$30358$new_n4956 ph[13][13] ph[13][16] $abc$30358$new_n4940 $abc$30358$new_n4939 +1111 1 +.names $abc$30358$new_n4958 ph[13][14] ph[13][15] $abc$30358$new_n4940 +111 1 +.names ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4941 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce ph[13][18] $abc$30358$new_n4938 $abc$30358$new_n4932 ph[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27557 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][17] $abc$30358$new_n4939 $abc$30358$new_n4933 ph[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27559 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4947 ph[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27561 +001 1 +011 1 +110 1 +111 1 +.names ph[13][14] ph[13][16] ph[13][15] $abc$30358$new_n4955 $abc$30358$new_n4948 $abc$30358$new_n4947 +00001 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n4949 ph[13][13] $abc$30358$new_n4948 +10 1 +.names $abc$30358$new_n4950 ph[13][11] ph[13][12] $abc$30358$new_n4949 +100 1 +.names $abc$30358$new_n4951 ph[13][10] $abc$30358$new_n4950 +10 1 +.names $abc$30358$new_n4952 ph[13][9] $abc$30358$new_n4951 +10 1 +.names $abc$30358$new_n4953 ph[13][8] $abc$30358$new_n4952 +10 1 +.names $abc$30358$new_n4954 ph[13][6] ph[13][7] $abc$30358$new_n4953 +100 1 +.names yv[13][20] $abc$30358$new_n4935 $abc$30358$new_n4954 +11 1 +.names ph[13][13] $abc$30358$new_n4956 $abc$30358$new_n4955 +11 1 +.names ph[13][10] ph[13][11] ph[13][12] $abc$30358$new_n4957 $abc$30358$new_n4956 +1111 1 +.names ph[13][9] $abc$30358$new_n4958 $abc$30358$new_n4957 +11 1 +.names ph[13][8] $abc$30358$new_n4959 $abc$30358$new_n4958 +11 1 +.names ph[13][6] ph[13][7] $abc$30358$new_n4960 $abc$30358$new_n4959 +111 1 +.names $abc$30358$new_n4941 yv[13][20] $abc$30358$new_n4960 +10 1 +.names i_ce $abc$30358$new_n4962 ph[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27563 +001 1 +011 1 +110 1 +111 1 +.names ph[13][14] ph[13][15] $abc$30358$new_n4955 $abc$30358$new_n4948 $abc$30358$new_n4962 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[13][14] $abc$30358$new_n4955 $abc$30358$new_n4948 ph[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27565 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][13] $abc$30358$new_n4956 $abc$30358$new_n4949 ph[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27567 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n4966 i_ce ph[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27569 +001 1 +010 1 +011 1 +.names i_ce ph[13][11] ph[13][12] $abc$30358$new_n4967 $abc$30358$new_n4950 $abc$30358$new_n4966 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ph[13][10] $abc$30358$new_n4957 $abc$30358$new_n4967 +11 1 +.names i_ce ph[13][11] $abc$30358$new_n4967 $abc$30358$new_n4950 ph[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27571 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][10] $abc$30358$new_n4951 $abc$30358$new_n4957 ph[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27573 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][9] $abc$30358$new_n4952 $abc$30358$new_n4958 ph[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27575 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[13][8] $abc$30358$new_n4953 $abc$30358$new_n4959 ph[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27577 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4973 ph[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27579 +001 1 +011 1 +100 1 +101 1 +.names ph[13][7] ph[13][6] $abc$30358$new_n4954 $abc$30358$new_n4960 $abc$30358$new_n4973 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[13][6] $abc$30358$new_n4954 $abc$30358$new_n4960 ph[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27581 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n4976 ph[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27583 +001 1 +011 1 +100 1 +101 1 +.names yv[13][20] ph[13][5] ph[13][4] ph[13][2] ph[13][3] $abc$30358$new_n4976 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n4978 ph[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27585 +001 1 +011 1 +110 1 +111 1 +.names ph[13][4] yv[13][20] ph[13][2] ph[13][3] $abc$30358$new_n4978 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[13][20] ph[13][2] ph[13][3] ph[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27587 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[13][2] ph[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27589 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[13][1] ph[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27591 +001 1 +011 1 +110 1 +111 1 +.names i_ce ph[13][0] ph[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27593 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[13][20] yv[13][19] $abc$30358$new_n4984 yv[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27595 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][18] xv[13][20] $abc$30358$new_n4996 $abc$30358$new_n4985 $abc$30358$new_n4984 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[13][20] $abc$30358$new_n6063 yv[13][16] yv[13][17] $abc$30358$new_n4985 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][20] yv[13][10] yv[13][11] $abc$30358$new_n4989 $abc$30358$new_n4994 $abc$30358$new_n4988 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[13][20] yv[13][8] yv[13][9] $abc$30358$new_n4990 $abc$30358$new_n4989 +0110 1 +1000 1 +.names xv[13][20] $abc$30358$new_n4991 yv[13][6] yv[13][7] $abc$30358$new_n4990 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[13][18] yv[13][4] xv[13][19] yv[13][5] $abc$30358$new_n4992 $abc$30358$new_n4991 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][16] yv[13][2] xv[13][17] yv[13][3] $abc$30358$new_n4993 $abc$30358$new_n4992 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][14] yv[13][0] xv[13][15] yv[13][1] $abc$30358$new_n4993 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[13][8] yv[13][9] $abc$30358$new_n4994 +00 1 +.names xv[13][20] $abc$30358$new_n4997 yv[13][16] yv[13][17] $abc$30358$new_n4996 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] yv[13][14] yv[13][15] $abc$30358$new_n4998 $abc$30358$new_n5005 $abc$30358$new_n4997 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][20] yv[13][12] yv[13][13] $abc$30358$new_n4999 $abc$30358$new_n4998 +0000 1 +1110 1 +.names xv[13][20] $abc$30358$new_n5000 yv[13][10] yv[13][11] $abc$30358$new_n4999 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] $abc$30358$new_n5001 yv[13][8] yv[13][9] $abc$30358$new_n5000 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][20] $abc$30358$new_n5002 yv[13][6] yv[13][7] $abc$30358$new_n5001 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[13][18] xv[13][19] yv[13][4] yv[13][5] $abc$30358$new_n5003 $abc$30358$new_n5002 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[13][16] xv[13][17] yv[13][2] yv[13][3] $abc$30358$new_n5004 $abc$30358$new_n5003 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[13][14] xv[13][15] yv[13][0] yv[13][1] $abc$30358$new_n5004 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[13][12] yv[13][13] $abc$30358$new_n5005 +00 1 +.names i_ce xv[13][20] yv[13][18] $abc$30358$new_n5007 yv[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27597 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n4985 $abc$30358$new_n4996 $abc$30358$new_n5007 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[13][20] yv[13][17] $abc$30358$new_n5009 yv[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27599 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][16] xv[13][20] $abc$30358$new_n4997 $abc$30358$new_n6063 $abc$30358$new_n5009 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5011 yv[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27601 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][16] yv[13][20] $abc$30358$new_n4997 $abc$30358$new_n6063 $abc$30358$new_n5011 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][15] $abc$30358$new_n5013 yv[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27603 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][14] yv[13][20] $abc$30358$new_n5015 xv[13][20] $abc$30358$new_n5014 $abc$30358$new_n5013 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +.names $abc$30358$new_n4998 $abc$30358$new_n5005 xv[13][20] $abc$30358$new_n5014 +001 1 +010 1 +011 1 +.names yv[13][20] xv[13][20] yv[13][12] yv[13][13] $abc$30358$new_n4988 $abc$30358$new_n5015 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[13][20] yv[13][14] $abc$30358$new_n5017 yv[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27605 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5015 $abc$30358$new_n5014 yv[13][20] $abc$30358$new_n5017 +000 1 +001 1 +011 1 +.names i_ce xv[13][20] yv[13][13] $abc$30358$new_n5019 yv[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27607 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][12] xv[13][20] $abc$30358$new_n4999 $abc$30358$new_n4988 $abc$30358$new_n5019 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5021 yv[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27609 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][12] yv[13][20] $abc$30358$new_n4999 $abc$30358$new_n4988 $abc$30358$new_n5021 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][11] $abc$30358$new_n5023 yv[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27611 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][10] xv[13][20] $abc$30358$new_n5000 $abc$30358$new_n5024 $abc$30358$new_n5023 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n4989 $abc$30358$new_n4994 xv[13][20] $abc$30358$new_n5024 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5026 yv[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27613 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][10] yv[13][20] $abc$30358$new_n5000 $abc$30358$new_n5024 $abc$30358$new_n5026 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][9] $abc$30358$new_n5028 yv[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27615 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][8] xv[13][20] $abc$30358$new_n5001 $abc$30358$new_n4990 $abc$30358$new_n5028 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5030 yv[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27617 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][8] yv[13][20] $abc$30358$new_n5001 $abc$30358$new_n4990 $abc$30358$new_n5030 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][20] yv[13][7] $abc$30358$new_n5032 yv[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27619 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][6] xv[13][20] $abc$30358$new_n5002 $abc$30358$new_n4991 $abc$30358$new_n5032 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5034 yv[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27621 +001 1 +011 1 +100 1 +101 1 +.names xv[13][20] yv[13][6] yv[13][20] $abc$30358$new_n5002 $abc$30358$new_n4991 $abc$30358$new_n5034 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[13][19] yv[13][5] $abc$30358$new_n5036 yv[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27623 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][4] xv[13][18] $abc$30358$new_n5003 $abc$30358$new_n4992 $abc$30358$new_n5036 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5038 yv[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27625 +001 1 +011 1 +110 1 +111 1 +.names xv[13][18] yv[13][4] yv[13][20] $abc$30358$new_n5003 $abc$30358$new_n4992 $abc$30358$new_n5038 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01101 1 +01111 1 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[13][17] yv[13][3] $abc$30358$new_n5040 yv[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27627 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] yv[13][2] xv[13][16] $abc$30358$new_n5004 $abc$30358$new_n4993 $abc$30358$new_n5040 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[13][16] yv[13][2] $abc$30358$new_n5042 yv[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27629 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] $abc$30358$new_n4993 $abc$30358$new_n5004 $abc$30358$new_n5042 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5044 yv[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27631 +001 1 +011 1 +110 1 +111 1 +.names xv[13][15] yv[13][1] yv[13][20] yv[13][0] xv[13][14] $abc$30358$new_n5044 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[13][14] yv[13][0] yv[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27633 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[13][19] $abc$30358$new_n5060 $abc$30358$new_n5047 xv[14][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27635 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n5048 $abc$30358$new_n5047 +10 1 +.names xv[13][18] $abc$30358$new_n5049 $abc$30358$new_n5048 +10 1 +.names xv[13][16] xv[13][17] $abc$30358$new_n5050 $abc$30358$new_n5049 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n5058 $abc$30358$new_n6065 $abc$30358$new_n5050 +10 1 +.names yv[13][20] xv[13][8] xv[13][6] xv[13][7] $abc$30358$new_n5054 $abc$30358$new_n5053 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +11110 1 +.names yv[13][18] xv[13][4] xv[13][5] yv[13][19] $abc$30358$new_n5055 $abc$30358$new_n5054 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[13][16] xv[13][2] xv[13][3] yv[13][17] $abc$30358$new_n5056 $abc$30358$new_n5055 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[13][14] xv[13][0] xv[13][1] yv[13][15] $abc$30358$new_n5056 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[13][20] xv[13][12] xv[13][13] xv[13][14] xv[13][15] $abc$30358$new_n5058 +00000 1 +11111 1 +.names yv[13][20] xv[13][17] xv[13][18] $abc$30358$new_n6067 $abc$30358$new_n5060 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$30358$new_n5064 yv[13][20] xv[13][9] xv[13][10] xv[13][11] $abc$30358$new_n5063 +10111 1 +11000 1 +.names xv[13][8] yv[13][20] xv[13][6] xv[13][7] $abc$30358$new_n5065 $abc$30358$new_n5064 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[13][5] yv[13][19] $abc$30358$new_n5066 $abc$30358$new_n5065 +000 1 +001 1 +011 1 +101 1 +.names xv[13][3] yv[13][17] xv[13][4] yv[13][18] $abc$30358$new_n5067 $abc$30358$new_n5066 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[13][2] yv[13][16] $abc$30358$new_n5068 $abc$30358$new_n5067 +000 1 +001 1 +011 1 +101 1 +.names xv[13][0] yv[13][14] xv[13][1] yv[13][15] $abc$30358$new_n5068 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[13][20] xv[13][12] xv[13][13] $abc$30358$new_n5070 +011 1 +100 1 +.names i_ce xv[13][17] xv[13][16] $abc$30358$new_n5075 xv[14][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27639 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[13][15] $abc$30358$new_n5076 $abc$30358$new_n5075 +00 1 +01 1 +10 1 +.names $abc$30358$new_n5077 yv[13][20] $abc$30358$new_n5063 $abc$30358$new_n5076 +001 1 +010 1 +011 1 +.names xv[13][14] xv[13][12] xv[13][13] $abc$30358$new_n6065 $abc$30358$new_n5077 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n5075 xv[13][16] xv[14][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27641 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[13][15] $abc$30358$new_n5076 xv[14][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27643 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5084 xv[14][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27647 +001 1 +011 1 +110 1 +111 1 +.names xv[13][13] yv[13][20] xv[13][12] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n5084 +00101 1 +00111 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n5086 i_ce xv[14][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27649 +001 1 +010 1 +011 1 +.names i_ce yv[13][20] xv[13][12] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n5086 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][11] xv[13][10] $abc$30358$new_n5088 xv[14][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27651 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[13][9] yv[13][20] $abc$30358$new_n5064 $abc$30358$new_n5053 $abc$30358$new_n5088 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[13][10] $abc$30358$new_n5088 xv[14][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27653 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5091 xv[14][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27655 +001 1 +011 1 +110 1 +111 1 +.names yv[13][20] xv[13][9] $abc$30358$new_n5053 $abc$30358$new_n5064 $abc$30358$new_n5091 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5096 xv[14][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27659 +001 1 +011 1 +110 1 +111 1 +.names xv[13][7] yv[13][20] xv[13][6] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n5096 +00100 1 +00110 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$30358$new_n5098 i_ce xv[14][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27661 +001 1 +010 1 +011 1 +.names i_ce yv[13][20] xv[13][6] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n5098 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[13][5] yv[13][19] $abc$30358$new_n5100 xv[14][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27663 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] yv[13][18] xv[13][4] $abc$30358$new_n5055 $abc$30358$new_n5066 $abc$30358$new_n5100 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[13][4] yv[13][18] $abc$30358$new_n5102 xv[14][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27665 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] xv[13][3] yv[13][17] $abc$30358$new_n5067 $abc$30358$new_n5055 $abc$30358$new_n5102 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[13][3] yv[13][17] $abc$30358$new_n5104 xv[14][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27667 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[13][20] xv[13][2] yv[13][16] $abc$30358$new_n5056 $abc$30358$new_n5068 $abc$30358$new_n5104 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[13][2] yv[13][16] $abc$30358$new_n5106 xv[14][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27669 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[13][20] $abc$30358$new_n5068 $abc$30358$new_n5056 $abc$30358$new_n5106 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n5108 xv[14][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27671 +001 1 +011 1 +110 1 +111 1 +.names xv[13][1] yv[13][15] yv[13][20] xv[13][0] yv[13][14] $abc$30358$new_n5108 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[13][0] yv[13][14] xv[14][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27673 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[14][19] $abc$30358$new_n5111 ph[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27675 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[14][17] ph[14][18] yv[14][20] $abc$30358$new_n5112 $abc$30358$new_n5117 $abc$30358$new_n5111 +00110 1 +00111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5113 ph[14][16] $abc$30358$new_n5112 +10 1 +.names $abc$30358$new_n5114 ph[14][13] ph[14][14] ph[14][15] $abc$30358$new_n5113 +1000 1 +.names $abc$30358$new_n5115 ph[14][9] ph[14][10] ph[14][11] ph[14][12] $abc$30358$new_n5114 +10000 1 +.names $abc$30358$new_n5116 ph[14][5] ph[14][6] ph[14][7] ph[14][8] $abc$30358$new_n5115 +10000 1 +.names ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5116 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names ph[14][16] $abc$30358$new_n5118 $abc$30358$new_n5117 +11 1 +.names ph[14][13] ph[14][14] ph[14][15] $abc$30358$new_n5119 $abc$30358$new_n5118 +1111 1 +.names ph[14][9] ph[14][10] ph[14][11] ph[14][12] $abc$30358$new_n5120 $abc$30358$new_n5119 +11111 1 +.names ph[14][5] ph[14][6] ph[14][7] ph[14][8] $abc$30358$new_n5121 $abc$30358$new_n5120 +11111 1 +.names ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5121 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n5123 ph[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27677 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] ph[14][18] ph[14][17] $abc$30358$new_n5117 $abc$30358$new_n5112 $abc$30358$new_n5123 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5125 ph[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27679 +001 1 +011 1 +110 1 +111 1 +.names ph[14][17] yv[14][20] $abc$30358$new_n5117 $abc$30358$new_n5112 $abc$30358$new_n5125 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5127 ph[15][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27681 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[14][16] yv[14][20] $abc$30358$new_n5118 $abc$30358$new_n5113 $abc$30358$new_n5127 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5129 ph[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27683 +001 1 +011 1 +110 1 +111 1 +.names ph[14][13] ph[14][15] ph[14][14] $abc$30358$new_n5136 $abc$30358$new_n5130 $abc$30358$new_n5129 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[14][11] ph[14][12] $abc$30358$new_n5131 $abc$30358$new_n5130 +111 1 +.names ph[14][9] ph[14][10] $abc$30358$new_n5132 $abc$30358$new_n5131 +111 1 +.names ph[14][8] $abc$30358$new_n5133 $abc$30358$new_n5132 +11 1 +.names ph[14][7] $abc$30358$new_n5134 $abc$30358$new_n5133 +11 1 +.names ph[14][5] ph[14][6] $abc$30358$new_n5135 $abc$30358$new_n5134 +111 1 +.names $abc$30358$new_n5121 yv[14][20] $abc$30358$new_n5135 +10 1 +.names $abc$30358$new_n5137 ph[14][11] ph[14][12] $abc$30358$new_n5136 +100 1 +.names $abc$30358$new_n5138 ph[14][9] ph[14][10] $abc$30358$new_n5137 +100 1 +.names $abc$30358$new_n5139 ph[14][8] $abc$30358$new_n5138 +10 1 +.names $abc$30358$new_n5140 ph[14][7] $abc$30358$new_n5139 +10 1 +.names $abc$30358$new_n5141 ph[14][5] ph[14][6] $abc$30358$new_n5140 +100 1 +.names yv[14][20] $abc$30358$new_n5116 $abc$30358$new_n5141 +11 1 +.names i_ce $abc$30358$new_n5143 ph[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27685 +001 1 +011 1 +110 1 +111 1 +.names ph[14][14] ph[14][13] $abc$30358$new_n5136 $abc$30358$new_n5130 $abc$30358$new_n5143 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce ph[14][13] $abc$30358$new_n5136 $abc$30358$new_n5130 ph[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27687 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5146 ph[14][12] ph[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27689 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[14][11] $abc$30358$new_n5131 $abc$30358$new_n5137 $abc$30358$new_n5146 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[14][11] $abc$30358$new_n5137 $abc$30358$new_n5131 ph[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27691 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5149 i_ce ph[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27693 +001 1 +010 1 +011 1 +.names i_ce ph[14][10] ph[14][9] $abc$30358$new_n5138 $abc$30358$new_n5132 $abc$30358$new_n5149 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[14][9] $abc$30358$new_n5138 $abc$30358$new_n5132 ph[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27695 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[14][8] $abc$30358$new_n5139 $abc$30358$new_n5133 ph[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27697 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[14][7] $abc$30358$new_n5140 $abc$30358$new_n5134 ph[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27699 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5154 ph[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27701 +001 1 +011 1 +100 1 +101 1 +.names ph[14][6] ph[14][5] $abc$30358$new_n5141 $abc$30358$new_n5135 $abc$30358$new_n5154 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[14][5] $abc$30358$new_n5141 $abc$30358$new_n5135 ph[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27703 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5157 ph[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27705 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] ph[14][4] ph[14][3] ph[14][1] ph[14][2] $abc$30358$new_n5157 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n5159 ph[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27707 +001 1 +011 1 +110 1 +111 1 +.names ph[14][3] yv[14][20] ph[14][1] ph[14][2] $abc$30358$new_n5159 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[14][20] ph[14][1] ph[14][2] ph[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27709 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[14][1] ph[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27711 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[14][0] ph[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27713 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[14][20] yv[14][19] $abc$30358$new_n5164 yv[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27715 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][18] xv[14][20] $abc$30358$new_n5177 $abc$30358$new_n5165 $abc$30358$new_n5164 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names xv[14][20] $abc$30358$new_n5166 yv[14][16] yv[14][17] $abc$30358$new_n5165 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5176 $abc$30358$new_n5167 xv[14][20] $abc$30358$new_n5166 +001 1 +011 1 +110 1 +111 1 +.names xv[14][20] yv[14][10] yv[14][11] $abc$30358$new_n5168 $abc$30358$new_n5174 $abc$30358$new_n5167 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[14][20] yv[14][8] yv[14][9] $abc$30358$new_n5169 $abc$30358$new_n5168 +0000 1 +1110 1 +.names xv[14][20] $abc$30358$new_n5170 yv[14][6] yv[14][7] $abc$30358$new_n5169 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[14][20] yv[14][5] $abc$30358$new_n5171 $abc$30358$new_n5170 +001 1 +100 1 +101 1 +111 1 +.names xv[14][19] yv[14][4] $abc$30358$new_n5172 $abc$30358$new_n5171 +001 1 +100 1 +101 1 +111 1 +.names xv[14][17] xv[14][18] yv[14][2] yv[14][3] $abc$30358$new_n5173 $abc$30358$new_n5172 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[14][15] xv[14][16] yv[14][0] yv[14][1] $abc$30358$new_n5173 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names yv[14][8] yv[14][9] $abc$30358$new_n5174 +00 1 +.names xv[14][20] yv[14][12] yv[14][13] yv[14][14] yv[14][15] $abc$30358$new_n5176 +00000 1 +11111 1 +.names xv[14][20] $abc$30358$new_n5178 yv[14][16] yv[14][17] $abc$30358$new_n5177 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$30358$new_n5185 $abc$30358$new_n5179 xv[14][20] $abc$30358$new_n5178 +000 1 +010 1 +110 1 +111 1 +.names xv[14][20] yv[14][10] yv[14][11] $abc$30358$new_n5180 $abc$30358$new_n5174 $abc$30358$new_n5179 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names xv[14][20] yv[14][8] yv[14][9] $abc$30358$new_n5181 $abc$30358$new_n5180 +0110 1 +1000 1 +.names xv[14][20] $abc$30358$new_n5182 yv[14][5] yv[14][6] yv[14][7] $abc$30358$new_n5181 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names xv[14][19] yv[14][4] $abc$30358$new_n5183 $abc$30358$new_n5182 +000 1 +001 1 +011 1 +101 1 +.names xv[14][17] yv[14][2] xv[14][18] yv[14][3] $abc$30358$new_n5184 $abc$30358$new_n5183 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[14][15] yv[14][0] xv[14][16] yv[14][1] $abc$30358$new_n5184 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[14][20] yv[14][12] yv[14][13] yv[14][14] yv[14][15] $abc$30358$new_n5185 +01111 1 +10000 1 +.names i_ce xv[14][20] yv[14][18] $abc$30358$new_n5187 yv[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27717 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] $abc$30358$new_n5165 $abc$30358$new_n5177 $abc$30358$new_n5187 +010 1 +011 1 +100 1 +110 1 +.names i_ce xv[14][20] yv[14][17] $abc$30358$new_n5189 yv[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27719 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][20] yv[14][16] $abc$30358$new_n5178 $abc$30358$new_n5166 $abc$30358$new_n5189 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5191 yv[15][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27721 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] xv[14][20] yv[14][16] $abc$30358$new_n5178 $abc$30358$new_n5166 $abc$30358$new_n5191 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][20] yv[14][15] $abc$30358$new_n5193 yv[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27723 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][14] xv[14][20] $abc$30358$new_n5195 $abc$30358$new_n5194 $abc$30358$new_n5193 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +.names xv[14][20] $abc$30358$new_n5167 yv[14][12] yv[14][13] $abc$30358$new_n5194 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[14][20] yv[14][12] yv[14][13] $abc$30358$new_n5179 $abc$30358$new_n5195 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[14][20] yv[14][14] $abc$30358$new_n5197 yv[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27725 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5194 $abc$30358$new_n5195 $abc$30358$new_n5197 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[14][20] yv[14][13] $abc$30358$new_n5199 yv[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27727 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][20] yv[14][12] $abc$30358$new_n5179 $abc$30358$new_n5167 $abc$30358$new_n5199 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5201 yv[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27729 +001 1 +011 1 +100 1 +101 1 +.names yv[14][20] xv[14][20] yv[14][12] $abc$30358$new_n5179 $abc$30358$new_n5167 $abc$30358$new_n5201 +00000 1 +00010 1 +00101 1 +00111 1 +01001 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][20] yv[14][11] $abc$30358$new_n5203 yv[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27731 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][10] xv[14][20] $abc$30358$new_n5205 $abc$30358$new_n5204 $abc$30358$new_n5203 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$30358$new_n5168 $abc$30358$new_n5174 xv[14][20] $abc$30358$new_n5204 +001 1 +010 1 +011 1 +.names $abc$30358$new_n5180 $abc$30358$new_n5174 xv[14][20] $abc$30358$new_n5205 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5207 yv[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27733 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] xv[14][20] yv[14][10] $abc$30358$new_n5205 $abc$30358$new_n5204 $abc$30358$new_n5207 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][20] yv[14][9] $abc$30358$new_n5209 yv[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27735 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][8] xv[14][20] $abc$30358$new_n5181 $abc$30358$new_n5169 $abc$30358$new_n5209 +00000 1 +00010 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n5211 yv[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27737 +001 1 +011 1 +110 1 +111 1 +.names yv[14][20] xv[14][20] yv[14][8] $abc$30358$new_n5181 $abc$30358$new_n5169 $abc$30358$new_n5211 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[14][20] yv[14][7] $abc$30358$new_n5213 yv[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27739 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][6] xv[14][20] $abc$30358$new_n5170 $abc$30358$new_n5214 $abc$30358$new_n5213 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[14][20] yv[14][5] $abc$30358$new_n5182 $abc$30358$new_n5214 +000 1 +001 1 +011 1 +101 1 +.names i_ce xv[14][20] yv[14][6] $abc$30358$new_n5216 yv[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27741 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] $abc$30358$new_n5214 $abc$30358$new_n5170 $abc$30358$new_n5216 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[14][20] yv[14][5] $abc$30358$new_n5218 yv[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27743 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5182 $abc$30358$new_n5171 $abc$30358$new_n5218 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5220 yv[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27745 +001 1 +011 1 +100 1 +101 1 +.names xv[14][19] yv[14][4] yv[14][20] $abc$30358$new_n5172 $abc$30358$new_n5183 $abc$30358$new_n5220 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[14][18] yv[14][3] $abc$30358$new_n5222 yv[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27747 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] yv[14][2] xv[14][17] $abc$30358$new_n5173 $abc$30358$new_n5184 $abc$30358$new_n5222 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[14][17] yv[14][2] $abc$30358$new_n5224 yv[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27749 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5184 $abc$30358$new_n5173 $abc$30358$new_n5224 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5226 yv[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27751 +001 1 +011 1 +110 1 +111 1 +.names xv[14][16] yv[14][1] yv[14][20] yv[14][0] xv[14][15] $abc$30358$new_n5226 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[14][15] yv[14][0] yv[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27753 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][19] $abc$30358$new_n5229 xv[15][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27755 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5243 yv[14][20] $abc$30358$new_n5230 $abc$30358$new_n5229 +100 1 +110 1 +111 1 +.names xv[14][17] $abc$30358$new_n5231 $abc$30358$new_n5230 +00 1 +01 1 +10 1 +.names xv[14][16] $abc$30358$new_n5232 $abc$30358$new_n5231 +11 1 +.names $abc$30358$new_n5241 $abc$30358$new_n5233 $abc$30358$new_n5232 +10 1 +.names $abc$30358$new_n5240 $abc$30358$new_n5234 yv[14][20] $abc$30358$new_n5239 $abc$30358$new_n5233 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$30358$new_n5235 yv[14][20] xv[14][8] $abc$30358$new_n5234 +101 1 +110 1 +.names yv[14][20] xv[14][5] xv[14][6] xv[14][7] $abc$30358$new_n5236 $abc$30358$new_n5235 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[14][3] yv[14][18] xv[14][4] yv[14][19] $abc$30358$new_n5237 $abc$30358$new_n5236 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names xv[14][2] yv[14][17] $abc$30358$new_n5238 $abc$30358$new_n5237 +000 1 +001 1 +011 1 +101 1 +.names xv[14][0] yv[14][15] xv[14][1] yv[14][16] $abc$30358$new_n5238 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[14][8] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5239 +0000 1 +.names yv[14][20] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5240 +0111 1 +1000 1 +.names yv[14][20] xv[14][12] xv[14][13] xv[14][14] xv[14][15] $abc$30358$new_n5241 +01111 1 +10000 1 +.names xv[14][18] $abc$30358$new_n5244 $abc$30358$new_n5243 +10 1 +.names xv[14][17] xv[14][16] $abc$30358$new_n5245 $abc$30358$new_n5244 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5252 $abc$30358$new_n5246 yv[14][20] $abc$30358$new_n5239 $abc$30358$new_n5245 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +.names $abc$30358$new_n5247 yv[14][20] xv[14][9] xv[14][10] xv[14][11] $abc$30358$new_n5246 +10000 1 +11111 1 +.names $abc$30358$new_n5248 yv[14][20] xv[14][8] $abc$30358$new_n5247 +100 1 +111 1 +.names yv[14][20] xv[14][6] xv[14][7] $abc$30358$new_n5249 xv[14][5] $abc$30358$new_n5248 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +11111 1 +.names yv[14][19] xv[14][4] $abc$30358$new_n5250 yv[14][20] xv[14][5] $abc$30358$new_n5249 +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names yv[14][17] xv[14][2] xv[14][3] yv[14][18] $abc$30358$new_n5251 $abc$30358$new_n5250 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names yv[14][15] xv[14][0] xv[14][1] yv[14][16] $abc$30358$new_n5251 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[14][20] xv[14][12] xv[14][13] xv[14][14] xv[14][15] $abc$30358$new_n5252 +00000 1 +11111 1 +.names i_ce xv[14][17] xv[14][16] $abc$30358$new_n5257 xv[15][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27759 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[14][15] $abc$30358$new_n5258 $abc$30358$new_n5257 +00 1 +01 1 +10 1 +.names xv[14][14] yv[14][20] $abc$30358$new_n5259 $abc$30358$new_n5260 $abc$30358$new_n5258 +1000 1 +1010 1 +1110 1 +1111 1 +.names xv[14][12] xv[14][13] $abc$30358$new_n5246 $abc$30358$new_n5259 +111 1 +.names xv[14][13] xv[14][12] $abc$30358$new_n5233 $abc$30358$new_n5260 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5257 xv[14][16] xv[15][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27761 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_ce xv[14][15] $abc$30358$new_n5258 xv[15][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27763 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5264 i_ce xv[15][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27765 +001 1 +010 1 +011 1 +.names i_ce xv[14][14] yv[14][20] $abc$30358$new_n5260 $abc$30358$new_n5259 $abc$30358$new_n5264 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5266 xv[15][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27767 +001 1 +011 1 +110 1 +111 1 +.names xv[14][13] yv[14][20] xv[14][12] $abc$30358$new_n5246 $abc$30358$new_n5233 $abc$30358$new_n5266 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5268 i_ce xv[15][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27769 +001 1 +010 1 +011 1 +.names i_ce yv[14][20] xv[14][12] $abc$30358$new_n5246 $abc$30358$new_n5233 $abc$30358$new_n5268 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[14][11] xv[14][10] $abc$30358$new_n5270 xv[15][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27771 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[14][9] $abc$30358$new_n5271 $abc$30358$new_n5270 +11 1 +.names yv[14][20] $abc$30358$new_n5234 $abc$30358$new_n5247 $abc$30358$new_n5271 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[14][10] $abc$30358$new_n5270 xv[15][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27773 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][9] $abc$30358$new_n5271 xv[15][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27775 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[14][7] $abc$30358$new_n5277 xv[15][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27779 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[14][6] yv[14][20] $abc$30358$new_n5278 $abc$30358$new_n5249 $abc$30358$new_n5277 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[14][5] $abc$30358$new_n5236 $abc$30358$new_n5278 +10 1 +.names $abc$30358$new_n5280 i_ce xv[15][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27781 +001 1 +010 1 +011 1 +.names i_ce yv[14][20] xv[14][6] $abc$30358$new_n5249 $abc$30358$new_n5278 $abc$30358$new_n5280 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5282 xv[14][5] xv[15][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27783 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[14][20] yv[14][19] xv[14][4] $abc$30358$new_n5250 $abc$30358$new_n5236 $abc$30358$new_n5282 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[14][4] yv[14][19] $abc$30358$new_n5284 xv[15][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27785 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[14][20] xv[14][3] yv[14][18] $abc$30358$new_n5237 $abc$30358$new_n5250 $abc$30358$new_n5284 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce xv[14][3] yv[14][18] $abc$30358$new_n5286 xv[15][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27787 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] xv[14][2] yv[14][17] $abc$30358$new_n5251 $abc$30358$new_n5238 $abc$30358$new_n5286 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[14][2] yv[14][17] $abc$30358$new_n5288 xv[15][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27789 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[14][20] $abc$30358$new_n5238 $abc$30358$new_n5251 $abc$30358$new_n5288 +010 1 +011 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5290 xv[15][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27791 +001 1 +011 1 +110 1 +111 1 +.names xv[14][1] yv[14][16] yv[14][20] xv[14][0] yv[14][15] $abc$30358$new_n5290 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[14][0] yv[14][15] xv[15][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27793 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5293 ph[15][19] ph[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27795 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][17] ph[15][18] $abc$30358$new_n5294 $abc$30358$new_n5302 $abc$30358$new_n5293 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[15][16] $abc$30358$new_n5295 $abc$30358$new_n5294 +11 1 +.names $abc$30358$new_n5296 ph[15][15] yv[15][20] $abc$30358$new_n5295 +110 1 +.names ph[15][14] $abc$30358$new_n5297 $abc$30358$new_n5296 +11 1 +.names ph[15][13] $abc$30358$new_n5298 $abc$30358$new_n5297 +11 1 +.names ph[15][12] $abc$30358$new_n5299 $abc$30358$new_n5298 +11 1 +.names ph[15][8] ph[15][9] ph[15][10] ph[15][11] $abc$30358$new_n5300 $abc$30358$new_n5299 +11111 1 +.names ph[15][4] ph[15][5] ph[15][6] ph[15][7] $abc$30358$new_n5301 $abc$30358$new_n5300 +11111 1 +.names ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5301 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5303 ph[15][16] $abc$30358$new_n5302 +10 1 +.names yv[15][20] $abc$30358$new_n5304 ph[15][15] $abc$30358$new_n5303 +110 1 +.names $abc$30358$new_n5305 ph[15][14] $abc$30358$new_n5304 +10 1 +.names $abc$30358$new_n5306 ph[15][13] $abc$30358$new_n5305 +10 1 +.names $abc$30358$new_n5307 ph[15][9] ph[15][10] ph[15][11] ph[15][12] $abc$30358$new_n5306 +10000 1 +.names $abc$30358$new_n5308 ph[15][5] ph[15][6] ph[15][7] ph[15][8] $abc$30358$new_n5307 +10000 1 +.names ph[15][4] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5308 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names i_ce $abc$30358$new_n5310 ph[15][18] ph[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27797 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][17] $abc$30358$new_n5294 $abc$30358$new_n5302 $abc$30358$new_n5310 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[15][17] $abc$30358$new_n5302 $abc$30358$new_n5294 ph[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27799 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[15][16] $abc$30358$new_n5303 $abc$30358$new_n5295 ph[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27801 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5314 ph[16][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27803 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce yv[15][20] ph[15][15] $abc$30358$new_n5304 $abc$30358$new_n5296 $abc$30358$new_n5314 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5316 ph[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27805 +001 1 +011 1 +110 1 +111 1 +.names yv[15][20] ph[15][14] $abc$30358$new_n5305 $abc$30358$new_n5297 $abc$30358$new_n5316 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5318 ph[16][13] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27807 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce yv[15][20] ph[15][13] $abc$30358$new_n5306 $abc$30358$new_n5298 $abc$30358$new_n5318 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce ph[15][12] $abc$30358$new_n5320 ph[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27809 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[15][9] ph[15][10] ph[15][11] $abc$30358$new_n5321 $abc$30358$new_n5325 $abc$30358$new_n5320 +00001 1 +00011 1 +11110 1 +11111 1 +.names ph[15][8] $abc$30358$new_n5322 $abc$30358$new_n5321 +11 1 +.names ph[15][6] ph[15][7] $abc$30358$new_n5323 $abc$30358$new_n5322 +111 1 +.names ph[15][4] ph[15][5] $abc$30358$new_n5324 $abc$30358$new_n5323 +111 1 +.names $abc$30358$new_n5301 yv[15][20] $abc$30358$new_n5324 +10 1 +.names $abc$30358$new_n5326 ph[15][8] $abc$30358$new_n5325 +10 1 +.names $abc$30358$new_n5327 ph[15][6] ph[15][7] $abc$30358$new_n5326 +100 1 +.names $abc$30358$new_n5328 ph[15][4] ph[15][5] $abc$30358$new_n5327 +100 1 +.names yv[15][20] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5328 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names i_ce $abc$30358$new_n5330 ph[15][11] ph[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27811 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[15][9] ph[15][10] $abc$30358$new_n5321 $abc$30358$new_n5325 $abc$30358$new_n5330 +0000 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5332 ph[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27813 +001 1 +011 1 +100 1 +101 1 +.names ph[15][10] ph[15][9] $abc$30358$new_n5325 $abc$30358$new_n5321 $abc$30358$new_n5332 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[15][9] $abc$30358$new_n5325 $abc$30358$new_n5321 ph[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27815 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[15][8] $abc$30358$new_n5326 $abc$30358$new_n5322 ph[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27817 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5336 i_ce ph[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27819 +001 1 +010 1 +011 1 +.names i_ce ph[15][7] ph[15][6] $abc$30358$new_n5327 $abc$30358$new_n5323 $abc$30358$new_n5336 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[15][6] $abc$30358$new_n5327 $abc$30358$new_n5323 ph[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27821 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5339 ph[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27823 +001 1 +011 1 +100 1 +101 1 +.names ph[15][5] ph[15][4] $abc$30358$new_n5328 $abc$30358$new_n5324 $abc$30358$new_n5339 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[15][4] $abc$30358$new_n5328 $abc$30358$new_n5324 ph[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27825 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5342 ph[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27827 +001 1 +011 1 +100 1 +101 1 +.names yv[15][20] ph[15][3] ph[15][2] ph[15][0] ph[15][1] $abc$30358$new_n5342 +00000 1 +00001 1 +00010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names i_ce $abc$30358$new_n5344 ph[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27829 +001 1 +011 1 +110 1 +111 1 +.names ph[15][2] yv[15][20] ph[15][0] ph[15][1] $abc$30358$new_n5344 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[15][20] ph[15][0] ph[15][1] ph[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27831 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[15][0] ph[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27833 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[15][20] yv[15][19] $abc$30358$new_n5348 yv[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27835 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][18] xv[15][20] $abc$30358$new_n5365 $abc$30358$new_n5349 $abc$30358$new_n5348 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5350 xv[15][20] yv[15][16] yv[15][17] $abc$30358$new_n5349 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$30358$new_n5364 $abc$30358$new_n5362 $abc$30358$new_n5360 $abc$30358$new_n5363 $abc$30358$new_n5351 $abc$30358$new_n5350 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][20] $abc$30358$new_n5393 yv[15][10] yv[15][11] $abc$30358$new_n5351 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names xv[15][20] yv[15][6] yv[15][7] $abc$30358$new_n5354 $abc$30358$new_n5358 $abc$30358$new_n5353 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +.names $abc$30358$new_n5355 xv[15][20] yv[15][5] $abc$30358$new_n5354 +101 1 +110 1 +.names xv[15][19] yv[15][3] xv[15][20] yv[15][4] $abc$30358$new_n5356 $abc$30358$new_n5355 +01010 1 +01100 1 +10010 1 +10100 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][18] yv[15][2] $abc$30358$new_n5357 $abc$30358$new_n5356 +000 1 +001 1 +011 1 +101 1 +.names xv[15][16] yv[15][0] xv[15][17] yv[15][1] $abc$30358$new_n5357 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names yv[15][4] yv[15][5] $abc$30358$new_n5358 +00 1 +.names xv[15][20] $abc$30358$new_n5361 yv[15][14] yv[15][15] $abc$30358$new_n5360 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[15][12] yv[15][13] $abc$30358$new_n5361 +00 1 +.names xv[15][20] yv[15][16] $abc$30358$new_n5362 +01 1 +10 1 +.names xv[15][20] yv[15][12] yv[15][13] yv[15][14] yv[15][15] $abc$30358$new_n5363 +01111 1 +10000 1 +.names xv[15][20] yv[15][17] $abc$30358$new_n5364 +01 1 +10 1 +.names xv[15][20] $abc$30358$new_n5366 yv[15][16] yv[15][17] $abc$30358$new_n5365 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] yv[15][14] yv[15][15] $abc$30358$new_n5367 $abc$30358$new_n5361 $abc$30358$new_n5366 +00001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][20] yv[15][12] yv[15][13] $abc$30358$new_n5368 $abc$30358$new_n5367 +0000 1 +1110 1 +.names xv[15][20] $abc$30358$new_n5369 yv[15][10] yv[15][11] $abc$30358$new_n5368 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5370 yv[15][8] yv[15][9] $abc$30358$new_n5369 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5371 yv[15][6] yv[15][7] $abc$30358$new_n5370 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][20] $abc$30358$new_n5372 yv[15][4] yv[15][5] $abc$30358$new_n5371 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[15][18] xv[15][19] yv[15][2] yv[15][3] $abc$30358$new_n5373 $abc$30358$new_n5372 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names xv[15][16] xv[15][17] yv[15][0] yv[15][1] $abc$30358$new_n5373 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names i_ce xv[15][20] yv[15][18] $abc$30358$new_n5375 yv[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27837 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][20] $abc$30358$new_n5349 $abc$30358$new_n5365 $abc$30358$new_n5375 +001 1 +011 1 +100 1 +101 1 +.names i_ce $abc$30358$new_n5377 $abc$30358$new_n5364 yv[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27839 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[15][20] yv[15][16] xv[15][20] $abc$30358$new_n5366 $abc$30358$new_n5378 $abc$30358$new_n5377 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5360 $abc$30358$new_n5351 $abc$30358$new_n5363 $abc$30358$new_n5378 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5380 $abc$30358$new_n5362 yv[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27841 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[15][20] $abc$30358$new_n5378 $abc$30358$new_n5366 $abc$30358$new_n5380 +000 1 +010 1 +110 1 +111 1 +.names i_ce xv[15][20] yv[15][15] $abc$30358$new_n5382 yv[16][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27843 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][14] xv[15][20] $abc$30358$new_n5384 $abc$30358$new_n5383 $abc$30358$new_n5382 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names xv[15][20] yv[15][12] yv[15][13] $abc$30358$new_n5351 $abc$30358$new_n5383 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5367 $abc$30358$new_n5361 xv[15][20] $abc$30358$new_n5384 +001 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5386 yv[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27845 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][14] yv[15][20] $abc$30358$new_n5384 $abc$30358$new_n5383 $abc$30358$new_n5386 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[15][20] yv[15][13] $abc$30358$new_n5388 yv[16][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27847 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][12] xv[15][20] $abc$30358$new_n5368 $abc$30358$new_n5351 $abc$30358$new_n5388 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5390 yv[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27849 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][12] yv[15][20] $abc$30358$new_n5368 $abc$30358$new_n5351 $abc$30358$new_n5390 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][11] $abc$30358$new_n5392 yv[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27851 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][10] xv[15][20] $abc$30358$new_n5369 $abc$30358$new_n5393 $abc$30358$new_n5392 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names xv[15][20] $abc$30358$new_n5353 yv[15][8] yv[15][9] $abc$30358$new_n5393 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_ce $abc$30358$new_n5395 yv[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27853 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][10] yv[15][20] $abc$30358$new_n5369 $abc$30358$new_n5393 $abc$30358$new_n5395 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][9] $abc$30358$new_n5397 yv[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27855 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][8] xv[15][20] $abc$30358$new_n5370 $abc$30358$new_n5353 $abc$30358$new_n5397 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n5399 yv[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27857 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][8] yv[15][20] $abc$30358$new_n5370 $abc$30358$new_n5353 $abc$30358$new_n5399 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][7] $abc$30358$new_n5401 yv[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27859 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][6] xv[15][20] $abc$30358$new_n5371 $abc$30358$new_n5402 $abc$30358$new_n5401 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n5354 $abc$30358$new_n5358 xv[15][20] $abc$30358$new_n5402 +000 1 +010 1 +011 1 +.names i_ce $abc$30358$new_n5404 yv[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27861 +001 1 +011 1 +100 1 +101 1 +.names xv[15][20] yv[15][6] yv[15][20] $abc$30358$new_n5371 $abc$30358$new_n5402 $abc$30358$new_n5404 +00000 1 +00001 1 +00101 1 +00111 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names i_ce xv[15][20] yv[15][5] $abc$30358$new_n5406 yv[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27863 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][4] xv[15][20] $abc$30358$new_n5372 $abc$30358$new_n5355 $abc$30358$new_n5406 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names i_ce xv[15][20] yv[15][4] $abc$30358$new_n5408 yv[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27865 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] xv[15][19] yv[15][3] $abc$30358$new_n5356 $abc$30358$new_n5372 $abc$30358$new_n5408 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_ce xv[15][19] yv[15][3] $abc$30358$new_n5410 yv[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27867 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] yv[15][2] xv[15][18] $abc$30358$new_n5373 $abc$30358$new_n5357 $abc$30358$new_n5410 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names i_ce xv[15][18] yv[15][2] $abc$30358$new_n5412 yv[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27869 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] $abc$30358$new_n5357 $abc$30358$new_n5373 $abc$30358$new_n5412 +000 1 +010 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5414 yv[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27871 +001 1 +011 1 +110 1 +111 1 +.names xv[15][17] yv[15][1] yv[15][20] yv[15][0] xv[15][16] $abc$30358$new_n5414 +00001 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11111 1 +.names i_ce xv[15][16] yv[15][0] yv[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27873 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][19] $abc$30358$new_n5417 xv[16][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27875 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[15][18] yv[15][20] $abc$30358$new_n5418 $abc$30358$new_n5429 $abc$30358$new_n5417 +1000 1 +1001 1 +1101 1 +1111 1 +.names xv[15][17] xv[15][16] $abc$30358$new_n5419 $abc$30358$new_n5418 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names xv[15][14] xv[15][15] $abc$30358$new_n5420 $abc$30358$new_n5419 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names yv[15][20] xv[15][12] xv[15][13] $abc$30358$new_n5421 $abc$30358$new_n5420 +0110 1 +1000 1 +.names yv[15][20] $abc$30358$new_n5427 $abc$30358$new_n5422 xv[15][10] xv[15][11] $abc$30358$new_n5421 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +.names yv[15][20] xv[15][7] xv[15][8] $abc$30358$new_n5423 xv[15][6] $abc$30358$new_n5422 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][6] yv[15][20] xv[15][4] xv[15][5] $abc$30358$new_n5424 $abc$30358$new_n5423 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +.names xv[15][3] yv[15][19] $abc$30358$new_n5425 $abc$30358$new_n5424 +010 1 +100 1 +110 1 +111 1 +.names xv[15][2] yv[15][18] $abc$30358$new_n5426 $abc$30358$new_n5425 +000 1 +001 1 +011 1 +101 1 +.names xv[15][0] yv[15][16] xv[15][1] yv[15][17] $abc$30358$new_n5426 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[15][9] yv[15][20] xv[15][7] xv[15][8] $abc$30358$new_n5423 $abc$30358$new_n5427 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[15][16] xv[15][17] $abc$30358$new_n5430 $abc$30358$new_n5429 +111 1 +.names $abc$30358$new_n5441 $abc$30358$new_n6078 $abc$30358$new_n5430 +10 1 +.names yv[15][20] xv[15][8] $abc$30358$new_n5434 $abc$30358$new_n5433 +000 1 +110 1 +.names yv[15][20] $abc$30358$new_n5439 $abc$30358$new_n5435 xv[15][4] $abc$30358$new_n5434 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[15][19] xv[15][3] $abc$30358$new_n5436 $abc$30358$new_n5435 +000 1 +100 1 +101 1 +110 1 +.names xv[15][2] yv[15][18] $abc$30358$new_n5437 $abc$30358$new_n5436 +001 1 +100 1 +101 1 +111 1 +.names yv[15][16] xv[15][0] xv[15][1] yv[15][17] $abc$30358$new_n5437 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[15][20] xv[15][5] xv[15][6] xv[15][7] $abc$30358$new_n5439 +0000 1 +1111 1 +.names yv[15][20] xv[15][12] xv[15][13] xv[15][14] xv[15][15] $abc$30358$new_n5441 +00000 1 +11111 1 +.names i_ce $abc$30358$new_n5447 xv[16][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27879 +001 1 +011 1 +110 1 +111 1 +.names xv[15][17] yv[15][20] xv[15][16] $abc$30358$new_n5430 $abc$30358$new_n5419 $abc$30358$new_n5447 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5449 i_ce xv[16][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27881 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][16] $abc$30358$new_n5430 $abc$30358$new_n5419 $abc$30358$new_n5449 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5451 xv[16][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27883 +001 1 +011 1 +110 1 +111 1 +.names xv[15][15] yv[15][20] xv[15][14] $abc$30358$new_n5420 $abc$30358$new_n5452 $abc$30358$new_n5451 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names xv[15][13] xv[15][12] $abc$30358$new_n6078 $abc$30358$new_n5452 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5454 i_ce xv[16][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27885 +001 1 +010 1 +011 1 +.names i_ce xv[15][14] yv[15][20] $abc$30358$new_n5420 $abc$30358$new_n5452 $abc$30358$new_n5454 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5456 xv[16][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27887 +001 1 +011 1 +110 1 +111 1 +.names xv[15][13] xv[15][12] $abc$30358$new_n5421 $abc$30358$new_n6078 $abc$30358$new_n5456 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[15][11] xv[15][10] $abc$30358$new_n5460 xv[16][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27891 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5427 $abc$30358$new_n5461 $abc$30358$new_n5460 +10 1 +.names yv[15][20] $abc$30358$new_n5433 $abc$30358$new_n5461 +10 1 +.names i_ce xv[15][10] $abc$30358$new_n5460 xv[16][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27893 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][9] $abc$30358$new_n5461 $abc$30358$new_n5464 xv[16][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27895 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[15][20] $abc$30358$new_n5465 xv[15][8] $abc$30358$new_n5464 +000 1 +010 1 +011 1 +.names xv[15][7] $abc$30358$new_n5423 $abc$30358$new_n5465 +00 1 +01 1 +10 1 +.names $abc$30358$new_n5467 i_ce xv[16][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27897 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][8] $abc$30358$new_n5434 $abc$30358$new_n5465 $abc$30358$new_n5467 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[15][7] xv[15][6] $abc$30358$new_n5469 xv[16][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27899 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[15][5] $abc$30358$new_n5471 $abc$30358$new_n5470 $abc$30358$new_n5469 +100 1 +.names yv[15][20] $abc$30358$new_n5424 xv[15][4] $abc$30358$new_n5470 +000 1 +001 1 +010 1 +.names yv[15][20] $abc$30358$new_n5435 xv[15][4] $abc$30358$new_n5471 +100 1 +110 1 +111 1 +.names i_ce xv[15][6] $abc$30358$new_n5469 xv[16][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27901 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[15][5] $abc$30358$new_n5471 $abc$30358$new_n5470 xv[16][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27903 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5475 i_ce xv[16][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27905 +001 1 +010 1 +011 1 +.names i_ce yv[15][20] xv[15][4] $abc$30358$new_n5435 $abc$30358$new_n5424 $abc$30358$new_n5475 +10000 1 +10010 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5477 xv[16][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27907 +001 1 +011 1 +100 1 +101 1 +.names yv[15][20] xv[15][3] yv[15][19] $abc$30358$new_n5436 $abc$30358$new_n5425 $abc$30358$new_n5477 +00001 1 +00011 1 +00100 1 +00110 1 +01000 1 +01010 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[15][2] yv[15][18] $abc$30358$new_n5479 xv[16][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27909 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[15][20] $abc$30358$new_n5426 $abc$30358$new_n5437 $abc$30358$new_n5479 +010 1 +011 1 +101 1 +111 1 +.names i_ce xv[15][1] yv[15][17] $abc$30358$new_n5481 xv[16][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27911 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[15][16] yv[15][20] xv[15][0] $abc$30358$new_n5481 +101 1 +110 1 +.names i_ce xv[15][0] yv[15][16] xv[16][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27913 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5484 ph[16][19] ph[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27915 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][18] $abc$30358$new_n5485 $abc$30358$new_n5491 $abc$30358$new_n5484 +000 1 +001 1 +100 1 +110 1 +.names yv[16][20] $abc$30358$new_n5486 ph[16][17] $abc$30358$new_n5485 +110 1 +.names $abc$30358$new_n5487 ph[16][16] $abc$30358$new_n5486 +10 1 +.names $abc$30358$new_n5488 ph[16][14] ph[16][15] $abc$30358$new_n5487 +100 1 +.names $abc$30358$new_n5489 ph[16][10] ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5488 +10000 1 +.names $abc$30358$new_n5490 ph[16][6] ph[16][7] ph[16][8] ph[16][9] $abc$30358$new_n5489 +10000 1 +.names ph[16][1] ph[16][2] ph[16][3] ph[16][4] ph[16][5] $abc$30358$new_n5490 +00000 1 +.names $abc$30358$new_n5492 ph[16][17] yv[16][20] $abc$30358$new_n5491 +110 1 +.names ph[16][16] $abc$30358$new_n5493 $abc$30358$new_n5492 +11 1 +.names ph[16][4] ph[16][6] ph[16][9] $abc$30358$new_n5496 $abc$30358$new_n5494 $abc$30358$new_n5493 +11111 1 +.names ph[16][3] ph[16][5] ph[16][7] ph[16][8] $abc$30358$new_n5495 $abc$30358$new_n5494 +11111 1 +.names ph[16][1] ph[16][2] ph[16][14] ph[16][15] $abc$30358$new_n5495 +1111 1 +.names ph[16][10] ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5496 +1111 1 +.names i_ce ph[16][18] $abc$30358$new_n5491 $abc$30358$new_n5485 ph[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27917 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5499 ph[17][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27919 +001 1 +011 1 +110 1 +111 1 +.names ph[16][17] yv[16][20] $abc$30358$new_n5492 $abc$30358$new_n5486 $abc$30358$new_n5499 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5501 ph[17][16] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$27921 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[16][16] yv[16][20] $abc$30358$new_n5493 $abc$30358$new_n5487 $abc$30358$new_n5501 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n5503 ph[16][15] ph[17][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27923 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][14] $abc$30358$new_n5504 ph[16][13] $abc$30358$new_n5509 ph[16][12] $abc$30358$new_n5503 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n5505 ph[16][11] ph[16][12] ph[16][13] $abc$30358$new_n5504 +1000 1 +.names $abc$30358$new_n5506 ph[16][9] ph[16][10] $abc$30358$new_n5505 +100 1 +.names $abc$30358$new_n5507 ph[16][6] ph[16][7] ph[16][8] $abc$30358$new_n5506 +1000 1 +.names $abc$30358$new_n5508 ph[16][5] $abc$30358$new_n5507 +10 1 +.names yv[16][20] ph[16][1] ph[16][2] ph[16][3] ph[16][4] $abc$30358$new_n5508 +10000 1 +.names ph[16][11] $abc$30358$new_n5510 $abc$30358$new_n5509 +11 1 +.names ph[16][9] ph[16][10] $abc$30358$new_n5511 $abc$30358$new_n5510 +111 1 +.names ph[16][6] ph[16][7] ph[16][8] $abc$30358$new_n5512 $abc$30358$new_n5511 +1111 1 +.names ph[16][5] $abc$30358$new_n5513 $abc$30358$new_n5512 +11 1 +.names ph[16][4] ph[16][1] ph[16][2] ph[16][3] yv[16][20] $abc$30358$new_n5513 +11110 1 +.names i_ce $abc$30358$new_n5515 ph[17][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27925 +001 1 +011 1 +110 1 +111 1 +.names ph[16][14] $abc$30358$new_n5504 ph[16][12] ph[16][13] $abc$30358$new_n5509 $abc$30358$new_n5515 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce ph[17][13] $abc$30358$new_n5504 $abc$30358$new_n5517 $abc$30358$auto$rtlil.cc:2693:MuxGate$27927 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[16][11] ph[16][13] ph[16][12] $abc$30358$new_n5510 $abc$30358$new_n5505 $abc$30358$new_n5517 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5519 ph[16][12] ph[17][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27929 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][11] $abc$30358$new_n5505 $abc$30358$new_n5510 $abc$30358$new_n5519 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[16][11] $abc$30358$new_n5510 $abc$30358$new_n5505 ph[17][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$27931 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5522 i_ce ph[17][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$27933 +001 1 +010 1 +011 1 +.names i_ce ph[16][9] ph[16][10] $abc$30358$new_n5511 $abc$30358$new_n5506 $abc$30358$new_n5522 +10000 1 +10010 1 +10101 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[16][9] $abc$30358$new_n5511 $abc$30358$new_n5506 ph[17][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$27935 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5506 ph[17][8] $abc$30358$new_n5525 $abc$30358$new_n5511 $abc$30358$auto$rtlil.cc:2693:MuxGate$27937 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names ph[16][8] ph[16][6] ph[16][7] $abc$30358$new_n5507 $abc$30358$new_n5512 $abc$30358$new_n5525 +01101 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5527 ph[16][7] ph[17][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$27939 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[16][6] $abc$30358$new_n5507 $abc$30358$new_n5512 $abc$30358$new_n5527 +000 1 +001 1 +100 1 +110 1 +.names i_ce ph[16][6] $abc$30358$new_n5512 $abc$30358$new_n5507 ph[17][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$27941 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[16][5] $abc$30358$new_n5513 $abc$30358$new_n5508 ph[17][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$27943 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5531 ph[17][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$27945 +001 1 +011 1 +100 1 +101 1 +.names ph[16][4] yv[16][20] ph[16][1] ph[16][2] ph[16][3] $abc$30358$new_n5531 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$30358$new_n5533 ph[17][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$27947 +001 1 +011 1 +100 1 +101 1 +.names ph[16][3] yv[16][20] ph[16][1] ph[16][2] $abc$30358$new_n5533 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[16][20] ph[16][1] ph[16][2] ph[17][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$27949 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[16][1] ph[17][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$27951 +001 1 +011 1 +100 1 +101 1 +.names i_ce ph[16][0] ph[17][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$27953 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[16][20] yv[16][19] $abc$30358$new_n5538 yv[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27955 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[16][20] yv[16][18] xv[16][20] $abc$30358$new_n5551 $abc$30358$new_n5539 $abc$30358$new_n5538 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +.names $abc$30358$new_n6084 xv[16][20] yv[16][16] yv[16][17] $abc$30358$new_n5539 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names xv[16][20] $abc$30358$new_n5546 $abc$30358$new_n5543 yv[16][4] $abc$30358$new_n5542 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1110 1 +.names xv[16][19] yv[16][2] $abc$30358$new_n5544 xv[16][20] yv[16][3] $abc$30358$new_n5543 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +.names xv[16][17] yv[16][0] xv[16][18] yv[16][1] $abc$30358$new_n5544 +0011 1 +0111 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names yv[16][6] yv[16][7] yv[16][5] xv[16][20] yv[16][3] $abc$30358$new_n5546 +00010 1 +00011 1 +11101 1 +.names xv[16][20] yv[16][8] yv[16][9] yv[16][10] yv[16][11] $abc$30358$new_n5549 +01111 1 +10000 1 +.names xv[16][20] $abc$30358$new_n5552 yv[16][16] yv[16][17] $abc$30358$new_n5551 +0100 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n5558 $abc$30358$new_n5559 xv[16][20] $abc$30358$new_n5554 $abc$30358$new_n5552 +0010 1 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names xv[16][20] $abc$30358$new_n5557 $abc$30358$new_n5555 yv[16][7] $abc$30358$new_n5554 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names yv[16][2] xv[16][19] $abc$30358$new_n5556 yv[16][3] xv[16][20] $abc$30358$new_n5555 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11100 1 +11101 1 +11111 1 +.names xv[16][17] xv[16][18] yv[16][0] yv[16][1] $abc$30358$new_n5556 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names xv[16][20] yv[16][6] yv[16][4] yv[16][5] yv[16][3] $abc$30358$new_n5557 +00000 1 +00001 1 +11111 1 +.names xv[16][20] yv[16][8] yv[16][9] yv[16][10] yv[16][11] $abc$30358$new_n5558 +00000 1 +11111 1 +.names xv[16][20] yv[16][12] yv[16][13] yv[16][14] yv[16][15] $abc$30358$new_n5559 +00000 1 +11111 1 +.names i_ce xv[16][20] yv[16][18] $abc$30358$new_n5561 yv[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27957 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[16][20] $abc$30358$new_n5539 $abc$30358$new_n5551 $abc$30358$new_n5561 +001 1 +011 1 +100 1 +101 1 +.names i_ce xv[16][19] $abc$30358$new_n6086 $abc$30358$new_n5580 xv[17][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27995 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5578 $abc$30358$new_n6086 $abc$30358$new_n5565 +10 1 +.names $abc$30358$new_n5571 yv[16][20] xv[16][4] $abc$30358$new_n5570 +100 1 +111 1 +.names xv[16][2] yv[16][19] yv[16][20] xv[16][3] $abc$30358$new_n5572 $abc$30358$new_n5571 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names yv[16][17] xv[16][0] xv[16][1] yv[16][18] $abc$30358$new_n5572 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[16][20] xv[16][12] xv[16][13] xv[16][14] xv[16][15] $abc$30358$new_n5578 +00000 1 +11111 1 +.names xv[16][18] xv[16][16] xv[16][17] $abc$30358$new_n5581 $abc$30358$new_n5580 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n5582 xv[16][14] xv[16][15] $abc$30358$new_n5581 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names xv[16][12] xv[16][13] $abc$30358$new_n5583 $abc$30358$new_n5582 +110 1 +.names yv[16][20] $abc$30358$new_n5584 xv[16][10] xv[16][11] $abc$30358$new_n5583 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names yv[16][20] xv[16][8] xv[16][9] $abc$30358$new_n5585 $abc$30358$new_n5584 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +1000 1 +.names xv[16][7] $abc$30358$new_n5586 yv[16][20] xv[16][6] $abc$30358$new_n5585 +0011 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names xv[16][6] yv[16][20] xv[16][4] xv[16][5] $abc$30358$new_n5587 $abc$30358$new_n5586 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +.names xv[16][2] yv[16][19] yv[16][20] xv[16][3] $abc$30358$new_n5588 $abc$30358$new_n5587 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[16][0] yv[16][17] xv[16][1] yv[16][18] $abc$30358$new_n5588 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names i_ce xv[16][17] $abc$30358$new_n5593 xv[17][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27999 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][16] yv[16][20] $abc$30358$new_n5581 $abc$30358$new_n5565 $abc$30358$new_n5593 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$30358$new_n5595 i_ce xv[17][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28001 +001 1 +010 1 +011 1 +.names i_ce yv[16][20] xv[16][16] $abc$30358$new_n5565 $abc$30358$new_n5581 $abc$30358$new_n5595 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce xv[16][15] $abc$30358$new_n5597 xv[17][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28003 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][14] $abc$30358$new_n5582 $abc$30358$new_n5598 $abc$30358$new_n5597 +110 1 +.names xv[16][13] xv[16][12] $abc$30358$new_n6086 $abc$30358$new_n5598 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_ce $abc$30358$new_n5602 xv[17][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28007 +001 1 +011 1 +110 1 +111 1 +.names xv[16][13] xv[16][12] $abc$30358$new_n5583 $abc$30358$new_n6086 $abc$30358$new_n5602 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce xv[16][11] xv[16][10] $abc$30358$new_n5606 xv[17][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28011 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][9] $abc$30358$new_n5607 $abc$30358$new_n5606 +11 1 +.names xv[16][8] $abc$30358$new_n5585 $abc$30358$new_n6088 $abc$30358$new_n5607 +110 1 +.names i_ce xv[16][10] $abc$30358$new_n5606 xv[17][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28013 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][9] $abc$30358$new_n5607 xv[17][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28015 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][7] xv[16][6] $abc$30358$new_n5613 xv[17][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28019 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[16][5] $abc$30358$new_n5615 $abc$30358$new_n5614 $abc$30358$new_n5613 +100 1 +.names yv[16][20] $abc$30358$new_n5570 $abc$30358$new_n5614 +10 1 +.names $abc$30358$new_n5587 xv[16][4] $abc$30358$new_n5615 +00 1 +01 1 +10 1 +.names i_ce xv[16][6] $abc$30358$new_n5613 xv[17][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$28021 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][5] $abc$30358$new_n5615 $abc$30358$new_n5614 xv[17][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28023 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[16][3] $abc$30358$new_n5621 xv[17][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28027 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[16][20] xv[16][2] yv[16][19] $abc$30358$new_n5572 $abc$30358$new_n5588 $abc$30358$new_n5621 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][2] yv[16][19] $abc$30358$new_n5623 xv[17][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28029 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[16][20] $abc$30358$new_n5588 $abc$30358$new_n5572 $abc$30358$new_n5623 +000 1 +001 1 +100 1 +110 1 +.names i_ce $abc$30358$new_n5625 xv[17][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28031 +001 1 +011 1 +110 1 +111 1 +.names xv[16][1] yv[16][18] yv[16][20] xv[16][0] yv[16][17] $abc$30358$new_n5625 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[16][0] yv[16][17] xv[17][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28033 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce ph[17][19] $abc$30358$new_n5628 ph[18][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28035 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][17] ph[17][18] yv[17][20] $abc$30358$new_n5629 $abc$30358$new_n5635 $abc$30358$new_n5628 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5630 ph[17][16] $abc$30358$new_n5629 +10 1 +.names $abc$30358$new_n5631 ph[17][15] $abc$30358$new_n5630 +10 1 +.names $abc$30358$new_n5632 ph[17][13] ph[17][14] $abc$30358$new_n5631 +100 1 +.names $abc$30358$new_n5633 ph[17][9] ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5632 +10000 1 +.names $abc$30358$new_n5634 ph[17][5] ph[17][6] ph[17][7] ph[17][8] $abc$30358$new_n5633 +10000 1 +.names ph[17][0] ph[17][1] ph[17][2] ph[17][3] ph[17][4] $abc$30358$new_n5634 +00000 1 +.names ph[17][16] $abc$30358$new_n5636 $abc$30358$new_n5635 +11 1 +.names ph[17][15] $abc$30358$new_n5637 $abc$30358$new_n5636 +11 1 +.names ph[17][3] ph[17][5] ph[17][8] $abc$30358$new_n5640 $abc$30358$new_n5638 $abc$30358$new_n5637 +11111 1 +.names ph[17][2] ph[17][4] ph[17][6] ph[17][7] $abc$30358$new_n5639 $abc$30358$new_n5638 +11111 1 +.names ph[17][0] ph[17][1] ph[17][13] ph[17][14] $abc$30358$new_n5639 +1111 1 +.names ph[17][9] ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5640 +1111 1 +.names i_ce $abc$30358$new_n5645 ph[18][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28039 +001 1 +011 1 +110 1 +111 1 +.names ph[17][17] yv[17][20] $abc$30358$new_n5635 $abc$30358$new_n5629 $abc$30358$new_n5645 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n5647 ph[18][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28041 +001 1 +011 1 +110 1 +111 1 +.names ph[17][16] yv[17][20] $abc$30358$new_n5636 $abc$30358$new_n5630 $abc$30358$new_n5647 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$30358$new_n5649 ph[18][15] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28043 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ph[17][15] yv[17][20] $abc$30358$new_n5637 $abc$30358$new_n5631 $abc$30358$new_n5649 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce ph[17][14] $abc$30358$new_n5651 ph[18][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28045 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][13] $abc$30358$new_n5652 $abc$30358$new_n5640 $abc$30358$new_n5657 ph[17][8] $abc$30358$new_n5651 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$30358$new_n5653 ph[17][10] ph[17][11] ph[17][12] $abc$30358$new_n5652 +1000 1 +.names $abc$30358$new_n5654 ph[17][8] ph[17][9] $abc$30358$new_n5653 +100 1 +.names $abc$30358$new_n5655 ph[17][7] $abc$30358$new_n5654 +10 1 +.names $abc$30358$new_n5656 ph[17][4] ph[17][5] ph[17][6] $abc$30358$new_n5655 +1000 1 +.names yv[17][20] ph[17][0] ph[17][1] ph[17][2] ph[17][3] $abc$30358$new_n5656 +10000 1 +.names ph[17][7] $abc$30358$new_n5658 $abc$30358$new_n5657 +11 1 +.names ph[17][4] ph[17][5] ph[17][6] $abc$30358$new_n5659 $abc$30358$new_n5658 +1111 1 +.names ph[17][3] ph[17][0] ph[17][1] ph[17][2] yv[17][20] $abc$30358$new_n5659 +11110 1 +.names i_ce $abc$30358$new_n5661 ph[18][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28047 +001 1 +011 1 +110 1 +111 1 +.names ph[17][13] $abc$30358$new_n5652 ph[17][8] $abc$30358$new_n5640 $abc$30358$new_n5657 $abc$30358$new_n5661 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names i_ce $abc$30358$new_n5663 ph[18][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28049 +001 1 +011 1 +110 1 +111 1 +.names ph[17][10] ph[17][12] ph[17][11] $abc$30358$new_n5653 $abc$30358$new_n5664 $abc$30358$new_n5663 +00010 1 +00011 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names ph[17][8] ph[17][9] $abc$30358$new_n5657 $abc$30358$new_n5664 +111 1 +.names i_ce ph[17][11] $abc$30358$new_n5666 ph[18][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28051 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names ph[17][10] $abc$30358$new_n5664 $abc$30358$new_n5653 $abc$30358$new_n5666 +000 1 +010 1 +100 1 +101 1 +.names i_ce ph[17][10] $abc$30358$new_n5653 $abc$30358$new_n5664 ph[18][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28053 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$30358$new_n5669 i_ce ph[18][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28055 +001 1 +010 1 +011 1 +.names i_ce ph[17][9] ph[17][8] $abc$30358$new_n5654 $abc$30358$new_n5657 $abc$30358$new_n5669 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce ph[17][8] $abc$30358$new_n5654 $abc$30358$new_n5657 ph[18][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28057 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[17][7] $abc$30358$new_n5655 $abc$30358$new_n5658 ph[18][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28059 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce ph[18][6] $abc$30358$new_n5655 $abc$30358$new_n5673 $abc$30358$auto$rtlil.cc:2693:MuxGate$28061 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names ph[17][4] ph[17][6] ph[17][5] $abc$30358$new_n5659 $abc$30358$new_n5656 $abc$30358$new_n5673 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5675 ph[18][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28063 +001 1 +011 1 +100 1 +101 1 +.names ph[17][5] ph[17][4] $abc$30358$new_n5656 $abc$30358$new_n5659 $abc$30358$new_n5675 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce ph[17][4] $abc$30358$new_n5656 $abc$30358$new_n5659 ph[18][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28065 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names i_ce $abc$30358$new_n5678 ph[18][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28067 +001 1 +011 1 +100 1 +101 1 +.names ph[17][3] yv[17][20] ph[17][0] ph[17][1] ph[17][2] $abc$30358$new_n5678 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +.names i_ce $abc$30358$new_n5680 ph[18][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28069 +001 1 +011 1 +100 1 +101 1 +.names ph[17][2] yv[17][20] ph[17][0] ph[17][1] $abc$30358$new_n5680 +0000 1 +0001 1 +0010 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +.names i_ce yv[17][20] ph[17][0] ph[17][1] ph[18][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28071 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce ph[17][0] ph[18][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28073 +001 1 +011 1 +100 1 +101 1 +.names i_ce i_xval[12] i_yval[12] ph[0][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28075 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names ph[0][18] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28077 +01 1 +10 1 +11 1 +.names i_ce ph[0][19] yv[0][20] ph[0][18] ph[1][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28079 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce yv[0][20] ph[0][18] ph[1][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28081 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce yv[0][20] ph[1][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28083 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28085 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28087 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28089 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28091 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28093 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28095 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28097 +001 1 +011 1 +100 1 +101 1 +.names i_ce yv[0][20] ph[1][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28099 +001 1 +011 1 +110 1 +111 1 +.names i_ce yv[0][20] ph[1][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28101 +001 1 +011 1 +110 1 +111 1 +.names ph[1][7] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28103 +01 1 +10 1 +11 1 +.names i_ce $abc$30358$new_n5699 xv[18][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$28105 +001 1 +011 1 +100 1 +101 1 +.names xv[17][19] yv[17][20] xv[17][18] $abc$30358$new_n5712 $abc$30358$new_n5700 $abc$30358$new_n5699 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names xv[17][17] xv[17][16] $abc$30358$new_n5701 $abc$30358$new_n5700 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names $abc$30358$new_n5711 $abc$30358$new_n5702 $abc$30358$new_n5701 +00 1 +01 1 +11 1 +.names $abc$30358$new_n5703 $abc$30358$new_n5709 yv[17][20] $abc$30358$new_n5702 +000 1 +010 1 +011 1 +.names $abc$30358$new_n5704 yv[17][20] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5703 +10111 1 +11000 1 +.names xv[17][8] yv[17][20] xv[17][6] xv[17][7] $abc$30358$new_n6098 $abc$30358$new_n5704 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +.names xv[17][0] yv[17][18] xv[17][1] yv[17][19] $abc$30358$new_n5707 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names xv[17][8] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5709 +0000 1 +.names yv[17][20] xv[17][12] xv[17][13] xv[17][14] xv[17][15] $abc$30358$new_n5711 +01111 1 +10000 1 +.names $abc$30358$new_n5725 xv[17][16] xv[17][17] $abc$30358$new_n5712 +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +110 1 +.names $abc$30358$new_n5715 $abc$30358$new_n5709 yv[17][20] $abc$30358$new_n5714 +001 1 +010 1 +011 1 +.names $abc$30358$new_n5716 yv[17][20] xv[17][9] xv[17][10] xv[17][11] $abc$30358$new_n5715 +10000 1 +11111 1 +.names yv[17][20] xv[17][8] xv[17][6] xv[17][7] $abc$30358$new_n5717 $abc$30358$new_n5716 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +11111 1 +.names yv[17][20] xv[17][3] xv[17][4] xv[17][5] $abc$30358$new_n5718 $abc$30358$new_n5717 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +.names yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5718 +000 1 +100 1 +101 1 +110 1 +.names yv[17][18] xv[17][0] xv[17][1] yv[17][19] $abc$30358$new_n5719 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names yv[17][20] xv[17][12] xv[17][13] xv[17][14] xv[17][15] $abc$30358$new_n5720 +00000 1 +11111 1 +.names $abc$30358$new_n5722 i_ce xv[18][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28107 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][18] $abc$30358$new_n5712 $abc$30358$new_n5700 $abc$30358$new_n5722 +10001 1 +10011 1 +10100 1 +10110 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5724 xv[18][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$28109 +001 1 +011 1 +110 1 +111 1 +.names xv[17][17] yv[17][20] xv[17][16] $abc$30358$new_n5725 $abc$30358$new_n5701 $abc$30358$new_n5724 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5720 $abc$30358$new_n5715 $abc$30358$new_n5725 +11 1 +.names $abc$30358$new_n5727 i_ce xv[18][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$28111 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][16] $abc$30358$new_n5725 $abc$30358$new_n5701 $abc$30358$new_n5727 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5729 xv[18][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$28113 +001 1 +011 1 +110 1 +111 1 +.names xv[17][15] xv[17][14] $abc$30358$new_n5731 $abc$30358$new_n5730 $abc$30358$new_n5729 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[17][12] xv[17][13] $abc$30358$new_n5714 $abc$30358$new_n5730 +110 1 +.names xv[17][12] xv[17][13] $abc$30358$new_n5702 $abc$30358$new_n5731 +110 1 +.names i_ce $abc$30358$new_n5735 xv[18][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$28117 +001 1 +011 1 +110 1 +111 1 +.names xv[17][13] yv[17][20] xv[17][12] $abc$30358$new_n5715 $abc$30358$new_n5703 $abc$30358$new_n5735 +00101 1 +00111 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5737 i_ce xv[18][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28119 +001 1 +010 1 +011 1 +.names i_ce xv[17][12] yv[17][20] $abc$30358$new_n5703 $abc$30358$new_n5714 $abc$30358$new_n5737 +10000 1 +10001 1 +10101 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce xv[17][11] xv[17][10] $abc$30358$new_n5739 xv[18][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$28121 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17][9] yv[17][20] $abc$30358$new_n5704 $abc$30358$new_n5716 $abc$30358$new_n5739 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[17][10] $abc$30358$new_n5739 xv[18][10] $abc$30358$auto$rtlil.cc:2693:MuxGate$28123 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5742 xv[18][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$28125 +001 1 +011 1 +110 1 +111 1 +.names yv[17][20] xv[17][9] $abc$30358$new_n5716 $abc$30358$new_n5704 $abc$30358$new_n5742 +0001 1 +0011 1 +0100 1 +0110 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce $abc$30358$new_n5747 xv[18][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$28129 +001 1 +011 1 +110 1 +111 1 +.names xv[17][7] xv[17][6] $abc$30358$new_n5717 $abc$30358$new_n6098 $abc$30358$new_n5747 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce xv[17][5] xv[17][4] $abc$30358$new_n5751 xv[18][5] $abc$30358$auto$rtlil.cc:2693:MuxGate$28133 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[17][3] xv[17][2] yv[17][20] $abc$30358$new_n5707 $abc$30358$new_n5719 $abc$30358$new_n5751 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce yv[17][20] xv[17][4] $abc$30358$new_n5753 xv[18][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28135 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[17][20] xv[17][2] xv[17][3] $abc$30358$new_n5707 $abc$30358$new_n5719 $abc$30358$new_n5753 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5755 xv[18][3] $abc$30358$auto$rtlil.cc:2693:MuxGate$28137 +001 1 +011 1 +110 1 +111 1 +.names xv[17][3] yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5707 $abc$30358$new_n5755 +00100 1 +00110 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5757 i_ce xv[18][2] $abc$30358$auto$rtlil.cc:2693:MuxGate$28139 +001 1 +010 1 +011 1 +.names i_ce yv[17][20] xv[17][2] $abc$30358$new_n5719 $abc$30358$new_n5707 $abc$30358$new_n5757 +10001 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5759 xv[18][1] $abc$30358$auto$rtlil.cc:2693:MuxGate$28141 +001 1 +011 1 +110 1 +111 1 +.names xv[17][1] yv[17][19] yv[17][20] xv[17][0] yv[17][18] $abc$30358$new_n5759 +00011 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11011 1 +11101 1 +.names i_ce xv[17][0] yv[17][18] xv[18][0] $abc$30358$auto$rtlil.cc:2693:MuxGate$28143 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[17][20] $abc$30358$new_n5762 xv[18][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28145 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names xv[17][18] xv[17][19] $abc$30358$new_n5712 yv[17][20] $abc$30358$new_n5700 $abc$30358$new_n5762 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n5766 ph[18][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28147 +001 1 +011 1 +100 1 +101 1 +.names ph[17][20] yv[17][20] ph[17][19] $abc$30358$new_n5628 $abc$30358$new_n5766 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[16][20] $abc$30358$new_n5768 xv[17][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28149 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[16][17] xv[16][18] xv[16][19] $abc$30358$new_n5593 $abc$30358$new_n5768 +1111 1 +.names i_ce yv[16][20] yv[17][20] $abc$30358$new_n5770 $abc$30358$new_n5773 $abc$30358$auto$rtlil.cc:2693:MuxGate$28151 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[16][20] yv[16][19] $abc$30358$new_n5771 $abc$30358$new_n5772 $abc$30358$new_n5770 +0001 1 +1110 1 +1111 1 +.names xv[16][20] yv[16][16] yv[16][17] yv[16][18] $abc$30358$new_n5552 $abc$30358$new_n5771 +00000 1 +11110 1 +.names yv[16][16] yv[16][17] yv[16][18] $abc$30358$new_n5772 +000 1 +.names xv[16][20] yv[16][19] $abc$30358$new_n6084 yv[16][18] $abc$30358$new_n5772 $abc$30358$new_n5773 +01110 1 +01111 1 +10001 1 +10011 1 +.names i_ce $abc$30358$new_n5775 ph[17][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28153 +001 1 +011 1 +100 1 +101 1 +.names ph[16][20] yv[16][20] ph[16][19] $abc$30358$new_n5484 $abc$30358$new_n5775 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[15][20] xv[15][19] $abc$30358$new_n5417 xv[16][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28155 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce yv[15][20] yv[16][20] $abc$30358$new_n5778 $abc$30358$new_n5781 $abc$30358$auto$rtlil.cc:2693:MuxGate$28157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names xv[15][20] yv[15][19] $abc$30358$new_n5779 $abc$30358$new_n5780 $abc$30358$new_n5778 +0001 1 +1110 1 +1111 1 +.names xv[15][20] yv[15][16] yv[15][17] yv[15][18] $abc$30358$new_n5366 $abc$30358$new_n5779 +00000 1 +11110 1 +.names yv[15][16] yv[15][17] yv[15][18] $abc$30358$new_n5780 +000 1 +.names xv[15][20] yv[15][19] $abc$30358$new_n5350 yv[15][18] $abc$30358$new_n5780 $abc$30358$new_n5781 +01110 1 +01111 1 +10001 1 +10011 1 +.names i_ce ph[15][20] $abc$30358$new_n5783 ph[16][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28159 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[15][20] ph[15][19] $abc$30358$new_n5293 $abc$30358$new_n5783 +010 1 +100 1 +.names i_ce xv[14][20] $abc$30358$new_n5785 xv[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28161 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names xv[14][19] $abc$30358$new_n5243 yv[14][20] $abc$30358$new_n5231 $abc$30358$new_n5785 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names i_ce $abc$30358$new_n5796 ph[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28165 +001 1 +011 1 +100 1 +101 1 +.names ph[14][20] yv[14][20] ph[14][19] $abc$30358$new_n5111 $abc$30358$new_n5796 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[13][20] $abc$30358$new_n5798 xv[14][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28167 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[13][19] $abc$30358$new_n5060 $abc$30358$new_n5048 yv[13][20] $abc$30358$new_n5798 +1000 1 +1010 1 +1011 1 +.names i_ce $abc$30358$new_n5809 ph[14][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28171 +001 1 +011 1 +100 1 +101 1 +.names ph[13][20] yv[13][20] ph[13][19] $abc$30358$new_n4931 $abc$30358$new_n5809 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[12][20] xv[12][19] $abc$30358$new_n4867 xv[13][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28173 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5821 ph[13][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28177 +001 1 +011 1 +100 1 +101 1 +.names ph[12][20] yv[12][20] ph[12][19] $abc$30358$new_n4749 $abc$30358$new_n5821 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[11][20] $abc$30358$new_n5823 xv[12][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28179 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[11][19] $abc$30358$new_n4697 yv[11][20] $abc$30358$new_n4686 xv[11][18] $abc$30358$new_n5823 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce $abc$30358$new_n5834 ph[12][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28183 +001 1 +011 1 +100 1 +101 1 +.names ph[11][20] yv[11][20] ph[11][19] $abc$30358$new_n4564 $abc$30358$new_n5834 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[10][20] $abc$30358$new_n5836 xv[11][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28185 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[10][19] $abc$30358$new_n4514 $abc$30358$new_n4503 $abc$30358$new_n5836 +100 1 +.names i_ce yv[11][20] $abc$30358$new_n6127 $abc$30358$new_n5842 $abc$30358$auto$rtlil.cc:2693:MuxGate$28187 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n4449 xv[10][20] yv[10][19] yv[10][18] $abc$30358$new_n5842 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5846 ph[11][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28189 +001 1 +011 1 +100 1 +101 1 +.names ph[10][20] yv[10][20] ph[10][19] $abc$30358$new_n4382 $abc$30358$new_n5846 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[9][20] $abc$30358$new_n5848 xv[10][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28191 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][19] $abc$30358$new_n4330 yv[9][20] $abc$30358$new_n4320 xv[9][18] $abc$30358$new_n5848 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce yv[10][20] $abc$30358$new_n5853 $abc$30358$new_n6129 $abc$30358$auto$rtlil.cc:2693:MuxGate$28193 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n4269 xv[9][20] yv[9][18] yv[9][19] $abc$30358$new_n5853 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5857 ph[10][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28195 +001 1 +011 1 +100 1 +101 1 +.names ph[9][20] yv[9][20] ph[9][19] $abc$30358$new_n4200 $abc$30358$new_n5857 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names xv[8][18] xv[8][19] $abc$30358$new_n5860 +11 1 +.names i_ce ph[8][20] $abc$30358$new_n4018 $abc$30358$new_n5871 ph[9][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28201 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[8][20] ph[8][19] $abc$30358$new_n5871 +00 1 +11 1 +.names i_ce xv[7][20] $abc$30358$new_n5873 xv[8][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28203 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[7][19] $abc$30358$new_n3969 yv[7][20] $abc$30358$new_n3955 xv[7][18] $abc$30358$new_n5873 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce ph[7][20] $abc$30358$new_n5884 ph[8][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28207 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[7][20] ph[7][19] $abc$30358$new_n3837 $abc$30358$new_n5884 +010 1 +100 1 +.names i_ce xv[6][20] $abc$30358$new_n5886 xv[7][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28209 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5887 yv[6][20] xv[6][16] xv[6][17] $abc$30358$new_n3770 $abc$30358$new_n5886 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[6][19] xv[6][18] $abc$30358$new_n3780 yv[6][20] $abc$30358$new_n5887 +1100 1 +1101 1 +1110 1 +.names $abc$30358$new_n3719 xv[6][20] yv[6][18] yv[6][19] $abc$30358$new_n5894 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5898 ph[7][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28213 +001 1 +011 1 +100 1 +101 1 +.names ph[6][20] yv[6][20] ph[6][19] $abc$30358$new_n3654 $abc$30358$new_n5898 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[5][20] $abc$30358$new_n5900 xv[6][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28215 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n5902 yv[5][20] $abc$30358$new_n3599 xv[5][17] $abc$30358$new_n5901 $abc$30358$new_n5900 +10011 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[5][16] xv[5][14] xv[5][15] $abc$30358$new_n3590 $abc$30358$new_n5901 +1111 1 +.names xv[5][18] xv[5][19] $abc$30358$new_n5902 +11 1 +.names i_ce yv[6][20] $abc$30358$new_n6150 $abc$30358$new_n6152 $abc$30358$auto$rtlil.cc:2693:MuxGate$28217 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names i_ce $abc$30358$new_n5912 ph[6][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28219 +001 1 +011 1 +100 1 +101 1 +.names ph[5][20] yv[5][20] ph[5][19] $abc$30358$new_n3475 $abc$30358$new_n5912 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +1011 1 +1101 1 +.names i_ce xv[4][20] $abc$30358$new_n5914 xv[5][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28221 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[4][19] $abc$30358$new_n3415 $abc$30358$new_n3424 yv[4][20] $abc$30358$new_n5914 +1000 1 +1010 1 +1011 1 +.names i_ce yv[5][20] $abc$30358$new_n5916 $abc$30358$new_n6154 $abc$30358$auto$rtlil.cc:2693:MuxGate$28223 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3352 xv[4][20] yv[4][19] yv[4][18] $abc$30358$new_n5916 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5924 ph[5][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28225 +001 1 +011 1 +100 1 +101 1 +.names ph[4][20] yv[4][20] ph[4][19] $abc$30358$new_n3298 $abc$30358$new_n5924 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[3][20] $abc$30358$new_n5926 xv[4][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28227 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[3][19] $abc$30358$new_n3249 $abc$30358$new_n3240 $abc$30358$new_n5926 +100 1 +.names i_ce yv[4][20] $abc$30358$new_n6156 $abc$30358$new_n5932 $abc$30358$auto$rtlil.cc:2693:MuxGate$28229 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$30358$new_n3170 xv[3][20] yv[3][19] yv[3][18] $abc$30358$new_n5932 +0111 1 +1000 1 +.names i_ce $abc$30358$new_n5935 ph[4][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28231 +001 1 +011 1 +100 1 +101 1 +.names ph[3][20] ph[3][19] $abc$30358$new_n3122 $abc$30358$new_n3116 $abc$30358$new_n5935 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_ce xv[2][20] $abc$30358$new_n5937 xv[3][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28233 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[2][19] xv[2][18] yv[2][20] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n5937 +11010 1 +11011 1 +11101 1 +11111 1 +.names yv[2][19] xv[2][20] yv[2][18] $abc$30358$new_n2986 $abc$30358$new_n5939 +0001 1 +1110 1 +.names i_ce $abc$30358$new_n5944 ph[3][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28237 +001 1 +011 1 +100 1 +101 1 +.names ph[2][20] yv[2][20] ph[2][19] $abc$30358$new_n2932 $abc$30358$new_n5944 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[1][20] $abc$30358$new_n5946 xv[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28239 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[1][19] xv[1][18] yv[1][20] $abc$30358$new_n2873 $abc$30358$new_n2882 $abc$30358$new_n5946 +11000 1 +11001 1 +11100 1 +11110 1 +.names i_ce xv[1][20] yv[1][18] yv[1][19] $abc$30358$new_n2804 $abc$30358$new_n5950 +10001 1 +11110 1 +.names i_ce $abc$30358$new_n5953 ph[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28243 +001 1 +011 1 +100 1 +101 1 +.names ph[1][20] ph[1][19] yv[1][20] $abc$30358$new_n2766 $abc$30358$new_n5953 +0000 1 +0001 1 +0011 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +.names i_ce xv[0][20] xv[0][19] $abc$30358$new_n2709 xv[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28245 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[0][20] $abc$30358$new_n5959 $abc$30358$new_n5956 yv[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28247 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n5958 xv[0][19] yv[0][18] $abc$30358$new_n2640 $abc$30358$new_n5957 $abc$30358$new_n5956 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[0][20] yv[0][19] $abc$30358$new_n5957 +11 1 +.names yv[0][20] yv[0][19] xv[0][20] $abc$30358$new_n5958 +101 1 +110 1 +111 1 +.names yv[0][20] yv[0][19] xv[0][20] $abc$30358$new_n2649 $abc$30358$new_n5959 +0000 1 +0100 1 +0101 1 +0110 1 +.names i_ce $abc$30358$new_n5961 o_mag[12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28249 +001 1 +011 1 +110 1 +111 1 +.names xv[18][20] xv[18][18] xv[18][19] $abc$30358$new_n2619 $abc$30358$new_n5961 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names i_ce ph[18][20] o_phase[20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28251 +001 1 +011 1 +110 1 +111 1 +.names i_ce ax[18] o_aux $abc$30358$auto$rtlil.cc:2693:MuxGate$28253 +001 1 +011 1 +110 1 +111 1 +.names xv[0][20] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28255 +10 1 +.names $abc$30358$new_n6162 yv[0][20] i_ce $abc$30358$auto$rtlil.cc:2693:MuxGate$28257 +010 1 +100 1 +101 1 +110 1 +111 1 +.names i_ce ax[17] ax[18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28259 +001 1 +011 1 +110 1 +111 1 +.names i_ce i_yval[12] ph[0][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28261 +001 1 +011 1 +110 1 +111 1 +.names i_ce $abc$30358$new_n5969 ph[1][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28263 +001 1 +011 1 +100 1 +101 1 +.names ph[0][20] yv[0][20] ph[0][18] ph[0][19] $abc$30358$new_n5969 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names i_yval[11] i_xval[11] i_xval[12] $abc$30358$new_n2460 $abc$30358$new_n2467 $abc$30358$new_n5970 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_xval[12] $abc$30358$new_n2532 $abc$30358$new_n2464 i_yval[12] $abc$30358$new_n2531 $abc$30358$new_n5972 +00011 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5972 i_yval[12] $abc$30358$new_n2533 $abc$30358$new_n2535 $abc$30358$new_n5973 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +.names i_ce $abc$30358$new_n5973 yv[0][9] $abc$30358$auto$rtlil.cc:2693:MuxGate$25911 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[0][18] $abc$30358$new_n6164 $abc$30358$new_n2563 $abc$30358$auto$rtlil.cc:2693:MuxGate$25933 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names yv[1][20] xv[1][18] $abc$30358$new_n2873 $abc$30358$new_n2882 $abc$30358$new_n5980 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n5980 xv[2][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26197 +001 1 +011 1 +110 1 +111 1 +.names yv[1][20] xv[1][16] yv[1][18] $abc$30358$new_n2883 $abc$30358$new_n2874 $abc$30358$new_n5982 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[1][17] $abc$30358$new_n5982 yv[1][19] xv[2][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26199 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][18] $abc$30358$new_n3055 $abc$30358$new_n3064 $abc$30358$new_n5984 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n5984 xv[3][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26317 +001 1 +011 1 +110 1 +111 1 +.names yv[2][20] xv[2][12] yv[2][15] $abc$30358$new_n3067 $abc$30358$new_n3058 $abc$30358$new_n5986 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[2][13] $abc$30358$new_n5986 yv[2][16] xv[3][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26327 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[2][20] xv[2][10] yv[2][13] $abc$30358$new_n3068 $abc$30358$new_n3059 $abc$30358$new_n5988 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[2][11] $abc$30358$new_n5988 yv[2][14] xv[3][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26331 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[3][20] ph[3][13] ph[3][14] $abc$30358$new_n3118 $abc$30358$new_n3124 $abc$30358$new_n5990 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n5990 ph[3][15] ph[4][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26363 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[3][17] xv[3][16] yv[3][20] $abc$30358$new_n3250 $abc$30358$new_n3241 $abc$30358$new_n5992 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5992 xv[3][18] xv[4][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26437 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[3][20] xv[3][10] yv[3][14] $abc$30358$new_n3253 $abc$30358$new_n3244 $abc$30358$new_n5994 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[3][11] $abc$30358$new_n5994 yv[3][15] xv[4][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26451 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names xv[4][17] xv[4][16] yv[4][20] $abc$30358$new_n3425 $abc$30358$new_n3416 $abc$30358$new_n5996 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n5996 xv[4][18] xv[5][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26557 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[4][20] xv[4][12] yv[4][17] $abc$30358$new_n3427 $abc$30358$new_n3418 $abc$30358$new_n5998 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce xv[4][13] $abc$30358$new_n5998 yv[4][18] xv[5][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26567 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[4][20] xv[4][10] yv[4][15] $abc$30358$new_n3428 $abc$30358$new_n3419 $abc$30358$new_n6000 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_ce xv[4][11] $abc$30358$new_n6000 yv[4][16] xv[5][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26571 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] xv[5][16] yv[5][10] $abc$30358$new_n3534 $abc$30358$new_n3543 $abc$30358$new_n6002 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[5][17] $abc$30358$new_n6002 yv[5][11] yv[6][11] $abc$30358$auto$rtlil.cc:2693:MuxGate$26651 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names yv[5][20] $abc$30358$new_n3599 xv[5][17] xv[5][16] $abc$30358$new_n3589 $abc$30358$new_n6004 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[5][19] $abc$30358$new_n6004 xv[5][18] xv[6][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26675 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[5][20] $abc$30358$new_n3599 xv[5][17] xv[5][16] $abc$30358$new_n3589 $abc$30358$new_n6006 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6006 xv[5][18] xv[6][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26677 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] xv[6][20] $abc$30358$new_n3712 yv[6][14] $abc$30358$new_n3737 $abc$30358$new_n6008 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6008 yv[6][15] yv[7][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26763 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[6][20] $abc$30358$new_n3780 xv[6][17] xv[6][16] $abc$30358$new_n3770 $abc$30358$new_n6010 +00110 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_ce xv[6][19] $abc$30358$new_n6010 xv[6][18] xv[7][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$26795 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[6][20] $abc$30358$new_n3780 xv[6][17] xv[6][16] $abc$30358$new_n3770 $abc$30358$new_n6012 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6012 xv[6][18] xv[7][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26797 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names yv[7][20] ph[7][13] ph[7][12] $abc$30358$new_n3841 $abc$30358$new_n3847 $abc$30358$new_n6014 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6014 ph[8][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$26847 +001 1 +011 1 +110 1 +111 1 +.names yv[7][20] $abc$30358$new_n3955 xv[7][16] xv[7][17] $abc$30358$new_n3970 $abc$30358$new_n6016 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names i_ce $abc$30358$new_n6016 xv[7][18] xv[8][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$26917 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[7][17] yv[7][20] xv[7][16] $abc$30358$new_n3956 $abc$30358$new_n3984 $abc$30358$new_n6018 +00100 1 +00101 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n6018 xv[8][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$26919 +001 1 +011 1 +110 1 +111 1 +.names yv[8][20] ph[8][15] ph[8][14] $abc$30358$new_n4021 $abc$30358$new_n4029 $abc$30358$new_n6020 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6020 ph[9][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$26963 +001 1 +011 1 +110 1 +111 1 +.names xv[8][17] xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6022 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce xv[8][19] $abc$30358$new_n6022 xv[8][18] xv[9][19] $abc$30358$auto$rtlil.cc:2693:MuxGate$27035 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][17] xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6024 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6024 xv[8][18] xv[9][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27037 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] ph[9][15] ph[9][14] $abc$30358$new_n4212 $abc$30358$new_n4204 $abc$30358$new_n6026 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6026 ph[10][15] $abc$30358$auto$rtlil.cc:2693:MuxGate$27083 +001 1 +011 1 +110 1 +111 1 +.names yv[9][20] $abc$30358$new_n4213 ph[9][12] $abc$30358$new_n4209 $abc$30358$new_n4205 $abc$30358$new_n6028 +00011 1 +00111 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_ce $abc$30358$new_n6028 ph[9][13] ph[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27087 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[9][17] xv[9][16] yv[9][20] $abc$30358$new_n4331 $abc$30358$new_n4321 $abc$30358$new_n6030 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6030 xv[9][18] xv[10][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27157 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[9][20] xv[9][14] $abc$30358$new_n4322 xv[9][13] $abc$30358$new_n4348 $abc$30358$new_n6032 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6032 xv[10][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27165 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4333 yv[9][20] xv[9][10] xv[9][11] $abc$30358$new_n4323 $abc$30358$new_n6034 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_ce xv[9][13] $abc$30358$new_n6034 xv[9][12] xv[10][13] $abc$30358$auto$rtlil.cc:2693:MuxGate$27167 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[9][20] $abc$30358$new_n4333 xv[9][11] xv[9][10] $abc$30358$new_n4323 $abc$30358$new_n6036 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6036 xv[9][12] xv[10][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27169 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$30358$new_n4447 yv[10][20] $abc$30358$new_n4470 $abc$30358$new_n4468 $abc$30358$new_n6038 +0010 1 +0011 1 +0100 1 +0110 1 +1000 1 +1001 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6038 yv[11][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27245 +001 1 +011 1 +110 1 +111 1 +.names xv[10][17] xv[10][16] yv[10][20] $abc$30358$new_n4514 $abc$30358$new_n4504 $abc$30358$new_n6040 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6040 xv[10][18] xv[11][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27277 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[10][16] $abc$30358$new_n4527 $abc$30358$new_n4514 xv[11][16] $abc$30358$auto$rtlil.cc:2693:MuxGate$27281 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[10][14] $abc$30358$new_n4515 $abc$30358$new_n4505 xv[11][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27285 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_ce xv[10][12] $abc$30358$new_n4516 $abc$30358$new_n4506 xv[11][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27289 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names yv[11][10] yv[11][11] yv[11][12] yv[11][13] yv[11][15] $abc$30358$new_n6045 +00000 1 +11111 1 +.names xv[11][20] $abc$30358$new_n4636 $abc$30358$new_n6045 yv[11][14] yv[11][15] $abc$30358$new_n6046 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[11][17] xv[11][16] yv[11][20] $abc$30358$new_n4699 $abc$30358$new_n4687 $abc$30358$new_n6047 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6047 xv[11][18] xv[12][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27397 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[11][14] $abc$30358$new_n4717 $abc$30358$new_n4718 xv[12][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27405 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[11][12] $abc$30358$new_n4701 $abc$30358$new_n4688 xv[12][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27409 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[12][10] yv[12][11] yv[12][12] yv[12][13] yv[12][15] $abc$30358$new_n6051 +00000 1 +11111 1 +.names xv[12][20] $abc$30358$new_n4802 $abc$30358$new_n6051 yv[12][14] yv[12][15] $abc$30358$new_n6052 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[12][20] xv[12][20] yv[12][16] $abc$30358$new_n6052 $abc$30358$new_n4814 $abc$30358$new_n6053 +00010 1 +00011 1 +01100 1 +01101 1 +10100 1 +10110 1 +11001 1 +11011 1 +.names i_ce $abc$30358$new_n6053 yv[12][17] yv[13][17] $abc$30358$auto$rtlil.cc:2693:MuxGate$27479 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$30358$new_n4882 xv[12][11] xv[12][9] xv[12][10] xv[12][8] $abc$30358$new_n6055 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6055 xv[12][11] yv[12][20] $abc$30358$new_n6056 +000 1 +001 1 +101 1 +111 1 +.names yv[12][20] xv[12][18] $abc$30358$new_n4889 $abc$30358$new_n4869 $abc$30358$new_n4878 $abc$30358$new_n6057 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce $abc$30358$new_n6057 xv[13][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27517 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[12][12] $abc$30358$new_n6056 $abc$30358$new_n4871 xv[13][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27529 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names xv[12][8] yv[12][20] xv[12][7] $abc$30358$new_n4873 $abc$30358$new_n4883 $abc$30358$new_n6060 +00100 1 +00101 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6060 xv[13][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27537 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n4988 yv[13][12] yv[13][13] yv[13][14] yv[13][15] $abc$30358$new_n6062 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6062 yv[13][15] xv[13][20] $abc$30358$new_n6063 +000 1 +001 1 +100 1 +110 1 +.names $abc$30358$new_n5053 xv[13][11] xv[13][9] xv[13][10] xv[13][8] $abc$30358$new_n6064 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6064 xv[13][11] yv[13][20] $abc$30358$new_n6065 +000 1 +001 1 +101 1 +111 1 +.names yv[13][20] xv[13][9] xv[13][10] xv[13][11] xv[13][14] $abc$30358$new_n6066 +01111 1 +10000 1 +.names $abc$30358$new_n5070 $abc$30358$new_n5064 $abc$30358$new_n6066 xv[13][15] xv[13][16] $abc$30358$new_n6067 +11111 1 +.names yv[13][20] xv[13][18] $abc$30358$new_n6067 xv[13][17] $abc$30358$new_n5049 $abc$30358$new_n6068 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n6068 xv[14][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27637 +001 1 +011 1 +110 1 +111 1 +.names xv[13][13] xv[13][12] yv[13][20] $abc$30358$new_n6065 $abc$30358$new_n5063 $abc$30358$new_n6070 +11001 1 +11011 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6070 xv[13][14] xv[14][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$27645 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names xv[13][6] xv[13][7] yv[13][20] $abc$30358$new_n5054 $abc$30358$new_n5065 $abc$30358$new_n6072 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6072 xv[13][8] xv[14][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27657 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[14][20] xv[14][18] $abc$30358$new_n5230 $abc$30358$new_n5244 $abc$30358$new_n6074 +0000 1 +0001 1 +0110 1 +0111 1 +1000 1 +1010 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6074 xv[15][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27757 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[14][8] $abc$30358$new_n5248 $abc$30358$new_n5235 xv[15][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$27777 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n5433 xv[15][11] xv[15][9] xv[15][10] xv[15][8] $abc$30358$new_n6077 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6077 xv[15][11] yv[15][20] $abc$30358$new_n6078 +000 1 +001 1 +101 1 +111 1 +.names yv[15][20] xv[15][18] $abc$30358$new_n5418 $abc$30358$new_n5429 $abc$30358$new_n6079 +0000 1 +0001 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1110 1 +.names i_ce $abc$30358$new_n6079 xv[16][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27877 +001 1 +011 1 +110 1 +111 1 +.names i_ce xv[15][12] $abc$30358$new_n6078 $abc$30358$new_n5421 xv[16][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$27889 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[16][12] yv[16][13] yv[16][14] yv[16][15] yv[16][17] $abc$30358$new_n6082 +00000 1 +11111 1 +.names yv[16][17] yv[16][16] xv[16][20] $abc$30358$new_n6082 $abc$30358$new_n5542 $abc$30358$new_n6083 +00100 1 +00101 1 +00110 1 +11010 1 +.names $abc$30358$new_n5549 $abc$30358$new_n6083 xv[16][20] yv[16][17] yv[16][16] $abc$30358$new_n6084 +00100 1 +01100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6088 xv[16][8] xv[16][9] xv[16][10] xv[16][11] $abc$30358$new_n6085 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6085 xv[16][11] yv[16][20] $abc$30358$new_n6086 +000 1 +001 1 +101 1 +111 1 +.names $abc$30358$new_n5570 xv[16][7] xv[16][5] xv[16][6] xv[16][4] $abc$30358$new_n6087 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$30358$new_n6087 xv[16][7] yv[16][20] $abc$30358$new_n6088 +000 1 +001 1 +101 1 +111 1 +.names xv[16][16] xv[16][17] yv[16][20] $abc$30358$new_n5565 $abc$30358$new_n5581 $abc$30358$new_n6089 +11000 1 +11010 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6089 xv[16][18] xv[17][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$27997 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[16][14] $abc$30358$new_n5582 $abc$30358$new_n5598 xv[17][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28005 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][12] $abc$30358$new_n6086 $abc$30358$new_n5583 xv[17][12] $abc$30358$auto$rtlil.cc:2693:MuxGate$28009 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce xv[16][8] $abc$30358$new_n5585 $abc$30358$new_n6088 xv[17][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28017 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_ce xv[16][4] $abc$30358$new_n5587 $abc$30358$new_n5571 xv[17][4] $abc$30358$auto$rtlil.cc:2693:MuxGate$28025 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names yv[17][20] ph[17][18] ph[17][17] $abc$30358$new_n5629 $abc$30358$new_n5635 $abc$30358$new_n6095 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6095 ph[18][18] $abc$30358$auto$rtlil.cc:2693:MuxGate$28037 +001 1 +011 1 +110 1 +111 1 +.names $abc$30358$new_n5707 xv[17][2] xv[17][3] xv[17][4] xv[17][5] $abc$30358$new_n6097 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$30358$new_n6097 xv[17][5] yv[17][20] $abc$30358$new_n6098 +000 1 +001 1 +100 1 +110 1 +.names i_ce xv[17][14] $abc$30358$new_n5731 $abc$30358$new_n5730 xv[18][14] $abc$30358$auto$rtlil.cc:2693:MuxGate$28115 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[17][6] xv[17][7] yv[17][20] $abc$30358$new_n5717 $abc$30358$new_n6098 $abc$30358$new_n6100 +11000 1 +11010 1 +11110 1 +11111 1 +.names i_ce $abc$30358$new_n6100 xv[17][8] xv[18][8] $abc$30358$auto$rtlil.cc:2693:MuxGate$28127 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names i_ce xv[17][6] $abc$30358$new_n5717 $abc$30358$new_n6098 xv[18][6] $abc$30358$auto$rtlil.cc:2693:MuxGate$28131 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names xv[14][20] yv[14][16] yv[14][17] yv[14][18] yv[14][19] $abc$30358$new_n6103 +00000 1 +11111 1 +.names $abc$30358$new_n6103 $abc$30358$new_n5166 yv[14][19] $abc$30358$new_n6107 $abc$30358$new_n6104 +0001 1 +0011 1 +0101 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_ce $abc$30358$new_n6104 yv[15][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28163 +001 1 +011 1 +110 1 +111 1 +.names xv[14][20] yv[14][18] yv[14][19] yv[14][16] yv[14][17] $abc$30358$new_n6106 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[14][20] $abc$30358$new_n5177 yv[14][19] $abc$30358$new_n6106 $abc$30358$new_n6107 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[13][20] yv[13][16] yv[13][17] yv[13][18] yv[13][19] $abc$30358$new_n6108 +01111 1 +10000 1 +.names xv[13][20] yv[13][16] yv[13][17] yv[13][18] yv[13][19] $abc$30358$new_n6110 +00000 1 +11111 1 +.names xv[12][20] yv[12][18] yv[12][19] yv[12][16] yv[12][17] $abc$30358$new_n6114 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names xv[12][20] yv[12][16] yv[12][17] yv[12][18] yv[12][19] $abc$30358$new_n6116 +00000 1 +11111 1 +.names xv[11][20] yv[11][16] yv[11][17] yv[11][18] yv[11][19] $abc$30358$new_n6120 +01111 1 +10000 1 +.names xv[11][20] yv[11][16] yv[11][17] yv[11][18] yv[11][19] $abc$30358$new_n6122 +00000 1 +11111 1 +.names xv[10][20] yv[10][18] yv[10][19] yv[10][16] yv[10][17] $abc$30358$new_n6126 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[10][20] $abc$30358$new_n4434 yv[10][19] $abc$30358$new_n6126 $abc$30358$new_n6127 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names xv[9][20] yv[9][16] yv[9][17] yv[9][18] yv[9][19] $abc$30358$new_n6128 +01111 1 +10000 1 +.names yv[9][20] $abc$30358$new_n4260 yv[9][19] $abc$30358$new_n6128 $abc$30358$new_n6129 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$30358$new_n5860 xv[8][16] yv[8][20] $abc$30358$new_n4150 $abc$30358$new_n4139 $abc$30358$new_n6130 +11000 1 +11010 1 +11100 1 +11101 1 +.names i_ce xv[8][20] $abc$30358$new_n6130 xv[8][17] xv[9][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28197 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names xv[8][20] yv[8][16] yv[8][17] yv[8][18] yv[8][19] $abc$30358$new_n6132 +01111 1 +10000 1 +.names xv[8][20] yv[8][16] yv[8][17] yv[8][18] yv[8][19] $abc$30358$new_n6134 +00000 1 +11111 1 +.names xv[7][20] yv[7][16] yv[7][17] yv[7][18] yv[7][19] $abc$30358$new_n6138 +01111 1 +10000 1 +.names xv[7][20] yv[7][16] yv[7][17] yv[7][18] yv[7][19] $abc$30358$new_n6140 +00000 1 +11111 1 +.names xv[6][20] yv[6][14] yv[6][15] yv[6][16] yv[6][19] $abc$30358$new_n6144 +01111 1 +10000 1 +.names $abc$30358$new_n6144 $abc$30358$new_n3712 yv[6][17] yv[6][18] yv[6][19] $abc$30358$new_n6145 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names yv[6][20] $abc$30358$new_n6145 $abc$30358$new_n6146 +11 1 +.names xv[5][20] yv[5][18] yv[5][19] yv[5][16] yv[5][17] $abc$30358$new_n6149 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[5][20] $abc$30358$new_n3539 yv[5][19] $abc$30358$new_n6149 $abc$30358$new_n6150 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[5][20] yv[5][16] yv[5][17] yv[5][18] yv[5][19] $abc$30358$new_n6151 +00000 1 +11111 1 +.names $abc$30358$new_n6151 $abc$30358$new_n3531 yv[5][19] $abc$30358$new_n6152 +101 1 +110 1 +.names xv[4][20] yv[4][18] yv[4][19] yv[4][16] yv[4][17] $abc$30358$new_n6153 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[4][20] $abc$30358$new_n3363 yv[4][19] $abc$30358$new_n6153 $abc$30358$new_n6154 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[3][20] yv[3][18] yv[3][19] yv[3][16] yv[3][17] $abc$30358$new_n6155 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names yv[3][20] $abc$30358$new_n3189 yv[3][19] $abc$30358$new_n6155 $abc$30358$new_n6156 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names xv[2][20] $abc$30358$new_n3003 yv[2][19] yv[2][18] yv[2][20] $abc$30358$new_n6157 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names i_ce yv[3][20] $abc$30358$new_n6157 $abc$30358$new_n5939 $abc$30358$auto$rtlil.cc:2693:MuxGate$28235 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$30358$new_n2821 xv[1][20] yv[1][19] yv[1][18] yv[1][20] $abc$30358$new_n6159 +00001 1 +00011 1 +00101 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names i_ce $abc$30358$new_n5950 $abc$30358$new_n6159 yv[2][20] $abc$30358$auto$rtlil.cc:2693:MuxGate$28241 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_xval[12] $abc$30358$new_n2425 $abc$30358$new_n2442 i_yval[11] i_xval[11] $abc$30358$new_n6161 +00001 1 +01000 1 +01001 1 +01011 1 +01101 1 +.names i_ce i_yval[12] $abc$30358$new_n2444 $abc$30358$new_n5970 $abc$30358$new_n6161 $abc$30358$new_n6162 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_yval[11] i_xval[11] i_yval[12] $abc$30358$new_n2460 $abc$30358$new_n2467 $abc$30358$new_n6163 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names i_xval[12] i_yval[12] $abc$30358$new_n2476 $abc$30358$new_n2454 $abc$30358$new_n6163 $abc$30358$new_n6164 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_yval[1] i_yval[0] i_xval[0] i_xval[12] i_yval[12] $abc$30358$new_n6165 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11101 1 +11110 1 +.names i_ce i_xval[1] $abc$30358$new_n6165 xv[0][7] $abc$30358$auto$rtlil.cc:2693:MuxGate$25955 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names yv[13][20] yv[13][19] $abc$30358$new_n6108 $abc$30358$new_n6063 $abc$30358$new_n4997 $abc$30358$new_n6169 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6169 yv[13][20] yv[14][20] $abc$30358$new_n6110 $abc$30358$auto$rtlil.cc:2693:MuxGate$28169 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[12][20] yv[12][19] $abc$30358$new_n6114 $abc$30358$new_n4813 $abc$30358$new_n6052 $abc$30358$new_n6173 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6173 yv[12][20] yv[13][20] $abc$30358$new_n6116 $abc$30358$auto$rtlil.cc:2693:MuxGate$28175 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[11][20] yv[11][19] $abc$30358$new_n6120 $abc$30358$new_n4619 $abc$30358$new_n6046 $abc$30358$new_n6177 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6177 yv[11][20] yv[12][20] $abc$30358$new_n6122 $abc$30358$auto$rtlil.cc:2693:MuxGate$28181 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[8][20] yv[8][19] $abc$30358$new_n6132 $abc$30358$new_n4088 $abc$30358$new_n4075 $abc$30358$new_n6181 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6181 yv[8][20] yv[9][20] $abc$30358$new_n6134 $abc$30358$auto$rtlil.cc:2693:MuxGate$28199 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names yv[7][20] yv[7][19] $abc$30358$new_n6138 $abc$30358$new_n3891 $abc$30358$new_n3904 $abc$30358$new_n6185 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11100 1 +11101 1 +.names i_ce $abc$30358$new_n6185 yv[7][20] yv[8][20] $abc$30358$new_n6140 $abc$30358$auto$rtlil.cc:2693:MuxGate$28205 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names i_ce yv[7][20] $abc$30358$new_n6146 $abc$30358$new_n5894 $abc$30358$auto$rtlil.cc:2693:MuxGate$28211 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28143 Q=xv[18][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28141 Q=xv[18][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28139 Q=xv[18][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28137 Q=xv[18][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28135 Q=xv[18][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28133 Q=xv[18][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28131 Q=xv[18][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28129 Q=xv[18][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28127 Q=xv[18][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28125 Q=xv[18][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28123 Q=xv[18][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28121 Q=xv[18][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28119 Q=xv[18][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28117 Q=xv[18][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28115 Q=xv[18][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28113 Q=xv[18][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28111 Q=xv[18][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28109 Q=xv[18][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28107 Q=xv[18][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28105 Q=xv[18][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28145 Q=xv[18][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28103 Q=ph[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28101 Q=ph[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28099 Q=ph[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28097 Q=ph[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28095 Q=ph[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28093 Q=ph[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28091 Q=ph[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28089 Q=ph[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28087 Q=ph[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28085 Q=ph[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28083 Q=ph[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28081 Q=ph[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28079 Q=ph[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28263 Q=ph[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28077 Q=ph[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28075 Q=ph[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28261 Q=ph[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28073 Q=ph[18][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28071 Q=ph[18][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28069 Q=ph[18][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28067 Q=ph[18][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28065 Q=ph[18][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28063 Q=ph[18][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28061 Q=ph[18][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28059 Q=ph[18][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28057 Q=ph[18][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28055 Q=ph[18][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28053 Q=ph[18][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28051 Q=ph[18][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28049 Q=ph[18][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28047 Q=ph[18][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28045 Q=ph[18][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28043 Q=ph[18][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28041 Q=ph[18][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28039 Q=ph[18][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28037 Q=ph[18][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28035 Q=ph[18][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28147 Q=ph[18][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28033 Q=xv[17][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28031 Q=xv[17][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28029 Q=xv[17][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28027 Q=xv[17][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28025 Q=xv[17][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28023 Q=xv[17][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28021 Q=xv[17][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28019 Q=xv[17][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28017 Q=xv[17][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28015 Q=xv[17][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28013 Q=xv[17][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28011 Q=xv[17][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28009 Q=xv[17][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28007 Q=xv[17][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28005 Q=xv[17][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28003 Q=xv[17][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28001 Q=xv[17][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27999 Q=xv[17][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27997 Q=xv[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27995 Q=xv[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28149 Q=xv[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27957 Q=yv[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27955 Q=yv[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28151 Q=yv[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27953 Q=ph[17][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27951 Q=ph[17][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27949 Q=ph[17][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27947 Q=ph[17][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27945 Q=ph[17][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27943 Q=ph[17][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27941 Q=ph[17][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27939 Q=ph[17][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27937 Q=ph[17][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27935 Q=ph[17][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27933 Q=ph[17][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27931 Q=ph[17][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27929 Q=ph[17][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27927 Q=ph[17][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27925 Q=ph[17][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27923 Q=ph[17][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27921 Q=ph[17][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27919 Q=ph[17][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27917 Q=ph[17][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27915 Q=ph[17][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28153 Q=ph[17][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27913 Q=xv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27911 Q=xv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27909 Q=xv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27907 Q=xv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27905 Q=xv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27903 Q=xv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27901 Q=xv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27899 Q=xv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27897 Q=xv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27895 Q=xv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27893 Q=xv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27891 Q=xv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27889 Q=xv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27887 Q=xv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27885 Q=xv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27883 Q=xv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27881 Q=xv[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27879 Q=xv[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27877 Q=xv[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27875 Q=xv[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28155 Q=xv[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27873 Q=yv[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27871 Q=yv[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27869 Q=yv[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27867 Q=yv[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27865 Q=yv[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27863 Q=yv[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27861 Q=yv[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27859 Q=yv[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27857 Q=yv[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27855 Q=yv[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27853 Q=yv[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27851 Q=yv[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27849 Q=yv[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27847 Q=yv[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27845 Q=yv[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27843 Q=yv[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27841 Q=yv[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27839 Q=yv[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27837 Q=yv[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27835 Q=yv[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28157 Q=yv[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27833 Q=ph[16][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27831 Q=ph[16][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27829 Q=ph[16][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27827 Q=ph[16][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27825 Q=ph[16][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27823 Q=ph[16][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27821 Q=ph[16][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27819 Q=ph[16][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27817 Q=ph[16][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27815 Q=ph[16][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27813 Q=ph[16][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27811 Q=ph[16][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27809 Q=ph[16][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27807 Q=ph[16][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27805 Q=ph[16][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27803 Q=ph[16][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27801 Q=ph[16][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27799 Q=ph[16][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27797 Q=ph[16][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27795 Q=ph[16][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28159 Q=ph[16][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27793 Q=xv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27791 Q=xv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27789 Q=xv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27787 Q=xv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27785 Q=xv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27783 Q=xv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27781 Q=xv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27779 Q=xv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27777 Q=xv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27775 Q=xv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27773 Q=xv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27771 Q=xv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27769 Q=xv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27767 Q=xv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27765 Q=xv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27763 Q=xv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27761 Q=xv[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27759 Q=xv[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27757 Q=xv[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27755 Q=xv[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28161 Q=xv[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27753 Q=yv[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27751 Q=yv[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27749 Q=yv[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27747 Q=yv[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27745 Q=yv[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27743 Q=yv[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27741 Q=yv[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27739 Q=yv[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27737 Q=yv[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27735 Q=yv[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27733 Q=yv[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27731 Q=yv[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27729 Q=yv[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27727 Q=yv[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27725 Q=yv[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27723 Q=yv[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27721 Q=yv[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27719 Q=yv[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27717 Q=yv[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27715 Q=yv[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28163 Q=yv[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27713 Q=ph[15][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27711 Q=ph[15][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27709 Q=ph[15][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27707 Q=ph[15][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27705 Q=ph[15][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27703 Q=ph[15][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27701 Q=ph[15][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27699 Q=ph[15][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27697 Q=ph[15][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27695 Q=ph[15][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27693 Q=ph[15][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27691 Q=ph[15][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27689 Q=ph[15][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27687 Q=ph[15][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27685 Q=ph[15][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27683 Q=ph[15][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27681 Q=ph[15][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27679 Q=ph[15][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27677 Q=ph[15][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27675 Q=ph[15][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28165 Q=ph[15][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27673 Q=xv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27671 Q=xv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27669 Q=xv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27667 Q=xv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27665 Q=xv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27663 Q=xv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27661 Q=xv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27659 Q=xv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27657 Q=xv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27655 Q=xv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27653 Q=xv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27651 Q=xv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27649 Q=xv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27647 Q=xv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27645 Q=xv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27643 Q=xv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27641 Q=xv[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27639 Q=xv[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27637 Q=xv[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27635 Q=xv[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28167 Q=xv[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27633 Q=yv[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27631 Q=yv[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27629 Q=yv[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27627 Q=yv[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27625 Q=yv[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27623 Q=yv[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27621 Q=yv[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27619 Q=yv[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27617 Q=yv[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27615 Q=yv[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27613 Q=yv[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27611 Q=yv[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27609 Q=yv[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27607 Q=yv[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27605 Q=yv[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27603 Q=yv[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27601 Q=yv[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27599 Q=yv[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27597 Q=yv[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27595 Q=yv[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28169 Q=yv[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27593 Q=ph[14][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27591 Q=ph[14][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27589 Q=ph[14][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27587 Q=ph[14][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27585 Q=ph[14][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27583 Q=ph[14][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27581 Q=ph[14][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27579 Q=ph[14][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27577 Q=ph[14][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27575 Q=ph[14][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27573 Q=ph[14][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27571 Q=ph[14][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27569 Q=ph[14][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27567 Q=ph[14][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27565 Q=ph[14][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27563 Q=ph[14][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27561 Q=ph[14][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27559 Q=ph[14][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27557 Q=ph[14][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27555 Q=ph[14][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28171 Q=ph[14][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27553 Q=xv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27551 Q=xv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27549 Q=xv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27547 Q=xv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27545 Q=xv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27543 Q=xv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27541 Q=xv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27539 Q=xv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27537 Q=xv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27535 Q=xv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27533 Q=xv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27531 Q=xv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27529 Q=xv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27527 Q=xv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27525 Q=xv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27523 Q=xv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27521 Q=xv[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27519 Q=xv[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27517 Q=xv[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27515 Q=xv[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28173 Q=xv[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27513 Q=yv[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27511 Q=yv[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27509 Q=yv[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27507 Q=yv[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27505 Q=yv[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27503 Q=yv[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27501 Q=yv[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27499 Q=yv[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27497 Q=yv[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27495 Q=yv[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27493 Q=yv[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27491 Q=yv[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27489 Q=yv[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27487 Q=yv[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27485 Q=yv[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27483 Q=yv[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27481 Q=yv[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27479 Q=yv[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27477 Q=yv[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27475 Q=yv[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28175 Q=yv[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27473 Q=ph[13][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27471 Q=ph[13][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27469 Q=ph[13][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27467 Q=ph[13][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27465 Q=ph[13][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27463 Q=ph[13][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27461 Q=ph[13][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27459 Q=ph[13][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27457 Q=ph[13][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27455 Q=ph[13][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27453 Q=ph[13][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27451 Q=ph[13][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27449 Q=ph[13][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27447 Q=ph[13][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27445 Q=ph[13][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27443 Q=ph[13][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27441 Q=ph[13][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27439 Q=ph[13][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27437 Q=ph[13][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27435 Q=ph[13][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28177 Q=ph[13][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27433 Q=xv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27431 Q=xv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27429 Q=xv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27427 Q=xv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27425 Q=xv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27423 Q=xv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27421 Q=xv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27419 Q=xv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27417 Q=xv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27415 Q=xv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27413 Q=xv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27411 Q=xv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27409 Q=xv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27407 Q=xv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27405 Q=xv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27403 Q=xv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27401 Q=xv[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27399 Q=xv[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27397 Q=xv[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27395 Q=xv[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28179 Q=xv[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27393 Q=yv[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27391 Q=yv[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27389 Q=yv[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27387 Q=yv[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27385 Q=yv[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27383 Q=yv[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27381 Q=yv[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27379 Q=yv[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27377 Q=yv[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27375 Q=yv[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27373 Q=yv[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27371 Q=yv[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27369 Q=yv[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27367 Q=yv[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27365 Q=yv[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27363 Q=yv[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27361 Q=yv[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27359 Q=yv[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27357 Q=yv[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27355 Q=yv[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28181 Q=yv[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27353 Q=ph[12][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27351 Q=ph[12][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27349 Q=ph[12][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27347 Q=ph[12][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27345 Q=ph[12][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27343 Q=ph[12][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27341 Q=ph[12][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27339 Q=ph[12][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27337 Q=ph[12][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27335 Q=ph[12][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27333 Q=ph[12][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27331 Q=ph[12][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27329 Q=ph[12][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27327 Q=ph[12][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27325 Q=ph[12][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27323 Q=ph[12][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27321 Q=ph[12][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27319 Q=ph[12][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27317 Q=ph[12][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27315 Q=ph[12][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28183 Q=ph[12][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27313 Q=xv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27311 Q=xv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27309 Q=xv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27307 Q=xv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27305 Q=xv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27303 Q=xv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27301 Q=xv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27299 Q=xv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27297 Q=xv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27295 Q=xv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27293 Q=xv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27291 Q=xv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27289 Q=xv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27287 Q=xv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27285 Q=xv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27283 Q=xv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27281 Q=xv[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27279 Q=xv[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27277 Q=xv[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27275 Q=xv[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28185 Q=xv[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27273 Q=yv[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27271 Q=yv[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27269 Q=yv[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27267 Q=yv[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27265 Q=yv[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27263 Q=yv[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27261 Q=yv[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27259 Q=yv[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27257 Q=yv[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27255 Q=yv[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27253 Q=yv[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27251 Q=yv[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27249 Q=yv[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27247 Q=yv[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27245 Q=yv[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27243 Q=yv[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27241 Q=yv[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27239 Q=yv[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27237 Q=yv[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27235 Q=yv[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28187 Q=yv[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27233 Q=ph[11][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27231 Q=ph[11][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27229 Q=ph[11][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27227 Q=ph[11][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27225 Q=ph[11][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27223 Q=ph[11][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27221 Q=ph[11][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27219 Q=ph[11][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27217 Q=ph[11][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27215 Q=ph[11][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27213 Q=ph[11][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27211 Q=ph[11][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27209 Q=ph[11][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27207 Q=ph[11][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27205 Q=ph[11][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27203 Q=ph[11][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27201 Q=ph[11][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27199 Q=ph[11][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27197 Q=ph[11][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27195 Q=ph[11][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28189 Q=ph[11][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27193 Q=xv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27191 Q=xv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27189 Q=xv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27187 Q=xv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27185 Q=xv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27183 Q=xv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27181 Q=xv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27179 Q=xv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27177 Q=xv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27175 Q=xv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27173 Q=xv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27171 Q=xv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27169 Q=xv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27167 Q=xv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27165 Q=xv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27163 Q=xv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27161 Q=xv[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27159 Q=xv[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27157 Q=xv[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27155 Q=xv[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28191 Q=xv[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27153 Q=yv[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27151 Q=yv[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27149 Q=yv[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27147 Q=yv[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27145 Q=yv[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27143 Q=yv[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27141 Q=yv[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27139 Q=yv[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27137 Q=yv[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27135 Q=yv[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27133 Q=yv[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27131 Q=yv[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27129 Q=yv[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27127 Q=yv[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27125 Q=yv[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27123 Q=yv[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27121 Q=yv[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27119 Q=yv[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27117 Q=yv[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27115 Q=yv[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28193 Q=yv[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27113 Q=ph[10][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27111 Q=ph[10][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27109 Q=ph[10][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27107 Q=ph[10][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27105 Q=ph[10][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27103 Q=ph[10][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27101 Q=ph[10][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27099 Q=ph[10][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27097 Q=ph[10][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27095 Q=ph[10][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27093 Q=ph[10][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27091 Q=ph[10][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27089 Q=ph[10][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27087 Q=ph[10][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27085 Q=ph[10][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27083 Q=ph[10][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27081 Q=ph[10][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27079 Q=ph[10][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27077 Q=ph[10][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27075 Q=ph[10][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28195 Q=ph[10][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27073 Q=xv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27071 Q=xv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27069 Q=xv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27067 Q=xv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27065 Q=xv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27063 Q=xv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27061 Q=xv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27059 Q=xv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27057 Q=xv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27055 Q=xv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27053 Q=xv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27051 Q=xv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27049 Q=xv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27047 Q=xv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27045 Q=xv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27043 Q=xv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27041 Q=xv[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27039 Q=xv[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27037 Q=xv[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27035 Q=xv[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28197 Q=xv[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27033 Q=yv[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27031 Q=yv[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27029 Q=yv[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27027 Q=yv[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27025 Q=yv[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27023 Q=yv[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27021 Q=yv[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27019 Q=yv[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27017 Q=yv[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27015 Q=yv[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27013 Q=yv[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27011 Q=yv[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27009 Q=yv[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27007 Q=yv[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27005 Q=yv[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27003 Q=yv[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$27001 Q=yv[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26999 Q=yv[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26997 Q=yv[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26995 Q=yv[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28199 Q=yv[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26993 Q=ph[9][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26991 Q=ph[9][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26989 Q=ph[9][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26987 Q=ph[9][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26985 Q=ph[9][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26983 Q=ph[9][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26981 Q=ph[9][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26979 Q=ph[9][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26977 Q=ph[9][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26975 Q=ph[9][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26973 Q=ph[9][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26971 Q=ph[9][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26969 Q=ph[9][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26967 Q=ph[9][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26965 Q=ph[9][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26963 Q=ph[9][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26961 Q=ph[9][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26959 Q=ph[9][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26957 Q=ph[9][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26955 Q=ph[9][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28201 Q=ph[9][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26953 Q=xv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26951 Q=xv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26949 Q=xv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26947 Q=xv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26945 Q=xv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26943 Q=xv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26941 Q=xv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26939 Q=xv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26937 Q=xv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26935 Q=xv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26933 Q=xv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26931 Q=xv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26929 Q=xv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26927 Q=xv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26925 Q=xv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26923 Q=xv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26921 Q=xv[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26919 Q=xv[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26917 Q=xv[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26915 Q=xv[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28203 Q=xv[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26913 Q=yv[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26911 Q=yv[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26909 Q=yv[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26907 Q=yv[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26905 Q=yv[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26903 Q=yv[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26901 Q=yv[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26899 Q=yv[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26897 Q=yv[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26895 Q=yv[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26893 Q=yv[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26891 Q=yv[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26889 Q=yv[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26887 Q=yv[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26885 Q=yv[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26883 Q=yv[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26881 Q=yv[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26879 Q=yv[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26877 Q=yv[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26875 Q=yv[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28205 Q=yv[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26873 Q=ph[8][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26871 Q=ph[8][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26869 Q=ph[8][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26867 Q=ph[8][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26865 Q=ph[8][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26863 Q=ph[8][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26861 Q=ph[8][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26859 Q=ph[8][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26857 Q=ph[8][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26855 Q=ph[8][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26853 Q=ph[8][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26851 Q=ph[8][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26849 Q=ph[8][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26847 Q=ph[8][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26845 Q=ph[8][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26843 Q=ph[8][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26841 Q=ph[8][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26839 Q=ph[8][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26837 Q=ph[8][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26835 Q=ph[8][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28207 Q=ph[8][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26833 Q=xv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26831 Q=xv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26829 Q=xv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26827 Q=xv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26825 Q=xv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26823 Q=xv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26821 Q=xv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26819 Q=xv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26817 Q=xv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26815 Q=xv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26813 Q=xv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26811 Q=xv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26809 Q=xv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26807 Q=xv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26805 Q=xv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26803 Q=xv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26801 Q=xv[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26799 Q=xv[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26797 Q=xv[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26795 Q=xv[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28209 Q=xv[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26793 Q=yv[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26791 Q=yv[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26789 Q=yv[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26787 Q=yv[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26785 Q=yv[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26783 Q=yv[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26781 Q=yv[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26779 Q=yv[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26777 Q=yv[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26775 Q=yv[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26773 Q=yv[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26771 Q=yv[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26769 Q=yv[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26767 Q=yv[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26765 Q=yv[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26763 Q=yv[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26761 Q=yv[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26759 Q=yv[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26757 Q=yv[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26755 Q=yv[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28211 Q=yv[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26753 Q=ph[7][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26751 Q=ph[7][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26749 Q=ph[7][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26747 Q=ph[7][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26745 Q=ph[7][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26743 Q=ph[7][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26741 Q=ph[7][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26739 Q=ph[7][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26737 Q=ph[7][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26735 Q=ph[7][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26733 Q=ph[7][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26731 Q=ph[7][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26729 Q=ph[7][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26727 Q=ph[7][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26725 Q=ph[7][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26723 Q=ph[7][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26721 Q=ph[7][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26719 Q=ph[7][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26717 Q=ph[7][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26715 Q=ph[7][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28213 Q=ph[7][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26713 Q=xv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26711 Q=xv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26709 Q=xv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26707 Q=xv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26705 Q=xv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26703 Q=xv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26701 Q=xv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26699 Q=xv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26697 Q=xv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26695 Q=xv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26693 Q=xv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26691 Q=xv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26689 Q=xv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26687 Q=xv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26685 Q=xv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26683 Q=xv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26681 Q=xv[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26679 Q=xv[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26677 Q=xv[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26675 Q=xv[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28215 Q=xv[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26673 Q=yv[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26671 Q=yv[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26669 Q=yv[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26667 Q=yv[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26665 Q=yv[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26663 Q=yv[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26661 Q=yv[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26659 Q=yv[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26657 Q=yv[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26655 Q=yv[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26653 Q=yv[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26651 Q=yv[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26649 Q=yv[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26647 Q=yv[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26645 Q=yv[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26643 Q=yv[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26641 Q=yv[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26639 Q=yv[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26637 Q=yv[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26635 Q=yv[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28217 Q=yv[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26633 Q=ph[6][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26631 Q=ph[6][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26629 Q=ph[6][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26627 Q=ph[6][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26625 Q=ph[6][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26623 Q=ph[6][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26621 Q=ph[6][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26619 Q=ph[6][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26617 Q=ph[6][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26615 Q=ph[6][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26613 Q=ph[6][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26611 Q=ph[6][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26609 Q=ph[6][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26607 Q=ph[6][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26605 Q=ph[6][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26603 Q=ph[6][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26601 Q=ph[6][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26599 Q=ph[6][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26597 Q=ph[6][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26595 Q=ph[6][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28219 Q=ph[6][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26593 Q=xv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26591 Q=xv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26589 Q=xv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26587 Q=xv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26585 Q=xv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26583 Q=xv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26581 Q=xv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26579 Q=xv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26577 Q=xv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26575 Q=xv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26573 Q=xv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26571 Q=xv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26569 Q=xv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26567 Q=xv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26565 Q=xv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26563 Q=xv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26561 Q=xv[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26559 Q=xv[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26557 Q=xv[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26555 Q=xv[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28221 Q=xv[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26553 Q=yv[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26551 Q=yv[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26549 Q=yv[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26547 Q=yv[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26545 Q=yv[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26543 Q=yv[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26541 Q=yv[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26539 Q=yv[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26537 Q=yv[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26535 Q=yv[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26533 Q=yv[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26531 Q=yv[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26529 Q=yv[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26527 Q=yv[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26525 Q=yv[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26523 Q=yv[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26521 Q=yv[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26519 Q=yv[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26517 Q=yv[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26515 Q=yv[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28223 Q=yv[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26513 Q=ph[5][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26511 Q=ph[5][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26509 Q=ph[5][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26507 Q=ph[5][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26505 Q=ph[5][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26503 Q=ph[5][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26501 Q=ph[5][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26499 Q=ph[5][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26497 Q=ph[5][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26495 Q=ph[5][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26493 Q=ph[5][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26491 Q=ph[5][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26489 Q=ph[5][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26487 Q=ph[5][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26485 Q=ph[5][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26483 Q=ph[5][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26481 Q=ph[5][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26479 Q=ph[5][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26477 Q=ph[5][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26475 Q=ph[5][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28225 Q=ph[5][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26473 Q=xv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26471 Q=xv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26469 Q=xv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26467 Q=xv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26465 Q=xv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26463 Q=xv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26461 Q=xv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26459 Q=xv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26457 Q=xv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26455 Q=xv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26453 Q=xv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26451 Q=xv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26449 Q=xv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26447 Q=xv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26445 Q=xv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26443 Q=xv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26441 Q=xv[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26439 Q=xv[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26437 Q=xv[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26435 Q=xv[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28227 Q=xv[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26433 Q=yv[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26431 Q=yv[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26429 Q=yv[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26427 Q=yv[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26425 Q=yv[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26423 Q=yv[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26421 Q=yv[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26419 Q=yv[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26417 Q=yv[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26415 Q=yv[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26413 Q=yv[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26411 Q=yv[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26409 Q=yv[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26407 Q=yv[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26405 Q=yv[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26403 Q=yv[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26401 Q=yv[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26399 Q=yv[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26397 Q=yv[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26395 Q=yv[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28229 Q=yv[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26393 Q=ph[4][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26391 Q=ph[4][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26389 Q=ph[4][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26387 Q=ph[4][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26385 Q=ph[4][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26383 Q=ph[4][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26381 Q=ph[4][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26379 Q=ph[4][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26377 Q=ph[4][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26375 Q=ph[4][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26373 Q=ph[4][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26371 Q=ph[4][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26369 Q=ph[4][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26367 Q=ph[4][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26365 Q=ph[4][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26363 Q=ph[4][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26361 Q=ph[4][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26359 Q=ph[4][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26357 Q=ph[4][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26355 Q=ph[4][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28231 Q=ph[4][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26353 Q=xv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26351 Q=xv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26349 Q=xv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26347 Q=xv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26345 Q=xv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26343 Q=xv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26341 Q=xv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26339 Q=xv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26337 Q=xv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26335 Q=xv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26333 Q=xv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26331 Q=xv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26329 Q=xv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26327 Q=xv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26325 Q=xv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26323 Q=xv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26321 Q=xv[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26319 Q=xv[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26317 Q=xv[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26315 Q=xv[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28233 Q=xv[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26313 Q=yv[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26311 Q=yv[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26309 Q=yv[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26307 Q=yv[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26305 Q=yv[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26303 Q=yv[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26301 Q=yv[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26299 Q=yv[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26297 Q=yv[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26295 Q=yv[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26293 Q=yv[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26291 Q=yv[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26289 Q=yv[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26287 Q=yv[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26285 Q=yv[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26283 Q=yv[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26281 Q=yv[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26279 Q=yv[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26277 Q=yv[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26275 Q=yv[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28235 Q=yv[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26273 Q=ph[3][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26271 Q=ph[3][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26269 Q=ph[3][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26267 Q=ph[3][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26265 Q=ph[3][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26263 Q=ph[3][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26261 Q=ph[3][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26259 Q=ph[3][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26257 Q=ph[3][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26255 Q=ph[3][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26253 Q=ph[3][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26251 Q=ph[3][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26249 Q=ph[3][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26247 Q=ph[3][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26245 Q=ph[3][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26243 Q=ph[3][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26241 Q=ph[3][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26239 Q=ph[3][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26237 Q=ph[3][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26235 Q=ph[3][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28237 Q=ph[3][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26233 Q=xv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26231 Q=xv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26229 Q=xv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26227 Q=xv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26225 Q=xv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26223 Q=xv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26221 Q=xv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26219 Q=xv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26217 Q=xv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26215 Q=xv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26213 Q=xv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26211 Q=xv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26209 Q=xv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26207 Q=xv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26205 Q=xv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26203 Q=xv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26201 Q=xv[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26199 Q=xv[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26197 Q=xv[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26195 Q=xv[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28239 Q=xv[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26193 Q=yv[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26191 Q=yv[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26189 Q=yv[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26187 Q=yv[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26185 Q=yv[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26183 Q=yv[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26181 Q=yv[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26179 Q=yv[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26177 Q=yv[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26175 Q=yv[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26173 Q=yv[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26171 Q=yv[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26169 Q=yv[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26167 Q=yv[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26165 Q=yv[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26163 Q=yv[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26161 Q=yv[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26159 Q=yv[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26157 Q=yv[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26155 Q=yv[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28241 Q=yv[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26153 Q=ph[2][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26151 Q=ph[2][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26149 Q=ph[2][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26147 Q=ph[2][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26145 Q=ph[2][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26143 Q=ph[2][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26141 Q=ph[2][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26139 Q=ph[2][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26137 Q=ph[2][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26135 Q=ph[2][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26133 Q=ph[2][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26131 Q=ph[2][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26129 Q=ph[2][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26127 Q=ph[2][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26125 Q=ph[2][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26123 Q=ph[2][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26121 Q=ph[2][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26119 Q=ph[2][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26117 Q=ph[2][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26115 Q=ph[2][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28243 Q=ph[2][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26113 Q=xv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26111 Q=xv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26109 Q=xv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26107 Q=xv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26105 Q=xv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26103 Q=xv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26101 Q=xv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26099 Q=xv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26097 Q=xv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26095 Q=xv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26093 Q=xv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26091 Q=xv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26089 Q=xv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26087 Q=xv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26085 Q=xv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26083 Q=xv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26081 Q=xv[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26079 Q=xv[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26077 Q=xv[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26075 Q=xv[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28245 Q=xv[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26073 Q=yv[1][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26071 Q=yv[1][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26069 Q=yv[1][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26067 Q=yv[1][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26065 Q=yv[1][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26063 Q=yv[1][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26061 Q=yv[1][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26059 Q=yv[1][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26057 Q=yv[1][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26055 Q=yv[1][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26053 Q=yv[1][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26051 Q=yv[1][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26049 Q=yv[1][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26047 Q=yv[1][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26045 Q=yv[1][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26043 Q=yv[1][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26041 Q=yv[1][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26039 Q=yv[1][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26037 Q=yv[1][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26035 Q=yv[1][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28247 Q=yv[1][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26033 Q=o_mag[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26031 Q=o_mag[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26029 Q=o_mag[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26027 Q=o_mag[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26025 Q=o_mag[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26023 Q=o_mag[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26021 Q=o_mag[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26019 Q=o_mag[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26017 Q=o_mag[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26015 Q=o_mag[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26013 Q=o_mag[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26011 Q=o_mag[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28249 Q=o_mag[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26009 Q=o_phase[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26007 Q=o_phase[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26005 Q=o_phase[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26003 Q=o_phase[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$26001 Q=o_phase[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25999 Q=o_phase[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25997 Q=o_phase[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25995 Q=o_phase[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25993 Q=o_phase[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25991 Q=o_phase[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25989 Q=o_phase[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25987 Q=o_phase[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25985 Q=o_phase[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25983 Q=o_phase[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25981 Q=o_phase[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25979 Q=o_phase[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25977 Q=o_phase[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25975 Q=o_phase[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25973 Q=o_phase[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25971 Q=o_phase[19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28251 Q=o_phase[20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28253 Q=o_aux R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25969 Q=xv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25967 Q=xv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25965 Q=xv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25963 Q=xv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25961 Q=xv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25959 Q=xv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25957 Q=xv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25955 Q=xv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25953 Q=xv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25951 Q=xv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25949 Q=xv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25947 Q=xv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25945 Q=xv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25943 Q=xv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25941 Q=xv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25939 Q=xv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25937 Q=xv[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25935 Q=xv[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25933 Q=xv[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25931 Q=xv[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28255 Q=xv[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25929 Q=yv[0][0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25927 Q=yv[0][1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25925 Q=yv[0][2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25923 Q=yv[0][3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25921 Q=yv[0][4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25919 Q=yv[0][5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25917 Q=yv[0][6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25915 Q=yv[0][7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25913 Q=yv[0][8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25911 Q=yv[0][9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25909 Q=yv[0][10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25907 Q=yv[0][11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25905 Q=yv[0][12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25903 Q=yv[0][13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25901 Q=yv[0][14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25899 Q=yv[0][15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25897 Q=yv[0][16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25895 Q=yv[0][17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25893 Q=yv[0][18] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25891 Q=yv[0][19] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28257 Q=yv[0][20] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25889 Q=ax[0] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25887 Q=ax[1] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25885 Q=ax[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25883 Q=ax[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25881 Q=ax[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25879 Q=ax[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25877 Q=ax[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25875 Q=ax[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25873 Q=ax[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25871 Q=ax[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25869 Q=ax[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25867 Q=ax[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25865 Q=ax[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25863 Q=ax[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25861 Q=ax[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25859 Q=ax[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25857 Q=ax[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$25855 Q=ax[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$30358$auto$rtlil.cc:2693:MuxGate$28259 Q=ax[18] R=i_reset +.names $false ph[0][0] +1 1 +.names $false ph[0][1] +1 1 +.names $false ph[0][2] +1 1 +.names $false ph[0][3] +1 1 +.names $false ph[0][4] +1 1 +.names $false ph[0][5] +1 1 +.names $false ph[0][6] +1 1 +.names $false ph[0][7] +1 1 +.names $false ph[0][8] +1 1 +.names $false ph[0][9] +1 1 +.names $false ph[0][10] +1 1 +.names $false ph[0][11] +1 1 +.names $false ph[0][12] +1 1 +.names $false ph[0][13] +1 1 +.names $false ph[0][14] +1 1 +.names $false ph[0][15] +1 1 +.names $false ph[0][16] +1 1 +.names $false ph[0][17] +1 1 +.names $false ph[1][0] +1 1 +.names $false ph[1][1] +1 1 +.names $false ph[1][2] +1 1 +.names $false ph[1][3] +1 1 +.names $false ph[1][4] +1 1 +.names $false ph[1][5] +1 1 +.names $false ph[1][6] +1 1 +.end diff --git a/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif new file mode 100644 index 00000000000..ad4923c7d2e --- /dev/null +++ b/vtr_flow/benchmarks/VIB/VIB_test_benchmarks/zipcore.blif @@ -0,0 +1,54152 @@ +# Generated by Yosys 0.38+46 (git sha1 UNKNOWN, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) + +.model zipcore +.inputs i_clk i_reset i_interrupt i_halt i_clear_cache i_dbg_wreg[0] i_dbg_wreg[1] i_dbg_wreg[2] i_dbg_wreg[3] i_dbg_wreg[4] i_dbg_we i_dbg_data[0] i_dbg_data[1] i_dbg_data[2] i_dbg_data[3] i_dbg_data[4] i_dbg_data[5] i_dbg_data[6] i_dbg_data[7] i_dbg_data[8] i_dbg_data[9] i_dbg_data[10] i_dbg_data[11] i_dbg_data[12] i_dbg_data[13] i_dbg_data[14] i_dbg_data[15] i_dbg_data[16] i_dbg_data[17] i_dbg_data[18] i_dbg_data[19] i_dbg_data[20] i_dbg_data[21] i_dbg_data[22] i_dbg_data[23] i_dbg_data[24] i_dbg_data[25] i_dbg_data[26] i_dbg_data[27] i_dbg_data[28] i_dbg_data[29] i_dbg_data[30] i_dbg_data[31] i_dbg_rreg[0] i_dbg_rreg[1] i_dbg_rreg[2] i_dbg_rreg[3] i_dbg_rreg[4] i_pf_valid i_pf_illegal i_pf_instruction[0] i_pf_instruction[1] i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] i_pf_instruction[10] i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[13] i_pf_instruction[14] i_pf_instruction[15] i_pf_instruction[16] i_pf_instruction[17] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[20] i_pf_instruction[21] i_pf_instruction[22] i_pf_instruction[23] i_pf_instruction[24] i_pf_instruction[25] i_pf_instruction[26] i_pf_instruction[27] i_pf_instruction[28] i_pf_instruction[29] i_pf_instruction[30] i_pf_instruction[31] i_pf_instruction_pc[0] i_pf_instruction_pc[1] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction_pc[4] i_pf_instruction_pc[5] i_pf_instruction_pc[6] i_pf_instruction_pc[7] i_pf_instruction_pc[8] i_pf_instruction_pc[9] i_pf_instruction_pc[10] i_pf_instruction_pc[11] i_pf_instruction_pc[12] i_pf_instruction_pc[13] i_pf_instruction_pc[14] i_pf_instruction_pc[15] i_pf_instruction_pc[16] i_pf_instruction_pc[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction_pc[20] i_pf_instruction_pc[21] i_pf_instruction_pc[22] i_pf_instruction_pc[23] i_pf_instruction_pc[24] i_pf_instruction_pc[25] i_pf_instruction_pc[26] i_pf_instruction_pc[27] i_pf_instruction_pc[28] i_pf_instruction_pc[29] i_pf_instruction_pc[30] i_pf_instruction_pc[31] i_mem_busy i_mem_rdbusy i_mem_pipe_stalled i_mem_valid i_bus_err i_mem_wreg[0] i_mem_wreg[1] i_mem_wreg[2] i_mem_wreg[3] i_mem_wreg[4] i_mem_result[0] i_mem_result[1] i_mem_result[2] i_mem_result[3] i_mem_result[4] i_mem_result[5] i_mem_result[6] i_mem_result[7] i_mem_result[8] i_mem_result[9] i_mem_result[10] i_mem_result[11] i_mem_result[12] i_mem_result[13] i_mem_result[14] i_mem_result[15] i_mem_result[16] i_mem_result[17] i_mem_result[18] i_mem_result[19] i_mem_result[20] i_mem_result[21] i_mem_result[22] i_mem_result[23] i_mem_result[24] i_mem_result[25] i_mem_result[26] i_mem_result[27] i_mem_result[28] i_mem_result[29] i_mem_result[30] i_mem_result[31] +.outputs o_clken o_dbg_stall o_dbg_reg[0] o_dbg_reg[1] o_dbg_reg[2] o_dbg_reg[3] o_dbg_reg[4] o_dbg_reg[5] o_dbg_reg[6] o_dbg_reg[7] o_dbg_reg[8] o_dbg_reg[9] o_dbg_reg[10] o_dbg_reg[11] o_dbg_reg[12] o_dbg_reg[13] o_dbg_reg[14] o_dbg_reg[15] o_dbg_reg[16] o_dbg_reg[17] o_dbg_reg[18] o_dbg_reg[19] o_dbg_reg[20] o_dbg_reg[21] o_dbg_reg[22] o_dbg_reg[23] o_dbg_reg[24] o_dbg_reg[25] o_dbg_reg[26] o_dbg_reg[27] o_dbg_reg[28] o_dbg_reg[29] o_dbg_reg[30] o_dbg_reg[31] o_dbg_cc[0] o_dbg_cc[1] o_dbg_cc[2] o_break o_pf_new_pc o_clear_icache o_pf_ready o_pf_request_address[0] o_pf_request_address[1] o_pf_request_address[2] o_pf_request_address[3] o_pf_request_address[4] o_pf_request_address[5] o_pf_request_address[6] o_pf_request_address[7] o_pf_request_address[8] o_pf_request_address[9] o_pf_request_address[10] o_pf_request_address[11] o_pf_request_address[12] o_pf_request_address[13] o_pf_request_address[14] o_pf_request_address[15] o_pf_request_address[16] o_pf_request_address[17] o_pf_request_address[18] o_pf_request_address[19] o_pf_request_address[20] o_pf_request_address[21] o_pf_request_address[22] o_pf_request_address[23] o_pf_request_address[24] o_pf_request_address[25] o_pf_request_address[26] o_pf_request_address[27] o_pf_request_address[28] o_pf_request_address[29] o_pf_request_address[30] o_pf_request_address[31] o_clear_dcache o_mem_ce o_bus_lock o_mem_op[0] o_mem_op[1] o_mem_op[2] o_mem_addr[0] o_mem_addr[1] o_mem_addr[2] o_mem_addr[3] o_mem_addr[4] o_mem_addr[5] o_mem_addr[6] o_mem_addr[7] o_mem_addr[8] o_mem_addr[9] o_mem_addr[10] o_mem_addr[11] o_mem_addr[12] o_mem_addr[13] o_mem_addr[14] o_mem_addr[15] o_mem_addr[16] o_mem_addr[17] o_mem_addr[18] o_mem_addr[19] o_mem_addr[20] o_mem_addr[21] o_mem_addr[22] o_mem_addr[23] o_mem_addr[24] o_mem_addr[25] o_mem_addr[26] o_mem_addr[27] o_mem_addr[28] o_mem_addr[29] o_mem_addr[30] o_mem_addr[31] o_mem_data[0] o_mem_data[1] o_mem_data[2] o_mem_data[3] o_mem_data[4] o_mem_data[5] o_mem_data[6] o_mem_data[7] o_mem_data[8] o_mem_data[9] o_mem_data[10] o_mem_data[11] o_mem_data[12] o_mem_data[13] o_mem_data[14] o_mem_data[15] o_mem_data[16] o_mem_data[17] o_mem_data[18] o_mem_data[19] o_mem_data[20] o_mem_data[21] o_mem_data[22] o_mem_data[23] o_mem_data[24] o_mem_data[25] o_mem_data[26] o_mem_data[27] o_mem_data[28] o_mem_data[29] o_mem_data[30] o_mem_data[31] o_mem_lock_pc[0] o_mem_lock_pc[1] o_mem_lock_pc[2] o_mem_lock_pc[3] o_mem_lock_pc[4] o_mem_lock_pc[5] o_mem_lock_pc[6] o_mem_lock_pc[7] o_mem_lock_pc[8] o_mem_lock_pc[9] o_mem_lock_pc[10] o_mem_lock_pc[11] o_mem_lock_pc[12] o_mem_lock_pc[13] o_mem_lock_pc[14] o_mem_lock_pc[15] o_mem_lock_pc[16] o_mem_lock_pc[17] o_mem_lock_pc[18] o_mem_lock_pc[19] o_mem_lock_pc[20] o_mem_lock_pc[21] o_mem_lock_pc[22] o_mem_lock_pc[23] o_mem_lock_pc[24] o_mem_lock_pc[25] o_mem_lock_pc[26] o_mem_lock_pc[27] o_mem_lock_pc[28] o_mem_lock_pc[29] o_mem_lock_pc[30] o_mem_lock_pc[31] o_mem_reg[0] o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] o_mem_reg[4] o_op_stall o_pf_stall o_i_count o_debug[0] o_debug[1] o_debug[2] o_debug[3] o_debug[4] o_debug[5] o_debug[6] o_debug[7] o_debug[8] o_debug[9] o_debug[10] o_debug[11] o_debug[12] o_debug[13] o_debug[14] o_debug[15] o_debug[16] o_debug[17] o_debug[18] o_debug[19] o_debug[20] o_debug[21] o_debug[22] o_debug[23] o_debug[24] o_debug[25] o_debug[26] o_debug[27] o_debug[28] o_debug[29] o_debug[30] o_debug[31] o_prof_stb o_prof_addr[0] o_prof_addr[1] o_prof_addr[2] o_prof_addr[3] o_prof_addr[4] o_prof_addr[5] o_prof_addr[6] o_prof_addr[7] o_prof_addr[8] o_prof_addr[9] o_prof_addr[10] o_prof_addr[11] o_prof_addr[12] o_prof_addr[13] o_prof_addr[14] o_prof_addr[15] o_prof_addr[16] o_prof_addr[17] o_prof_addr[18] o_prof_addr[19] o_prof_addr[20] o_prof_addr[21] o_prof_addr[22] o_prof_addr[23] o_prof_addr[24] o_prof_addr[25] o_prof_addr[26] o_prof_addr[27] o_prof_addr[28] o_prof_addr[29] o_prof_addr[30] o_prof_addr[31] o_prof_ticks[0] o_prof_ticks[1] o_prof_ticks[2] o_prof_ticks[3] o_prof_ticks[4] o_prof_ticks[5] o_prof_ticks[6] o_prof_ticks[7] o_prof_ticks[8] o_prof_ticks[9] o_prof_ticks[10] o_prof_ticks[11] o_prof_ticks[12] o_prof_ticks[13] o_prof_ticks[14] o_prof_ticks[15] o_prof_ticks[16] o_prof_ticks[17] o_prof_ticks[18] o_prof_ticks[19] o_prof_ticks[20] o_prof_ticks[21] o_prof_ticks[22] o_prof_ticks[23] o_prof_ticks[24] o_prof_ticks[25] o_prof_ticks[26] o_prof_ticks[27] o_prof_ticks[28] o_prof_ticks[29] o_prof_ticks[30] o_prof_ticks[31] +.names $false +.names $true +1 +.names $undef +.names $abc$24881$new_n3673 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3672 +100 1 +.names $abc$24881$new_n3674 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3673 +100 1 +.names $abc$24881$new_n3675 DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3674 +10 1 +.names $abc$24881$new_n3676 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3675 +1000 1 +.names $abc$24881$new_n3677 DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3676 +10 1 +.names $abc$24881$new_n3678 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3677 +1000 1 +.names $abc$24881$new_n3679 DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3678 +10 1 +.names $abc$24881$new_n3680 DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3679 +10 1 +.names $abc$24881$new_n3681 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3680 +100 1 +.names $abc$24881$new_n3682 DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3681 +10 1 +.names $abc$24881$new_n3683 DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3682 +10 1 +.names $abc$24881$new_n3684 DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3683 +10 1 +.names $abc$24881$new_n3685 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3684 +10 1 +.names $abc$24881$new_n3686 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3685 +10 1 +.names $abc$24881$new_n3687 DIVIDE.thedivide.r_dividend[6] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3686 +100 1 +.names $abc$24881$new_n3688 DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3687 +1000 1 +.names $abc$24881$new_n3689 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3688 +10 1 +.names DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_dividend[1] $abc$24881$new_n3689 +00 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3702 r_op_Av[30] o_mem_data[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3692 +111 1 +.names o_mem_reg[4] o_mem_reg[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3693 +0011 1 +0101 1 +1010 1 +1100 1 +.names i_mem_valid alu_reg[4] i_mem_wreg[4] $abc$24881$new_n3694 +000 1 +001 1 +100 1 +110 1 +.names i_mem_valid alu_reg[3] i_mem_wreg[3] $abc$24881$new_n3695 +000 1 +001 1 +100 1 +110 1 +.names o_mem_reg[0] o_mem_reg[1] $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3696 +0011 1 +0101 1 +1010 1 +1100 1 +.names i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n3697 +000 1 +001 1 +100 1 +110 1 +.names i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n3698 +000 1 +001 1 +100 1 +110 1 +.names o_mem_reg[2] $abc$24881$new_n3701 i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3699 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names new_pc DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err doalu.o_valid alu_wR $abc$24881$new_n3700 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +.names i_mem_valid alu_reg[2] i_mem_wreg[2] $abc$24881$new_n3701 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n3703 i_mem_result[30] wr_index[0] wr_index[1] $abc$24881$new_n3702 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[30] alu_result[30] dbg_val[30] $abc$24881$new_n3703 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3704 +10 1 +.names DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3704 DIVIDE.thedivide.pre_sign $abc$24881$new_n3672 $abc$24881$new_n3706 $abc$24881$auto$rtlil.cc:2693:MuxGate$22568 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[29] DIVIDE.thedivide.r_dividend[28] $abc$24881$new_n3706 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3708 r_op_Av[29] o_mem_data[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3709 i_mem_result[29] wr_index[0] wr_index[1] $abc$24881$new_n3708 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[29] alu_result[29] dbg_val[29] $abc$24881$new_n3709 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3714 r_op_Av[28] o_mem_data[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3715 i_mem_result[28] wr_index[0] wr_index[1] $abc$24881$new_n3714 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[28] alu_result[28] dbg_val[28] $abc$24881$new_n3715 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3717 DIVIDE.thedivide.r_dividend[27] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3673 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22572 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[27] DIVIDE.thedivide.r_dividend[26] $abc$24881$new_n3717 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3719 r_op_Av[27] o_mem_data[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3720 i_mem_result[27] wr_index[0] wr_index[1] $abc$24881$new_n3719 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[27] alu_result[27] dbg_val[27] $abc$24881$new_n3720 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3725 r_op_Av[26] o_mem_data[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3726 i_mem_result[26] wr_index[0] wr_index[1] $abc$24881$new_n3725 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[26] alu_result[26] dbg_val[26] $abc$24881$new_n3726 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3728 DIVIDE.thedivide.r_dividend[25] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3674 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22576 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[25] DIVIDE.thedivide.r_dividend[24] $abc$24881$new_n3728 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3730 r_op_Av[25] o_mem_data[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3731 i_mem_result[25] wr_index[0] wr_index[1] $abc$24881$new_n3730 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[25] alu_result[25] dbg_val[25] $abc$24881$new_n3731 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3733 DIVIDE.thedivide.r_dividend[24] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3675 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22578 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[24] DIVIDE.thedivide.r_dividend[23] $abc$24881$new_n3733 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3735 r_op_Av[24] o_mem_data[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3736 i_mem_result[24] wr_index[0] wr_index[1] $abc$24881$new_n3735 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[24] alu_result[24] dbg_val[24] $abc$24881$new_n3736 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3741 r_op_Av[23] o_mem_data[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3742 i_mem_result[23] wr_index[0] wr_index[1] $abc$24881$new_n3741 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[23] alu_result[23] dbg_val[23] $abc$24881$new_n3742 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3747 r_op_Av[22] o_mem_data[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3748 i_mem_result[22] wr_index[0] wr_index[1] $abc$24881$new_n3747 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[22] alu_result[22] dbg_val[22] $abc$24881$new_n3748 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3750 DIVIDE.thedivide.r_dividend[21] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3676 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22584 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[21] DIVIDE.thedivide.r_dividend[20] $abc$24881$new_n3750 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3752 r_op_Av[21] o_mem_data[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3753 i_mem_result[21] wr_index[0] wr_index[1] $abc$24881$new_n3752 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[21] alu_result[21] dbg_val[21] $abc$24881$new_n3753 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3755 DIVIDE.thedivide.r_dividend[20] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3677 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22586 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[20] DIVIDE.thedivide.r_dividend[19] $abc$24881$new_n3755 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3757 r_op_Av[20] o_mem_data[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3758 i_mem_result[20] wr_index[0] wr_index[1] $abc$24881$new_n3757 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[20] alu_result[20] dbg_val[20] $abc$24881$new_n3758 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3763 r_op_Av[19] o_mem_data[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3764 i_mem_result[19] wr_index[0] wr_index[1] $abc$24881$new_n3763 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[19] alu_result[19] dbg_val[19] $abc$24881$new_n3764 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3769 r_op_Av[18] o_mem_data[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3770 i_mem_result[18] wr_index[0] wr_index[1] $abc$24881$new_n3769 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[18] alu_result[18] dbg_val[18] $abc$24881$new_n3770 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3772 DIVIDE.thedivide.r_dividend[17] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3678 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22592 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[17] DIVIDE.thedivide.r_dividend[16] $abc$24881$new_n3772 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3774 r_op_Av[17] o_mem_data[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3775 i_mem_result[17] wr_index[0] wr_index[1] $abc$24881$new_n3774 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[17] alu_result[17] dbg_val[17] $abc$24881$new_n3775 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3777 DIVIDE.thedivide.r_dividend[16] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3679 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22594 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[16] DIVIDE.thedivide.r_dividend[15] $abc$24881$new_n3777 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3779 r_op_Av[16] o_mem_data[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3780 i_mem_result[16] wr_index[0] wr_index[1] $abc$24881$new_n3779 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[16] alu_result[16] dbg_val[16] $abc$24881$new_n3780 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3782 DIVIDE.thedivide.r_dividend[15] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3680 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22596 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[15] DIVIDE.thedivide.r_dividend[14] $abc$24881$new_n3782 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3784 r_op_Av[15] o_mem_data[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3785 i_mem_result[15] wr_index[0] wr_index[1] $abc$24881$new_n3784 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[15] alu_result[15] dbg_val[15] $abc$24881$new_n3785 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3790 r_op_Av[14] o_mem_data[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3791 i_mem_result[14] wr_index[0] wr_index[1] $abc$24881$new_n3790 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[14] alu_result[14] dbg_val[14] $abc$24881$new_n3791 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3793 DIVIDE.thedivide.r_dividend[13] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3681 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22600 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[13] DIVIDE.thedivide.r_dividend[12] $abc$24881$new_n3793 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3795 r_op_Av[13] o_mem_data[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3796 i_mem_result[13] wr_index[0] wr_index[1] $abc$24881$new_n3795 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[13] alu_result[13] dbg_val[13] $abc$24881$new_n3796 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3798 DIVIDE.thedivide.r_dividend[12] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3682 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22602 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[12] DIVIDE.thedivide.r_dividend[11] $abc$24881$new_n3798 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3800 r_op_Av[12] o_mem_data[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3801 i_mem_result[12] wr_index[0] wr_index[1] $abc$24881$new_n3800 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[12] alu_result[12] dbg_val[12] $abc$24881$new_n3801 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3803 DIVIDE.thedivide.r_dividend[11] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3683 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22604 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[11] DIVIDE.thedivide.r_dividend[10] $abc$24881$new_n3803 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3805 r_op_Av[11] o_mem_data[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3806 i_mem_result[11] wr_index[0] wr_index[1] $abc$24881$new_n3805 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[11] alu_result[11] dbg_val[11] $abc$24881$new_n3806 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3808 DIVIDE.thedivide.r_dividend[10] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3684 DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22606 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10101 1 +11001 1 +11011 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign o_mem_data[10] DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3808 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3810 r_op_Av[10] o_mem_data[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3811 i_mem_result[10] wr_index[0] wr_index[1] $abc$24881$new_n3810 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[10] alu_result[10] dbg_val[10] $abc$24881$new_n3811 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3813 DIVIDE.thedivide.r_dividend[9] $abc$24881$new_n3685 $abc$24881$auto$rtlil.cc:2693:MuxGate$22608 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[9] DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3813 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3815 r_op_Av[9] o_mem_data[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3816 i_mem_result[9] wr_index[0] wr_index[1] $abc$24881$new_n3815 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[9] alu_result[9] dbg_val[9] $abc$24881$new_n3816 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign $abc$24881$new_n3818 DIVIDE.thedivide.r_dividend[8] $abc$24881$new_n3686 $abc$24881$auto$rtlil.cc:2693:MuxGate$22610 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1011 1 +1100 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] o_mem_data[8] DIVIDE.thedivide.r_dividend[7] $abc$24881$new_n3818 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3820 r_op_Av[8] o_mem_data[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3821 i_mem_result[8] wr_index[0] wr_index[1] $abc$24881$new_n3820 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[8] alu_result[8] dbg_val[8] $abc$24881$new_n3821 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3825 r_op_Av[7] o_mem_data[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3826 i_mem_result[7] wr_index[0] wr_index[1] $abc$24881$new_n3825 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[7] alu_result[7] dbg_val[7] $abc$24881$new_n3826 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n3828 +00 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n3829 +10 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3834 DIVIDE.thedivide.r_dividend[6] o_mem_data[6] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22614 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3832 r_op_Av[6] o_mem_data[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3833 i_mem_result[6] wr_index[0] wr_index[1] $abc$24881$new_n3832 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[6] alu_result[6] dbg_val[6] $abc$24881$new_n3833 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[5] $abc$24881$new_n3834 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3838 r_op_Av[5] o_mem_data[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3839 i_mem_result[5] wr_index[0] wr_index[1] $abc$24881$new_n3838 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[5] alu_result[5] dbg_val[5] $abc$24881$new_n3839 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3845 DIVIDE.thedivide.r_dividend[4] o_mem_data[4] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22618 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3843 r_op_Av[4] o_mem_data[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3844 i_mem_result[4] wr_index[0] wr_index[1] $abc$24881$new_n3843 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[4] alu_result[4] dbg_val[4] $abc$24881$new_n3844 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[4] DIVIDE.thedivide.r_dividend[3] $abc$24881$new_n3688 DIVIDE.thedivide.r_busy $abc$24881$new_n3845 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3850 DIVIDE.thedivide.r_dividend[3] o_mem_data[3] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22620 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3848 r_op_Av[3] o_mem_data[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3849 i_mem_result[3] wr_index[0] wr_index[1] $abc$24881$new_n3848 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[3] alu_result[3] dbg_val[3] $abc$24881$new_n3849 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[3] DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3689 DIVIDE.thedivide.r_busy $abc$24881$new_n3850 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[2] $abc$24881$new_n3855 o_mem_data[2] $abc$24881$new_n3828 $abc$24881$auto$rtlil.cc:2693:MuxGate$22622 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] o_mem_data[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3854 i_mem_result[2] wr_index[0] wr_index[1] $abc$24881$new_n3853 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[2] alu_result[2] dbg_val[2] $abc$24881$new_n3854 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[2] DIVIDE.thedivide.r_dividend[1] DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy $abc$24881$new_n3855 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3704 $abc$24881$new_n3857 DIVIDE.thedivide.r_dividend[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22624 +000 1 +001 1 +101 1 +111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[1] o_mem_data[1] $abc$24881$new_n3857 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +10000 1 +10001 1 +10100 1 +10101 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names r_op_Av[1] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3859 o_mem_data[1] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names wr_index[0] wr_index[1] $abc$24881$new_n3860 DIVIDE.thedivide.o_quotient[1] i_mem_result[1] $abc$24881$new_n3859 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names wr_index[1] alu_result[1] dbg_val[1] $abc$24881$new_n3860 +000 1 +010 1 +100 1 +101 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[0] o_mem_data[0] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$22626 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names r_op_Av[0] $abc$24881$new_n3699 $abc$24881$new_n3696 $abc$24881$new_n3693 $abc$24881$new_n3863 o_mem_data[0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n3864 dbg_val[0] wr_index[1] wr_index[0] $abc$24881$new_n3863 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.o_quotient[0] i_mem_result[0] alu_result[0] $abc$24881$new_n3864 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3866 DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22630 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3867 $abc$24881$new_n3866 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3868 $abc$24881$new_n3867 +001 1 +100 1 +101 1 +111 1 +.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n3869 $abc$24881$new_n3868 +000 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_dividend[60] DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n3870 $abc$24881$new_n3869 +000 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3871 $abc$24881$new_n3870 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3872 $abc$24881$new_n3871 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3873 $abc$24881$new_n3872 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3874 $abc$24881$new_n3873 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3875 $abc$24881$new_n3874 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3876 $abc$24881$new_n3875 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3877 $abc$24881$new_n3876 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3878 $abc$24881$new_n3877 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3879 $abc$24881$new_n3878 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3880 $abc$24881$new_n3879 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3881 $abc$24881$new_n3880 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3882 $abc$24881$new_n3881 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[34] DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3883 $abc$24881$new_n3882 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3884 $abc$24881$new_n3883 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[31] $abc$24881$new_n3884 +10 1 +.names $abc$24881$new_n3886 DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22634 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3887 $abc$24881$new_n3886 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[28] DIVIDE.thedivide.r_dividend[59] DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3871 $abc$24881$new_n3887 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3889 DIVIDE.thedivide.r_dividend[59] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22638 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[58] DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n3871 $abc$24881$new_n3867 $abc$24881$new_n3889 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3891 DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22642 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3892 $abc$24881$new_n3891 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[26] DIVIDE.thedivide.r_dividend[57] DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3872 $abc$24881$new_n3892 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3894 DIVIDE.thedivide.r_dividend[57] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22646 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[56] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n3872 $abc$24881$new_n3867 $abc$24881$new_n3894 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3896 DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22650 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3897 $abc$24881$new_n3896 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_dividend[55] DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3873 $abc$24881$new_n3897 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3899 DIVIDE.thedivide.r_dividend[55] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22654 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[54] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n3873 $abc$24881$new_n3867 $abc$24881$new_n3899 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3901 DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22658 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3902 $abc$24881$new_n3901 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_dividend[53] DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3874 $abc$24881$new_n3902 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3904 DIVIDE.thedivide.r_dividend[53] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22662 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[52] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n3874 $abc$24881$new_n3867 $abc$24881$new_n3904 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3906 DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22666 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3907 $abc$24881$new_n3906 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_dividend[51] DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3875 $abc$24881$new_n3907 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3909 DIVIDE.thedivide.r_dividend[51] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22670 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[50] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n3875 $abc$24881$new_n3867 $abc$24881$new_n3909 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3911 DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22674 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3912 $abc$24881$new_n3911 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_dividend[49] DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3876 $abc$24881$new_n3912 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3914 DIVIDE.thedivide.r_dividend[49] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22678 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[48] DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n3876 $abc$24881$new_n3867 $abc$24881$new_n3914 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3916 DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22682 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3917 $abc$24881$new_n3916 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[16] DIVIDE.thedivide.r_dividend[47] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3877 $abc$24881$new_n3917 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3919 DIVIDE.thedivide.r_dividend[47] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22686 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3877 $abc$24881$new_n3867 $abc$24881$new_n3919 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3921 DIVIDE.thedivide.r_dividend[46] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22690 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3922 $abc$24881$new_n3921 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_dividend[45] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3878 $abc$24881$new_n3922 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3924 DIVIDE.thedivide.r_dividend[45] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22694 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n3878 $abc$24881$new_n3867 $abc$24881$new_n3924 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3926 DIVIDE.thedivide.r_dividend[44] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22698 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3927 $abc$24881$new_n3926 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3879 $abc$24881$new_n3927 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3929 DIVIDE.thedivide.r_dividend[43] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22702 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[42] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n3879 $abc$24881$new_n3867 $abc$24881$new_n3929 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3931 DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22706 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3932 $abc$24881$new_n3931 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_dividend[41] DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3880 $abc$24881$new_n3932 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3934 DIVIDE.thedivide.r_dividend[41] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22710 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[40] DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n3880 $abc$24881$new_n3867 $abc$24881$new_n3934 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3936 DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22714 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3937 $abc$24881$new_n3936 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[8] DIVIDE.thedivide.r_dividend[39] DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3881 $abc$24881$new_n3937 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3939 DIVIDE.thedivide.r_dividend[39] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22718 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[38] DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n3881 $abc$24881$new_n3867 $abc$24881$new_n3939 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3941 DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22722 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3942 $abc$24881$new_n3941 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[6] DIVIDE.thedivide.r_dividend[37] DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3882 $abc$24881$new_n3942 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3944 DIVIDE.thedivide.r_dividend[37] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22726 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[36] DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n3882 $abc$24881$new_n3867 $abc$24881$new_n3944 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3946 DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22730 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3947 $abc$24881$new_n3946 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[4] DIVIDE.thedivide.r_dividend[35] DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3947 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3949 DIVIDE.thedivide.r_dividend[35] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22734 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3950 $abc$24881$new_n3949 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[3] DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3883 $abc$24881$new_n3950 +001 1 +010 1 +100 1 +111 1 +.names $abc$24881$new_n3952 DIVIDE.thedivide.r_dividend[34] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22738 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n3867 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3953 $abc$24881$new_n3952 +1001 1 +1011 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_dividend[33] DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3884 $abc$24881$new_n3953 +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n3955 DIVIDE.thedivide.r_dividend[33] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$22742 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n3884 $abc$24881$new_n3867 $abc$24881$new_n3955 +10010 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] SET_USER_PC.r_upc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22744 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3958 $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n3957 +1000 1 +.names $abc$24881$new_n3698 $abc$24881$new_n3697 $abc$24881$new_n3959 $abc$24881$new_n3958 +000 1 +.names i_mem_valid dbgv $abc$24881$new_n3700 $abc$24881$new_n3959 +000 1 +.names SET_GIE.r_gie $abc$24881$new_n3961 $abc$24881$new_n3960 +10 1 +.names mem_pc_valid o_i_count SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n3961 +000 1 +001 1 +011 1 +.names r_alu_pc_valid new_pc DIVIDE.thedivide.o_busy o_i_count +100 1 +.names wr_index[1] wr_index[0] alu_result[30] i_mem_result[30] dbg_val[30] $abc$24881$new_n3963 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] SET_USER_PC.r_upc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22746 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[29] i_mem_result[29] dbg_val[29] $abc$24881$new_n3965 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] SET_USER_PC.r_upc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22748 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[28] i_mem_result[28] dbg_val[28] $abc$24881$new_n3967 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] SET_USER_PC.r_upc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$22750 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[27] i_mem_result[27] dbg_val[27] $abc$24881$new_n3969 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] SET_USER_PC.r_upc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22752 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[26] i_mem_result[26] dbg_val[26] $abc$24881$new_n3971 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] SET_USER_PC.r_upc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$22754 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[25] i_mem_result[25] dbg_val[25] $abc$24881$new_n3973 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] SET_USER_PC.r_upc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$22756 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[24] i_mem_result[24] dbg_val[24] $abc$24881$new_n3975 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] SET_USER_PC.r_upc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$22758 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[23] i_mem_result[23] dbg_val[23] $abc$24881$new_n3977 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] SET_USER_PC.r_upc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$22760 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[22] i_mem_result[22] dbg_val[22] $abc$24881$new_n3979 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] SET_USER_PC.r_upc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$22762 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[21] i_mem_result[21] dbg_val[21] $abc$24881$new_n3981 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] SET_USER_PC.r_upc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$22764 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[20] i_mem_result[20] dbg_val[20] $abc$24881$new_n3983 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] SET_USER_PC.r_upc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$22766 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[19] i_mem_result[19] dbg_val[19] $abc$24881$new_n3985 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] SET_USER_PC.r_upc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$22768 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[18] i_mem_result[18] dbg_val[18] $abc$24881$new_n3987 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] SET_USER_PC.r_upc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$22770 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[17] i_mem_result[17] dbg_val[17] $abc$24881$new_n3989 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] SET_USER_PC.r_upc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$22772 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[16] i_mem_result[16] dbg_val[16] $abc$24881$new_n3991 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] SET_USER_PC.r_upc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$22774 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[15] i_mem_result[15] dbg_val[15] $abc$24881$new_n3993 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] SET_USER_PC.r_upc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$22776 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[14] i_mem_result[14] dbg_val[14] $abc$24881$new_n3995 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] SET_USER_PC.r_upc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22778 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[13] i_mem_result[13] dbg_val[13] $abc$24881$new_n3997 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] SET_USER_PC.r_upc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22780 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[12] i_mem_result[12] dbg_val[12] $abc$24881$new_n3999 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] SET_USER_PC.r_upc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22782 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[11] i_mem_result[11] dbg_val[11] $abc$24881$new_n4001 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] SET_USER_PC.r_upc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22784 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[10] i_mem_result[10] dbg_val[10] $abc$24881$new_n4003 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] SET_USER_PC.r_upc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22786 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[9] i_mem_result[9] dbg_val[9] $abc$24881$new_n4005 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] SET_USER_PC.r_upc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22788 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[8] i_mem_result[8] dbg_val[8] $abc$24881$new_n4007 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] SET_USER_PC.r_upc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22790 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[7] i_mem_result[7] dbg_val[7] $abc$24881$new_n4009 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] SET_USER_PC.r_upc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22792 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[6] i_mem_result[6] dbg_val[6] $abc$24881$new_n4011 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] SET_USER_PC.r_upc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22794 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[5] i_mem_result[5] dbg_val[5] $abc$24881$new_n4013 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] SET_USER_PC.r_upc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22796 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[4] i_mem_result[4] dbg_val[4] $abc$24881$new_n4015 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] SET_USER_PC.r_upc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22798 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[3] i_mem_result[3] dbg_val[3] $abc$24881$new_n4017 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] SET_USER_PC.r_upc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22800 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] alu_result[2] i_mem_result[2] dbg_val[2] $abc$24881$new_n4019 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4123 $abc$24881$new_n4021 $abc$24881$new_n4122 $abc$24881$new_n3963 $abc$24881$auto$rtlil.cc:2693:MuxGate$22802 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4022 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 $abc$24881$new_n4121 $abc$24881$new_n4021 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4023 $abc$24881$new_n4087 SET_USER_PC.r_upc[30] $abc$24881$new_n4022 +0001 1 +0010 1 +0011 1 +.names $abc$24881$new_n4024 pf_pc[30] pf_pc[28] pf_pc[29] $abc$24881$new_n4090 $abc$24881$new_n4023 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4024 +10 1 +.names $abc$24881$new_n4026 $abc$24881$new_n4086 i_reset $abc$24881$new_n4025 +000 1 +001 1 +011 1 +.names $abc$24881$new_n4075 $abc$24881$new_n4081 new_pc $abc$24881$new_n4085 o_pf_ready $abc$24881$new_n4026 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4028 o_pf_ready +00 1 +.names instruction_decoder.r_valid $abc$24881$new_n4029 $abc$24881$new_n4028 +10 1 +.names instruction_decoder.r_valid op_valid $abc$24881$new_n4030 $abc$24881$new_n4051 $abc$24881$new_n4073 $abc$24881$new_n4029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10110 1 +11010 1 +.names mem_ce $abc$24881$new_n4031 $abc$24881$new_n4030 +00 1 +.names $abc$24881$new_n4032 i_mem_rdbusy op_valid_mem $abc$24881$new_n4047 $abc$24881$new_n4031 +1000 1 +.names $abc$24881$new_n4033 $abc$24881$new_n4040 r_op_break BUSLOCK.r_prelock_stall DIVERR.r_idiv_err_flag $abc$24881$new_n4032 +11000 1 +.names $abc$24881$new_n4037 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4033 +10 1 +.names $abc$24881$new_n3697 $abc$24881$new_n4035 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y +11 1 +.names $abc$24881$new_n4036 $abc$24881$new_n3959 $abc$24881$new_n4035 +10 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n3695 $abc$24881$new_n4036 +000 1 +.names last_write_to_cc o_break sleep GEN_ALU_PHASE.r_alu_phase i_halt $abc$24881$new_n4037 +00000 1 +00010 1 +00011 1 +.names $abc$24881$new_n4039 ill_err_i SET_GIE.r_gie i_bus_err DIVIDE.thedivide.o_err o_break +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names new_pc GEN_PENDING_BREAK.r_break_pending SET_GIE.r_gie SET_ALU_ILLEGAL.r_alu_illegal break_en $abc$24881$new_n4039 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4044 $abc$24881$new_n4046 $abc$24881$new_n4041 $abc$24881$new_n4040 +100 1 +.names $abc$24881$new_n4042 GEN_PENDING_INTERRUPT.r_pending_interrupt i_halt $abc$24881$new_n4041 +110 1 +.names GEN_ALU_PHASE.r_alu_phase o_bus_lock $abc$24881$new_n4042 +00 1 +.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] o_bus_lock +01 1 +10 1 +11 1 +.names $abc$24881$new_n4045 i_mem_busy op_valid_div op_illegal $abc$24881$new_n4044 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names op_valid SET_ALU_ILLEGAL.r_alu_illegal ibus_err_flag DIVIDE.thedivide.o_busy $abc$24881$new_n4045 +1000 1 +.names user_step GEN_PENDING_INTERRUPT.r_user_stepped SET_GIE.r_gie $abc$24881$new_n4046 +111 1 +.names i_mem_busy $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] $abc$24881$new_n4047 +11000 1 +11110 1 +.names GEN_OP_WR.r_op_wR o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n4048 +1111 1 +.names $abc$24881$new_n4050 $abc$24881$new_n4032 i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4035 mem_ce +11000 1 +.names op_valid_mem i_mem_pipe_stalled new_pc GEN_OP_PIPE.r_op_pipe i_mem_busy $abc$24881$new_n4050 +10000 1 +10010 1 +10011 1 +.names i_halt $abc$24881$new_n4064 $abc$24881$new_n9842 $abc$24881$new_n4072 dcd_rB $abc$24881$new_n4051 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +.names instruction_decoder.o_dcdB[3] alu_reg[3] alu_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n4062 +0000 1 +0011 1 +1100 1 +1111 1 +.names $abc$24881$new_n4065 $abc$24881$new_n4067 dcd_F[3] instruction_decoder.o_dcdA[2] $abc$24881$new_n4070 $abc$24881$new_n4064 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names GEN_OP_STALL.r_pending_sreg_write op_valid $abc$24881$new_n4048 $abc$24881$new_n4066 $abc$24881$new_n4065 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names o_mem_reg[0] SET_GIE.r_gie o_mem_reg[4] $abc$24881$new_n4066 +100 1 +111 1 +.names dcd_rB $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] $abc$24881$new_n4068 instruction_decoder.o_dcdB[0] $abc$24881$new_n4067 +11100 1 +11101 1 +11110 1 +.names SET_GIE.r_gie instruction_decoder.o_dcdB[4] $abc$24881$new_n4068 +00 1 +11 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4069 +11 1 +.names dcd_rA instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n4071 instruction_decoder.o_dcdA[0] $abc$24881$new_n4070 +11100 1 +11101 1 +11110 1 +.names SET_GIE.r_gie instruction_decoder.o_dcdA[4] $abc$24881$new_n4071 +00 1 +11 1 +.names i_mem_rdbusy op_valid DIVIDE.thedivide.o_busy $abc$24881$new_n4072 +000 1 +.names GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 $abc$24881$new_n4072 dcd_Bcc dcd_rB $abc$24881$new_n4073 +01000 1 +01001 1 +01010 1 +01011 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_rA dcd_Acc op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n4074 +1101 1 +1110 1 +1111 1 +.names $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4075 +0000 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_reset $abc$24881$new_n4077 $abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +01 1 +10 1 +11 1 +.names SET_GIE.r_gie $abc$24881$new_n4078 $abc$24881$new_n4077 +10 1 +.names $abc$24881$new_n4080 $abc$24881$new_n4079 $abc$24881$new_n4013 $abc$24881$new_n4078 +100 1 +101 1 +110 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n3694 $abc$24881$new_n4079 +10 1 +.names i_bus_err DIVIDE.thedivide.o_err $abc$24881$new_n4041 i_mem_busy $abc$24881$new_n4080 +0000 1 +0001 1 +0011 1 +.names $abc$24881$new_n4082 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y SET_GIE.r_gie dbg_clear_pipe o_clear_icache $abc$24881$new_n4081 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +.names $abc$24881$new_n4083 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n4082 +1000 1 +.names $abc$24881$new_n3694 $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y $abc$24881$new_n4083 +11 1 +.names $abc$24881$new_n4035 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y +1010 1 +1100 1 +.names i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n4085 +10 1 +.names dbgv $abc$24881$new_n4036 SET_GIE.r_gie $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n4086 +11010 1 +11100 1 +.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4087 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4081 $abc$24881$new_n4075 $abc$24881$new_n4088 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc o_pf_new_pc +01 1 +10 1 +11 1 +.names pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4090 +11 1 +.names pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4091 +11 1 +.names pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4092 +11 1 +.names pf_pc[22] pf_pc[23] pf_pc[24] $abc$24881$new_n4094 $abc$24881$new_n4093 +1111 1 +.names pf_pc[19] pf_pc[20] pf_pc[21] $abc$24881$new_n4095 $abc$24881$new_n4094 +1111 1 +.names pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4095 +11 1 +.names pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4096 +11 1 +.names pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4097 +11 1 +.names pf_pc[13] pf_pc[14] pf_pc[15] $abc$24881$new_n4099 $abc$24881$new_n4098 +1111 1 +.names pf_pc[11] pf_pc[12] $abc$24881$new_n4100 $abc$24881$new_n4099 +111 1 +.names pf_pc[7] pf_pc[8] pf_pc[9] pf_pc[10] $abc$24881$new_n4101 $abc$24881$new_n4100 +11111 1 +.names pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4101 +11 1 +.names pf_pc[2] pf_pc[3] pf_pc[4] pf_pc[5] $abc$24881$new_n4102 +1111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4026 $abc$24881$new_n4104 $abc$24881$new_n4103 +000 1 +001 1 +010 1 +.names i_reset $abc$24881$new_n4086 $abc$24881$new_n4105 $abc$24881$new_n4104 +000 1 +.names dbg_clear_pipe o_clear_icache $abc$24881$new_n4082 $abc$24881$new_n4077 $abc$24881$new_n4105 +0000 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4106 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 $abc$24881$new_n4107 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4108 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 $abc$24881$new_n4109 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 $abc$24881$new_n4110 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 $abc$24881$new_n4111 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 $abc$24881$new_n4112 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n4114 $abc$24881$new_n4113 +11111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 $abc$24881$new_n4114 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n4116 $abc$24881$new_n4115 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 $abc$24881$new_n4116 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n4118 $abc$24881$new_n4117 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n4119 $abc$24881$new_n4118 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 $abc$24881$new_n4119 +11 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n4120 +111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4121 +11 1 +.names $abc$24881$new_n4104 $abc$24881$new_n4087 $abc$24881$new_n4025 $abc$24881$new_n4122 +000 1 +.names ipc[30] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[30] $abc$24881$new_n4123 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4104 $abc$24881$new_n4026 $abc$24881$new_n4124 +10 1 +.names $abc$24881$new_n4088 o_pf_new_pc o_pf_ready $abc$24881$new_n4085 $abc$24881$new_n4125 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4129 $abc$24881$new_n4127 $abc$24881$new_n4128 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22804 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$24881$new_n4121 $abc$24881$new_n4024 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4106 SET_USER_PC.r_upc[29] $abc$24881$new_n4127 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10110 1 +10111 1 +.names $abc$24881$new_n4024 pf_pc[29] pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4128 +1000 1 +1001 1 +1010 1 +1111 1 +.names $abc$24881$new_n4130 $abc$24881$new_n4122 $abc$24881$new_n3965 $abc$24881$new_n4129 +100 1 +101 1 +111 1 +.names ipc[29] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[29] $abc$24881$new_n4130 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4132 pf_pc[28] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22806 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4133 $abc$24881$new_n3967 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[28] $abc$24881$new_n4132 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n4107 $abc$24881$new_n4134 $abc$24881$new_n4133 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 pf_pc[28] $abc$24881$new_n4090 $abc$24881$new_n4025 SET_USER_PC.r_upc[28] $abc$24881$new_n4134 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4136 pf_pc[27] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22808 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4137 $abc$24881$new_n3969 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[27] $abc$24881$new_n4136 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[27] $abc$24881$new_n4091 $abc$24881$new_n4138 $abc$24881$new_n4137 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n4108 SET_USER_PC.r_upc[27] $abc$24881$new_n4138 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4140 pf_pc[26] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22810 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4141 $abc$24881$new_n3971 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[26] $abc$24881$new_n4140 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$new_n4109 $abc$24881$new_n4142 $abc$24881$new_n4141 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 pf_pc[26] $abc$24881$new_n4092 $abc$24881$new_n4025 SET_USER_PC.r_upc[26] $abc$24881$new_n4142 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4144 ipc[25] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22812 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4145 $abc$24881$new_n3973 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[25] $abc$24881$new_n4144 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[25] $abc$24881$new_n4093 $abc$24881$new_n4146 $abc$24881$new_n4145 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n4110 SET_USER_PC.r_upc[25] $abc$24881$new_n4146 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4148 $abc$24881$new_n4122 $abc$24881$new_n3975 $abc$24881$auto$rtlil.cc:2693:MuxGate$22814 +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$24881$new_n4151 $abc$24881$new_n4103 $abc$24881$new_n4150 $abc$24881$new_n4149 $abc$24881$new_n4148 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[24] pf_pc[22] pf_pc[23] $abc$24881$new_n4094 $abc$24881$new_n4149 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n4111 SET_USER_PC.r_upc[24] $abc$24881$new_n4150 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names ipc[24] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[24] $abc$24881$new_n4151 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4153 pf_pc[23] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22816 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4155 $abc$24881$new_n4103 $abc$24881$new_n4156 $abc$24881$new_n4154 $abc$24881$new_n4153 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[23] pf_pc[22] $abc$24881$new_n4094 $abc$24881$new_n4154 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3977 ipc[23] $abc$24881$new_n4124 $abc$24881$new_n4155 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$new_n4112 SET_USER_PC.r_upc[23] $abc$24881$new_n4156 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3979 pf_pc[22] $abc$24881$new_n4125 $abc$24881$new_n4160 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4163 ipc[21] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22820 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4165 $abc$24881$new_n4103 $abc$24881$new_n4166 $abc$24881$new_n4164 $abc$24881$new_n4163 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[21] pf_pc[19] pf_pc[20] $abc$24881$new_n4095 $abc$24881$new_n4164 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3981 pf_pc[21] $abc$24881$new_n4125 $abc$24881$new_n4165 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n4113 SET_USER_PC.r_upc[21] $abc$24881$new_n4166 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4125 $abc$24881$new_n4168 pf_pc[20] $abc$24881$new_n4169 $abc$24881$new_n4103 $abc$24881$auto$rtlil.cc:2693:MuxGate$22822 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4124 ipc[20] $abc$24881$new_n4122 $abc$24881$new_n3983 $abc$24881$new_n4168 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[20] $abc$24881$new_n4171 $abc$24881$new_n4170 $abc$24881$new_n4169 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names pf_pc[20] pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4170 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n4114 $abc$24881$new_n4171 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4173 ipc[19] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22824 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4175 $abc$24881$new_n4103 $abc$24881$new_n4176 $abc$24881$new_n4174 $abc$24881$new_n4173 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n4114 $abc$24881$new_n4174 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3985 pf_pc[19] $abc$24881$new_n4125 $abc$24881$new_n4175 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 pf_pc[19] $abc$24881$new_n4095 $abc$24881$new_n4025 SET_USER_PC.r_upc[19] $abc$24881$new_n4176 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4178 ipc[18] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22826 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4179 $abc$24881$new_n3987 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[18] $abc$24881$new_n4178 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4180 $abc$24881$new_n4181 SET_USER_PC.r_upc[18] $abc$24881$new_n4087 $abc$24881$new_n4179 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4024 pf_pc[18] $abc$24881$new_n4096 $abc$24881$new_n4180 +101 1 +110 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 $abc$24881$new_n4181 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4183 ipc[17] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22828 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4184 $abc$24881$new_n3989 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[17] $abc$24881$new_n4183 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[17] $abc$24881$new_n4097 $abc$24881$new_n4185 $abc$24881$new_n4184 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n4114 SET_USER_PC.r_upc[17] $abc$24881$new_n4185 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4187 ipc[16] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22830 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4188 $abc$24881$new_n3991 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[16] $abc$24881$new_n4187 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[16] $abc$24881$new_n4098 $abc$24881$new_n4189 $abc$24881$new_n4188 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n4115 SET_USER_PC.r_upc[16] $abc$24881$new_n4189 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4194 $abc$24881$new_n3993 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4191 $abc$24881$auto$rtlil.cc:2693:MuxGate$22832 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[15] $abc$24881$new_n4192 $abc$24881$new_n4193 $abc$24881$new_n4191 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n4116 $abc$24881$new_n4192 +011 1 +100 1 +101 1 +110 1 +.names pf_pc[15] pf_pc[13] pf_pc[14] $abc$24881$new_n4099 $abc$24881$new_n4193 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ipc[15] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[15] $abc$24881$new_n4194 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3995 pf_pc[14] $abc$24881$new_n4125 $abc$24881$new_n4198 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n3997 pf_pc[13] $abc$24881$new_n4125 $abc$24881$new_n4203 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4208 $abc$24881$new_n4103 $abc$24881$new_n4206 $abc$24881$new_n4122 $abc$24881$new_n3999 $abc$24881$auto$rtlil.cc:2693:MuxGate$22838 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n4207 pf_pc[12] pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4024 $abc$24881$new_n4206 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4117 SET_USER_PC.r_upc[12] $abc$24881$new_n4207 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names ipc[12] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[12] $abc$24881$new_n4208 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4210 ipc[11] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22840 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4212 $abc$24881$new_n4103 $abc$24881$new_n4213 $abc$24881$new_n4211 $abc$24881$new_n4210 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n4118 $abc$24881$new_n4211 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4001 pf_pc[11] $abc$24881$new_n4125 $abc$24881$new_n4212 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 pf_pc[11] $abc$24881$new_n4100 $abc$24881$new_n4025 SET_USER_PC.r_upc[11] $abc$24881$new_n4213 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4218 $abc$24881$new_n4103 $abc$24881$new_n4215 $abc$24881$new_n4122 $abc$24881$new_n4003 $abc$24881$auto$rtlil.cc:2693:MuxGate$22842 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n4024 $abc$24881$new_n4216 $abc$24881$new_n4217 SET_USER_PC.r_upc[10] $abc$24881$new_n4087 $abc$24881$new_n4215 +00000 1 +00100 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 $abc$24881$new_n4216 +1000 1 +1001 1 +1010 1 +1111 1 +.names pf_pc[10] pf_pc[7] pf_pc[8] pf_pc[9] $abc$24881$new_n4101 $abc$24881$new_n4217 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names ipc[10] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[10] $abc$24881$new_n4218 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4220 pf_pc[9] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22844 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4222 $abc$24881$new_n4103 $abc$24881$new_n4221 $abc$24881$new_n4223 $abc$24881$new_n4220 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[9] pf_pc[7] pf_pc[8] $abc$24881$new_n4101 $abc$24881$new_n4221 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4005 ipc[9] $abc$24881$new_n4124 $abc$24881$new_n4222 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n4118 SET_USER_PC.r_upc[9] $abc$24881$new_n4223 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4228 $abc$24881$new_n4007 $abc$24881$new_n4122 $abc$24881$new_n4103 $abc$24881$new_n4225 $abc$24881$auto$rtlil.cc:2693:MuxGate$22846 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 SET_USER_PC.r_upc[8] $abc$24881$new_n4227 $abc$24881$new_n4226 $abc$24881$new_n4225 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names pf_pc[8] pf_pc[7] $abc$24881$new_n4101 $abc$24881$new_n4226 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 $abc$24881$new_n4227 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names ipc[8] $abc$24881$new_n4124 $abc$24881$new_n4125 pf_pc[8] $abc$24881$new_n4228 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4009 pf_pc[7] $abc$24881$new_n4125 $abc$24881$new_n4232 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4235 ipc[6] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22850 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4236 $abc$24881$new_n4011 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[6] $abc$24881$new_n4235 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[6] $abc$24881$new_n4102 $abc$24881$new_n4237 $abc$24881$new_n4236 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4119 SET_USER_PC.r_upc[6] $abc$24881$new_n4237 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4239 pf_pc[5] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22852 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4241 $abc$24881$new_n4103 $abc$24881$new_n4240 $abc$24881$new_n4242 $abc$24881$new_n4239 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4024 pf_pc[5] pf_pc[2] pf_pc[3] pf_pc[4] $abc$24881$new_n4240 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4122 $abc$24881$new_n4013 ipc[5] $abc$24881$new_n4124 $abc$24881$new_n4241 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$new_n4120 SET_USER_PC.r_upc[5] $abc$24881$new_n4242 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4244 pf_pc[4] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22854 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4245 $abc$24881$new_n4015 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[4] $abc$24881$new_n4244 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4246 $abc$24881$new_n4247 SET_USER_PC.r_upc[4] $abc$24881$new_n4087 $abc$24881$new_n4245 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4024 pf_pc[4] pf_pc[2] pf_pc[3] $abc$24881$new_n4246 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n4247 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n4249 pf_pc[3] $abc$24881$new_n4125 $abc$24881$auto$rtlil.cc:2693:MuxGate$22856 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4250 $abc$24881$new_n4017 $abc$24881$new_n4122 $abc$24881$new_n4124 ipc[3] $abc$24881$new_n4249 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4024 pf_pc[2] pf_pc[3] $abc$24881$new_n4251 $abc$24881$new_n4250 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4087 $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n4251 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n4087 SET_USER_PC.r_upc[2] $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$new_n4255 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 dcd_Bpc $abc$24881$new_n4257 $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22860 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4258 $abc$24881$new_n4257 +1100 1 +.names $abc$24881$new_n4281 $abc$24881$new_n4266 $abc$24881$new_n4259 $abc$24881$new_n4274 $abc$24881$new_n4283 $abc$24881$new_n4258 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4271 $abc$24881$new_n4273 $abc$24881$new_n4259 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4260 +110 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4262 $abc$24881$new_n4261 +10 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4266 $abc$24881$new_n4262 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4263 +00 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[9] i_pf_instruction[25] $abc$24881$new_n4264 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[10] i_pf_instruction[26] $abc$24881$new_n4265 +000 1 +010 1 +100 1 +101 1 +.names i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4266 +00 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[8] i_pf_instruction[24] $abc$24881$new_n4267 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4264 i_pf_instruction[23] $abc$24881$new_n4267 $abc$24881$new_n4268 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4263 $abc$24881$new_n4266 i_pf_instruction[25] $abc$24881$new_n4269 +000 1 +001 1 +010 1 +.names $abc$24881$new_n4265 $abc$24881$new_n4267 $abc$24881$new_n4264 $abc$24881$new_n4266 $abc$24881$new_n4270 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4272 $abc$24881$new_n4271 +11 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4263 $abc$24881$new_n4272 +11 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] i_pf_instruction[23] $abc$24881$new_n4273 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4275 $abc$24881$new_n4271 $abc$24881$new_n4274 +100 1 +.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4275 +110 1 +.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4265 $abc$24881$new_n4276 +110 1 +.names $abc$24881$new_n4280 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n4277 +000 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[13] i_pf_instruction[29] $abc$24881$new_n4278 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[12] i_pf_instruction[28] $abc$24881$new_n4279 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[14] i_pf_instruction[30] $abc$24881$new_n4280 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n4282 $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4281 +10000 1 +.names $abc$24881$new_n4266 i_pf_instruction[22] $abc$24881$new_n4267 $abc$24881$new_n4265 $abc$24881$new_n4264 $abc$24881$new_n4282 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[2] i_pf_instruction[18] $abc$24881$new_n4283 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[17] $abc$24881$new_n4287 $abc$24881$new_n4285 $abc$24881$new_n4284 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4286 $abc$24881$new_n4285 +11 1 +.names $abc$24881$new_n4264 $abc$24881$new_n4265 $abc$24881$new_n4286 +10 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[6] i_pf_instruction[22] $abc$24881$new_n4287 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[16] $abc$24881$new_n4289 $abc$24881$new_n4285 $abc$24881$new_n4288 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[5] i_pf_instruction[21] $abc$24881$new_n4289 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4266 i_pf_instruction[15] $abc$24881$new_n4291 $abc$24881$new_n4285 $abc$24881$new_n4290 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[4] i_pf_instruction[20] $abc$24881$new_n4291 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4293 i_pf_instruction[31] $abc$24881$new_n4285 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[14] $abc$24881$new_n4292 +00000 1 +00100 1 +10000 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[3] i_pf_instruction[19] $abc$24881$new_n4293 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[4] SET_GIE.r_gie $abc$24881$new_n4295 i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22862 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4281 $abc$24881$new_n4295 +11 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$auto$rtlil.cc:2693:MuxGate$22864 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$auto$rtlil.cc:2693:MuxGate$22866 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$auto$rtlil.cc:2693:MuxGate$22868 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdB[0] $abc$24881$new_n4292 $abc$24881$auto$rtlil.cc:2693:MuxGate$22870 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_Apc $abc$24881$new_n4301 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22872 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4277 $abc$24881$new_n4295 SET_GIE.r_gie $abc$24881$new_n4283 $abc$24881$new_n4301 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[11] i_pf_instruction[27] $abc$24881$new_n4302 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[4] SET_GIE.r_gie $abc$24881$new_n4295 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$22874 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[3] $abc$24881$new_n4280 $abc$24881$auto$rtlil.cc:2693:MuxGate$22876 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[2] $abc$24881$new_n4278 $abc$24881$auto$rtlil.cc:2693:MuxGate$22878 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[1] $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$22880 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_dcdA[0] $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$22882 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[13] i_pf_instruction[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$22884 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[12] i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$22886 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[11] i_pf_instruction[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22888 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[10] i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$22890 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[9] i_pf_instruction[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$22892 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[8] i_pf_instruction[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22894 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[7] i_pf_instruction[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22896 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[6] i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22898 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[5] i_pf_instruction[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[4] i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22902 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[3] i_pf_instruction[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22904 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[2] i_pf_instruction[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22906 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[1] i_pf_instruction[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22908 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[0] i_pf_instruction[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22910 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_opn[2] $abc$24881$new_n4323 $abc$24881$new_n4262 $abc$24881$auto$rtlil.cc:2693:MuxGate$22914 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$new_n4273 $abc$24881$new_n4323 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n4028 dcd_opn[1] $abc$24881$new_n4323 $abc$24881$new_n4268 $abc$24881$auto$rtlil.cc:2693:MuxGate$22918 +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_opn[0] $abc$24881$new_n4282 $abc$24881$new_n4323 $abc$24881$auto$rtlil.cc:2693:MuxGate$22922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n5090 dcd_I[31] $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n4327 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +11111 1 +.names $abc$24881$new_n4995 dcd_I[31] $abc$24881$new_n9877 $abc$24881$new_n5041 $abc$24881$new_n4329 $abc$24881$new_n4328 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4972 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n9843 $abc$24881$new_n4971 $abc$24881$new_n4329 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n9502 dcd_I[13] dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n9847 $abc$24881$new_n4334 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4635 dcd_I[10] $abc$24881$new_n9496 $abc$24881$new_n4658 $abc$24881$new_n4337 $abc$24881$new_n4336 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4566 dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n4590 $abc$24881$new_n4338 $abc$24881$new_n4337 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9489 dcd_I[5] dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n4339 $abc$24881$new_n4338 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4406 dcd_I[4] dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n9858 $abc$24881$new_n4339 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4345 regset[29][4] regset[25][4] $abc$24881$new_n4344 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][4] regset[24][4] $abc$24881$new_n4345 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4348 regset[21][4] regset[17][4] $abc$24881$new_n4347 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][4] regset[16][4] $abc$24881$new_n4348 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4349 +00 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4352 regset[31][4] regset[27][4] $abc$24881$new_n4351 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][4] regset[26][4] $abc$24881$new_n4352 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4355 regset[23][4] regset[19][4] $abc$24881$new_n4354 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][4] regset[18][4] $abc$24881$new_n4355 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4356 +10 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4359 $abc$24881$new_n4361 $abc$24881$new_n4363 $abc$24881$new_n4358 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4360 regset[5][4] regset[1][4] $abc$24881$new_n4359 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][4] regset[0][4] $abc$24881$new_n4360 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4362 regset[7][4] regset[3][4] $abc$24881$new_n4361 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][4] regset[2][4] $abc$24881$new_n4362 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4364 regset[15][4] regset[11][4] $abc$24881$new_n4363 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][4] regset[10][4] $abc$24881$new_n4364 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4366 regset[13][4] regset[9][4] $abc$24881$new_n4365 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][4] regset[8][4] $abc$24881$new_n4366 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3843 $abc$24881$new_n4367 +10 1 +.names dcd_rB $abc$24881$new_n4371 $abc$24881$new_n4369 $abc$24881$new_n3959 $abc$24881$new_n4368 +1110 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] $abc$24881$new_n3701 $abc$24881$new_n3698 $abc$24881$new_n4370 $abc$24881$new_n4369 +00110 1 +01010 1 +10100 1 +11000 1 +.names instruction_decoder.o_dcdB[0] i_mem_valid alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4370 +1000 1 +1001 1 +1100 1 +1110 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n4372 $abc$24881$new_n4371 +00110 1 +01010 1 +10100 1 +11000 1 +.names i_mem_valid instruction_decoder.o_dcdB[0] alu_reg[0] i_mem_wreg[0] $abc$24881$new_n4372 +0010 1 +0011 1 +1001 1 +1011 1 +.names dcd_rB $abc$24881$new_n4369 $abc$24881$new_n4371 $abc$24881$new_n3959 $abc$24881$new_n4373 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][3] regset[18][3] $abc$24881$new_n4381 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][3] regset[19][3] $abc$24881$new_n4382 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4384 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][3] regset[16][3] $abc$24881$new_n4383 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][3] regset[17][3] $abc$24881$new_n4384 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4386 regset[31][3] regset[27][3] $abc$24881$new_n4385 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][3] regset[26][3] $abc$24881$new_n4386 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4389 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][3] regset[3][3] $abc$24881$new_n4388 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][3] regset[2][3] $abc$24881$new_n4389 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4391 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][3] regset[0][3] $abc$24881$new_n4390 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][3] regset[1][3] $abc$24881$new_n4391 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4394 regset[15][3] regset[11][3] $abc$24881$new_n4393 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][3] regset[10][3] $abc$24881$new_n4394 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4396 $abc$24881$new_n4395 +100 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4397 regset[13][3] regset[9][3] $abc$24881$new_n4396 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][3] regset[8][3] $abc$24881$new_n4397 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n4398 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4403 flags[3] $abc$24881$new_n4399 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4402 $abc$24881$new_n4401 $abc$24881$new_n4400 +11 1 +.names alu_wF doalu.o_valid DIVIDE.thedivide.o_valid DIVIDE.thedivide.o_err $abc$24881$new_n4401 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names SET_GIE.r_gie new_pc $abc$24881$new_n4402 +10 1 +.names doalu.set_ovfl wr_index[1] doalu.n doalu.pre_sign wr_index[0] $abc$24881$new_n4403 +11010 1 +11100 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4403 iflags[3] $abc$24881$new_n4404 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4401 new_pc SET_GIE.r_gie $abc$24881$new_n4405 +100 1 +.names dcd_I[2] dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n9442 $abc$24881$new_n4406 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][2] regset[11][2] $abc$24881$new_n4413 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][2] regset[10][2] $abc$24881$new_n4414 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4417 $abc$24881$new_n4418 $abc$24881$new_n4416 +10000 1 +10010 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[2] regset[29][2] regset[25][2] $abc$24881$new_n4417 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[28][2] regset[24][2] $abc$24881$new_n4418 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4430 regset[4][2] regset[0][2] $abc$24881$new_n4429 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[5][2] regset[1][2] $abc$24881$new_n4430 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[13][2] regset[9][2] $abc$24881$new_n4432 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[12][2] regset[8][2] $abc$24881$new_n4433 +001 1 +011 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n4434 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4436 iflags[2] $abc$24881$new_n4435 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4437 wr_index[1] wr_index[0] DIVIDE.thedivide.w_n $abc$24881$new_n4436 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names wr_index[1] doalu.keep_sgn_on_ovfl wr_index[0] doalu.pre_sign doalu.n $abc$24881$new_n4437 +10001 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4436 flags[2] $abc$24881$new_n4438 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4467 $abc$24881$new_n9455 $abc$24881$new_n4368 $abc$24881$new_n3859 $abc$24881$new_n4439 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][1] regset[3][1] $abc$24881$new_n4465 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][1] regset[2][1] $abc$24881$new_n4466 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4468 $abc$24881$new_n4470 $abc$24881$new_n4467 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4469 iflags[1] $abc$24881$new_n4468 +000 1 +010 1 +110 1 +111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.r_c doalu.c $abc$24881$new_n4469 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4469 flags[1] $abc$24881$new_n4470 +000 1 +010 1 +110 1 +111 1 +.names dcd_I[0] $abc$24881$new_n4500 $abc$24881$new_n4473 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n4471 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4373 $abc$24881$new_n4472 +11 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3863 $abc$24881$new_n4473 +10 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9868 $abc$24881$new_n4475 $abc$24881$new_n4476 dcd_Bcc $abc$24881$new_n4474 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names iflags[0] $abc$24881$new_n4405 $abc$24881$new_n4475 +10 1 +.names $abc$24881$new_n4405 $abc$24881$new_n4486 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4482 $abc$24881$new_n4476 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4478 $abc$24881$new_n4479 alu_result[22] alu_result[21] alu_result[20] $abc$24881$new_n4477 +11000 1 +.names alu_result[27] alu_result[26] alu_result[25] alu_result[24] $abc$24881$new_n4478 +0000 1 +.names doalu.n alu_result[30] alu_result[29] alu_result[28] alu_result[23] $abc$24881$new_n4479 +00000 1 +.names $abc$24881$new_n4481 alu_result[7] alu_result[6] alu_result[5] alu_result[4] $abc$24881$new_n4480 +10000 1 +.names alu_result[11] alu_result[10] alu_result[9] alu_result[8] $abc$24881$new_n4481 +0000 1 +.names wr_index[1] $abc$24881$new_n4483 $abc$24881$new_n4485 $abc$24881$new_n4484 wr_index[0] $abc$24881$new_n4482 +11110 1 +.names alu_result[3] alu_result[2] alu_result[1] alu_result[0] $abc$24881$new_n4483 +0000 1 +.names alu_result[19] alu_result[18] alu_result[17] alu_result[16] $abc$24881$new_n4484 +0000 1 +.names alu_result[15] alu_result[14] alu_result[13] alu_result[12] $abc$24881$new_n4485 +0000 1 +.names wr_index[1] DIVIDE.thedivide.r_z wr_index[0] $abc$24881$new_n4486 +111 1 +.names instruction_decoder.o_dcdB[2] regset[5][0] regset[1][0] $abc$24881$new_n4495 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[4][0] regset[0][0] $abc$24881$new_n4496 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9871 $abc$24881$new_n4400 $abc$24881$new_n4516 $abc$24881$new_n4501 flags[0] $abc$24881$new_n4500 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n4486 $abc$24881$new_n4482 $abc$24881$new_n4480 $abc$24881$new_n4477 $abc$24881$new_n4501 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4504 +10 1 +.names instruction_decoder.o_dcdB[2] regset[31][0] regset[27][0] $abc$24881$new_n4508 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[30][0] regset[26][0] $abc$24881$new_n4509 +001 1 +011 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4516 +11 1 +.names $abc$24881$new_n4373 dcd_Bcc $abc$24881$new_n4519 +10 1 +.names user_step SET_GIE.r_gie $abc$24881$new_n4520 +10 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4525 regset[13][6] regset[9][6] $abc$24881$new_n4524 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][6] regset[8][6] $abc$24881$new_n4525 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4530 regset[15][6] regset[11][6] $abc$24881$new_n4529 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][6] regset[10][6] $abc$24881$new_n4530 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4534 regset[31][6] regset[27][6] $abc$24881$new_n4533 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][6] regset[26][6] $abc$24881$new_n4534 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4537 regset[21][6] regset[17][6] $abc$24881$new_n4536 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][6] regset[16][6] $abc$24881$new_n4537 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4539 regset[29][6] regset[25][6] $abc$24881$new_n4538 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][6] regset[24][6] $abc$24881$new_n4539 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4541 regset[23][6] regset[19][6] $abc$24881$new_n4540 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][6] regset[18][6] $abc$24881$new_n4541 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4543 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][6] regset[2][6] $abc$24881$new_n4542 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][6] regset[3][6] $abc$24881$new_n4543 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4548 regset[13][5] regset[9][5] $abc$24881$new_n4547 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][5] regset[8][5] $abc$24881$new_n4548 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][5] regset[0][5] $abc$24881$new_n4549 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][5] regset[1][5] $abc$24881$new_n4550 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4553 regset[15][5] regset[11][5] $abc$24881$new_n4552 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][5] regset[10][5] $abc$24881$new_n4553 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4555 regset[7][5] regset[3][5] $abc$24881$new_n4554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][5] regset[2][5] $abc$24881$new_n4555 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4504 $abc$24881$new_n4557 $abc$24881$new_n4069 $abc$24881$new_n4564 $abc$24881$new_n4556 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$new_n4558 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4560 $abc$24881$new_n4562 $abc$24881$new_n4557 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4559 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][5] regset[18][5] $abc$24881$new_n4558 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][5] regset[19][5] $abc$24881$new_n4559 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4561 regset[21][5] regset[20][5] $abc$24881$new_n4560 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][5] regset[16][5] $abc$24881$new_n4561 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4563 regset[29][5] regset[25][5] $abc$24881$new_n4562 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][5] regset[24][5] $abc$24881$new_n4563 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4565 regset[31][5] regset[27][5] $abc$24881$new_n4564 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][5] regset[26][5] $abc$24881$new_n4565 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4566 +10 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4571 $abc$24881$new_n4573 $abc$24881$new_n4575 $abc$24881$new_n4570 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4572 regset[21][7] regset[17][7] $abc$24881$new_n4571 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][7] regset[16][7] $abc$24881$new_n4572 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4574 regset[29][7] regset[28][7] $abc$24881$new_n4573 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][7] regset[24][7] $abc$24881$new_n4574 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4576 regset[23][7] regset[19][7] $abc$24881$new_n4575 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][7] regset[18][7] $abc$24881$new_n4576 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4578 regset[31][7] regset[30][7] $abc$24881$new_n4577 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][7] regset[26][7] $abc$24881$new_n4578 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4581 $abc$24881$new_n4583 $abc$24881$new_n4585 $abc$24881$new_n4580 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4582 regset[5][7] regset[1][7] $abc$24881$new_n4581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][7] regset[0][7] $abc$24881$new_n4582 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4584 regset[13][7] regset[9][7] $abc$24881$new_n4583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][7] regset[8][7] $abc$24881$new_n4584 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4586 regset[7][7] regset[3][7] $abc$24881$new_n4585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][7] regset[2][7] $abc$24881$new_n4586 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4588 regset[15][7] regset[11][7] $abc$24881$new_n4587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][7] regset[10][7] $abc$24881$new_n4588 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9493 dcd_I[7] $abc$24881$new_n4590 +10 1 +.names $abc$24881$new_n4612 $abc$24881$new_n4592 $abc$24881$new_n4368 $abc$24881$new_n3820 $abc$24881$new_n4591 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4593 $abc$24881$new_n4603 $abc$24881$new_n4605 $abc$24881$new_n4592 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names $abc$24881$new_n4594 $abc$24881$new_n4601 $abc$24881$new_n4069 $abc$24881$new_n4593 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4595 $abc$24881$new_n4597 $abc$24881$new_n4599 $abc$24881$new_n4594 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4596 regset[5][8] regset[1][8] $abc$24881$new_n4595 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][8] regset[0][8] $abc$24881$new_n4596 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4598 regset[13][8] regset[9][8] $abc$24881$new_n4597 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][8] regset[8][8] $abc$24881$new_n4598 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4600 regset[7][8] regset[3][8] $abc$24881$new_n4599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][8] regset[2][8] $abc$24881$new_n4600 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4602 regset[15][8] regset[11][8] $abc$24881$new_n4601 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][8] regset[10][8] $abc$24881$new_n4602 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4604 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][8] regset[26][8] $abc$24881$new_n4603 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][8] regset[27][8] $abc$24881$new_n4604 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4606 $abc$24881$new_n4608 $abc$24881$new_n4610 $abc$24881$new_n4605 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4607 regset[21][8] regset[17][8] $abc$24881$new_n4606 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][8] regset[16][8] $abc$24881$new_n4607 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4609 regset[29][8] regset[28][8] $abc$24881$new_n4608 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][8] regset[24][8] $abc$24881$new_n4609 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4611 regset[23][8] regset[19][8] $abc$24881$new_n4610 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][8] regset[18][8] $abc$24881$new_n4611 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n4612 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4617 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4619 $abc$24881$new_n4621 $abc$24881$new_n4616 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4618 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][10] regset[3][10] $abc$24881$new_n4617 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][10] regset[2][10] $abc$24881$new_n4618 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4620 regset[5][10] regset[1][10] $abc$24881$new_n4619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][10] regset[0][10] $abc$24881$new_n4620 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4622 regset[13][10] regset[9][10] $abc$24881$new_n4621 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][10] regset[8][10] $abc$24881$new_n4622 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4624 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][10] regset[26][10] $abc$24881$new_n4623 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][10] regset[27][10] $abc$24881$new_n4624 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4626 $abc$24881$new_n4628 $abc$24881$new_n4630 $abc$24881$new_n4625 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4627 regset[21][10] regset[17][10] $abc$24881$new_n4626 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][10] regset[16][10] $abc$24881$new_n4627 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4629 regset[29][10] regset[28][10] $abc$24881$new_n4628 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][10] regset[24][10] $abc$24881$new_n4629 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4631 regset[23][10] regset[19][10] $abc$24881$new_n4630 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][10] regset[18][10] $abc$24881$new_n4631 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4633 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][10] regset[10][10] $abc$24881$new_n4632 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][10] regset[11][10] $abc$24881$new_n4633 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_I[9] $abc$24881$new_n4636 $abc$24881$new_n4635 +10 1 +.names $abc$24881$new_n4657 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n4637 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n4636 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n4638 $abc$24881$new_n4648 instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4655 $abc$24881$new_n4637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4639 $abc$24881$new_n4642 $abc$24881$new_n4644 $abc$24881$new_n4646 $abc$24881$new_n4069 $abc$24881$new_n4638 +10000 1 +10010 1 +10011 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4640 $abc$24881$new_n4639 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4641 regset[29][9] regset[25][9] $abc$24881$new_n4640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][9] regset[24][9] $abc$24881$new_n4641 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4643 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][9] regset[16][9] $abc$24881$new_n4642 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][9] regset[17][9] $abc$24881$new_n4643 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4645 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][9] regset[18][9] $abc$24881$new_n4644 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][9] regset[19][9] $abc$24881$new_n4645 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4647 regset[31][9] regset[27][9] $abc$24881$new_n4646 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][9] regset[26][9] $abc$24881$new_n4647 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4649 $abc$24881$new_n4651 $abc$24881$new_n4653 $abc$24881$new_n4648 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4650 regset[13][9] regset[9][9] $abc$24881$new_n4649 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][9] regset[8][9] $abc$24881$new_n4650 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4652 regset[15][9] regset[11][9] $abc$24881$new_n4651 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][9] regset[10][9] $abc$24881$new_n4652 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4654 regset[5][9] regset[1][9] $abc$24881$new_n4653 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][9] regset[0][9] $abc$24881$new_n4654 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4656 regset[7][9] regset[3][9] $abc$24881$new_n4655 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][9] regset[2][9] $abc$24881$new_n4656 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4368 $abc$24881$new_n3815 $abc$24881$new_n4657 +10 1 +.names $abc$24881$new_n4636 dcd_I[9] $abc$24881$new_n4658 +10 1 +.names $abc$24881$new_n4681 $abc$24881$new_n4661 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3805 $abc$24881$new_n4660 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4662 $abc$24881$new_n4669 $abc$24881$new_n4679 $abc$24881$new_n4069 $abc$24881$new_n4661 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4663 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4665 $abc$24881$new_n4667 $abc$24881$new_n4662 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4664 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][11] regset[3][11] $abc$24881$new_n4663 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][11] regset[2][11] $abc$24881$new_n4664 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4666 regset[5][11] regset[1][11] $abc$24881$new_n4665 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][11] regset[0][11] $abc$24881$new_n4666 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4668 regset[13][11] regset[9][11] $abc$24881$new_n4667 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][11] regset[8][11] $abc$24881$new_n4668 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4672 $abc$24881$new_n4670 $abc$24881$new_n4675 $abc$24881$new_n4677 $abc$24881$new_n4069 $abc$24881$new_n4669 +00000 1 +00010 1 +00011 1 +.names $abc$24881$new_n4671 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][11] regset[18][11] $abc$24881$new_n4670 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][11] regset[19][11] $abc$24881$new_n4671 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4673 $abc$24881$new_n4672 +100 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4674 regset[29][11] regset[25][11] $abc$24881$new_n4673 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][11] regset[24][11] $abc$24881$new_n4674 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4676 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][11] regset[17][11] $abc$24881$new_n4675 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][11] regset[16][11] $abc$24881$new_n4676 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4678 regset[31][11] regset[27][11] $abc$24881$new_n4677 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][11] regset[26][11] $abc$24881$new_n4678 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4680 regset[15][11] regset[11][11] $abc$24881$new_n4679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][11] regset[10][11] $abc$24881$new_n4680 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] dcd_Bcc DIVERR.USER_DIVERR.r_udiv_err_flag DIVERR.r_idiv_err_flag $abc$24881$new_n4681 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4687 $abc$24881$new_n4689 $abc$24881$new_n4686 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4688 regset[15][12] regset[11][12] $abc$24881$new_n4687 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][12] regset[10][12] $abc$24881$new_n4688 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4690 regset[13][12] regset[9][12] $abc$24881$new_n4689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][12] regset[8][12] $abc$24881$new_n4690 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4692 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][12] regset[2][12] $abc$24881$new_n4691 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][12] regset[3][12] $abc$24881$new_n4692 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4695 $abc$24881$new_n4697 $abc$24881$new_n4699 $abc$24881$new_n4694 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4696 regset[21][12] regset[17][12] $abc$24881$new_n4695 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][12] regset[16][12] $abc$24881$new_n4696 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4698 regset[29][12] regset[25][12] $abc$24881$new_n4697 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][12] regset[24][12] $abc$24881$new_n4698 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4700 regset[31][12] regset[27][12] $abc$24881$new_n4699 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][12] regset[26][12] $abc$24881$new_n4700 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4702 regset[23][12] regset[19][12] $abc$24881$new_n4701 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][12] regset[18][12] $abc$24881$new_n4702 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4704 regset[5][12] regset[1][12] $abc$24881$new_n4703 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][12] regset[0][12] $abc$24881$new_n4704 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4709 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4711 $abc$24881$new_n4713 $abc$24881$new_n4708 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4710 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][13] regset[3][13] $abc$24881$new_n4709 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][13] regset[2][13] $abc$24881$new_n4710 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4712 regset[5][13] regset[1][13] $abc$24881$new_n4711 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][13] regset[0][13] $abc$24881$new_n4712 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4714 regset[13][13] regset[9][13] $abc$24881$new_n4713 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][13] regset[8][13] $abc$24881$new_n4714 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4716 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][13] regset[26][13] $abc$24881$new_n4715 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][13] regset[27][13] $abc$24881$new_n4716 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4718 $abc$24881$new_n4720 $abc$24881$new_n4722 $abc$24881$new_n4717 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4719 regset[21][13] regset[17][13] $abc$24881$new_n4718 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][13] regset[16][13] $abc$24881$new_n4719 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4721 regset[29][13] regset[28][13] $abc$24881$new_n4720 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][13] regset[24][13] $abc$24881$new_n4721 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4723 regset[23][13] regset[19][13] $abc$24881$new_n4722 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][13] regset[18][13] $abc$24881$new_n4723 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4725 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][13] regset[10][13] $abc$24881$new_n4724 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][13] regset[11][13] $abc$24881$new_n4725 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4731 $abc$24881$new_n4733 $abc$24881$new_n4730 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4732 regset[15][14] regset[11][14] $abc$24881$new_n4731 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][14] regset[10][14] $abc$24881$new_n4732 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4734 regset[13][14] regset[9][14] $abc$24881$new_n4733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][14] regset[8][14] $abc$24881$new_n4734 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4736 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][14] regset[2][14] $abc$24881$new_n4735 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][14] regset[3][14] $abc$24881$new_n4736 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4739 $abc$24881$new_n4741 $abc$24881$new_n4743 $abc$24881$new_n4738 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4740 regset[21][14] regset[17][14] $abc$24881$new_n4739 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][14] regset[16][14] $abc$24881$new_n4740 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4742 regset[29][14] regset[25][14] $abc$24881$new_n4741 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][14] regset[24][14] $abc$24881$new_n4742 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4744 regset[31][14] regset[27][14] $abc$24881$new_n4743 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][14] regset[26][14] $abc$24881$new_n4744 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4746 regset[23][14] regset[19][14] $abc$24881$new_n4745 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][14] regset[18][14] $abc$24881$new_n4746 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4748 regset[5][14] regset[1][14] $abc$24881$new_n4747 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][14] regset[0][14] $abc$24881$new_n4748 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4754 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][16] regset[18][16] $abc$24881$new_n4753 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][16] regset[19][16] $abc$24881$new_n4754 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4756 regset[21][16] regset[20][16] $abc$24881$new_n4755 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][16] regset[16][16] $abc$24881$new_n4756 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4758 regset[29][16] regset[25][16] $abc$24881$new_n4757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][16] regset[24][16] $abc$24881$new_n4758 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4760 regset[31][16] regset[27][16] $abc$24881$new_n4759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][16] regset[26][16] $abc$24881$new_n4760 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4762 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4764 $abc$24881$new_n4766 $abc$24881$new_n4761 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4763 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][16] regset[11][16] $abc$24881$new_n4762 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][16] regset[10][16] $abc$24881$new_n4763 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4765 regset[13][16] regset[12][16] $abc$24881$new_n4764 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][16] regset[8][16] $abc$24881$new_n4765 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4767 regset[5][16] regset[1][16] $abc$24881$new_n4766 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][16] regset[0][16] $abc$24881$new_n4767 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4769 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][16] regset[2][16] $abc$24881$new_n4768 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][16] regset[3][16] $abc$24881$new_n4769 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4775 $abc$24881$new_n4777 $abc$24881$new_n4779 $abc$24881$new_n4774 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4776 regset[13][15] regset[9][15] $abc$24881$new_n4775 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][15] regset[8][15] $abc$24881$new_n4776 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4778 regset[7][15] regset[3][15] $abc$24881$new_n4777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][15] regset[2][15] $abc$24881$new_n4778 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4780 regset[5][15] regset[1][15] $abc$24881$new_n4779 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][15] regset[0][15] $abc$24881$new_n4780 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4782 regset[15][15] regset[11][15] $abc$24881$new_n4781 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][15] regset[10][15] $abc$24881$new_n4782 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4785 $abc$24881$new_n4787 $abc$24881$new_n4784 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4786 regset[31][15] regset[27][15] $abc$24881$new_n4785 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][15] regset[26][15] $abc$24881$new_n4786 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4788 regset[29][15] regset[25][15] $abc$24881$new_n4787 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][15] regset[24][15] $abc$24881$new_n4788 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4790 regset[23][15] regset[19][15] $abc$24881$new_n4789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][15] regset[18][15] $abc$24881$new_n4790 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4792 regset[21][15] regset[17][15] $abc$24881$new_n4791 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][15] regset[16][15] $abc$24881$new_n4792 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4800 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][17] regset[18][17] $abc$24881$new_n4799 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][17] regset[19][17] $abc$24881$new_n4800 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4802 regset[21][17] regset[20][17] $abc$24881$new_n4801 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][17] regset[16][17] $abc$24881$new_n4802 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4804 regset[29][17] regset[25][17] $abc$24881$new_n4803 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][17] regset[24][17] $abc$24881$new_n4804 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4806 regset[31][17] regset[27][17] $abc$24881$new_n4805 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][17] regset[26][17] $abc$24881$new_n4806 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4808 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4810 $abc$24881$new_n4812 $abc$24881$new_n4807 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4809 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][17] regset[11][17] $abc$24881$new_n4808 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][17] regset[10][17] $abc$24881$new_n4809 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4811 regset[13][17] regset[12][17] $abc$24881$new_n4810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][17] regset[8][17] $abc$24881$new_n4811 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4813 regset[5][17] regset[1][17] $abc$24881$new_n4812 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][17] regset[0][17] $abc$24881$new_n4813 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4815 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][17] regset[2][17] $abc$24881$new_n4814 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][17] regset[3][17] $abc$24881$new_n4815 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4818 $abc$24881$new_n4368 $abc$24881$new_n3769 $abc$24881$new_n4817 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4819 $abc$24881$new_n4826 $abc$24881$new_n4349 $abc$24881$new_n4836 $abc$24881$new_n4818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4820 $abc$24881$new_n4822 $abc$24881$new_n4824 $abc$24881$new_n4819 +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4821 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][18] regset[10][18] $abc$24881$new_n4820 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][18] regset[11][18] $abc$24881$new_n4821 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4823 regset[13][18] regset[9][18] $abc$24881$new_n4822 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][18] regset[8][18] $abc$24881$new_n4823 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4825 regset[7][18] regset[3][18] $abc$24881$new_n4824 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][18] regset[2][18] $abc$24881$new_n4825 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4827 $abc$24881$new_n4834 $abc$24881$new_n4356 $abc$24881$new_n4826 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4828 $abc$24881$new_n4830 $abc$24881$new_n4832 $abc$24881$new_n4827 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4829 regset[21][18] regset[17][18] $abc$24881$new_n4828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][18] regset[16][18] $abc$24881$new_n4829 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4831 regset[29][18] regset[25][18] $abc$24881$new_n4830 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][18] regset[24][18] $abc$24881$new_n4831 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4833 regset[31][18] regset[27][18] $abc$24881$new_n4832 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][18] regset[26][18] $abc$24881$new_n4833 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4835 regset[23][18] regset[19][18] $abc$24881$new_n4834 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][18] regset[18][18] $abc$24881$new_n4835 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4837 regset[5][18] regset[1][18] $abc$24881$new_n4836 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][18] regset[0][18] $abc$24881$new_n4837 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4840 $abc$24881$new_n4368 $abc$24881$new_n3763 $abc$24881$new_n4839 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4843 $abc$24881$new_n4841 $abc$24881$new_n4852 $abc$24881$new_n4850 $abc$24881$new_n4840 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4842 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][19] regset[2][19] $abc$24881$new_n4841 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][19] regset[3][19] $abc$24881$new_n4842 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4844 $abc$24881$new_n4846 $abc$24881$new_n4848 $abc$24881$new_n4843 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4845 regset[5][19] regset[4][19] $abc$24881$new_n4844 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[1][19] regset[0][19] $abc$24881$new_n4845 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4847 regset[15][19] regset[11][19] $abc$24881$new_n4846 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][19] regset[10][19] $abc$24881$new_n4847 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4849 regset[13][19] regset[9][19] $abc$24881$new_n4848 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][19] regset[8][19] $abc$24881$new_n4849 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4851 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[31][19] regset[27][19] $abc$24881$new_n4850 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[30][19] regset[26][19] $abc$24881$new_n4851 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4853 $abc$24881$new_n4855 $abc$24881$new_n4857 $abc$24881$new_n4852 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4854 regset[29][19] regset[25][19] $abc$24881$new_n4853 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][19] regset[24][19] $abc$24881$new_n4854 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4856 regset[23][19] regset[19][19] $abc$24881$new_n4855 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][19] regset[18][19] $abc$24881$new_n4856 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4858 regset[21][19] regset[17][19] $abc$24881$new_n4857 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][19] regset[16][19] $abc$24881$new_n4858 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4861 $abc$24881$new_n4368 $abc$24881$new_n3757 $abc$24881$new_n4860 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4864 $abc$24881$new_n4862 $abc$24881$new_n4873 $abc$24881$new_n4871 $abc$24881$new_n4861 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4863 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[15][20] regset[11][20] $abc$24881$new_n4862 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4069 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[14][20] regset[10][20] $abc$24881$new_n4863 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4865 $abc$24881$new_n4867 $abc$24881$new_n4869 $abc$24881$new_n4864 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4866 regset[13][20] regset[9][20] $abc$24881$new_n4865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][20] regset[8][20] $abc$24881$new_n4866 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4868 regset[7][20] regset[3][20] $abc$24881$new_n4867 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][20] regset[2][20] $abc$24881$new_n4868 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4870 regset[5][20] regset[1][20] $abc$24881$new_n4869 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][20] regset[0][20] $abc$24881$new_n4870 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4872 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][20] regset[18][20] $abc$24881$new_n4871 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][20] regset[19][20] $abc$24881$new_n4872 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4874 $abc$24881$new_n4876 $abc$24881$new_n4878 $abc$24881$new_n4873 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4875 regset[21][20] regset[20][20] $abc$24881$new_n4874 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][20] regset[16][20] $abc$24881$new_n4875 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4877 regset[31][20] regset[27][20] $abc$24881$new_n4876 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][20] regset[26][20] $abc$24881$new_n4877 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4879 regset[29][20] regset[25][20] $abc$24881$new_n4878 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][20] regset[24][20] $abc$24881$new_n4879 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4885 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4887 $abc$24881$new_n4889 $abc$24881$new_n4884 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names $abc$24881$new_n4886 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[20][21] regset[16][21] $abc$24881$new_n4885 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][21] regset[17][21] $abc$24881$new_n4886 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4888 regset[29][21] regset[25][21] $abc$24881$new_n4887 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][21] regset[24][21] $abc$24881$new_n4888 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4890 regset[31][21] regset[27][21] $abc$24881$new_n4889 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][21] regset[26][21] $abc$24881$new_n4890 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] $abc$24881$new_n4894 $abc$24881$new_n4901 instruction_decoder.o_dcdB[3] $abc$24881$new_n4899 $abc$24881$new_n4893 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4895 $abc$24881$new_n4897 $abc$24881$new_n4898 $abc$24881$new_n4894 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4896 regset[13][21] regset[9][21] $abc$24881$new_n4895 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][21] regset[8][21] $abc$24881$new_n4896 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[2] regset[4][21] regset[0][21] $abc$24881$new_n4897 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] regset[5][21] regset[1][21] $abc$24881$new_n4898 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4900 regset[15][21] regset[11][21] $abc$24881$new_n4899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][21] regset[10][21] $abc$24881$new_n4900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4902 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[6][21] regset[2][21] $abc$24881$new_n4901 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[7][21] regset[3][21] $abc$24881$new_n4902 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n4905 $abc$24881$new_n4368 $abc$24881$new_n3747 $abc$24881$new_n4904 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4906 $abc$24881$new_n4913 $abc$24881$new_n4356 $abc$24881$new_n4923 $abc$24881$new_n4905 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4907 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4909 $abc$24881$new_n4911 $abc$24881$new_n4906 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n4908 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][22] regset[0][22] $abc$24881$new_n4907 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4349 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][22] regset[1][22] $abc$24881$new_n4908 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4910 regset[15][22] regset[11][22] $abc$24881$new_n4909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][22] regset[10][22] $abc$24881$new_n4910 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4912 regset[13][22] regset[9][22] $abc$24881$new_n4911 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][22] regset[8][22] $abc$24881$new_n4912 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4914 $abc$24881$new_n4921 $abc$24881$new_n4069 $abc$24881$new_n4913 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4915 $abc$24881$new_n4917 $abc$24881$new_n4919 $abc$24881$new_n4914 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4916 regset[21][22] regset[17][22] $abc$24881$new_n4915 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][22] regset[16][22] $abc$24881$new_n4916 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4918 regset[22][22] regset[18][22] $abc$24881$new_n4917 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[23][22] regset[19][22] $abc$24881$new_n4918 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4920 regset[29][22] regset[25][22] $abc$24881$new_n4919 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][22] regset[24][22] $abc$24881$new_n4920 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4922 regset[31][22] regset[27][22] $abc$24881$new_n4921 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][22] regset[26][22] $abc$24881$new_n4922 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4924 regset[7][22] regset[3][22] $abc$24881$new_n4923 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][22] regset[2][22] $abc$24881$new_n4924 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n4925 +00 1 +11 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4930 $abc$24881$new_n4932 $abc$24881$new_n4934 $abc$24881$new_n4929 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4931 regset[23][24] regset[19][24] $abc$24881$new_n4930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][24] regset[18][24] $abc$24881$new_n4931 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4933 regset[21][24] regset[17][24] $abc$24881$new_n4932 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][24] regset[16][24] $abc$24881$new_n4933 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4935 regset[29][24] regset[28][24] $abc$24881$new_n4934 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][24] regset[24][24] $abc$24881$new_n4935 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4937 regset[31][24] regset[30][24] $abc$24881$new_n4936 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][24] regset[26][24] $abc$24881$new_n4937 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4940 $abc$24881$new_n4942 $abc$24881$new_n4944 $abc$24881$new_n4939 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4941 regset[7][24] regset[3][24] $abc$24881$new_n4940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][24] regset[2][24] $abc$24881$new_n4941 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4943 regset[5][24] regset[1][24] $abc$24881$new_n4942 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][24] regset[0][24] $abc$24881$new_n4943 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4945 regset[13][24] regset[9][24] $abc$24881$new_n4944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][24] regset[8][24] $abc$24881$new_n4945 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4947 regset[15][24] regset[11][24] $abc$24881$new_n4946 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][24] regset[10][24] $abc$24881$new_n4947 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9524 dcd_I[31] $abc$24881$new_n4948 +10 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4953 $abc$24881$new_n4955 $abc$24881$new_n4957 $abc$24881$new_n4952 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4954 regset[23][23] regset[19][23] $abc$24881$new_n4953 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][23] regset[18][23] $abc$24881$new_n4954 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4956 regset[21][23] regset[17][23] $abc$24881$new_n4955 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][23] regset[16][23] $abc$24881$new_n4956 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4958 regset[29][23] regset[28][23] $abc$24881$new_n4957 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][23] regset[24][23] $abc$24881$new_n4958 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4960 regset[31][23] regset[30][23] $abc$24881$new_n4959 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][23] regset[26][23] $abc$24881$new_n4960 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4963 $abc$24881$new_n4965 $abc$24881$new_n4967 $abc$24881$new_n4962 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4964 regset[7][23] regset[3][23] $abc$24881$new_n4963 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][23] regset[2][23] $abc$24881$new_n4964 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4966 regset[5][23] regset[1][23] $abc$24881$new_n4965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][23] regset[0][23] $abc$24881$new_n4966 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4968 regset[13][23] regset[9][23] $abc$24881$new_n4967 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][23] regset[8][23] $abc$24881$new_n4968 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4970 regset[15][23] regset[11][23] $abc$24881$new_n4969 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][23] regset[10][23] $abc$24881$new_n4970 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n4971 +10 1 +.names dcd_I[31] $abc$24881$new_n9527 $abc$24881$new_n4972 +00 1 +11 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4977 $abc$24881$new_n4979 $abc$24881$new_n4981 $abc$24881$new_n4976 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4978 regset[23][25] regset[19][25] $abc$24881$new_n4977 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][25] regset[18][25] $abc$24881$new_n4978 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4980 regset[21][25] regset[17][25] $abc$24881$new_n4979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][25] regset[16][25] $abc$24881$new_n4980 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4982 regset[29][25] regset[28][25] $abc$24881$new_n4981 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][25] regset[24][25] $abc$24881$new_n4982 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n4984 regset[31][25] regset[30][25] $abc$24881$new_n4983 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][25] regset[26][25] $abc$24881$new_n4984 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4987 $abc$24881$new_n4989 $abc$24881$new_n4991 $abc$24881$new_n4986 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4988 regset[7][25] regset[3][25] $abc$24881$new_n4987 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][25] regset[2][25] $abc$24881$new_n4988 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4990 regset[5][25] regset[1][25] $abc$24881$new_n4989 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][25] regset[0][25] $abc$24881$new_n4990 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4992 regset[13][25] regset[9][25] $abc$24881$new_n4991 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][25] regset[8][25] $abc$24881$new_n4992 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n4994 regset[15][25] regset[11][25] $abc$24881$new_n4993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][25] regset[10][25] $abc$24881$new_n4994 +001 1 +011 1 +110 1 +111 1 +.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n4996 $abc$24881$new_n4995 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names dcd_I[31] $abc$24881$new_n9521 $abc$24881$new_n9527 $abc$24881$new_n4996 +000 1 +001 1 +010 1 +011 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5001 $abc$24881$new_n5003 $abc$24881$new_n5005 $abc$24881$new_n5000 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5002 regset[23][27] regset[19][27] $abc$24881$new_n5001 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[22][27] regset[18][27] $abc$24881$new_n5002 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5004 regset[21][27] regset[17][27] $abc$24881$new_n5003 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][27] regset[16][27] $abc$24881$new_n5004 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5006 regset[29][27] regset[28][27] $abc$24881$new_n5005 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[25][27] regset[24][27] $abc$24881$new_n5006 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5008 regset[31][27] regset[30][27] $abc$24881$new_n5007 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[27][27] regset[26][27] $abc$24881$new_n5008 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5011 $abc$24881$new_n5013 $abc$24881$new_n5015 $abc$24881$new_n5010 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5012 regset[15][27] regset[11][27] $abc$24881$new_n5011 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[14][27] regset[10][27] $abc$24881$new_n5012 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5014 regset[13][27] regset[9][27] $abc$24881$new_n5013 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[12][27] regset[8][27] $abc$24881$new_n5014 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5016 regset[5][27] regset[1][27] $abc$24881$new_n5015 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][27] regset[0][27] $abc$24881$new_n5016 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5018 regset[7][27] regset[3][27] $abc$24881$new_n5017 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][27] regset[2][27] $abc$24881$new_n5018 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5023 $abc$24881$new_n5025 $abc$24881$new_n5027 $abc$24881$new_n5022 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5024 regset[13][26] regset[9][26] $abc$24881$new_n5023 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][26] regset[8][26] $abc$24881$new_n5024 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5026 regset[7][26] regset[3][26] $abc$24881$new_n5025 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][26] regset[2][26] $abc$24881$new_n5026 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5028 regset[5][26] regset[1][26] $abc$24881$new_n5027 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][26] regset[0][26] $abc$24881$new_n5028 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5030 regset[15][26] regset[11][26] $abc$24881$new_n5029 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][26] regset[10][26] $abc$24881$new_n5030 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5033 $abc$24881$new_n5035 $abc$24881$new_n5032 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5034 regset[31][26] regset[27][26] $abc$24881$new_n5033 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][26] regset[26][26] $abc$24881$new_n5034 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5036 regset[29][26] regset[25][26] $abc$24881$new_n5035 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][26] regset[24][26] $abc$24881$new_n5036 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5038 regset[23][26] regset[19][26] $abc$24881$new_n5037 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][26] regset[18][26] $abc$24881$new_n5038 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5040 regset[21][26] regset[17][26] $abc$24881$new_n5039 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][26] regset[16][26] $abc$24881$new_n5040 +000 1 +010 1 +100 1 +101 1 +.names dcd_I[31] $abc$24881$new_n9533 $abc$24881$new_n9530 $abc$24881$new_n5041 +000 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5046 regset[31][28] regset[27][28] $abc$24881$new_n5045 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][28] regset[26][28] $abc$24881$new_n5046 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5049 regset[29][28] regset[25][28] $abc$24881$new_n5048 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][28] regset[24][28] $abc$24881$new_n5049 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5051 regset[21][28] regset[17][28] $abc$24881$new_n5050 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][28] regset[16][28] $abc$24881$new_n5051 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5053 regset[23][28] regset[19][28] $abc$24881$new_n5052 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][28] regset[18][28] $abc$24881$new_n5053 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5056 regset[7][28] regset[3][28] $abc$24881$new_n5055 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][28] regset[2][28] $abc$24881$new_n5056 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5059 regset[15][28] regset[11][28] $abc$24881$new_n5058 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][28] regset[10][28] $abc$24881$new_n5059 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5062 regset[13][28] regset[9][28] $abc$24881$new_n5061 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][28] regset[8][28] $abc$24881$new_n5062 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5064 regset[5][28] regset[1][28] $abc$24881$new_n5063 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][28] regset[0][28] $abc$24881$new_n5064 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5065 +10 1 +.names $abc$24881$new_n4029 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$new_n5066 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names dcd_rB dcd_Bpc $abc$24881$new_n5067 +11 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5073 regset[7][29] regset[3][29] $abc$24881$new_n5072 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][29] regset[2][29] $abc$24881$new_n5073 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5075 regset[13][29] regset[9][29] $abc$24881$new_n5074 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][29] regset[8][29] $abc$24881$new_n5075 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5077 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[4][29] regset[0][29] $abc$24881$new_n5076 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[5][29] regset[1][29] $abc$24881$new_n5077 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5079 regset[15][29] regset[11][29] $abc$24881$new_n5078 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][29] regset[10][29] $abc$24881$new_n5079 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5081 instruction_decoder.o_dcdB[3] $abc$24881$new_n5089 $abc$24881$new_n5088 instruction_decoder.o_dcdB[1] $abc$24881$new_n5080 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5082 $abc$24881$new_n5084 $abc$24881$new_n5086 $abc$24881$new_n5081 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n5083 regset[23][29] regset[22][29] $abc$24881$new_n5082 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[19][29] regset[18][29] $abc$24881$new_n5083 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5085 regset[21][29] regset[17][29] $abc$24881$new_n5084 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[20][29] regset[16][29] $abc$24881$new_n5085 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5087 regset[31][29] regset[27][29] $abc$24881$new_n5086 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][29] regset[26][29] $abc$24881$new_n5087 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[28][29] regset[24][29] $abc$24881$new_n5088 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][29] regset[25][29] $abc$24881$new_n5089 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n3702 $abc$24881$new_n4368 $abc$24881$new_n4519 $abc$24881$new_n5091 $abc$24881$new_n5101 $abc$24881$new_n5090 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5092 instruction_decoder.o_dcdB[4] $abc$24881$new_n5099 instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n5091 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5093 $abc$24881$new_n5095 $abc$24881$new_n5097 $abc$24881$new_n5092 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5094 regset[5][30] regset[1][30] $abc$24881$new_n5093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[4][30] regset[0][30] $abc$24881$new_n5094 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5096 regset[15][30] regset[11][30] $abc$24881$new_n5095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[14][30] regset[10][30] $abc$24881$new_n5096 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5098 regset[7][30] regset[3][30] $abc$24881$new_n5097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[6][30] regset[2][30] $abc$24881$new_n5098 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5100 regset[13][30] regset[9][30] $abc$24881$new_n5099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[12][30] regset[8][30] $abc$24881$new_n5100 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n5102 $abc$24881$new_n5109 $abc$24881$new_n4349 $abc$24881$new_n5101 +1100 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5103 $abc$24881$new_n5105 $abc$24881$new_n5107 $abc$24881$new_n5102 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5104 regset[31][30] regset[27][30] $abc$24881$new_n5103 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[30][30] regset[26][30] $abc$24881$new_n5104 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5106 regset[29][30] regset[25][30] $abc$24881$new_n5105 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[28][30] regset[24][30] $abc$24881$new_n5106 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5108 regset[23][30] regset[19][30] $abc$24881$new_n5107 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[22][30] regset[18][30] $abc$24881$new_n5108 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n5110 regset[21][30] regset[17][30] $abc$24881$new_n5109 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[2] regset[20][30] regset[16][30] $abc$24881$new_n5110 +000 1 +010 1 +100 1 +101 1 +.names dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5144 $abc$24881$new_n5114 $abc$24881$new_n5113 +00000 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[31] $abc$24881$new_n5115 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5114 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[21] $abc$24881$new_n5116 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5115 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n5143 dcd_I[19] dcd_I[20] $abc$24881$new_n5142 $abc$24881$new_n5117 $abc$24881$new_n5116 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5141 dcd_I[17] dcd_I[18] $abc$24881$new_n5140 $abc$24881$new_n5118 $abc$24881$new_n5117 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5139 dcd_I[15] dcd_I[16] $abc$24881$new_n5138 $abc$24881$new_n5119 $abc$24881$new_n5118 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5137 dcd_I[13] dcd_I[14] $abc$24881$new_n5136 $abc$24881$new_n5120 $abc$24881$new_n5119 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5135 dcd_I[11] dcd_I[12] $abc$24881$new_n5134 $abc$24881$new_n5121 $abc$24881$new_n5120 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5133 dcd_I[9] dcd_I[10] $abc$24881$new_n5132 $abc$24881$new_n5122 $abc$24881$new_n5121 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5131 dcd_I[7] dcd_I[8] $abc$24881$new_n5130 $abc$24881$new_n5123 $abc$24881$new_n5122 +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n4068 dcd_I[6] $abc$24881$new_n5124 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5123 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[5] $abc$24881$new_n5125 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5124 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[4] $abc$24881$new_n5126 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5125 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[3] $abc$24881$new_n5127 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5126 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[2] $abc$24881$new_n5128 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5127 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n4068 dcd_I[1] $abc$24881$new_n5129 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5128 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11010 1 +.names dcd_I[0] SET_GIE.r_gie instruction_decoder.o_dcdB[4] instruction_decoder.o_pc[2] SET_USER_PC.r_upc[2] $abc$24881$new_n5129 +10010 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n5130 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n5131 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n5132 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n5133 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n5134 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n5135 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5136 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n5137 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5138 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5139 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n5140 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5141 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5142 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5143 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n5144 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n5145 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5146 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n5147 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n5148 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4068 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5149 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3702 r_op_Bv[30] o_mem_addr[30] +001 1 +011 1 +100 1 +101 1 +.names OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n5151 +111 1 +.names $abc$24881$new_n5153 $abc$24881$new_n5154 $abc$24881$new_n3700 dbgv i_mem_valid $abc$24881$new_n5152 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[2] i_mem_wreg[2] alu_reg[2] $abc$24881$new_n5153 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names OP_REG_ADVANEC.r_op_Bid[1] i_mem_valid alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5154 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5157 $abc$24881$new_n5156 OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$new_n3697 $abc$24881$new_n5158 $abc$24881$new_n5155 +11010 1 +11100 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[3] i_mem_wreg[3] alu_reg[3] $abc$24881$new_n5156 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[4] i_mem_wreg[4] alu_reg[4] $abc$24881$new_n5157 +0000 1 +0010 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names i_mem_valid OP_REG_ADVANEC.r_op_Bid[1] alu_reg[1] i_mem_wreg[1] $abc$24881$new_n5158 +0010 1 +0011 1 +1001 1 +1011 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3708 r_op_Bv[29] o_mem_addr[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4995 $abc$24881$new_n4329 $abc$24881$new_n5041 $abc$24881$new_n5166 +100 1 +101 1 +110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3714 r_op_Bv[28] o_mem_addr[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5170 o_mem_addr[27] $abc$24881$new_n5067 $abc$24881$new_n5172 $abc$24881$auto$rtlil.cc:2693:MuxGate$22930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9530 dcd_I[31] $abc$24881$new_n5067 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5170 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +10000 1 +11011 1 +.names $abc$24881$new_n4996 $abc$24881$new_n4329 $abc$24881$new_n5171 +10 1 +.names dcd_I[31] $abc$24881$new_n5144 $abc$24881$new_n5146 $abc$24881$new_n5145 $abc$24881$new_n5114 $abc$24881$new_n5172 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3719 r_op_Bv[27] o_mem_addr[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n9548 $abc$24881$new_n3725 r_op_Bv[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$22932 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5066 $abc$24881$new_n5177 +11 1 +.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n5146 $abc$24881$new_n5114 $abc$24881$new_n5067 $abc$24881$new_n5182 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 o_mem_addr[24] $abc$24881$new_n5185 $abc$24881$new_n5186 $abc$24881$auto$rtlil.cc:2693:MuxGate$22936 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n4925 $abc$24881$new_n4948 $abc$24881$new_n4971 $abc$24881$new_n9843 $abc$24881$new_n5185 +10000 1 +10010 1 +10011 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5187 $abc$24881$new_n5115 $abc$24881$new_n5186 +100 1 +111 1 +.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[24] instruction_decoder.o_pc[24] $abc$24881$new_n5187 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3735 r_op_Bv[24] o_mem_addr[24] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[21] $abc$24881$new_n5116 $abc$24881$new_n4068 SET_USER_PC.r_upc[23] instruction_decoder.o_pc[23] $abc$24881$new_n5192 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names dcd_I[20] $abc$24881$new_n5142 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5196 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3747 r_op_Bv[22] o_mem_addr[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5177 dcd_I[19] $abc$24881$new_n5143 $abc$24881$new_n5117 $abc$24881$new_n5201 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[18] $abc$24881$new_n5140 dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5205 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3757 r_op_Bv[20] o_mem_addr[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[19] $abc$24881$new_n5208 $abc$24881$new_n5209 $abc$24881$auto$rtlil.cc:2693:MuxGate$22946 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names dcd_I[19] $abc$24881$new_n4839 $abc$24881$new_n9845 $abc$24881$new_n5208 +001 1 +010 1 +100 1 +111 1 +.names dcd_I[17] $abc$24881$new_n5141 $abc$24881$new_n5118 $abc$24881$new_n5209 +000 1 +011 1 +101 1 +110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3763 r_op_Bv[19] o_mem_addr[19] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[16] $abc$24881$new_n5138 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5214 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3769 r_op_Bv[18] o_mem_addr[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5177 dcd_I[15] $abc$24881$new_n5139 $abc$24881$new_n5119 $abc$24881$new_n5219 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[14] $abc$24881$new_n5136 dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5223 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names dcd_I[16] $abc$24881$new_n9508 $abc$24881$new_n5224 +00 1 +11 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3779 r_op_Bv[16] o_mem_addr[16] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[13] $abc$24881$new_n5137 $abc$24881$new_n5120 $abc$24881$new_n5229 +001 1 +010 1 +100 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5231 o_mem_addr[14] $abc$24881$new_n5067 $abc$24881$new_n5233 $abc$24881$auto$rtlil.cc:2693:MuxGate$22956 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5065 dcd_I[14] $abc$24881$new_n9505 $abc$24881$new_n5232 $abc$24881$new_n5231 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$24881$new_n9502 dcd_I[13] $abc$24881$new_n9847 $abc$24881$new_n5232 +001 1 +100 1 +101 1 +111 1 +.names dcd_I[12] $abc$24881$new_n5134 dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5233 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3790 r_op_Bv[14] o_mem_addr[14] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[11] $abc$24881$new_n5135 $abc$24881$new_n5121 $abc$24881$new_n5238 +001 1 +010 1 +100 1 +111 1 +.names dcd_I[10] $abc$24881$new_n5132 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5242 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3800 r_op_Bv[12] o_mem_addr[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5245 $abc$24881$new_n3805 r_op_Bv[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$22962 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5246 dcd_I[9] $abc$24881$new_n5133 $abc$24881$new_n5122 $abc$24881$new_n5177 $abc$24881$new_n5245 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5065 dcd_I[11] $abc$24881$new_n4660 $abc$24881$new_n4336 $abc$24881$new_n5246 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[8] $abc$24881$new_n5130 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5250 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3810 r_op_Bv[10] o_mem_addr[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5066 o_mem_addr[9] $abc$24881$new_n5253 $abc$24881$new_n5254 $abc$24881$auto$rtlil.cc:2693:MuxGate$22966 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5065 $abc$24881$new_n4337 $abc$24881$new_n4658 $abc$24881$new_n4635 $abc$24881$new_n5253 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n5067 dcd_I[7] $abc$24881$new_n5131 $abc$24881$new_n5123 $abc$24881$new_n5254 +1001 1 +1010 1 +1100 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3815 r_op_Bv[9] o_mem_addr[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5257 $abc$24881$new_n3820 r_op_Bv[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$22968 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5259 $abc$24881$new_n5258 $abc$24881$new_n5260 $abc$24881$new_n5257 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4566 $abc$24881$new_n4338 $abc$24881$new_n4590 $abc$24881$new_n5258 +001 1 +010 1 +011 1 +.names dcd_I[8] $abc$24881$new_n4591 $abc$24881$new_n5259 +00 1 +11 1 +.names dcd_I[6] $abc$24881$new_n5124 $abc$24881$new_n4068 SET_USER_PC.r_upc[8] instruction_decoder.o_pc[8] $abc$24881$new_n5260 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5262 $abc$24881$new_n3825 r_op_Bv[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$22970 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5263 $abc$24881$new_n5264 $abc$24881$new_n5125 $abc$24881$new_n5177 $abc$24881$new_n5262 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n5065 dcd_I[7] $abc$24881$new_n9493 $abc$24881$new_n4338 $abc$24881$new_n5263 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[5] $abc$24881$new_n4068 SET_USER_PC.r_upc[7] instruction_decoder.o_pc[7] $abc$24881$new_n5264 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5266 $abc$24881$new_n3832 r_op_Bv[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$22972 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n5268 $abc$24881$new_n5267 $abc$24881$new_n5269 $abc$24881$new_n5266 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n9489 dcd_I[5] $abc$24881$new_n4339 $abc$24881$new_n5267 +001 1 +100 1 +101 1 +111 1 +.names dcd_I[6] $abc$24881$new_n9873 $abc$24881$new_n5268 +00 1 +11 1 +.names dcd_I[4] $abc$24881$new_n5126 $abc$24881$new_n4068 SET_USER_PC.r_upc[6] instruction_decoder.o_pc[6] $abc$24881$new_n5269 +00000 1 +00001 1 +00100 1 +00110 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5271 $abc$24881$new_n3838 r_op_Bv[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22974 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5272 $abc$24881$new_n5273 $abc$24881$new_n5127 $abc$24881$new_n5177 $abc$24881$new_n5271 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n5065 dcd_I[5] $abc$24881$new_n9489 $abc$24881$new_n4339 $abc$24881$new_n5272 +1000 1 +1011 1 +1101 1 +1110 1 +.names dcd_I[3] $abc$24881$new_n4068 SET_USER_PC.r_upc[5] instruction_decoder.o_pc[5] $abc$24881$new_n5273 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n4406 dcd_I[3] $abc$24881$new_n9436 $abc$24881$new_n5276 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3843 r_op_Bv[4] o_mem_addr[4] +001 1 +011 1 +100 1 +101 1 +.names dcd_I[2] $abc$24881$new_n4068 SET_USER_PC.r_upc[4] instruction_decoder.o_pc[4] $abc$24881$new_n5279 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5281 o_mem_addr[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22978 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5129 $abc$24881$new_n5283 $abc$24881$new_n5282 $abc$24881$new_n5281 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names dcd_I[3] $abc$24881$new_n4406 $abc$24881$new_n9436 $abc$24881$new_n5282 +000 1 +011 1 +101 1 +110 1 +.names dcd_I[1] $abc$24881$new_n4068 SET_USER_PC.r_upc[3] instruction_decoder.o_pc[3] $abc$24881$new_n5283 +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names r_op_Bv[3] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3848 o_mem_addr[3] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n5286 $abc$24881$new_n3853 r_op_Bv[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22980 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5287 $abc$24881$new_n5065 $abc$24881$new_n5288 $abc$24881$new_n5286 +000 1 +001 1 +011 1 +.names $abc$24881$new_n5177 dcd_I[0] $abc$24881$new_n4068 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n5287 +10000 1 +10001 1 +10100 1 +10110 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names dcd_I[2] $abc$24881$new_n9442 dcd_I[1] $abc$24881$new_n4471 $abc$24881$new_n4439 $abc$24881$new_n5288 +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5290 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22982 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5067 $abc$24881$new_n4471 $abc$24881$new_n5291 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4068 $abc$24881$new_n5290 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names dcd_I[1] $abc$24881$new_n4439 $abc$24881$new_n5291 +00 1 +11 1 +.names r_op_Bv[1] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3859 o_mem_addr[1] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 dcd_I[0] $abc$24881$new_n5294 $abc$24881$new_n5067 o_mem_addr[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22984 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4473 $abc$24881$new_n4500 $abc$24881$new_n4472 $abc$24881$new_n4474 $abc$24881$new_n5294 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names r_op_Bv[0] OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5155 $abc$24881$new_n5152 $abc$24881$new_n3863 o_mem_addr[0] +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] r_op_F[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$22986 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] r_op_F[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22988 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] r_op_F[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22990 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] r_op_F[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$22992 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] r_op_F[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$22994 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] r_op_F[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$22996 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] instruction_decoder.o_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$22998 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23000 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] instruction_decoder.o_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23002 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] instruction_decoder.o_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23004 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] instruction_decoder.o_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23006 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] instruction_decoder.o_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23008 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] instruction_decoder.o_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23010 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] instruction_decoder.o_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23012 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] instruction_decoder.o_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23014 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] instruction_decoder.o_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23016 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] instruction_decoder.o_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23018 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] instruction_decoder.o_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23020 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] instruction_decoder.o_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] instruction_decoder.o_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] instruction_decoder.o_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23026 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] instruction_decoder.o_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23028 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] instruction_decoder.o_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23030 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] instruction_decoder.o_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23032 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] instruction_decoder.o_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23034 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] instruction_decoder.o_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23036 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] instruction_decoder.o_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] instruction_decoder.o_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23040 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] instruction_decoder.o_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23042 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] instruction_decoder.o_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23044 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] instruction_decoder.o_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23046 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] instruction_decoder.o_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23048 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] instruction_decoder.o_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23050 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] instruction_decoder.o_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23052 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] instruction_decoder.o_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23054 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 wr_index[0] op_valid_div op_valid_mem $abc$24881$auto$rtlil.cc:2693:MuxGate$23056 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3963 GEN_ALU_PC.r_alu_pc[30] ipc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23058 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4035 $abc$24881$new_n3694 $abc$24881$new_n3697 $abc$24881$new_n5333 +110 1 +.names SET_GIE.r_gie GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n3961 $abc$24881$new_n5334 +000 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3965 GEN_ALU_PC.r_alu_pc[29] ipc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23060 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3967 GEN_ALU_PC.r_alu_pc[28] ipc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23062 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3969 GEN_ALU_PC.r_alu_pc[27] ipc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23064 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3971 GEN_ALU_PC.r_alu_pc[26] ipc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23066 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3973 GEN_ALU_PC.r_alu_pc[25] ipc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23068 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3975 GEN_ALU_PC.r_alu_pc[24] ipc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23070 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3977 GEN_ALU_PC.r_alu_pc[23] ipc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23072 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3979 GEN_ALU_PC.r_alu_pc[22] ipc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23074 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3981 GEN_ALU_PC.r_alu_pc[21] ipc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23076 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3983 GEN_ALU_PC.r_alu_pc[20] ipc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23078 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3985 GEN_ALU_PC.r_alu_pc[19] ipc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23080 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3987 GEN_ALU_PC.r_alu_pc[18] ipc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23082 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3989 GEN_ALU_PC.r_alu_pc[17] ipc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23084 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3991 GEN_ALU_PC.r_alu_pc[16] ipc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23086 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3993 GEN_ALU_PC.r_alu_pc[15] ipc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23088 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3995 GEN_ALU_PC.r_alu_pc[14] ipc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23090 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3997 GEN_ALU_PC.r_alu_pc[13] ipc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23092 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n3999 GEN_ALU_PC.r_alu_pc[12] ipc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23094 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4001 GEN_ALU_PC.r_alu_pc[11] ipc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23096 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4003 GEN_ALU_PC.r_alu_pc[10] ipc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23098 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4005 GEN_ALU_PC.r_alu_pc[9] ipc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23100 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4007 GEN_ALU_PC.r_alu_pc[8] ipc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23102 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4009 GEN_ALU_PC.r_alu_pc[7] ipc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23104 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4011 GEN_ALU_PC.r_alu_pc[6] ipc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23106 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4013 GEN_ALU_PC.r_alu_pc[5] ipc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23108 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4015 GEN_ALU_PC.r_alu_pc[4] ipc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23110 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4017 GEN_ALU_PC.r_alu_pc[3] ipc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23112 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n4019 GEN_ALU_PC.r_alu_pc[2] ipc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23114 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[3] OP_REG_ADVANEC.r_op_Bid[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23116 +001 1 +011 1 +110 1 +111 1 +.names dcd_rB $abc$24881$new_n5066 instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n5364 +1100 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[2] OP_REG_ADVANEC.r_op_Bid[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23118 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[1] OP_REG_ADVANEC.r_op_Bid[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23120 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[0] OP_REG_ADVANEC.r_op_Bid[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23122 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[3] o_mem_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23124 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[2] o_mem_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23126 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[1] o_mem_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23128 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[0] o_mem_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23130 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[3] i_dbg_wreg[3] alu_reg[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5383 alu_ce o_mem_ce $abc$24881$new_n5373 +000 1 +.names $abc$24881$new_n5375 mem_ce o_mem_ce +11 1 +.names $abc$24881$new_n5378 $abc$24881$new_n5376 r_op_F[2] $abc$24881$new_n5381 $abc$24881$new_n5375 +1100 1 +1111 1 +.names $abc$24881$new_n5377 SET_GIE.r_gie r_op_F[3] $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n5376 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names r_op_F[1] SET_GIE.r_gie r_op_F[5] $abc$24881$new_n4470 $abc$24881$new_n4468 $abc$24881$new_n5377 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names r_op_F[0] SET_GIE.r_gie r_op_F[4] $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n5378 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10110 1 +11100 1 +11101 1 +.names $abc$24881$new_n4476 $abc$24881$new_n4475 $abc$24881$new_n5379 +00 1 +.names $abc$24881$new_n4400 $abc$24881$new_n4501 flags[0] $abc$24881$new_n5380 +000 1 +010 1 +110 1 +111 1 +.names r_op_F[6] SET_GIE.r_gie $abc$24881$new_n4435 $abc$24881$new_n4438 $abc$24881$new_n5381 +1000 1 +1001 1 +1100 1 +1110 1 +.names op_valid_alu $abc$24881$new_n4031 alu_ce +11 1 +.names op_valid_div $abc$24881$new_n5375 $abc$24881$new_n4031 $abc$24881$new_n5383 +111 1 +.names i_dbg_we o_dbg_stall $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +10 1 +.names r_halted r_dbg_stall o_dbg_stall +00 1 +01 1 +11 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[2] i_dbg_wreg[2] alu_reg[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23134 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[1] i_dbg_wreg[1] alu_reg[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23136 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[0] i_dbg_wreg[0] alu_reg[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23138 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 o_mem_op[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[2] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23142 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 o_mem_op[1] dcd_opn[1] instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23146 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$24881$new_n5066 DIVIDE.thedivide.i_signed instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[0] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23150 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[30] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] o_mem_lock_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23152 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5394 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5393 +10 1 +.names $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] SET_OP_PC.r_op_pc[27] $abc$24881$new_n5394 +100 1 +.names $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] SET_OP_PC.r_op_pc[25] $abc$24881$new_n5395 +100 1 +.names $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] SET_OP_PC.r_op_pc[23] $abc$24881$new_n5396 +100 1 +.names $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] SET_OP_PC.r_op_pc[21] $abc$24881$new_n5397 +100 1 +.names $abc$24881$new_n5399 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5398 +10 1 +.names $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] SET_OP_PC.r_op_pc[18] $abc$24881$new_n5399 +100 1 +.names $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] SET_OP_PC.r_op_pc[16] $abc$24881$new_n5400 +100 1 +.names $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] SET_OP_PC.r_op_pc[14] $abc$24881$new_n5401 +100 1 +.names $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] SET_OP_PC.r_op_pc[12] $abc$24881$new_n5402 +100 1 +.names $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] SET_OP_PC.r_op_pc[10] $abc$24881$new_n5403 +100 1 +.names $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] SET_OP_PC.r_op_pc[8] $abc$24881$new_n5404 +100 1 +.names $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] SET_OP_PC.r_op_pc[6] $abc$24881$new_n5405 +100 1 +.names SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] SET_OP_PC.r_op_pc[4] $abc$24881$new_n5406 +000 1 +.names op_valid GEN_OPLOCK.r_op_lock $abc$24881$new_n5066 $abc$24881$new_n5407 +111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[29] $abc$24881$new_n5393 o_mem_lock_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23154 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[28] $abc$24881$new_n5394 o_mem_lock_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23156 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[27] $abc$24881$new_n5395 SET_OP_PC.r_op_pc[26] o_mem_lock_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23158 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[26] $abc$24881$new_n5395 o_mem_lock_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23160 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[25] $abc$24881$new_n5396 SET_OP_PC.r_op_pc[24] o_mem_lock_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23162 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[24] $abc$24881$new_n5396 o_mem_lock_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23164 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[23] $abc$24881$new_n5397 SET_OP_PC.r_op_pc[22] o_mem_lock_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23166 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[22] $abc$24881$new_n5397 o_mem_lock_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23168 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[21] $abc$24881$new_n5398 SET_OP_PC.r_op_pc[20] o_mem_lock_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23170 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[20] $abc$24881$new_n5398 o_mem_lock_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23172 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[19] $abc$24881$new_n5399 o_mem_lock_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23174 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[18] $abc$24881$new_n5400 SET_OP_PC.r_op_pc[17] o_mem_lock_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23176 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[17] $abc$24881$new_n5400 o_mem_lock_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23178 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[16] $abc$24881$new_n5401 SET_OP_PC.r_op_pc[15] o_mem_lock_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23180 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[15] $abc$24881$new_n5401 o_mem_lock_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23182 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[14] $abc$24881$new_n5402 SET_OP_PC.r_op_pc[13] o_mem_lock_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23184 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[13] $abc$24881$new_n5402 o_mem_lock_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23186 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[12] $abc$24881$new_n5403 SET_OP_PC.r_op_pc[11] o_mem_lock_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23188 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[11] $abc$24881$new_n5403 o_mem_lock_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23190 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[10] $abc$24881$new_n5404 SET_OP_PC.r_op_pc[9] o_mem_lock_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23192 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[9] $abc$24881$new_n5404 o_mem_lock_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23194 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[8] $abc$24881$new_n5405 SET_OP_PC.r_op_pc[7] o_mem_lock_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23196 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[7] $abc$24881$new_n5405 o_mem_lock_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23198 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[6] $abc$24881$new_n5406 SET_OP_PC.r_op_pc[5] o_mem_lock_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23200 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[5] $abc$24881$new_n5406 o_mem_lock_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23202 +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[4] SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23204 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] SET_OP_PC.r_op_pc[3] o_mem_lock_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23206 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[2] o_mem_lock_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23208 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5407 SET_OP_PC.r_op_pc[1] o_mem_lock_pc[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23210 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5438 $abc$24881$new_n4028 dcd_I[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23212 +000 1 +001 1 +011 1 +.names $abc$24881$new_n5443 $abc$24881$new_n5439 $abc$24881$new_n4028 $abc$24881$new_n5438 +000 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4289 $abc$24881$new_n5439 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$new_n5441 $abc$24881$new_n4283 $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n5442 $abc$24881$new_n5440 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5441 +00100 1 +01100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[1] i_pf_instruction[17] $abc$24881$new_n5442 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4266 $abc$24881$new_n4272 $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5443 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +.names $abc$24881$new_n4028 dcd_I[20] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5445 $abc$24881$auto$rtlil.cc:2693:MuxGate$23214 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4291 $abc$24881$new_n5445 +100 1 +101 1 +110 1 +.names $abc$24881$new_n4028 dcd_I[19] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5447 $abc$24881$auto$rtlil.cc:2693:MuxGate$23216 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4293 $abc$24881$new_n5447 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 dcd_I[18] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$auto$rtlil.cc:2693:MuxGate$23218 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5449 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 dcd_I[17] $abc$24881$new_n5451 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23220 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[17] $abc$24881$new_n5452 $abc$24881$new_n5451 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4281 $abc$24881$new_n4271 $abc$24881$new_n4283 $abc$24881$new_n5452 +001 1 +010 1 +011 1 +.names $abc$24881$new_n4028 dcd_I[16] $abc$24881$new_n5454 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23222 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$new_n5452 $abc$24881$new_n5455 $abc$24881$new_n5454 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[0] i_pf_instruction[16] $abc$24881$new_n5455 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 dcd_I[15] $abc$24881$new_n5457 $abc$24881$new_n4266 $abc$24881$new_n5441 $abc$24881$auto$rtlil.cc:2693:MuxGate$23224 +00000 1 +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n5452 i_pf_instruction[15] $abc$24881$new_n5457 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$24881$new_n4028 dcd_I[14] $abc$24881$new_n5459 $abc$24881$new_n5443 $abc$24881$auto$rtlil.cc:2693:MuxGate$23226 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5441 i_pf_instruction[14] $abc$24881$new_n5452 $abc$24881$new_n5459 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4028 dcd_I[13] $abc$24881$new_n5443 $abc$24881$new_n5461 $abc$24881$auto$rtlil.cc:2693:MuxGate$23228 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n4281 i_pf_instruction[12] i_pf_instruction[13] $abc$24881$new_n5461 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_I[12] $abc$24881$new_n5443 i_pf_instruction[12] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23230 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[11] $abc$24881$new_n5443 i_pf_instruction[11] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23232 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[10] $abc$24881$new_n5443 i_pf_instruction[10] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23234 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[9] $abc$24881$new_n5443 i_pf_instruction[9] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23236 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[8] $abc$24881$new_n5443 i_pf_instruction[8] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23238 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[7] $abc$24881$new_n5443 i_pf_instruction[7] $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23240 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[6] $abc$24881$new_n5469 $abc$24881$auto$rtlil.cc:2693:MuxGate$23242 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[6] $abc$24881$new_n4283 $abc$24881$new_n4287 $abc$24881$new_n5469 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4273 $abc$24881$new_n4272 $abc$24881$new_n5470 +00 1 +.names $abc$24881$new_n4028 dcd_I[5] $abc$24881$new_n5472 $abc$24881$auto$rtlil.cc:2693:MuxGate$23244 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[5] $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n5472 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 dcd_I[4] $abc$24881$new_n5474 $abc$24881$auto$rtlil.cc:2693:MuxGate$23246 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5470 i_pf_instruction[4] $abc$24881$new_n4283 $abc$24881$new_n4291 $abc$24881$new_n5474 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4028 dcd_I[3] $abc$24881$new_n5476 $abc$24881$auto$rtlil.cc:2693:MuxGate$23248 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n5477 $abc$24881$new_n5470 $abc$24881$new_n4283 $abc$24881$new_n4266 $abc$24881$new_n5476 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4266 i_pf_instruction[3] $abc$24881$new_n5470 $abc$24881$new_n4293 $abc$24881$new_n5477 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[2] i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23250 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[1] i_pf_instruction[1] $abc$24881$new_n5442 $abc$24881$auto$rtlil.cc:2693:MuxGate$23252 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4266 dcd_I[0] i_pf_instruction[0] $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23254 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 BUSLOCK.r_bus_lock[1] GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23256 +0001 1 +0010 1 +0011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[30] SET_OP_PC.r_op_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23258 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[29] SET_OP_PC.r_op_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23260 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[28] SET_OP_PC.r_op_pc[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$23262 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[27] SET_OP_PC.r_op_pc[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23264 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[26] SET_OP_PC.r_op_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23266 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[25] SET_OP_PC.r_op_pc[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23268 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[24] SET_OP_PC.r_op_pc[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23270 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[23] SET_OP_PC.r_op_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23272 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[22] SET_OP_PC.r_op_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23274 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[21] SET_OP_PC.r_op_pc[21] $abc$24881$auto$rtlil.cc:2693:MuxGate$23276 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[20] SET_OP_PC.r_op_pc[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23278 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[19] SET_OP_PC.r_op_pc[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23280 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[18] SET_OP_PC.r_op_pc[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23282 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[17] SET_OP_PC.r_op_pc[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23284 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[16] SET_OP_PC.r_op_pc[16] $abc$24881$auto$rtlil.cc:2693:MuxGate$23286 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[15] SET_OP_PC.r_op_pc[15] $abc$24881$auto$rtlil.cc:2693:MuxGate$23288 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[14] SET_OP_PC.r_op_pc[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23290 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[13] SET_OP_PC.r_op_pc[13] $abc$24881$auto$rtlil.cc:2693:MuxGate$23292 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[12] SET_OP_PC.r_op_pc[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23294 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[11] SET_OP_PC.r_op_pc[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23296 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[10] SET_OP_PC.r_op_pc[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23298 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[9] SET_OP_PC.r_op_pc[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23300 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[8] SET_OP_PC.r_op_pc[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23302 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[7] SET_OP_PC.r_op_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23304 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[6] SET_OP_PC.r_op_pc[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23306 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[5] SET_OP_PC.r_op_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23308 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[4] SET_OP_PC.r_op_pc[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23310 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[3] SET_OP_PC.r_op_pc[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23312 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[2] SET_OP_PC.r_op_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23314 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n5529 $abc$24881$new_n5512 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23318 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5512 +100 1 +.names $abc$24881$new_n5514 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5513 +10 1 +.names $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5514 +100 1 +.names $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5515 +100 1 +.names $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5516 +100 1 +.names $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5517 +100 1 +.names $abc$24881$new_n5519 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5518 +10 1 +.names $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5519 +1000 1 +.names $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5520 +10000 1 +.names $abc$24881$new_n5522 DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5521 +10 1 +.names $abc$24881$new_n5523 DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5522 +10 1 +.names $abc$24881$new_n5524 DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5523 +10 1 +.names $abc$24881$new_n5525 DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5524 +10 1 +.names $abc$24881$new_n5526 DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5525 +10 1 +.names $abc$24881$new_n5527 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5526 +10 1 +.names $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5527 +100 1 +.names DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n5528 +00 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n5530 $abc$24881$new_n5529 +10 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n5530 +11 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy $abc$24881$new_n5531 +11 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5533 DIVIDE.thedivide.r_divisor[28] o_mem_addr[28] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23320 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[28] $abc$24881$new_n5513 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5533 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[27] $abc$24881$new_n5529 $abc$24881$new_n5513 o_mem_addr[27] $abc$24881$auto$rtlil.cc:2693:MuxGate$23322 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[26] $abc$24881$new_n5529 $abc$24881$new_n5514 o_mem_addr[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23324 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3725 r_op_Bv[26] o_mem_addr[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5540 DIVIDE.thedivide.r_divisor[25] o_mem_addr[25] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23326 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[25] $abc$24881$new_n5515 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5540 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3730 r_op_Bv[25] o_mem_addr[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[24] $abc$24881$new_n5529 $abc$24881$new_n5515 o_mem_addr[24] $abc$24881$auto$rtlil.cc:2693:MuxGate$23328 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5545 DIVIDE.thedivide.r_divisor[23] o_mem_addr[23] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23330 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[23] $abc$24881$new_n5516 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5545 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3741 r_op_Bv[23] o_mem_addr[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[22] $abc$24881$new_n5529 $abc$24881$new_n5516 o_mem_addr[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23332 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5550 DIVIDE.thedivide.r_divisor[21] o_mem_addr[21] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23334 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[21] $abc$24881$new_n5517 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5550 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3752 r_op_Bv[21] o_mem_addr[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[20] $abc$24881$new_n5529 $abc$24881$new_n5517 o_mem_addr[20] $abc$24881$auto$rtlil.cc:2693:MuxGate$23336 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5555 DIVIDE.thedivide.r_divisor[19] o_mem_addr[19] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23338 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[19] $abc$24881$new_n5518 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5555 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[18] $abc$24881$new_n5529 $abc$24881$new_n5518 o_mem_addr[18] $abc$24881$auto$rtlil.cc:2693:MuxGate$23340 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[17] $abc$24881$new_n5529 $abc$24881$new_n5519 o_mem_addr[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23342 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3774 r_op_Bv[17] o_mem_addr[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5560 DIVIDE.thedivide.r_divisor[16] o_mem_addr[16] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23344 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[16] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5560 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5562 DIVIDE.thedivide.r_divisor[15] o_mem_addr[15] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23346 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n5520 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5562 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3784 r_op_Bv[15] o_mem_addr[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[14] $abc$24881$new_n5529 $abc$24881$new_n5520 o_mem_addr[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23348 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n5529 DIVIDE.thedivide.r_divisor[13] o_mem_addr[13] $abc$24881$new_n5568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23350 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[13] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5568 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3795 r_op_Bv[13] o_mem_addr[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5571 DIVIDE.thedivide.r_divisor[12] o_mem_addr[12] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23352 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[12] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5571 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 $abc$24881$new_n5573 DIVIDE.thedivide.r_divisor[11] o_mem_addr[11] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23354 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[11] $abc$24881$new_n5521 DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5573 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3805 r_op_Bv[11] o_mem_addr[11] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[10] $abc$24881$new_n5521 $abc$24881$new_n5529 o_mem_addr[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23356 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[9] $abc$24881$new_n5530 $abc$24881$new_n5522 o_mem_addr[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23358 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[8] $abc$24881$new_n5530 $abc$24881$new_n5523 o_mem_addr[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23360 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3820 r_op_Bv[8] o_mem_addr[8] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[7] $abc$24881$new_n5530 $abc$24881$new_n5524 o_mem_addr[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23362 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3825 r_op_Bv[7] o_mem_addr[7] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[6] $abc$24881$new_n5529 $abc$24881$new_n5525 o_mem_addr[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23364 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3832 r_op_Bv[6] o_mem_addr[6] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[5] $abc$24881$new_n5530 $abc$24881$new_n5526 o_mem_addr[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23366 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3838 r_op_Bv[5] o_mem_addr[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[4] $abc$24881$new_n5529 $abc$24881$new_n5527 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23368 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5529 DIVIDE.thedivide.r_busy o_mem_addr[3] DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5588 $abc$24881$auto$rtlil.cc:2693:MuxGate$23370 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[3] $abc$24881$new_n5528 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5588 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[2] $abc$24881$new_n5529 $abc$24881$new_n5528 o_mem_addr[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23372 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3853 r_op_Bv[2] o_mem_addr[2] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_divisor[1] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n5530 o_mem_addr[1] $abc$24881$auto$rtlil.cc:2693:MuxGate$23374 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names DIVIDE.thedivide.r_busy o_mem_addr[0] DIVIDE.thedivide.r_divisor[0] $abc$24881$auto$rtlil.cc:2693:MuxGate$23376 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n5595 +10 1 +.names $abc$24881$new_n5599 $abc$24881$new_n5597 instruction_decoder.o_dcdA[0] $abc$24881$new_n3697 $abc$24881$new_n5066 $abc$24881$new_n5596 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11111 1 +.names $abc$24881$new_n5598 instruction_decoder.o_dcdA[3] $abc$24881$new_n3695 $abc$24881$new_n3959 $abc$24881$new_n5597 +1010 1 +1100 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[2] $abc$24881$new_n3701 $abc$24881$new_n3694 $abc$24881$new_n5598 +0011 1 +0101 1 +1010 1 +1100 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n3698 $abc$24881$new_n5599 +01 1 +10 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[30] SET_USER_PC.r_upc[30] $abc$24881$new_n5601 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5603 $abc$24881$new_n5613 $abc$24881$new_n5618 $abc$24881$new_n5602 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5604 $abc$24881$new_n5611 $abc$24881$new_n5609 $abc$24881$new_n5603 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5605 $abc$24881$new_n5608 $abc$24881$new_n5607 $abc$24881$new_n5604 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$24881$new_n5606 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][30] regset[18][30] $abc$24881$new_n5605 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][30] regset[19][30] $abc$24881$new_n5606 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][30] regset[26][30] $abc$24881$new_n5607 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][30] regset[27][30] $abc$24881$new_n5608 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5610 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][30] regset[17][30] $abc$24881$new_n5609 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][30] regset[16][30] $abc$24881$new_n5610 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n5612 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][30] regset[24][30] $abc$24881$new_n5611 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][30] regset[25][30] $abc$24881$new_n5612 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5614 $abc$24881$new_n5616 $abc$24881$new_n5613 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5615 regset[13][30] regset[9][30] $abc$24881$new_n5614 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][30] regset[8][30] $abc$24881$new_n5615 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5617 regset[4][30] regset[0][30] $abc$24881$new_n5616 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][30] regset[1][30] $abc$24881$new_n5617 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5620 $abc$24881$new_n5619 $abc$24881$new_n5622 $abc$24881$new_n5621 $abc$24881$new_n5618 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][30] regset[6][30] $abc$24881$new_n5619 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][30] regset[2][30] $abc$24881$new_n5620 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][30] regset[7][30] $abc$24881$new_n5621 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][30] regset[3][30] $abc$24881$new_n5622 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n5066 $abc$24881$new_n3692 OP_REG_ADVANEC.r_op_rA $abc$24881$new_n5623 +000 1 +001 1 +010 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5629 $abc$24881$new_n5631 $abc$24881$new_n5633 $abc$24881$new_n5628 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5630 regset[5][29] regset[1][29] $abc$24881$new_n5629 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][29] regset[0][29] $abc$24881$new_n5630 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5632 regset[15][29] regset[11][29] $abc$24881$new_n5631 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][29] regset[10][29] $abc$24881$new_n5632 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5634 regset[7][29] regset[3][29] $abc$24881$new_n5633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][29] regset[2][29] $abc$24881$new_n5634 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5636 regset[13][29] regset[9][29] $abc$24881$new_n5635 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][29] regset[8][29] $abc$24881$new_n5636 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5637 +10 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5640 $abc$24881$new_n5642 $abc$24881$new_n5644 $abc$24881$new_n5639 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5641 regset[31][29] regset[27][29] $abc$24881$new_n5640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][29] regset[26][29] $abc$24881$new_n5641 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5643 regset[21][29] regset[17][29] $abc$24881$new_n5642 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][29] regset[16][29] $abc$24881$new_n5643 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5645 regset[23][29] regset[19][29] $abc$24881$new_n5644 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][29] regset[18][29] $abc$24881$new_n5645 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5647 regset[29][29] regset[25][29] $abc$24881$new_n5646 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][29] regset[24][29] $abc$24881$new_n5647 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5660 $abc$24881$new_n5653 $abc$24881$new_n5658 instruction_decoder.o_dcdA[3] $abc$24881$new_n5652 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5654 $abc$24881$new_n5656 $abc$24881$new_n5653 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5655 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[23][28] regset[19][28] $abc$24881$new_n5654 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[31][28] regset[27][28] $abc$24881$new_n5655 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n5657 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[22][28] regset[18][28] $abc$24881$new_n5656 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[30][28] regset[26][28] $abc$24881$new_n5657 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5659 regset[21][28] regset[17][28] $abc$24881$new_n5658 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][28] regset[16][28] $abc$24881$new_n5659 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5661 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][28] regset[24][28] $abc$24881$new_n5660 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][28] regset[25][28] $abc$24881$new_n5661 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5663 $abc$24881$new_n5670 $abc$24881$new_n5668 $abc$24881$new_n5662 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5664 $abc$24881$new_n5666 $abc$24881$new_n5663 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5665 regset[13][28] regset[9][28] $abc$24881$new_n5664 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][28] regset[8][28] $abc$24881$new_n5665 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5667 regset[4][28] regset[0][28] $abc$24881$new_n5666 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][28] regset[1][28] $abc$24881$new_n5667 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5669 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][28] regset[2][28] $abc$24881$new_n5668 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][28] regset[3][28] $abc$24881$new_n5669 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n5671 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][28] regset[10][28] $abc$24881$new_n5670 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][28] regset[11][28] $abc$24881$new_n5671 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_Apc $abc$24881$new_n5596 $abc$24881$new_n5672 +11 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5679 $abc$24881$new_n5686 $abc$24881$new_n5684 $abc$24881$new_n5678 +0000 1 +0100 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[0] $abc$24881$new_n5680 $abc$24881$new_n5682 $abc$24881$new_n5683 $abc$24881$new_n5679 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n5681 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][27] regset[24][27] $abc$24881$new_n5680 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][27] regset[25][27] $abc$24881$new_n5681 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] regset[31][27] regset[27][27] $abc$24881$new_n5682 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] regset[30][27] regset[26][27] $abc$24881$new_n5683 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5685 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[18][27] regset[16][27] $abc$24881$new_n5684 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[22][27] regset[20][27] $abc$24881$new_n5685 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n5687 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[19][27] regset[17][27] $abc$24881$new_n5686 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] regset[23][27] regset[21][27] $abc$24881$new_n5687 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5690 regset[15][27] regset[11][27] $abc$24881$new_n5689 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][27] regset[10][27] $abc$24881$new_n5690 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5692 regset[13][27] regset[9][27] $abc$24881$new_n5691 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][27] regset[8][27] $abc$24881$new_n5692 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5695 regset[5][27] regset[1][27] $abc$24881$new_n5694 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][27] regset[0][27] $abc$24881$new_n5695 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5698 regset[7][27] regset[3][27] $abc$24881$new_n5697 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][27] regset[2][27] $abc$24881$new_n5698 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5709 $abc$24881$new_n5704 $abc$24881$new_n5711 instruction_decoder.o_dcdA[1] $abc$24881$new_n5703 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5705 $abc$24881$new_n5708 $abc$24881$new_n5707 $abc$24881$new_n5704 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5706 regset[5][26] regset[1][26] $abc$24881$new_n5705 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][26] regset[0][26] $abc$24881$new_n5706 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][26] regset[2][26] $abc$24881$new_n5707 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][26] regset[3][26] $abc$24881$new_n5708 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5710 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][26] regset[9][26] $abc$24881$new_n5709 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][26] regset[8][26] $abc$24881$new_n5710 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5712 regset[15][26] regset[11][26] $abc$24881$new_n5711 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][26] regset[10][26] $abc$24881$new_n5712 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5714 $abc$24881$new_n5719 $abc$24881$new_n5721 $abc$24881$new_n5713 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5715 $abc$24881$new_n5717 $abc$24881$new_n5714 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5716 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][26] regset[26][26] $abc$24881$new_n5715 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][26] regset[27][26] $abc$24881$new_n5716 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5718 regset[29][26] regset[25][26] $abc$24881$new_n5717 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][26] regset[24][26] $abc$24881$new_n5718 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5720 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][26] regset[18][26] $abc$24881$new_n5719 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][26] regset[19][26] $abc$24881$new_n5720 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5722 regset[21][26] regset[17][26] $abc$24881$new_n5721 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][26] regset[16][26] $abc$24881$new_n5722 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5725 r_op_Av[25] $abc$24881$auto$rtlil.cc:2693:MuxGate$23388 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5726 $abc$24881$new_n5672 $abc$24881$new_n5595 $abc$24881$new_n5747 $abc$24881$new_n3730 $abc$24881$new_n5725 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[1] dcd_Acc $abc$24881$new_n5727 $abc$24881$new_n5737 $abc$24881$new_n5726 +10001 1 +10011 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5728 $abc$24881$new_n5733 $abc$24881$new_n5735 $abc$24881$new_n5727 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5730 $abc$24881$new_n5729 $abc$24881$new_n5732 $abc$24881$new_n5731 $abc$24881$new_n5728 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][25] regset[19][25] $abc$24881$new_n5729 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][25] regset[18][25] $abc$24881$new_n5730 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][25] regset[27][25] $abc$24881$new_n5731 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][25] regset[26][25] $abc$24881$new_n5732 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5734 regset[15][25] regset[11][25] $abc$24881$new_n5733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][25] regset[10][25] $abc$24881$new_n5734 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5736 regset[6][25] regset[2][25] $abc$24881$new_n5735 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[7][25] regset[3][25] $abc$24881$new_n5736 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] $abc$24881$new_n5738 $abc$24881$new_n5743 $abc$24881$new_n5745 $abc$24881$new_n5737 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5740 $abc$24881$new_n5739 $abc$24881$new_n5742 $abc$24881$new_n5741 $abc$24881$new_n5738 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[21][25] regset[17][25] $abc$24881$new_n5739 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][25] regset[16][25] $abc$24881$new_n5740 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][25] regset[25][25] $abc$24881$new_n5741 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][25] regset[24][25] $abc$24881$new_n5742 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5744 regset[12][25] regset[8][25] $abc$24881$new_n5743 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[13][25] regset[9][25] $abc$24881$new_n5744 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5746 regset[4][25] regset[0][25] $abc$24881$new_n5745 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[5][25] regset[1][25] $abc$24881$new_n5746 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[25] SET_USER_PC.r_upc[25] $abc$24881$new_n5747 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5753 $abc$24881$new_n5755 $abc$24881$new_n5757 $abc$24881$new_n5752 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5754 regset[21][24] regset[17][24] $abc$24881$new_n5753 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][24] regset[16][24] $abc$24881$new_n5754 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5756 regset[31][24] regset[27][24] $abc$24881$new_n5755 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][24] regset[26][24] $abc$24881$new_n5756 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5758 regset[23][24] regset[19][24] $abc$24881$new_n5757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][24] regset[18][24] $abc$24881$new_n5758 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5760 regset[29][24] regset[25][24] $abc$24881$new_n5759 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][24] regset[24][24] $abc$24881$new_n5760 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5763 $abc$24881$new_n5765 $abc$24881$new_n5767 $abc$24881$new_n5762 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5764 regset[5][24] regset[1][24] $abc$24881$new_n5763 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][24] regset[0][24] $abc$24881$new_n5764 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5766 regset[15][24] regset[11][24] $abc$24881$new_n5765 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][24] regset[10][24] $abc$24881$new_n5766 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5768 regset[7][24] regset[3][24] $abc$24881$new_n5767 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][24] regset[2][24] $abc$24881$new_n5768 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5770 regset[13][24] regset[9][24] $abc$24881$new_n5769 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][24] regset[8][24] $abc$24881$new_n5770 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n9598 r_op_Av[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23392 +000 1 +001 1 +101 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5777 $abc$24881$new_n5779 $abc$24881$new_n5781 $abc$24881$new_n5776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5778 regset[15][23] regset[11][23] $abc$24881$new_n5777 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][23] regset[10][23] $abc$24881$new_n5778 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5780 regset[13][23] regset[9][23] $abc$24881$new_n5779 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][23] regset[8][23] $abc$24881$new_n5780 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5782 regset[7][23] regset[3][23] $abc$24881$new_n5781 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][23] regset[2][23] $abc$24881$new_n5782 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5784 regset[5][23] regset[1][23] $abc$24881$new_n5783 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][23] regset[0][23] $abc$24881$new_n5784 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5787 $abc$24881$new_n5789 $abc$24881$new_n5791 $abc$24881$new_n5786 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5788 regset[31][23] regset[27][23] $abc$24881$new_n5787 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][23] regset[26][23] $abc$24881$new_n5788 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5790 regset[29][23] regset[25][23] $abc$24881$new_n5789 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][23] regset[24][23] $abc$24881$new_n5790 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5792 regset[21][23] regset[17][23] $abc$24881$new_n5791 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][23] regset[16][23] $abc$24881$new_n5792 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5794 regset[23][23] regset[19][23] $abc$24881$new_n5793 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][23] regset[18][23] $abc$24881$new_n5794 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[23] SET_USER_PC.r_upc[23] $abc$24881$new_n5795 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5800 $abc$24881$new_n5805 $abc$24881$new_n5807 $abc$24881$new_n5799 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5801 $abc$24881$new_n5803 $abc$24881$new_n5800 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5802 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][22] regset[26][22] $abc$24881$new_n5801 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][22] regset[27][22] $abc$24881$new_n5802 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5804 regset[29][22] regset[25][22] $abc$24881$new_n5803 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][22] regset[24][22] $abc$24881$new_n5804 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5806 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][22] regset[18][22] $abc$24881$new_n5805 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][22] regset[19][22] $abc$24881$new_n5806 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5808 regset[21][22] regset[17][22] $abc$24881$new_n5807 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][22] regset[16][22] $abc$24881$new_n5808 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5810 $abc$24881$new_n5813 $abc$24881$new_n5812 $abc$24881$new_n5809 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5811 regset[5][22] regset[1][22] $abc$24881$new_n5810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][22] regset[0][22] $abc$24881$new_n5811 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][22] regset[2][22] $abc$24881$new_n5812 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][22] regset[3][22] $abc$24881$new_n5813 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5816 regset[15][22] regset[14][22] $abc$24881$new_n5815 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[11][22] regset[10][22] $abc$24881$new_n5816 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5818 regset[13][22] regset[12][22] $abc$24881$new_n5817 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[9][22] regset[8][22] $abc$24881$new_n5818 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[22] SET_USER_PC.r_upc[22] $abc$24881$new_n5819 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5823 $abc$24881$new_n5828 $abc$24881$new_n5830 $abc$24881$new_n5822 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5824 $abc$24881$new_n5827 $abc$24881$new_n5826 $abc$24881$new_n5823 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5825 regset[29][21] regset[25][21] $abc$24881$new_n5824 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][21] regset[24][21] $abc$24881$new_n5825 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][21] regset[27][21] $abc$24881$new_n5826 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][21] regset[26][21] $abc$24881$new_n5827 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5829 regset[23][21] regset[19][21] $abc$24881$new_n5828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][21] regset[18][21] $abc$24881$new_n5829 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5831 regset[21][21] regset[17][21] $abc$24881$new_n5830 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][21] regset[16][21] $abc$24881$new_n5831 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5833 $abc$24881$new_n5838 $abc$24881$new_n5637 $abc$24881$new_n5840 $abc$24881$new_n5832 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5834 $abc$24881$new_n5837 $abc$24881$new_n5836 $abc$24881$new_n5833 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5835 regset[5][21] regset[1][21] $abc$24881$new_n5834 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][21] regset[0][21] $abc$24881$new_n5835 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][21] regset[2][21] $abc$24881$new_n5836 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][21] regset[3][21] $abc$24881$new_n5837 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5839 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[15][21] regset[11][21] $abc$24881$new_n5838 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[14][21] regset[10][21] $abc$24881$new_n5839 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5841 regset[13][21] regset[9][21] $abc$24881$new_n5840 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][21] regset[8][21] $abc$24881$new_n5841 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[21] SET_USER_PC.r_upc[21] $abc$24881$new_n5843 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5848 $abc$24881$new_n5853 $abc$24881$new_n5855 $abc$24881$new_n5847 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5849 $abc$24881$new_n5852 $abc$24881$new_n5851 $abc$24881$new_n5848 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5850 regset[5][20] regset[1][20] $abc$24881$new_n5849 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][20] regset[0][20] $abc$24881$new_n5850 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][20] regset[2][20] $abc$24881$new_n5851 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][20] regset[3][20] $abc$24881$new_n5852 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5854 regset[13][20] regset[9][20] $abc$24881$new_n5853 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][20] regset[8][20] $abc$24881$new_n5854 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5856 regset[15][20] regset[11][20] $abc$24881$new_n5855 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][20] regset[10][20] $abc$24881$new_n5856 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5858 $abc$24881$new_n5863 $abc$24881$new_n5865 $abc$24881$new_n5857 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5859 $abc$24881$new_n5861 $abc$24881$new_n5858 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5860 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][20] regset[26][20] $abc$24881$new_n5859 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][20] regset[27][20] $abc$24881$new_n5860 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5862 regset[29][20] regset[25][20] $abc$24881$new_n5861 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][20] regset[24][20] $abc$24881$new_n5862 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5864 regset[23][20] regset[19][20] $abc$24881$new_n5863 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][20] regset[18][20] $abc$24881$new_n5864 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5866 regset[21][20] regset[17][20] $abc$24881$new_n5865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][20] regset[16][20] $abc$24881$new_n5866 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5869 r_op_Av[19] $abc$24881$auto$rtlil.cc:2693:MuxGate$23400 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3763 $abc$24881$new_n5870 $abc$24881$new_n5891 $abc$24881$new_n5869 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n5871 $abc$24881$new_n5881 $abc$24881$new_n5886 $abc$24881$new_n5870 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5872 $abc$24881$new_n5877 $abc$24881$new_n5879 instruction_decoder.o_dcdA[3] $abc$24881$new_n5871 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5875 $abc$24881$new_n5873 instruction_decoder.o_dcdA[3] $abc$24881$new_n5872 +010 1 +100 1 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5874 regset[20][19] regset[16][19] $abc$24881$new_n5873 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[21][19] regset[17][19] $abc$24881$new_n5874 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5876 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][19] regset[24][19] $abc$24881$new_n5875 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][19] regset[25][19] $abc$24881$new_n5876 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5878 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][19] regset[26][19] $abc$24881$new_n5877 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[31][19] regset[27][19] $abc$24881$new_n5878 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5880 regset[22][19] regset[18][19] $abc$24881$new_n5879 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[23][19] regset[19][19] $abc$24881$new_n5880 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5884 $abc$24881$new_n5882 instruction_decoder.o_dcdA[3] $abc$24881$new_n5881 +010 1 +100 1 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5883 regset[4][19] regset[0][19] $abc$24881$new_n5882 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][19] regset[1][19] $abc$24881$new_n5883 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5885 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][19] regset[8][19] $abc$24881$new_n5884 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][19] regset[9][19] $abc$24881$new_n5885 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n5888 $abc$24881$new_n5887 $abc$24881$new_n5890 $abc$24881$new_n5889 $abc$24881$new_n5886 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[14][19] regset[10][19] $abc$24881$new_n5887 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[6][19] regset[2][19] $abc$24881$new_n5888 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[15][19] regset[11][19] $abc$24881$new_n5889 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[7][19] regset[3][19] $abc$24881$new_n5890 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[19] SET_USER_PC.r_upc[19] $abc$24881$new_n5891 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5896 $abc$24881$new_n5901 $abc$24881$new_n5903 $abc$24881$new_n5895 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5897 $abc$24881$new_n5899 $abc$24881$new_n5896 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5898 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][18] regset[26][18] $abc$24881$new_n5897 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][18] regset[27][18] $abc$24881$new_n5898 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5900 regset[29][18] regset[25][18] $abc$24881$new_n5899 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][18] regset[24][18] $abc$24881$new_n5900 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5902 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][18] regset[18][18] $abc$24881$new_n5901 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][18] regset[19][18] $abc$24881$new_n5902 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5904 regset[21][18] regset[17][18] $abc$24881$new_n5903 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][18] regset[16][18] $abc$24881$new_n5904 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5906 $abc$24881$new_n5909 $abc$24881$new_n5908 $abc$24881$new_n5905 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5907 regset[5][18] regset[1][18] $abc$24881$new_n5906 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][18] regset[0][18] $abc$24881$new_n5907 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][18] regset[2][18] $abc$24881$new_n5908 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][18] regset[3][18] $abc$24881$new_n5909 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5912 regset[13][18] regset[12][18] $abc$24881$new_n5911 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[9][18] regset[8][18] $abc$24881$new_n5912 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n5914 regset[15][18] regset[14][18] $abc$24881$new_n5913 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[11][18] regset[10][18] $abc$24881$new_n5914 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[18] SET_USER_PC.r_upc[18] $abc$24881$new_n5915 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5917 r_op_Av[17] $abc$24881$auto$rtlil.cc:2693:MuxGate$23404 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3774 $abc$24881$new_n5918 $abc$24881$new_n5939 $abc$24881$new_n5917 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n5934 $abc$24881$new_n5919 $abc$24881$new_n5929 instruction_decoder.o_dcdA[3] $abc$24881$new_n5918 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5920 $abc$24881$new_n5925 $abc$24881$new_n5927 $abc$24881$new_n5919 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5921 $abc$24881$new_n5923 $abc$24881$new_n5920 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5922 regset[23][17] regset[19][17] $abc$24881$new_n5921 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][17] regset[18][17] $abc$24881$new_n5922 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5924 regset[21][17] regset[17][17] $abc$24881$new_n5923 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][17] regset[16][17] $abc$24881$new_n5924 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5926 regset[30][17] regset[26][17] $abc$24881$new_n5925 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[31][17] regset[27][17] $abc$24881$new_n5926 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5928 regset[29][17] regset[25][17] $abc$24881$new_n5927 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][17] regset[24][17] $abc$24881$new_n5928 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5930 $abc$24881$new_n5933 $abc$24881$new_n5932 $abc$24881$new_n5929 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5931 regset[5][17] regset[1][17] $abc$24881$new_n5930 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][17] regset[0][17] $abc$24881$new_n5931 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][17] regset[2][17] $abc$24881$new_n5932 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][17] regset[3][17] $abc$24881$new_n5933 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5935 $abc$24881$new_n5938 $abc$24881$new_n5937 $abc$24881$new_n5934 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5936 regset[15][17] regset[11][17] $abc$24881$new_n5935 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][17] regset[10][17] $abc$24881$new_n5936 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][17] regset[9][17] $abc$24881$new_n5937 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][17] regset[8][17] $abc$24881$new_n5938 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[17] SET_USER_PC.r_upc[17] $abc$24881$new_n5939 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5944 $abc$24881$new_n5949 $abc$24881$new_n5951 $abc$24881$new_n5943 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5945 $abc$24881$new_n5947 $abc$24881$new_n5944 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5946 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][16] regset[26][16] $abc$24881$new_n5945 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][16] regset[27][16] $abc$24881$new_n5946 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5948 regset[29][16] regset[25][16] $abc$24881$new_n5947 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][16] regset[24][16] $abc$24881$new_n5948 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5950 regset[23][16] regset[19][16] $abc$24881$new_n5949 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][16] regset[18][16] $abc$24881$new_n5950 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5952 regset[21][16] regset[17][16] $abc$24881$new_n5951 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][16] regset[16][16] $abc$24881$new_n5952 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5954 $abc$24881$new_n5957 $abc$24881$new_n5956 $abc$24881$new_n5953 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5955 regset[5][16] regset[1][16] $abc$24881$new_n5954 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][16] regset[0][16] $abc$24881$new_n5955 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][16] regset[2][16] $abc$24881$new_n5956 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][16] regset[3][16] $abc$24881$new_n5957 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5960 regset[15][16] regset[11][16] $abc$24881$new_n5959 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][16] regset[10][16] $abc$24881$new_n5960 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5962 regset[13][16] regset[9][16] $abc$24881$new_n5961 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][16] regset[8][16] $abc$24881$new_n5962 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[16] SET_USER_PC.r_upc[16] $abc$24881$new_n5963 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5968 $abc$24881$new_n5973 $abc$24881$new_n5975 $abc$24881$new_n5967 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5969 $abc$24881$new_n5971 $abc$24881$new_n5968 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5970 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][15] regset[26][15] $abc$24881$new_n5969 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][15] regset[27][15] $abc$24881$new_n5970 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5972 regset[29][15] regset[25][15] $abc$24881$new_n5971 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][15] regset[24][15] $abc$24881$new_n5972 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5974 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][15] regset[18][15] $abc$24881$new_n5973 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][15] regset[19][15] $abc$24881$new_n5974 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5976 regset[21][15] regset[17][15] $abc$24881$new_n5975 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][15] regset[16][15] $abc$24881$new_n5976 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n5983 $abc$24881$new_n5978 $abc$24881$new_n5985 instruction_decoder.o_dcdA[1] $abc$24881$new_n5977 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5979 $abc$24881$new_n5982 $abc$24881$new_n5981 $abc$24881$new_n5978 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5980 regset[5][15] regset[1][15] $abc$24881$new_n5979 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][15] regset[0][15] $abc$24881$new_n5980 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][15] regset[2][15] $abc$24881$new_n5981 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][15] regset[3][15] $abc$24881$new_n5982 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n5984 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][15] regset[8][15] $abc$24881$new_n5983 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][15] regset[9][15] $abc$24881$new_n5984 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5986 regset[15][15] regset[11][15] $abc$24881$new_n5985 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][15] regset[10][15] $abc$24881$new_n5986 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n5993 $abc$24881$new_n5996 $abc$24881$new_n5995 $abc$24881$new_n5992 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5994 regset[5][14] regset[1][14] $abc$24881$new_n5993 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][14] regset[0][14] $abc$24881$new_n5994 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][14] regset[2][14] $abc$24881$new_n5995 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][14] regset[3][14] $abc$24881$new_n5996 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n5999 regset[15][14] regset[11][14] $abc$24881$new_n5998 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][14] regset[10][14] $abc$24881$new_n5999 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6001 regset[13][14] regset[9][14] $abc$24881$new_n6000 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][14] regset[8][14] $abc$24881$new_n6001 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6003 $abc$24881$new_n6008 $abc$24881$new_n6010 $abc$24881$new_n6002 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6004 $abc$24881$new_n6006 $abc$24881$new_n6003 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6005 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][14] regset[26][14] $abc$24881$new_n6004 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][14] regset[27][14] $abc$24881$new_n6005 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6007 regset[29][14] regset[25][14] $abc$24881$new_n6006 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][14] regset[24][14] $abc$24881$new_n6007 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6009 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][14] regset[18][14] $abc$24881$new_n6008 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][14] regset[19][14] $abc$24881$new_n6009 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6011 regset[21][14] regset[17][14] $abc$24881$new_n6010 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][14] regset[16][14] $abc$24881$new_n6011 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6014 r_op_Av[13] $abc$24881$new_n5595 $abc$24881$new_n6016 $abc$24881$auto$rtlil.cc:2693:MuxGate$23412 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5596 $abc$24881$new_n3795 dcd_Apc $abc$24881$new_n6015 $abc$24881$new_n6014 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[13] SET_USER_PC.r_upc[13] $abc$24881$new_n6015 +000 1 +010 1 +100 1 +101 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6017 GEN_UHALT_PHASE.r_uhalt_phase GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n6016 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6018 $abc$24881$new_n6030 $abc$24881$new_n6028 $abc$24881$new_n6017 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n6019 $abc$24881$new_n6026 $abc$24881$new_n5637 $abc$24881$new_n6018 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6020 $abc$24881$new_n6022 $abc$24881$new_n6024 $abc$24881$new_n6019 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6021 regset[21][13] regset[17][13] $abc$24881$new_n6020 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][13] regset[16][13] $abc$24881$new_n6021 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6023 regset[23][13] regset[19][13] $abc$24881$new_n6022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][13] regset[18][13] $abc$24881$new_n6023 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6025 regset[31][13] regset[27][13] $abc$24881$new_n6024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][13] regset[26][13] $abc$24881$new_n6025 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6027 regset[29][13] regset[25][13] $abc$24881$new_n6026 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][13] regset[24][13] $abc$24881$new_n6027 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6029 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][13] regset[8][13] $abc$24881$new_n6028 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][13] regset[9][13] $abc$24881$new_n6029 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6031 $abc$24881$new_n6033 $abc$24881$new_n6035 $abc$24881$new_n6030 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6032 regset[5][13] regset[1][13] $abc$24881$new_n6031 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][13] regset[0][13] $abc$24881$new_n6032 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6034 regset[15][13] regset[11][13] $abc$24881$new_n6033 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][13] regset[10][13] $abc$24881$new_n6034 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6036 regset[7][13] regset[6][13] $abc$24881$new_n6035 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][13] regset[2][13] $abc$24881$new_n6036 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[12] SET_USER_PC.r_upc[12] $abc$24881$new_n6040 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] $abc$24881$new_n6042 $abc$24881$new_n6052 $abc$24881$new_n6057 $abc$24881$new_n6041 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] $abc$24881$new_n6043 $abc$24881$new_n6050 $abc$24881$new_n6048 $abc$24881$new_n6042 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6044 $abc$24881$new_n6047 $abc$24881$new_n6046 $abc$24881$new_n6043 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$24881$new_n6045 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[22][12] regset[18][12] $abc$24881$new_n6044 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[23][12] regset[19][12] $abc$24881$new_n6045 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[30][12] regset[26][12] $abc$24881$new_n6046 +0001 1 +0011 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[31][12] regset[27][12] $abc$24881$new_n6047 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6049 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[21][12] regset[17][12] $abc$24881$new_n6048 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[20][12] regset[16][12] $abc$24881$new_n6049 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n6051 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][12] regset[24][12] $abc$24881$new_n6050 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][12] regset[25][12] $abc$24881$new_n6051 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[3] $abc$24881$new_n6053 $abc$24881$new_n6055 $abc$24881$new_n6052 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6054 regset[13][12] regset[9][12] $abc$24881$new_n6053 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][12] regset[8][12] $abc$24881$new_n6054 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6056 regset[4][12] regset[0][12] $abc$24881$new_n6055 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[2] regset[5][12] regset[1][12] $abc$24881$new_n6056 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] $abc$24881$new_n6059 $abc$24881$new_n6058 $abc$24881$new_n6061 $abc$24881$new_n6060 $abc$24881$new_n6057 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[14][12] regset[6][12] $abc$24881$new_n6058 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[10][12] regset[2][12] $abc$24881$new_n6059 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[3] regset[15][12] regset[7][12] $abc$24881$new_n6060 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] regset[11][12] regset[3][12] $abc$24881$new_n6061 +0000 1 +0010 1 +1000 1 +1001 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6063 r_op_Av[11] $abc$24881$auto$rtlil.cc:2693:MuxGate$23416 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3805 $abc$24881$new_n9625 $abc$24881$new_n6086 $abc$24881$new_n6063 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6068 $abc$24881$new_n6070 $abc$24881$new_n6072 $abc$24881$new_n6067 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6069 regset[21][11] regset[17][11] $abc$24881$new_n6068 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][11] regset[16][11] $abc$24881$new_n6069 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6071 regset[31][11] regset[27][11] $abc$24881$new_n6070 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][11] regset[26][11] $abc$24881$new_n6071 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6073 regset[23][11] regset[19][11] $abc$24881$new_n6072 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][11] regset[18][11] $abc$24881$new_n6073 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6077 $abc$24881$new_n5637 $abc$24881$new_n6085 $abc$24881$new_n6084 $abc$24881$new_n6076 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6078 $abc$24881$new_n6080 $abc$24881$new_n6082 $abc$24881$new_n6077 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6079 regset[15][11] regset[11][11] $abc$24881$new_n6078 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][11] regset[10][11] $abc$24881$new_n6079 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6081 regset[7][11] regset[6][11] $abc$24881$new_n6080 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][11] regset[2][11] $abc$24881$new_n6081 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6083 regset[5][11] regset[1][11] $abc$24881$new_n6082 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][11] regset[0][11] $abc$24881$new_n6083 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[13][11] regset[9][11] $abc$24881$new_n6084 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][11] regset[8][11] $abc$24881$new_n6085 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[11] SET_USER_PC.r_upc[11] $abc$24881$new_n6086 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6088 r_op_Av[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23418 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3810 $abc$24881$new_n6089 $abc$24881$new_n6110 $abc$24881$new_n6088 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6090 SET_USER_BUSERR.r_ubus_err_flag ibus_err_flag $abc$24881$new_n6089 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6091 $abc$24881$new_n6103 $abc$24881$new_n6101 $abc$24881$new_n6090 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n6092 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6097 $abc$24881$new_n6099 $abc$24881$new_n6091 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6093 $abc$24881$new_n6095 $abc$24881$new_n6092 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6094 regset[5][10] regset[1][10] $abc$24881$new_n6093 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][10] regset[0][10] $abc$24881$new_n6094 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6096 regset[7][10] regset[3][10] $abc$24881$new_n6095 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][10] regset[2][10] $abc$24881$new_n6096 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6098 regset[15][10] regset[11][10] $abc$24881$new_n6097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][10] regset[10][10] $abc$24881$new_n6098 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6100 regset[13][10] regset[9][10] $abc$24881$new_n6099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][10] regset[8][10] $abc$24881$new_n6100 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6102 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][10] regset[25][10] $abc$24881$new_n6101 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][10] regset[24][10] $abc$24881$new_n6102 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6104 $abc$24881$new_n6106 $abc$24881$new_n6108 $abc$24881$new_n6103 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6105 regset[21][10] regset[17][10] $abc$24881$new_n6104 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][10] regset[16][10] $abc$24881$new_n6105 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6107 regset[23][10] regset[19][10] $abc$24881$new_n6106 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][10] regset[18][10] $abc$24881$new_n6107 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6109 regset[31][10] regset[27][10] $abc$24881$new_n6108 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][10] regset[26][10] $abc$24881$new_n6109 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[10] SET_USER_PC.r_upc[10] $abc$24881$new_n6110 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6112 r_op_Av[9] $abc$24881$auto$rtlil.cc:2693:MuxGate$23420 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3815 $abc$24881$new_n6113 $abc$24881$new_n6134 $abc$24881$new_n6112 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names dcd_Acc $abc$24881$new_n6114 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n6113 +010 1 +011 1 +100 1 +110 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6115 $abc$24881$new_n6127 $abc$24881$new_n6125 $abc$24881$new_n6114 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n6116 $abc$24881$new_n6123 $abc$24881$new_n5637 $abc$24881$new_n6115 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6117 $abc$24881$new_n6119 $abc$24881$new_n6121 $abc$24881$new_n6116 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6118 regset[23][9] regset[19][9] $abc$24881$new_n6117 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][9] regset[18][9] $abc$24881$new_n6118 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6120 regset[21][9] regset[17][9] $abc$24881$new_n6119 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][9] regset[16][9] $abc$24881$new_n6120 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6122 regset[31][9] regset[27][9] $abc$24881$new_n6121 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][9] regset[26][9] $abc$24881$new_n6122 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6124 regset[29][9] regset[25][9] $abc$24881$new_n6123 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][9] regset[24][9] $abc$24881$new_n6124 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6126 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][9] regset[8][9] $abc$24881$new_n6125 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][9] regset[9][9] $abc$24881$new_n6126 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6128 $abc$24881$new_n6130 $abc$24881$new_n6132 $abc$24881$new_n6127 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6129 regset[7][9] regset[6][9] $abc$24881$new_n6128 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[3][9] regset[2][9] $abc$24881$new_n6129 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6131 regset[15][9] regset[11][9] $abc$24881$new_n6130 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][9] regset[10][9] $abc$24881$new_n6131 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6133 regset[5][9] regset[1][9] $abc$24881$new_n6132 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][9] regset[0][9] $abc$24881$new_n6133 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[9] SET_USER_PC.r_upc[9] $abc$24881$new_n6134 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6136 r_op_Av[8] $abc$24881$auto$rtlil.cc:2693:MuxGate$23422 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3820 $abc$24881$new_n6137 $abc$24881$new_n6159 $abc$24881$new_n6136 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6138 SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n6137 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6139 $abc$24881$new_n6149 $abc$24881$new_n6154 $abc$24881$new_n6138 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +.names $abc$24881$new_n6140 $abc$24881$new_n6147 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6145 $abc$24881$new_n6139 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6141 $abc$24881$new_n6143 $abc$24881$new_n6144 $abc$24881$new_n6140 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6142 regset[15][8] regset[11][8] $abc$24881$new_n6141 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][8] regset[10][8] $abc$24881$new_n6142 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][8] regset[2][8] $abc$24881$new_n6143 +0000 1 +0010 1 +1000 1 +1001 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][8] regset[3][8] $abc$24881$new_n6144 +1000 1 +1010 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6146 regset[13][8] regset[9][8] $abc$24881$new_n6145 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][8] regset[8][8] $abc$24881$new_n6146 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6148 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][8] regset[0][8] $abc$24881$new_n6147 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][8] regset[1][8] $abc$24881$new_n6148 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6150 $abc$24881$new_n6152 $abc$24881$new_n6149 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6151 regset[23][8] regset[19][8] $abc$24881$new_n6150 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][8] regset[18][8] $abc$24881$new_n6151 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6153 regset[29][8] regset[25][8] $abc$24881$new_n6152 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][8] regset[24][8] $abc$24881$new_n6153 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6155 $abc$24881$new_n6157 $abc$24881$new_n6154 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6156 regset[31][8] regset[27][8] $abc$24881$new_n6155 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][8] regset[26][8] $abc$24881$new_n6156 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6158 regset[21][8] regset[17][8] $abc$24881$new_n6157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][8] regset[16][8] $abc$24881$new_n6158 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[8] SET_USER_PC.r_upc[8] $abc$24881$new_n6159 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6161 r_op_Av[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23424 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3825 $abc$24881$new_n6162 $abc$24881$new_n6183 $abc$24881$new_n6161 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n6163 SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n6162 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n6164 $abc$24881$new_n6174 $abc$24881$new_n6176 $abc$24881$new_n6163 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$24881$new_n6165 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6172 $abc$24881$new_n6164 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6166 $abc$24881$new_n6168 $abc$24881$new_n6170 $abc$24881$new_n6165 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6167 regset[21][7] regset[17][7] $abc$24881$new_n6166 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][7] regset[16][7] $abc$24881$new_n6167 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6169 regset[23][7] regset[22][7] $abc$24881$new_n6168 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][7] regset[18][7] $abc$24881$new_n6169 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6171 regset[29][7] regset[25][7] $abc$24881$new_n6170 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][7] regset[24][7] $abc$24881$new_n6171 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6173 regset[31][7] regset[30][7] $abc$24881$new_n6172 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[27][7] regset[26][7] $abc$24881$new_n6173 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6175 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[13][7] regset[9][7] $abc$24881$new_n6174 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[12][7] regset[8][7] $abc$24881$new_n6175 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6177 $abc$24881$new_n6179 $abc$24881$new_n6181 $abc$24881$new_n6176 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6178 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[6][7] regset[2][7] $abc$24881$new_n6177 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[7][7] regset[3][7] $abc$24881$new_n6178 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6180 regset[15][7] regset[11][7] $abc$24881$new_n6179 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][7] regset[10][7] $abc$24881$new_n6180 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6182 regset[4][7] regset[0][7] $abc$24881$new_n6181 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[5][7] regset[1][7] $abc$24881$new_n6182 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[7] SET_USER_PC.r_upc[7] $abc$24881$new_n6183 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6185 r_op_Av[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23426 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3832 $abc$24881$new_n9887 $abc$24881$new_n6209 $abc$24881$new_n6185 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6191 regset[5][6] regset[1][6] $abc$24881$new_n6190 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][6] regset[0][6] $abc$24881$new_n6191 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6193 regset[13][6] regset[9][6] $abc$24881$new_n6192 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][6] regset[8][6] $abc$24881$new_n6193 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6198 regset[15][6] regset[11][6] $abc$24881$new_n6197 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][6] regset[10][6] $abc$24881$new_n6198 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6200 $abc$24881$new_n6207 $abc$24881$new_n5637 $abc$24881$new_n6199 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6201 $abc$24881$new_n6203 $abc$24881$new_n6205 $abc$24881$new_n6200 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6202 regset[31][6] regset[27][6] $abc$24881$new_n6201 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][6] regset[26][6] $abc$24881$new_n6202 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6204 regset[23][6] regset[19][6] $abc$24881$new_n6203 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][6] regset[18][6] $abc$24881$new_n6204 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6206 regset[21][6] regset[17][6] $abc$24881$new_n6205 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][6] regset[16][6] $abc$24881$new_n6206 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6208 regset[29][6] regset[25][6] $abc$24881$new_n6207 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][6] regset[24][6] $abc$24881$new_n6208 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[6] SET_USER_PC.r_upc[6] $abc$24881$new_n6209 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6214 $abc$24881$new_n5637 $abc$24881$new_n6222 $abc$24881$new_n6221 $abc$24881$new_n6213 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6215 $abc$24881$new_n6217 $abc$24881$new_n6219 $abc$24881$new_n6214 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6216 regset[31][5] regset[27][5] $abc$24881$new_n6215 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][5] regset[26][5] $abc$24881$new_n6216 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6218 regset[23][5] regset[19][5] $abc$24881$new_n6217 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][5] regset[18][5] $abc$24881$new_n6218 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6220 regset[21][5] regset[17][5] $abc$24881$new_n6219 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][5] regset[16][5] $abc$24881$new_n6220 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][5] regset[25][5] $abc$24881$new_n6221 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][5] regset[24][5] $abc$24881$new_n6222 +0001 1 +0011 1 +1010 1 +1011 1 +.names $abc$24881$new_n6224 instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6231 $abc$24881$new_n6223 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6225 $abc$24881$new_n6227 $abc$24881$new_n6229 $abc$24881$new_n6224 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6226 regset[12][5] regset[8][5] $abc$24881$new_n6225 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[13][5] regset[9][5] $abc$24881$new_n6226 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6228 regset[15][5] regset[11][5] $abc$24881$new_n6227 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][5] regset[10][5] $abc$24881$new_n6228 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6230 regset[5][5] regset[1][5] $abc$24881$new_n6229 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][5] regset[0][5] $abc$24881$new_n6230 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6232 regset[7][5] regset[3][5] $abc$24881$new_n6231 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][5] regset[2][5] $abc$24881$new_n6232 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6235 r_op_Av[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23430 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3843 $abc$24881$new_n9635 $abc$24881$new_n6258 $abc$24881$new_n6235 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6240 regset[21][4] regset[17][4] $abc$24881$new_n6239 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[20][4] regset[16][4] $abc$24881$new_n6240 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6242 regset[29][4] regset[25][4] $abc$24881$new_n6241 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[28][4] regset[24][4] $abc$24881$new_n6242 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6244 $abc$24881$new_n6246 $abc$24881$new_n6243 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6245 regset[31][4] regset[27][4] $abc$24881$new_n6244 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][4] regset[26][4] $abc$24881$new_n6245 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6247 regset[23][4] regset[19][4] $abc$24881$new_n6246 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[22][4] regset[18][4] $abc$24881$new_n6247 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6250 regset[15][4] regset[11][4] $abc$24881$new_n6249 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][4] regset[10][4] $abc$24881$new_n6250 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6254 $abc$24881$new_n6252 $abc$24881$new_n6256 $abc$24881$new_n6251 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6253 regset[13][4] regset[9][4] $abc$24881$new_n6252 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][4] regset[8][4] $abc$24881$new_n6253 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6255 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[4][4] regset[0][4] $abc$24881$new_n6254 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[5][4] regset[1][4] $abc$24881$new_n6255 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6257 regset[6][4] regset[2][4] $abc$24881$new_n6256 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[7][4] regset[3][4] $abc$24881$new_n6257 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[4] SET_USER_PC.r_upc[4] $abc$24881$new_n6258 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n6260 r_op_Av[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$23432 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3848 $abc$24881$new_n9639 $abc$24881$new_n6285 $abc$24881$new_n6260 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6265 regset[21][3] regset[20][3] $abc$24881$new_n6264 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][3] regset[16][3] $abc$24881$new_n6265 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6267 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][3] regset[25][3] $abc$24881$new_n6266 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][3] regset[24][3] $abc$24881$new_n6267 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6270 regset[23][3] regset[22][3] $abc$24881$new_n6269 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][3] regset[18][3] $abc$24881$new_n6270 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6273 regset[31][3] regset[27][3] $abc$24881$new_n6272 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][3] regset[26][3] $abc$24881$new_n6273 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6276 $abc$24881$new_n6278 $abc$24881$new_n6275 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6277 regset[13][3] regset[9][3] $abc$24881$new_n6276 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][3] regset[8][3] $abc$24881$new_n6277 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6279 regset[7][3] regset[3][3] $abc$24881$new_n6278 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][3] regset[2][3] $abc$24881$new_n6279 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6281 regset[5][3] regset[1][3] $abc$24881$new_n6280 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][3] regset[0][3] $abc$24881$new_n6281 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6283 regset[15][3] regset[11][3] $abc$24881$new_n6282 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][3] regset[10][3] $abc$24881$new_n6283 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4071 instruction_decoder.o_pc[3] SET_USER_PC.r_upc[3] $abc$24881$new_n6285 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6292 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][2] regset[25][2] $abc$24881$new_n6291 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][2] regset[24][2] $abc$24881$new_n6292 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6295 regset[31][2] regset[27][2] $abc$24881$new_n6294 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][2] regset[26][2] $abc$24881$new_n6295 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6298 regset[23][2] regset[22][2] $abc$24881$new_n6297 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][2] regset[18][2] $abc$24881$new_n6298 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6301 regset[21][2] regset[20][2] $abc$24881$new_n6300 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][2] regset[16][2] $abc$24881$new_n6301 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6304 $abc$24881$new_n6306 $abc$24881$new_n6303 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6305 regset[13][2] regset[9][2] $abc$24881$new_n6304 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][2] regset[8][2] $abc$24881$new_n6305 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6307 regset[7][2] regset[3][2] $abc$24881$new_n6306 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][2] regset[2][2] $abc$24881$new_n6307 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6309 regset[5][2] regset[1][2] $abc$24881$new_n6308 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[4][2] regset[0][2] $abc$24881$new_n6309 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6311 regset[15][2] regset[11][2] $abc$24881$new_n6310 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[14][2] regset[10][2] $abc$24881$new_n6311 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6318 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[29][1] regset[25][1] $abc$24881$new_n6317 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5637 instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] regset[28][1] regset[24][1] $abc$24881$new_n6318 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6321 regset[31][1] regset[27][1] $abc$24881$new_n6320 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[30][1] regset[26][1] $abc$24881$new_n6321 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6324 regset[23][1] regset[22][1] $abc$24881$new_n6323 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[19][1] regset[18][1] $abc$24881$new_n6324 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6327 regset[21][1] regset[20][1] $abc$24881$new_n6326 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] regset[17][1] regset[16][1] $abc$24881$new_n6327 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6329 $abc$24881$new_n6334 $abc$24881$new_n6336 $abc$24881$new_n6328 +00100 1 +00101 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6330 $abc$24881$new_n6332 $abc$24881$new_n6329 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6331 regset[7][1] regset[3][1] $abc$24881$new_n6330 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[6][1] regset[2][1] $abc$24881$new_n6331 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6333 regset[13][1] regset[9][1] $abc$24881$new_n6332 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[2] regset[12][1] regset[8][1] $abc$24881$new_n6333 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6335 regset[5][1] regset[1][1] $abc$24881$new_n6334 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][1] regset[0][1] $abc$24881$new_n6335 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6337 regset[15][1] regset[11][1] $abc$24881$new_n6336 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][1] regset[10][1] $abc$24881$new_n6337 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5672 $abc$24881$new_n3859 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4071 $abc$24881$new_n6338 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1110 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6345 $abc$24881$new_n6347 $abc$24881$new_n6349 $abc$24881$new_n6344 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6346 regset[7][0] regset[3][0] $abc$24881$new_n6345 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][0] regset[2][0] $abc$24881$new_n6346 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6348 regset[13][0] regset[9][0] $abc$24881$new_n6347 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][0] regset[8][0] $abc$24881$new_n6348 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6350 regset[15][0] regset[11][0] $abc$24881$new_n6349 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][0] regset[10][0] $abc$24881$new_n6350 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6352 regset[5][0] regset[1][0] $abc$24881$new_n6351 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][0] regset[0][0] $abc$24881$new_n6352 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6355 $abc$24881$new_n6357 $abc$24881$new_n6359 $abc$24881$new_n6354 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6356 regset[31][0] regset[27][0] $abc$24881$new_n6355 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][0] regset[26][0] $abc$24881$new_n6356 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6358 regset[29][0] regset[25][0] $abc$24881$new_n6357 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][0] regset[24][0] $abc$24881$new_n6358 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6360 regset[23][0] regset[22][0] $abc$24881$new_n6359 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] regset[19][0] regset[18][0] $abc$24881$new_n6360 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6362 regset[21][0] regset[17][0] $abc$24881$new_n6361 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[20][0] regset[16][0] $abc$24881$new_n6362 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6364 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23440 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n4280 $abc$24881$new_n6364 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n6382 i_pf_instruction[17] i_pf_instruction_pc[29] i_pf_instruction_pc[28] $abc$24881$new_n6366 $abc$24881$new_n6365 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names i_pf_instruction[17] i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6366 +0110 1 +1000 1 +.names $abc$24881$new_n6380 i_pf_instruction[17] $abc$24881$new_n6368 $abc$24881$new_n6367 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n6379 i_pf_instruction[17] i_pf_instruction_pc[21] i_pf_instruction_pc[20] $abc$24881$new_n6369 $abc$24881$new_n6368 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11000 1 +.names i_pf_instruction_pc[18] i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6369 +00100 1 +00110 1 +00111 1 +11010 1 +.names i_pf_instruction[15] i_pf_instruction_pc[15] i_pf_instruction[16] i_pf_instruction_pc[16] $abc$24881$new_n6371 $abc$24881$new_n6370 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[13] i_pf_instruction[13] i_pf_instruction_pc[14] i_pf_instruction[14] $abc$24881$new_n6372 $abc$24881$new_n6371 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[11] i_pf_instruction[11] i_pf_instruction_pc[12] i_pf_instruction[12] $abc$24881$new_n6373 $abc$24881$new_n6372 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[9] i_pf_instruction[9] i_pf_instruction_pc[10] i_pf_instruction[10] $abc$24881$new_n6374 $abc$24881$new_n6373 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names i_pf_instruction_pc[8] i_pf_instruction[8] $abc$24881$new_n6375 $abc$24881$new_n6374 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n6376 i_pf_instruction_pc[7] i_pf_instruction[7] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6375 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names i_pf_instruction_pc[5] i_pf_instruction[5] i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6377 $abc$24881$new_n6376 +01010 1 +01100 1 +10010 1 +10100 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6377 +000 1 +001 1 +011 1 +101 1 +.names i_pf_instruction[2] i_pf_instruction_pc[2] i_pf_instruction_pc[3] i_pf_instruction[3] $abc$24881$new_n6378 +0000 1 +0001 1 +0010 1 +0100 1 +1000 1 +1100 1 +.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[19] $abc$24881$new_n6379 +000 1 +001 1 +010 1 +011 1 +100 1 +.names i_pf_instruction[17] i_pf_instruction_pc[25] i_pf_instruction_pc[24] i_pf_instruction_pc[23] i_pf_instruction_pc[22] $abc$24881$new_n6380 +01111 1 +10000 1 +.names i_pf_instruction[17] i_pf_instruction_pc[26] i_pf_instruction_pc[27] $abc$24881$new_n6382 +000 1 +001 1 +010 1 +011 1 +100 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] $abc$24881$new_n6387 $abc$24881$new_n4279 $abc$24881$auto$rtlil.cc:2693:MuxGate$23444 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[28] $abc$24881$new_n6382 $abc$24881$new_n6366 $abc$24881$new_n6387 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] $abc$24881$new_n6389 $abc$24881$new_n4302 $abc$24881$auto$rtlil.cc:2693:MuxGate$23446 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[27] i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n6389 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6391 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] $abc$24881$auto$rtlil.cc:2693:MuxGate$23448 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[26] $abc$24881$new_n6367 $abc$24881$new_n4265 $abc$24881$new_n6391 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] $abc$24881$new_n6393 $abc$24881$new_n4264 $abc$24881$auto$rtlil.cc:2693:MuxGate$23450 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[25] i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6393 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11001 1 +.names i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n6394 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] $abc$24881$new_n6396 $abc$24881$new_n4267 $abc$24881$auto$rtlil.cc:2693:MuxGate$23452 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[24] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n6396 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6398 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] $abc$24881$auto$rtlil.cc:2693:MuxGate$23454 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[23] $abc$24881$new_n6394 $abc$24881$new_n4273 $abc$24881$new_n6398 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 $abc$24881$new_n6400 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$auto$rtlil.cc:2693:MuxGate$23456 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[22] $abc$24881$new_n6368 $abc$24881$new_n4287 $abc$24881$new_n6400 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] $abc$24881$new_n6402 $abc$24881$new_n4289 $abc$24881$auto$rtlil.cc:2693:MuxGate$23458 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[21] i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6402 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10111 1 +11010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] $abc$24881$new_n6404 $abc$24881$new_n4291 $abc$24881$auto$rtlil.cc:2693:MuxGate$23460 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[20] $abc$24881$new_n6379 $abc$24881$new_n6369 $abc$24881$new_n6404 +0000 1 +0001 1 +0011 1 +0110 1 +1010 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] $abc$24881$new_n6406 $abc$24881$new_n4293 $abc$24881$auto$rtlil.cc:2693:MuxGate$23462 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[19] i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6406 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11001 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] $abc$24881$new_n6408 $abc$24881$new_n4283 $abc$24881$auto$rtlil.cc:2693:MuxGate$23464 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[17] i_pf_instruction_pc[18] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n6408 +0010 1 +0100 1 +0101 1 +0111 1 +1001 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] $abc$24881$new_n6410 $abc$24881$auto$rtlil.cc:2693:MuxGate$23466 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[17] i_pf_instruction_pc[17] $abc$24881$new_n6370 $abc$24881$new_n5442 $abc$24881$new_n6410 +00000 1 +00001 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] $abc$24881$new_n6412 $abc$24881$new_n5455 $abc$24881$auto$rtlil.cc:2693:MuxGate$23468 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[16] i_pf_instruction_pc[16] i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 $abc$24881$new_n6412 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] $abc$24881$new_n6414 $abc$24881$auto$rtlil.cc:2693:MuxGate$23470 +001 1 +011 1 +110 1 +111 1 +.names i_pf_instruction[15] i_pf_instruction_pc[15] $abc$24881$new_n6371 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6414 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n6416 i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23472 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[14] i_pf_instruction[14] i_pf_instruction_pc[13] i_pf_instruction[13] $abc$24881$new_n6372 $abc$24881$new_n6416 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n6418 $abc$24881$auto$rtlil.cc:2693:MuxGate$23474 +001 1 +011 1 +110 1 +111 1 +.names i_pf_instruction[13] i_pf_instruction_pc[13] $abc$24881$new_n6372 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6418 +0000 1 +0110 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n6420 i_pf_instruction[12] $abc$24881$auto$rtlil.cc:2693:MuxGate$23476 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[12] i_pf_instruction[12] i_pf_instruction_pc[11] i_pf_instruction[11] $abc$24881$new_n6373 $abc$24881$new_n6420 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] $abc$24881$new_n6422 $abc$24881$auto$rtlil.cc:2693:MuxGate$23478 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[11] i_pf_instruction_pc[11] $abc$24881$new_n6373 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6422 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] $abc$24881$new_n6424 i_pf_instruction[10] $abc$24881$auto$rtlil.cc:2693:MuxGate$23480 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[10] i_pf_instruction[10] i_pf_instruction_pc[9] i_pf_instruction[9] $abc$24881$new_n6374 $abc$24881$new_n6424 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] $abc$24881$new_n6426 $abc$24881$auto$rtlil.cc:2693:MuxGate$23482 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[9] i_pf_instruction_pc[9] $abc$24881$new_n6374 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6426 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] $abc$24881$new_n6428 $abc$24881$auto$rtlil.cc:2693:MuxGate$23484 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[8] i_pf_instruction_pc[8] $abc$24881$new_n6375 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6428 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1110 1 +.names $abc$24881$new_n4028 i_pf_instruction[7] $abc$24881$new_n6430 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$auto$rtlil.cc:2693:MuxGate$23486 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_pf_instruction_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6376 i_pf_instruction_pc[6] i_pf_instruction[6] $abc$24881$new_n6430 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n6432 i_pf_instruction[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23488 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[6] i_pf_instruction[6] i_pf_instruction_pc[5] i_pf_instruction[5] $abc$24881$new_n6377 $abc$24881$new_n6432 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 i_pf_instruction[5] $abc$24881$new_n6434 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] $abc$24881$auto$rtlil.cc:2693:MuxGate$23490 +0010 1 +0011 1 +0100 1 +0101 1 +1001 1 +1011 1 +1101 1 +1111 1 +.names i_pf_instruction_pc[5] $abc$24881$new_n6377 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6434 +000 1 +110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] $abc$24881$new_n6436 i_pf_instruction[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23492 +00010 1 +00011 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[4] i_pf_instruction[4] $abc$24881$new_n6378 $abc$24881$new_n6436 +000 1 +011 1 +101 1 +110 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] $abc$24881$new_n6438 $abc$24881$auto$rtlil.cc:2693:MuxGate$23494 +000 1 +010 1 +110 1 +111 1 +.names i_pf_instruction[3] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6438 +00000 1 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +11000 1 +.names $abc$24881$new_n4028 i_pf_instruction[2] i_pf_instruction_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] $abc$24881$auto$rtlil.cc:2693:MuxGate$23496 +00000 1 +00001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6441 $abc$24881$new_n6459 $abc$24881$auto$rtlil.cc:2693:MuxGate$23498 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] instruction_decoder.o_pc[29] $abc$24881$new_n6442 $abc$24881$new_n6441 +1111 1 +.names instruction_decoder.o_pc[23] instruction_decoder.o_pc[24] instruction_decoder.o_pc[25] instruction_decoder.o_pc[26] $abc$24881$new_n6443 $abc$24881$new_n6442 +11111 1 +.names instruction_decoder.o_pc[20] instruction_decoder.o_pc[21] instruction_decoder.o_pc[22] $abc$24881$new_n6444 $abc$24881$new_n6443 +1111 1 +.names instruction_decoder.o_pc[18] instruction_decoder.o_pc[19] $abc$24881$new_n6445 $abc$24881$new_n6444 +111 1 +.names instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6445 +11 1 +.names instruction_decoder.o_pc[16] $abc$24881$new_n6447 $abc$24881$new_n6446 +11 1 +.names instruction_decoder.o_pc[15] $abc$24881$new_n6448 $abc$24881$new_n6447 +11 1 +.names instruction_decoder.o_pc[14] $abc$24881$new_n6449 $abc$24881$new_n6448 +11 1 +.names instruction_decoder.o_pc[13] $abc$24881$new_n6450 $abc$24881$new_n6449 +11 1 +.names instruction_decoder.o_pc[12] $abc$24881$new_n6451 $abc$24881$new_n6450 +11 1 +.names instruction_decoder.o_pc[11] $abc$24881$new_n6452 $abc$24881$new_n6451 +11 1 +.names instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6452 +11 1 +.names instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6453 +11 1 +.names instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6454 +11 1 +.names instruction_decoder.o_pc[6] instruction_decoder.o_pc[7] $abc$24881$new_n6456 $abc$24881$new_n6455 +111 1 +.names instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6456 +11 1 +.names instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6457 +11 1 +.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] instruction_decoder.o_pc[3] $abc$24881$new_n6458 +111 1 +.names i_pf_instruction_pc[30] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6459 +0010 1 +1000 1 +1001 1 +1011 1 +.names i_pf_instruction_pc[29] $abc$24881$new_n6461 $abc$24881$new_n6460 +11 1 +.names i_pf_instruction_pc[28] $abc$24881$new_n6462 $abc$24881$new_n6461 +11 1 +.names i_pf_instruction_pc[27] i_pf_instruction_pc[26] $abc$24881$new_n6463 $abc$24881$new_n6462 +111 1 +.names i_pf_instruction_pc[25] i_pf_instruction_pc[24] $abc$24881$new_n6464 $abc$24881$new_n6463 +111 1 +.names i_pf_instruction_pc[23] i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 $abc$24881$new_n6464 +1111 1 +.names i_pf_instruction_pc[20] i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 $abc$24881$new_n6465 +1111 1 +.names i_pf_instruction_pc[17] $abc$24881$new_n6467 $abc$24881$new_n6466 +11 1 +.names i_pf_instruction_pc[16] $abc$24881$new_n6468 $abc$24881$new_n6467 +11 1 +.names i_pf_instruction_pc[15] $abc$24881$new_n6469 $abc$24881$new_n6468 +11 1 +.names i_pf_instruction_pc[14] $abc$24881$new_n6470 $abc$24881$new_n6469 +11 1 +.names i_pf_instruction_pc[13] $abc$24881$new_n6471 $abc$24881$new_n6470 +11 1 +.names i_pf_instruction_pc[12] $abc$24881$new_n6472 $abc$24881$new_n6471 +11 1 +.names i_pf_instruction_pc[11] i_pf_instruction_pc[10] $abc$24881$new_n6473 $abc$24881$new_n6472 +111 1 +.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] $abc$24881$new_n6474 $abc$24881$new_n6473 +1111 1 +.names i_pf_instruction_pc[6] i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] $abc$24881$new_n6474 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_valid $abc$24881$new_n6475 +001 1 +010 1 +011 1 +.names $abc$24881$new_n6475 $abc$24881$new_n6477 instruction_decoder.o_pc[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$23500 +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n6478 i_pf_instruction_pc[29] $abc$24881$new_n6461 i_pf_instruction[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6477 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[29] instruction_decoder.o_pc[27] instruction_decoder.o_pc[28] $abc$24881$new_n6442 $abc$24881$new_n6478 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6480 $abc$24881$new_n6481 $abc$24881$auto$rtlil.cc:2693:MuxGate$23502 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[27] $abc$24881$new_n6442 $abc$24881$new_n6480 +11 1 +.names i_pf_instruction_pc[28] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6462 i_pf_instruction[31] $abc$24881$new_n6481 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6442 $abc$24881$new_n6483 $abc$24881$auto$rtlil.cc:2693:MuxGate$23504 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[27] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[26] $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6483 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6485 $abc$24881$new_n6488 $abc$24881$auto$rtlil.cc:2693:MuxGate$23506 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[25] $abc$24881$new_n6486 $abc$24881$new_n6485 +11 1 +.names instruction_decoder.o_pc[24] $abc$24881$new_n6487 $abc$24881$new_n6486 +11 1 +.names instruction_decoder.o_pc[23] $abc$24881$new_n6443 $abc$24881$new_n6487 +11 1 +.names i_pf_instruction_pc[26] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6463 i_pf_instruction[31] $abc$24881$new_n6488 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6486 $abc$24881$new_n6490 $abc$24881$auto$rtlil.cc:2693:MuxGate$23508 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[25] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[24] $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6490 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6487 $abc$24881$new_n6492 $abc$24881$auto$rtlil.cc:2693:MuxGate$23510 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6464 i_pf_instruction[31] $abc$24881$new_n6492 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[23] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6443 $abc$24881$new_n6494 $abc$24881$auto$rtlil.cc:2693:MuxGate$23512 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[23] $abc$24881$new_n6495 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6494 +010 1 +100 1 +.names i_pf_instruction_pc[22] i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6495 +1110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6497 $abc$24881$new_n6499 $abc$24881$auto$rtlil.cc:2693:MuxGate$23514 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[21] $abc$24881$new_n6498 $abc$24881$new_n6497 +11 1 +.names instruction_decoder.o_pc[20] $abc$24881$new_n6444 $abc$24881$new_n6498 +11 1 +.names i_pf_instruction_pc[22] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[21] $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6499 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6498 $abc$24881$new_n6501 $abc$24881$auto$rtlil.cc:2693:MuxGate$23516 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[21] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6465 i_pf_instruction[31] $abc$24881$new_n6501 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[20] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6444 $abc$24881$new_n6503 $abc$24881$auto$rtlil.cc:2693:MuxGate$23518 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[20] $abc$24881$new_n6504 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6503 +010 1 +100 1 +.names i_pf_instruction_pc[19] i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6504 +1110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6506 $abc$24881$new_n6507 $abc$24881$auto$rtlil.cc:2693:MuxGate$23520 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[18] $abc$24881$new_n6445 $abc$24881$new_n6506 +11 1 +.names i_pf_instruction_pc[19] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[18] $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6507 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6445 $abc$24881$new_n6509 $abc$24881$auto$rtlil.cc:2693:MuxGate$23522 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[18] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6466 i_pf_instruction[31] $abc$24881$new_n6509 +0010 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[17] $abc$24881$new_n6446 $abc$24881$new_n6511 $abc$24881$auto$rtlil.cc:2693:MuxGate$23524 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[17] $abc$24881$new_n6467 i_pf_instruction[31] $abc$24881$new_n6511 +000 1 +001 1 +011 1 +110 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6447 $abc$24881$new_n6513 $abc$24881$auto$rtlil.cc:2693:MuxGate$23526 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[16] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6468 i_pf_instruction[31] $abc$24881$new_n6513 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6448 $abc$24881$new_n6515 $abc$24881$auto$rtlil.cc:2693:MuxGate$23528 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[15] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6469 i_pf_instruction[31] $abc$24881$new_n6515 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6449 $abc$24881$new_n6517 $abc$24881$auto$rtlil.cc:2693:MuxGate$23530 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[14] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6470 i_pf_instruction[31] $abc$24881$new_n6517 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6450 $abc$24881$new_n6519 $abc$24881$auto$rtlil.cc:2693:MuxGate$23532 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[13] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6471 i_pf_instruction[31] $abc$24881$new_n6519 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6451 $abc$24881$new_n6521 $abc$24881$auto$rtlil.cc:2693:MuxGate$23534 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[12] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6472 i_pf_instruction[31] $abc$24881$new_n6521 +0010 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6452 $abc$24881$new_n6523 $abc$24881$auto$rtlil.cc:2693:MuxGate$23536 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names i_pf_instruction_pc[11] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6523 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[10] $abc$24881$new_n6453 $abc$24881$new_n6525 $abc$24881$auto$rtlil.cc:2693:MuxGate$23538 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[10] $abc$24881$new_n6473 i_pf_instruction[31] $abc$24881$new_n6525 +010 1 +100 1 +101 1 +111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[9] $abc$24881$new_n6454 $abc$24881$new_n6527 $abc$24881$auto$rtlil.cc:2693:MuxGate$23540 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[9] i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6527 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6528 +11110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[8] $abc$24881$new_n6455 $abc$24881$new_n6530 $abc$24881$auto$rtlil.cc:2693:MuxGate$23542 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[8] i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6530 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[7] $abc$24881$new_n6532 $abc$24881$new_n6533 $abc$24881$auto$rtlil.cc:2693:MuxGate$23544 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6532 +11 1 +.names i_pf_instruction_pc[7] i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6533 +011 1 +100 1 +101 1 +110 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[6] $abc$24881$new_n6456 $abc$24881$new_n6535 $abc$24881$auto$rtlil.cc:2693:MuxGate$23546 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[6] $abc$24881$new_n6528 $abc$24881$new_n6535 +01 1 +10 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[5] $abc$24881$new_n6457 $abc$24881$new_n6537 $abc$24881$auto$rtlil.cc:2693:MuxGate$23548 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[5] i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6537 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[4] $abc$24881$new_n6458 $abc$24881$new_n6539 $abc$24881$auto$rtlil.cc:2693:MuxGate$23550 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[4] i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6539 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[3] $abc$24881$new_n6541 $abc$24881$new_n6542 $abc$24881$auto$rtlil.cc:2693:MuxGate$23552 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_pc[1] instruction_decoder.o_pc[2] $abc$24881$new_n6541 +11 1 +.names i_pf_instruction_pc[3] i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6542 +010 1 +100 1 +101 1 +111 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6475 instruction_decoder.o_pc[2] instruction_decoder.o_pc[1] $abc$24881$new_n6544 $abc$24881$auto$rtlil.cc:2693:MuxGate$23554 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_pf_instruction_pc[2] i_pf_instruction[31] $abc$24881$new_n6544 +00 1 +11 1 +.names $abc$24881$new_n6546 $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[31] $abc$24881$new_n6568 $abc$24881$auto$rtlil.cc:2693:MuxGate$23556 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +11010 1 +11011 1 +.names $abc$24881$new_n9657 $abc$24881$new_n4071 $abc$24881$new_n5672 instruction_decoder.o_pc[31] SET_USER_PC.r_upc[31] $abc$24881$new_n6546 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6550 $abc$24881$new_n6552 $abc$24881$new_n6554 $abc$24881$new_n6549 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6551 regset[15][31] regset[11][31] $abc$24881$new_n6550 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[14][31] regset[10][31] $abc$24881$new_n6551 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6553 regset[7][31] regset[3][31] $abc$24881$new_n6552 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[6][31] regset[2][31] $abc$24881$new_n6553 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6555 regset[5][31] regset[1][31] $abc$24881$new_n6554 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[4][31] regset[0][31] $abc$24881$new_n6555 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6557 regset[13][31] regset[9][31] $abc$24881$new_n6556 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[12][31] regset[8][31] $abc$24881$new_n6557 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6559 $abc$24881$new_n6561 $abc$24881$new_n6563 $abc$24881$new_n6558 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6560 regset[23][31] regset[19][31] $abc$24881$new_n6559 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[22][31] regset[18][31] $abc$24881$new_n6560 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6562 regset[31][31] regset[27][31] $abc$24881$new_n6561 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[30][31] regset[26][31] $abc$24881$new_n6562 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[2] instruction_decoder.o_dcdA[0] $abc$24881$new_n6564 regset[21][31] regset[20][31] $abc$24881$new_n6563 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[0] regset[17][31] regset[16][31] $abc$24881$new_n6564 +000 1 +010 1 +100 1 +101 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] $abc$24881$new_n6567 regset[29][31] regset[25][31] $abc$24881$new_n6566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[2] regset[28][31] regset[24][31] $abc$24881$new_n6567 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6569 i_mem_result[31] wr_index[0] wr_index[1] $abc$24881$new_n6568 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names wr_index[1] wr_index[0] DIVIDE.thedivide.w_n doalu.n dbg_val[31] $abc$24881$new_n6569 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6576 $abc$24881$new_n5065 $abc$24881$new_n6577 $abc$24881$new_n6571 $abc$24881$new_n6572 $abc$24881$auto$rtlil.cc:2693:MuxGate$23558 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_I[31] $abc$24881$new_n5090 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n6571 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 $abc$24881$new_n6575 $abc$24881$new_n6573 $abc$24881$new_n6574 $abc$24881$new_n6572 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names dcd_I[31] $abc$24881$new_n5148 $abc$24881$new_n5147 $abc$24881$new_n5149 $abc$24881$new_n5113 $abc$24881$new_n6573 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11110 1 +.names $abc$24881$new_n5151 $abc$24881$new_n6568 $abc$24881$new_n6574 +10 1 +.names dcd_I[31] $abc$24881$new_n4068 SET_USER_PC.r_upc[31] instruction_decoder.o_pc[31] $abc$24881$new_n6575 +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names r_op_Bv[31] $abc$24881$new_n5151 $abc$24881$new_n5066 $abc$24881$new_n6576 +100 1 +.names dcd_I[31] $abc$24881$new_n6568 $abc$24881$new_n4373 $abc$24881$new_n4368 $abc$24881$new_n6578 $abc$24881$new_n6577 +00000 1 +00001 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n6579 $abc$24881$new_n6589 $abc$24881$new_n6596 $abc$24881$new_n6578 +00000 1 +00001 1 +00010 1 +00011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$24881$new_n6580 $abc$24881$new_n6587 $abc$24881$new_n4069 $abc$24881$new_n6579 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6581 $abc$24881$new_n6583 $abc$24881$new_n6585 $abc$24881$new_n6580 +00010 1 +00011 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6582 regset[7][31] regset[3][31] $abc$24881$new_n6581 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[6][31] regset[2][31] $abc$24881$new_n6582 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6584 regset[5][31] regset[1][31] $abc$24881$new_n6583 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[4][31] regset[0][31] $abc$24881$new_n6584 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6586 regset[13][31] regset[12][31] $abc$24881$new_n6585 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[9][31] regset[8][31] $abc$24881$new_n6586 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6588 regset[15][31] regset[14][31] $abc$24881$new_n6587 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[11][31] regset[10][31] $abc$24881$new_n6588 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n6590 $abc$24881$new_n6592 $abc$24881$new_n6594 $abc$24881$new_n6589 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6591 regset[29][31] regset[25][31] $abc$24881$new_n6590 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[28][31] regset[24][31] $abc$24881$new_n6591 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] $abc$24881$new_n6593 regset[31][31] regset[27][31] $abc$24881$new_n6592 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[2] regset[30][31] regset[26][31] $abc$24881$new_n6593 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n6595 regset[21][31] regset[20][31] $abc$24881$new_n6594 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] regset[17][31] regset[16][31] $abc$24881$new_n6595 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6597 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[22][31] regset[18][31] $abc$24881$new_n6596 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4356 instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[23][31] regset[19][31] $abc$24881$new_n6597 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n5066 $abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] r_op_F[6] $abc$24881$auto$rtlil.cc:2693:MuxGate$23560 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6600 op_wF $abc$24881$auto$rtlil.cc:2693:MuxGate$23562 +001 1 +011 1 +110 1 +111 1 +.names dcd_wF instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_wR dcd_Acc $abc$24881$new_n6600 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n5364 OP_REG_ADVANEC.r_op_rB $abc$24881$new_n5066 $abc$24881$auto$rtlil.cc:2693:MuxGate$23564 +010 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5066 OP_REG_ADVANEC.r_op_rA dcd_rA instruction_decoder.o_illegal instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23566 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11100 1 +.names $abc$24881$new_n5364 instruction_decoder.o_dcdB[4] OP_REG_ADVANEC.r_op_Bid[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23568 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.o_dcdA[4] o_mem_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23570 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 GEN_OP_WR.r_op_wR dcd_wR instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23572 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$24881$new_n5066 FWD_OPERATION.r_op_opn[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch dcd_opn[3] instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23576 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5373 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y o_mem_reg[4] i_dbg_wreg[4] alu_reg[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$23578 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.o_pc[1] i_pf_instruction[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23582 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4028 dcd_I[31] $abc$24881$new_n5443 $abc$24881$new_n4266 $abc$24881$new_n6610 $abc$24881$auto$rtlil.cc:2693:MuxGate$23584 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5440 $abc$24881$new_n4271 $abc$24881$new_n4287 $abc$24881$new_n6610 +100 1 +101 1 +111 1 +.names $abc$24881$new_n4028 instruction_decoder.r_nxt_half[14] i_pf_instruction[14] $abc$24881$auto$rtlil.cc:2693:MuxGate$23586 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_rB $abc$24881$new_n4258 $abc$24881$auto$rtlil.cc:2693:MuxGate$23588 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n6614 $abc$24881$new_n4028 dcd_rA $abc$24881$auto$rtlil.cc:2693:MuxGate$23590 +000 1 +001 1 +011 1 +.names $abc$24881$new_n6620 $abc$24881$new_n6615 $abc$24881$new_n6617 $abc$24881$new_n6616 $abc$24881$new_n6614 +1100 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4269 $abc$24881$new_n4261 $abc$24881$new_n4270 $abc$24881$new_n6615 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4282 $abc$24881$new_n6616 +10 1 +.names $abc$24881$new_n6618 $abc$24881$new_n4281 $abc$24881$new_n6619 $abc$24881$new_n4267 $abc$24881$new_n6617 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4269 $abc$24881$new_n4268 $abc$24881$new_n4267 $abc$24881$new_n6618 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +.names i_pf_instruction[25] $abc$24881$new_n4266 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6619 +1111 1 +.names $abc$24881$new_n6622 $abc$24881$new_n6621 $abc$24881$new_n6620 +00 1 +.names $abc$24881$new_n4276 $abc$24881$new_n4277 $abc$24881$new_n4273 $abc$24881$new_n4267 $abc$24881$new_n6621 +1000 1 +1001 1 +1010 1 +.names i_pf_instruction[25] $abc$24881$new_n4265 $abc$24881$new_n4266 $abc$24881$new_n4267 $abc$24881$new_n4273 $abc$24881$new_n6622 +11100 1 +.names $abc$24881$new_n4028 dcd_wR $abc$24881$new_n6615 $abc$24881$new_n4275 $abc$24881$new_n6616 $abc$24881$auto$rtlil.cc:2693:MuxGate$23592 +00100 1 +01100 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_lock $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23594 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.o_DV $abc$24881$new_n6622 $abc$24881$auto$rtlil.cc:2693:MuxGate$23596 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n4028 dcd_M $abc$24881$new_n4260 $abc$24881$auto$rtlil.cc:2693:MuxGate$23598 +001 1 +011 1 +110 1 +111 1 +.names dcd_ALU $abc$24881$new_n4028 $abc$24881$new_n6615 $abc$24881$new_n6628 $abc$24881$new_n6618 $abc$24881$auto$rtlil.cc:2693:MuxGate$23600 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4271 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n6628 +000 1 +001 1 +011 1 +.names $abc$24881$new_n4028 dcd_opn[3] $abc$24881$new_n4269 $abc$24881$auto$rtlil.cc:2693:MuxGate$23604 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n6615 $abc$24881$new_n4028 dcd_wF $abc$24881$new_n6633 $abc$24881$new_n6631 $abc$24881$auto$rtlil.cc:2693:MuxGate$23606 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4028 $abc$24881$new_n4274 $abc$24881$new_n4293 $abc$24881$new_n6632 $abc$24881$new_n6631 +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n4289 $abc$24881$new_n4291 $abc$24881$new_n6632 +10 1 +.names $abc$24881$new_n6620 $abc$24881$new_n6634 $abc$24881$new_n6617 $abc$24881$new_n6633 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n4277 $abc$24881$new_n4267 $abc$24881$new_n4268 $abc$24881$new_n4269 $abc$24881$new_n6634 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0111 1 +.names $abc$24881$new_n6631 dcd_F[3] $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23608 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n6637 dcd_zI $abc$24881$new_n4028 $abc$24881$auto$rtlil.cc:2693:MuxGate$23610 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5459 $abc$24881$new_n6639 $abc$24881$new_n6638 $abc$24881$new_n5438 $abc$24881$new_n6637 +1111 1 +.names $abc$24881$new_n4266 $abc$24881$new_n5449 $abc$24881$new_n5447 $abc$24881$new_n5445 $abc$24881$new_n6610 $abc$24881$new_n6638 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11111 1 +.names $abc$24881$new_n6640 $abc$24881$new_n5457 $abc$24881$new_n5454 $abc$24881$new_n5451 $abc$24881$new_n5461 $abc$24881$new_n6639 +11110 1 +.names $abc$24881$new_n6641 $abc$24881$new_n4266 i_pf_instruction[7] i_pf_instruction[8] $abc$24881$new_n6640 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n6642 $abc$24881$new_n5477 $abc$24881$new_n5474 $abc$24881$new_n5472 $abc$24881$new_n5469 $abc$24881$new_n6641 +11100 1 +.names $abc$24881$new_n6643 $abc$24881$new_n6644 $abc$24881$new_n4266 i_pf_instruction[2] $abc$24881$new_n4283 $abc$24881$new_n6642 +11001 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4266 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n5455 $abc$24881$new_n5442 $abc$24881$new_n6643 +00011 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$24881$new_n4266 i_pf_instruction[11] i_pf_instruction[12] i_pf_instruction[9] i_pf_instruction[10] $abc$24881$new_n6644 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +.names $abc$24881$new_n4028 dcd_Bcc $abc$24881$new_n4292 $abc$24881$new_n4257 $abc$24881$auto$rtlil.cc:2693:MuxGate$23612 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_Acc $abc$24881$new_n4302 $abc$24881$new_n4301 $abc$24881$auto$rtlil.cc:2693:MuxGate$23614 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 dcd_break $abc$24881$new_n4273 $abc$24881$new_n4275 $abc$24881$new_n4287 $abc$24881$auto$rtlil.cc:2693:MuxGate$23616 +00111 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names alu_ce $abc$24881$new_n6649 doalu.set_ovfl $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23618 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11110 1 +.names $abc$24881$new_n6650 $abc$24881$new_n6653 $abc$24881$new_n6655 $abc$24881$new_n6649 +000 1 +010 1 +100 1 +101 1 +.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6650 +01 1 +10 1 +.names $abc$24881$new_n5151 $abc$24881$new_n6568 r_op_Bv[31] o_mem_addr[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3692 $abc$24881$new_n6568 r_op_Av[31] o_mem_data[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n6654 DIVIDE.thedivide.i_signed $abc$24881$new_n6653 +10 1 +.names FWD_OPERATION.r_op_opn[3] o_mem_op[1] o_mem_op[2] $abc$24881$new_n6654 +000 1 +.names $abc$24881$new_n6656 DIVIDE.thedivide.i_signed $abc$24881$new_n6655 +10 1 +.names o_mem_op[1] FWD_OPERATION.r_op_opn[3] o_mem_op[2] $abc$24881$new_n6656 +100 1 +.names o_mem_op[2] FWD_OPERATION.r_op_opn[3] o_mem_op[1] DIVIDE.thedivide.i_signed $abc$24881$new_n6657 +1001 1 +1010 1 +1011 1 +.names o_mem_op[2] DIVIDE.thedivide.i_signed o_mem_op[1] FWD_OPERATION.r_op_opn[3] $abc$24881$new_n6658 +1110 1 +.names alu_ce $abc$24881$new_n6649 doalu.keep_sgn_on_ovfl $abc$24881$auto$rtlil.cc:2693:MuxGate$23620 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[28] o_mem_data[28] o_mem_addr[29] o_mem_data[29] $abc$24881$new_n6663 $abc$24881$new_n6662 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[26] o_mem_data[26] o_mem_addr[27] o_mem_data[27] $abc$24881$new_n6664 $abc$24881$new_n6663 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[24] o_mem_data[24] o_mem_addr[25] o_mem_data[25] $abc$24881$new_n6665 $abc$24881$new_n6664 +00110 1 +00111 1 +01011 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[22] o_mem_data[22] o_mem_addr[23] o_mem_data[23] $abc$24881$new_n6666 $abc$24881$new_n6665 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[20] o_mem_data[20] o_mem_addr[21] o_mem_data[21] $abc$24881$new_n6667 $abc$24881$new_n6666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[18] o_mem_data[18] o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6668 $abc$24881$new_n6667 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[16] o_mem_data[16] o_mem_addr[17] o_mem_data[17] $abc$24881$new_n6669 $abc$24881$new_n6668 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[14] o_mem_data[14] o_mem_addr[15] o_mem_data[15] $abc$24881$new_n6670 $abc$24881$new_n6669 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[12] o_mem_data[12] o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6671 $abc$24881$new_n6670 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01100 1 +10000 1 +10001 1 +10010 1 +10100 1 +11000 1 +11001 1 +.names o_mem_addr[10] o_mem_data[10] o_mem_addr[11] o_mem_data[11] $abc$24881$new_n6672 $abc$24881$new_n6671 +00110 1 +00111 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[8] o_mem_data[8] o_mem_addr[9] o_mem_data[9] $abc$24881$new_n6673 $abc$24881$new_n6672 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names o_mem_addr[6] o_mem_data[6] o_mem_addr[7] o_mem_data[7] $abc$24881$new_n6674 $abc$24881$new_n6673 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names o_mem_addr[4] o_mem_data[4] o_mem_addr[5] o_mem_data[5] $abc$24881$new_n9661 $abc$24881$new_n6674 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11000 1 +11001 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3692 $abc$24881$new_n3853 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n6678 +00011 1 +00111 1 +01001 1 +01011 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5151 $abc$24881$new_n3692 r_op_Av[2] r_op_Bv[2] $abc$24881$new_n3853 $abc$24881$new_n6679 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01011 1 +01100 1 +01111 1 +10000 1 +10010 1 +10101 1 +10111 1 +.names o_mem_addr[0] o_mem_data[0] o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6680 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6682 +11 1 +.names o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6683 +01 1 +10 1 +.names $abc$24881$new_n6723 $abc$24881$new_n6788 $abc$24881$new_n6686 $abc$24881$new_n6650 $abc$24881$new_n6685 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6722 $abc$24881$new_n6683 $abc$24881$new_n6687 $abc$24881$new_n6686 +000 1 +.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6720 $abc$24881$new_n6687 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6719 $abc$24881$new_n6689 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6718 $abc$24881$new_n6688 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6717 $abc$24881$new_n6690 o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6716 $abc$24881$new_n6689 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10100 1 +10110 1 +11000 1 +11100 1 +11110 1 +.names $abc$24881$new_n6714 o_mem_addr[22] $abc$24881$new_n6691 $abc$24881$new_n6715 o_mem_data[22] $abc$24881$new_n6690 +00000 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +.names $abc$24881$new_n6711 o_mem_addr[20] $abc$24881$new_n6692 o_mem_data[20] $abc$24881$new_n6713 $abc$24881$new_n6691 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01110 1 +10010 1 +10100 1 +10110 1 +11110 1 +.names o_mem_addr[17] $abc$24881$new_n6693 $abc$24881$new_n6710 o_mem_data[17] $abc$24881$new_n6707 $abc$24881$new_n6692 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10111 1 +11011 1 +11111 1 +.names o_mem_addr[15] $abc$24881$new_n6694 $abc$24881$new_n6706 o_mem_data[15] $abc$24881$new_n6705 $abc$24881$new_n6693 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10110 1 +11010 1 +11110 1 +.names $abc$24881$new_n6701 $abc$24881$new_n6704 $abc$24881$new_n6695 $abc$24881$new_n6703 $abc$24881$new_n6702 $abc$24881$new_n6694 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names o_mem_data[10] o_mem_addr[10] o_mem_addr[11] o_mem_data[11] $abc$24881$new_n6696 $abc$24881$new_n6695 +00000 1 +00010 1 +00011 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11110 1 +.names o_mem_addr[8] o_mem_addr[9] o_mem_data[8] o_mem_data[9] $abc$24881$new_n6697 $abc$24881$new_n6696 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[6] o_mem_addr[7] o_mem_data[6] o_mem_data[7] $abc$24881$new_n6698 $abc$24881$new_n6697 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[4] o_mem_addr[5] o_mem_data[4] o_mem_data[5] $abc$24881$new_n6699 $abc$24881$new_n6698 +00001 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +10000 1 +10001 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n6700 o_mem_addr[2] o_mem_data[2] o_mem_data[3] $abc$24881$new_n6699 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_addr[1] o_mem_data[0] o_mem_data[1] $abc$24881$new_n6700 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6701 +00 1 +11 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6702 +01 1 +10 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6703 +01 1 +10 1 +.names o_mem_data[12] o_mem_addr[12] o_mem_addr[13] o_mem_data[13] $abc$24881$new_n6704 +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6705 +01 1 +10 1 +.names o_mem_data[14] o_mem_addr[14] $abc$24881$new_n6706 +10 1 +.names $abc$24881$new_n6709 $abc$24881$new_n6708 $abc$24881$new_n6707 +00 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6708 +01 1 +10 1 +.names o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6709 +01 1 +10 1 +.names o_mem_data[16] o_mem_addr[16] $abc$24881$new_n6710 +10 1 +.names o_mem_addr[19] o_mem_data[19] $abc$24881$new_n6712 $abc$24881$new_n6711 +000 1 +100 1 +101 1 +110 1 +.names o_mem_data[18] o_mem_addr[18] $abc$24881$new_n6712 +10 1 +.names o_mem_addr[21] o_mem_data[21] $abc$24881$new_n6713 +10 1 +.names o_mem_data[23] o_mem_addr[23] $abc$24881$new_n6714 +10 1 +.names o_mem_data[21] o_mem_addr[21] $abc$24881$new_n6715 +10 1 +.names o_mem_data[25] o_mem_addr[25] $abc$24881$new_n6716 +10 1 +.names o_mem_addr[23] o_mem_data[23] $abc$24881$new_n6717 +10 1 +.names o_mem_data[27] o_mem_addr[27] $abc$24881$new_n6718 +10 1 +.names o_mem_addr[25] o_mem_data[25] $abc$24881$new_n6719 +10 1 +.names o_mem_data[29] o_mem_addr[29] $abc$24881$new_n6720 +10 1 +.names o_mem_addr[27] o_mem_data[27] $abc$24881$new_n6721 +10 1 +.names o_mem_addr[29] o_mem_data[29] $abc$24881$new_n6722 +10 1 +.names $abc$24881$new_n6657 $abc$24881$new_n6724 $abc$24881$new_n6787 $abc$24881$new_n6785 $abc$24881$new_n6751 $abc$24881$new_n6723 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6777 $abc$24881$new_n6658 $abc$24881$new_n9664 $abc$24881$new_n6784 o_mem_addr[5] $abc$24881$new_n6724 +10000 1 +10010 1 +10011 1 +.names o_mem_addr[3] $abc$24881$new_n6728 $abc$24881$new_n6733 $abc$24881$new_n6727 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6729 $abc$24881$new_n6731 $abc$24881$new_n6728 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6730 o_mem_data[14] o_mem_data[13] $abc$24881$new_n6729 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[16] o_mem_data[15] $abc$24881$new_n6730 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6732 o_mem_data[10] o_mem_data[9] $abc$24881$new_n6731 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[12] o_mem_data[11] $abc$24881$new_n6732 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n6734 $abc$24881$new_n6736 $abc$24881$new_n6733 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6735 o_mem_data[6] o_mem_data[5] $abc$24881$new_n6734 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[8] o_mem_data[7] $abc$24881$new_n6735 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] $abc$24881$new_n6737 $abc$24881$new_n6738 $abc$24881$new_n6736 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[4] o_mem_data[3] $abc$24881$new_n6737 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[2] o_mem_data[1] $abc$24881$new_n6738 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] $abc$24881$new_n6742 $abc$24881$new_n6743 $abc$24881$new_n6741 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[28] o_mem_data[27] $abc$24881$new_n6742 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[26] o_mem_data[25] $abc$24881$new_n6743 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6744 +00 1 +.names o_mem_addr[0] o_mem_addr[1] o_mem_data[30] o_mem_data[29] o_mem_data[31] $abc$24881$new_n6745 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n6747 $abc$24881$new_n6749 $abc$24881$new_n6746 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6748 o_mem_data[24] o_mem_data[23] $abc$24881$new_n6747 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[22] o_mem_data[21] $abc$24881$new_n6748 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6750 o_mem_data[20] o_mem_data[19] $abc$24881$new_n6749 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[18] o_mem_data[17] $abc$24881$new_n6750 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[4] $abc$24881$new_n6769 $abc$24881$new_n6752 $abc$24881$new_n6764 o_mem_addr[3] $abc$24881$new_n6751 +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names o_mem_addr[3] $abc$24881$new_n6753 $abc$24881$new_n6759 $abc$24881$new_n6752 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6754 $abc$24881$new_n6757 $abc$24881$new_n6753 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6755 $abc$24881$new_n6756 $abc$24881$new_n6754 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[16] o_mem_data[15] $abc$24881$new_n6755 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[18] o_mem_data[17] $abc$24881$new_n6756 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6758 o_mem_data[20] o_mem_data[19] $abc$24881$new_n6757 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[22] o_mem_data[21] $abc$24881$new_n6758 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n6760 $abc$24881$new_n6762 $abc$24881$new_n6759 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6761 o_mem_data[24] o_mem_data[23] $abc$24881$new_n6760 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[26] o_mem_data[25] $abc$24881$new_n6761 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6763 o_mem_data[28] o_mem_data[27] $abc$24881$new_n6762 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[30] o_mem_data[29] $abc$24881$new_n6763 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6767 $abc$24881$new_n6764 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6766 o_mem_data[10] o_mem_data[9] $abc$24881$new_n6765 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[8] o_mem_data[7] $abc$24881$new_n6766 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6768 o_mem_data[14] o_mem_data[13] $abc$24881$new_n6767 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[12] o_mem_data[11] $abc$24881$new_n6768 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n6770 $abc$24881$new_n6773 $abc$24881$new_n6769 +1001 1 +1011 1 +1100 1 +1101 1 +.names o_mem_addr[1] $abc$24881$new_n6771 $abc$24881$new_n6772 $abc$24881$new_n6770 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[4] o_mem_data[3] $abc$24881$new_n6771 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[6] o_mem_data[5] $abc$24881$new_n6772 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] $abc$24881$new_n6774 $abc$24881$new_n6775 $abc$24881$new_n6773 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[2] o_mem_data[1] $abc$24881$new_n6774 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[0] $abc$24881$new_n6775 +11 1 +.names o_mem_op[1] o_mem_op[2] FWD_OPERATION.r_op_opn[3] DIVIDE.thedivide.i_signed $abc$24881$new_n6776 +1100 1 +.names $abc$24881$new_n6781 $abc$24881$new_n6778 $abc$24881$new_n6783 o_mem_addr[29] o_mem_addr[30] $abc$24881$new_n6777 +11100 1 +.names $abc$24881$new_n6779 o_mem_addr[31] o_mem_addr[6] o_mem_addr[7] o_mem_addr[8] $abc$24881$new_n6778 +10000 1 +.names $abc$24881$new_n6780 o_mem_addr[11] o_mem_addr[13] o_mem_addr[15] o_mem_addr[17] $abc$24881$new_n6779 +10000 1 +.names o_mem_addr[21] o_mem_addr[23] o_mem_addr[25] o_mem_addr[26] $abc$24881$new_n6780 +0000 1 +.names $abc$24881$new_n6782 o_mem_addr[9] o_mem_addr[10] o_mem_addr[12] o_mem_addr[14] $abc$24881$new_n6781 +10000 1 +.names o_mem_addr[16] o_mem_addr[18] o_mem_addr[19] o_mem_addr[20] $abc$24881$new_n6782 +0000 1 +.names o_mem_addr[22] o_mem_addr[24] o_mem_addr[27] o_mem_addr[28] $abc$24881$new_n6783 +0000 1 +.names $abc$24881$new_n6744 o_mem_addr[0] o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n6784 +1000 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 $abc$24881$new_n6785 +11 1 +.names $abc$24881$new_n6777 o_mem_addr[5] $abc$24881$new_n6786 +10 1 +.names $abc$24881$new_n6658 o_mem_data[31] $abc$24881$new_n6786 $abc$24881$new_n6787 +110 1 +.names o_mem_data[30] o_mem_data[31] o_mem_addr[30] o_mem_addr[31] $abc$24881$new_n6653 $abc$24881$new_n6788 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01111 1 +10011 1 +10101 1 +10111 1 +11111 1 +.names alu_ce o_mem_data[31] doalu.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$23624 +001 1 +011 1 +110 1 +111 1 +.names op_valid_div $abc$24881$new_n5375 $abc$24881$new_n4031 DIVIDE.thedivide.i_wr +111 1 +.names $abc$24881$new_n5383 DIVIDE.thedivide.zero_divisor $abc$24881$new_n6786 $abc$24881$new_n6784 $abc$24881$auto$rtlil.cc:2693:MuxGate$23626 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n4085 $abc$24881$auto$rtlil.cc:2693:MuxGate$23628 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n6794 $abc$24881$auto$rtlil.cc:2693:MuxGate$23630 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6796 $abc$24881$new_n6795 $abc$24881$new_n6798 instruction_decoder.o_dcdB[3] $abc$24881$new_n4284 $abc$24881$new_n6794 +11100 1 +11111 1 +.names $abc$24881$new_n4260 $abc$24881$new_n4258 $abc$24881$new_n6795 +10 1 +.names $abc$24881$new_n6797 dcd_opn[0] $abc$24881$new_n4282 instruction_decoder.o_dcdB[2] $abc$24881$new_n4288 $abc$24881$new_n6796 +10100 1 +10111 1 +11000 1 +11011 1 +.names instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6797 +101 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[1] $abc$24881$new_n4290 $abc$24881$new_n4292 $abc$24881$new_n6798 +0011 1 +0101 1 +1010 1 +1100 1 +.names $abc$24881$new_n6795 $abc$24881$new_n4277 $abc$24881$new_n4284 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n6801 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n4085 $abc$24881$flatten\instruction_decoder.$procmux$2071_Y $abc$24881$auto$rtlil.cc:2693:MuxGate$23634 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_instruction[30] $abc$24881$new_n6806 i_pf_instruction[21] i_pf_instruction[25] $abc$24881$flatten\instruction_decoder.$procmux$2071_Y +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction[29] $abc$24881$new_n6807 i_pf_instruction[20] i_pf_instruction[24] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6806 +11000 1 +.names $abc$24881$new_n6808 i_pf_instruction[23] i_pf_instruction[28] i_pf_instruction[27] i_pf_instruction[26] $abc$24881$new_n6807 +11110 1 +.names i_pf_instruction[31] i_pf_instruction[18] i_pf_instruction[19] i_pf_instruction[22] $abc$24881$new_n6808 +0000 1 +.names $abc$24881$new_n6475 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb $abc$24881$new_n6810 $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$auto$rtlil.cc:2693:MuxGate$23636 +00001 1 +00011 1 +00101 1 +00111 1 +01011 1 +01100 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6820 $abc$24881$new_n4277 $abc$24881$new_n4286 $abc$24881$new_n6811 $abc$24881$new_n6818 $abc$24881$new_n6810 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6812 $abc$24881$new_n4293 $abc$24881$new_n6816 $abc$24881$new_n6814 $abc$24881$new_n5455 $abc$24881$new_n6811 +11110 1 +.names i_pf_instruction[17] $abc$24881$new_n6632 $abc$24881$new_n6813 $abc$24881$new_n4085 instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6812 +11110 1 +.names i_pf_instruction[14] i_pf_instruction[31] i_pf_instruction[11] i_pf_instruction[12] $abc$24881$new_n6813 +1000 1 +.names i_pf_instruction[15] i_pf_instruction[18] $abc$24881$new_n6815 i_pf_instruction[0] i_pf_instruction[1] $abc$24881$new_n6814 +11100 1 +.names i_pf_instruction[2] i_pf_instruction[3] i_pf_instruction[4] i_pf_instruction[5] $abc$24881$new_n6815 +0000 1 +.names $abc$24881$new_n6817 $abc$24881$new_n4287 i_pf_instruction[10] i_pf_instruction[13] $abc$24881$new_n4273 $abc$24881$new_n6816 +11000 1 +.names i_pf_instruction[6] i_pf_instruction[7] i_pf_instruction[8] i_pf_instruction[9] $abc$24881$new_n6817 +0000 1 +.names $abc$24881$new_n4291 $abc$24881$new_n6819 $abc$24881$new_n4283 $abc$24881$new_n4289 $abc$24881$new_n4293 $abc$24881$new_n6818 +11100 1 +.names instruction_decoder.GEN_CIS_PHASE.r_phase instruction_decoder.r_nxt_half[7] $abc$24881$new_n5442 $abc$24881$new_n5455 $abc$24881$new_n4287 $abc$24881$new_n6819 +11110 1 +.names $abc$24881$new_n4267 $abc$24881$new_n4302 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp i_pf_valid $abc$24881$new_n6820 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction[31] $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23638 +00110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_valid o_pf_ready instruction_decoder.o_illegal $abc$24881$new_n6825 $abc$24881$new_n6823 $abc$24881$auto$rtlil.cc:2693:MuxGate$23640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n4277 $abc$24881$new_n6622 $abc$24881$new_n4269 $abc$24881$new_n6824 $abc$24881$new_n4261 $abc$24881$new_n6823 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4270 $abc$24881$new_n4262 $abc$24881$new_n4277 $abc$24881$new_n4282 $abc$24881$new_n4268 $abc$24881$new_n6824 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_illegal $abc$24881$new_n6621 $abc$24881$new_n4275 $abc$24881$new_n4273 $abc$24881$new_n4287 $abc$24881$new_n6825 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names $abc$24881$new_n6827 o_mem_addr[31] DIVIDE.thedivide.r_busy $abc$24881$auto$rtlil.cc:2693:MuxGate$23642 +000 1 +001 1 +010 1 +011 1 +110 1 +.names DIVIDE.thedivide.r_divisor[31] DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n6828 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n6827 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n5512 DIVIDE.thedivide.r_divisor[29] $abc$24881$new_n6828 +10 1 +.names $abc$24881$new_n5531 DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n5529 $abc$24881$new_n6828 o_mem_addr[30] $abc$24881$auto$rtlil.cc:2693:MuxGate$23644 +00001 1 +00011 1 +01001 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_z $abc$24881$new_n3867 $abc$24881$new_n3829 $abc$24881$auto$rtlil.cc:2693:MuxGate$23646 +100 1 +110 1 +111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.o_valid $abc$24881$auto$rtlil.cc:2693:MuxGate$23648 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6834 $abc$24881$new_n5383 $abc$24881$auto$rtlil.cc:2693:MuxGate$23650 +01 1 +10 1 +11 1 +.names DIVIDE.thedivide.o_busy DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor DIVIDE.thedivide.last_bit DIVIDE.thedivide.r_sign $abc$24881$new_n6834 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n5383 DIVIDE.thedivide.r_busy DIVIDE.thedivide.last_bit DIVIDE.thedivide.zero_divisor $abc$24881$auto$rtlil.cc:2693:MuxGate$23652 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n3957 $abc$24881$new_n3960 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] SET_USER_PC.r_upc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23654 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names wr_index[1] wr_index[0] doalu.n i_mem_result[31] dbg_val[31] $abc$24881$new_n6837 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names SET_GIE.r_gie $abc$24881$new_n3957 $abc$24881$new_n6840 $abc$24881$new_n6839 GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23656 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names wr_index[0] wr_index[1] $abc$24881$new_n3860 i_mem_result[1] $abc$24881$new_n6839 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1110 1 +1111 1 +.names r_alu_pc_valid DIVIDE.thedivide.o_busy GEN_UHALT_PHASE.r_uhalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$new_n6840 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_i_count SET_GIE.r_gie GEN_IHALT_PHASE.r_ihalt_phase GEN_ALU_PHASE.r_alu_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23658 +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6843 DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23660 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie dbgv $abc$24881$new_n6843 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6845 DIVERR.r_idiv_err_flag $abc$24881$new_n4001 DIVIDE.thedivide.o_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23662 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names dbgv $abc$24881$new_n3697 $abc$24881$new_n3694 $abc$24881$new_n4036 $abc$24881$new_n6845 +1111 1 +.names $abc$24881$new_n6843 SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23664 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6843 SET_USER_ILLEGAL_INSN.r_ill_err_u $abc$24881$new_n4007 SET_ALU_ILLEGAL.r_alu_illegal $abc$24881$new_n4402 $abc$24881$auto$rtlil.cc:2693:MuxGate$23666 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names SET_TRAP_N_UBREAK.r_ubreak GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n4077 $abc$24881$new_n6843 $abc$24881$new_n4009 $abc$24881$auto$rtlil.cc:2693:MuxGate$23668 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names SET_TRAP_N_UBREAK.r_trap SET_GIE.r_gie $abc$24881$new_n6850 dbgv $abc$24881$new_n4005 $abc$24881$auto$rtlil.cc:2693:MuxGate$23670 +01000 1 +01001 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6850 +000 1 +001 1 +010 1 +011 1 +110 1 +.names SET_GIE.r_gie $abc$24881$new_n4082 $abc$24881$auto$rtlil.cc:2693:MuxGate$23672 +01 1 +10 1 +11 1 +.names $abc$24881$new_n6853 op_illegal $abc$24881$new_n4031 $abc$24881$auto$rtlil.cc:2693:MuxGate$23674 +000 1 +001 1 +010 1 +011 1 +111 1 +.names i_interrupt GEN_PENDING_BREAK.r_break_pending GEN_PENDING_INTERRUPT.r_pending_interrupt $abc$24881$new_n6854 $abc$24881$new_n6853 +0000 1 +.names user_step GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n3959 $abc$24881$new_n6855 $abc$24881$new_n6854 +1100 1 +1101 1 +1111 1 +.names i_mem_busy DIVIDE.thedivide.o_busy $abc$24881$new_n6855 +00 1 +.names GEN_PENDING_INTERRUPT.r_user_stepped $abc$24881$new_n6857 $abc$24881$auto$rtlil.cc:2693:MuxGate$23676 +01 1 +10 1 +11 1 +.names GEN_OPLOCK.r_op_lock OPT_CIS_OP_PHASE.r_op_phase BUSLOCK.r_bus_lock[1] $abc$24881$new_n4030 $abc$24881$new_n6857 +0000 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y SET_GIE.r_gie $abc$24881$new_n4013 sleep $abc$24881$new_n6859 $abc$24881$auto$rtlil.cc:2693:MuxGate$23678 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4015 i_interrupt SET_GIE.r_gie $abc$24881$new_n4013 $abc$24881$new_n6859 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names GEN_PENDING_BREAK.r_break_pending $abc$24881$new_n3959 $abc$24881$new_n6855 r_op_break $abc$24881$new_n4046 $abc$24881$auto$rtlil.cc:2693:MuxGate$23680 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names BUSLOCK.r_bus_lock[1] BUSLOCK.r_bus_lock[0] $abc$24881$new_n4030 GEN_OPLOCK.r_op_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23682 +0001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n6863 GEN_OPLOCK.r_op_lock $abc$24881$new_n4031 o_bus_lock $abc$24881$auto$rtlil.cc:2693:MuxGate$23684 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names BUSLOCK.r_prelock_stall instruction_decoder.r_valid op_valid i_pf_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6863 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +.names $abc$24881$new_n4030 GEN_ALU_PHASE.r_alu_phase OPT_CIS_OP_PHASE.r_op_phase $abc$24881$auto$rtlil.cc:2693:MuxGate$23686 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_CIS_PHASE.r_phase OPT_CIS_OP_PHASE.r_op_phase dcd_Apc dcd_wR $abc$24881$auto$rtlil.cc:2693:MuxGate$23688 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 GEN_OPLOCK.r_op_lock instruction_decoder.o_lock instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23690 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6868 op_valid_mem instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$auto$rtlil.cc:2693:MuxGate$23692 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names GEN_OP_PIPE.r_op_pipe mem_ce $abc$24881$new_n5152 $abc$24881$new_n5155 $abc$24881$new_n6868 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n6870 $abc$24881$new_n4030 i_mem_rdbusy GEN_OP_STALL.r_pending_sreg_write $abc$24881$auto$rtlil.cc:2693:MuxGate$23694 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names o_mem_reg[1] o_mem_reg[2] o_mem_reg[3] $abc$24881$new_n6871 $abc$24881$new_n4066 $abc$24881$new_n6870 +11110 1 +.names $abc$24881$new_n5375 GEN_OP_WR.r_op_wR op_illegal $abc$24881$new_n6871 +110 1 +.names $abc$24881$new_n5333 $abc$24881$new_n5334 $abc$24881$new_n6837 GEN_ALU_PC.r_alu_pc[31] ipc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23696 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6845 ibus_err_flag $abc$24881$new_n4003 i_bus_err SET_GIE.r_gie $abc$24881$auto$rtlil.cc:2693:MuxGate$23698 +00010 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names ill_err_i $abc$24881$new_n6845 $abc$24881$new_n6875 $abc$24881$new_n4007 $abc$24881$auto$rtlil.cc:2693:MuxGate$23700 +0010 1 +0011 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1110 1 +.names SET_ALU_ILLEGAL.r_alu_illegal new_pc SET_GIE.r_gie $abc$24881$new_n6875 +100 1 +.names $abc$24881$new_n4079 SET_GIE.r_gie user_step $abc$24881$new_n4011 $abc$24881$auto$rtlil.cc:2693:MuxGate$23702 +0010 1 +0011 1 +0110 1 +0111 1 +1000 1 +1010 1 +1110 1 +1111 1 +.names $abc$24881$new_n4083 $abc$24881$new_n4009 break_en $abc$24881$auto$rtlil.cc:2693:MuxGate$23704 +001 1 +011 1 +100 1 +101 1 +.names OPT_CIS_OP_PHASE.r_op_phase $abc$24881$new_n4031 DIVIDE.thedivide.o_busy r_alu_pc_valid new_pc $abc$24881$auto$rtlil.cc:2693:MuxGate$23706 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n4030 wr_index[1] op_valid_div op_valid_alu $abc$24881$auto$rtlil.cc:2693:MuxGate$23708 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n6881 op_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23710 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_illegal instruction_decoder.r_valid instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6881 +1100 1 +.names $abc$24881$new_n5066 r_op_break dcd_break instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23712 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11110 1 +.names $abc$24881$new_n6884 op_valid $abc$24881$new_n4030 $abc$24881$auto$rtlil.cc:2693:MuxGate$23714 +011 1 +100 1 +101 1 +110 1 +111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp $abc$24881$new_n6884 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6886 op_valid_mem $abc$24881$new_n6887 dcd_M instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23716 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 $abc$24881$new_n5066 $abc$24881$new_n6886 +10 1 +.names $abc$24881$new_n5066 instruction_decoder.r_valid new_pc instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$new_n6887 +11000 1 +.names $abc$24881$new_n6887 op_valid_alu $abc$24881$new_n6886 dcd_ALU instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23718 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6886 op_valid_div $abc$24881$new_n6887 instruction_decoder.o_DV instruction_decoder.o_illegal $abc$24881$auto$rtlil.cc:2693:MuxGate$23720 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6475 instruction_decoder.o_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase $abc$24881$new_n6891 $abc$24881$new_n6892 $abc$24881$auto$rtlil.cc:2693:MuxGate$23722 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names instruction_decoder.o_pc[30] $abc$24881$new_n6441 $abc$24881$new_n6891 +11 1 +.names i_pf_instruction_pc[31] instruction_decoder.GEN_CIS_PHASE.r_phase i_pf_instruction_pc[30] $abc$24881$new_n6460 i_pf_instruction[31] $abc$24881$new_n6892 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6894 $abc$24881$new_n4266 $abc$24881$auto$rtlil.cc:2693:MuxGate$23724 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[31] i_pf_instruction[17] i_pf_instruction_pc[30] $abc$24881$new_n6365 $abc$24881$new_n6894 +0000 1 +0001 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1101 1 +.names $abc$24881$new_n5066 SET_OP_PC.r_op_pc[1] instruction_decoder.o_pc[1] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch $abc$24881$auto$rtlil.cc:2693:MuxGate$23728 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names $abc$24881$new_n3829 $abc$24881$new_n6897 DIVIDE.thedivide.r_dividend[62] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23732 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[61] DIVIDE.thedivide.r_divisor[30] $abc$24881$new_n3869 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n6897 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10010 1 +10011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n3829 $abc$24881$new_n6899 DIVIDE.thedivide.r_dividend[32] $abc$24881$new_n3704 $abc$24881$auto$rtlil.cc:2693:MuxGate$23734 +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] $abc$24881$new_n3867 $abc$24881$new_n6899 +000 1 +001 1 +011 1 +110 1 +.names $abc$24881$new_n6901 ipc[31] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$23736 +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$24881$new_n6902 $abc$24881$new_n6837 $abc$24881$new_n4122 $abc$24881$new_n4125 pf_pc[31] $abc$24881$new_n6901 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n4103 $abc$24881$new_n4121 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] $abc$24881$new_n6903 $abc$24881$new_n6904 $abc$24881$new_n6902 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] $abc$24881$new_n4106 $abc$24881$new_n6903 +111 1 +.names $abc$24881$new_n4024 pf_pc[31] $abc$24881$new_n6905 SET_USER_PC.r_upc[31] $abc$24881$new_n4087 $abc$24881$new_n6904 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names pf_pc[28] pf_pc[29] pf_pc[30] $abc$24881$new_n4090 $abc$24881$new_n6905 +1111 1 +.names $abc$24881$new_n5066 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch SET_OP_PC.r_op_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] instruction_decoder.o_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4030 GEN_ALU_PC.r_alu_pc[31] SET_OP_PC.r_op_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23740 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5407 $abc$24881$new_n6909 o_mem_lock_pc[31] $abc$24881$auto$rtlil.cc:2693:MuxGate$23742 +001 1 +011 1 +110 1 +111 1 +.names SET_OP_PC.r_op_pc[31] $abc$24881$new_n5393 SET_OP_PC.r_op_pc[29] SET_OP_PC.r_op_pc[30] $abc$24881$new_n6909 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_clear_icache DIVIDE.thedivide.i_reset instruction_decoder.i_reset +01 1 +10 1 +11 1 +.names new_pc i_reset DIVIDE.thedivide.i_reset +01 1 +10 1 +11 1 +.names $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y o_pf_ready $abc$24881$new_n4085 i_pf_illegal $abc$24881$auto$opt_dff.cc:253:combine_resets$3478 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.i_reset $abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n4028 dcd_F[1] $abc$24881$new_n4291 $abc$24881$new_n4274 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] $abc$24881$auto$opt_dff.cc:253:combine_resets$4528 +00 1 +01 1 +11 1 +.names $abc$24881$new_n4028 dcd_F[2] $abc$24881$new_n4274 $abc$24881$new_n4289 $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +0010 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4085 instruction_decoder.i_reset $abc$24881$new_n4028 $abc$24881$auto$opt_dff.cc:253:combine_resets$3474 +000 1 +001 1 +010 1 +011 1 +101 1 +110 1 +111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3460 +00 1 +01 1 +11 1 +.names $abc$24881$new_n3829 DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +00 1 +01 1 +11 1 +.names $abc$24881$new_n4078 i_reset $abc$24881$new_n4046 $abc$24881$new_n4402 $abc$24881$auto$opt_dff.cc:253:combine_resets$3429 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n4031 new_pc $abc$24881$auto$opt_dff.cc:253:combine_resets$3420 +00 1 +01 1 +11 1 +.names $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y $abc$24881$new_n4035 $abc$24881$auto$opt_dff.cc:253:combine_resets$3407 +01 1 +10 1 +11 1 +.names r_halted i_reset $abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y +00 1 +01 1 +11 1 +.names $abc$24881$new_n4105 i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3404 +00 1 +01 1 +11 1 +.names $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y DIVIDE.thedivide.i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3389 +00 1 +01 1 +11 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] +11 1 +.names alu_ce i_reset $abc$24881$auto$opt_dff.cc:253:combine_resets$3485 +00 1 +01 1 +11 1 +.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[0] $abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y +11110 1 +.names $abc$24881$new_n6931 $abc$24881$new_n6930 $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y +11 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n6930 +11 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n6931 +11 1 +.names $abc$24881$new_n6933 DIVIDE.thedivide.r_dividend[62] DIVIDE.thedivide.r_divisor[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y +100 1 +111 1 +.names $abc$24881$new_n6934 $abc$24881$new_n6949 DIVIDE.thedivide.r_divisor[29] DIVIDE.thedivide.r_dividend[60] $abc$24881$new_n6933 +1100 1 +1111 1 +.names $abc$24881$new_n6935 DIVIDE.thedivide.r_divisor[27] DIVIDE.thedivide.r_dividend[58] $abc$24881$new_n3887 $abc$24881$new_n6934 +1000 1 +1110 1 +.names $abc$24881$new_n6936 DIVIDE.thedivide.r_divisor[25] DIVIDE.thedivide.r_dividend[56] $abc$24881$new_n3892 $abc$24881$new_n6935 +1000 1 +1110 1 +.names $abc$24881$new_n6937 DIVIDE.thedivide.r_divisor[23] DIVIDE.thedivide.r_dividend[54] $abc$24881$new_n3897 $abc$24881$new_n6936 +1000 1 +1110 1 +.names $abc$24881$new_n6938 DIVIDE.thedivide.r_divisor[21] DIVIDE.thedivide.r_dividend[52] $abc$24881$new_n3902 $abc$24881$new_n6937 +1000 1 +1110 1 +.names $abc$24881$new_n6939 DIVIDE.thedivide.r_divisor[19] DIVIDE.thedivide.r_dividend[50] $abc$24881$new_n3907 $abc$24881$new_n6938 +1000 1 +1110 1 +.names $abc$24881$new_n9670 DIVIDE.thedivide.r_divisor[17] DIVIDE.thedivide.r_dividend[48] $abc$24881$new_n3912 $abc$24881$new_n6939 +1000 1 +1110 1 +.names $abc$24881$new_n6944 DIVIDE.thedivide.r_divisor[9] DIVIDE.thedivide.r_dividend[40] $abc$24881$new_n3937 $abc$24881$new_n6943 +1000 1 +1110 1 +.names $abc$24881$new_n6945 DIVIDE.thedivide.r_divisor[7] DIVIDE.thedivide.r_dividend[38] $abc$24881$new_n3942 $abc$24881$new_n6944 +1000 1 +1110 1 +.names $abc$24881$new_n6946 DIVIDE.thedivide.r_divisor[5] DIVIDE.thedivide.r_dividend[36] $abc$24881$new_n3947 $abc$24881$new_n6945 +1000 1 +1110 1 +.names $abc$24881$new_n6947 $abc$24881$new_n3953 $abc$24881$new_n3950 $abc$24881$new_n6946 +100 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[0] DIVIDE.thedivide.r_dividend[32] DIVIDE.thedivide.r_divisor[1] $abc$24881$new_n6947 +10000 1 +10011 1 +11100 1 +11111 1 +.names DIVIDE.thedivide.r_divisor[30] DIVIDE.thedivide.r_dividend[61] $abc$24881$new_n6949 +00 1 +11 1 +.names DIVIDE.thedivide.i_signed DIVIDE.thedivide.i_wr o_mem_addr[31] o_mem_data[31] $abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y +1101 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.o_valid DIVIDE.thedivide.i_reset $abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n4033 $abc$24881$new_n4029 o_op_stall +10 1 +.names $abc$24881$new_n4033 i_pf_valid o_pf_stall +10 1 +.names i_halt new_pc $abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n5375 op_wF op_illegal $abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y +110 1 +.names op_valid new_pc $abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y +00 1 +01 1 +11 1 +.names GEN_CLOCK_GATE.r_clken i_clear_cache i_dbg_we $abc$24881$new_n6958 o_clken +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_halt sleep i_interrupt $abc$24881$new_n6958 +000 1 +001 1 +011 1 +.names SET_GIE.r_gie user_step i_reset $abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y +000 1 +001 1 +010 1 +011 1 +100 1 +101 1 +111 1 +.names i_reset $abc$24881$new_n4082 $abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +01 1 +10 1 +11 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3863 regset[15][0] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3859 regset[15][1] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3853 regset[15][2] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3848 regset[15][3] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3843 regset[15][4] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3838 regset[15][5] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3832 regset[15][6] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3825 regset[15][7] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3820 regset[15][8] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3815 regset[15][9] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3810 regset[15][10] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3805 regset[15][11] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3800 regset[15][12] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3795 regset[15][13] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3790 regset[15][14] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3784 regset[15][15] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3779 regset[15][16] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3774 regset[15][17] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3769 regset[15][18] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3763 regset[15][19] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3757 regset[15][20] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n5333 $abc$24881$new_n3752 regset[15][21] $abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] +001 1 +011 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$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3810 regset[3][10] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3805 regset[3][11] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3800 regset[3][12] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3795 regset[3][13] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3790 regset[3][14] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3784 regset[3][15] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3779 regset[3][16] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3774 regset[3][17] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3769 regset[3][18] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3763 regset[3][19] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3757 regset[3][20] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3752 regset[3][21] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3747 regset[3][22] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3741 regset[3][23] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3735 regset[3][24] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3730 regset[3][25] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3725 regset[3][26] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3719 regset[3][27] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3714 regset[3][28] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3708 regset[3][29] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n3702 regset[3][30] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7309 $abc$24881$new_n6568 regset[3][31] $abc$24881$memory\regset$wrmux[3][0][0]$y$4328[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.pre_sign $abc$24881$new_n7342 o_mem_data[31] DIVIDE.thedivide.r_dividend[30] $abc$24881$flatten\DIVIDE.thedivide.$0\r_dividend[62:0][31] +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.pre_sign $abc$24881$new_n3672 DIVIDE.thedivide.r_dividend[29] DIVIDE.thedivide.r_dividend[30] $abc$24881$new_n7342 +11100 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3863 regset[16][0] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n7027 $abc$24881$new_n3694 $abc$24881$new_n7344 +1110 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3859 regset[16][1] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3853 regset[16][2] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3848 regset[16][3] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3843 regset[16][4] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3838 regset[16][5] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3832 regset[16][6] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3825 regset[16][7] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3820 regset[16][8] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3815 regset[16][9] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3810 regset[16][10] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3805 regset[16][11] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3800 regset[16][12] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3795 regset[16][13] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3790 regset[16][14] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3784 regset[16][15] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3779 regset[16][16] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3774 regset[16][17] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3769 regset[16][18] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3763 regset[16][19] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3757 regset[16][20] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3752 regset[16][21] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3747 regset[16][22] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3741 regset[16][23] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3735 regset[16][24] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3730 regset[16][25] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3725 regset[16][26] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3719 regset[16][27] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3714 regset[16][28] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3708 regset[16][29] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n3702 regset[16][30] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7344 $abc$24881$new_n6568 regset[16][31] $abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_dividend[31] DIVIDE.thedivide.r_divisor[31] $abc$24881$new_n7377 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y +0001 1 +0011 1 +0101 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.zero_divisor $abc$24881$new_n7377 +110 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3863 regset[2][0] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7143 $abc$24881$new_n7379 +1111 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3859 regset[2][1] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3853 regset[2][2] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3848 regset[2][3] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3843 regset[2][4] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3838 regset[2][5] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3832 regset[2][6] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3825 regset[2][7] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3820 regset[2][8] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3815 regset[2][9] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3810 regset[2][10] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3805 regset[2][11] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3800 regset[2][12] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3795 regset[2][13] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3790 regset[2][14] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3784 regset[2][15] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3779 regset[2][16] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3774 regset[2][17] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3769 regset[2][18] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3763 regset[2][19] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3757 regset[2][20] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3752 regset[2][21] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3747 regset[2][22] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3741 regset[2][23] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3735 regset[2][24] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3730 regset[2][25] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3725 regset[2][26] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3719 regset[2][27] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3714 regset[2][28] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3708 regset[2][29] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n3702 regset[2][30] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7379 $abc$24881$new_n6568 regset[2][31] $abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] +001 1 +011 1 +100 1 +101 1 +.names DIVIDE.thedivide.r_busy $abc$24881$new_n3867 DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign $abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y +0011 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names DIVIDE.thedivide.o_quotient[0] DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.r_busy $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] +0110 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] +00110 1 +00111 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[2] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names DIVIDE.thedivide.o_quotient[2] DIVIDE.thedivide.o_quotient[1] DIVIDE.thedivide.o_quotient[0] $abc$24881$new_n7415 +000 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7415 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[4] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7415 DIVIDE.thedivide.o_quotient[4] DIVIDE.thedivide.o_quotient[3] $abc$24881$new_n7418 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7418 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[6] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7418 DIVIDE.thedivide.o_quotient[6] DIVIDE.thedivide.o_quotient[5] $abc$24881$new_n7421 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7421 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[8] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7421 DIVIDE.thedivide.o_quotient[8] DIVIDE.thedivide.o_quotient[7] $abc$24881$new_n7424 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7424 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[10] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7424 DIVIDE.thedivide.o_quotient[10] DIVIDE.thedivide.o_quotient[9] $abc$24881$new_n7427 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7427 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[12] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7427 DIVIDE.thedivide.o_quotient[12] DIVIDE.thedivide.o_quotient[11] $abc$24881$new_n7430 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7430 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[14] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7430 DIVIDE.thedivide.o_quotient[14] DIVIDE.thedivide.o_quotient[13] $abc$24881$new_n7433 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[16] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7433 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[17] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7436 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7433 DIVIDE.thedivide.o_quotient[15] $abc$24881$new_n7436 +10 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7438 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7436 DIVIDE.thedivide.o_quotient[16] $abc$24881$new_n7438 +10 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[18] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7438 DIVIDE.thedivide.o_quotient[18] DIVIDE.thedivide.o_quotient[17] $abc$24881$new_n7440 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[20] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7440 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7443 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7440 DIVIDE.thedivide.o_quotient[19] $abc$24881$new_n7443 +10 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[21] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7443 DIVIDE.thedivide.o_quotient[21] DIVIDE.thedivide.o_quotient[20] $abc$24881$new_n7445 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7445 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 DIVIDE.thedivide.o_quotient[23] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7445 DIVIDE.thedivide.o_quotient[23] DIVIDE.thedivide.o_quotient[22] $abc$24881$new_n7448 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[25] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7448 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7451 DIVIDE.thedivide.o_quotient[25] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[25] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7448 DIVIDE.thedivide.o_quotient[25] DIVIDE.thedivide.o_quotient[24] $abc$24881$new_n7451 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[27] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7451 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[26] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7454 DIVIDE.thedivide.o_quotient[27] $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[27] +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7451 DIVIDE.thedivide.o_quotient[27] DIVIDE.thedivide.o_quotient[26] $abc$24881$new_n7454 +100 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[29] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7454 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[28] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.o_quotient[30] DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[29] $abc$24881$new_n7457 $abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[29] +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11110 1 +11111 1 +.names $abc$24881$new_n7454 DIVIDE.thedivide.o_quotient[28] $abc$24881$new_n7457 +10 1 +.names DIVIDE.thedivide.r_sign DIVIDE.thedivide.w_n DIVIDE.thedivide.r_busy DIVIDE.thedivide.o_quotient[30] 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1 +.names $abc$24881$new_n7526 $abc$24881$new_n3784 regset[28][15] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3779 regset[28][16] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3774 regset[28][17] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3769 regset[28][18] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3763 regset[28][19] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3757 regset[28][20] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3752 regset[28][21] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3747 regset[28][22] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3741 regset[28][23] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3735 regset[28][24] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3730 regset[28][25] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3725 regset[28][26] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3719 regset[28][27] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3714 regset[28][28] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3708 regset[28][29] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n3702 regset[28][30] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7526 $abc$24881$new_n6568 regset[28][31] $abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] +001 1 +011 1 +100 1 +101 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[2] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] o_pf_request_address[2] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[3] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] o_pf_request_address[3] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[4] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] o_pf_request_address[4] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[5] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] o_pf_request_address[5] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[6] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] o_pf_request_address[6] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[7] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] o_pf_request_address[7] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[8] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] o_pf_request_address[8] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[9] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] o_pf_request_address[9] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[10] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] o_pf_request_address[10] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[11] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] o_pf_request_address[11] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[12] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] o_pf_request_address[12] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] o_pf_request_address[13] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[14] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] o_pf_request_address[14] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[15] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] o_pf_request_address[15] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[16] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] o_pf_request_address[16] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[17] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] o_pf_request_address[17] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[18] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] o_pf_request_address[18] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[19] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] o_pf_request_address[19] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[20] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] o_pf_request_address[20] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[21] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] o_pf_request_address[21] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[22] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] o_pf_request_address[22] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[23] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] o_pf_request_address[23] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[24] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] o_pf_request_address[24] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[25] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] o_pf_request_address[25] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[26] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] o_pf_request_address[26] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[27] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] o_pf_request_address[27] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[28] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] o_pf_request_address[28] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[29] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] o_pf_request_address[29] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[30] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] o_pf_request_address[30] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb new_pc pf_pc[31] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] o_pf_request_address[31] +0010 1 +0011 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3863 regset[27][0] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3958 $abc$24881$new_n3695 $abc$24881$new_n3694 $abc$24881$new_n7589 +1100 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3859 regset[27][1] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3853 regset[27][2] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3848 regset[27][3] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3843 regset[27][4] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3838 regset[27][5] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3832 regset[27][6] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3825 regset[27][7] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3820 regset[27][8] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3815 regset[27][9] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3810 regset[27][10] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3805 regset[27][11] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3800 regset[27][12] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3795 regset[27][13] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3790 regset[27][14] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3784 regset[27][15] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3779 regset[27][16] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3774 regset[27][17] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3769 regset[27][18] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3763 regset[27][19] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3757 regset[27][20] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3752 regset[27][21] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3747 regset[27][22] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3741 regset[27][23] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3735 regset[27][24] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3730 regset[27][25] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3725 regset[27][26] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3719 regset[27][27] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3714 regset[27][28] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3708 regset[27][29] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n3702 regset[27][30] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7589 $abc$24881$new_n6568 regset[27][31] $abc$24881$memory\regset$wrmux[27][0][0]$y$4496[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3863 regset[22][0] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7143 $abc$24881$new_n3695 $abc$24881$new_n3701 $abc$24881$new_n3694 $abc$24881$new_n7622 +1100 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3859 regset[22][1] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3853 regset[22][2] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3848 regset[22][3] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3843 regset[22][4] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3838 regset[22][5] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3832 regset[22][6] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3825 regset[22][7] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3820 regset[22][8] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n7622 $abc$24881$new_n3815 regset[22][9] $abc$24881$memory\regset$wrmux[22][0][0]$y$4462[9] +001 1 +011 1 +100 1 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o_mem_addr[2] $abc$24881$new_n7701 $abc$24881$new_n7703 $abc$24881$new_n7700 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7702 o_mem_data[27] o_mem_data[26] $abc$24881$new_n7701 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[0] o_mem_data[25] o_mem_data[24] $abc$24881$new_n7702 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[1] $abc$24881$new_n7704 $abc$24881$new_n7705 $abc$24881$new_n7703 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[0] o_mem_data[29] o_mem_data[28] $abc$24881$new_n7704 +000 1 +010 1 +100 1 +101 1 +.names o_mem_addr[0] o_mem_data[30] o_mem_data[31] $abc$24881$new_n7705 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n7707 $abc$24881$new_n7709 $abc$24881$new_n7706 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7708 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7707 +00100 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+11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7722 $abc$24881$new_n6656 $abc$24881$new_n7721 +00 1 +.names o_mem_op[2] FWD_OPERATION.r_op_opn[3] DIVIDE.thedivide.i_signed o_mem_op[1] $abc$24881$new_n7722 +1000 1 +.names DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7723 +11 1 +.names DIVIDE.thedivide.i_signed $abc$24881$new_n6656 $abc$24881$new_n7724 +11 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[31] o_mem_addr[0] $abc$24881$new_n7725 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names FWD_OPERATION.r_op_opn[3] o_mem_op[1] o_mem_op[2] $abc$24881$new_n7726 +100 1 +.names $abc$24881$new_n7728 $abc$24881$new_n6657 $abc$24881$new_n7727 +00 1 +.names FWD_OPERATION.r_op_opn[3] o_mem_op[2] DIVIDE.thedivide.i_signed o_mem_op[1] $abc$24881$new_n7728 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7731 $abc$24881$new_n7690 $abc$24881$new_n7745 $abc$24881$new_n7730 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6787 $abc$24881$new_n9679 $abc$24881$new_n6785 $abc$24881$new_n7739 o_mem_addr[4] $abc$24881$new_n7731 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names o_mem_addr[2] $abc$24881$new_n7734 $abc$24881$new_n7735 $abc$24881$new_n7733 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6768 o_mem_data[10] o_mem_data[9] $abc$24881$new_n7734 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6755 o_mem_data[14] o_mem_data[13] $abc$24881$new_n7735 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] $abc$24881$new_n6766 $abc$24881$new_n6772 $abc$24881$new_n7737 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7740 $abc$24881$new_n7743 $abc$24881$new_n7739 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7741 $abc$24881$new_n7742 $abc$24881$new_n7740 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6756 o_mem_data[20] o_mem_data[19] $abc$24881$new_n7741 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6758 o_mem_data[24] o_mem_data[23] $abc$24881$new_n7742 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7744 $abc$24881$new_n6763 o_mem_data[31] $abc$24881$new_n7743 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6761 o_mem_data[28] o_mem_data[27] $abc$24881$new_n7744 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n9679 $abc$24881$new_n7746 $abc$24881$new_n7750 $abc$24881$new_n7745 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7740 $abc$24881$new_n7747 $abc$24881$new_n7746 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7744 $abc$24881$new_n7748 $abc$24881$new_n7747 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6763 $abc$24881$new_n7749 $abc$24881$new_n7748 +010 1 +011 1 +100 1 +110 1 +.names o_mem_data[31] o_mem_addr[0] $abc$24881$new_n7749 +10 1 +.names o_mem_addr[1] o_mem_addr[3] $abc$24881$new_n7751 o_mem_addr[2] $abc$24881$new_n7750 +0000 1 +.names o_mem_addr[0] o_mem_data[1] o_mem_data[0] $abc$24881$new_n7751 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7781 $abc$24881$new_n7785 $abc$24881$new_n7727 $abc$24881$new_n7760 $abc$24881$auto$rtlil.cc:2582:Mux$3529[2] +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7761 $abc$24881$new_n7690 $abc$24881$new_n7776 $abc$24881$new_n7760 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n6787 $abc$24881$new_n7769 $abc$24881$new_n6785 $abc$24881$new_n7762 o_mem_addr[4] $abc$24881$new_n7761 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names o_mem_addr[3] $abc$24881$new_n7763 $abc$24881$new_n7766 $abc$24881$new_n7762 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n7764 o_mem_data[31] o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7763 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names o_mem_addr[2] $abc$24881$new_n7765 o_mem_addr[1] $abc$24881$new_n7705 $abc$24881$new_n7764 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7704 o_mem_data[27] o_mem_data[26] $abc$24881$new_n7765 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7767 $abc$24881$new_n7768 $abc$24881$new_n7766 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7699 o_mem_data[19] o_mem_data[18] $abc$24881$new_n7767 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7702 o_mem_data[23] o_mem_data[22] $abc$24881$new_n7768 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7773 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7770 $abc$24881$new_n7769 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7771 $abc$24881$new_n7772 $abc$24881$new_n7770 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7710 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7771 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7697 o_mem_data[15] o_mem_data[14] $abc$24881$new_n7772 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7774 $abc$24881$new_n7775 $abc$24881$new_n7773 +1001 1 +1011 1 +1100 1 +1101 1 +.names o_mem_addr[1] $abc$24881$new_n7708 $abc$24881$new_n7714 $abc$24881$new_n7774 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n7713 $abc$24881$new_n7716 $abc$24881$new_n7775 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7769 $abc$24881$new_n7777 $abc$24881$new_n7778 $abc$24881$new_n7776 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7766 $abc$24881$new_n7764 $abc$24881$new_n7777 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n7779 o_mem_addr[3] $abc$24881$new_n7778 +10 1 +.names o_mem_addr[2] $abc$24881$new_n7780 $abc$24881$new_n7779 +00 1 +.names o_mem_addr[1] $abc$24881$new_n6738 o_mem_data[0] o_mem_addr[0] $abc$24881$new_n7780 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7782 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7722 $abc$24881$new_n6655 $abc$24881$new_n7781 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +.names $abc$24881$new_n7784 $abc$24881$new_n6653 $abc$24881$new_n6700 $abc$24881$new_n6679 $abc$24881$new_n7783 $abc$24881$new_n7782 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7721 o_mem_addr[2] $abc$24881$new_n6654 o_mem_data[2] DIVIDE.thedivide.i_signed $abc$24881$new_n7783 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7724 o_mem_data[2] o_mem_addr[2] $abc$24881$new_n7784 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[29] o_mem_addr[2] $abc$24881$new_n7785 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7787 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n7802 $abc$24881$new_n7804 $abc$24881$auto$rtlil.cc:2582:Mux$3529[3] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n7801 $abc$24881$new_n7788 $abc$24881$new_n7728 $abc$24881$new_n7690 $abc$24881$new_n7795 $abc$24881$new_n7787 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6787 $abc$24881$new_n7789 $abc$24881$new_n6785 $abc$24881$new_n7792 o_mem_addr[4] $abc$24881$new_n7788 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n7791 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7789 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n6754 $abc$24881$new_n6767 $abc$24881$new_n7790 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n6765 $abc$24881$new_n6770 $abc$24881$new_n7791 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7794 $abc$24881$new_n7792 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6757 $abc$24881$new_n6760 $abc$24881$new_n7793 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6762 o_mem_data[31] $abc$24881$new_n7794 +010 1 +011 1 +100 1 +110 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7789 $abc$24881$new_n7796 $abc$24881$new_n7798 $abc$24881$new_n7795 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7793 $abc$24881$new_n7797 $abc$24881$new_n7796 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6762 $abc$24881$new_n7749 o_mem_addr[1] $abc$24881$new_n7797 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7799 o_mem_addr[3] $abc$24881$new_n7798 +10 1 +.names o_mem_addr[2] $abc$24881$new_n7800 $abc$24881$new_n7799 +00 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7751 o_mem_data[3] o_mem_data[2] $abc$24881$new_n7800 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[28] o_mem_addr[3] $abc$24881$new_n7801 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7803 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7802 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] o_mem_data[2] $abc$24881$new_n6700 $abc$24881$new_n7803 +001 1 +100 1 +101 1 +111 1 +.names o_mem_addr[3] o_mem_data[3] $abc$24881$new_n7805 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n7804 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +10000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n6678 $abc$24881$new_n6679 $abc$24881$new_n6680 $abc$24881$new_n7805 +000 1 +001 1 +011 1 +.names $abc$24881$new_n7807 $abc$24881$new_n7722 o_mem_addr[4] o_mem_data[4] $abc$24881$new_n7822 $abc$24881$auto$rtlil.cc:2582:Mux$3529[4] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n7819 $abc$24881$new_n7728 $abc$24881$new_n7808 $abc$24881$new_n7821 o_mem_addr[4] $abc$24881$new_n7807 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7809 $abc$24881$new_n7817 $abc$24881$new_n7689 $abc$24881$new_n7692 $abc$24881$new_n7811 $abc$24881$new_n7808 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n7810 $abc$24881$new_n7809 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[3] o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7810 +111 1 +.names o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7812 $abc$24881$new_n7815 $abc$24881$new_n7816 $abc$24881$new_n7811 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7812 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n7703 $abc$24881$new_n7813 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7698 $abc$24881$new_n7701 $abc$24881$new_n7814 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7696 $abc$24881$new_n7709 $abc$24881$new_n7815 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7707 $abc$24881$new_n7712 $abc$24881$new_n7816 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7818 $abc$24881$new_n7817 +00 1 +.names o_mem_addr[2] $abc$24881$new_n6736 $abc$24881$new_n7717 $abc$24881$new_n7818 +010 1 +011 1 +100 1 +110 1 +.names $abc$24881$new_n7727 o_mem_addr[27] $abc$24881$new_n7820 $abc$24881$new_n7819 +000 1 +001 1 +010 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed $abc$24881$new_n7820 +10 1 +.names DIVIDE.thedivide.i_signed $abc$24881$new_n7726 $abc$24881$new_n7821 +11 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7824 $abc$24881$new_n7823 $abc$24881$new_n7721 $abc$24881$new_n7822 +1000 1 +1010 1 +1011 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n6699 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7823 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6656 o_mem_addr[4] o_mem_data[4] $abc$24881$new_n9661 DIVIDE.thedivide.i_signed $abc$24881$new_n7824 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7827 $abc$24881$new_n7690 $abc$24881$new_n7835 $abc$24881$new_n7826 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7829 $abc$24881$new_n6785 $abc$24881$new_n7832 o_mem_addr[4] $abc$24881$new_n7827 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n6787 $abc$24881$new_n7828 +10 1 +.names $abc$24881$new_n7831 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7830 $abc$24881$new_n7829 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7735 $abc$24881$new_n7741 $abc$24881$new_n7830 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7734 $abc$24881$new_n7737 $abc$24881$new_n7831 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7810 $abc$24881$new_n7833 $abc$24881$new_n7834 $abc$24881$new_n7832 +0010 1 +0011 1 +1000 1 +1010 1 +.names o_mem_addr[2] $abc$24881$new_n7742 $abc$24881$new_n7744 $abc$24881$new_n7833 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n6763 o_mem_data[31] $abc$24881$new_n7834 +0000 1 +0001 1 +1001 1 +1011 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7829 $abc$24881$new_n7836 $abc$24881$new_n7837 $abc$24881$new_n7835 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7833 o_mem_addr[2] $abc$24881$new_n7748 $abc$24881$new_n7836 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[3] $abc$24881$new_n7838 $abc$24881$new_n7837 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7839 o_mem_addr[1] $abc$24881$new_n7751 $abc$24881$new_n7838 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7840 o_mem_data[3] o_mem_data[2] $abc$24881$new_n7839 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[5] o_mem_data[4] $abc$24881$new_n7840 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n6699 $abc$24881$new_n7843 +001 1 +100 1 +101 1 +111 1 +.names o_mem_addr[5] o_mem_data[5] $abc$24881$new_n7845 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n7844 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[4] o_mem_data[4] $abc$24881$new_n9661 $abc$24881$new_n7845 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[26] o_mem_addr[5] $abc$24881$new_n7847 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7863 $abc$24881$new_n7849 $abc$24881$new_n7867 $abc$24881$new_n7821 o_mem_addr[6] $abc$24881$auto$rtlil.cc:2582:Mux$3529[6] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7850 $abc$24881$new_n7690 $abc$24881$new_n7857 $abc$24881$new_n7849 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7851 $abc$24881$new_n6785 $abc$24881$new_n7854 o_mem_addr[4] $abc$24881$new_n7850 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n7853 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7852 $abc$24881$new_n7851 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names o_mem_addr[2] $abc$24881$new_n7772 $abc$24881$new_n7767 $abc$24881$new_n7852 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n6744 o_mem_addr[2] $abc$24881$new_n7771 $abc$24881$new_n7774 $abc$24881$new_n7853 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[3] $abc$24881$new_n7855 $abc$24881$new_n7856 $abc$24881$new_n7854 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7768 $abc$24881$new_n7765 $abc$24881$new_n7855 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[2] o_mem_data[31] $abc$24881$new_n7705 $abc$24881$new_n7856 +0001 1 +0011 1 +0100 1 +0101 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7851 $abc$24881$new_n7858 $abc$24881$new_n7860 $abc$24881$new_n7857 +00100 1 +00101 1 +00110 1 +00111 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7855 $abc$24881$new_n7859 $abc$24881$new_n7858 +010 1 +011 1 +100 1 +110 1 +.names o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n7705 $abc$24881$new_n7859 +000 1 +.names o_mem_addr[3] $abc$24881$new_n7861 $abc$24881$new_n7860 +00 1 +.names o_mem_addr[2] $abc$24881$new_n7780 $abc$24881$new_n7862 $abc$24881$new_n7861 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6737 o_mem_data[6] o_mem_data[5] $abc$24881$new_n7862 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7864 $abc$24881$new_n7727 $abc$24881$new_n7866 $abc$24881$new_n7721 $abc$24881$new_n7863 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n7865 o_mem_addr[6] o_mem_data[6] $abc$24881$new_n7722 $abc$24881$new_n7864 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n6656 o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 DIVIDE.thedivide.i_signed $abc$24881$new_n7865 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7866 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n7820 o_mem_addr[25] $abc$24881$new_n7867 +11 1 +.names $abc$24881$new_n7870 $abc$24881$new_n7820 o_mem_addr[24] $abc$24881$new_n7821 o_mem_addr[7] $abc$24881$new_n7869 +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7871 $abc$24881$new_n7690 $abc$24881$new_n7874 $abc$24881$new_n7870 +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n6785 $abc$24881$new_n7872 $abc$24881$new_n7871 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7873 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6759 o_mem_data[31] $abc$24881$new_n7872 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n6753 $abc$24881$new_n6764 $abc$24881$new_n7873 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7873 $abc$24881$new_n7876 $abc$24881$new_n7875 $abc$24881$new_n7874 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +01101 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n6759 $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[2] $abc$24881$new_n7875 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6776 o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7876 +100 1 +.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7800 $abc$24881$new_n7877 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7840 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7878 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6674 $abc$24881$new_n7881 +000 1 +001 1 +011 1 +101 1 +.names o_mem_addr[6] o_mem_data[6] $abc$24881$new_n6698 $abc$24881$new_n7884 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7828 o_mem_data[31] o_mem_addr[4] $abc$24881$new_n6658 o_mem_addr[3] $abc$24881$new_n7888 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[3] $abc$24881$new_n6733 $abc$24881$new_n7717 o_mem_addr[2] $abc$24881$new_n7891 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7896 $abc$24881$new_n7893 $abc$24881$new_n7895 $abc$24881$new_n7722 $abc$24881$new_n7892 +10000 1 +10001 1 +10010 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7894 $abc$24881$new_n7723 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7893 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +.names $abc$24881$new_n6654 $abc$24881$new_n7895 $abc$24881$new_n6697 DIVIDE.thedivide.i_signed o_mem_addr[8] $abc$24881$new_n7894 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +11100 1 +11101 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n7895 +01 1 +10 1 +.names $abc$24881$new_n6656 o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 DIVIDE.thedivide.i_signed $abc$24881$new_n7896 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[23] o_mem_addr[8] $abc$24881$new_n7897 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7899 o_mem_addr[9] $abc$24881$new_n7821 $abc$24881$new_n7727 $abc$24881$new_n7909 $abc$24881$auto$rtlil.cc:2582:Mux$3529[9] +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7900 $abc$24881$new_n7903 o_mem_addr[22] $abc$24881$new_n7820 $abc$24881$new_n7899 +00100 1 +00101 1 +00110 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[4] $abc$24881$new_n7902 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7747 $abc$24881$new_n7900 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n7901 +10 1 +.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7743 o_mem_data[31] $abc$24881$new_n7902 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7904 $abc$24881$new_n7689 $abc$24881$new_n7905 $abc$24881$new_n7903 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n7740 $abc$24881$new_n7904 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7906 $abc$24881$new_n7751 o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7905 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7839 $abc$24881$new_n7907 $abc$24881$new_n7906 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[7] o_mem_data[6] $abc$24881$new_n7907 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[9] o_mem_data[8] $abc$24881$new_n7908 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7910 $abc$24881$new_n7913 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7722 $abc$24881$new_n7909 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7911 o_mem_data[9] o_mem_addr[9] $abc$24881$new_n7723 $abc$24881$new_n7910 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7912 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7911 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6697 $abc$24881$new_n7912 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6656 o_mem_addr[9] o_mem_data[9] $abc$24881$new_n7914 DIVIDE.thedivide.i_signed $abc$24881$new_n7913 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[8] o_mem_data[8] $abc$24881$new_n6673 $abc$24881$new_n7914 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7928 $abc$24881$new_n7916 $abc$24881$new_n7727 $abc$24881$new_n9694 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[10] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +.names $abc$24881$new_n7917 $abc$24881$new_n7919 $abc$24881$new_n7918 $abc$24881$new_n7689 $abc$24881$new_n7920 $abc$24881$new_n7916 +10000 1 +10001 1 +10011 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7901 o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n7917 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7763 o_mem_data[31] $abc$24881$new_n7918 +11000 1 +11001 1 +11101 1 +11111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7770 $abc$24881$new_n7766 $abc$24881$new_n7919 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7779 $abc$24881$new_n7921 $abc$24881$new_n7920 +001 1 +011 1 +100 1 +101 1 +.names o_mem_addr[2] $abc$24881$new_n7862 $abc$24881$new_n7922 $abc$24881$new_n7921 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6735 o_mem_data[10] o_mem_data[9] $abc$24881$new_n7922 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[10] o_mem_addr[21] $abc$24881$new_n7928 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7943 $abc$24881$new_n7930 $abc$24881$new_n7727 $abc$24881$new_n7937 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[11] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10000 1 +10010 1 +10100 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7931 $abc$24881$new_n7933 $abc$24881$new_n7689 $abc$24881$new_n7934 $abc$24881$new_n7930 +10000 1 +10001 1 +10011 1 +.names o_mem_addr[4] $abc$24881$new_n7932 $abc$24881$new_n7901 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n7931 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6785 o_mem_addr[3] o_mem_addr[2] o_mem_data[31] $abc$24881$new_n6762 $abc$24881$new_n7932 +10000 1 +10010 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7790 $abc$24881$new_n7793 $abc$24881$new_n7933 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7935 $abc$24881$new_n7799 $abc$24881$new_n7934 +010 1 +011 1 +100 1 +110 1 +.names o_mem_addr[2] $abc$24881$new_n7878 $abc$24881$new_n7936 $abc$24881$new_n7935 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7908 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7936 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7938 $abc$24881$new_n7941 $abc$24881$new_n7721 $abc$24881$new_n7937 +100 1 +110 1 +111 1 +.names $abc$24881$new_n7939 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7722 $abc$24881$new_n7938 +0000 1 +0001 1 +0010 1 +0100 1 +0110 1 +0111 1 +.names $abc$24881$new_n6656 o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7940 DIVIDE.thedivide.i_signed $abc$24881$new_n7939 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 $abc$24881$new_n7940 +000 1 +001 1 +011 1 +101 1 +.names o_mem_addr[11] o_mem_data[11] $abc$24881$new_n7942 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7941 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 $abc$24881$new_n7942 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[20] o_mem_addr[11] $abc$24881$new_n7943 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names $abc$24881$new_n7951 $abc$24881$new_n7946 $abc$24881$new_n7728 $abc$24881$new_n7692 $abc$24881$new_n7950 $abc$24881$new_n7945 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7947 $abc$24881$new_n6787 $abc$24881$new_n7690 $abc$24881$new_n7948 $abc$24881$new_n7691 $abc$24881$new_n7946 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +.names o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6785 o_mem_addr[2] o_mem_addr[3] $abc$24881$new_n7947 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7818 $abc$24881$new_n7949 $abc$24881$new_n7948 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n6731 $abc$24881$new_n6734 $abc$24881$new_n7949 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7813 $abc$24881$new_n7814 $abc$24881$new_n7815 $abc$24881$new_n7950 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_addr[19] o_mem_addr[12] $abc$24881$new_n7951 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n7955 $abc$24881$new_n6702 $abc$24881$new_n6695 $abc$24881$new_n6653 $abc$24881$new_n7954 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6654 o_mem_addr[12] o_mem_data[12] DIVIDE.thedivide.i_signed $abc$24881$new_n7955 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7968 $abc$24881$new_n7728 $abc$24881$new_n7962 $abc$24881$new_n7959 $abc$24881$new_n7967 $abc$24881$new_n7958 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n7961 $abc$24881$new_n7901 $abc$24881$new_n6785 $abc$24881$new_n7960 $abc$24881$new_n7959 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7834 o_mem_data[31] o_mem_addr[2] $abc$24881$new_n7960 +0000 1 +0001 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7748 $abc$24881$new_n7961 +000 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7689 $abc$24881$new_n7963 $abc$24881$new_n7962 +100 1 +101 1 +111 1 +.names o_mem_addr[3] $abc$24881$new_n7838 $abc$24881$new_n7964 $abc$24881$new_n7963 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7907 $abc$24881$new_n7965 $abc$24881$new_n7964 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[11] o_mem_data[10] $abc$24881$new_n7965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[13] o_mem_data[12] $abc$24881$new_n7966 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7830 $abc$24881$new_n7833 $abc$24881$new_n7967 +10000 1 +10001 1 +11000 1 +11010 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[18] o_mem_addr[13] $abc$24881$new_n7968 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1100 1 +1110 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7971 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7973 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7972 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6695 $abc$24881$new_n7973 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n7986 $abc$24881$new_n7975 $abc$24881$new_n7982 $abc$24881$new_n7985 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[14] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10110 1 +.names $abc$24881$new_n7828 $abc$24881$new_n7976 $abc$24881$new_n7978 $abc$24881$new_n7689 $abc$24881$new_n7979 $abc$24881$new_n7975 +10000 1 +10001 1 +10011 1 +.names o_mem_addr[4] $abc$24881$new_n7977 $abc$24881$new_n7901 $abc$24881$new_n7859 o_mem_addr[3] $abc$24881$new_n7976 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6785 o_mem_addr[3] $abc$24881$new_n7856 o_mem_data[31] $abc$24881$new_n7977 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7692 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7852 $abc$24881$new_n7855 $abc$24881$new_n7978 +10000 1 +10001 1 +11000 1 +11010 1 +.names o_mem_addr[3] $abc$24881$new_n7861 $abc$24881$new_n7980 $abc$24881$new_n7979 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7922 $abc$24881$new_n7981 $abc$24881$new_n7980 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6732 o_mem_data[14] o_mem_data[13] $abc$24881$new_n7981 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7983 $abc$24881$new_n7721 $abc$24881$new_n7722 $abc$24881$new_n6701 $abc$24881$new_n7982 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n7984 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7983 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11101 1 +.names $abc$24881$new_n6704 $abc$24881$new_n6695 $abc$24881$new_n6703 $abc$24881$new_n6702 $abc$24881$new_n7984 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +.names $abc$24881$new_n6656 o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7724 $abc$24881$new_n7985 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[14] o_mem_addr[17] $abc$24881$new_n7986 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7988 $abc$24881$new_n8001 $abc$24881$new_n7728 $abc$24881$new_n7994 $abc$24881$auto$rtlil.cc:2582:Mux$3529[15] +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7989 $abc$24881$new_n7992 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7722 $abc$24881$new_n7988 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n7990 o_mem_data[15] o_mem_addr[15] $abc$24881$new_n7723 $abc$24881$new_n7989 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n7990 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6706 $abc$24881$new_n6694 $abc$24881$new_n7991 +00 1 +.names $abc$24881$new_n6656 o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7993 DIVIDE.thedivide.i_signed $abc$24881$new_n7992 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[14] o_mem_data[14] $abc$24881$new_n6670 $abc$24881$new_n7993 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7995 $abc$24881$new_n7997 $abc$24881$new_n7689 $abc$24881$new_n7998 $abc$24881$new_n7994 +0000 1 +0001 1 +0011 1 +.names $abc$24881$new_n7901 o_mem_addr[4] $abc$24881$new_n6752 $abc$24881$new_n7996 $abc$24881$new_n7995 +1000 1 +1001 1 +1101 1 +1111 1 +.names $abc$24881$new_n7749 o_mem_addr[1] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n7996 +1000 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6786 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6752 $abc$24881$new_n7997 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names o_mem_addr[3] $abc$24881$new_n7877 $abc$24881$new_n7999 $abc$24881$new_n7998 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[2] $abc$24881$new_n7936 $abc$24881$new_n8000 $abc$24881$new_n7999 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n7966 o_mem_data[15] o_mem_data[14] $abc$24881$new_n8000 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_addr[16] o_mem_addr[15] $abc$24881$new_n8001 +1010 1 +1011 1 +1101 1 +1111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8006 $abc$24881$new_n8011 $abc$24881$new_n8003 $abc$24881$new_n8012 $abc$24881$auto$rtlil.cc:2582:Mux$3529[16] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8004 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n7723 $abc$24881$new_n8003 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11111 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n8005 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8004 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11111 1 +.names o_mem_addr[15] o_mem_data[15] $abc$24881$new_n7991 $abc$24881$new_n8005 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n9702 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[16] o_mem_addr[15] $abc$24881$new_n8006 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6656 o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6669 DIVIDE.thedivide.i_signed $abc$24881$new_n8011 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7722 $abc$24881$new_n6705 $abc$24881$new_n8012 +11 1 +.names $abc$24881$new_n8014 $abc$24881$new_n8019 $abc$24881$new_n7820 o_mem_addr[14] $abc$24881$auto$rtlil.cc:2582:Mux$3529[17] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7721 $abc$24881$new_n8015 $abc$24881$new_n8017 $abc$24881$new_n8014 +1000 1 +1001 1 +1101 1 +1111 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8016 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n8015 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[16] o_mem_data[16] $abc$24881$new_n6669 $abc$24881$new_n8016 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8018 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8017 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6710 $abc$24881$new_n6693 $abc$24881$new_n8018 +00 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8020 $abc$24881$new_n8025 o_mem_data[17] $abc$24881$new_n7821 $abc$24881$new_n8019 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8021 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7906 $abc$24881$new_n8022 $abc$24881$new_n8020 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7746 $abc$24881$new_n7750 $abc$24881$new_n8021 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n7965 $abc$24881$new_n8023 $abc$24881$new_n8022 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8024 o_mem_data[15] o_mem_data[14] $abc$24881$new_n8023 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[17] o_mem_data[16] $abc$24881$new_n8024 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7739 o_mem_data[31] $abc$24881$new_n8025 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n6786 o_mem_addr[4] $abc$24881$new_n8026 +10 1 +.names $abc$24881$new_n8031 $abc$24881$new_n8028 $abc$24881$new_n8038 $abc$24881$auto$rtlil.cc:2582:Mux$3529[18] +000 1 +001 1 +011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8029 $abc$24881$new_n7721 $abc$24881$new_n6708 $abc$24881$new_n7722 $abc$24881$new_n8028 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n8030 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8029 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[17] o_mem_data[17] $abc$24881$new_n8018 $abc$24881$new_n8030 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n8032 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[18] o_mem_addr[13] $abc$24881$new_n8031 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8033 $abc$24881$new_n8037 $abc$24881$new_n8032 +000 1 +010 1 +011 1 +.names $abc$24881$new_n8034 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7777 $abc$24881$new_n7778 $abc$24881$new_n8033 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7690 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7921 $abc$24881$new_n8035 $abc$24881$new_n8034 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[2] $abc$24881$new_n7981 $abc$24881$new_n8036 $abc$24881$new_n8035 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] $abc$24881$new_n6730 $abc$24881$new_n6750 $abc$24881$new_n8036 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8026 $abc$24881$new_n6658 $abc$24881$new_n7762 o_mem_data[31] $abc$24881$new_n8037 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n6656 o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6668 DIVIDE.thedivide.i_signed $abc$24881$new_n8038 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n8045 $abc$24881$new_n8043 $abc$24881$new_n8040 o_mem_addr[12] $abc$24881$new_n7820 $abc$24881$auto$rtlil.cc:2582:Mux$3529[19] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +11011 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8041 $abc$24881$new_n7721 $abc$24881$new_n6709 $abc$24881$new_n7722 $abc$24881$new_n8040 +10000 1 +10001 1 +10010 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6653 $abc$24881$new_n8042 o_mem_addr[19] $abc$24881$new_n6654 o_mem_data[19] $abc$24881$new_n8041 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6709 o_mem_data[18] o_mem_addr[18] $abc$24881$new_n8030 $abc$24881$new_n8042 +0000 1 +0100 1 +0101 1 +0110 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n6656 o_mem_addr[19] o_mem_data[19] $abc$24881$new_n8044 DIVIDE.thedivide.i_signed $abc$24881$new_n8043 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[18] o_mem_data[18] $abc$24881$new_n6668 $abc$24881$new_n8044 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8046 $abc$24881$new_n8050 o_mem_data[19] $abc$24881$new_n7821 $abc$24881$new_n8045 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8047 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7935 $abc$24881$new_n8048 $abc$24881$new_n8046 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7796 $abc$24881$new_n7798 $abc$24881$new_n8047 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8000 $abc$24881$new_n8049 $abc$24881$new_n8048 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8024 o_mem_data[19] o_mem_data[18] $abc$24881$new_n8049 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7792 o_mem_data[31] $abc$24881$new_n8050 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n6656 o_mem_addr[20] o_mem_data[20] $abc$24881$new_n6667 DIVIDE.thedivide.i_signed $abc$24881$new_n8056 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8026 o_mem_data[31] $abc$24881$new_n7812 $abc$24881$new_n7810 $abc$24881$new_n8058 +0000 1 +0001 1 +0010 1 +0011 1 +1010 1 +1110 1 +.names o_mem_addr[2] $abc$24881$new_n6729 $abc$24881$new_n6749 $abc$24881$new_n8062 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[20] o_mem_addr[11] $abc$24881$new_n8063 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8065 $abc$24881$new_n8078 $abc$24881$new_n8071 $abc$24881$auto$rtlil.cc:2582:Mux$3529[21] +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n8066 $abc$24881$new_n8068 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n7722 $abc$24881$new_n8065 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n6656 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n8067 DIVIDE.thedivide.i_signed $abc$24881$new_n8066 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[20] o_mem_data[20] $abc$24881$new_n6667 $abc$24881$new_n8067 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n8070 o_mem_addr[21] o_mem_data[21] $abc$24881$new_n8069 $abc$24881$new_n6653 $abc$24881$new_n8068 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n6711 o_mem_addr[20] $abc$24881$new_n6692 o_mem_data[20] $abc$24881$new_n8069 +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6654 o_mem_addr[21] o_mem_data[21] DIVIDE.thedivide.i_signed $abc$24881$new_n8070 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8072 $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$new_n8077 $abc$24881$new_n8071 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n8073 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7964 $abc$24881$new_n8074 $abc$24881$new_n8072 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7836 $abc$24881$new_n7837 $abc$24881$new_n8073 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8023 $abc$24881$new_n8075 $abc$24881$new_n8074 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8076 o_mem_data[19] o_mem_data[18] $abc$24881$new_n8075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[21] o_mem_data[20] $abc$24881$new_n8076 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n8026 $abc$24881$new_n7832 o_mem_data[31] $abc$24881$new_n8077 +000 1 +010 1 +110 1 +111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[21] o_mem_addr[10] $abc$24881$new_n8078 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8080 $abc$24881$new_n8085 $abc$24881$new_n7820 o_mem_addr[9] $abc$24881$auto$rtlil.cc:2582:Mux$3529[22] +0000 1 +0001 1 +0010 1 +0011 1 +0111 1 +.names $abc$24881$new_n8084 $abc$24881$new_n8081 $abc$24881$new_n8082 $abc$24881$new_n7721 $abc$24881$new_n8080 +1000 1 +1010 1 +1011 1 +.names $abc$24881$new_n6656 o_mem_addr[22] o_mem_data[22] $abc$24881$new_n6666 DIVIDE.thedivide.i_signed $abc$24881$new_n8081 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n8083 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8082 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n6715 $abc$24881$new_n6691 $abc$24881$new_n8083 +00 1 +.names $abc$24881$new_n7727 o_mem_data[22] o_mem_addr[22] $abc$24881$new_n7722 $abc$24881$new_n8084 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8086 $abc$24881$new_n8090 o_mem_data[22] $abc$24881$new_n7821 $abc$24881$new_n8085 +00000 1 +00001 1 +00010 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n8087 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7980 $abc$24881$new_n8088 $abc$24881$new_n8086 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7858 $abc$24881$new_n7860 $abc$24881$new_n8087 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names o_mem_addr[2] $abc$24881$new_n8036 $abc$24881$new_n8089 $abc$24881$new_n8088 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6748 o_mem_data[20] o_mem_data[19] $abc$24881$new_n8089 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7854 o_mem_data[31] $abc$24881$new_n8090 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8092 $abc$24881$new_n8104 $abc$24881$new_n8098 $abc$24881$auto$rtlil.cc:2582:Mux$3529[23] +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n8093 $abc$24881$new_n8096 o_mem_addr[23] o_mem_data[23] $abc$24881$new_n7722 $abc$24881$new_n8092 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8094 o_mem_data[23] o_mem_addr[23] $abc$24881$new_n7723 $abc$24881$new_n8093 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +.names o_mem_addr[23] o_mem_data[23] $abc$24881$new_n8095 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8094 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n8083 $abc$24881$new_n8095 +001 1 +100 1 +101 1 +111 1 +.names $abc$24881$new_n6656 o_mem_addr[23] o_mem_data[23] $abc$24881$new_n8097 DIVIDE.thedivide.i_signed $abc$24881$new_n8096 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11110 1 +.names o_mem_addr[22] o_mem_data[22] $abc$24881$new_n6666 $abc$24881$new_n8097 +000 1 +001 1 +011 1 +101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n6657 $abc$24881$new_n8099 $abc$24881$new_n8103 $abc$24881$new_n8098 +0000 1 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +.names $abc$24881$new_n8100 o_mem_addr[4] $abc$24881$new_n7876 $abc$24881$new_n7875 $abc$24881$new_n6776 $abc$24881$new_n8099 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 o_mem_addr[3] $abc$24881$new_n7691 $abc$24881$new_n7999 $abc$24881$new_n8101 $abc$24881$new_n8100 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[2] $abc$24881$new_n8049 $abc$24881$new_n8102 $abc$24881$new_n8101 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8076 o_mem_data[23] o_mem_data[22] $abc$24881$new_n8102 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 o_mem_addr[3] o_mem_data[31] $abc$24881$new_n6759 $abc$24881$new_n8103 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[23] o_mem_addr[8] $abc$24881$new_n8104 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n8109 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8108 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6717 $abc$24881$new_n6690 $abc$24881$new_n8109 +00 1 +.names $abc$24881$new_n6656 o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6665 DIVIDE.thedivide.i_signed $abc$24881$new_n8110 +10010 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8113 o_mem_data[24] $abc$24881$new_n7821 $abc$24881$new_n8112 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n8114 $abc$24881$new_n8115 $abc$24881$new_n8116 o_mem_addr[4] $abc$24881$new_n7891 $abc$24881$new_n8113 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7828 $abc$24881$new_n6744 $abc$24881$new_n6785 $abc$24881$new_n7700 o_mem_data[31] $abc$24881$new_n8114 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n6744 $abc$24881$new_n7700 $abc$24881$new_n8115 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n6728 $abc$24881$new_n6746 $abc$24881$new_n8116 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8123 $abc$24881$new_n8118 $abc$24881$new_n7721 $abc$24881$new_n8121 $abc$24881$auto$rtlil.cc:2582:Mux$3529[25] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8119 o_mem_addr[25] o_mem_data[25] $abc$24881$new_n7722 $abc$24881$new_n8118 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +10111 1 +.names $abc$24881$new_n6656 o_mem_addr[25] o_mem_data[25] $abc$24881$new_n8120 DIVIDE.thedivide.i_signed $abc$24881$new_n8119 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n6665 $abc$24881$new_n8120 +000 1 +001 1 +010 1 +100 1 +.names o_mem_addr[25] o_mem_data[25] $abc$24881$new_n8122 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8121 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n8109 $abc$24881$new_n8122 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n8131 $abc$24881$new_n8124 $abc$24881$new_n7728 $abc$24881$new_n8123 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8125 $abc$24881$new_n7691 $abc$24881$new_n7690 $abc$24881$new_n8127 $abc$24881$new_n8128 $abc$24881$new_n8124 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8126 $abc$24881$new_n8026 $abc$24881$new_n7743 o_mem_addr[3] $abc$24881$new_n8125 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 o_mem_data[31] $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8126 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +.names $abc$24881$new_n6776 $abc$24881$new_n7905 $abc$24881$new_n6744 $abc$24881$new_n7747 $abc$24881$new_n8127 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8022 $abc$24881$new_n8075 $abc$24881$new_n8129 $abc$24881$new_n8128 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[23] o_mem_data[22] $abc$24881$new_n8129 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names o_mem_addr[0] o_mem_data[25] o_mem_data[24] $abc$24881$new_n8130 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[25] o_mem_addr[6] $abc$24881$new_n8131 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8133 $abc$24881$new_n8143 $abc$24881$new_n7728 $abc$24881$new_n8138 $abc$24881$auto$rtlil.cc:2582:Mux$3529[26] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +.names $abc$24881$new_n8134 $abc$24881$new_n7727 $abc$24881$new_n8136 $abc$24881$new_n7721 $abc$24881$new_n8133 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n8135 o_mem_addr[26] o_mem_data[26] $abc$24881$new_n7722 $abc$24881$new_n8134 +1000 1 +1001 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8135 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01100 1 +01101 1 +10000 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n8137 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8136 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10001 1 +10011 1 +10111 1 +11101 1 +.names $abc$24881$new_n6719 $abc$24881$new_n6689 $abc$24881$new_n8137 +00 1 +.names $abc$24881$new_n8139 $abc$24881$new_n7690 $abc$24881$new_n8140 $abc$24881$new_n7691 $abc$24881$new_n8141 $abc$24881$new_n8138 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6744 $abc$24881$new_n6786 o_mem_data[31] $abc$24881$new_n7763 $abc$24881$new_n8139 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11101 1 +11111 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7920 o_mem_addr[3] $abc$24881$new_n7764 $abc$24881$new_n8140 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8035 $abc$24881$new_n8089 $abc$24881$new_n8142 $abc$24881$new_n8141 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6743 o_mem_data[24] o_mem_data[23] $abc$24881$new_n8142 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11010 1 +11100 1 +11110 1 +.names $abc$24881$new_n7727 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[26] o_mem_addr[5] $abc$24881$new_n8143 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n8150 $abc$24881$new_n8145 $abc$24881$new_n8148 $abc$24881$auto$rtlil.cc:2582:Mux$3529[27] +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$24881$new_n7722 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n7721 $abc$24881$new_n8146 $abc$24881$new_n8145 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8147 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n8146 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n8137 $abc$24881$new_n8147 +000 1 +100 1 +101 1 +110 1 +.names $abc$24881$new_n6656 o_mem_addr[27] o_mem_data[27] $abc$24881$new_n8149 DIVIDE.thedivide.i_signed $abc$24881$new_n8148 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[26] o_mem_data[26] $abc$24881$new_n6664 $abc$24881$new_n8149 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n8156 $abc$24881$new_n8151 $abc$24881$new_n7728 $abc$24881$new_n8150 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8152 $abc$24881$new_n7690 $abc$24881$new_n8153 $abc$24881$new_n7691 $abc$24881$new_n8154 $abc$24881$new_n8151 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n8126 $abc$24881$new_n7794 $abc$24881$new_n6786 $abc$24881$new_n6744 $abc$24881$new_n8152 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +.names o_mem_addr[4] $abc$24881$new_n6776 $abc$24881$new_n7934 o_mem_addr[3] $abc$24881$new_n7797 $abc$24881$new_n8153 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8048 $abc$24881$new_n8102 $abc$24881$new_n8155 $abc$24881$new_n8154 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8130 o_mem_data[27] o_mem_data[26] $abc$24881$new_n8155 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[27] o_mem_addr[4] $abc$24881$new_n8156 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7721 $abc$24881$new_n8160 $abc$24881$new_n6653 $abc$24881$new_n8159 $abc$24881$new_n8158 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6721 $abc$24881$new_n6688 $abc$24881$new_n8159 +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[28] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[28] $abc$24881$new_n8160 +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n7724 $abc$24881$new_n6655 $abc$24881$new_n8161 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01100 1 +01101 1 +10000 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +.names $abc$24881$new_n8166 $abc$24881$new_n8164 $abc$24881$new_n6658 $abc$24881$new_n8167 $abc$24881$new_n7691 $abc$24881$new_n8163 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +11001 1 +11101 1 +.names $abc$24881$new_n8026 $abc$24881$new_n8165 o_mem_data[31] o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8164 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +.names $abc$24881$new_n7813 o_mem_addr[3] $abc$24881$new_n8165 +10 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7948 $abc$24881$new_n8165 $abc$24881$new_n8166 +10001 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8062 $abc$24881$new_n6741 $abc$24881$new_n6747 $abc$24881$new_n8167 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6656 o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8172 DIVIDE.thedivide.i_signed $abc$24881$new_n8171 +10000 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names o_mem_addr[28] o_mem_data[28] $abc$24881$new_n6663 $abc$24881$new_n8172 +000 1 +001 1 +010 1 +100 1 +.names $abc$24881$new_n7721 $abc$24881$new_n6653 $abc$24881$new_n8174 $abc$24881$new_n8175 $abc$24881$new_n8176 $abc$24881$new_n8173 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n6721 $abc$24881$new_n6688 o_mem_addr[28] o_mem_data[28] $abc$24881$new_n8174 +0010 1 +0100 1 +0110 1 +0111 1 +1000 1 +1010 1 +1011 1 +1100 1 +1110 1 +1111 1 +.names o_mem_addr[29] o_mem_data[29] $abc$24881$new_n8175 +00 1 +11 1 +.names o_mem_addr[29] $abc$24881$new_n6654 DIVIDE.thedivide.i_signed o_mem_data[29] $abc$24881$new_n8176 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n8026 $abc$24881$new_n6657 $abc$24881$new_n7960 o_mem_data[31] $abc$24881$new_n8179 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n8074 $abc$24881$new_n8182 $abc$24881$new_n8181 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n8129 $abc$24881$new_n8183 $abc$24881$new_n8184 $abc$24881$new_n8182 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[0] o_mem_data[27] o_mem_data[26] $abc$24881$new_n8183 +000 1 +001 1 +100 1 +110 1 +.names o_mem_addr[0] o_mem_data[29] o_mem_data[28] $abc$24881$new_n8184 +000 1 +001 1 +100 1 +110 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[29] o_mem_addr[2] $abc$24881$new_n8185 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7722 $abc$24881$new_n8175 $abc$24881$new_n8186 +10 1 +.names $abc$24881$new_n8191 $abc$24881$new_n8190 $abc$24881$new_n8199 $abc$24881$new_n7721 $abc$24881$new_n8188 $abc$24881$auto$rtlil.cc:2582:Mux$3529[30] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names DIVIDE.thedivide.i_signed o_mem_addr[30] $abc$24881$new_n6654 $abc$24881$new_n8189 o_mem_data[30] $abc$24881$new_n8188 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11110 1 +.names $abc$24881$new_n6683 $abc$24881$new_n6722 $abc$24881$new_n6687 $abc$24881$new_n8189 +001 1 +010 1 +011 1 +100 1 +.names $abc$24881$new_n6655 $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n8190 +100 1 +111 1 +.names $abc$24881$new_n8198 $abc$24881$new_n8192 $abc$24881$new_n7728 $abc$24881$new_n8191 +101 1 +110 1 +111 1 +.names $abc$24881$new_n8194 $abc$24881$new_n8193 $abc$24881$new_n8195 o_mem_addr[4] $abc$24881$new_n7979 $abc$24881$new_n8192 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 $abc$24881$new_n7859 o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n8193 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6657 $abc$24881$new_n8126 $abc$24881$new_n8026 $abc$24881$new_n7856 o_mem_addr[3] $abc$24881$new_n8194 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7691 o_mem_addr[3] $abc$24881$new_n8088 $abc$24881$new_n8196 $abc$24881$new_n8195 +1001 1 +1011 1 +1110 1 +1111 1 +.names o_mem_addr[2] $abc$24881$new_n8142 $abc$24881$new_n8197 $abc$24881$new_n8196 +001 1 +011 1 +110 1 +111 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n6742 o_mem_data[30] o_mem_data[29] $abc$24881$new_n8197 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7726 DIVIDE.thedivide.i_signed o_mem_data[30] o_mem_addr[1] $abc$24881$new_n8198 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n7727 o_mem_data[30] o_mem_addr[30] $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n8199 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9720 $abc$24881$new_n8207 $abc$24881$new_n8201 $abc$24881$new_n8213 $abc$24881$auto$rtlil.cc:2582:Mux$3529[31] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6650 $abc$24881$new_n7724 $abc$24881$new_n6682 $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n8201 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +10011 1 +.names $abc$24881$new_n6650 o_mem_addr[30] o_mem_data[30] $abc$24881$new_n6722 $abc$24881$new_n6687 $abc$24881$new_n8203 +00000 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6654 o_mem_addr[31] DIVIDE.thedivide.i_signed $abc$24881$new_n8206 +010 1 +011 1 +100 1 +110 1 +.names $abc$24881$new_n9723 DIVIDE.thedivide.i_signed $abc$24881$new_n7726 o_mem_data[31] o_mem_addr[0] $abc$24881$new_n8207 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names o_mem_addr[1] o_mem_addr[0] $abc$24881$new_n8184 o_mem_data[30] o_mem_data[31] $abc$24881$new_n8212 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n6656 DIVIDE.thedivide.i_signed o_mem_addr[31] o_mem_data[31] $abc$24881$new_n8213 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n8215 $abc$24881$new_n3863 regset[18][0] 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regset[12][12] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3795 regset[12][13] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3790 regset[12][14] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3784 regset[12][15] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3779 regset[12][16] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3774 regset[12][17] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3769 regset[12][18] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3763 regset[12][19] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3757 regset[12][20] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3752 regset[12][21] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3747 regset[12][22] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3741 regset[12][23] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3735 regset[12][24] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3730 regset[12][25] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3725 regset[12][26] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3719 regset[12][27] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3714 regset[12][28] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3708 regset[12][29] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n3702 regset[12][30] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n8478 $abc$24881$new_n6568 regset[12][31] $abc$24881$memory\regset$wrmux[12][0][0]$y$4394[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4083 $abc$24881$new_n3993 i_clear_cache o_dbg_stall $abc$24881$procmux$2463_Y +0010 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9727 GEN_UHALT_PHASE.r_uhalt_phase GEN_IHALT_PHASE.r_ihalt_phase $0\genblk43.SETDBG.r_dbg_reg[31:0][1] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8517 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][1] regset[28][1] $abc$24881$new_n8515 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] $abc$24881$new_n8516 +10 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][1] regset[30][1] $abc$24881$new_n8517 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8521 $abc$24881$new_n8520 $abc$24881$new_n8519 $abc$24881$new_n8522 $abc$24881$new_n8518 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][1] regset[16][1] $abc$24881$new_n8519 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][1] regset[18][1] $abc$24881$new_n8520 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][1] regset[20][1] $abc$24881$new_n8521 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][1] regset[22][1] $abc$24881$new_n8522 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8524 regset[27][1] regset[26][1] $abc$24881$new_n8523 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][1] regset[24][1] $abc$24881$new_n8524 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8526 $abc$24881$new_n6930 $abc$24881$new_n8525 +11 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8526 +10 1 +.names $abc$24881$new_n8530 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][1] regset[4][1] $abc$24881$new_n8529 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][1] regset[6][1] $abc$24881$new_n8530 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8532 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][1] regset[0][1] $abc$24881$new_n8531 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][1] regset[2][1] $abc$24881$new_n8532 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8534 regset[11][1] regset[10][1] $abc$24881$new_n8533 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][1] regset[8][1] $abc$24881$new_n8534 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8536 regset[15][1] regset[14][1] $abc$24881$new_n8535 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][1] regset[12][1] $abc$24881$new_n8536 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8542 regset[23][2] regset[22][2] $abc$24881$new_n8541 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][2] regset[20][2] $abc$24881$new_n8542 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8544 regset[19][2] regset[18][2] $abc$24881$new_n8543 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][2] regset[16][2] $abc$24881$new_n8544 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8546 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][2] regset[28][2] $abc$24881$new_n8545 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][2] regset[30][2] $abc$24881$new_n8546 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8548 regset[27][2] regset[26][2] $abc$24881$new_n8547 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][2] regset[24][2] $abc$24881$new_n8548 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8550 $abc$24881$new_n8555 $abc$24881$new_n8558 $abc$24881$new_n8549 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8551 $abc$24881$new_n8553 $abc$24881$new_n8550 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8552 regset[7][2] regset[6][2] $abc$24881$new_n8551 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][2] regset[4][2] $abc$24881$new_n8552 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8554 regset[3][2] regset[2][2] $abc$24881$new_n8553 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][2] regset[0][2] $abc$24881$new_n8554 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8556 regset[11][2] regset[10][2] $abc$24881$new_n8555 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][2] regset[8][2] $abc$24881$new_n8556 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][2] regset[13][2] regset[12][2] $abc$24881$new_n8558 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n8582 $abc$24881$new_n9734 $abc$24881$new_n9738 $0\genblk43.SETDBG.r_dbg_reg[31:0][3] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8567 regset[19][3] regset[18][3] $abc$24881$new_n8566 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][3] regset[16][3] $abc$24881$new_n8567 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8569 regset[27][3] regset[26][3] $abc$24881$new_n8568 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][3] regset[24][3] $abc$24881$new_n8569 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][3] regset[2][3] $abc$24881$new_n8575 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8577 regset[7][3] regset[6][3] $abc$24881$new_n8576 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][3] regset[4][3] $abc$24881$new_n8577 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[9][3] regset[8][3] $abc$24881$new_n8579 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8583 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n8582 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[3] ipc[3] $abc$24881$new_n8583 +1001 1 +1011 1 +1110 1 +1111 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 $abc$24881$new_n8584 +11 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8586 SET_USER_PC.r_upc[4] ipc[4] $0\genblk43.SETDBG.r_dbg_reg[31:0][4] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] sleep $abc$24881$new_n8587 $abc$24881$new_n8597 $abc$24881$new_n8586 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8588 i_dbg_rreg[3] $abc$24881$new_n8590 $abc$24881$new_n8595 i_dbg_rreg[2] $abc$24881$new_n8587 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8589 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][4] regset[28][4] $abc$24881$new_n8588 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][4] regset[30][4] $abc$24881$new_n8589 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8593 $abc$24881$new_n8592 $abc$24881$new_n8591 $abc$24881$new_n8594 $abc$24881$new_n8590 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][4] regset[16][4] $abc$24881$new_n8591 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][4] regset[18][4] $abc$24881$new_n8592 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][4] regset[20][4] $abc$24881$new_n8593 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][4] regset[22][4] $abc$24881$new_n8594 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8596 regset[27][4] regset[26][4] $abc$24881$new_n8595 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][4] regset[24][4] $abc$24881$new_n8596 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8598 $abc$24881$new_n8603 $abc$24881$new_n8606 $abc$24881$new_n8597 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n8601 $abc$24881$new_n8599 i_dbg_rreg[2] $abc$24881$new_n8598 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8600 regset[7][4] regset[6][4] $abc$24881$new_n8599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][4] regset[4][4] $abc$24881$new_n8600 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8602 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][4] regset[0][4] $abc$24881$new_n8601 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][4] regset[2][4] $abc$24881$new_n8602 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8604 regset[11][4] regset[10][4] $abc$24881$new_n8603 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][4] regset[8][4] $abc$24881$new_n8604 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][4] regset[13][4] regset[12][4] $abc$24881$new_n8606 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8611 $abc$24881$new_n8614 $abc$24881$new_n8613 $abc$24881$new_n8610 +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8612 regset[3][0] regset[2][0] $abc$24881$new_n8611 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][0] regset[0][0] $abc$24881$new_n8612 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[5][0] regset[4][0] $abc$24881$new_n8613 +0001 1 +0011 1 +1010 1 +1011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] regset[7][0] regset[6][0] $abc$24881$new_n8614 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n8616 i_dbg_rreg[0] $abc$24881$new_n8516 regset[13][0] regset[12][0] $abc$24881$new_n8615 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 i_dbg_rreg[0] regset[15][0] regset[14][0] $abc$24881$new_n8616 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8618 regset[11][0] regset[10][0] $abc$24881$new_n8617 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][0] regset[8][0] $abc$24881$new_n8618 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8622 regset[23][0] regset[22][0] $abc$24881$new_n8621 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][0] regset[20][0] $abc$24881$new_n8622 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8624 regset[19][0] regset[18][0] $abc$24881$new_n8623 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][0] regset[16][0] $abc$24881$new_n8624 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8626 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][0] regset[28][0] $abc$24881$new_n8625 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][0] regset[30][0] $abc$24881$new_n8626 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8628 regset[27][0] regset[26][0] $abc$24881$new_n8627 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][0] regset[24][0] $abc$24881$new_n8628 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8630 SET_USER_PC.r_upc[5] ipc[5] $0\genblk43.SETDBG.r_dbg_reg[31:0][5] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8641 $abc$24881$new_n8631 $abc$24881$new_n8630 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8632 $abc$24881$new_n8637 $abc$24881$new_n8640 $abc$24881$new_n8631 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n8635 $abc$24881$new_n8633 i_dbg_rreg[2] $abc$24881$new_n8632 +000 1 +001 1 +011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8634 regset[3][5] regset[2][5] $abc$24881$new_n8633 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][5] regset[0][5] $abc$24881$new_n8634 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8636 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][5] regset[4][5] $abc$24881$new_n8635 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][5] regset[6][5] $abc$24881$new_n8636 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8638 regset[11][5] regset[10][5] $abc$24881$new_n8637 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][5] regset[8][5] $abc$24881$new_n8638 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][5] regset[13][5] regset[12][5] $abc$24881$new_n8640 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8642 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8647 $abc$24881$new_n8649 $abc$24881$new_n8641 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8643 $abc$24881$new_n8645 $abc$24881$new_n8642 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8644 regset[27][5] regset[26][5] $abc$24881$new_n8643 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][5] regset[24][5] $abc$24881$new_n8644 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8646 regset[31][5] regset[30][5] $abc$24881$new_n8645 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][5] regset[28][5] $abc$24881$new_n8646 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8648 regset[19][5] regset[18][5] $abc$24881$new_n8647 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][5] regset[16][5] $abc$24881$new_n8648 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8650 regset[23][5] regset[22][5] $abc$24881$new_n8649 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][5] regset[20][5] $abc$24881$new_n8650 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8653 +10 1 +.names i_dbg_rreg[3] $abc$24881$new_n8657 $abc$24881$new_n8655 $abc$24881$new_n6930 $abc$24881$new_n8660 $abc$24881$new_n8654 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8656 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][6] regset[20][6] $abc$24881$new_n8655 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][6] regset[22][6] $abc$24881$new_n8656 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8658 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][6] regset[16][6] $abc$24881$new_n8657 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][6] regset[18][6] $abc$24881$new_n8658 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[29][6] regset[28][6] $abc$24881$new_n8660 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8662 regset[27][6] regset[26][6] $abc$24881$new_n8661 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][6] regset[24][6] $abc$24881$new_n8662 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8668 $abc$24881$new_n8667 $abc$24881$new_n8666 $abc$24881$new_n8669 $abc$24881$new_n8665 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][6] regset[0][6] $abc$24881$new_n8666 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][6] regset[2][6] $abc$24881$new_n8667 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][6] regset[4][6] $abc$24881$new_n8668 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][6] regset[6][6] $abc$24881$new_n8669 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8671 regset[11][6] regset[10][6] $abc$24881$new_n8670 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][6] regset[8][6] $abc$24881$new_n8671 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][6] regset[13][6] regset[12][6] $abc$24881$new_n8673 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8679 regset[3][7] regset[2][7] $abc$24881$new_n8678 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][7] regset[0][7] $abc$24881$new_n8679 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8681 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][7] regset[4][7] $abc$24881$new_n8680 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][7] regset[6][7] $abc$24881$new_n8681 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8684 regset[11][7] regset[10][7] $abc$24881$new_n8683 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][7] regset[8][7] $abc$24881$new_n8684 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] regset[13][7] regset[12][7] $abc$24881$new_n8686 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8689 $abc$24881$new_n8697 $abc$24881$new_n8694 $abc$24881$new_n8688 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] $abc$24881$new_n8692 $abc$24881$new_n8691 $abc$24881$new_n8690 $abc$24881$new_n8693 $abc$24881$new_n8689 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][7] regset[20][7] $abc$24881$new_n8690 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][7] regset[22][7] $abc$24881$new_n8691 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][7] regset[16][7] $abc$24881$new_n8692 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][7] regset[18][7] $abc$24881$new_n8693 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8695 regset[27][7] regset[26][7] $abc$24881$new_n8694 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][7] regset[24][7] $abc$24881$new_n8695 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[29][7] regset[28][7] $abc$24881$new_n8697 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n8698 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8700 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[8] ipc[8] $0\genblk43.SETDBG.r_dbg_reg[31:0][8] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n8721 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n8701 $abc$24881$new_n9754 $abc$24881$new_n8700 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8702 $abc$24881$new_n8707 $abc$24881$new_n8710 $abc$24881$new_n8701 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8703 $abc$24881$new_n8705 $abc$24881$new_n8702 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8704 regset[7][8] regset[6][8] $abc$24881$new_n8703 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][8] regset[4][8] $abc$24881$new_n8704 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8706 regset[3][8] regset[2][8] $abc$24881$new_n8705 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][8] regset[0][8] $abc$24881$new_n8706 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8708 regset[11][8] regset[10][8] $abc$24881$new_n8707 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][8] regset[8][8] $abc$24881$new_n8708 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][8] regset[13][8] regset[12][8] $abc$24881$new_n8710 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8714 regset[23][8] regset[22][8] $abc$24881$new_n8713 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][8] regset[20][8] $abc$24881$new_n8714 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8720 regset[27][8] regset[26][8] $abc$24881$new_n8719 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][8] regset[24][8] $abc$24881$new_n8720 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_USER_ILLEGAL_INSN.r_ill_err_u ill_err_i $abc$24881$new_n8721 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8723 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[9] ipc[9] $0\genblk43.SETDBG.r_dbg_reg[31:0][9] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n8724 $abc$24881$new_n8734 $abc$24881$new_n8653 $abc$24881$new_n8525 SET_TRAP_N_UBREAK.r_trap $abc$24881$new_n8723 +00000 1 +00001 1 +00010 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +.names $abc$24881$new_n8725 $abc$24881$new_n8732 i_dbg_rreg[3] $abc$24881$new_n8730 i_dbg_rreg[2] $abc$24881$new_n8724 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8726 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8727 $abc$24881$new_n8729 $abc$24881$new_n8725 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +.names $abc$24881$new_n8584 i_dbg_rreg[0] i_dbg_rreg[4] $abc$24881$new_n8726 +001 1 +011 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8728 regset[11][9] regset[10][9] $abc$24881$new_n8727 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][9] regset[8][9] $abc$24881$new_n8728 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][9] regset[13][9] regset[12][9] $abc$24881$new_n8729 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8731 regset[3][9] regset[2][9] $abc$24881$new_n8730 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][9] regset[0][9] $abc$24881$new_n8731 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8733 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][9] regset[4][9] $abc$24881$new_n8732 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][9] regset[6][9] $abc$24881$new_n8733 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8740 i_dbg_rreg[3] $abc$24881$new_n8735 $abc$24881$new_n8742 i_dbg_rreg[2] $abc$24881$new_n8734 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8736 $abc$24881$new_n8738 i_dbg_rreg[2] $abc$24881$new_n8735 +000 1 +001 1 +011 1 +.names $abc$24881$new_n8737 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][9] regset[20][9] $abc$24881$new_n8736 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][9] regset[22][9] $abc$24881$new_n8737 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8739 regset[19][9] regset[18][9] $abc$24881$new_n8738 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][9] regset[16][9] $abc$24881$new_n8739 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8741 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][9] regset[28][9] $abc$24881$new_n8740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][9] regset[30][9] $abc$24881$new_n8741 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8743 regset[27][9] regset[26][9] $abc$24881$new_n8742 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][9] regset[24][9] $abc$24881$new_n8743 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8745 SET_USER_PC.r_upc[10] ipc[10] $0\genblk43.SETDBG.r_dbg_reg[31:0][10] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8766 i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n9758 $abc$24881$new_n8756 $abc$24881$new_n8745 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][10] regset[18][10] $abc$24881$new_n8749 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8751 regset[23][10] regset[22][10] $abc$24881$new_n8750 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][10] regset[20][10] $abc$24881$new_n8751 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[25][10] regset[24][10] $abc$24881$new_n8753 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8757 $abc$24881$new_n8765 $abc$24881$new_n8762 $abc$24881$new_n8756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8760 $abc$24881$new_n8758 $abc$24881$new_n8757 +000 1 +.names $abc$24881$new_n8759 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][10] regset[0][10] $abc$24881$new_n8758 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][10] regset[2][10] $abc$24881$new_n8759 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8761 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][10] regset[4][10] $abc$24881$new_n8760 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][10] regset[6][10] $abc$24881$new_n8761 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8763 regset[11][10] regset[10][10] $abc$24881$new_n8762 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][10] regset[8][10] $abc$24881$new_n8763 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][10] regset[13][10] regset[12][10] $abc$24881$new_n8765 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] $abc$24881$new_n8584 SET_USER_BUSERR.r_ubus_err_flag ibus_err_flag $abc$24881$new_n8766 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] $abc$24881$new_n8770 $abc$24881$new_n8775 $abc$24881$new_n8777 i_dbg_rreg[3] $abc$24881$new_n8769 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8771 $abc$24881$new_n8773 $abc$24881$new_n8770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8772 regset[27][11] regset[26][11] $abc$24881$new_n8771 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][11] regset[24][11] $abc$24881$new_n8772 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8774 regset[31][11] regset[30][11] $abc$24881$new_n8773 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][11] regset[28][11] $abc$24881$new_n8774 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8776 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][11] regset[16][11] $abc$24881$new_n8775 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][11] regset[18][11] $abc$24881$new_n8776 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8778 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][11] regset[20][11] $abc$24881$new_n8777 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][11] regset[22][11] $abc$24881$new_n8778 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8782 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][11] regset[4][11] $abc$24881$new_n8781 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][11] regset[6][11] $abc$24881$new_n8782 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8784 regset[3][11] regset[2][11] $abc$24881$new_n8783 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][11] regset[0][11] $abc$24881$new_n8784 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8786 regset[11][11] regset[10][11] $abc$24881$new_n8785 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][11] regset[8][11] $abc$24881$new_n8786 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8788 $abc$24881$new_n6930 $abc$24881$new_n6931 regset[15][11] $abc$24881$new_n8787 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][11] regset[13][11] regset[12][11] $abc$24881$new_n8788 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8584 i_dbg_rreg[4] DIVERR.USER_DIVERR.r_udiv_err_flag DIVERR.r_idiv_err_flag $abc$24881$new_n8789 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8795 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][12] regset[0][12] $abc$24881$new_n8794 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][12] regset[2][12] $abc$24881$new_n8795 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8797 regset[7][12] regset[6][12] $abc$24881$new_n8796 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][12] regset[4][12] $abc$24881$new_n8797 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8799 regset[11][12] regset[10][12] $abc$24881$new_n8798 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][12] regset[8][12] $abc$24881$new_n8799 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] regset[13][12] regset[12][12] $abc$24881$new_n8801 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8804 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][12] regset[20][12] $abc$24881$new_n8803 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][12] regset[22][12] $abc$24881$new_n8804 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8806 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][12] regset[16][12] $abc$24881$new_n8805 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][12] regset[18][12] $abc$24881$new_n8806 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8808 $abc$24881$new_n8810 $abc$24881$new_n8807 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8809 regset[27][12] regset[26][12] $abc$24881$new_n8808 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][12] regset[24][12] $abc$24881$new_n8809 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8811 regset[31][12] regset[30][12] $abc$24881$new_n8810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][12] regset[28][12] $abc$24881$new_n8811 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8817 regset[23][13] regset[22][13] $abc$24881$new_n8816 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][13] regset[20][13] $abc$24881$new_n8817 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8819 regset[19][13] regset[18][13] $abc$24881$new_n8818 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][13] regset[16][13] $abc$24881$new_n8819 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8822 regset[27][13] regset[26][13] $abc$24881$new_n8821 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][13] regset[24][13] $abc$24881$new_n8822 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8516 i_dbg_rreg[0] regset[29][13] regset[28][13] $abc$24881$new_n8823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8826 $abc$24881$new_n8831 $abc$24881$new_n8833 $abc$24881$new_n8825 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n8827 $abc$24881$new_n8829 $abc$24881$new_n8826 +010 1 +011 1 +101 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8828 regset[3][13] regset[2][13] $abc$24881$new_n8827 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][13] regset[0][13] $abc$24881$new_n8828 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8830 regset[7][13] regset[6][13] $abc$24881$new_n8829 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][13] regset[4][13] $abc$24881$new_n8830 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8832 regset[11][13] regset[10][13] $abc$24881$new_n8831 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][13] regset[8][13] $abc$24881$new_n8832 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][13] regset[13][13] regset[12][13] $abc$24881$new_n8833 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8841 regset[27][14] regset[26][14] $abc$24881$new_n8840 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][14] regset[24][14] $abc$24881$new_n8841 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8843 regset[31][14] regset[30][14] $abc$24881$new_n8842 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][14] regset[28][14] $abc$24881$new_n8843 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8845 regset[19][14] regset[18][14] $abc$24881$new_n8844 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][14] regset[16][14] $abc$24881$new_n8845 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8847 regset[23][14] regset[22][14] $abc$24881$new_n8846 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][14] regset[20][14] $abc$24881$new_n8847 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8849 $abc$24881$new_n8857 $abc$24881$new_n8854 $abc$24881$new_n8848 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8850 $abc$24881$new_n8852 i_dbg_rreg[2] $abc$24881$new_n8849 +000 1 +001 1 +011 1 +.names $abc$24881$new_n8851 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][14] regset[4][14] $abc$24881$new_n8850 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][14] regset[6][14] $abc$24881$new_n8851 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8853 regset[3][14] regset[2][14] $abc$24881$new_n8852 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][14] regset[0][14] $abc$24881$new_n8853 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8855 regset[11][14] regset[10][14] $abc$24881$new_n8854 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][14] regset[8][14] $abc$24881$new_n8855 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][14] regset[13][14] regset[12][14] $abc$24881$new_n8857 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8864 regset[7][15] regset[6][15] $abc$24881$new_n8863 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][15] regset[4][15] $abc$24881$new_n8864 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8866 regset[3][15] regset[2][15] $abc$24881$new_n8865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][15] regset[0][15] $abc$24881$new_n8866 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8868 regset[11][15] regset[10][15] $abc$24881$new_n8867 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][15] regset[8][15] $abc$24881$new_n8868 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][15] regset[13][15] regset[12][15] $abc$24881$new_n8870 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8872 $abc$24881$new_n8877 $abc$24881$new_n8879 $abc$24881$new_n8871 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8875 $abc$24881$new_n8874 $abc$24881$new_n8873 $abc$24881$new_n8876 $abc$24881$new_n8872 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][15] regset[20][15] $abc$24881$new_n8873 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][15] regset[22][15] $abc$24881$new_n8874 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][15] regset[16][15] $abc$24881$new_n8875 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][15] regset[18][15] $abc$24881$new_n8876 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8878 regset[27][15] regset[26][15] $abc$24881$new_n8877 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][15] regset[24][15] $abc$24881$new_n8878 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8880 regset[31][15] regset[30][15] $abc$24881$new_n8879 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][15] regset[28][15] $abc$24881$new_n8880 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n8903 $abc$24881$new_n8883 $abc$24881$new_n8893 $0\genblk43.SETDBG.r_dbg_reg[31:0][16] +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n8884 i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8889 $abc$24881$new_n8891 $abc$24881$new_n8883 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8885 $abc$24881$new_n8887 $abc$24881$new_n8884 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8886 regset[11][16] regset[10][16] $abc$24881$new_n8885 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][16] regset[8][16] $abc$24881$new_n8886 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8888 regset[15][16] regset[14][16] $abc$24881$new_n8887 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][16] regset[12][16] $abc$24881$new_n8888 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8890 regset[3][16] regset[2][16] $abc$24881$new_n8889 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][16] regset[0][16] $abc$24881$new_n8890 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8892 regset[7][16] regset[6][16] $abc$24881$new_n8891 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][16] regset[4][16] $abc$24881$new_n8892 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8894 $abc$24881$new_n8899 $abc$24881$new_n8901 $abc$24881$new_n8893 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8897 $abc$24881$new_n8896 $abc$24881$new_n8895 $abc$24881$new_n8898 $abc$24881$new_n8894 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][16] regset[20][16] $abc$24881$new_n8895 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][16] regset[22][16] $abc$24881$new_n8896 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][16] regset[16][16] $abc$24881$new_n8897 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][16] regset[18][16] $abc$24881$new_n8898 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8900 regset[27][16] regset[26][16] $abc$24881$new_n8899 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][16] regset[24][16] $abc$24881$new_n8900 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8902 regset[31][16] regset[30][16] $abc$24881$new_n8901 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][16] regset[28][16] $abc$24881$new_n8902 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[4] SET_USER_PC.r_upc[16] ipc[16] $abc$24881$new_n8903 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8908 regset[11][17] regset[10][17] $abc$24881$new_n8907 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][17] regset[8][17] $abc$24881$new_n8908 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8910 regset[15][17] regset[14][17] $abc$24881$new_n8909 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][17] regset[12][17] $abc$24881$new_n8910 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8912 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][17] regset[0][17] $abc$24881$new_n8911 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][17] regset[2][17] $abc$24881$new_n8912 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n8914 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][17] regset[4][17] $abc$24881$new_n8913 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][17] regset[6][17] $abc$24881$new_n8914 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8916 $abc$24881$new_n8921 $abc$24881$new_n8923 $abc$24881$new_n8915 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n8919 $abc$24881$new_n8918 $abc$24881$new_n8917 $abc$24881$new_n8920 $abc$24881$new_n8916 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][17] regset[16][17] $abc$24881$new_n8917 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][17] regset[18][17] $abc$24881$new_n8918 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][17] regset[20][17] $abc$24881$new_n8919 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][17] regset[22][17] $abc$24881$new_n8920 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8922 regset[27][17] regset[26][17] $abc$24881$new_n8921 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][17] regset[24][17] $abc$24881$new_n8922 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8924 regset[31][17] regset[30][17] $abc$24881$new_n8923 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][17] regset[28][17] $abc$24881$new_n8924 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8930 regset[19][18] regset[18][18] $abc$24881$new_n8929 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][18] regset[16][18] $abc$24881$new_n8930 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8932 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][18] regset[20][18] $abc$24881$new_n8931 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][18] regset[22][18] $abc$24881$new_n8932 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8934 regset[27][18] regset[26][18] $abc$24881$new_n8933 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][18] regset[24][18] $abc$24881$new_n8934 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8936 regset[31][18] regset[30][18] $abc$24881$new_n8935 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][18] regset[28][18] $abc$24881$new_n8936 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8938 $abc$24881$new_n8946 $abc$24881$new_n8943 $abc$24881$new_n8937 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n8939 $abc$24881$new_n8941 $abc$24881$new_n8938 +0000 1 +0001 1 +1000 1 +1010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8940 regset[3][18] regset[2][18] $abc$24881$new_n8939 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][18] regset[0][18] $abc$24881$new_n8940 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8942 regset[7][18] regset[6][18] $abc$24881$new_n8941 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][18] regset[4][18] $abc$24881$new_n8942 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8944 regset[11][18] regset[10][18] $abc$24881$new_n8943 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][18] regset[8][18] $abc$24881$new_n8944 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][18] regset[13][18] regset[12][18] $abc$24881$new_n8946 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8955 regset[23][19] regset[22][19] $abc$24881$new_n8954 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][19] regset[20][19] $abc$24881$new_n8955 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8959 regset[27][19] regset[26][19] $abc$24881$new_n8958 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][19] regset[24][19] $abc$24881$new_n8959 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n6930 i_dbg_rreg[0] regset[15][19] regset[14][19] $abc$24881$new_n8963 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8966 regset[7][19] regset[6][19] $abc$24881$new_n8965 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][19] regset[4][19] $abc$24881$new_n8966 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8968 regset[3][19] regset[2][19] $abc$24881$new_n8967 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][19] regset[0][19] $abc$24881$new_n8968 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8970 regset[11][19] regset[10][19] $abc$24881$new_n8969 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][19] regset[8][19] $abc$24881$new_n8970 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8976 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][20] regset[20][20] $abc$24881$new_n8975 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][20] regset[22][20] $abc$24881$new_n8976 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n8978 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][20] regset[16][20] $abc$24881$new_n8977 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][20] regset[18][20] $abc$24881$new_n8978 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8983 regset[27][20] regset[26][20] $abc$24881$new_n8982 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][20] regset[24][20] $abc$24881$new_n8983 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8988 $abc$24881$new_n8986 i_dbg_rreg[2] $abc$24881$new_n8985 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8987 regset[7][20] regset[6][20] $abc$24881$new_n8986 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][20] regset[4][20] $abc$24881$new_n8987 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n8989 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][20] regset[0][20] $abc$24881$new_n8988 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][20] regset[2][20] $abc$24881$new_n8989 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8991 regset[11][20] regset[10][20] $abc$24881$new_n8990 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][20] regset[8][20] $abc$24881$new_n8991 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[14][20] regset[13][20] regset[12][20] $abc$24881$new_n8993 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9002 regset[11][21] regset[10][21] $abc$24881$new_n9001 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][21] regset[8][21] $abc$24881$new_n9002 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9007 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][21] regset[20][21] $abc$24881$new_n9006 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][21] regset[22][21] $abc$24881$new_n9007 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9010 regset[27][21] regset[26][21] $abc$24881$new_n9009 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][21] regset[24][21] $abc$24881$new_n9010 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9013 i_dbg_rreg[0] i_dbg_rreg[1] regset[5][21] regset[4][21] $abc$24881$new_n9012 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][21] regset[6][21] $abc$24881$new_n9013 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9015 regset[3][21] regset[2][21] $abc$24881$new_n9014 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][21] regset[0][21] $abc$24881$new_n9015 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[29][21] regset[28][21] $abc$24881$new_n9018 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9040 $abc$24881$new_n9020 $abc$24881$new_n9030 $0\genblk43.SETDBG.r_dbg_reg[31:0][22] +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9021 $abc$24881$new_n9026 $abc$24881$new_n9028 $abc$24881$new_n9020 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9022 $abc$24881$new_n9024 $abc$24881$new_n9021 +000 1 +001 1 +100 1 +110 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9023 regset[19][22] regset[18][22] $abc$24881$new_n9022 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][22] regset[16][22] $abc$24881$new_n9023 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9025 regset[23][22] regset[22][22] $abc$24881$new_n9024 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][22] regset[20][22] $abc$24881$new_n9025 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9027 regset[27][22] regset[26][22] $abc$24881$new_n9026 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][22] regset[24][22] $abc$24881$new_n9027 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9029 regset[31][22] regset[30][22] $abc$24881$new_n9028 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][22] regset[28][22] $abc$24881$new_n9029 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9031 $abc$24881$new_n9036 $abc$24881$new_n9038 $abc$24881$new_n9030 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9032 $abc$24881$new_n9034 $abc$24881$new_n9031 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9033 regset[7][22] regset[6][22] $abc$24881$new_n9032 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][22] regset[4][22] $abc$24881$new_n9033 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9035 regset[3][22] regset[2][22] $abc$24881$new_n9034 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][22] regset[0][22] $abc$24881$new_n9035 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9037 regset[11][22] regset[10][22] $abc$24881$new_n9036 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][22] regset[8][22] $abc$24881$new_n9037 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9039 regset[15][22] regset[14][22] $abc$24881$new_n9038 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[13][22] regset[12][22] $abc$24881$new_n9039 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[4] SET_USER_PC.r_upc[22] ipc[22] $abc$24881$new_n9040 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9046 regset[23][23] regset[22][23] $abc$24881$new_n9045 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][23] regset[20][23] $abc$24881$new_n9046 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9048 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][23] regset[16][23] $abc$24881$new_n9047 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][23] regset[18][23] $abc$24881$new_n9048 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9050 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][23] regset[28][23] $abc$24881$new_n9049 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][23] regset[30][23] $abc$24881$new_n9050 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9052 regset[27][23] regset[26][23] $abc$24881$new_n9051 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][23] regset[24][23] $abc$24881$new_n9052 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9054 $abc$24881$new_n9059 $abc$24881$new_n9061 $abc$24881$new_n9053 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9057 $abc$24881$new_n9055 i_dbg_rreg[2] $abc$24881$new_n9054 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9056 regset[7][23] regset[6][23] $abc$24881$new_n9055 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][23] regset[4][23] $abc$24881$new_n9056 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9058 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][23] regset[0][23] $abc$24881$new_n9057 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][23] regset[2][23] $abc$24881$new_n9058 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9060 regset[11][23] regset[10][23] $abc$24881$new_n9059 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][23] regset[8][23] $abc$24881$new_n9060 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][23] regset[13][23] regset[12][23] $abc$24881$new_n9061 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[11][24] regset[9][24] regset[8][24] $abc$24881$new_n9068 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9070 regset[7][24] regset[6][24] $abc$24881$new_n9069 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][24] regset[4][24] $abc$24881$new_n9070 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[0] regset[1][24] regset[0][24] $abc$24881$new_n9072 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9076 regset[23][24] regset[22][24] $abc$24881$new_n9075 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][24] regset[20][24] $abc$24881$new_n9076 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9078 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][24] regset[16][24] $abc$24881$new_n9077 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][24] regset[18][24] $abc$24881$new_n9078 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9080 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][24] regset[28][24] $abc$24881$new_n9079 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][24] regset[30][24] $abc$24881$new_n9080 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9082 regset[27][24] regset[26][24] $abc$24881$new_n9081 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][24] regset[24][24] $abc$24881$new_n9082 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9084 SET_USER_PC.r_upc[25] ipc[25] $0\genblk43.SETDBG.r_dbg_reg[31:0][25] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9095 $abc$24881$new_n9085 $abc$24881$new_n9084 +010 1 +011 1 +101 1 +111 1 +.names $abc$24881$new_n9086 i_dbg_rreg[3] $abc$24881$new_n9088 $abc$24881$new_n9093 i_dbg_rreg[2] $abc$24881$new_n9085 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9087 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][25] regset[28][25] $abc$24881$new_n9086 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][25] regset[30][25] $abc$24881$new_n9087 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9091 $abc$24881$new_n9090 $abc$24881$new_n9089 $abc$24881$new_n9092 $abc$24881$new_n9088 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][25] regset[16][25] $abc$24881$new_n9089 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][25] regset[18][25] $abc$24881$new_n9090 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][25] regset[20][25] $abc$24881$new_n9091 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][25] regset[22][25] $abc$24881$new_n9092 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9094 regset[27][25] regset[26][25] $abc$24881$new_n9093 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][25] regset[24][25] $abc$24881$new_n9094 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9096 $abc$24881$new_n9101 $abc$24881$new_n9103 $abc$24881$new_n9095 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[2] $abc$24881$new_n9097 $abc$24881$new_n9099 $abc$24881$new_n9096 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9098 regset[7][25] regset[6][25] $abc$24881$new_n9097 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][25] regset[4][25] $abc$24881$new_n9098 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9100 regset[3][25] regset[2][25] $abc$24881$new_n9099 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][25] regset[0][25] $abc$24881$new_n9100 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9102 regset[11][25] regset[10][25] $abc$24881$new_n9101 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][25] regset[8][25] $abc$24881$new_n9102 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][25] regset[13][25] regset[12][25] $abc$24881$new_n9103 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9109 regset[3][26] regset[2][26] $abc$24881$new_n9108 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][26] regset[0][26] $abc$24881$new_n9109 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9113 regset[11][26] regset[10][26] $abc$24881$new_n9112 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][26] regset[8][26] $abc$24881$new_n9113 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][26] regset[18][26] $abc$24881$new_n9119 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n9121 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][26] regset[20][26] $abc$24881$new_n9120 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][26] regset[22][26] $abc$24881$new_n9121 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][26] regset[24][26] $abc$24881$new_n9123 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n8653 i_dbg_rreg[0] $abc$24881$new_n8516 regset[13][27] regset[12][27] $abc$24881$new_n9129 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9133 $abc$24881$new_n9132 $abc$24881$new_n9131 $abc$24881$new_n9134 $abc$24881$new_n9130 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][27] regset[0][27] $abc$24881$new_n9131 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][27] regset[2][27] $abc$24881$new_n9132 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][27] regset[4][27] $abc$24881$new_n9133 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][27] regset[6][27] $abc$24881$new_n9134 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9136 regset[11][27] regset[10][27] $abc$24881$new_n9135 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][27] regset[8][27] $abc$24881$new_n9136 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9140 regset[23][27] regset[22][27] $abc$24881$new_n9139 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][27] regset[20][27] $abc$24881$new_n9140 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9142 i_dbg_rreg[0] i_dbg_rreg[1] regset[17][27] regset[16][27] $abc$24881$new_n9141 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][27] regset[18][27] $abc$24881$new_n9142 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9145 regset[27][27] regset[26][27] $abc$24881$new_n9144 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][27] regset[24][27] $abc$24881$new_n9145 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9154 regset[27][28] regset[26][28] $abc$24881$new_n9153 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][28] regset[24][28] $abc$24881$new_n9154 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9156 regset[31][28] regset[30][28] $abc$24881$new_n9155 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[29][28] regset[28][28] $abc$24881$new_n9156 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9158 regset[19][28] regset[18][28] $abc$24881$new_n9157 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][28] regset[16][28] $abc$24881$new_n9158 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9160 regset[23][28] regset[22][28] $abc$24881$new_n9159 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[21][28] regset[20][28] $abc$24881$new_n9160 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9166 regset[3][28] regset[2][28] $abc$24881$new_n9165 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][28] regset[0][28] $abc$24881$new_n9166 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9168 regset[11][28] regset[10][28] $abc$24881$new_n9167 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][28] regset[8][28] $abc$24881$new_n9168 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9177 regset[19][29] regset[18][29] $abc$24881$new_n9176 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][29] regset[16][29] $abc$24881$new_n9177 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9179 i_dbg_rreg[0] i_dbg_rreg[1] regset[21][29] regset[20][29] $abc$24881$new_n9178 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][29] regset[22][29] $abc$24881$new_n9179 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n9181 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][29] regset[28][29] $abc$24881$new_n9180 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][29] regset[30][29] $abc$24881$new_n9181 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9183 regset[27][29] regset[26][29] $abc$24881$new_n9182 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][29] regset[24][29] $abc$24881$new_n9183 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9185 $abc$24881$new_n9190 $abc$24881$new_n9192 $abc$24881$new_n9184 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9188 $abc$24881$new_n9186 i_dbg_rreg[2] $abc$24881$new_n9185 +000 1 +001 1 +010 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9187 regset[7][29] regset[6][29] $abc$24881$new_n9186 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[5][29] regset[4][29] $abc$24881$new_n9187 +000 1 +010 1 +100 1 +101 1 +.names $abc$24881$new_n9189 i_dbg_rreg[0] i_dbg_rreg[1] regset[1][29] regset[0][29] $abc$24881$new_n9188 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][29] regset[2][29] $abc$24881$new_n9189 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9191 regset[11][29] regset[10][29] $abc$24881$new_n9190 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][29] regset[8][29] $abc$24881$new_n9191 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][29] regset[13][29] regset[12][29] $abc$24881$new_n9192 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] $abc$24881$new_n9199 $abc$24881$new_n9198 $abc$24881$new_n9197 $abc$24881$new_n9200 $abc$24881$new_n9196 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[21][30] regset[20][30] $abc$24881$new_n9197 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][30] regset[22][30] $abc$24881$new_n9198 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[17][30] regset[16][30] $abc$24881$new_n9199 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][30] regset[18][30] $abc$24881$new_n9200 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9202 regset[27][30] regset[26][30] $abc$24881$new_n9201 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][30] regset[24][30] $abc$24881$new_n9202 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9209 $abc$24881$new_n9208 $abc$24881$new_n9207 $abc$24881$new_n9210 $abc$24881$new_n9206 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[5][30] regset[4][30] $abc$24881$new_n9207 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][30] regset[6][30] $abc$24881$new_n9208 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[1][30] regset[0][30] $abc$24881$new_n9209 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][30] regset[2][30] $abc$24881$new_n9210 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9212 regset[11][30] regset[10][30] $abc$24881$new_n9211 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][30] regset[8][30] $abc$24881$new_n9212 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9217 SET_USER_PC.r_upc[31] ipc[31] $0\genblk43.SETDBG.r_dbg_reg[31:0][31] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9218 $abc$24881$new_n9228 $abc$24881$new_n9217 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9219 i_dbg_rreg[3] $abc$24881$new_n9221 $abc$24881$new_n9226 i_dbg_rreg[2] $abc$24881$new_n9218 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9220 i_dbg_rreg[0] $abc$24881$new_n8516 regset[29][31] regset[28][31] $abc$24881$new_n9219 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] i_dbg_rreg[0] regset[31][31] regset[30][31] $abc$24881$new_n9220 +11001 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9224 $abc$24881$new_n9223 $abc$24881$new_n9222 $abc$24881$new_n9225 $abc$24881$new_n9221 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[17][31] regset[16][31] $abc$24881$new_n9222 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[19][31] regset[18][31] $abc$24881$new_n9223 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[21][31] regset[20][31] $abc$24881$new_n9224 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[23][31] regset[22][31] $abc$24881$new_n9225 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9227 regset[27][31] regset[26][31] $abc$24881$new_n9226 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[25][31] regset[24][31] $abc$24881$new_n9227 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9229 $abc$24881$new_n9234 $abc$24881$new_n9236 $abc$24881$new_n9228 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names i_dbg_rreg[1] $abc$24881$new_n9232 $abc$24881$new_n9231 $abc$24881$new_n9230 $abc$24881$new_n9233 $abc$24881$new_n9229 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +10000 1 +10010 1 +11000 1 +11010 1 +.names i_dbg_rreg[0] regset[1][31] regset[0][31] $abc$24881$new_n9230 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[3][31] regset[2][31] $abc$24881$new_n9231 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +.names i_dbg_rreg[0] regset[5][31] regset[4][31] $abc$24881$new_n9232 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] i_dbg_rreg[1] regset[7][31] regset[6][31] $abc$24881$new_n9233 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9235 regset[11][31] regset[10][31] $abc$24881$new_n9234 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[0] regset[9][31] regset[8][31] $abc$24881$new_n9235 +001 1 +011 1 +110 1 +111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][31] regset[13][31] regset[12][31] $abc$24881$new_n9236 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_halt r_halted $abc$24881$new_n4042 $abc$24881$new_n9238 $abc$24881$procmux$2428_Y +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_pf_valid $abc$24881$new_n6855 instruction_decoder.r_valid instruction_decoder.o_illegal $abc$24881$new_n9238 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3863 regset[11][0] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n3958 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9240 +1110 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3859 regset[11][1] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3853 regset[11][2] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3848 regset[11][3] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3843 regset[11][4] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3838 regset[11][5] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3832 regset[11][6] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3825 regset[11][7] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3820 regset[11][8] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3815 regset[11][9] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3810 regset[11][10] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3805 regset[11][11] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3800 regset[11][12] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3795 regset[11][13] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3790 regset[11][14] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3784 regset[11][15] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3779 regset[11][16] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3774 regset[11][17] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3769 regset[11][18] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3763 regset[11][19] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3757 regset[11][20] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3752 regset[11][21] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3747 regset[11][22] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3741 regset[11][23] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3735 regset[11][24] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3730 regset[11][25] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3725 regset[11][26] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3719 regset[11][27] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3714 regset[11][28] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3708 regset[11][29] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n3702 regset[11][30] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9240 $abc$24881$new_n6568 regset[11][31] $abc$24881$memory\regset$wrmux[11][0][0]$y$4386[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4042 i_bus_err i_halt GEN_PENDING_INTERRUPT.r_pending_interrupt $abc$24881$new_n6958 $abc$24881$new_n9274 +10000 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3863 regset[10][0] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7143 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9277 +1110 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3859 regset[10][1] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3853 regset[10][2] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3848 regset[10][3] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3843 regset[10][4] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3838 regset[10][5] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3832 regset[10][6] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3825 regset[10][7] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3820 regset[10][8] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3815 regset[10][9] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3810 regset[10][10] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3805 regset[10][11] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3800 regset[10][12] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3795 regset[10][13] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3790 regset[10][14] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3784 regset[10][15] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3779 regset[10][16] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3774 regset[10][17] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3769 regset[10][18] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3763 regset[10][19] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3757 regset[10][20] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3752 regset[10][21] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3747 regset[10][22] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3741 regset[10][23] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3735 regset[10][24] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3730 regset[10][25] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3725 regset[10][26] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3719 regset[10][27] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3714 regset[10][28] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3708 regset[10][29] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n3702 regset[10][30] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9277 $abc$24881$new_n6568 regset[10][31] $abc$24881$memory\regset$wrmux[10][0][0]$y$4380[31] +001 1 +011 1 +100 1 +101 1 +.names alu_ce $abc$24881$new_n6871 $abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y $abc$24881$procmux$2659_Y +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3863 regset[9][0] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7177 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9311 +1110 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3859 regset[9][1] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3853 regset[9][2] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3848 regset[9][3] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3843 regset[9][4] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3838 regset[9][5] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3832 regset[9][6] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3825 regset[9][7] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3820 regset[9][8] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3815 regset[9][9] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3810 regset[9][10] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3805 regset[9][11] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3800 regset[9][12] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3795 regset[9][13] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3790 regset[9][14] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3784 regset[9][15] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3779 regset[9][16] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3774 regset[9][17] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3769 regset[9][18] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3763 regset[9][19] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3757 regset[9][20] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3752 regset[9][21] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3747 regset[9][22] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3741 regset[9][23] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3735 regset[9][24] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3730 regset[9][25] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3725 regset[9][26] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3719 regset[9][27] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3714 regset[9][28] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3708 regset[9][29] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n3702 regset[9][30] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9311 $abc$24881$new_n6568 regset[9][31] $abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9344 GEN_OP_STALL.r_cc_invalid_for_dcd i_mem_rdbusy DIVIDE.thedivide.o_busy $abc$24881$procmux$2728_Y +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5375 $abc$24881$new_n9345 alu_ce mem_ce $abc$24881$new_n9344 +1001 1 +1010 1 +1011 1 +.names $abc$24881$new_n4048 SET_GIE.r_gie o_mem_reg[4] o_mem_reg[0] op_wF $abc$24881$new_n9345 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01010 1 +01100 1 +01110 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11110 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3863 regset[8][0] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n3701 $abc$24881$new_n7027 $abc$24881$new_n3694 $abc$24881$new_n3695 $abc$24881$new_n9347 +1110 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3859 regset[8][1] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3853 regset[8][2] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3848 regset[8][3] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3843 regset[8][4] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3838 regset[8][5] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3832 regset[8][6] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3825 regset[8][7] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3820 regset[8][8] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3815 regset[8][9] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3810 regset[8][10] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3805 regset[8][11] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3800 regset[8][12] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3795 regset[8][13] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3790 regset[8][14] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3784 regset[8][15] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3779 regset[8][16] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3774 regset[8][17] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3769 regset[8][18] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3763 regset[8][19] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3757 regset[8][20] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3752 regset[8][21] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3747 regset[8][22] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3741 regset[8][23] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3735 regset[8][24] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3730 regset[8][25] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3725 regset[8][26] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3719 regset[8][27] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3714 regset[8][28] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3708 regset[8][29] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n3702 regset[8][30] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n9347 $abc$24881$new_n6568 regset[8][31] $abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] +001 1 +011 1 +100 1 +101 1 +.names $abc$24881$new_n4083 $abc$24881$new_n3995 i_clear_cache o_dbg_stall $abc$24881$procmux$2755_Y +0010 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +.names DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[1] +01 1 +10 1 +.names DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[2] +011 1 +100 1 +101 1 +110 1 +.names DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[3] +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names DIVIDE.thedivide.r_bit[4] DIVIDE.thedivide.r_bit[3] DIVIDE.thedivide.r_bit[2] DIVIDE.thedivide.r_bit[1] DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.Y[4] +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names DIVIDE.thedivide.r_bit[0] $auto$alumacc.cc:485:replace_alu$3654.X[0] +0 1 +.names $abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] $abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] +0 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[29] $abc$24881$new_n3672 o_mem_data[30] $abc$24881$new_n9386 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9386 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[30] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22566 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[27] $abc$24881$new_n3673 o_mem_data[28] $abc$24881$new_n9388 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9388 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[28] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22570 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[25] $abc$24881$new_n3674 o_mem_data[26] $abc$24881$new_n9390 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9390 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[26] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22574 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.r_dividend[21] o_mem_data[23] $abc$24881$new_n9392 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[23] DIVIDE.thedivide.pre_sign $abc$24881$new_n9392 $abc$24881$new_n3676 $abc$24881$auto$rtlil.cc:2693:MuxGate$22580 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[21] $abc$24881$new_n3676 o_mem_data[22] $abc$24881$new_n9394 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9394 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[22] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22582 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.r_dividend[17] o_mem_data[19] $abc$24881$new_n9396 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11001 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[19] DIVIDE.thedivide.pre_sign $abc$24881$new_n9396 $abc$24881$new_n3678 $abc$24881$auto$rtlil.cc:2693:MuxGate$22588 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01010 1 +01011 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[17] $abc$24881$new_n3678 o_mem_data[18] $abc$24881$new_n9398 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9398 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[18] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22590 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[13] $abc$24881$new_n3681 o_mem_data[14] $abc$24881$new_n9400 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9400 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[14] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22598 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[6] $abc$24881$new_n3687 o_mem_data[7] $abc$24881$new_n9402 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9402 $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[7] DIVIDE.thedivide.pre_sign $abc$24881$auto$rtlil.cc:2693:MuxGate$22612 +0011 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.pre_sign DIVIDE.thedivide.r_busy DIVIDE.thedivide.r_dividend[4] $abc$24881$new_n3688 o_mem_data[5] $abc$24881$new_n9404 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n3704 DIVIDE.thedivide.r_dividend[5] DIVIDE.thedivide.pre_sign $abc$24881$new_n9404 DIVIDE.thedivide.r_dividend[3] $abc$24881$auto$rtlil.cc:2693:MuxGate$22616 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4062 alu_reg[0] instruction_decoder.o_dcdB[0] alu_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9406 +10000 1 +10011 1 +11100 1 +11111 1 +.names GEN_OP_WR.r_op_wR o_mem_reg[0] instruction_decoder.o_dcdB[0] o_mem_reg[1] instruction_decoder.o_dcdB[1] $abc$24881$new_n9410 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$24881$new_n9410 o_mem_reg[2] instruction_decoder.o_dcdB[2] o_mem_reg[3] instruction_decoder.o_dcdB[3] $abc$24881$new_n9411 +10000 1 +10011 1 +11100 1 +11111 1 +.names $abc$24881$new_n9411 o_mem_reg[4] instruction_decoder.o_dcdB[4] $abc$24881$new_n9412 +100 1 +111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] $abc$24881$new_n4113 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] pf_pc[22] $abc$24881$new_n9413 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9413 $abc$24881$new_n4094 $abc$24881$new_n4025 SET_USER_PC.r_upc[22] $abc$24881$new_n9414 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4160 $abc$24881$new_n4103 $abc$24881$new_n9414 ipc[22] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22818 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 pf_pc[14] $abc$24881$new_n4099 pf_pc[13] instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] $abc$24881$new_n9416 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9416 $abc$24881$new_n4116 $abc$24881$new_n4025 SET_USER_PC.r_upc[14] $abc$24881$new_n9417 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4198 $abc$24881$new_n4103 $abc$24881$new_n9417 ipc[14] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22834 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] $abc$24881$new_n4117 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] $abc$24881$new_n4099 $abc$24881$new_n9419 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9419 pf_pc[13] $abc$24881$new_n4025 SET_USER_PC.r_upc[13] $abc$24881$new_n9420 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4203 $abc$24881$new_n4103 $abc$24881$new_n9420 ipc[13] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22836 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4025 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] $abc$24881$new_n4119 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] $abc$24881$new_n4101 $abc$24881$new_n9422 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4087 $abc$24881$new_n9422 pf_pc[7] $abc$24881$new_n4025 SET_USER_PC.r_upc[7] $abc$24881$new_n9423 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n4232 $abc$24881$new_n4103 $abc$24881$new_n9423 ipc[7] $abc$24881$new_n4124 $abc$24881$auto$rtlil.cc:2693:MuxGate$22848 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11111 1 +.names $abc$24881$new_n4103 pf_pc[2] $abc$24881$new_n4125 $abc$24881$new_n4255 $abc$24881$new_n4024 $abc$24881$new_n9425 +00010 1 +00110 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9425 ipc[2] $abc$24881$new_n4124 $abc$24881$new_n4122 $abc$24881$new_n4019 $abc$24881$auto$rtlil.cc:2693:MuxGate$22858 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5149 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n5147 dcd_I[31] $abc$24881$new_n9427 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n4327 o_mem_addr[30] $abc$24881$new_n9427 $abc$24881$new_n5067 $abc$24881$auto$rtlil.cc:2693:MuxGate$22924 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4351 $abc$24881$new_n4344 $abc$24881$new_n9429 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] $abc$24881$new_n4395 $abc$24881$new_n4390 $abc$24881$new_n4388 $abc$24881$new_n9433 +00000 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n9439 instruction_decoder.o_dcdB[4] $abc$24881$new_n4383 $abc$24881$new_n4069 $abc$24881$new_n4385 $abc$24881$new_n9434 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4398 $abc$24881$new_n9434 instruction_decoder.o_dcdB[4] $abc$24881$new_n9433 $abc$24881$new_n4393 $abc$24881$new_n9435 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9435 $abc$24881$new_n3848 $abc$24881$new_n4368 $abc$24881$new_n9436 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][3] regset[28][3] $abc$24881$new_n9437 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n9437 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][3] regset[24][3] $abc$24881$new_n9438 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] $abc$24881$new_n9438 instruction_decoder.o_dcdB[1] $abc$24881$new_n4382 $abc$24881$new_n4381 $abc$24881$new_n9439 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[0] $abc$24881$new_n4429 $abc$24881$new_n4432 $abc$24881$new_n4433 $abc$24881$new_n9440 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n9449 instruction_decoder.o_dcdB[4] $abc$24881$new_n9445 $abc$24881$new_n9440 instruction_decoder.o_dcdB[1] $abc$24881$new_n9441 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$new_n4434 $abc$24881$new_n9441 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3853 $abc$24881$new_n9442 +01000 1 +01001 1 +01011 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][2] regset[6][2] $abc$24881$new_n9443 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdB[1] $abc$24881$new_n9443 instruction_decoder.o_dcdB[2] regset[3][2] regset[2][2] $abc$24881$new_n9444 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n9444 $abc$24881$new_n4414 $abc$24881$new_n4413 $abc$24881$new_n9445 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] regset[21][2] regset[17][2] $abc$24881$new_n9446 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9446 instruction_decoder.o_dcdB[0] regset[20][2] regset[16][2] $abc$24881$new_n9447 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9860 $abc$24881$new_n9447 $abc$24881$new_n9451 $abc$24881$new_n4416 $abc$24881$new_n9449 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][2] regset[22][2] $abc$24881$new_n9450 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9450 instruction_decoder.o_dcdB[2] regset[19][2] regset[18][2] $abc$24881$new_n9451 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][1] regset[30][1] $abc$24881$new_n9452 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9452 instruction_decoder.o_dcdB[2] regset[27][1] regset[26][1] $abc$24881$new_n9453 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n9453 $abc$24881$new_n9863 $abc$24881$new_n9464 $abc$24881$new_n9455 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][1] regset[20][1] $abc$24881$new_n9456 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9456 instruction_decoder.o_dcdB[2] regset[17][1] regset[16][1] $abc$24881$new_n9457 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][1] regset[22][1] $abc$24881$new_n9458 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9458 instruction_decoder.o_dcdB[2] regset[19][1] regset[18][1] $abc$24881$new_n9459 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4466 $abc$24881$new_n4465 $abc$24881$new_n9460 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][1] regset[4][1] $abc$24881$new_n9462 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9462 instruction_decoder.o_dcdB[2] regset[1][1] regset[0][1] $abc$24881$new_n9463 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9460 $abc$24881$new_n9466 instruction_decoder.o_dcdB[1] $abc$24881$new_n9865 $abc$24881$new_n9463 $abc$24881$new_n9464 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][1] regset[14][1] $abc$24881$new_n9465 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9465 instruction_decoder.o_dcdB[2] regset[11][1] regset[10][1] $abc$24881$new_n9466 +10000 1 +10010 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[15][0] regset[14][0] $abc$24881$new_n9467 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9467 instruction_decoder.o_dcdB[2] regset[11][0] regset[10][0] $abc$24881$new_n9468 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names dcd_Bcc instruction_decoder.o_dcdB[0] $abc$24881$new_n4349 $abc$24881$new_n4495 $abc$24881$new_n4496 $abc$24881$new_n9469 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[7][0] regset[6][0] $abc$24881$new_n9471 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9471 instruction_decoder.o_dcdB[2] regset[3][0] regset[2][0] $abc$24881$new_n9472 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][0] regset[22][0] $abc$24881$new_n9473 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9473 instruction_decoder.o_dcdB[2] regset[19][0] regset[18][0] $abc$24881$new_n9474 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n4504 instruction_decoder.o_dcdB[0] $abc$24881$new_n4069 $abc$24881$new_n4508 $abc$24881$new_n4509 $abc$24881$new_n9475 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[21][0] regset[20][0] $abc$24881$new_n9477 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9477 instruction_decoder.o_dcdB[2] regset[17][0] regset[16][0] $abc$24881$new_n9478 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4529 $abc$24881$new_n4524 $abc$24881$new_n4542 $abc$24881$new_n9479 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[5][6] regset[4][6] $abc$24881$new_n9483 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4349 $abc$24881$new_n9483 instruction_decoder.o_dcdB[2] regset[1][6] regset[0][6] $abc$24881$new_n9484 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4533 $abc$24881$new_n4538 $abc$24881$new_n9485 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4504 $abc$24881$new_n9485 instruction_decoder.o_dcdB[3] $abc$24881$new_n4540 $abc$24881$new_n4536 $abc$24881$new_n9486 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n4554 $abc$24881$new_n4550 $abc$24881$new_n4549 $abc$24881$new_n9487 +00000 1 +00100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9487 instruction_decoder.o_dcdB[3] $abc$24881$new_n4552 $abc$24881$new_n4547 $abc$24881$new_n9488 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +.names $abc$24881$new_n4556 $abc$24881$new_n9488 $abc$24881$new_n4368 $abc$24881$new_n3838 $abc$24881$new_n4472 $abc$24881$new_n9489 +01000 1 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_TRAP_N_UBREAK.r_ubreak break_en $abc$24881$new_n4580 $abc$24881$new_n9490 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4570 $abc$24881$new_n4577 $abc$24881$new_n4587 $abc$24881$new_n9491 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9490 dcd_Bcc $abc$24881$new_n9491 $abc$24881$new_n9492 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$24881$new_n9492 $abc$24881$new_n3825 $abc$24881$new_n4368 $abc$24881$new_n9493 +100 1 +110 1 +111 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] SET_USER_BUSERR.r_ubus_err_flag $abc$24881$new_n4625 $abc$24881$new_n4623 $abc$24881$new_n9494 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9494 instruction_decoder.o_dcdB[4] ibus_err_flag $abc$24881$new_n4616 $abc$24881$new_n4632 $abc$24881$new_n9495 +00010 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9495 $abc$24881$new_n4368 $abc$24881$new_n3810 $abc$24881$new_n9496 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4703 $abc$24881$new_n4349 $abc$24881$new_n4691 $abc$24881$new_n9497 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9497 $abc$24881$new_n4694 $abc$24881$new_n4701 $abc$24881$new_n4686 $abc$24881$new_n9498 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9498 $abc$24881$new_n4368 $abc$24881$new_n3800 $abc$24881$new_n9499 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names dcd_Bcc instruction_decoder.o_dcdB[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n4717 $abc$24881$new_n4715 $abc$24881$new_n9500 +01010 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9500 instruction_decoder.o_dcdB[4] GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n4708 $abc$24881$new_n4724 $abc$24881$new_n9501 +00010 1 +00110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9501 $abc$24881$new_n4368 $abc$24881$new_n3795 $abc$24881$new_n9502 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4356 $abc$24881$new_n4747 $abc$24881$new_n4349 $abc$24881$new_n4735 $abc$24881$new_n9503 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01101 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9503 $abc$24881$new_n4738 $abc$24881$new_n4745 $abc$24881$new_n4730 $abc$24881$new_n9504 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9504 $abc$24881$new_n4368 $abc$24881$new_n3790 $abc$24881$new_n9505 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4759 $abc$24881$new_n4757 $abc$24881$new_n4755 $abc$24881$new_n9506 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9506 $abc$24881$new_n4753 $abc$24881$new_n4761 $abc$24881$new_n4768 $abc$24881$new_n9507 +00010 1 +00110 1 +01010 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9507 $abc$24881$new_n4368 $abc$24881$new_n3779 $abc$24881$new_n9508 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n4784 $abc$24881$new_n4791 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n4789 $abc$24881$new_n9509 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9509 $abc$24881$new_n4774 $abc$24881$new_n4069 $abc$24881$new_n4781 $abc$24881$new_n9510 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9510 $abc$24881$new_n4368 $abc$24881$new_n3784 $abc$24881$new_n9511 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[1] $abc$24881$new_n4805 $abc$24881$new_n4803 $abc$24881$new_n4801 $abc$24881$new_n9512 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9512 $abc$24881$new_n4799 $abc$24881$new_n4807 $abc$24881$new_n4814 $abc$24881$new_n9513 +00010 1 +00110 1 +01010 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9513 $abc$24881$new_n4368 $abc$24881$new_n3774 $abc$24881$new_n9514 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[23][21] regset[22][21] $abc$24881$new_n9515 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n4356 $abc$24881$new_n9515 instruction_decoder.o_dcdB[2] regset[19][21] regset[18][21] $abc$24881$new_n9516 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 instruction_decoder.o_dcdB[4] $abc$24881$new_n4893 $abc$24881$new_n4884 $abc$24881$new_n9516 $abc$24881$new_n9517 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n9517 $abc$24881$new_n3752 $abc$24881$new_n4368 $abc$24881$new_n9518 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4929 $abc$24881$new_n4936 $abc$24881$new_n4946 $abc$24881$new_n9519 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9519 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4939 $abc$24881$new_n9520 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9520 $abc$24881$new_n3735 $abc$24881$new_n4368 $abc$24881$new_n9521 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4952 $abc$24881$new_n4959 $abc$24881$new_n4969 $abc$24881$new_n9522 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9522 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4962 $abc$24881$new_n9523 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9523 $abc$24881$new_n3741 $abc$24881$new_n4368 $abc$24881$new_n9524 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n4069 $abc$24881$new_n4976 $abc$24881$new_n4983 $abc$24881$new_n4993 $abc$24881$new_n9525 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9525 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4986 $abc$24881$new_n9526 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +11000 1 +11100 1 +11101 1 +.names $abc$24881$new_n9526 $abc$24881$new_n3730 $abc$24881$new_n4368 $abc$24881$new_n9527 +100 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5007 $abc$24881$new_n5017 $abc$24881$new_n9528 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9528 instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n5000 $abc$24881$new_n5010 $abc$24881$new_n9529 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9529 $abc$24881$new_n4368 $abc$24881$new_n3719 $abc$24881$new_n9530 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names $abc$24881$new_n5032 $abc$24881$new_n5039 $abc$24881$new_n4349 $abc$24881$new_n4356 $abc$24881$new_n5037 $abc$24881$new_n9531 +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9531 $abc$24881$new_n5022 $abc$24881$new_n4069 $abc$24881$new_n5029 $abc$24881$new_n9532 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9532 $abc$24881$new_n4368 $abc$24881$new_n3725 $abc$24881$new_n9533 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdB[3] instruction_decoder.o_dcdB[4] $abc$24881$new_n5058 $abc$24881$new_n5055 $abc$24881$new_n9534 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[3] $abc$24881$new_n5078 $abc$24881$new_n5074 $abc$24881$new_n5072 $abc$24881$new_n9539 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9539 $abc$24881$new_n5080 instruction_decoder.o_dcdB[1] $abc$24881$new_n5076 $abc$24881$new_n9540 +01000 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n4373 $abc$24881$new_n9540 dcd_Bcc $abc$24881$new_n4368 $abc$24881$new_n3708 $abc$24881$new_n9541 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names $abc$24881$new_n5147 $abc$24881$new_n5148 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5113 $abc$24881$new_n9542 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10010 1 +10011 1 +10101 1 +11010 1 +11011 1 +11110 1 +.names $abc$24881$new_n9542 $abc$24881$new_n9541 $abc$24881$new_n4328 $abc$24881$new_n5067 $abc$24881$new_n9543 +0010 1 +0100 1 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9543 o_mem_addr[29] $abc$24881$auto$rtlil.cc:2693:MuxGate$22926 +001 1 +011 1 +110 1 +111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9877 $abc$24881$new_n5166 $abc$24881$new_n5148 $abc$24881$new_n5113 $abc$24881$new_n9545 +00000 1 +00001 1 +00010 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10101 1 +10110 1 +11001 1 +11010 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 dcd_I[31] $abc$24881$new_n9545 o_mem_addr[28] $abc$24881$auto$rtlil.cc:2693:MuxGate$22928 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names $abc$24881$new_n5145 $abc$24881$new_n5146 $abc$24881$new_n5067 dcd_I[31] $abc$24881$new_n5114 $abc$24881$new_n9547 +00010 1 +00011 1 +00100 1 +01010 1 +01011 1 +01111 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9547 $abc$24881$new_n9533 $abc$24881$new_n5171 $abc$24881$new_n5067 $abc$24881$new_n9548 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11110 1 +.names dcd_I[31] $abc$24881$new_n9524 $abc$24881$new_n9521 $abc$24881$new_n9843 $abc$24881$new_n9549 +0000 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n5182 $abc$24881$new_n9549 $abc$24881$new_n4972 $abc$24881$new_n5067 $abc$24881$new_n9550 +1000 1 +1001 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9550 $abc$24881$new_n5066 r_op_Bv[25] $abc$24881$new_n3730 $abc$24881$auto$rtlil.cc:2693:MuxGate$22934 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9524 $abc$24881$new_n9843 dcd_I[31] $abc$24881$new_n5192 $abc$24881$new_n9552 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9552 r_op_Bv[23] $abc$24881$new_n3741 $abc$24881$auto$rtlil.cc:2693:MuxGate$22938 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4904 dcd_I[31] $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n9554 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[22] $abc$24881$new_n9554 $abc$24881$new_n5196 $abc$24881$auto$rtlil.cc:2693:MuxGate$22940 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5201 $abc$24881$new_n9518 $abc$24881$new_n9844 dcd_I[21] $abc$24881$new_n5065 $abc$24881$new_n9556 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9556 $abc$24881$new_n5066 r_op_Bv[21] $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$22942 +00010 1 +00011 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4860 dcd_I[20] $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] $abc$24881$new_n9558 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[20] $abc$24881$new_n9558 $abc$24881$new_n5205 $abc$24881$auto$rtlil.cc:2693:MuxGate$22944 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n4817 dcd_I[18] $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n9560 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[18] $abc$24881$new_n9560 $abc$24881$new_n5214 $abc$24881$auto$rtlil.cc:2693:MuxGate$22948 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5219 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] $abc$24881$new_n5065 $abc$24881$new_n9562 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01100 1 +01110 1 +01111 1 +.names $abc$24881$new_n5151 $abc$24881$new_n9562 $abc$24881$new_n5066 r_op_Bv[17] $abc$24881$new_n3774 $abc$24881$auto$rtlil.cc:2693:MuxGate$22950 +00010 1 +00011 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5224 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n9564 +0000 1 +0001 1 +0011 1 +0101 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[16] $abc$24881$new_n9564 $abc$24881$new_n5223 $abc$24881$auto$rtlil.cc:2693:MuxGate$22952 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] $abc$24881$new_n5229 $abc$24881$new_n9566 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9566 r_op_Bv[15] $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$22954 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n9502 $abc$24881$new_n9847 dcd_I[13] $abc$24881$new_n5238 $abc$24881$new_n9568 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5151 $abc$24881$new_n9568 r_op_Bv[13] $abc$24881$new_n3795 $abc$24881$auto$rtlil.cc:2693:MuxGate$22958 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9499 dcd_I[12] $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] $abc$24881$new_n9570 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[12] $abc$24881$new_n9570 $abc$24881$new_n5242 $abc$24881$auto$rtlil.cc:2693:MuxGate$22960 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n9496 dcd_I[10] $abc$24881$new_n4636 $abc$24881$new_n4337 dcd_I[9] $abc$24881$new_n9572 +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01011 1 +01101 1 +10000 1 +10001 1 +10011 1 +10101 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names $abc$24881$new_n5066 $abc$24881$new_n5067 o_mem_addr[10] $abc$24881$new_n9572 $abc$24881$new_n5250 $abc$24881$auto$rtlil.cc:2693:MuxGate$22964 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5067 $abc$24881$new_n5279 $abc$24881$new_n5128 $abc$24881$new_n9858 dcd_I[4] $abc$24881$new_n9574 +00001 1 +00010 1 +00101 1 +00110 1 +01001 1 +01010 1 +01101 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5066 $abc$24881$new_n9574 $abc$24881$new_n5276 $abc$24881$new_n5067 o_mem_addr[4] $abc$24881$auto$rtlil.cc:2693:MuxGate$22976 +00001 1 +00011 1 +00101 1 +00111 1 +01001 1 +01011 1 +01101 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names dcd_Apc $abc$24881$new_n5601 $abc$24881$new_n5602 dcd_Acc $abc$24881$new_n9576 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[30] $abc$24881$new_n9576 $abc$24881$new_n3702 $abc$24881$auto$rtlil.cc:2693:MuxGate$23378 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5646 $abc$24881$new_n5635 $abc$24881$new_n9578 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[28] SET_USER_PC.r_upc[28] $abc$24881$new_n9582 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9582 dcd_Acc dcd_Apc $abc$24881$new_n5652 $abc$24881$new_n5662 $abc$24881$new_n9583 +00000 1 +00010 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[28] $abc$24881$new_n9583 $abc$24881$new_n3714 $abc$24881$auto$rtlil.cc:2693:MuxGate$23382 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5689 $abc$24881$new_n5691 $abc$24881$new_n9585 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9585 instruction_decoder.o_dcdA[3] $abc$24881$new_n5694 $abc$24881$new_n5697 $abc$24881$new_n9586 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[26] SET_USER_PC.r_upc[26] $abc$24881$new_n9589 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9589 dcd_Acc dcd_Apc $abc$24881$new_n5713 $abc$24881$new_n5703 $abc$24881$new_n9590 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[26] $abc$24881$new_n9590 $abc$24881$new_n3725 $abc$24881$auto$rtlil.cc:2693:MuxGate$23386 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n5759 $abc$24881$new_n5769 $abc$24881$new_n9592 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n5793 $abc$24881$new_n5783 $abc$24881$new_n9596 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9596 instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n5786 $abc$24881$new_n5776 $abc$24881$new_n9597 +10001 1 +10011 1 +11010 1 +11011 1 +.names $abc$24881$new_n5596 dcd_Apc $abc$24881$new_n3741 $abc$24881$new_n5795 $abc$24881$new_n9597 $abc$24881$new_n9598 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5809 $abc$24881$new_n5815 $abc$24881$new_n5817 $abc$24881$new_n9599 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5819 $abc$24881$new_n5799 $abc$24881$new_n9599 $abc$24881$new_n9600 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[22] $abc$24881$new_n9600 $abc$24881$new_n3747 $abc$24881$auto$rtlil.cc:2693:MuxGate$23394 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5843 $abc$24881$new_n5822 $abc$24881$new_n5832 $abc$24881$new_n9602 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[21] $abc$24881$new_n9602 $abc$24881$new_n3752 $abc$24881$auto$rtlil.cc:2693:MuxGate$23396 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[20] SET_USER_PC.r_upc[20] $abc$24881$new_n9604 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9604 dcd_Apc $abc$24881$new_n5857 $abc$24881$new_n5847 $abc$24881$new_n9605 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[20] $abc$24881$new_n9605 $abc$24881$new_n3757 $abc$24881$auto$rtlil.cc:2693:MuxGate$23398 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5905 $abc$24881$new_n5913 $abc$24881$new_n5911 $abc$24881$new_n9607 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5915 $abc$24881$new_n5895 $abc$24881$new_n9607 $abc$24881$new_n9608 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[18] $abc$24881$new_n9608 $abc$24881$new_n3769 $abc$24881$auto$rtlil.cc:2693:MuxGate$23402 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5953 $abc$24881$new_n5959 $abc$24881$new_n5961 $abc$24881$new_n9610 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc instruction_decoder.o_dcdA[4] $abc$24881$new_n5963 $abc$24881$new_n5943 $abc$24881$new_n9610 $abc$24881$new_n9611 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[16] $abc$24881$new_n9611 $abc$24881$new_n3779 $abc$24881$auto$rtlil.cc:2693:MuxGate$23406 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[15] SET_USER_PC.r_upc[15] $abc$24881$new_n9613 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9613 dcd_Acc dcd_Apc $abc$24881$new_n5967 $abc$24881$new_n5977 $abc$24881$new_n9614 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[15] $abc$24881$new_n9614 $abc$24881$new_n3784 $abc$24881$auto$rtlil.cc:2693:MuxGate$23408 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[14] SET_USER_PC.r_upc[14] $abc$24881$new_n9616 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9616 dcd_Acc dcd_Apc $abc$24881$new_n6002 $abc$24881$new_n9619 $abc$24881$new_n9617 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[14] $abc$24881$new_n9617 $abc$24881$new_n3790 $abc$24881$auto$rtlil.cc:2693:MuxGate$23410 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n5992 $abc$24881$new_n5998 $abc$24881$new_n6000 $abc$24881$new_n9619 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc $abc$24881$new_n6040 $abc$24881$new_n6041 dcd_Acc $abc$24881$new_n9620 +0001 1 +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[12] $abc$24881$new_n9620 $abc$24881$new_n3800 $abc$24881$auto$rtlil.cc:2693:MuxGate$23414 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[29][11] regset[28][11] $abc$24881$new_n9622 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n5637 $abc$24881$new_n9622 instruction_decoder.o_dcdA[2] regset[25][11] regset[24][11] $abc$24881$new_n9623 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names dcd_Acc DIVERR.USER_DIVERR.r_udiv_err_flag $abc$24881$new_n6067 $abc$24881$new_n9623 $abc$24881$new_n9624 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9624 DIVERR.r_idiv_err_flag $abc$24881$new_n6076 $abc$24881$new_n9625 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6197 $abc$24881$new_n6192 $abc$24881$new_n9626 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[5] SET_USER_PC.r_upc[5] $abc$24881$new_n9630 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9630 dcd_Acc dcd_Apc $abc$24881$new_n6213 $abc$24881$new_n6223 $abc$24881$new_n9631 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[5] $abc$24881$new_n9631 $abc$24881$new_n3838 $abc$24881$auto$rtlil.cc:2693:MuxGate$23428 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[4] $abc$24881$new_n6241 $abc$24881$new_n6239 $abc$24881$new_n6249 $abc$24881$new_n9633 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n6251 instruction_decoder.o_dcdA[1] $abc$24881$new_n9633 $abc$24881$new_n6243 $abc$24881$new_n9634 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10101 1 +10111 1 +11001 1 +11101 1 +11111 1 +.names dcd_Acc $abc$24881$new_n9634 sleep $abc$24881$new_n9635 +010 1 +011 1 +101 1 +111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6272 $abc$24881$new_n6269 $abc$24881$new_n6264 $abc$24881$new_n9636 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6275 $abc$24881$new_n6282 $abc$24881$new_n6280 $abc$24881$new_n9637 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9637 $abc$24881$new_n9636 $abc$24881$new_n6266 $abc$24881$new_n9638 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9638 $abc$24881$new_n4399 $abc$24881$new_n4404 $abc$24881$new_n9639 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names dcd_Apc $abc$24881$new_n4071 $abc$24881$new_n9645 SET_USER_PC.r_upc[2] instruction_decoder.o_pc[2] $abc$24881$new_n9640 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[2] $abc$24881$new_n9640 $abc$24881$new_n3853 $abc$24881$auto$rtlil.cc:2693:MuxGate$23434 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6294 $abc$24881$new_n6297 $abc$24881$new_n6300 $abc$24881$new_n9642 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6303 $abc$24881$new_n6310 $abc$24881$new_n6308 $abc$24881$new_n9643 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9643 $abc$24881$new_n9642 $abc$24881$new_n6291 $abc$24881$new_n9644 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n9644 $abc$24881$new_n4438 $abc$24881$new_n4435 $abc$24881$new_n9645 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n4468 $abc$24881$new_n6328 $abc$24881$new_n9646 +0001 1 +0011 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names instruction_decoder.o_dcdA[1] instruction_decoder.o_dcdA[3] $abc$24881$new_n6320 $abc$24881$new_n6323 $abc$24881$new_n6326 $abc$24881$new_n9648 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names instruction_decoder.o_dcdA[4] instruction_decoder.o_dcdA[3] instruction_decoder.o_dcdA[1] $abc$24881$new_n6361 $abc$24881$new_n6351 $abc$24881$new_n9650 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_pf_instruction_pc[29] $abc$24881$new_n6382 i_pf_instruction[17] $abc$24881$new_n6366 i_pf_instruction_pc[28] $abc$24881$new_n9654 +00001 1 +00011 1 +01011 1 +01100 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] $abc$24881$new_n4278 $abc$24881$new_n9654 $abc$24881$auto$rtlil.cc:2693:MuxGate$23442 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Acc instruction_decoder.o_dcdA[4] $abc$24881$new_n5637 $abc$24881$new_n6566 $abc$24881$new_n6556 $abc$24881$new_n9656 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names $abc$24881$new_n5595 instruction_decoder.o_dcdA[4] $abc$24881$new_n9656 $abc$24881$new_n6558 $abc$24881$new_n6549 $abc$24881$new_n9657 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6683 $abc$24881$new_n6662 $abc$24881$new_n6682 $abc$24881$new_n9658 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names alu_ce doalu.c $abc$24881$new_n6685 $abc$24881$new_n6655 $abc$24881$new_n9658 $abc$24881$auto$rtlil.cc:2693:MuxGate$23622 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$24881$new_n3692 r_op_Av[3] $abc$24881$new_n3848 $abc$24881$new_n9660 +000 1 +001 1 +101 1 +111 1 +.names $abc$24881$new_n6678 o_mem_addr[3] $abc$24881$new_n9660 $abc$24881$new_n6680 $abc$24881$new_n6679 $abc$24881$new_n9661 +00000 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n6746 $abc$24881$new_n6741 $abc$24881$new_n6745 $abc$24881$new_n9662 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[5] o_mem_addr[4] o_mem_data[31] $abc$24881$new_n6727 $abc$24881$new_n9662 $abc$24881$new_n9663 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[5] $abc$24881$new_n6776 $abc$24881$new_n9663 o_mem_data[0] $abc$24881$new_n6751 $abc$24881$new_n9664 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n4282 $abc$24881$new_n4284 $abc$24881$new_n4302 $abc$24881$new_n4292 $abc$24881$new_n4280 $abc$24881$new_n9665 +10001 1 +10111 1 +11000 1 +11110 1 +.names $abc$24881$new_n9665 $abc$24881$new_n4288 $abc$24881$new_n4290 $abc$24881$new_n4279 $abc$24881$new_n4278 $abc$24881$new_n9666 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$24881$new_n4028 instruction_decoder.GEN_OPIPE.r_insn_is_pipeable $abc$24881$new_n6801 $abc$24881$new_n9666 $abc$24881$auto$rtlil.cc:2693:MuxGate$23632 +0011 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names DIVIDE.thedivide.r_dividend[44] DIVIDE.thedivide.r_divisor[13] DIVIDE.thedivide.r_dividend[46] DIVIDE.thedivide.r_divisor[15] $abc$24881$new_n3932 $abc$24881$new_n9668 +00000 1 +00110 1 +11000 1 +11110 1 +.names $abc$24881$new_n3879 DIVIDE.thedivide.r_divisor[12] DIVIDE.thedivide.r_dividend[43] DIVIDE.thedivide.r_divisor[11] DIVIDE.thedivide.r_dividend[42] $abc$24881$new_n9669 +00000 1 +00011 1 +01100 1 +01111 1 +10100 1 +10111 1 +11000 1 +11011 1 +.names $abc$24881$new_n6943 $abc$24881$new_n9669 $abc$24881$new_n9668 $abc$24881$new_n3922 $abc$24881$new_n3917 $abc$24881$new_n9670 +11100 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7726 o_mem_addr[0] o_mem_data[0] $abc$24881$new_n9671 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n9671 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9672 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[1] o_mem_data[1] $abc$24881$new_n6775 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9674 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[2] o_mem_addr[1] $abc$24881$new_n7737 $abc$24881$new_n6771 $abc$24881$new_n6774 $abc$24881$new_n9678 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7733 $abc$24881$new_n9678 $abc$24881$new_n9679 +0001 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names o_mem_addr[5] o_mem_data[5] $abc$24881$new_n7843 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9680 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7721 $abc$24881$new_n9680 $abc$24881$new_n7844 $abc$24881$new_n9681 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9681 $abc$24881$new_n7826 $abc$24881$new_n7847 $abc$24881$auto$rtlil.cc:2582:Mux$3529[5] +100 1 +110 1 +111 1 +.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7884 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9683 +00101 1 +01001 1 +10000 1 +10001 1 +10010 1 +10100 1 +10110 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[7] o_mem_data[7] $abc$24881$new_n7881 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9684 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names o_mem_addr[3] o_mem_addr[4] $abc$24881$new_n7700 $abc$24881$new_n7695 $abc$24881$new_n7706 $abc$24881$new_n9688 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names $abc$24881$new_n7888 $abc$24881$new_n7692 $abc$24881$new_n9688 $abc$24881$new_n7689 $abc$24881$new_n7891 $abc$24881$new_n9689 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7892 $abc$24881$new_n7897 $abc$24881$new_n9689 $abc$24881$new_n7728 $abc$24881$auto$rtlil.cc:2582:Mux$3529[8] +0000 1 +0001 1 +0010 1 +0011 1 +0110 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6696 DIVIDE.thedivide.i_signed $abc$24881$new_n6654 $abc$24881$new_n9691 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +01000 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10101 1 +10111 1 +11001 1 +.names $abc$24881$new_n7722 o_mem_addr[10] o_mem_data[10] $abc$24881$new_n9691 $abc$24881$new_n9692 +0001 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1110 1 +1111 1 +.names o_mem_addr[10] o_mem_data[10] $abc$24881$new_n6672 DIVIDE.thedivide.i_signed $abc$24881$new_n7722 $abc$24881$new_n9693 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +10000 1 +11100 1 +11101 1 +.names $abc$24881$new_n6656 $abc$24881$new_n9692 $abc$24881$new_n9693 $abc$24881$new_n9694 +010 1 +011 1 +101 1 +111 1 +.names o_mem_addr[12] o_mem_data[12] $abc$24881$new_n6671 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9695 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01100 1 +10100 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9695 $abc$24881$new_n6656 $abc$24881$new_n7954 $abc$24881$new_n9696 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9696 $abc$24881$new_n7945 $abc$24881$auto$rtlil.cc:2582:Mux$3529[12] +10 1 +.names o_mem_addr[13] o_mem_data[13] $abc$24881$new_n7971 $abc$24881$new_n7724 $abc$24881$new_n7722 $abc$24881$new_n9698 +00000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11110 1 +.names $abc$24881$new_n7958 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9698 $abc$24881$new_n7972 $abc$24881$auto$rtlil.cc:2582:Mux$3529[13] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n6658 $abc$24881$new_n6776 o_mem_addr[4] o_mem_data[31] $abc$24881$new_n7718 $abc$24881$new_n9700 +01000 1 +01001 1 +01010 1 +01011 1 +01101 1 +01111 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$24881$new_n9700 $abc$24881$new_n7728 o_mem_addr[4] $abc$24881$new_n6727 $abc$24881$new_n7694 $abc$24881$new_n9701 +00000 1 +00010 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n6786 $abc$24881$new_n9701 o_mem_data[31] $abc$24881$new_n6658 $abc$24881$new_n7728 $abc$24881$new_n9702 +00110 1 +01110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6653 $abc$24881$new_n6654 $abc$24881$new_n6711 $abc$24881$new_n6692 $abc$24881$new_n9703 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1110 1 +.names o_mem_addr[20] o_mem_data[20] $abc$24881$new_n9703 $abc$24881$new_n7722 $abc$24881$new_n6653 $abc$24881$new_n9704 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +10000 1 +10001 1 +11000 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n8056 $abc$24881$new_n9704 $abc$24881$new_n6656 $abc$24881$new_n9705 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9705 $abc$24881$new_n9709 $abc$24881$new_n8063 $abc$24881$auto$rtlil.cc:2582:Mux$3529[20] +100 1 +110 1 +111 1 +.names o_mem_addr[4] o_mem_addr[3] $abc$24881$new_n7817 $abc$24881$new_n7949 $abc$24881$new_n8062 $abc$24881$new_n9707 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7690 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n9707 $abc$24881$new_n7812 $abc$24881$new_n9708 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n7728 $abc$24881$new_n9708 $abc$24881$new_n6657 $abc$24881$new_n6658 $abc$24881$new_n8058 $abc$24881$new_n9709 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +.names o_mem_addr[24] o_mem_data[24] $abc$24881$new_n7722 $abc$24881$new_n7723 $abc$24881$new_n7721 $abc$24881$new_n9710 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9710 $abc$24881$new_n8110 $abc$24881$new_n7721 $abc$24881$new_n8108 $abc$24881$new_n9711 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9711 $abc$24881$new_n8112 $abc$24881$new_n7820 o_mem_addr[7] $abc$24881$auto$rtlil.cc:2582:Mux$3529[24] +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$24881$new_n7727 o_mem_data[28] o_mem_addr[28] DIVIDE.thedivide.i_signed o_mem_addr[3] $abc$24881$new_n9713 +00001 1 +00101 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n9713 $abc$24881$new_n7726 $abc$24881$new_n8163 $abc$24881$new_n7728 $abc$24881$new_n9714 +00000 1 +00100 1 +01000 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8161 $abc$24881$new_n7727 $abc$24881$new_n8158 $abc$24881$new_n9714 $abc$24881$new_n7722 $abc$24881$auto$rtlil.cc:2582:Mux$3529[28] +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8181 $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7961 $abc$24881$new_n7963 $abc$24881$new_n9716 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names $abc$24881$new_n7728 $abc$24881$new_n8185 $abc$24881$new_n8179 $abc$24881$new_n9716 $abc$24881$new_n7690 $abc$24881$new_n9717 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9717 $abc$24881$new_n7727 $abc$24881$new_n8186 $abc$24881$new_n8173 $abc$24881$new_n8171 $abc$24881$auto$rtlil.cc:2582:Mux$3529[29] +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7722 o_mem_data[31] o_mem_addr[31] $abc$24881$new_n6656 $abc$24881$new_n7723 $abc$24881$new_n9719 +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01001 1 +01100 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9719 $abc$24881$new_n7722 $abc$24881$new_n8206 $abc$24881$new_n8203 $abc$24881$new_n6653 $abc$24881$new_n9720 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names o_mem_addr[3] o_mem_addr[2] $abc$24881$new_n8101 $abc$24881$new_n8155 $abc$24881$new_n8212 $abc$24881$new_n9721 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n6776 o_mem_addr[4] $abc$24881$new_n7998 $abc$24881$new_n9721 $abc$24881$new_n7996 $abc$24881$new_n9722 +00001 1 +00011 1 +00101 1 +00111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7728 $abc$24881$new_n7690 $abc$24881$new_n9722 o_mem_data[31] $abc$24881$new_n6658 $abc$24881$new_n9723 +00011 1 +00111 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8535 $abc$24881$new_n8523 $abc$24881$new_n8533 $abc$24881$new_n9724 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] $abc$24881$new_n8529 $abc$24881$new_n8531 $abc$24881$new_n8515 $abc$24881$new_n8518 $abc$24881$new_n9725 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10110 1 +11010 1 +11110 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9724 $abc$24881$new_n9725 $abc$24881$new_n8515 $abc$24881$new_n9726 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] $abc$24881$new_n9726 $abc$24881$new_n4470 $abc$24881$new_n4468 $abc$24881$new_n9727 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9895 SET_USER_PC.r_upc[2] ipc[2] $0\genblk43.SETDBG.r_dbg_reg[31:0][2] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] regset[21][3] regset[20][3] $abc$24881$new_n9731 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9731 regset[23][3] regset[22][3] $abc$24881$new_n9732 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[0] $abc$24881$new_n9732 regset[29][3] regset[28][3] $abc$24881$new_n9733 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9733 $abc$24881$new_n8568 $abc$24881$new_n8566 $abc$24881$new_n9734 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n8575 regset[1][3] regset[0][3] $abc$24881$new_n9735 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8579 regset[11][3] regset[10][3] $abc$24881$new_n9736 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9736 regset[13][3] regset[12][3] $abc$24881$new_n9737 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9735 $abc$24881$new_n9737 $abc$24881$new_n8576 i_dbg_rreg[2] $abc$24881$new_n9738 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8621 $abc$24881$new_n8627 $abc$24881$new_n8623 $abc$24881$new_n9739 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8615 $abc$24881$new_n8610 $abc$24881$new_n8617 i_dbg_rreg[2] $abc$24881$new_n9740 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11100 1 +.names i_dbg_rreg[4] $abc$24881$new_n9740 $abc$24881$new_n8625 $abc$24881$new_n9739 $abc$24881$new_n9741 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1010 1 +1100 1 +1101 1 +1110 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] $abc$24881$new_n9741 $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$procmux$2451_Y[0] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8673 $abc$24881$new_n8661 $abc$24881$new_n8670 $abc$24881$new_n9743 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n9743 $abc$24881$new_n8654 $abc$24881$new_n8665 $abc$24881$new_n9744 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 $abc$24881$new_n9744 $abc$24881$new_n4520 i_dbg_rreg[4] $abc$24881$new_n9745 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9745 SET_USER_PC.r_upc[6] ipc[6] $0\genblk43.SETDBG.r_dbg_reg[31:0][6] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[7] ipc[7] $abc$24881$new_n9747 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8686 $abc$24881$new_n8683 $abc$24881$new_n8678 $abc$24881$new_n9748 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n9748 $abc$24881$new_n8688 $abc$24881$new_n8680 i_dbg_rreg[3] $abc$24881$new_n9749 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01110 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9747 $abc$24881$new_n8698 $abc$24881$new_n9749 $abc$24881$new_n8525 $0\genblk43.SETDBG.r_dbg_reg[31:0][7] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names i_dbg_rreg[0] i_dbg_rreg[2] regset[29][8] regset[28][8] $abc$24881$new_n9751 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9751 i_dbg_rreg[1] regset[19][8] regset[18][8] $abc$24881$new_n9752 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9752 i_dbg_rreg[2] i_dbg_rreg[1] regset[17][8] regset[16][8] $abc$24881$new_n9753 +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9753 $abc$24881$new_n8713 $abc$24881$new_n8719 $abc$24881$new_n9754 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n8749 regset[17][10] regset[16][10] $abc$24881$new_n9755 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n8753 regset[27][10] regset[26][10] $abc$24881$new_n9756 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9756 regset[29][10] regset[28][10] $abc$24881$new_n9757 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9755 $abc$24881$new_n9757 $abc$24881$new_n8750 i_dbg_rreg[2] $abc$24881$new_n9758 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n8781 i_dbg_rreg[2] $abc$24881$new_n8785 $abc$24881$new_n8783 $abc$24881$new_n9759 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8789 $abc$24881$new_n8525 $abc$24881$new_n8769 $abc$24881$new_n8787 $abc$24881$new_n9759 $abc$24881$new_n9760 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9760 SET_USER_PC.r_upc[11] ipc[11] $0\genblk43.SETDBG.r_dbg_reg[31:0][11] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n8807 $abc$24881$new_n8805 $abc$24881$new_n8803 $abc$24881$new_n9762 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9762 i_dbg_rreg[2] $abc$24881$new_n8801 $abc$24881$new_n8796 $abc$24881$new_n8798 $abc$24881$new_n9763 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8816 $abc$24881$new_n8821 $abc$24881$new_n8818 $abc$24881$new_n9767 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[14] ipc[14] $abc$24881$new_n9770 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8842 $abc$24881$new_n8846 $abc$24881$new_n9771 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9771 i_dbg_rreg[2] $abc$24881$new_n8844 $abc$24881$new_n8840 $abc$24881$new_n9772 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9770 $abc$24881$new_n9772 $abc$24881$new_n8848 $0\genblk43.SETDBG.r_dbg_reg[31:0][14] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[15] ipc[15] $abc$24881$new_n9774 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8870 $abc$24881$new_n8863 $abc$24881$new_n9775 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9775 i_dbg_rreg[2] $abc$24881$new_n8865 $abc$24881$new_n8867 $abc$24881$new_n9776 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9774 $abc$24881$new_n9776 $abc$24881$new_n8871 $0\genblk43.SETDBG.r_dbg_reg[31:0][15] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] SET_USER_PC.r_upc[17] $abc$24881$new_n8909 $abc$24881$new_n8907 $abc$24881$new_n9778 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[3] $abc$24881$new_n9778 $abc$24881$new_n8913 $abc$24881$new_n8911 $abc$24881$new_n9779 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9779 ipc[17] $abc$24881$new_n8915 $0\genblk43.SETDBG.r_dbg_reg[31:0][17] +00000 1 +00001 1 +00010 1 +00011 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8935 $abc$24881$new_n8933 $abc$24881$new_n8929 $abc$24881$new_n9781 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9781 i_dbg_rreg[3] SET_USER_PC.r_upc[18] $abc$24881$new_n8931 $abc$24881$new_n9782 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01010 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y $abc$24881$new_n9782 ipc[18] $abc$24881$new_n8937 $0\genblk43.SETDBG.r_dbg_reg[31:0][18] +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8965 $abc$24881$new_n8969 $abc$24881$new_n8967 $abc$24881$new_n9785 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[2] regset[31][19] regset[30][19] $abc$24881$new_n9787 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9787 i_dbg_rreg[1] regset[17][19] regset[16][19] $abc$24881$new_n9788 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9788 i_dbg_rreg[2] i_dbg_rreg[1] regset[19][19] regset[18][19] $abc$24881$new_n9789 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +10100 1 +10101 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9789 $abc$24881$new_n8954 $abc$24881$new_n8958 $abc$24881$new_n9790 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[4] i_dbg_rreg[2] $abc$24881$new_n8993 $abc$24881$new_n8982 $abc$24881$new_n8990 $abc$24881$new_n9792 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +.names i_dbg_rreg[4] $abc$24881$new_n9797 $abc$24881$new_n8985 $abc$24881$new_n8975 $abc$24881$new_n8977 $abc$24881$new_n9793 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10100 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9792 $abc$24881$new_n9793 $abc$24881$new_n9797 $abc$24881$new_n9794 +00010 1 +00011 1 +00110 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11001 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9794 SET_USER_PC.r_upc[20] ipc[20] $0\genblk43.SETDBG.r_dbg_reg[31:0][20] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[31][20] regset[30][20] $abc$24881$new_n9796 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6930 $abc$24881$new_n9796 i_dbg_rreg[1] regset[29][20] regset[28][20] $abc$24881$new_n9797 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9012 i_dbg_rreg[2] $abc$24881$new_n9001 $abc$24881$new_n9014 $abc$24881$new_n9798 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9922 SET_USER_PC.r_upc[21] ipc[21] $0\genblk43.SETDBG.r_dbg_reg[31:0][21] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9047 i_dbg_rreg[2] $abc$24881$new_n9051 $abc$24881$new_n9045 $abc$24881$new_n9801 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9053 $abc$24881$new_n9801 $abc$24881$new_n9049 $abc$24881$new_n9802 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9802 SET_USER_PC.r_upc[23] ipc[23] $0\genblk43.SETDBG.r_dbg_reg[31:0][23] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9077 i_dbg_rreg[2] $abc$24881$new_n9081 $abc$24881$new_n9075 $abc$24881$new_n9804 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9810 $abc$24881$new_n9079 $abc$24881$new_n9804 $abc$24881$new_n9805 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9805 SET_USER_PC.r_upc[24] ipc[24] $0\genblk43.SETDBG.r_dbg_reg[31:0][24] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[15][24] regset[13][24] regset[12][24] $abc$24881$new_n9807 +00000 1 +00010 1 +00100 1 +00110 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[3] regset[10][24] regset[3][24] regset[2][24] $abc$24881$new_n9808 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names i_dbg_rreg[3] i_dbg_rreg[1] $abc$24881$new_n9808 $abc$24881$new_n9068 $abc$24881$new_n9072 $abc$24881$new_n9809 +00001 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10010 1 +10011 1 +10110 1 +10111 1 +11010 1 +11011 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9809 $abc$24881$new_n9807 $abc$24881$new_n9069 $abc$24881$new_n9810 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[26] ipc[26] $abc$24881$new_n9811 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names $abc$24881$new_n9911 i_dbg_rreg[2] $abc$24881$new_n9112 $abc$24881$new_n9108 $abc$24881$new_n9813 +0000 1 +0010 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9811 $abc$24881$new_n9813 $abc$24881$new_n9818 $0\genblk43.SETDBG.r_dbg_reg[31:0][26] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] $abc$24881$new_n9119 regset[17][26] regset[16][26] $abc$24881$new_n9815 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9123 regset[27][26] regset[26][26] $abc$24881$new_n9816 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[0] $abc$24881$new_n9816 regset[29][26] regset[28][26] $abc$24881$new_n9817 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] $abc$24881$new_n9817 $abc$24881$new_n9815 $abc$24881$new_n9120 $abc$24881$new_n9818 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9141 i_dbg_rreg[2] $abc$24881$new_n9135 $abc$24881$new_n9139 $abc$24881$new_n9819 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9915 SET_USER_PC.r_upc[27] ipc[27] $0\genblk43.SETDBG.r_dbg_reg[31:0][27] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] SET_USER_PC.r_upc[28] ipc[28] $abc$24881$new_n9823 +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +1100 1 +1101 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9155 $abc$24881$new_n9159 $abc$24881$new_n9824 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9824 i_dbg_rreg[2] $abc$24881$new_n9157 $abc$24881$new_n9153 $abc$24881$new_n9825 +0000 1 +0001 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1010 1 +.names i_dbg_rreg[4] $abc$24881$new_n8584 $abc$24881$new_n9823 $abc$24881$new_n9825 $abc$24881$new_n9830 $0\genblk43.SETDBG.r_dbg_reg[31:0][28] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names i_dbg_rreg[0] regset[5][28] regset[4][28] $abc$24881$new_n9827 +000 1 +010 1 +100 1 +101 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] $abc$24881$new_n9827 regset[7][28] regset[6][28] $abc$24881$new_n9828 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[3] i_dbg_rreg[0] $abc$24881$new_n9828 regset[13][28] regset[12][28] $abc$24881$new_n9829 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names i_dbg_rreg[2] i_dbg_rreg[3] $abc$24881$new_n9829 $abc$24881$new_n9167 $abc$24881$new_n9165 $abc$24881$new_n9830 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9178 i_dbg_rreg[2] $abc$24881$new_n9182 $abc$24881$new_n9176 $abc$24881$new_n9831 +00001 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8653 $abc$24881$new_n9184 $abc$24881$new_n9831 $abc$24881$new_n9180 $abc$24881$new_n9832 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9832 SET_USER_PC.r_upc[29] ipc[29] $0\genblk43.SETDBG.r_dbg_reg[31:0][29] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[2] i_dbg_rreg[4] $abc$24881$new_n9917 $abc$24881$new_n9201 $abc$24881$new_n9211 $abc$24881$new_n9835 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9835 $abc$24881$new_n9196 $abc$24881$new_n9206 $abc$24881$new_n9836 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9836 SET_USER_PC.r_upc[30] ipc[30] $0\genblk43.SETDBG.r_dbg_reg[31:0][30] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names r_halted i_halt $abc$24881$new_n9274 $abc$24881$new_n3959 DIVIDE.thedivide.o_busy $abc$24881$new_n9838 +00110 1 +01110 1 +10110 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9838 o_mem_ce i_dbg_we i_mem_busy $abc$24881$procmux$2578_Y +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names i_mem_rdbusy alu_reg[2] instruction_decoder.o_dcdB[2] $abc$24881$new_n9406 instruction_decoder.GEN_OPIPE.r_pipe $abc$24881$new_n9840 +00010 1 +00011 1 +01110 1 +01111 1 +10001 1 +10101 1 +10111 1 +11001 1 +11011 1 +11101 1 +.names i_mem_rdbusy $abc$24881$new_n9412 $abc$24881$new_n4035 $abc$24881$new_n9840 DIVIDE.thedivide.o_busy $abc$24881$new_n9841 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names dcd_Bcc dcd_zI $abc$24881$new_n9841 op_wF GEN_OP_STALL.r_cc_invalid_for_dcd $abc$24881$new_n9842 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +11000 1 +11100 1 +.names $abc$24881$new_n9518 $abc$24881$new_n9844 $abc$24881$new_n4904 dcd_I[31] dcd_I[21] $abc$24881$new_n9843 +00100 1 +00101 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4860 $abc$24881$new_n4839 $abc$24881$new_n9845 dcd_I[19] dcd_I[20] $abc$24881$new_n9844 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4817 $abc$24881$new_n9514 $abc$24881$new_n9846 dcd_I[17] dcd_I[18] $abc$24881$new_n9845 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9508 $abc$24881$new_n9511 $abc$24881$new_n4334 dcd_I[15] dcd_I[16] $abc$24881$new_n9846 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9499 $abc$24881$new_n4660 $abc$24881$new_n4336 dcd_I[11] dcd_I[12] $abc$24881$new_n9847 +00100 1 +01000 1 +01100 1 +01110 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +11000 1 +11001 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[27] SET_USER_PC.r_upc[27] $abc$24881$new_n9848 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9848 dcd_Acc dcd_Apc $abc$24881$new_n9586 $abc$24881$new_n5678 $abc$24881$new_n9849 +00000 1 +00001 1 +01000 1 +01001 1 +01010 1 +01011 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[27] $abc$24881$new_n9849 $abc$24881$new_n3719 $abc$24881$auto$rtlil.cc:2693:MuxGate$23384 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9646 instruction_decoder.o_dcdA[4] $abc$24881$new_n4470 $abc$24881$new_n9648 $abc$24881$new_n6317 $abc$24881$new_n9851 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5595 r_op_Av[1] $abc$24881$new_n9851 $abc$24881$new_n6338 $abc$24881$auto$rtlil.cc:2693:MuxGate$23436 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] $abc$24881$new_n9650 dcd_Acc $abc$24881$new_n6344 $abc$24881$new_n6354 $abc$24881$new_n9853 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9853 dcd_Apc dcd_Acc $abc$24881$new_n5380 $abc$24881$new_n5379 $abc$24881$new_n9854 +00100 1 +00110 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[0] $abc$24881$new_n9854 $abc$24881$new_n3863 $abc$24881$auto$rtlil.cc:2693:MuxGate$23438 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9429 instruction_decoder.o_dcdB[3] $abc$24881$new_n4354 $abc$24881$new_n4347 $abc$24881$new_n9856 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[4] $abc$24881$new_n9856 $abc$24881$new_n4358 $abc$24881$new_n4365 instruction_decoder.o_dcdB[1] $abc$24881$new_n9857 +00100 1 +00101 1 +00110 1 +00111 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n4367 dcd_Bcc $abc$24881$new_n4373 $abc$24881$new_n9857 sleep $abc$24881$new_n9858 +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[31][2] regset[30][2] $abc$24881$new_n9859 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n4069 $abc$24881$new_n9859 instruction_decoder.o_dcdB[2] regset[27][2] regset[26][2] $abc$24881$new_n9860 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][1] regset[28][1] $abc$24881$new_n9861 +0100 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +.names $abc$24881$new_n9861 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][1] regset[24][1] $abc$24881$new_n9862 +00000 1 +00010 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9459 $abc$24881$new_n9457 instruction_decoder.o_dcdB[3] $abc$24881$new_n9862 $abc$24881$new_n9863 +0000 1 +0001 1 +0010 1 +.names instruction_decoder.o_dcdB[0] regset[9][1] regset[8][1] $abc$24881$new_n9864 +001 1 +011 1 +110 1 +111 1 +.names instruction_decoder.o_dcdB[2] instruction_decoder.o_dcdB[0] $abc$24881$new_n9864 regset[13][1] regset[12][1] $abc$24881$new_n9865 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[13][0] regset[12][0] $abc$24881$new_n9866 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9866 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[9][0] regset[8][0] $abc$24881$new_n9867 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9468 $abc$24881$new_n9469 $abc$24881$new_n9472 instruction_decoder.o_dcdB[3] $abc$24881$new_n9867 $abc$24881$new_n9868 +11000 1 +11001 1 +11010 1 +.names instruction_decoder.o_dcdB[0] instruction_decoder.o_dcdB[2] regset[29][0] regset[28][0] $abc$24881$new_n9869 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9869 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[2] regset[25][0] regset[24][0] $abc$24881$new_n9870 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$24881$new_n9474 $abc$24881$new_n9475 $abc$24881$new_n9478 instruction_decoder.o_dcdB[3] $abc$24881$new_n9870 $abc$24881$new_n9871 +11000 1 +11001 1 +11010 1 +.names instruction_decoder.o_dcdB[4] dcd_Bcc $abc$24881$new_n4520 $abc$24881$new_n9479 $abc$24881$new_n9484 $abc$24881$new_n9872 +00000 1 +00001 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n3832 $abc$24881$new_n4368 $abc$24881$new_n9872 $abc$24881$new_n4373 $abc$24881$new_n9486 $abc$24881$new_n9873 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names instruction_decoder.o_dcdB[4] instruction_decoder.o_dcdB[3] $abc$24881$new_n5045 $abc$24881$new_n5061 $abc$24881$new_n5063 $abc$24881$new_n9874 +00001 1 +00011 1 +00101 1 +00111 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9534 instruction_decoder.o_dcdB[1] $abc$24881$new_n5048 $abc$24881$new_n5050 $abc$24881$new_n9875 +0001 1 +0011 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$24881$new_n9875 instruction_decoder.o_dcdB[1] instruction_decoder.o_dcdB[4] $abc$24881$new_n9874 $abc$24881$new_n5052 $abc$24881$new_n9876 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01110 1 +10000 1 +10001 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +.names $abc$24881$new_n4519 $abc$24881$new_n9876 $abc$24881$new_n4368 $abc$24881$new_n3714 $abc$24881$new_n9877 +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[29] SET_USER_PC.r_upc[29] $abc$24881$new_n9878 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9878 $abc$24881$new_n9578 dcd_Apc $abc$24881$new_n5628 $abc$24881$new_n5639 $abc$24881$new_n9879 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[29] $abc$24881$new_n9879 $abc$24881$new_n3708 $abc$24881$auto$rtlil.cc:2693:MuxGate$23380 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] SET_GIE.r_gie dcd_Apc instruction_decoder.o_pc[24] SET_USER_PC.r_upc[24] $abc$24881$new_n9881 +00110 1 +00111 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n9881 $abc$24881$new_n9592 dcd_Apc $abc$24881$new_n5762 $abc$24881$new_n5752 $abc$24881$new_n9882 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n5623 $abc$24881$new_n5596 r_op_Av[24] $abc$24881$new_n9882 $abc$24881$new_n3735 $abc$24881$auto$rtlil.cc:2693:MuxGate$23390 +00000 1 +00010 1 +00100 1 +00110 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[0] instruction_decoder.o_dcdA[2] regset[7][6] regset[6][6] $abc$24881$new_n9884 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9626 $abc$24881$new_n9884 instruction_decoder.o_dcdA[2] regset[2][6] regset[3][6] $abc$24881$new_n9885 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11010 1 +.names $abc$24881$new_n9626 dcd_Acc instruction_decoder.o_dcdA[3] $abc$24881$new_n9885 $abc$24881$new_n6190 $abc$24881$new_n9886 +00001 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names instruction_decoder.o_dcdA[4] dcd_Acc $abc$24881$new_n9886 $abc$24881$new_n4520 $abc$24881$new_n6199 $abc$24881$new_n9887 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11100 1 +11101 1 +.names $abc$24881$new_n7727 o_mem_addr[1] o_mem_data[1] DIVIDE.thedivide.i_signed o_mem_addr[30] $abc$24881$new_n9888 +00001 1 +00101 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n7727 $abc$24881$new_n7722 $abc$24881$new_n9888 $abc$24881$new_n9671 $abc$24881$new_n9672 $abc$24881$new_n9889 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +10001 1 +10011 1 +10101 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n7727 $abc$24881$new_n6656 $abc$24881$new_n9889 $abc$24881$new_n7730 $abc$24881$new_n9674 $abc$24881$auto$rtlil.cc:2582:Mux$3529[1] +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$24881$new_n7869 $abc$24881$new_n7721 $abc$24881$new_n7727 $abc$24881$new_n9683 $abc$24881$new_n9684 $abc$24881$auto$rtlil.cc:2582:Mux$3529[7] +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01110 1 +01111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n8541 $abc$24881$new_n8547 $abc$24881$new_n8543 $abc$24881$new_n9893 +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 $abc$24881$new_n4438 $abc$24881$new_n8545 $abc$24881$new_n9893 $abc$24881$new_n9894 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names i_dbg_rreg[4] $abc$24881$new_n8525 $abc$24881$new_n9894 $abc$24881$new_n4435 $abc$24881$new_n8549 $abc$24881$new_n9895 +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$new_n9762 $abc$24881$new_n8584 $abc$24881$new_n9763 i_dbg_rreg[4] $abc$24881$new_n8794 $abc$24881$new_n9896 +00000 1 +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9896 SET_USER_PC.r_upc[12] ipc[12] $0\genblk43.SETDBG.r_dbg_reg[31:0][12] +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names $abc$24881$new_n8525 i_dbg_rreg[4] GEN_UHALT_PHASE.r_uhalt_phase $abc$24881$new_n9767 $abc$24881$new_n8823 $abc$24881$new_n9898 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$new_n9898 i_dbg_rreg[4] $abc$24881$new_n8726 $abc$24881$new_n8825 GEN_IHALT_PHASE.r_ihalt_phase $abc$24881$new_n9899 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +.names $abc$24881$new_n9899 i_dbg_rreg[4] $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y SET_USER_PC.r_upc[13] ipc[13] $0\genblk43.SETDBG.r_dbg_reg[31:0][13] +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[4] regset[29][19] regset[28][19] $abc$24881$new_n9901 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n8516 $abc$24881$new_n9901 i_dbg_rreg[4] regset[13][19] regset[12][19] $abc$24881$new_n9902 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n9902 i_dbg_rreg[4] $abc$24881$new_n9790 $abc$24881$new_n9785 $abc$24881$new_n8963 $abc$24881$new_n9903 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$24881$eq$./benchmark/zipcore.v:3393$815_Y i_dbg_rreg[4] $abc$24881$new_n9903 SET_USER_PC.r_upc[19] ipc[19] $0\genblk43.SETDBG.r_dbg_reg[31:0][19] +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[19][21] regset[18][21] $abc$24881$new_n9905 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9905 i_dbg_rreg[3] i_dbg_rreg[1] regset[16][21] regset[17][21] $abc$24881$new_n9906 +00000 1 +00001 1 +00100 1 +00101 1 +00110 1 +00111 1 +10000 1 +10010 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9006 $abc$24881$new_n9906 $abc$24881$new_n9009 $abc$24881$new_n9907 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[1] i_dbg_rreg[0] regset[7][26] regset[5][26] $abc$24881$new_n9909 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9909 i_dbg_rreg[3] i_dbg_rreg[0] regset[6][26] regset[4][26] $abc$24881$new_n9910 +00001 1 +00011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9910 i_dbg_rreg[2] regset[13][26] regset[12][26] $abc$24881$new_n9911 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[0] i_dbg_rreg[1] regset[31][27] regset[30][27] $abc$24881$new_n9912 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names i_dbg_rreg[3] $abc$24881$new_n9912 i_dbg_rreg[1] regset[29][27] regset[28][27] $abc$24881$new_n9913 +10001 1 +10011 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[2] $abc$24881$new_n9130 $abc$24881$new_n9913 $abc$24881$new_n9144 $abc$24881$new_n9914 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10110 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[3] i_dbg_rreg[4] $abc$24881$new_n9819 $abc$24881$new_n9129 $abc$24881$new_n9914 $abc$24881$new_n9915 +00011 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01111 1 +10110 1 +10111 1 +11001 1 +11011 1 +11101 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] i_dbg_rreg[0] regset[29][30] regset[13][30] $abc$24881$new_n9916 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9916 i_dbg_rreg[1] i_dbg_rreg[0] regset[28][30] regset[12][30] $abc$24881$new_n9917 +00001 1 +00011 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names i_dbg_rreg[0] i_dbg_rreg[4] regset[31][21] regset[30][21] $abc$24881$new_n9918 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n9918 i_dbg_rreg[1] regset[15][21] regset[14][21] $abc$24881$new_n9919 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1110 1 +1111 1 +.names $abc$24881$new_n6930 $abc$24881$new_n9919 i_dbg_rreg[1] regset[13][21] regset[12][21] $abc$24881$new_n9920 +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10010 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +.names $abc$24881$new_n6930 i_dbg_rreg[1] $abc$24881$new_n9907 $abc$24881$new_n9918 $abc$24881$new_n9018 $abc$24881$new_n9921 +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10101 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11110 1 +11111 1 +.names i_dbg_rreg[4] $abc$24881$new_n9921 $abc$24881$new_n9798 $abc$24881$new_n9920 $abc$24881$new_n9922 +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +1111 1 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2451_Y[0] Q=o_dbg_reg[0] R=$abc$24881$eq$./benchmark/zipcore.v:3393$815_Y +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[4] +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[5] +.subckt dff C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[6] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[4] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[0] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[5] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[1] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$$auto$proc_rom.cc:150:do_switch$1988$rdreg[0]$d[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[2] R=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23656 Q=GEN_UHALT_PHASE.r_uhalt_phase R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[0] Q=regset[4][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[1] Q=regset[4][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[2] Q=regset[4][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[3] Q=regset[4][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[4] Q=regset[4][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[5] Q=regset[4][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[6] Q=regset[4][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[7] Q=regset[4][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[8] Q=regset[4][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[9] Q=regset[4][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[10] Q=regset[4][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[11] Q=regset[4][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[12] Q=regset[4][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[13] Q=regset[4][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[14] Q=regset[4][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[15] Q=regset[4][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[16] Q=regset[4][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[17] Q=regset[4][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[18] Q=regset[4][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[19] Q=regset[4][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[20] Q=regset[4][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[21] Q=regset[4][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[22] Q=regset[4][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[23] Q=regset[4][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[24] Q=regset[4][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[25] Q=regset[4][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[26] Q=regset[4][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[27] Q=regset[4][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[28] Q=regset[4][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[29] Q=regset[4][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[30] Q=regset[4][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[4][0][0]$y$4338[31] Q=regset[4][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[0] Q=regset[11][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[1] Q=regset[11][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[2] Q=regset[11][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[3] Q=regset[11][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[4] Q=regset[11][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[5] Q=regset[11][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[6] Q=regset[11][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[7] Q=regset[11][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[8] Q=regset[11][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[9] Q=regset[11][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[10] Q=regset[11][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[11] Q=regset[11][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[12] Q=regset[11][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[13] Q=regset[11][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[14] Q=regset[11][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[15] Q=regset[11][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[16] Q=regset[11][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[17] Q=regset[11][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[18] Q=regset[11][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[19] Q=regset[11][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[20] Q=regset[11][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[21] Q=regset[11][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[22] Q=regset[11][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[23] Q=regset[11][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[24] Q=regset[11][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[25] Q=regset[11][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[26] Q=regset[11][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[27] Q=regset[11][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[28] Q=regset[11][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[29] Q=regset[11][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[30] Q=regset[11][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[11][0][0]$y$4386[31] Q=regset[11][31] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][1] Q=o_dbg_reg[1] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][2] Q=o_dbg_reg[2] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][3] Q=o_dbg_reg[3] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][4] Q=o_dbg_reg[4] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][5] Q=o_dbg_reg[5] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][6] Q=o_dbg_reg[6] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][7] Q=o_dbg_reg[7] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][8] Q=o_dbg_reg[8] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][9] Q=o_dbg_reg[9] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][10] Q=o_dbg_reg[10] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][11] Q=o_dbg_reg[11] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][12] Q=o_dbg_reg[12] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][13] Q=o_dbg_reg[13] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][14] Q=o_dbg_reg[14] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][15] Q=o_dbg_reg[15] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][16] Q=o_dbg_reg[16] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][17] Q=o_dbg_reg[17] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][18] Q=o_dbg_reg[18] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][19] Q=o_dbg_reg[19] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][20] Q=o_dbg_reg[20] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][21] Q=o_dbg_reg[21] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][22] Q=o_dbg_reg[22] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][23] Q=o_dbg_reg[23] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][24] Q=o_dbg_reg[24] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][25] Q=o_dbg_reg[25] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][26] Q=o_dbg_reg[26] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][27] Q=o_dbg_reg[27] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][28] Q=o_dbg_reg[28] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][29] Q=o_dbg_reg[29] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][30] Q=o_dbg_reg[30] +.subckt dff C=i_clk D=$0\genblk43.SETDBG.r_dbg_reg[31:0][31] Q=o_dbg_reg[31] +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1613$573_Y Q=alu_wF R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3485 +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[0] Q=regset[5][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[1] Q=regset[5][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[2] Q=regset[5][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[3] Q=regset[5][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[4] Q=regset[5][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[5] Q=regset[5][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[6] Q=regset[5][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[7] Q=regset[5][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[8] Q=regset[5][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[9] Q=regset[5][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[10] Q=regset[5][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[11] Q=regset[5][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[12] Q=regset[5][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[13] Q=regset[5][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[14] Q=regset[5][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[15] Q=regset[5][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[16] Q=regset[5][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[17] Q=regset[5][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[18] Q=regset[5][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[19] Q=regset[5][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[20] Q=regset[5][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[21] Q=regset[5][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[22] Q=regset[5][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[23] Q=regset[5][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[24] Q=regset[5][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[25] Q=regset[5][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[26] Q=regset[5][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[27] Q=regset[5][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[28] Q=regset[5][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[29] Q=regset[5][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[30] Q=regset[5][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[5][0][0]$y$4344[31] Q=regset[5][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[0] Q=regset[10][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[1] Q=regset[10][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[2] Q=regset[10][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[3] Q=regset[10][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[4] Q=regset[10][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[5] Q=regset[10][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[6] Q=regset[10][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[7] Q=regset[10][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[8] Q=regset[10][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[9] Q=regset[10][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[10] Q=regset[10][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[11] Q=regset[10][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[12] Q=regset[10][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[13] Q=regset[10][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[14] Q=regset[10][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[15] Q=regset[10][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[16] Q=regset[10][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[17] Q=regset[10][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[18] Q=regset[10][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[19] Q=regset[10][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[20] Q=regset[10][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[21] Q=regset[10][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[22] Q=regset[10][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[23] Q=regset[10][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[24] Q=regset[10][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[25] Q=regset[10][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[26] Q=regset[10][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[27] Q=regset[10][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[28] Q=regset[10][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[29] Q=regset[10][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[30] Q=regset[10][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[10][0][0]$y$4380[31] Q=regset[10][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[0] Q=regset[27][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[1] Q=regset[27][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[2] Q=regset[27][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[3] Q=regset[27][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[4] Q=regset[27][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[5] Q=regset[27][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[6] Q=regset[27][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[7] Q=regset[27][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[8] Q=regset[27][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[9] Q=regset[27][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[10] Q=regset[27][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[11] Q=regset[27][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[12] Q=regset[27][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[13] Q=regset[27][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[14] Q=regset[27][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[15] Q=regset[27][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[16] Q=regset[27][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[17] Q=regset[27][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[18] Q=regset[27][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[19] Q=regset[27][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[20] Q=regset[27][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[21] Q=regset[27][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[22] Q=regset[27][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[23] Q=regset[27][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[24] Q=regset[27][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[25] Q=regset[27][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[26] Q=regset[27][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[27] Q=regset[27][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[28] Q=regset[27][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[29] Q=regset[27][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[30] Q=regset[27][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[27][0][0]$y$4496[31] Q=regset[27][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23314 Q=GEN_ALU_PC.r_alu_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23312 Q=GEN_ALU_PC.r_alu_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23310 Q=GEN_ALU_PC.r_alu_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23308 Q=GEN_ALU_PC.r_alu_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23306 Q=GEN_ALU_PC.r_alu_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23304 Q=GEN_ALU_PC.r_alu_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23302 Q=GEN_ALU_PC.r_alu_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23300 Q=GEN_ALU_PC.r_alu_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23298 Q=GEN_ALU_PC.r_alu_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23296 Q=GEN_ALU_PC.r_alu_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23294 Q=GEN_ALU_PC.r_alu_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23292 Q=GEN_ALU_PC.r_alu_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23290 Q=GEN_ALU_PC.r_alu_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23288 Q=GEN_ALU_PC.r_alu_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23286 Q=GEN_ALU_PC.r_alu_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23284 Q=GEN_ALU_PC.r_alu_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23282 Q=GEN_ALU_PC.r_alu_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23280 Q=GEN_ALU_PC.r_alu_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23278 Q=GEN_ALU_PC.r_alu_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23276 Q=GEN_ALU_PC.r_alu_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23274 Q=GEN_ALU_PC.r_alu_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23272 Q=GEN_ALU_PC.r_alu_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23270 Q=GEN_ALU_PC.r_alu_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23268 Q=GEN_ALU_PC.r_alu_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23266 Q=GEN_ALU_PC.r_alu_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23264 Q=GEN_ALU_PC.r_alu_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23262 Q=GEN_ALU_PC.r_alu_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23260 Q=GEN_ALU_PC.r_alu_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23258 Q=GEN_ALU_PC.r_alu_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23740 Q=GEN_ALU_PC.r_alu_pc[31] +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[0] Q=alu_result[0] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[1] Q=alu_result[1] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[2] Q=alu_result[2] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[3] Q=alu_result[3] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[4] Q=alu_result[4] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[5] Q=alu_result[5] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[6] Q=alu_result[6] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[7] Q=alu_result[7] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[8] Q=alu_result[8] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[9] Q=alu_result[9] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[10] Q=alu_result[10] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[11] Q=alu_result[11] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[12] Q=alu_result[12] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[13] Q=alu_result[13] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[14] Q=alu_result[14] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[15] Q=alu_result[15] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[16] Q=alu_result[16] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[17] Q=alu_result[17] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[18] Q=alu_result[18] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[19] Q=alu_result[19] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[20] Q=alu_result[20] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[21] Q=alu_result[21] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[22] Q=alu_result[22] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[23] Q=alu_result[23] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[24] Q=alu_result[24] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[25] Q=alu_result[25] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[26] Q=alu_result[26] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[27] Q=alu_result[27] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[28] Q=alu_result[28] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[29] Q=alu_result[29] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[30] Q=alu_result[30] RN=alu_ce +.subckt sdffrn C=i_clk D=$abc$24881$auto$rtlil.cc:2582:Mux$3529[31] Q=doalu.n RN=alu_ce +.subckt sdffr C=i_clk D=$abc$24881$memory$auto$proc_rom.cc:150:do_switch$1988$rdmux[0][1][0]$b$3899[6] Q=$abc$24881$auto$proc_rom.cc:149:do_switch$1987[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$4528 +.subckt sdffs C=i_clk D=$abc$24881$procmux$2428_Y Q=r_halted S=i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2463_Y Q=o_clear_dcache R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23658 Q=GEN_IHALT_PHASE.r_ihalt_phase R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23660 Q=DIVERR.USER_DIVERR.r_udiv_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23662 Q=DIVERR.r_idiv_err_flag R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23664 Q=SET_USER_BUSERR.r_ubus_err_flag R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23666 Q=SET_USER_ILLEGAL_INSN.r_ill_err_u R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23668 Q=SET_TRAP_N_UBREAK.r_ubreak R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23670 Q=SET_TRAP_N_UBREAK.r_trap R=$abc$24881$logic_or$./benchmark/zipcore.v:2870$740_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23672 Q=SET_GIE.r_gie R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23674 Q=GEN_PENDING_INTERRUPT.r_pending_interrupt R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3429 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23676 Q=GEN_PENDING_INTERRUPT.r_user_stepped R=$abc$24881$logic_or$./benchmark/zipcore.v:2741$689_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23678 Q=sleep R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3432 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2578_Y Q=GEN_CLOCK_GATE.r_clken R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23680 Q=GEN_PENDING_BREAK.r_break_pending R=$abc$24881$logic_or$./benchmark/zipcore.v:2501$630_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23256 Q=BUSLOCK.r_bus_lock[0] R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23682 Q=BUSLOCK.r_bus_lock[1] R=new_pc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23254 Q=dcd_I[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23252 Q=dcd_I[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23250 Q=dcd_I[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23248 Q=dcd_I[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23246 Q=dcd_I[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23244 Q=dcd_I[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23242 Q=dcd_I[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23240 Q=dcd_I[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23238 Q=dcd_I[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23236 Q=dcd_I[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23234 Q=dcd_I[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23232 Q=dcd_I[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23230 Q=dcd_I[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23228 Q=dcd_I[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23226 Q=dcd_I[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23224 Q=dcd_I[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23222 Q=dcd_I[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23220 Q=dcd_I[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23218 Q=dcd_I[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23216 Q=dcd_I[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23214 Q=dcd_I[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23212 Q=dcd_I[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23584 Q=dcd_I[31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23684 Q=BUSLOCK.r_prelock_stall R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23686 Q=GEN_ALU_PHASE.r_alu_phase R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23210 Q=o_mem_lock_pc[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23208 Q=o_mem_lock_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23206 Q=o_mem_lock_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23204 Q=o_mem_lock_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23202 Q=o_mem_lock_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23200 Q=o_mem_lock_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23198 Q=o_mem_lock_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23196 Q=o_mem_lock_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23194 Q=o_mem_lock_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23192 Q=o_mem_lock_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23190 Q=o_mem_lock_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23188 Q=o_mem_lock_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23186 Q=o_mem_lock_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23184 Q=o_mem_lock_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23182 Q=o_mem_lock_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23180 Q=o_mem_lock_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23178 Q=o_mem_lock_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23176 Q=o_mem_lock_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23174 Q=o_mem_lock_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23172 Q=o_mem_lock_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23170 Q=o_mem_lock_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23168 Q=o_mem_lock_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23166 Q=o_mem_lock_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23164 Q=o_mem_lock_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23162 Q=o_mem_lock_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23160 Q=o_mem_lock_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23158 Q=o_mem_lock_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23156 Q=o_mem_lock_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23154 Q=o_mem_lock_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23152 Q=o_mem_lock_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23742 Q=o_mem_lock_pc[31] +.subckt sdffr C=i_clk D=op_illegal Q=SET_ALU_ILLEGAL.r_alu_illegal R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3420 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23688 Q=OPT_CIS_OP_PHASE.r_op_phase R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2659_Y Q=alu_wR R=i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23150 Q=DIVIDE.thedivide.i_signed +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23146 Q=o_mem_op[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23142 Q=o_mem_op[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23576 Q=FWD_OPERATION.r_op_opn[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23138 Q=alu_reg[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23136 Q=alu_reg[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23134 Q=alu_reg[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23132 Q=alu_reg[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23578 Q=alu_reg[4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[0] Q=regset[25][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[1] Q=regset[25][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[2] Q=regset[25][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[3] Q=regset[25][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[4] Q=regset[25][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[5] Q=regset[25][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[6] Q=regset[25][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[7] Q=regset[25][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[8] Q=regset[25][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[9] Q=regset[25][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[10] Q=regset[25][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[11] Q=regset[25][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[12] Q=regset[25][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[13] Q=regset[25][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[14] Q=regset[25][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[15] Q=regset[25][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[16] Q=regset[25][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[17] Q=regset[25][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[18] Q=regset[25][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[19] Q=regset[25][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[20] Q=regset[25][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[21] Q=regset[25][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[22] Q=regset[25][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[23] Q=regset[25][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[24] Q=regset[25][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[25] Q=regset[25][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[26] Q=regset[25][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[27] Q=regset[25][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[28] Q=regset[25][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[29] Q=regset[25][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[30] Q=regset[25][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[25][0][0]$y$4484[31] Q=regset[25][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23690 Q=GEN_OPLOCK.r_op_lock R=new_pc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23572 Q=GEN_OP_WR.r_op_wR +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23728 Q=SET_OP_PC.r_op_pc[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23130 Q=o_mem_reg[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23128 Q=o_mem_reg[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23126 Q=o_mem_reg[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23124 Q=o_mem_reg[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23570 Q=o_mem_reg[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23122 Q=OP_REG_ADVANEC.r_op_Bid[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23120 Q=OP_REG_ADVANEC.r_op_Bid[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23118 Q=OP_REG_ADVANEC.r_op_Bid[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23116 Q=OP_REG_ADVANEC.r_op_Bid[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23568 Q=OP_REG_ADVANEC.r_op_Bid[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23566 Q=OP_REG_ADVANEC.r_op_rA +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23692 Q=GEN_OP_PIPE.r_op_pipe R=$abc$24881$logic_or$./benchmark/zipcore.v:728$452_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23694 Q=GEN_OP_STALL.r_pending_sreg_write R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23114 Q=ipc[2] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23112 Q=ipc[3] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23110 Q=ipc[4] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23108 Q=ipc[5] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23106 Q=ipc[6] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23104 Q=ipc[7] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23102 Q=ipc[8] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23100 Q=ipc[9] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23098 Q=ipc[10] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23096 Q=ipc[11] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23094 Q=ipc[12] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23092 Q=ipc[13] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23090 Q=ipc[14] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23088 Q=ipc[15] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23086 Q=ipc[16] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23084 Q=ipc[17] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23082 Q=ipc[18] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23080 Q=ipc[19] R=i_reset +.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23078 Q=ipc[20] S=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23076 Q=ipc[21] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23074 Q=ipc[22] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23072 Q=ipc[23] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23070 Q=ipc[24] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23068 Q=ipc[25] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23066 Q=ipc[26] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23064 Q=ipc[27] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23062 Q=ipc[28] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23060 Q=ipc[29] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23058 Q=ipc[30] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23696 Q=ipc[31] R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$procmux$2728_Y Q=GEN_OP_STALL.r_cc_invalid_for_dcd R=new_pc +.subckt dff C=i_clk D=sleep Q=o_dbg_cc[0] +.subckt dff C=i_clk D=SET_GIE.r_gie Q=o_dbg_cc[1] +.subckt dff C=i_clk D=i_bus_err Q=o_dbg_cc[2] +.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=r_dbg_stall S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3407 +.subckt sdffs C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:3323$377_Y Q=new_pc S=$abc$24881$auto$opt_dff.cc:253:combine_resets$3404 +.subckt sdffr C=i_clk D=$abc$24881$procmux$2755_Y Q=o_clear_icache R=i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23564 Q=OP_REG_ADVANEC.r_op_rB +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:2585$648_Y Q=last_write_to_cc R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23698 Q=ibus_err_flag R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23700 Q=ill_err_i R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23702 Q=user_step R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23704 Q=break_en R=i_reset +.subckt dff C=i_clk D=$0\iflags[3:0][0] Q=iflags[0] +.subckt dff C=i_clk D=$0\iflags[3:0][1] Q=iflags[1] +.subckt dff C=i_clk D=$0\iflags[3:0][2] Q=iflags[2] +.subckt dff C=i_clk D=$0\iflags[3:0][3] Q=iflags[3] +.subckt dff C=i_clk D=$0\flags[3:0][0] Q=flags[0] +.subckt dff C=i_clk D=$0\flags[3:0][1] Q=flags[1] +.subckt dff C=i_clk D=$0\flags[3:0][2] Q=flags[2] +.subckt dff C=i_clk D=$0\flags[3:0][3] Q=flags[3] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23706 Q=r_alu_pc_valid R=new_pc +.subckt sdffr C=i_clk D=mem_ce Q=mem_pc_valid R=i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23056 Q=wr_index[0] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23708 Q=wr_index[1] R=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y +.subckt dff C=i_clk D=i_dbg_data[0] Q=dbg_val[0] +.subckt dff C=i_clk D=i_dbg_data[1] Q=dbg_val[1] +.subckt dff C=i_clk D=i_dbg_data[2] Q=dbg_val[2] +.subckt dff C=i_clk D=i_dbg_data[3] Q=dbg_val[3] +.subckt dff C=i_clk D=i_dbg_data[4] Q=dbg_val[4] +.subckt dff C=i_clk D=i_dbg_data[5] Q=dbg_val[5] +.subckt dff C=i_clk D=i_dbg_data[6] Q=dbg_val[6] +.subckt dff C=i_clk D=i_dbg_data[7] Q=dbg_val[7] +.subckt dff C=i_clk D=i_dbg_data[8] Q=dbg_val[8] +.subckt dff C=i_clk D=i_dbg_data[9] Q=dbg_val[9] +.subckt dff C=i_clk D=i_dbg_data[10] Q=dbg_val[10] +.subckt dff C=i_clk D=i_dbg_data[11] Q=dbg_val[11] +.subckt dff C=i_clk D=i_dbg_data[12] Q=dbg_val[12] +.subckt dff C=i_clk D=i_dbg_data[13] Q=dbg_val[13] +.subckt dff C=i_clk D=i_dbg_data[14] Q=dbg_val[14] +.subckt dff C=i_clk D=i_dbg_data[15] Q=dbg_val[15] +.subckt dff C=i_clk D=i_dbg_data[16] Q=dbg_val[16] +.subckt dff C=i_clk D=i_dbg_data[17] Q=dbg_val[17] +.subckt dff C=i_clk D=i_dbg_data[18] Q=dbg_val[18] +.subckt dff C=i_clk D=i_dbg_data[19] Q=dbg_val[19] +.subckt dff C=i_clk D=i_dbg_data[20] Q=dbg_val[20] +.subckt dff C=i_clk D=i_dbg_data[21] Q=dbg_val[21] +.subckt dff C=i_clk D=i_dbg_data[22] Q=dbg_val[22] +.subckt dff C=i_clk D=i_dbg_data[23] Q=dbg_val[23] +.subckt dff C=i_clk D=i_dbg_data[24] Q=dbg_val[24] +.subckt dff C=i_clk D=i_dbg_data[25] Q=dbg_val[25] +.subckt dff C=i_clk D=i_dbg_data[26] Q=dbg_val[26] +.subckt dff C=i_clk D=i_dbg_data[27] Q=dbg_val[27] +.subckt dff C=i_clk D=i_dbg_data[28] Q=dbg_val[28] +.subckt dff C=i_clk D=i_dbg_data[29] Q=dbg_val[29] +.subckt dff C=i_clk D=i_dbg_data[30] Q=dbg_val[30] +.subckt dff C=i_clk D=i_dbg_data[31] Q=dbg_val[31] +.subckt sdffr C=i_clk D=$abc$24881$procmux$3022_Y Q=dbg_clear_pipe R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3389 +.subckt sdffr C=i_clk D=$abc$24881$logic_and$./benchmark/zipcore.v:1618$577_Y Q=dbgv R=$abc$24881$logic_or$./benchmark/zipcore.v:1716$199_Y +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23054 Q=SET_OP_PC.r_op_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23052 Q=SET_OP_PC.r_op_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23050 Q=SET_OP_PC.r_op_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23048 Q=SET_OP_PC.r_op_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23046 Q=SET_OP_PC.r_op_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23044 Q=SET_OP_PC.r_op_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23042 Q=SET_OP_PC.r_op_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23040 Q=SET_OP_PC.r_op_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23038 Q=SET_OP_PC.r_op_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23036 Q=SET_OP_PC.r_op_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23034 Q=SET_OP_PC.r_op_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23032 Q=SET_OP_PC.r_op_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23030 Q=SET_OP_PC.r_op_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23028 Q=SET_OP_PC.r_op_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23026 Q=SET_OP_PC.r_op_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23024 Q=SET_OP_PC.r_op_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23022 Q=SET_OP_PC.r_op_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23020 Q=SET_OP_PC.r_op_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23018 Q=SET_OP_PC.r_op_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23016 Q=SET_OP_PC.r_op_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23014 Q=SET_OP_PC.r_op_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23012 Q=SET_OP_PC.r_op_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23010 Q=SET_OP_PC.r_op_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23008 Q=SET_OP_PC.r_op_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23006 Q=SET_OP_PC.r_op_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23004 Q=SET_OP_PC.r_op_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23002 Q=SET_OP_PC.r_op_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23000 Q=SET_OP_PC.r_op_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22998 Q=SET_OP_PC.r_op_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23738 Q=SET_OP_PC.r_op_pc[31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23710 Q=op_illegal R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23712 Q=r_op_break R=new_pc +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23714 Q=op_valid R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23716 Q=op_valid_mem R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23718 Q=op_valid_alu R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23720 Q=op_valid_div R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23562 Q=op_wF +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22996 Q=r_op_F[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22994 Q=r_op_F[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22992 Q=r_op_F[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22990 Q=r_op_F[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22988 Q=r_op_F[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22986 Q=r_op_F[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23560 Q=r_op_F[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22984 Q=r_op_Bv[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22982 Q=r_op_Bv[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22980 Q=r_op_Bv[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22978 Q=r_op_Bv[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22976 Q=r_op_Bv[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22974 Q=r_op_Bv[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22972 Q=r_op_Bv[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22970 Q=r_op_Bv[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22968 Q=r_op_Bv[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22966 Q=r_op_Bv[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22964 Q=r_op_Bv[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22962 Q=r_op_Bv[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22960 Q=r_op_Bv[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22958 Q=r_op_Bv[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22956 Q=r_op_Bv[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22954 Q=r_op_Bv[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22952 Q=r_op_Bv[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22950 Q=r_op_Bv[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22948 Q=r_op_Bv[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22946 Q=r_op_Bv[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22944 Q=r_op_Bv[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22942 Q=r_op_Bv[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22940 Q=r_op_Bv[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22938 Q=r_op_Bv[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22936 Q=r_op_Bv[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22934 Q=r_op_Bv[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22932 Q=r_op_Bv[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22930 Q=r_op_Bv[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22928 Q=r_op_Bv[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22926 Q=r_op_Bv[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22924 Q=r_op_Bv[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23558 Q=r_op_Bv[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[0] Q=regset[23][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[1] Q=regset[23][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[2] Q=regset[23][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[3] Q=regset[23][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[4] Q=regset[23][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[5] Q=regset[23][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[6] Q=regset[23][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[7] Q=regset[23][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[8] Q=regset[23][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[9] Q=regset[23][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[10] Q=regset[23][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[11] Q=regset[23][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[12] Q=regset[23][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[13] Q=regset[23][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[14] Q=regset[23][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[15] Q=regset[23][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[16] Q=regset[23][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[17] Q=regset[23][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[18] Q=regset[23][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[19] Q=regset[23][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[20] Q=regset[23][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[21] Q=regset[23][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[22] Q=regset[23][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[23] Q=regset[23][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[24] Q=regset[23][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[25] Q=regset[23][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[26] Q=regset[23][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[27] Q=regset[23][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[28] Q=regset[23][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[29] Q=regset[23][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[30] Q=regset[23][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[23][0][0]$y$4468[31] Q=regset[23][31] +.subckt dff C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$0\r_dividend[62:0][31] Q=DIVIDE.thedivide.r_dividend[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23618 Q=doalu.set_ovfl +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23636 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_ljmp R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23610 Q=dcd_zI +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23608 Q=dcd_F[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22922 Q=dcd_opn[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22918 Q=dcd_opn[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22914 Q=dcd_opn[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23604 Q=dcd_opn[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23606 Q=dcd_wF +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23592 Q=dcd_wR +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23588 Q=dcd_rB +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23600 Q=dcd_ALU +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23598 Q=dcd_M +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22910 Q=instruction_decoder.r_nxt_half[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22908 Q=instruction_decoder.r_nxt_half[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22906 Q=instruction_decoder.r_nxt_half[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22904 Q=instruction_decoder.r_nxt_half[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22902 Q=instruction_decoder.r_nxt_half[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22900 Q=instruction_decoder.r_nxt_half[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22898 Q=instruction_decoder.r_nxt_half[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22896 Q=instruction_decoder.r_nxt_half[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22894 Q=instruction_decoder.r_nxt_half[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22892 Q=instruction_decoder.r_nxt_half[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22890 Q=instruction_decoder.r_nxt_half[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22888 Q=instruction_decoder.r_nxt_half[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22886 Q=instruction_decoder.r_nxt_half[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22884 Q=instruction_decoder.r_nxt_half[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23586 Q=instruction_decoder.r_nxt_half[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23590 Q=dcd_rA +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23582 Q=instruction_decoder.o_pc[1] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23640 Q=instruction_decoder.o_illegal R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22882 Q=instruction_decoder.o_dcdA[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22880 Q=instruction_decoder.o_dcdA[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22878 Q=instruction_decoder.o_dcdA[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22876 Q=instruction_decoder.o_dcdA[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22874 Q=instruction_decoder.o_dcdA[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22872 Q=dcd_Apc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23614 Q=dcd_Acc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22870 Q=instruction_decoder.o_dcdB[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22868 Q=instruction_decoder.o_dcdB[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22866 Q=instruction_decoder.o_dcdB[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22864 Q=instruction_decoder.o_dcdB[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22862 Q=instruction_decoder.o_dcdB[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22860 Q=dcd_Bpc +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23612 Q=dcd_Bcc +.subckt sdffr C=i_clk D=$abc$24881$flatten\instruction_decoder.$procmux$2071_Y Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch_stb R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3474 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23638 Q=instruction_decoder.GEN_CIS_PHASE.r_phase R=$abc$24881$flatten\instruction_decoder.$logic_or$./benchmark/idecode.v:410$1888_Y +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23616 Q=dcd_break +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[0] Q=regset[28][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[1] Q=regset[28][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[2] Q=regset[28][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[3] Q=regset[28][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[4] Q=regset[28][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[5] Q=regset[28][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[6] Q=regset[28][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[7] Q=regset[28][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[8] Q=regset[28][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[9] Q=regset[28][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[10] Q=regset[28][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[11] Q=regset[28][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[12] Q=regset[28][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[13] Q=regset[28][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[14] Q=regset[28][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[15] Q=regset[28][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[16] Q=regset[28][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[17] Q=regset[28][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[18] Q=regset[28][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[19] Q=regset[28][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[20] Q=regset[28][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[21] Q=regset[28][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[22] Q=regset[28][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[23] Q=regset[28][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[24] Q=regset[28][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[25] Q=regset[28][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[26] Q=regset[28][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[27] Q=regset[28][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[28] Q=regset[28][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[29] Q=regset[28][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[30] Q=regset[28][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[28][0][0]$y$4504[31] Q=regset[28][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23630 Q=instruction_decoder.GEN_OPIPE.r_pipe R=instruction_decoder.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23632 Q=instruction_decoder.GEN_OPIPE.r_insn_is_pipeable R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3478 +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23634 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_early_branch R=instruction_decoder.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23596 Q=instruction_decoder.o_DV +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23594 Q=instruction_decoder.o_lock +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22858 Q=pf_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22856 Q=pf_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22854 Q=pf_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22852 Q=pf_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22850 Q=pf_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22848 Q=pf_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22846 Q=pf_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22844 Q=pf_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22842 Q=pf_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22840 Q=pf_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22838 Q=pf_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22836 Q=pf_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22834 Q=pf_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22832 Q=pf_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22830 Q=pf_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22828 Q=pf_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22826 Q=pf_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22824 Q=pf_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22822 Q=pf_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22820 Q=pf_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22818 Q=pf_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22816 Q=pf_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22814 Q=pf_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22812 Q=pf_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22810 Q=pf_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22808 Q=pf_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22806 Q=pf_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22804 Q=pf_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22802 Q=pf_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23736 Q=pf_pc[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23626 Q=DIVIDE.thedivide.zero_divisor +.subckt sdffr C=i_clk D=alu_ce Q=doalu.o_valid R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22800 Q=SET_USER_PC.r_upc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22798 Q=SET_USER_PC.r_upc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22796 Q=SET_USER_PC.r_upc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22794 Q=SET_USER_PC.r_upc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22792 Q=SET_USER_PC.r_upc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22790 Q=SET_USER_PC.r_upc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22788 Q=SET_USER_PC.r_upc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22786 Q=SET_USER_PC.r_upc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22784 Q=SET_USER_PC.r_upc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22782 Q=SET_USER_PC.r_upc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22780 Q=SET_USER_PC.r_upc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22778 Q=SET_USER_PC.r_upc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22776 Q=SET_USER_PC.r_upc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22774 Q=SET_USER_PC.r_upc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22772 Q=SET_USER_PC.r_upc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22770 Q=SET_USER_PC.r_upc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22768 Q=SET_USER_PC.r_upc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22766 Q=SET_USER_PC.r_upc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22764 Q=SET_USER_PC.r_upc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22762 Q=SET_USER_PC.r_upc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22760 Q=SET_USER_PC.r_upc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22758 Q=SET_USER_PC.r_upc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22756 Q=SET_USER_PC.r_upc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22754 Q=SET_USER_PC.r_upc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22752 Q=SET_USER_PC.r_upc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22750 Q=SET_USER_PC.r_upc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22748 Q=SET_USER_PC.r_upc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22746 Q=SET_USER_PC.r_upc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22744 Q=SET_USER_PC.r_upc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23654 Q=SET_USER_PC.r_upc[31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23622 Q=doalu.c +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23620 Q=doalu.keep_sgn_on_ovfl +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23624 Q=doalu.pre_sign +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22742 Q=DIVIDE.thedivide.r_dividend[33] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22738 Q=DIVIDE.thedivide.r_dividend[34] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22734 Q=DIVIDE.thedivide.r_dividend[35] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22730 Q=DIVIDE.thedivide.r_dividend[36] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22726 Q=DIVIDE.thedivide.r_dividend[37] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22722 Q=DIVIDE.thedivide.r_dividend[38] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22718 Q=DIVIDE.thedivide.r_dividend[39] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22714 Q=DIVIDE.thedivide.r_dividend[40] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22710 Q=DIVIDE.thedivide.r_dividend[41] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22706 Q=DIVIDE.thedivide.r_dividend[42] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22702 Q=DIVIDE.thedivide.r_dividend[43] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22698 Q=DIVIDE.thedivide.r_dividend[44] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22694 Q=DIVIDE.thedivide.r_dividend[45] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22690 Q=DIVIDE.thedivide.r_dividend[46] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22686 Q=DIVIDE.thedivide.r_dividend[47] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22682 Q=DIVIDE.thedivide.r_dividend[48] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22678 Q=DIVIDE.thedivide.r_dividend[49] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22674 Q=DIVIDE.thedivide.r_dividend[50] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22670 Q=DIVIDE.thedivide.r_dividend[51] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22666 Q=DIVIDE.thedivide.r_dividend[52] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22662 Q=DIVIDE.thedivide.r_dividend[53] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22658 Q=DIVIDE.thedivide.r_dividend[54] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22654 Q=DIVIDE.thedivide.r_dividend[55] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22650 Q=DIVIDE.thedivide.r_dividend[56] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22646 Q=DIVIDE.thedivide.r_dividend[57] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22642 Q=DIVIDE.thedivide.r_dividend[58] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22638 Q=DIVIDE.thedivide.r_dividend[59] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22634 Q=DIVIDE.thedivide.r_dividend[60] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22630 Q=DIVIDE.thedivide.r_dividend[61] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23732 Q=DIVIDE.thedivide.r_dividend[62] +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.X[0] Q=DIVIDE.thedivide.r_bit[0] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[1] Q=DIVIDE.thedivide.r_bit[1] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[2] Q=DIVIDE.thedivide.r_bit[2] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[3] Q=DIVIDE.thedivide.r_bit[3] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$auto$alumacc.cc:485:replace_alu$3654.Y[4] Q=DIVIDE.thedivide.r_bit[4] R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3455 +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$eq$./benchmark/div.v:248$1635_Y Q=DIVIDE.thedivide.last_bit R=$abc$24881$auto$opt_dff.cc:253:combine_resets$3460 +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:263$1639_Y Q=DIVIDE.thedivide.pre_sign R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23648 Q=DIVIDE.thedivide.o_valid R=$abc$24881$flatten\DIVIDE.thedivide.$logic_or$./benchmark/div.v:189$1625_Y +.subckt sdffs C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23646 Q=DIVIDE.thedivide.r_z S=DIVIDE.thedivide.i_wr +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23628 Q=instruction_decoder.r_valid R=instruction_decoder.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2314_Y Q=DIVIDE.thedivide.r_sign R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2305_Y Q=DIVIDE.thedivide.o_quotient[0] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[0] Q=DIVIDE.thedivide.o_quotient[1] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[1] Q=DIVIDE.thedivide.o_quotient[2] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[2] Q=DIVIDE.thedivide.o_quotient[3] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[3] Q=DIVIDE.thedivide.o_quotient[4] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[4] Q=DIVIDE.thedivide.o_quotient[5] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[5] Q=DIVIDE.thedivide.o_quotient[6] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[6] Q=DIVIDE.thedivide.o_quotient[7] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[7] Q=DIVIDE.thedivide.o_quotient[8] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[8] Q=DIVIDE.thedivide.o_quotient[9] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[9] Q=DIVIDE.thedivide.o_quotient[10] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[10] Q=DIVIDE.thedivide.o_quotient[11] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[11] Q=DIVIDE.thedivide.o_quotient[12] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[12] Q=DIVIDE.thedivide.o_quotient[13] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[13] Q=DIVIDE.thedivide.o_quotient[14] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[14] Q=DIVIDE.thedivide.o_quotient[15] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[15] Q=DIVIDE.thedivide.o_quotient[16] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[16] Q=DIVIDE.thedivide.o_quotient[17] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[17] Q=DIVIDE.thedivide.o_quotient[18] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[18] Q=DIVIDE.thedivide.o_quotient[19] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[19] Q=DIVIDE.thedivide.o_quotient[20] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[20] Q=DIVIDE.thedivide.o_quotient[21] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[21] Q=DIVIDE.thedivide.o_quotient[22] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[22] Q=DIVIDE.thedivide.o_quotient[23] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[23] Q=DIVIDE.thedivide.o_quotient[24] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[24] Q=DIVIDE.thedivide.o_quotient[25] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[25] Q=DIVIDE.thedivide.o_quotient[26] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[26] Q=DIVIDE.thedivide.o_quotient[27] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[27] Q=DIVIDE.thedivide.o_quotient[28] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[28] Q=DIVIDE.thedivide.o_quotient[29] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[29] Q=DIVIDE.thedivide.o_quotient[30] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$procmux$2294_Y[30] Q=DIVIDE.thedivide.w_n R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$flatten\DIVIDE.thedivide.$logic_and$./benchmark/div.v:372$1666_Y Q=DIVIDE.thedivide.r_c R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23642 Q=DIVIDE.thedivide.r_divisor[31] R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[0] Q=regset[9][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[1] Q=regset[9][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[2] Q=regset[9][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[3] Q=regset[9][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[4] Q=regset[9][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[5] Q=regset[9][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[6] Q=regset[9][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[7] Q=regset[9][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[8] Q=regset[9][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[9] Q=regset[9][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[10] Q=regset[9][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[11] Q=regset[9][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[12] Q=regset[9][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[13] Q=regset[9][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[14] Q=regset[9][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[15] Q=regset[9][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[16] Q=regset[9][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[17] Q=regset[9][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[18] Q=regset[9][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[19] Q=regset[9][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[20] Q=regset[9][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[21] Q=regset[9][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[22] Q=regset[9][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[23] Q=regset[9][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[24] Q=regset[9][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[25] Q=regset[9][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[26] Q=regset[9][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[27] Q=regset[9][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[28] Q=regset[9][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[29] Q=regset[9][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[30] Q=regset[9][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[9][0][0]$y$4374[31] Q=regset[9][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[0] Q=regset[8][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[1] Q=regset[8][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[2] Q=regset[8][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[3] Q=regset[8][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[4] Q=regset[8][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[5] Q=regset[8][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[6] Q=regset[8][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[7] Q=regset[8][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[8] Q=regset[8][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[9] Q=regset[8][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[10] Q=regset[8][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[11] Q=regset[8][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[12] Q=regset[8][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[13] Q=regset[8][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[14] Q=regset[8][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[15] Q=regset[8][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[16] Q=regset[8][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[17] Q=regset[8][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[18] Q=regset[8][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[19] Q=regset[8][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[20] Q=regset[8][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[21] Q=regset[8][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[22] Q=regset[8][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[23] Q=regset[8][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[24] Q=regset[8][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[25] Q=regset[8][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[26] Q=regset[8][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[27] Q=regset[8][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[28] Q=regset[8][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[29] Q=regset[8][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[30] Q=regset[8][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[8][0][0]$y$4368[31] Q=regset[8][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22626 Q=DIVIDE.thedivide.r_dividend[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22624 Q=DIVIDE.thedivide.r_dividend[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22622 Q=DIVIDE.thedivide.r_dividend[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22620 Q=DIVIDE.thedivide.r_dividend[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22618 Q=DIVIDE.thedivide.r_dividend[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22616 Q=DIVIDE.thedivide.r_dividend[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22614 Q=DIVIDE.thedivide.r_dividend[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22612 Q=DIVIDE.thedivide.r_dividend[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22610 Q=DIVIDE.thedivide.r_dividend[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22608 Q=DIVIDE.thedivide.r_dividend[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22606 Q=DIVIDE.thedivide.r_dividend[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22604 Q=DIVIDE.thedivide.r_dividend[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22602 Q=DIVIDE.thedivide.r_dividend[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22600 Q=DIVIDE.thedivide.r_dividend[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22598 Q=DIVIDE.thedivide.r_dividend[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22596 Q=DIVIDE.thedivide.r_dividend[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22594 Q=DIVIDE.thedivide.r_dividend[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22592 Q=DIVIDE.thedivide.r_dividend[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22590 Q=DIVIDE.thedivide.r_dividend[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22588 Q=DIVIDE.thedivide.r_dividend[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22586 Q=DIVIDE.thedivide.r_dividend[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22584 Q=DIVIDE.thedivide.r_dividend[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22582 Q=DIVIDE.thedivide.r_dividend[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22580 Q=DIVIDE.thedivide.r_dividend[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22578 Q=DIVIDE.thedivide.r_dividend[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22576 Q=DIVIDE.thedivide.r_dividend[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22574 Q=DIVIDE.thedivide.r_dividend[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22572 Q=DIVIDE.thedivide.r_dividend[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22570 Q=DIVIDE.thedivide.r_dividend[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22568 Q=DIVIDE.thedivide.r_dividend[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$22566 Q=DIVIDE.thedivide.r_dividend[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23734 Q=DIVIDE.thedivide.r_dividend[32] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[0] Q=regset[6][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[1] Q=regset[6][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[2] Q=regset[6][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[3] Q=regset[6][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[4] Q=regset[6][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[5] Q=regset[6][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[6] Q=regset[6][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[7] Q=regset[6][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[8] Q=regset[6][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[9] Q=regset[6][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[10] Q=regset[6][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[11] Q=regset[6][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[12] Q=regset[6][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[13] Q=regset[6][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[14] Q=regset[6][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[15] Q=regset[6][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[16] Q=regset[6][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[17] Q=regset[6][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[18] Q=regset[6][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[19] Q=regset[6][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[20] Q=regset[6][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[21] Q=regset[6][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[22] Q=regset[6][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[23] Q=regset[6][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[24] Q=regset[6][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[25] Q=regset[6][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[26] Q=regset[6][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[27] Q=regset[6][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[28] Q=regset[6][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[29] Q=regset[6][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[30] Q=regset[6][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[6][0][0]$y$4350[31] Q=regset[6][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$simplemap.cc:240:simplemap_eqne$9293[0] Q=DIVIDE.thedivide.o_err R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23650 Q=DIVIDE.thedivide.o_busy R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23652 Q=DIVIDE.thedivide.r_busy R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[0] Q=regset[29][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[1] Q=regset[29][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[2] Q=regset[29][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[3] Q=regset[29][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[4] Q=regset[29][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[5] Q=regset[29][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[6] Q=regset[29][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[7] Q=regset[29][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[8] Q=regset[29][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[9] Q=regset[29][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[10] Q=regset[29][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[11] Q=regset[29][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[12] Q=regset[29][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[13] Q=regset[29][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[14] Q=regset[29][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[15] Q=regset[29][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[16] Q=regset[29][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[17] Q=regset[29][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[18] Q=regset[29][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[19] Q=regset[29][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[20] Q=regset[29][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[21] Q=regset[29][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[22] Q=regset[29][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[23] Q=regset[29][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[24] Q=regset[29][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[25] Q=regset[29][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[26] Q=regset[29][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[27] Q=regset[29][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[28] Q=regset[29][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[29] Q=regset[29][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[30] Q=regset[29][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[29][0][0]$y$4510[31] Q=regset[29][31] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][0] Q=dcd_F[0] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][1] Q=dcd_F[1] +.subckt dff C=i_clk D=$abc$24881$flatten\instruction_decoder.$0\o_cond[3:0][2] Q=dcd_F[2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[0] Q=regset[20][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[1] Q=regset[20][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[2] Q=regset[20][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[3] Q=regset[20][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[4] Q=regset[20][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[5] Q=regset[20][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[6] Q=regset[20][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[7] Q=regset[20][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[8] Q=regset[20][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[9] Q=regset[20][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[10] Q=regset[20][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[11] Q=regset[20][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[12] Q=regset[20][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[13] Q=regset[20][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[14] Q=regset[20][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[15] Q=regset[20][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[16] Q=regset[20][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[17] Q=regset[20][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[18] Q=regset[20][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[19] Q=regset[20][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[20] Q=regset[20][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[21] Q=regset[20][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[22] Q=regset[20][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[23] Q=regset[20][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[24] Q=regset[20][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[25] Q=regset[20][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[26] Q=regset[20][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[27] Q=regset[20][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[28] Q=regset[20][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[29] Q=regset[20][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[30] Q=regset[20][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[20][0][0]$y$4450[31] Q=regset[20][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23554 Q=instruction_decoder.o_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23552 Q=instruction_decoder.o_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23550 Q=instruction_decoder.o_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23548 Q=instruction_decoder.o_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23546 Q=instruction_decoder.o_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23544 Q=instruction_decoder.o_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23542 Q=instruction_decoder.o_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23540 Q=instruction_decoder.o_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23538 Q=instruction_decoder.o_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23536 Q=instruction_decoder.o_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23534 Q=instruction_decoder.o_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23532 Q=instruction_decoder.o_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23530 Q=instruction_decoder.o_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23528 Q=instruction_decoder.o_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23526 Q=instruction_decoder.o_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23524 Q=instruction_decoder.o_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23522 Q=instruction_decoder.o_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23520 Q=instruction_decoder.o_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23518 Q=instruction_decoder.o_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23516 Q=instruction_decoder.o_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23514 Q=instruction_decoder.o_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23512 Q=instruction_decoder.o_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23510 Q=instruction_decoder.o_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23508 Q=instruction_decoder.o_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23506 Q=instruction_decoder.o_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23504 Q=instruction_decoder.o_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23502 Q=instruction_decoder.o_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23500 Q=instruction_decoder.o_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23498 Q=instruction_decoder.o_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23722 Q=instruction_decoder.o_pc[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[0] Q=regset[7][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[1] Q=regset[7][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[2] Q=regset[7][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[3] Q=regset[7][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[4] Q=regset[7][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[5] Q=regset[7][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[6] Q=regset[7][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[7] Q=regset[7][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[8] Q=regset[7][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[9] Q=regset[7][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[10] Q=regset[7][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[11] Q=regset[7][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[12] Q=regset[7][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[13] Q=regset[7][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[14] Q=regset[7][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[15] Q=regset[7][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[16] Q=regset[7][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[17] Q=regset[7][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[18] Q=regset[7][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[19] Q=regset[7][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[20] Q=regset[7][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[21] Q=regset[7][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[22] Q=regset[7][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[23] Q=regset[7][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[24] Q=regset[7][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[25] Q=regset[7][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[26] Q=regset[7][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[27] Q=regset[7][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[28] Q=regset[7][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[29] Q=regset[7][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[30] Q=regset[7][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[7][0][0]$y$4356[31] Q=regset[7][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[0] Q=regset[31][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[1] Q=regset[31][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[2] Q=regset[31][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[3] Q=regset[31][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[4] Q=regset[31][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[5] Q=regset[31][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[6] Q=regset[31][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[7] Q=regset[31][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[8] Q=regset[31][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[9] Q=regset[31][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[10] Q=regset[31][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[11] Q=regset[31][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[12] Q=regset[31][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[13] Q=regset[31][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[14] Q=regset[31][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[15] Q=regset[31][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[16] Q=regset[31][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[17] Q=regset[31][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[18] Q=regset[31][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[19] Q=regset[31][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[20] Q=regset[31][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[21] Q=regset[31][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[22] Q=regset[31][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[23] Q=regset[31][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[24] Q=regset[31][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[25] Q=regset[31][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[26] Q=regset[31][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[27] Q=regset[31][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[28] Q=regset[31][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[29] Q=regset[31][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[30] Q=regset[31][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[31][0][0]$y$4522[31] Q=regset[31][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23496 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23494 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23492 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23490 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23488 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23486 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23484 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23482 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23480 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23478 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23476 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23474 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23472 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23470 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23468 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23466 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23464 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23462 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23460 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23458 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23456 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23454 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23452 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23450 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23448 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23446 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23444 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23442 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23440 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23724 Q=instruction_decoder.GEN_EARLY_BRANCH_LOGIC.r_branch_pc[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[0] Q=regset[21][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[1] Q=regset[21][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[2] Q=regset[21][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[3] Q=regset[21][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[4] Q=regset[21][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[5] Q=regset[21][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[6] Q=regset[21][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[7] Q=regset[21][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[8] Q=regset[21][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[9] Q=regset[21][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[10] Q=regset[21][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[11] Q=regset[21][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[12] Q=regset[21][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[13] Q=regset[21][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[14] Q=regset[21][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[15] Q=regset[21][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[16] Q=regset[21][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[17] Q=regset[21][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[18] Q=regset[21][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[19] Q=regset[21][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[20] Q=regset[21][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[21] Q=regset[21][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[22] Q=regset[21][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[23] Q=regset[21][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[24] Q=regset[21][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[25] Q=regset[21][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[26] Q=regset[21][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[27] Q=regset[21][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[28] Q=regset[21][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[29] Q=regset[21][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[30] Q=regset[21][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[21][0][0]$y$4456[31] Q=regset[21][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[0] Q=regset[24][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[1] Q=regset[24][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[2] Q=regset[24][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[3] Q=regset[24][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[4] Q=regset[24][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[5] Q=regset[24][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[6] Q=regset[24][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[7] Q=regset[24][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[8] Q=regset[24][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[9] Q=regset[24][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[10] Q=regset[24][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[11] Q=regset[24][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[12] Q=regset[24][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[13] Q=regset[24][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[14] Q=regset[24][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[15] Q=regset[24][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[16] Q=regset[24][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[17] Q=regset[24][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[18] Q=regset[24][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[19] Q=regset[24][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[20] Q=regset[24][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[21] Q=regset[24][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[22] Q=regset[24][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[23] Q=regset[24][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[24] Q=regset[24][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[25] Q=regset[24][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[26] Q=regset[24][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[27] Q=regset[24][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[28] Q=regset[24][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[29] Q=regset[24][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[30] Q=regset[24][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[24][0][0]$y$4478[31] Q=regset[24][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[0] Q=regset[22][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[1] Q=regset[22][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[2] Q=regset[22][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[3] Q=regset[22][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[4] Q=regset[22][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[5] Q=regset[22][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[6] Q=regset[22][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[7] Q=regset[22][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[8] Q=regset[22][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[9] Q=regset[22][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[10] Q=regset[22][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[11] Q=regset[22][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[12] Q=regset[22][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[13] Q=regset[22][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[14] Q=regset[22][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[15] Q=regset[22][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[16] Q=regset[22][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[17] Q=regset[22][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[18] Q=regset[22][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[19] Q=regset[22][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[20] Q=regset[22][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[21] Q=regset[22][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[22] Q=regset[22][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[23] Q=regset[22][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[24] Q=regset[22][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[25] Q=regset[22][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[26] Q=regset[22][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[27] Q=regset[22][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[28] Q=regset[22][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[29] Q=regset[22][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[30] Q=regset[22][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[22][0][0]$y$4462[31] Q=regset[22][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[0] Q=regset[26][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[1] Q=regset[26][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[2] Q=regset[26][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[3] Q=regset[26][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[4] Q=regset[26][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[5] Q=regset[26][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[6] Q=regset[26][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[7] Q=regset[26][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[8] Q=regset[26][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[9] Q=regset[26][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[10] Q=regset[26][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[11] Q=regset[26][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[12] Q=regset[26][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[13] Q=regset[26][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[14] Q=regset[26][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[15] Q=regset[26][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[16] Q=regset[26][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[17] Q=regset[26][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[18] Q=regset[26][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[19] Q=regset[26][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[20] Q=regset[26][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[21] Q=regset[26][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[22] Q=regset[26][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[23] Q=regset[26][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[24] Q=regset[26][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[25] Q=regset[26][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[26] Q=regset[26][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[27] Q=regset[26][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[28] Q=regset[26][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[29] Q=regset[26][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[30] Q=regset[26][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[26][0][0]$y$4490[31] Q=regset[26][31] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23438 Q=r_op_Av[0] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23436 Q=r_op_Av[1] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23434 Q=r_op_Av[2] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23432 Q=r_op_Av[3] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23430 Q=r_op_Av[4] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23428 Q=r_op_Av[5] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23426 Q=r_op_Av[6] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23424 Q=r_op_Av[7] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23422 Q=r_op_Av[8] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23420 Q=r_op_Av[9] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23418 Q=r_op_Av[10] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23416 Q=r_op_Av[11] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23414 Q=r_op_Av[12] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23412 Q=r_op_Av[13] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23410 Q=r_op_Av[14] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23408 Q=r_op_Av[15] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23406 Q=r_op_Av[16] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23404 Q=r_op_Av[17] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23402 Q=r_op_Av[18] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23400 Q=r_op_Av[19] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23398 Q=r_op_Av[20] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23396 Q=r_op_Av[21] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23394 Q=r_op_Av[22] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23392 Q=r_op_Av[23] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23390 Q=r_op_Av[24] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23388 Q=r_op_Av[25] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23386 Q=r_op_Av[26] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23384 Q=r_op_Av[27] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23382 Q=r_op_Av[28] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23380 Q=r_op_Av[29] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23378 Q=r_op_Av[30] +.subckt dff C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23556 Q=r_op_Av[31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[0] Q=regset[30][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[1] Q=regset[30][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[2] Q=regset[30][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[3] Q=regset[30][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[4] Q=regset[30][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[5] Q=regset[30][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[6] Q=regset[30][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[7] Q=regset[30][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[8] Q=regset[30][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[9] Q=regset[30][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[10] Q=regset[30][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[11] Q=regset[30][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[12] Q=regset[30][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[13] Q=regset[30][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[14] Q=regset[30][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[15] Q=regset[30][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[16] Q=regset[30][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[17] Q=regset[30][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[18] Q=regset[30][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[19] Q=regset[30][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[20] Q=regset[30][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[21] Q=regset[30][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[22] Q=regset[30][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[23] Q=regset[30][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[24] Q=regset[30][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[25] Q=regset[30][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[26] Q=regset[30][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[27] Q=regset[30][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[28] Q=regset[30][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[29] Q=regset[30][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[30] Q=regset[30][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[30][0][0]$y$4516[31] Q=regset[30][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[0] Q=regset[19][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[1] Q=regset[19][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[2] Q=regset[19][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[3] Q=regset[19][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[4] Q=regset[19][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[5] Q=regset[19][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[6] Q=regset[19][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[7] Q=regset[19][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[8] Q=regset[19][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[9] Q=regset[19][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[10] Q=regset[19][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[11] Q=regset[19][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[12] Q=regset[19][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[13] Q=regset[19][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[14] Q=regset[19][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[15] Q=regset[19][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[16] Q=regset[19][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[17] Q=regset[19][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[18] Q=regset[19][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[19] Q=regset[19][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[20] Q=regset[19][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[21] Q=regset[19][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[22] Q=regset[19][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[23] Q=regset[19][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[24] Q=regset[19][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[25] Q=regset[19][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[26] Q=regset[19][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[27] Q=regset[19][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[28] Q=regset[19][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[29] Q=regset[19][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[30] Q=regset[19][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[19][0][0]$y$4442[31] Q=regset[19][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[0] Q=regset[18][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[1] Q=regset[18][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[2] Q=regset[18][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[3] Q=regset[18][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[4] Q=regset[18][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[5] Q=regset[18][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[6] Q=regset[18][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[7] Q=regset[18][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[8] Q=regset[18][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[9] Q=regset[18][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[10] Q=regset[18][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[11] Q=regset[18][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[12] Q=regset[18][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[13] Q=regset[18][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[14] Q=regset[18][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[15] Q=regset[18][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[16] Q=regset[18][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[17] Q=regset[18][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[18] Q=regset[18][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[19] Q=regset[18][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[20] Q=regset[18][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[21] Q=regset[18][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[22] Q=regset[18][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[23] Q=regset[18][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[24] Q=regset[18][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[25] Q=regset[18][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[26] Q=regset[18][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[27] Q=regset[18][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[28] Q=regset[18][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[29] Q=regset[18][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[30] Q=regset[18][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[18][0][0]$y$4436[31] Q=regset[18][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[0] Q=regset[16][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[1] Q=regset[16][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[2] Q=regset[16][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[3] Q=regset[16][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[4] Q=regset[16][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[5] Q=regset[16][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[6] Q=regset[16][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[7] Q=regset[16][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[8] Q=regset[16][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[9] Q=regset[16][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[10] Q=regset[16][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[11] Q=regset[16][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[12] Q=regset[16][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[13] Q=regset[16][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[14] Q=regset[16][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[15] Q=regset[16][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[16] Q=regset[16][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[17] Q=regset[16][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[18] Q=regset[16][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[19] Q=regset[16][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[20] Q=regset[16][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[21] Q=regset[16][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[22] Q=regset[16][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[23] Q=regset[16][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[24] Q=regset[16][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[25] Q=regset[16][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[26] Q=regset[16][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[27] Q=regset[16][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[28] Q=regset[16][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[29] Q=regset[16][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[30] Q=regset[16][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[16][0][0]$y$4424[31] Q=regset[16][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[0] Q=regset[0][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[1] Q=regset[0][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[2] Q=regset[0][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[3] Q=regset[0][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[4] Q=regset[0][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[5] Q=regset[0][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[6] Q=regset[0][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[7] Q=regset[0][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[8] Q=regset[0][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[9] Q=regset[0][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[10] Q=regset[0][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[11] Q=regset[0][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[12] Q=regset[0][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[13] Q=regset[0][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[14] Q=regset[0][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[15] Q=regset[0][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[16] Q=regset[0][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[17] Q=regset[0][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[18] Q=regset[0][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[19] Q=regset[0][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[20] Q=regset[0][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[21] Q=regset[0][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[22] Q=regset[0][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[23] Q=regset[0][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[24] Q=regset[0][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[25] Q=regset[0][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[26] Q=regset[0][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[27] Q=regset[0][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[28] Q=regset[0][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[29] Q=regset[0][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[30] Q=regset[0][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[0][0][0]$y$4300[31] Q=regset[0][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[0] Q=regset[17][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[1] Q=regset[17][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[2] Q=regset[17][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[3] Q=regset[17][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[4] Q=regset[17][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[5] Q=regset[17][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[6] Q=regset[17][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[7] Q=regset[17][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[8] Q=regset[17][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[9] Q=regset[17][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[10] Q=regset[17][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[11] Q=regset[17][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[12] Q=regset[17][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[13] Q=regset[17][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[14] Q=regset[17][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[15] Q=regset[17][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[16] Q=regset[17][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[17] Q=regset[17][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[18] Q=regset[17][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[19] Q=regset[17][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[20] Q=regset[17][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[21] Q=regset[17][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[22] Q=regset[17][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[23] Q=regset[17][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[24] Q=regset[17][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[25] Q=regset[17][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[26] Q=regset[17][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[27] Q=regset[17][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[28] Q=regset[17][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[29] Q=regset[17][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[30] Q=regset[17][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[17][0][0]$y$4430[31] Q=regset[17][31] +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23376 Q=DIVIDE.thedivide.r_divisor[0] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23374 Q=DIVIDE.thedivide.r_divisor[1] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23372 Q=DIVIDE.thedivide.r_divisor[2] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23370 Q=DIVIDE.thedivide.r_divisor[3] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23368 Q=DIVIDE.thedivide.r_divisor[4] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23366 Q=DIVIDE.thedivide.r_divisor[5] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23364 Q=DIVIDE.thedivide.r_divisor[6] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23362 Q=DIVIDE.thedivide.r_divisor[7] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23360 Q=DIVIDE.thedivide.r_divisor[8] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23358 Q=DIVIDE.thedivide.r_divisor[9] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23356 Q=DIVIDE.thedivide.r_divisor[10] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23354 Q=DIVIDE.thedivide.r_divisor[11] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23352 Q=DIVIDE.thedivide.r_divisor[12] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23350 Q=DIVIDE.thedivide.r_divisor[13] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23348 Q=DIVIDE.thedivide.r_divisor[14] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23346 Q=DIVIDE.thedivide.r_divisor[15] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23344 Q=DIVIDE.thedivide.r_divisor[16] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23342 Q=DIVIDE.thedivide.r_divisor[17] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23340 Q=DIVIDE.thedivide.r_divisor[18] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23338 Q=DIVIDE.thedivide.r_divisor[19] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23336 Q=DIVIDE.thedivide.r_divisor[20] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23334 Q=DIVIDE.thedivide.r_divisor[21] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23332 Q=DIVIDE.thedivide.r_divisor[22] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23330 Q=DIVIDE.thedivide.r_divisor[23] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23328 Q=DIVIDE.thedivide.r_divisor[24] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23326 Q=DIVIDE.thedivide.r_divisor[25] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23324 Q=DIVIDE.thedivide.r_divisor[26] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23322 Q=DIVIDE.thedivide.r_divisor[27] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23320 Q=DIVIDE.thedivide.r_divisor[28] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23318 Q=DIVIDE.thedivide.r_divisor[29] R=DIVIDE.thedivide.i_reset +.subckt sdffr C=i_clk D=$abc$24881$auto$rtlil.cc:2693:MuxGate$23644 Q=DIVIDE.thedivide.r_divisor[30] R=DIVIDE.thedivide.i_reset +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[0] Q=regset[1][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[1] Q=regset[1][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[2] Q=regset[1][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[3] Q=regset[1][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[4] Q=regset[1][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[5] Q=regset[1][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[6] Q=regset[1][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[7] Q=regset[1][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[8] Q=regset[1][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[9] Q=regset[1][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[10] Q=regset[1][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[11] Q=regset[1][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[12] Q=regset[1][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[13] Q=regset[1][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[14] Q=regset[1][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[15] Q=regset[1][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[16] Q=regset[1][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[17] Q=regset[1][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[18] Q=regset[1][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[19] Q=regset[1][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[20] Q=regset[1][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[21] Q=regset[1][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[22] Q=regset[1][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[23] Q=regset[1][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[24] Q=regset[1][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[25] Q=regset[1][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[26] Q=regset[1][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[27] Q=regset[1][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[28] Q=regset[1][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[29] Q=regset[1][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[30] Q=regset[1][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[1][0][0]$y$4310[31] Q=regset[1][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[0] Q=regset[15][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[1] Q=regset[15][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[2] Q=regset[15][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[3] Q=regset[15][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[4] Q=regset[15][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[5] Q=regset[15][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[6] Q=regset[15][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[7] Q=regset[15][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[8] Q=regset[15][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[9] Q=regset[15][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[10] Q=regset[15][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[11] Q=regset[15][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[12] Q=regset[15][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[13] Q=regset[15][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[14] Q=regset[15][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[15] Q=regset[15][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[16] Q=regset[15][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[17] Q=regset[15][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[18] Q=regset[15][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[19] Q=regset[15][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[20] Q=regset[15][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[21] Q=regset[15][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[22] Q=regset[15][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[23] Q=regset[15][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[24] Q=regset[15][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[25] Q=regset[15][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[26] Q=regset[15][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[27] Q=regset[15][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[28] Q=regset[15][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[29] Q=regset[15][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[30] Q=regset[15][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[15][0][0]$y$4412[31] Q=regset[15][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[0] Q=regset[14][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[1] Q=regset[14][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[2] Q=regset[14][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[3] Q=regset[14][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[4] Q=regset[14][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[5] Q=regset[14][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[6] Q=regset[14][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[7] Q=regset[14][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[8] Q=regset[14][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[9] Q=regset[14][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[10] Q=regset[14][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[11] Q=regset[14][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[12] Q=regset[14][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[13] Q=regset[14][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[14] Q=regset[14][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[15] Q=regset[14][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[16] Q=regset[14][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[17] Q=regset[14][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[18] Q=regset[14][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[19] Q=regset[14][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[20] Q=regset[14][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[21] Q=regset[14][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[22] Q=regset[14][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[23] Q=regset[14][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[24] Q=regset[14][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[25] Q=regset[14][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[26] Q=regset[14][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[27] Q=regset[14][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[28] Q=regset[14][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[29] Q=regset[14][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[30] Q=regset[14][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[14][0][0]$y$4406[31] Q=regset[14][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[0] Q=regset[2][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[1] Q=regset[2][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[2] Q=regset[2][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[3] Q=regset[2][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[4] Q=regset[2][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[5] Q=regset[2][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[6] Q=regset[2][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[7] Q=regset[2][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[8] Q=regset[2][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[9] Q=regset[2][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[10] Q=regset[2][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[11] Q=regset[2][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[12] Q=regset[2][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[13] Q=regset[2][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[14] Q=regset[2][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[15] Q=regset[2][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[16] Q=regset[2][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[17] Q=regset[2][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[18] Q=regset[2][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[19] Q=regset[2][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[20] Q=regset[2][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[21] Q=regset[2][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[22] Q=regset[2][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[23] Q=regset[2][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[24] Q=regset[2][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[25] Q=regset[2][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[26] Q=regset[2][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[27] Q=regset[2][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[28] Q=regset[2][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[29] Q=regset[2][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[30] Q=regset[2][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[2][0][0]$y$4320[31] Q=regset[2][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[0] Q=regset[13][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[1] Q=regset[13][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[2] Q=regset[13][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[3] Q=regset[13][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[4] Q=regset[13][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[5] Q=regset[13][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[6] Q=regset[13][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[7] Q=regset[13][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[8] Q=regset[13][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[9] Q=regset[13][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[10] Q=regset[13][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[11] Q=regset[13][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[12] Q=regset[13][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[13] Q=regset[13][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[14] Q=regset[13][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[15] Q=regset[13][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[16] Q=regset[13][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[17] Q=regset[13][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[18] Q=regset[13][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[19] Q=regset[13][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[20] Q=regset[13][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[21] Q=regset[13][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[22] Q=regset[13][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[23] Q=regset[13][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[24] Q=regset[13][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[25] Q=regset[13][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[26] Q=regset[13][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[27] Q=regset[13][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[28] Q=regset[13][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[29] Q=regset[13][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[30] Q=regset[13][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[13][0][0]$y$4400[31] Q=regset[13][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[0] Q=regset[3][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[1] Q=regset[3][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[2] Q=regset[3][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[3] Q=regset[3][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[4] Q=regset[3][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[5] Q=regset[3][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[6] Q=regset[3][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[7] Q=regset[3][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[8] Q=regset[3][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[9] Q=regset[3][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[10] Q=regset[3][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[11] Q=regset[3][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[12] Q=regset[3][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[13] Q=regset[3][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[14] Q=regset[3][14] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[15] Q=regset[3][15] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[16] Q=regset[3][16] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[17] Q=regset[3][17] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[18] Q=regset[3][18] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[19] Q=regset[3][19] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[20] Q=regset[3][20] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[21] Q=regset[3][21] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[22] Q=regset[3][22] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[23] Q=regset[3][23] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[24] Q=regset[3][24] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[25] Q=regset[3][25] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[26] Q=regset[3][26] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[27] Q=regset[3][27] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[28] Q=regset[3][28] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[29] Q=regset[3][29] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[30] Q=regset[3][30] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[3][0][0]$y$4328[31] Q=regset[3][31] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[0] Q=regset[12][0] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[1] Q=regset[12][1] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[2] Q=regset[12][2] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[3] Q=regset[12][3] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[4] Q=regset[12][4] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[5] Q=regset[12][5] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[6] Q=regset[12][6] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[7] Q=regset[12][7] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[8] Q=regset[12][8] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[9] Q=regset[12][9] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[10] Q=regset[12][10] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[11] Q=regset[12][11] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[12] Q=regset[12][12] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[13] Q=regset[12][13] +.subckt dff C=i_clk D=$abc$24881$memory\regset$wrmux[12][0][0]$y$4394[14] Q=regset[12][14] +.subckt dff C=i_clk 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+.names $false o_prof_ticks[16] +1 1 +.names $false o_prof_ticks[17] +1 1 +.names $false o_prof_ticks[18] +1 1 +.names $false o_prof_ticks[19] +1 1 +.names $false o_prof_ticks[20] +1 1 +.names $false o_prof_ticks[21] +1 1 +.names $false o_prof_ticks[22] +1 1 +.names $false o_prof_ticks[23] +1 1 +.names $false o_prof_ticks[24] +1 1 +.names $false o_prof_ticks[25] +1 1 +.names $false o_prof_ticks[26] +1 1 +.names $false o_prof_ticks[27] +1 1 +.names $false o_prof_ticks[28] +1 1 +.names $false o_prof_ticks[29] +1 1 +.names $false o_prof_ticks[30] +1 1 +.names $false o_prof_ticks[31] +1 1 +.names $false pf_pc[0] +1 1 +.names $false pf_pc[1] +1 1 +.names $false wr_index[2] +1 1 +.end diff --git a/vtr_flow/benchmarks/microbenchmarks/and_clk.blif b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif new file mode 100644 index 00000000000..3f31b82b8d7 --- /dev/null +++ b/vtr_flow/benchmarks/microbenchmarks/and_clk.blif @@ -0,0 +1,12 @@ + +.model discrete_dffn +.inputs clk_ni d_i +.outputs d_o + +.names clk_ni int_clk_reg_exp_0 +0 1 + +.subckt dff D=d_i Q=d_o C=int_clk_reg_exp_0 + +.end + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt new file mode 100755 index 00000000000..fbf3358dd11 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/config.txt @@ -0,0 +1,29 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt new file mode 100755 index 00000000000..f06f65791c8 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt @@ -0,0 +1,29 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_perimeter_cb_90nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt new file mode 100755 index 00000000000..a37a1a874db --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/config.txt @@ -0,0 +1,30 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +script_params=-starting_stage vpr -verify_rr_graph --route_chan_width 60 -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt new file mode 100755 index 00000000000..aa015e865a0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/config.txt @@ -0,0 +1,30 @@ +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/4 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=diffeq.blif +circuit_list_add=ex5p.blif +circuit_list_add=s298.blif + +# Add architectures to list to sweep +arch_list_add=k4_N4_tileable_90nm.xml + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt +parse_file=vpr_parse_second_file.txt + +# How to parse QoR info +qor_parse_file=qor_rr_graph.txt + +# Pass requirements +pass_requirements_file=pass_requirements_verify_rr_graph.txt + +script_params=-starting_stage vpr -verify_rr_graph -rr_graph_ext .bin --route_chan_width 100 -track_memory_usage + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt new file mode 100644 index 00000000000..8576e7f7dc7 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin/config/golden_results.txt @@ -0,0 +1,4 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem yosys_synth_time max_yosys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_tileable_90nm.xml diffeq.blif common 9.82 vpr 61.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 62920 64 39 1935 1974 1 1104 520 23 23 529 clb auto 18.8 MiB 0.14 10227 61.2 MiB 0.57 0.01 6.71028 -1587.65 -6.71028 6.71028 0.25 0.0007736 0.0005813 0.0896507 0.0699632 34 17207 50 983127 929624 921133. 1741.27 7.25 0.536827 0.433199 14874 22 8645 29434 2727679 902790 6.8984 6.8984 -1779.84 -6.8984 0 0 1.17586e+06 2222.80 0.07 0.39 0.058014 0.0505961 +k4_N4_tileable_90nm.xml ex5p.blif common 15.22 vpr 52.07 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 53324 8 63 1072 1135 0 909 417 21 21 441 clb auto 14.2 MiB 0.10 11660 52.1 MiB 0.46 0.00 7.1886 -311.061 -7.1886 nan 0.20 0.000496 0.0003719 0.0573232 0.0458367 56 22886 46 804782 771343 1.13430e+06 2572.11 12.88 0.310125 0.253318 18533 21 8880 28500 4332796 1534540 7.97924 nan -339.269 -7.97924 0 0 1.45200e+06 3292.52 0.08 0.50 0.0368923 0.0322975 +k4_N4_tileable_90nm.xml s298.blif common 21.05 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-6725-gff83963de-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64 2022-11-01T15:38:22 LAPTOP-CVNHOGSN /home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks 77672 4 6 1942 1948 1 1193 581 26 26 676 clb auto 21.3 MiB 0.14 14254 75.9 MiB 0.69 0.01 13.2884 -103 -13.2884 13.2884 0.33 0.0008181 0.0006197 0.0966404 0.0764946 42 26119 42 1.28409e+06 1.27294e+06 1.41510e+06 2093.35 17.58 0.615507 0.493511 22147 19 9442 45483 4771423 1297512 13.6006 13.6006 -107.558 -13.6006 0 0 1.86822e+06 2763.64 0.19 0.67 0.0640435 0.0560669 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt new file mode 100644 index 00000000000..ab137e3b7da --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/config.txt @@ -0,0 +1,27 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif + +# Path to directory of architectures to use +archs_dir=arch/VIB + +# Add circuits to list to sweep +circuit_list_add=tseng.blif + +# Add architectures to list to sweep +arch_list_add=vib_test_arch.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +script_params=-starting_stage vpr --route_chan_width 138 --max_router_iterations 400 --device ultimate diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt new file mode 100644 index 00000000000..a512510d787 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vib/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +vib_test_arch.xml tseng.blif common 5.38 vpr 65.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 135 52 0 0 success unkown release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-49-generic x86_64 2025-01-16T17:23:42 yuanqiwang-virtual-machine /home/yuanqiwang/Wang/vtr/vtr-patch-1-old/vtr-verilog-to-routing-patch-1/vtr_flow/tasks 67284 52 122 1483 1605 1 1099 309 20 14 280 -1 ultimate 27.7 MiB 0.28 7177 63993 16752 32956 14285 65.7 MiB 0.35 0.01 3.57193 -517.324 -3.57193 3.57193 1.08 0.000907145 0.000734596 0.0683261 0.0559363 -1 9148 14 1.31729e+07 7.27569e+06 2.24313e+06 8011.19 0.60 0.126578 0.108805 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt new file mode 100644 index 00000000000..a3ceed7c14d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/config.txt @@ -0,0 +1,27 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/microbenchmarks + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=and_clk.blif + +# Add architectures to list to sweep +arch_list_add=k4_frac_N4_fracff_localClkGen_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --read_vpr_constraints ../../../../floor_plan.xml:../../../../route_constraint.xml --write_vpr_constraints vpr_constraints.xml --clock_modeling ideal diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt new file mode 100644 index 00000000000..1de222ff286 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/config/golden_results.txt @@ -0,0 +1,2 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_frac_N4_fracff_localClkGen_40nm.xml and_clk.blif common 0.07 vpr 46.89 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success bd5999406-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.15.0-67-generic x86_64 2023-03-17T17:48:18 workstation /home/tao/works/dev/route/vtr-verilog-to-routing/vtr_flow/tasks 48016 2 1 4 5 1 4 5 4 4 16 clb auto 7.9 MiB 0.00 11 46.9 MiB 0.00 0.00 1.13498 -1.13498 -1.13498 1.13498 0.00 3.031e-06 1.541e-06 3.5814e-05 2.5748e-05 -1 8 1 215576 107788 120301. 7518.81 0.00 0.00010342 7.9026e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml new file mode 100644 index 00000000000..861adf40966 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/floor_plan.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml new file mode 100644 index 00000000000..ca3d794706b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_vpr_constraint/route_constraint.xml @@ -0,0 +1,7 @@ + + + + + + + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index dc70228462c..a8628ef89af 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -99,6 +99,12 @@ regression_tests/vtr_reg_strong/koios_test regression_tests/vtr_reg_strong/koios_test_no_hb regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail +regression_tests/vtr_reg_strong/strong_vpr_constraint +regression_tests/vtr_reg_strong/strong_tileable_rr_graph +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify +regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router regression_tests/vtr_reg_strong/strong_routing_constraints +regression_tests/vtr_reg_strong/strong_vib