diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index c370562fd58..6070663eddc 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1253,6 +1253,15 @@ Analytical Placement is generally split into three stages: **Default:** ``annealer`` +.. option:: --ap_timing_tradeoff + + Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow. + + A value of 0.0 makes the AP flow focus completely on wirelength minimization, + while a value of 1.0 makes the AP flow focus completely on timing optimization. + + **Default:** ``0.5`` + .. option:: --ap_verbosity Controls the verbosity of the AP flow output. diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 2007a15b199..853f4cb2f02 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -7,9 +7,11 @@ #include "analytical_placement_flow.h" #include +#include "PreClusterTimingManager.h" #include "analytical_solver.h" #include "ap_netlist.h" #include "atom_netlist.h" +#include "cluster_util.h" #include "detailed_placer.h" #include "full_legalizer.h" #include "gen_ap_netlist_from_atoms.h" @@ -120,6 +122,7 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, const AtomNetlist& atom_nlist, const APNetlist& ap_netlist, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const DeviceContext& device_ctx) { if (g_vpr_ctx.atom().flat_placement_info().valid) { VTR_LOG("Flat Placement is provided in the AP flow, skipping the Global Placement.\n"); @@ -139,6 +142,8 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, device_ctx.grid, device_ctx.logical_block_types, device_ctx.physical_tile_types, + pre_cluster_timing_manager, + ap_opts.ap_timing_tradeoff, ap_opts.log_verbosity); return global_placer->place(); } @@ -163,12 +168,25 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { constraints); print_ap_netlist_stats(ap_netlist); + // Pre-compute the pre-clustering timing delays. This object will be passed + // into the global placer and the full legalizer to make them timing driven. + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + atom_nlist, + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + *device_ctx.arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + // Run the Global Placer. const t_ap_opts& ap_opts = vpr_setup.APOpts; PartialPlacement p_placement = run_global_placer(ap_opts, atom_nlist, ap_netlist, prepacker, + pre_cluster_timing_manager, device_ctx); // Verify that the partial placement is valid before running the full @@ -185,6 +203,7 @@ void run_analytical_placement_flow(t_vpr_setup& vpr_setup) { ap_netlist, atom_nlist, prepacker, + pre_cluster_timing_manager, vpr_setup, *device_ctx.arch, device_ctx.grid); diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 2aae5099608..e8c351d25b6 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -13,6 +13,9 @@ #include #include #include +#include "PreClusterTimingManager.h" +#include "atom_netlist.h" +#include "atom_netlist_fwd.h" #include "device_grid.h" #include "flat_placement_types.h" #include "partial_placement.h" @@ -42,15 +45,26 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, const APNetlist& netlist, const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity) { // Based on the solver type passed in, build the solver. switch (solver_type) { case e_ap_analytical_solver::QP_Hybrid: #ifdef EIGEN_INSTALLED - return std::make_unique(netlist, device_grid, log_verbosity); + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); #else (void)netlist; (void)device_grid; + (void)atom_netlist; + (void)pre_cluster_timing_manager; + (void)ap_timing_tradeoff; (void)log_verbosity; VPR_FATAL_ERROR(VPR_ERROR_AP, "QP Hybrid Solver requires the Eigen library"); @@ -58,7 +72,12 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver #endif // EIGEN_INSTALLED case e_ap_analytical_solver::LP_B2B: #ifdef EIGEN_INSTALLED - return std::make_unique(netlist, device_grid, log_verbosity); + return std::make_unique(netlist, + device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, + log_verbosity); #else VPR_FATAL_ERROR(VPR_ERROR_AP, "LP B2B Solver requires the Eigen library"); @@ -72,10 +91,15 @@ std::unique_ptr make_analytical_solver(e_ap_analytical_solver return nullptr; } -AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, int log_verbosity) +AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity) : netlist_(netlist) , blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()) , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) + , net_weights_(netlist.nets().size(), 1.0f) , log_verbosity_(log_verbosity) { // Get the number of moveable blocks in the netlist and create a unique // row ID from [0, num_moveable_blocks) for each moveable block in the @@ -94,6 +118,21 @@ AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, int log_verbosity) current_row_id++; num_moveable_blocks_++; } + + if (pre_cluster_timing_manager.is_valid()) { + for (APNetId net_id : netlist.nets()) { + // Get the atom net associated with the given AP net. When + // constructing the AP netlist, we happen to set the name of each + // AP net to the same name as the atom net that generated them! + // TODO: Create a proper lookup structure to go from the AP Netlist + // back to the Atom Netlist. + AtomNetId atom_net_id = atom_netlist.find_net(netlist.net_name(net_id)); + VTR_ASSERT(atom_net_id.is_valid()); + float crit = pre_cluster_timing_manager.calc_net_setup_criticality(atom_net_id, atom_netlist); + + net_weights_[net_id] = ap_timing_tradeoff * crit + (1.0f - ap_timing_tradeoff); + } + } } #ifdef EIGEN_INSTALLED @@ -201,12 +240,15 @@ void QPHybridSolver::init_linear_system() { for (APNetId net_id : netlist_.nets()) { size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_DEBUG(num_pins > 1); + + double net_weight = net_weights_[net_id]; + if (num_pins > star_num_pins_threshold) { // Create a star node and connect each block in the net to the star // node. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = static_cast(num_pins) / static_cast(num_pins - 1); + double w = net_weight * static_cast(num_pins) / static_cast(num_pins - 1); size_t star_node_id = num_moveable_blocks_ + star_node_offset; for (APPinId pin_id : netlist_.net_pins(net_id)) { APBlockId blk_id = netlist_.pin_block(pin_id); @@ -220,7 +262,7 @@ void QPHybridSolver::init_linear_system() { // exactly once to every other block in the net. // Using the weight from FastPlace // TODO: Investigate other weight terms. - double w = 1.0 / static_cast(num_pins - 1); + double w = net_weight * 1.0 / static_cast(num_pins - 1); for (size_t ipin_idx = 0; ipin_idx < num_pins; ipin_idx++) { APPinId first_pin_id = netlist_.net_pin(net_id, ipin_idx); APBlockId first_blk_id = netlist_.pin_block(first_pin_id); @@ -638,6 +680,7 @@ static inline APNetBounds get_unique_net_bounds(APNetId net_id, void B2BSolver::add_connection_to_system(APBlockId first_blk_id, APBlockId second_blk_id, size_t num_pins, + double net_w, const vtr::vector& blk_locs, std::vector>& triplet_list, Eigen::VectorXd& b) { @@ -660,7 +703,7 @@ void B2BSolver::add_connection_to_system(APBlockId first_blk_id, // The denominator of weight is zero, which causes infinity term in the matrix. Another way of // interpreting epsilon is the minimum distance two nodes are considered to be in placement. double dist = std::max(std::abs(blk_locs[first_blk_id] - blk_locs[second_blk_id]), distance_epsilon_); - double w = (2.0 / static_cast(num_pins - 1)) * (1.0 / dist); + double w = net_w * (2.0 / static_cast(num_pins - 1)) * (1.0 / dist); // Update the connectivity matrix and the constant vector. // This is similar to how connections are added for the quadratic formulation. @@ -696,6 +739,8 @@ void B2BSolver::init_linear_system(PartialPlacement& p_placement) { size_t num_pins = netlist_.net_pins(net_id).size(); VTR_ASSERT_SAFE_MSG(num_pins > 1, "net must have at least 2 pins"); + double net_w = net_weights_[net_id]; + // Find the bounding blocks APNetBounds net_bounds = get_unique_net_bounds(net_id, p_placement, netlist_); @@ -706,19 +751,19 @@ void B2BSolver::init_linear_system(PartialPlacement& p_placement) { for (APPinId pin_id : netlist_.net_pins(net_id)) { APBlockId blk_id = netlist_.pin_block(pin_id); if (blk_id != net_bounds.max_x_blk && blk_id != net_bounds.min_x_blk) { - add_connection_to_system(blk_id, net_bounds.max_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); - add_connection_to_system(blk_id, net_bounds.min_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(blk_id, net_bounds.max_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(blk_id, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); } if (blk_id != net_bounds.max_y_blk && blk_id != net_bounds.min_y_blk) { - add_connection_to_system(blk_id, net_bounds.max_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); - add_connection_to_system(blk_id, net_bounds.min_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(blk_id, net_bounds.max_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(blk_id, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); } } // Connect the bounds to each other. Its just easier to put these here // instead of in the for loop above. - add_connection_to_system(net_bounds.max_x_blk, net_bounds.min_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); - add_connection_to_system(net_bounds.max_y_blk, net_bounds.min_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(net_bounds.max_x_blk, net_bounds.min_x_blk, num_pins, net_w, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(net_bounds.max_y_blk, net_bounds.min_y_blk, num_pins, net_w, p_placement.block_y_locs, triplet_list_y, b_y); } // Build the sparse connectivity matrices from the triplets. diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index 1c00fc055a4..2d748e2a493 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -31,6 +31,8 @@ // Forward declarations class PartialPlacement; class APNetlist; +class AtomNetlist; +class PreClusterTimingManager; /** * @brief A strong ID for the rows in a matrix used during solving. @@ -60,7 +62,11 @@ class AnalyticalSolver { * Initializes the internal data members of the base class which are useful * for all solvers. */ - AnalyticalSolver(const APNetlist& netlist, int log_verbosity); + AnalyticalSolver(const APNetlist& netlist, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, + int log_verbosity); /** * @brief Run an iteration of the solver using the given partial placement @@ -113,6 +119,12 @@ class AnalyticalSolver { /// solver. vtr::vector row_id_to_blk_id_; + /// @brief The base weight of each net in the AP netlist. This weight can + /// be used to make the solver more interested in some nets over + /// others. These weights can be any positive value, but are often + /// between 0 and 1. + vtr::vector net_weights_; + /// @brief The verbosity of log messages in the Analytical Solver. int log_verbosity_; }; @@ -123,6 +135,9 @@ class AnalyticalSolver { std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, const APNetlist& netlist, const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. @@ -278,8 +293,11 @@ class QPHybridSolver : public AnalyticalSolver { */ QPHybridSolver(const APNetlist& netlist, const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity) - : AnalyticalSolver(netlist, log_verbosity) { + : AnalyticalSolver(netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) { // Initializing the linear system only depends on the netlist and fixed // block locations. Both are provided by the netlist, allowing this to // be initialized in the constructor. @@ -411,8 +429,11 @@ class B2BSolver : public AnalyticalSolver { public: B2BSolver(const APNetlist& ap_netlist, const DeviceGrid& device_grid, + const AtomNetlist& atom_netlist, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity) - : AnalyticalSolver(ap_netlist, log_verbosity) + : AnalyticalSolver(ap_netlist, atom_netlist, pre_cluster_timing_manager, ap_timing_tradeoff, log_verbosity) , device_grid_width_(device_grid.width()) , device_grid_height_(device_grid.height()) {} @@ -503,6 +524,7 @@ class B2BSolver : public AnalyticalSolver { void add_connection_to_system(APBlockId first_blk_id, APBlockId second_blk_id, size_t num_pins, + double net_w, const vtr::vector& blk_locs, std::vector>& triplet_list, Eigen::VectorXd& b); diff --git a/vpr/src/analytical_place/full_legalizer.cpp b/vpr/src/analytical_place/full_legalizer.cpp index 6981908c479..767ac67e3d9 100644 --- a/vpr/src/analytical_place/full_legalizer.cpp +++ b/vpr/src/analytical_place/full_legalizer.cpp @@ -16,6 +16,7 @@ #include #include +#include "PreClusterTimingManager.h" #include "ShowSetup.h" #include "ap_flow_enums.h" #include "ap_netlist_fwd.h" @@ -58,6 +59,7 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega const APNetlist& ap_netlist, const AtomNetlist& atom_netlist, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const t_vpr_setup& vpr_setup, const t_arch& arch, const DeviceGrid& device_grid) { @@ -66,6 +68,7 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega return std::make_unique(ap_netlist, atom_netlist, prepacker, + pre_cluster_timing_manager, vpr_setup, arch, device_grid); @@ -73,6 +76,7 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega return std::make_unique(ap_netlist, atom_netlist, prepacker, + pre_cluster_timing_manager, vpr_setup, arch, device_grid); @@ -516,9 +520,9 @@ void APPack::legalize(const PartialPlacement& p_placement) { try_pack(vpr_setup_.PackerOpts, vpr_setup_.AnalysisOpts, arch_, - vpr_setup_.RoutingArch, vpr_setup_.PackerRRGraph, prepacker_, + pre_cluster_timing_manager_, flat_placement_info); // The Packer stores the clusters into a .net file. Load the packing file. diff --git a/vpr/src/analytical_place/full_legalizer.h b/vpr/src/analytical_place/full_legalizer.h index 3532022760d..57baef27fc9 100644 --- a/vpr/src/analytical_place/full_legalizer.h +++ b/vpr/src/analytical_place/full_legalizer.h @@ -19,6 +19,7 @@ class ClusteredNetlist; class DeviceGrid; class PartialPlacement; class PlaceMacros; +class PreClusterTimingManager; class Prepacker; struct t_arch; struct t_vpr_setup; @@ -37,12 +38,14 @@ class FullLegalizer { FullLegalizer(const APNetlist& ap_netlist, const AtomNetlist& atom_netlist, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const t_vpr_setup& vpr_setup, const t_arch& arch, const DeviceGrid& device_grid) : ap_netlist_(ap_netlist) , atom_netlist_(atom_netlist) , prepacker_(prepacker) + , pre_cluster_timing_manager_(pre_cluster_timing_manager) , vpr_setup_(vpr_setup) , arch_(arch) , device_grid_(device_grid) {} @@ -66,6 +69,10 @@ class FullLegalizer { /// @brief The Prepacker used to create molecules from the Atom Netlist. const Prepacker& prepacker_; + /// @brief Pre-Clustering timing manager, hold pre-computed delay information + /// at the primitive level prior to packing. + const PreClusterTimingManager& pre_cluster_timing_manager_; + /// @brief The VPR setup options passed into the VPR flow. This must be /// mutable since some parts of packing modify the options. const t_vpr_setup& vpr_setup_; @@ -84,6 +91,7 @@ std::unique_ptr make_full_legalizer(e_ap_full_legalizer full_lega const APNetlist& ap_netlist, const AtomNetlist& atom_netlist, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const t_vpr_setup& vpr_setup, const t_arch& arch, const DeviceGrid& device_grid); diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index 3e716b7ea16..d9131e85308 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -35,6 +35,8 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity) { return std::make_unique(analytical_solver_type, partial_legalizer_type, @@ -44,6 +46,8 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic device_grid, logical_block_types, physical_tile_types, + pre_cluster_timing_manager, + ap_timing_tradeoff, log_verbosity); } @@ -55,6 +59,8 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity) : GlobalPlacer(ap_netlist, log_verbosity) { // This can be a long method. Good to time this to see how long it takes to @@ -66,6 +72,9 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_ty solver_ = make_analytical_solver(analytical_solver_type, ap_netlist_, device_grid, + atom_netlist, + pre_cluster_timing_manager, + ap_timing_tradeoff, log_verbosity_); // Build the density manager used by the partial legalizer. diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 94f68e260f9..7772aa302bb 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -24,6 +24,7 @@ class APNetlist; class AnalyticalSolver; class PartialLegalizer; class Prepacker; +class PreClusterTimingManager; struct PartialPlacement; /** @@ -80,6 +81,8 @@ std::unique_ptr make_global_placer(e_ap_analytical_solver analytic const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity); /** @@ -143,6 +146,8 @@ class SimPLGlobalPlacer : public GlobalPlacer { const DeviceGrid& device_grid, const std::vector& logical_block_types, const std::vector& physical_tile_types, + const PreClusterTimingManager& pre_cluster_timing_manager, + float ap_timing_tradeoff, int log_verbosity); /** diff --git a/vpr/src/base/CheckSetup.cpp b/vpr/src/base/CheckSetup.cpp index 1beb53242e7..923413ac498 100644 --- a/vpr/src/base/CheckSetup.cpp +++ b/vpr/src/base/CheckSetup.cpp @@ -5,7 +5,6 @@ #include "vpr_types.h" #include "vpr_error.h" #include "globals.h" -#include "read_xml_arch_file.h" static constexpr int DYMANIC_PORT_RANGE_MIN = 49152; static constexpr int DYNAMIC_PORT_RANGE_MAX = 65535; @@ -83,10 +82,11 @@ void CheckSetup(const t_packer_opts& packer_opts, "Analytical placement should skip packing.\n"); } - // TODO: Should check that read_vpr_constraint_file is non-empty or - // check within analytical placement that the floorplanning has - // some fixed blocks somewhere. Maybe we can live without fixed - // blocks. + // Make sure that the timing tradeoff is valid. + if (ap_opts.ap_timing_tradeoff < 0.0f || ap_opts.ap_timing_tradeoff > 1.0f) { + VPR_FATAL_ERROR(VPR_ERROR_OTHER, + "ap_timing_tradeoff expects a value between 0.0 and 1.0"); + } // TODO: Should we enforce that the size of the device is fixed. This // goes with ensuring that some blocks are fixed. diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index fe046fd932e..78b8f797ff5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -551,6 +551,7 @@ void SetupAPOpts(const t_options& options, apOpts.partial_legalizer_type = options.ap_partial_legalizer.value(); apOpts.full_legalizer_type = options.ap_full_legalizer.value(); apOpts.detailed_placer_type = options.ap_detailed_placer.value(); + apOpts.ap_timing_tradeoff = options.ap_timing_tradeoff.value(); apOpts.log_verbosity = options.ap_verbosity.value(); } diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 712fa5619c1..f21200e97ee 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -649,6 +649,7 @@ static void ShowAnalyticalPlacerOpts(const t_ap_opts& APOpts) { VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown detailed_placer_type\n"); } + VTR_LOG("AnalyticalPlacerOpts.ap_timing_tradeoff: %f\n", APOpts.ap_timing_tradeoff); VTR_LOG("AnalyticalPlacerOpts.log_verbosity: %d\n", APOpts.log_verbosity); } diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index b3891336861..26f9b5bb132 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1931,6 +1931,13 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio .default_value("annealer") .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.ap_timing_tradeoff, "--ap_timing_tradeoff") + .help( + "Controls the trade-off between wirelength (HPWL) and delay minimization in the AP flow.\n" + "A value of 0.0 makes the AP flow focus completely on wirelength minimization, while a value of 1.0 makes the AP flow focus completely on timing optimization.") + .default_value("0.5") + .show_in(argparse::ShowIn::HELP_ONLY); + ap_grp.add_argument(args.ap_verbosity, "--ap_verbosity") .help( "Controls how verbose the AP flow's log messages will be. Higher " diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index bc6b62660bb..dd1be4b2575 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -102,6 +102,7 @@ struct t_options { argparse::ArgValue ap_full_legalizer; argparse::ArgValue ap_detailed_placer; argparse::ArgValue ap_verbosity; + argparse::ArgValue ap_timing_tradeoff; /* Clustering options */ argparse::ArgValue connection_driven_clustering; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 3e2c0fd4f48..be6115112e4 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -17,6 +17,7 @@ #include #include +#include "PreClusterTimingManager.h" #include "flat_placement_types.h" #include "cluster_util.h" #include "physical_types.h" @@ -620,10 +621,22 @@ bool vpr_pack(t_vpr_setup& vpr_setup, const t_arch& arch) { const Prepacker prepacker(g_vpr_ctx.atom().netlist(), g_vpr_ctx.device().logical_block_types); + // Setup pre-clustering timing analysis + PreClusterTimingManager pre_cluster_timing_manager(vpr_setup.PackerOpts.timing_driven, + g_vpr_ctx.atom().netlist(), + g_vpr_ctx.atom().lookup(), + prepacker, + vpr_setup.PackerOpts.timing_update_type, + arch, + vpr_setup.RoutingArch, + vpr_setup.PackerOpts.device_layout, + vpr_setup.AnalysisOpts); + return try_pack(vpr_setup.PackerOpts, vpr_setup.AnalysisOpts, - arch, vpr_setup.RoutingArch, + arch, vpr_setup.PackerRRGraph, prepacker, + pre_cluster_timing_manager, g_vpr_ctx.atom().flat_placement_info()); } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 78f28407612..92100562dfb 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1056,6 +1056,9 @@ struct t_placer_opts { * The type of full legalizer the AP flow will use. * @param detailed_placer_type * The type of detailed placter the AP flow will use. + * @param ap_timing_tradeoff + * A trade-off parameter used to decide how focused the AP flow + * should be on optimizing timing over wirelength. * @param log_verbosity * The verbosity level of log messages in the AP flow, with higher * values leading to more verbose messages. @@ -1071,6 +1074,8 @@ struct t_ap_opts { e_ap_detailed_placer detailed_placer_type; + float ap_timing_tradeoff; + int log_verbosity; }; diff --git a/vpr/src/pack/pack.cpp b/vpr/src/pack/pack.cpp index ae1cde8244d..c1f7750459b 100644 --- a/vpr/src/pack/pack.cpp +++ b/vpr/src/pack/pack.cpp @@ -30,9 +30,9 @@ static bool try_size_device_grid(const t_arch& arch, bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, const t_arch& arch, - const t_det_routing_arch& routing_arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const FlatPlacementInfo& flat_placement_info) { const AtomContext& atom_ctx = g_vpr_ctx.atom(); const DeviceContext& device_ctx = g_vpr_ctx.device(); @@ -67,17 +67,6 @@ bool try_pack(const t_packer_opts& packer_opts, */ AttractionInfo attraction_groups(false); - // Setup pre-clustering timing analysis - PreClusterTimingManager pre_cluster_timing_manager(packer_opts.timing_driven, - atom_ctx.netlist(), - atom_ctx.lookup(), - prepacker, - packer_opts.timing_update_type, - arch, - routing_arch, - packer_opts.device_layout, - analysis_opts); - // We keep track of the overfilled partition regions from all pack iterations in // this vector. This is so that if the first iteration fails due to overfilled // partition regions, and it fails again, we can carry over the previous failed diff --git a/vpr/src/pack/pack.h b/vpr/src/pack/pack.h index c0cb1a4581f..64189ea4ee9 100644 --- a/vpr/src/pack/pack.h +++ b/vpr/src/pack/pack.h @@ -6,10 +6,10 @@ class AtomNetId; class FlatPlacementInfo; +class PreClusterTimingManager; class Prepacker; struct t_analysis_opts; struct t_arch; -struct t_det_routing_arch; struct t_lb_type_rr_node; struct t_packer_opts; @@ -24,8 +24,12 @@ struct t_packer_opts; * performed in the packer. * @param arch * The architecture to create clusters for. - * @param routing_arch * @param lb_type_rr_graphs + * @param prepacker + * The prepacker used to form atoms into molecules prior to packing. + * @param pre_cluster_timing_manager + * Manager object to store the pre-computed timing delay calculations. + * Used to inform the packer of timing critical paths. * @param flat_placement_info * Flat (primitive-level) placement information that may be * provided by the user as a hint for packing. Will be invalid if @@ -34,9 +38,9 @@ struct t_packer_opts; bool try_pack(const t_packer_opts& packer_opts, const t_analysis_opts& analysis_opts, const t_arch& arch, - const t_det_routing_arch& routing_arch, std::vector* lb_type_rr_graphs, const Prepacker& prepacker, + const PreClusterTimingManager& pre_cluster_timing_manager, const FlatPlacementInfo& flat_placement_info); std::unordered_set alloc_and_load_is_clock(); diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp index ec3b6a44958..44407d61522 100644 --- a/vpr/src/timing/PreClusterTimingManager.cpp +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -21,6 +21,7 @@ #include "tatum/echo_writer.hpp" #include "vpr_types.h" #include "vtr_assert.h" +#include "vtr_time.h" /** * Since the parameters of a switch may change as a function of its fanin, @@ -65,6 +66,9 @@ PreClusterTimingManager::PreClusterTimingManager(bool timing_driven, } is_valid_ = true; + // Start an overall timer for building the pre-cluster timing info. + vtr::ScopedStartFinishTimer timer("Initializing Pre-Cluster Timing"); + // Approximate the inter-cluster delay // FIXME: This can probably be simplified. It can also be improved using // AP information. @@ -274,3 +278,19 @@ float PreClusterTimingManager::calc_atom_setup_criticality(AtomBlockId blk_id, return crit; } + +float PreClusterTimingManager::calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const { + VTR_ASSERT_SAFE_MSG(is_valid_, + "PreClusterTimingManager has not been initialized"); + VTR_ASSERT_SAFE_MSG(net_id.is_valid(), + "Invalid net ID"); + + // We let the criticality of an entire net to be the max criticality of all + // timing edges within the net. Since all timing paths start at the driver, + // this is equivalent to the criticality of the driver pin. + AtomPinId net_driver_pin_id = atom_netlist.net_driver(net_id); + VTR_ASSERT_SAFE_MSG(net_driver_pin_id.is_valid(), + "Net has no driver"); + return timing_info_->setup_pin_criticality(net_driver_pin_id); +} diff --git a/vpr/src/timing/PreClusterTimingManager.h b/vpr/src/timing/PreClusterTimingManager.h index f76489b8ee9..0aaed6edea1 100644 --- a/vpr/src/timing/PreClusterTimingManager.h +++ b/vpr/src/timing/PreClusterTimingManager.h @@ -75,6 +75,17 @@ class PreClusterTimingManager { float calc_atom_setup_criticality(AtomBlockId blk_id, const AtomNetlist& atom_netlist) const; + /** + * @brief Calculates the setup criticality of the given net in the primitive + * netlist. + * + * Currently defined as the maximum criticality over all edges in the net + * from the driver pin to the sink pins. This is equivalent to the criticality + * of the driver pin. + */ + float calc_net_setup_criticality(AtomNetId net_id, + const AtomNetlist& atom_netlist) const; + /** * @brief Returns whether or not the pre-cluster timing manager was * initialized (i.e. timing information can be computed). diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt index 651ce660172..f1a65749d89 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.36 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76392 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 9403 6159 8332 1169 4944 2219 74.6 MiB 2.06 0.01 6.38627 5.03307 -82.5272 -5.03307 nan 0.05 0.00184828 0.00145901 0.0761667 0.0633817 74.6 MiB 2.06 74.6 MiB 1.36 10201 18.4801 2604 4.71739 4077 19753 686869 111324 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.47355 nan -88.2759 -5.47355 0 0 0.19 -1 -1 74.6 MiB 0.25 0.188153 0.163341 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.38 vpr 75.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77100 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 8563 7535 44489 711 9803 33975 75.3 MiB 0.67 0.01 6.75273 4.22233 -808.963 -4.22233 nan 0.07 0.00206921 0.00182545 0.0513366 0.0463847 75.3 MiB 0.67 75.3 MiB 0.37 10334 17.2809 2851 4.76756 2724 5860 351757 83165 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.44165 nan -865.851 -4.44165 0 0 0.21 -1 -1 75.3 MiB 0.18 0.157515 0.145045 75.3 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.38 vpr 103.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 294 10 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105556 10 10 2659 20 0 1271 314 22 22 484 -1 mcnc_large -1 -1 35357 24411 60010 16230 38382 5398 103.1 MiB 8.28 0.02 9.43184 6.46379 -62.5671 -6.46379 nan 0.16 0.00656395 0.00519987 0.417008 0.342569 103.1 MiB 8.28 103.1 MiB 4.38 37499 29.5035 9497 7.47207 8209 52283 2194356 288045 2.15576e+07 1.58448e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75089 nan -64.5268 -6.75089 0 0 0.64 -1 -1 103.1 MiB 0.89 0.797133 0.683077 103.1 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.23 vpr 75.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77600 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 10195 6390 9775 797 4761 4217 75.8 MiB 1.99 0.01 6.7004 4.74782 -144.082 -4.74782 nan 0.06 0.00226831 0.00182788 0.0691298 0.0583805 75.8 MiB 1.99 75.8 MiB 1.23 10367 18.2518 2719 4.78697 4167 22236 721470 123170 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.02595 nan -149.084 -5.02595 0 0 0.19 -1 -1 75.8 MiB 0.29 0.198778 0.17414 75.8 MiB -1 0.06 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 3.59 vpr 75.35 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77156 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.3 MiB 2.81 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.05 0.00179692 0.00145997 0.0947522 0.0791883 75.3 MiB 2.81 75.3 MiB 1.73 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.34 -1 -1 75.3 MiB 0.25 0.210289 0.182458 75.3 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.99 vpr 76.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77936 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.1 MiB 1.14 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.12 0.0036209 0.00320967 0.0974498 0.0783511 76.1 MiB 1.14 76.1 MiB 0.58 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.37 -1 -1 76.1 MiB 0.25 0.241683 0.211802 76.1 MiB -1 0.12 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 12.92 vpr 106.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108560 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 106.0 MiB 10.38 0.02 9.2649 6.61089 -64.2928 -6.61089 nan 0.15 0.00607931 0.0048535 0.385282 0.31707 106.0 MiB 10.38 106.0 MiB 5.44 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.10 -1 -1 106.0 MiB 0.85 0.754783 0.64805 106.0 MiB -1 0.15 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.71 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78472 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.6 MiB 3.58 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00393615 0.00326892 0.130272 0.112932 76.6 MiB 3.58 76.6 MiB 2.21 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.33 -1 -1 76.6 MiB 0.51 0.372342 0.333335 76.6 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt index b81de13a2b0..0d53ef34c88 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.30 vpr 74.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76348 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 9403 6159 8332 1169 4944 2219 74.6 MiB 2.07 0.01 6.38627 5.03307 -82.5272 -5.03307 nan 0.05 0.00163075 0.00127541 0.0698617 0.0579099 74.6 MiB 2.07 74.6 MiB 1.38 10201 18.4801 2604 4.71739 4077 19753 686869 111324 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.47355 nan -88.2759 -5.47355 0 0 0.19 -1 -1 74.6 MiB 0.23 0.174176 0.150615 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.46 vpr 75.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77480 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 8563 7535 44489 711 9803 33975 75.7 MiB 0.69 0.01 6.75273 4.22233 -808.963 -4.22233 nan 0.07 0.00230416 0.00205573 0.0543722 0.0491359 75.7 MiB 0.69 75.7 MiB 0.38 10334 17.2809 2851 4.76756 2724 5860 351757 83165 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.44165 nan -865.851 -4.44165 0 0 0.22 -1 -1 75.7 MiB 0.20 0.166801 0.153732 75.7 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.34 vpr 103.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 294 10 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105984 10 10 2659 20 0 1271 314 22 22 484 -1 mcnc_large -1 -1 35357 24411 60010 16230 38382 5398 103.5 MiB 8.19 0.02 9.43184 6.46379 -62.5671 -6.46379 nan 0.16 0.00653141 0.00517397 0.420809 0.346396 103.5 MiB 8.19 103.5 MiB 4.27 37499 29.5035 9497 7.47207 8209 52283 2194356 288045 2.15576e+07 1.58448e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75089 nan -64.5268 -6.75089 0 0 0.64 -1 -1 103.5 MiB 0.90 0.816903 0.702518 103.5 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.26 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77524 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 10195 6390 9775 797 4761 4217 75.7 MiB 1.97 0.01 6.7004 4.74782 -144.082 -4.74782 nan 0.05 0.00190585 0.00149849 0.0653002 0.0549159 75.7 MiB 1.97 75.7 MiB 1.23 10367 18.2518 2719 4.78697 4167 22236 721470 123170 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.02595 nan -149.084 -5.02595 0 0 0.19 -1 -1 75.7 MiB 0.27 0.189214 0.165171 75.7 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.74 vpr 75.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77540 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.7 MiB 3.70 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.09 0.0035052 0.00298022 0.180058 0.153756 75.7 MiB 3.70 75.7 MiB 2.39 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.32 -1 -1 75.7 MiB 0.44 0.38029 0.335234 75.7 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.13 vpr 76.22 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78052 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.2 MiB 1.12 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.13 0.00329462 0.00292336 0.0814643 0.073498 76.2 MiB 1.12 76.2 MiB 0.62 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.44 -1 -1 76.2 MiB 0.26 0.228991 0.210429 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 14.37 vpr 106.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108600 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 106.1 MiB 11.86 0.02 9.2649 6.61089 -64.2928 -6.61089 nan 0.16 0.00709645 0.00577285 0.43209 0.360098 106.1 MiB 11.86 106.1 MiB 6.76 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.10 -1 -1 106.1 MiB 0.84 0.802982 0.692043 106.1 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.72 vpr 76.63 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78472 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.6 MiB 3.56 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00423796 0.00353974 0.144045 0.126533 76.6 MiB 3.56 76.6 MiB 2.22 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.35 -1 -1 76.6 MiB 0.49 0.365708 0.327139 76.6 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt index 7f6c398f2d7..fd84ac2c275 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.33 vpr 74.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76408 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 9403 6159 8332 1169 4944 2219 74.6 MiB 2.07 0.01 6.38627 5.03307 -82.5272 -5.03307 nan 0.05 0.00174681 0.00136501 0.0775146 0.0645634 74.6 MiB 2.07 74.6 MiB 1.37 10201 18.4801 2604 4.71739 4077 19753 686869 111324 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.47355 nan -88.2759 -5.47355 0 0 0.19 -1 -1 74.6 MiB 0.24 0.187199 0.162157 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.42 vpr 75.41 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77220 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 8563 7535 44489 711 9803 33975 75.4 MiB 0.67 0.01 6.75273 4.22233 -808.963 -4.22233 nan 0.07 0.00206925 0.0018412 0.0508939 0.0460358 75.4 MiB 0.67 75.4 MiB 0.37 10334 17.2809 2851 4.76756 2724 5860 351757 83165 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.44165 nan -865.851 -4.44165 0 0 0.21 -1 -1 75.4 MiB 0.19 0.160523 0.14791 75.4 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.53 vpr 103.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 294 10 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105740 10 10 2659 20 0 1271 314 22 22 484 -1 mcnc_large -1 -1 35357 24411 60010 16230 38382 5398 103.3 MiB 8.21 0.02 9.43184 6.46379 -62.5671 -6.46379 nan 0.16 0.00644882 0.00510584 0.417293 0.342947 103.3 MiB 8.21 103.3 MiB 4.32 37499 29.5035 9497 7.47207 8209 52283 2194356 288045 2.15576e+07 1.58448e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75089 nan -64.5268 -6.75089 0 0 0.63 -1 -1 103.3 MiB 0.86 0.791005 0.677375 103.3 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.21 vpr 75.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77656 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 10195 6390 9775 797 4761 4217 75.8 MiB 1.98 0.01 6.7004 4.74782 -144.082 -4.74782 nan 0.06 0.00192868 0.00151668 0.0664797 0.0560886 75.8 MiB 1.98 75.8 MiB 1.23 10367 18.2518 2719 4.78697 4167 22236 721470 123170 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.02595 nan -149.084 -5.02595 0 0 0.19 -1 -1 75.8 MiB 0.28 0.192055 0.167866 75.8 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.83 vpr 75.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77412 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.6 MiB 3.75 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.09 0.00361843 0.00310078 0.177919 0.151899 75.6 MiB 3.75 75.6 MiB 2.43 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.34 -1 -1 75.6 MiB 0.45 0.377186 0.332405 75.6 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.00 vpr 76.24 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78072 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.2 MiB 1.12 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.13 0.00374322 0.0033467 0.0845942 0.0761009 76.2 MiB 1.12 76.2 MiB 0.62 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.38 -1 -1 76.2 MiB 0.26 0.230663 0.21125 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.71 vpr 106.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108596 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 106.1 MiB 14.09 0.02 9.2649 6.61089 -64.2928 -6.61089 nan 0.30 0.00665661 0.00535536 0.666172 0.560129 106.1 MiB 14.09 106.1 MiB 7.75 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.12 -1 -1 106.1 MiB 0.93 1.06756 0.920617 106.1 MiB -1 0.30 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.72 vpr 76.76 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78604 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.8 MiB 3.58 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00435878 0.0036697 0.124285 0.107404 76.8 MiB 3.58 76.8 MiB 2.26 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.35 -1 -1 76.8 MiB 0.48 0.351249 0.313025 76.8 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt index 6f5f90a4c3c..de30f274bbf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.30 vpr 74.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76280 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 9403 6159 8332 1169 4944 2219 74.5 MiB 2.02 0.01 6.38627 5.03307 -82.5272 -5.03307 nan 0.05 0.00186748 0.00147374 0.075299 0.0626077 74.5 MiB 2.02 74.5 MiB 1.33 10201 18.4801 2604 4.71739 4077 19753 686869 111324 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.47355 nan -88.2759 -5.47355 0 0 0.19 -1 -1 74.5 MiB 0.25 0.187127 0.162486 74.5 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.40 vpr 75.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77092 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 8563 7535 44489 711 9803 33975 75.3 MiB 0.67 0.01 6.75273 4.22233 -808.963 -4.22233 nan 0.07 0.00223446 0.00199382 0.0522672 0.0472954 75.3 MiB 0.67 75.3 MiB 0.37 10334 17.2809 2851 4.76756 2724 5860 351757 83165 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.44165 nan -865.851 -4.44165 0 0 0.21 -1 -1 75.3 MiB 0.18 0.157983 0.145454 75.3 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.43 vpr 103.27 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 294 10 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105744 10 10 2659 20 0 1271 314 22 22 484 -1 mcnc_large -1 -1 35357 24411 60010 16230 38382 5398 103.3 MiB 8.26 0.02 9.43184 6.46379 -62.5671 -6.46379 nan 0.17 0.00657205 0.00518572 0.421775 0.347051 103.3 MiB 8.26 103.3 MiB 4.34 37499 29.5035 9497 7.47207 8209 52283 2194356 288045 2.15576e+07 1.58448e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75089 nan -64.5268 -6.75089 0 0 0.63 -1 -1 103.3 MiB 0.89 0.808608 0.694348 103.3 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.22 vpr 75.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77184 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 10195 6390 9775 797 4761 4217 75.4 MiB 1.98 0.01 6.7004 4.74782 -144.082 -4.74782 nan 0.05 0.00198299 0.00156918 0.0659499 0.0554529 75.4 MiB 1.98 75.4 MiB 1.23 10367 18.2518 2719 4.78697 4167 22236 721470 123170 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.02595 nan -149.084 -5.02595 0 0 0.19 -1 -1 75.4 MiB 0.26 0.19016 0.165955 75.4 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.72 vpr 75.72 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77540 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.7 MiB 3.68 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.08 0.00350713 0.00300109 0.161716 0.138088 75.7 MiB 3.68 75.7 MiB 2.36 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.33 -1 -1 75.7 MiB 0.43 0.350348 0.308618 75.7 MiB -1 0.08 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.98 vpr 76.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77936 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.1 MiB 1.10 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.13 0.00370737 0.00330932 0.0842991 0.0760928 76.1 MiB 1.10 76.1 MiB 0.59 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.38 -1 -1 76.1 MiB 0.27 0.233583 0.214694 76.1 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.80 vpr 105.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108108 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 105.6 MiB 14.32 0.04 9.2649 6.61089 -64.2928 -6.61089 nan 0.28 0.0111602 0.00917763 0.734799 0.619682 105.6 MiB 14.32 105.6 MiB 7.72 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.18 -1 -1 105.6 MiB 1.46 1.37597 1.19895 105.6 MiB -1 0.28 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.61 vpr 76.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78480 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.6 MiB 3.50 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00396579 0.00332055 0.127703 0.110502 76.6 MiB 3.50 76.6 MiB 2.19 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.33 -1 -1 76.6 MiB 0.48 0.3515 0.312821 76.6 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index 26f3273119e..26aa2b1f6f2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.42 vpr 74.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76412 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 9403 6159 8332 1169 4944 2219 74.6 MiB 2.07 0.01 6.38627 5.03307 -82.5272 -5.03307 nan 0.05 0.00163693 0.00127812 0.0763521 0.063641 74.6 MiB 2.07 74.6 MiB 1.37 10201 18.4801 2604 4.71739 4077 19753 686869 111324 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.47355 nan -88.2759 -5.47355 0 0 0.19 -1 -1 74.6 MiB 0.25 0.188399 0.163633 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.42 vpr 75.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77344 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 8563 7535 44489 711 9803 33975 75.5 MiB 0.67 0.01 6.75273 4.22233 -808.963 -4.22233 nan 0.07 0.00198854 0.00175913 0.0485999 0.0437247 75.5 MiB 0.67 75.5 MiB 0.37 10334 17.2809 2851 4.76756 2724 5860 351757 83165 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.44165 nan -865.851 -4.44165 0 0 0.21 -1 -1 75.5 MiB 0.18 0.153989 0.141495 75.5 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.42 vpr 103.30 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 294 10 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105784 10 10 2659 20 0 1271 314 22 22 484 -1 mcnc_large -1 -1 35357 24411 60010 16230 38382 5398 103.3 MiB 8.23 0.02 9.43184 6.46379 -62.5671 -6.46379 nan 0.16 0.0063497 0.0050375 0.425885 0.351879 103.3 MiB 8.23 103.3 MiB 4.31 37499 29.5035 9497 7.47207 8209 52283 2194356 288045 2.15576e+07 1.58448e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.75089 nan -64.5268 -6.75089 0 0 0.64 -1 -1 103.3 MiB 0.84 0.793649 0.680537 103.3 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.29 vpr 75.68 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77496 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 10195 6390 9775 797 4761 4217 75.7 MiB 1.99 0.01 6.7004 4.74782 -144.082 -4.74782 nan 0.05 0.00234249 0.00188299 0.0692247 0.0585205 75.7 MiB 1.99 75.7 MiB 1.24 10367 18.2518 2719 4.78697 4167 22236 721470 123170 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.02595 nan -149.084 -5.02595 0 0 0.19 -1 -1 75.7 MiB 0.29 0.197995 0.173511 75.7 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.59 vpr 75.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77016 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 9742 6119 10249 1760 5821 2668 75.2 MiB 3.54 0.01 6.60912 5.26997 -81.789 -5.26997 nan 0.09 0.00354286 0.00301655 0.171129 0.146473 75.2 MiB 3.54 75.2 MiB 2.27 9723 17.3316 2505 4.46524 4006 19859 666446 110600 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.51321 nan -87.5291 -5.51321 0 0 0.35 -1 -1 75.2 MiB 0.43 0.36251 0.319941 75.2 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.99 vpr 75.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77788 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 8094 7501 39126 389 7567 31170 76.0 MiB 1.11 0.02 5.73036 4.09857 -784.452 -4.09857 nan 0.13 0.00368892 0.00328333 0.0831872 0.0750083 76.0 MiB 1.11 76.0 MiB 0.60 10270 17.6460 2810 4.82818 2238 5018 286471 63337 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.45761 nan -846.555 -4.45761 0 0 0.38 -1 -1 76.0 MiB 0.27 0.234296 0.215278 76.0 MiB -1 0.13 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.92 vpr 105.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 290 10 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 108468 10 10 2659 20 0 1285 310 22 22 484 -1 mcnc_large -1 -1 35642 24564 56902 15498 35924 5480 105.9 MiB 14.36 0.04 9.2649 6.61089 -64.2928 -6.61089 nan 0.28 0.0116327 0.00955067 0.723654 0.605356 105.9 MiB 14.36 105.9 MiB 7.81 37798 29.4148 9576 7.45214 8278 52602 2224659 293057 2.15576e+07 1.56293e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.83554 nan -66.0686 -6.83554 0 0 1.15 -1 -1 105.9 MiB 1.56 1.40718 1.22223 105.9 MiB -1 0.28 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.84 vpr 76.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78484 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 10490 6475 10406 884 4940 4582 76.6 MiB 3.62 0.01 6.29657 4.68967 -140.848 -4.68967 nan 0.09 0.00411942 0.00341582 0.129154 0.11135 76.6 MiB 3.62 76.6 MiB 2.26 10487 18.1436 2747 4.75259 4099 21208 684107 115230 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 18 28900 206586 -1 4.97595 nan -146.106 -4.97595 0 0 0.34 -1 -1 76.6 MiB 0.56 0.390736 0.347936 76.6 MiB -1 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt index 9bc3116c877..884cd26d780 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.91 vpr 74.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76164 9 19 897 28 0 553 108 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 74.4 MiB 1.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.4 MiB 1.81 74.4 MiB 1.37 13272 24.0435 3469 6.28442 3878 18598 715986 106519 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.45087 nan -103.767 -6.45087 0 0 0.19 -1 -1 74.4 MiB 0.26 0.112595 0.100491 74.4 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.97 vpr 75.29 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 256 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77096 256 245 954 501 0 598 561 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 0.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.3 MiB 0.42 75.3 MiB 0.38 11212 18.7492 3056 5.11037 2113 4530 278846 60151 2.15576e+07 3.23364e+06 1.49107e+06 3080.73 12 47664 245996 -1 6.64463 nan -975.374 -6.64463 0 0 0.21 -1 -1 75.3 MiB 0.14 0.084613 0.0790408 75.3 MiB -1 0.07 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.85 vpr 75.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12360-gc452b7d62-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T20:05:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77176 41 35 1006 76 0 568 161 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.4 MiB 1.71 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.4 MiB 1.71 75.4 MiB 1.21 14272 25.1268 3820 6.72535 3679 18279 692666 109920 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.47993 nan -177.198 -6.47993 0 0 0.19 -1 -1 75.4 MiB 0.27 0.123284 0.110324 75.4 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.09 vpr 75.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77668 9 19 897 28 0 562 109 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.8 MiB 2.98 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.8 MiB 2.98 75.8 MiB 2.29 13700 24.4207 3605 6.42602 3824 18535 740174 111014 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.68571 nan -104.773 -6.68571 0 0 0.32 -1 -1 75.8 MiB 0.43 0.182813 0.165173 75.8 MiB -1 0.09 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.72 vpr 76.20 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78028 256 245 954 501 0 582 553 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.68 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.2 MiB 0.68 76.2 MiB 0.60 10878 18.6907 2992 5.14089 2230 4782 309509 70390 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 15 47664 245996 -1 5.48159 nan -917.381 -5.48159 0 0 0.39 -1 -1 76.2 MiB 0.27 0.151724 0.140523 76.2 MiB -1 0.13 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.23 vpr 76.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12398-g63e0de52b-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-57-generic x86_64 2025-04-10T16:22:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78152 41 35 1006 76 0 578 158 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 76.3 MiB 2.99 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 76.3 MiB 2.99 76.3 MiB 2.17 15044 26.0277 4012 6.94118 4183 20973 821310 128455 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.07325 nan -173.533 -6.07325 0 0 0.35 -1 -1 76.3 MiB 0.49 0.206091 0.186137 76.3 MiB -1 0.09