Skip to content

[Place] Expand search range for sparse blocks #2960

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 47 commits into
base: master
Choose a base branch
from

Conversation

amin1377
Copy link
Contributor

@amin1377 amin1377 commented Apr 1, 2025

This PR addresses Issue #2959. The solution to fix the problem is a bit different from the one stated there, though. To ensure moving sparse blocks (e.g., IO blocks), we expand the search range to include the whole column if the number of compatible blocks in the given column is less than a certain threshold (currently, this number is set to 3)

The above update changed the placement of the top picture to the placement of the bottom one (where there is only one IO block left on the top).
Screenshot 2025-04-01 151404


Screenshot 2025-04-01 150305

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Apr 1, 2025
@amin1377 amin1377 requested a review from vaughnbetz April 1, 2025 19:37
Copy link
Contributor

@soheilshahrouz soheilshahrouz left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think the implementation can be made more modular by adding another function to modify the search limit instead of modifying when you're searching for a compatibale location.

@soheilshahrouz
Copy link
Contributor

Does the described problem happen only when IO blocks are located at the top/bottom rows? What if they are initially placed at left/right sides of the device?

@amin1377
Copy link
Contributor Author

amin1377 commented Apr 1, 2025

Does the described problem happen only when IO blocks are located at the top/bottom rows? What if they are initially placed at left/right sides of the device?

I'm not entirely sure, but given that the x-axis of the compressed grid is fully dense, I don't think this happens for the x-axis.

@amin1377
Copy link
Contributor Author

amin1377 commented Apr 2, 2025

Does the described problem happen only when IO blocks are located at the top/bottom rows? What if they are initially placed at left/right sides of the device?

I'm not entirely sure, but given that the x-axis of the compressed grid is fully dense, I don't think this happens for the x-axis.

Upon further discussion with @soheilshahrouz, it seems likely that the same issue occurs along the x-axis. So, it would make sense to expand the x-axis range limit if the number of compatible blocks in a given row falls below a certain threshold. Otherwise, there’s a bias toward placing IO blocks on the top and bottom edges rather than on the left and right.

I’ll look into this in a separate PR.

@tpagarani FYI

@amin1377
Copy link
Contributor Author

amin1377 commented Apr 3, 2025

@soheilshahrouz: I’ve addressed all your comments and implemented the changes you requested. Since the code has changed significantly since your last review, I’d appreciate it if you could take another look. Thanks!

@vaughnbetz
Copy link
Contributor

You should add QoR data on a couple of big benchmark suites.

@vaughnbetz
Copy link
Contributor

Also summarize the QoR-related regtest failrues (basic has two failing QoR, but it is because the wirelength improved a lot (45%) on two small circuits which is certainly fine!
I'd run at least one more benchmark suite if Titan shows some degradation, to see if it's real or not. We can accept a degradation and retune if needed but I'd like to understand it.

@vaughnbetz
Copy link
Contributor

Results on 3 seeds show the cpd degradation isn't consistent (the other 2 seeds were fine). I think this is good to merge. Can you also add a link to the 3 seed data here for posterity @amin1377 ?

@vaughnbetz
Copy link
Contributor

It looks like some golden results need to be updated. I looked at the parmys basic failure and it is a single small design that improved too much, so it's not a problem (actually it's good news):
[Fail]
k6_frac_N10_mem32K_40nm.xml/multiclock_separate_and_latch.v/common routed_wirelength relative value 0.4 outside of range [0.6,1.5], above absolute threshold 5.0 and not equal to golden value: 10.0

@vaughnbetz
Copy link
Contributor

vaughnbetz commented Apr 28, 2025 via email

@amin1377
Copy link
Contributor Author

@vaughnbetz
I tested five different seeds for both cases. With the changes in this branch, the IO blocks were placed close to each other in 3 out of 5 runs. After modifying the code to expand the search range only when the number of blocks in a column is less than 3, the IO blocks were placed close together in 1 out of 5 runs.

Unfortunately, I lost the S10 results due to some issues on Wintermute. I’m rerunning the benchmark now and will post the results as soon as they’re available.

@vaughnbetz
Copy link
Contributor

Thanks @amin1377 . Intriguing ... I would have thought the algorithms would be equivalent in that case.

@amin1377
Copy link
Contributor Author

Thanks @amin1377 . Intriguing ... I would have thought the algorithms would be equivalent in that case.

Yes, I’m also a bit surprised that the results aren’t consistent across different seeds with the current change. I’ll need to dig into it a bit more, but I think this highlights that adding those weak links you mentioned earlier is likely a more reliable approach than relying on simulated annealing to place IO blocks close to each other.

@amin1377
Copy link
Contributor Author

amin1377 commented May 1, 2025

Results on S10: [Link] Timing is basically tied (I also included the number of swaps and heap operations). Packing time increased by 10%, which I believe is due to machine load variation, as the packing code hasn’t changed in this PR. In terms of QoR, CPD increased by 1% while WL decreased by 1%.

Overall, the QoR is pretty much a tie, though I have to admit, I like the current code better since it’s cleaner... maybe I'm just a little biased :)

@amin1377
Copy link
Contributor Author

Titan results: Link

VTR results: Link

Copy link

@vaughnb-cerebras vaughnb-cerebras left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I have one minor feedback I think you can improve.
Other than that this is OK to merge.

@@ -19,6 +19,8 @@
//Note: The flag is only effective if compiled with VTR_ENABLE_DEBUG_LOGGING
bool f_placer_breakpoint_reached = false;

constexpr int MIN_NUMBER_OF_BLOCK_PER_COLUMN = 3;

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This needs a comment. Better name would be MIN_BLK_PER_COLUMN_EXPAND (or something like that). Current name makes it sound like we can't have fewer blocks than that in a column.
I also think this should be pushed down to the routine that uses it, if it is only used in one place.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Moved the variable to the routine and added the following comment:

// If the number of blocks in a column is less than this number, we 
// will expand the search range to the whole column

@amin1377
Copy link
Contributor Author

@vaughnbetz: I made a few changes since there were some outliers in Titan results (CPD for two circuits increased by about 20%). I am gathering QoR now after these changes.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
lang-cpp C/C++ code libarchfpga Library for handling FPGA Architecture descriptions VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants