diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst index 685db863924..7ca650a39c3 100644 --- a/doc/src/vpr/command_line_usage.rst +++ b/doc/src/vpr/command_line_usage.rst @@ -1195,15 +1195,43 @@ Analytical Placement is generally split into three stages: Analytical Placement is experimental and under active development. -.. option:: --ap_global_placer {quadratic-bipartitioning-lookahead | quadratic-flowbased-lookahead} +.. option:: --ap_analytical_solver {qp-hybrid | lp-b2b} - Controls which Global Placer to use in the AP Flow. + Controls which Analytical Solver the Global Placer will use in the AP Flow. + The Analytical Solver solves for a placement which optimizes some objective + function, ignorant of the FPGA legality constraints. This provides a "lower- + bound" solution. The Global Placer will legalize this solution and feed it + back to the analytical solver to make its solution more legal. - * ``quadratic-bipartitioning-lookahead`` Use a Global Placer which uses a quadratic solver and a bi-partitioning lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution. + * ``qp-hybrid`` Solves for a placement that minimizes the quadratic HPWL of + the flat placement using a hybrid clique/star net model (as described in + FastPlace :cite:`Viswanathan2005_FastPlace`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). - * ``quadratic-flowbased-lookahead`` Use a Global Placer which uses a quadratic solver and a multi-commodity-flow-based lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution. + * ``lp-b2b`` Solves for a placement that minimizes the linear HPWL of the + flat placement using the Bound2Bound net model (as described in Kraftwerk2 :cite:`Spindler2008_Kraftwerk2`). + Uses the legalized solution as anchor-points to pull the solution to a + more legal solution (similar to the approach from SimPL :cite:`Kim2013_SimPL`). - **Default:** ``quadratic-bipartitioning-lookahead`` + **Default:** ``qp-hybrid`` + +.. option:: --ap_partial_legalizer {bipartitioning | flow-based} + + Controls which Partial Legalizer the Global Placer will use in the AP Flow. + The Partial Legalizer legalizes a placement generated by an Analytical Solver. + It is used within the Global Placer to guide the solver to a more legal + solution. + + * ``bipartitioning`` Creates minimum windows around over-dense regions of + the device bi-partitions the atoms in these windows such that the region + is no longer over-dense and the atoms are in tiles that they can be placed + into. + + * ``flow-based`` Flows atoms from regions that are overfilled to regions that + are underfilled. + + **Default:** ``bipartitioning`` .. option:: --ap_full_legalizer {naive | appack} diff --git a/doc/src/z_references.bib b/doc/src/z_references.bib index 8822890713d..fc064f2c433 100644 --- a/doc/src/z_references.bib +++ b/doc/src/z_references.bib @@ -436,3 +436,46 @@ @inproceedings{kosar2024parallel booktitle={The 23rd International Conference on Field-Programmable Technology}, year={2024} } + +@ARTICLE{Viswanathan2005_FastPlace, + author={Viswanathan, N. and Chu, C.C.-N.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={{FastPlace}: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model}, + year={2005}, + volume={24}, + number={5}, + month=may, + pages={722-733}, + keywords={Clustering algorithms;Partitioning algorithms;Algorithm design and analysis;Integrated circuit interconnections;Large-scale systems;Minimization;Delay;Simulated annealing;Iterative algorithms;Acceleration;Analytical placement;computer-aided design;net models;standard cell placement}, + doi={10.1109/TCAD.2005.846365} +} + +@article{Kim2013_SimPL, + author = {Kim, Myung-Chul and Lee, Dong-Jin and Markov, Igor L.}, + journal = {Commun. ACM}, + title = {{SimPL}: an algorithm for placing {VLSI} circuits}, + year = {2013}, + issue_date = {June 2013}, + publisher = {Association for Computing Machinery}, + address = {New York, NY, USA}, + volume = {56}, + number = {6}, + issn = {0001-0782}, + doi = {10.1145/2461256.2461279}, + month = jun, + pages = {105–113}, + numpages = {9} +} + +@ARTICLE{Spindler2008_Kraftwerk2, + author={Spindler, Peter and Schlichtmann, Ulf and Johannes, Frank M.}, + journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + title={Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model}, + year={2008}, + volume={27}, + number={8}, + month=aug, + pages={1398-1411}, + keywords={Cost function;Central Processing Unit;Runtime;Quality control;Convergence;Computational efficiency;Integrated circuit synthesis;Stochastic processes;Circuit simulation;Bound2Bound;force-directed;half-perimeter wirelength (HPWL);Kraftwerk2;quadratic placement;Kraftwerk2;force-directed;quadratic placement;Bound2Bound;HPWL}, + doi={10.1109/TCAD.2008.925783} +} diff --git a/vpr/src/analytical_place/analytical_placement_flow.cpp b/vpr/src/analytical_place/analytical_placement_flow.cpp index 40e62fcf027..2007a15b199 100644 --- a/vpr/src/analytical_place/analytical_placement_flow.cpp +++ b/vpr/src/analytical_place/analytical_placement_flow.cpp @@ -131,7 +131,8 @@ static PartialPlacement run_global_placer(const t_ap_opts& ap_opts, return p_placement; } else { // Run the Global Placer - std::unique_ptr global_placer = make_global_placer(ap_opts.global_placer_type, + std::unique_ptr global_placer = make_global_placer(ap_opts.analytical_solver_type, + ap_opts.partial_legalizer_type, ap_netlist, prepacker, atom_nlist, diff --git a/vpr/src/analytical_place/analytical_solver.cpp b/vpr/src/analytical_place/analytical_solver.cpp index 60217dab2e3..030ecae0a4e 100644 --- a/vpr/src/analytical_place/analytical_solver.cpp +++ b/vpr/src/analytical_place/analytical_solver.cpp @@ -9,6 +9,7 @@ #include "analytical_solver.h" #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include "ap_netlist.h" #include "vpr_error.h" #include "vtr_assert.h" +#include "vtr_time.h" #include "vtr_vector.h" #ifdef EIGEN_INSTALLED @@ -37,20 +39,30 @@ #pragma GCC diagnostic pop #endif // EIGEN_INSTALLED -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, const APNetlist& netlist, - const DeviceGrid& device_grid) { + const DeviceGrid& device_grid, + int log_verbosity) { // Based on the solver type passed in, build the solver. switch (solver_type) { - case e_analytical_solver::QP_HYBRID: + case e_ap_analytical_solver::QP_Hybrid: #ifdef EIGEN_INSTALLED - return std::make_unique(netlist, device_grid); + return std::make_unique(netlist, device_grid, log_verbosity); #else (void)netlist; (void)device_grid; + (void)log_verbosity; VPR_FATAL_ERROR(VPR_ERROR_AP, "QP Hybrid Solver requires the Eigen library"); break; +#endif // EIGEN_INSTALLED + case e_ap_analytical_solver::LP_B2B: +#ifdef EIGEN_INSTALLED + return std::make_unique(netlist, device_grid, log_verbosity); +#else + VPR_FATAL_ERROR(VPR_ERROR_AP, + "LP B2B Solver requires the Eigen library"); + break; #endif // EIGEN_INSTALLED default: VPR_FATAL_ERROR(VPR_ERROR_AP, @@ -60,10 +72,11 @@ std::unique_ptr make_analytical_solver(e_analytical_solver sol return nullptr; } -AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist) +AnalyticalSolver::AnalyticalSolver(const APNetlist& netlist, int log_verbosity) : netlist_(netlist) , blk_id_to_row_id_(netlist.blocks().size(), APRowId::INVALID()) - , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) { + , row_id_to_blk_id_(netlist.blocks().size(), APBlockId::INVALID()) + , log_verbosity_(log_verbosity) { // Get the number of moveable blocks in the netlist and create a unique // row ID from [0, num_moveable_blocks) for each moveable block in the // netlist. @@ -335,8 +348,10 @@ void QPHybridSolver::solve(unsigned iteration, PartialPlacement& p_placement) { VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at compute!"); // Use the solver to solve for x and y using the constant vectors Eigen::VectorXd x = cg.solveWithGuess(b_x_diff, guess_x); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_x!"); Eigen::VectorXd y = cg.solveWithGuess(b_y_diff, guess_y); + total_num_cg_iters_ += cg.iterations(); VTR_ASSERT(cg.info() == Eigen::Success && "Conjugate Gradient failed at solving b_y!"); // Write the results back into the partial placement object. @@ -380,4 +395,368 @@ void QPHybridSolver::store_solution_into_placement(const Eigen::VectorXd& x_soln } } +void QPHybridSolver::print_statistics() { + VTR_LOG("QP-Hybrid Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); +} + +void B2BSolver::solve(unsigned iteration, PartialPlacement& p_placement) { + // Store an initial placement into the p_placement object as a starting point + // for the B2B solver. + if (iteration == 0) { + // In the first iteration, we have no prior information. + // Run the intial placer to get a first guess. + switch (initial_placement_ty_) { + case e_initial_placement_type::LeastDense: + initialize_placement_least_dense(p_placement); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_AP, "Unknown initial placement type"); + } + } else { + // After the first iteration, the prior solved solution will serve as + // the best starting points for the bounds. + + // Save the legalized solution; we need it for the anchors. + block_x_locs_legalized = p_placement.block_x_locs; + block_y_locs_legalized = p_placement.block_y_locs; + + // Store last solved position into p_placement for b2b model + p_placement.block_x_locs = block_x_locs_solved; + p_placement.block_y_locs = block_y_locs_solved; + } + + // Run the B2B solver using p_placement as a starting point. + b2b_solve_loop(iteration, p_placement); + + // Store the solved solutions for the next iteration. + block_x_locs_solved = p_placement.block_x_locs; + block_y_locs_solved = p_placement.block_y_locs; +} + +void B2BSolver::initialize_placement_least_dense(PartialPlacement& p_placement) { + // Find a gap for the blocks such that each block can fit onto the device + // if they were evenly spaced by this gap. + double gap = std::sqrt(device_grid_height_ * device_grid_width_ / static_cast(num_moveable_blocks_)); + + // Assuming this gap, get how many columns/rows of blocks there will be. + size_t cols = std::ceil(device_grid_width_ / gap); + size_t rows = std::ceil(device_grid_height_ / gap); + + // Spread the blocks at these grid coordinates. + for (size_t r = 0; r <= rows; r++) { + for (size_t c = 0; c <= cols; c++) { + size_t i = r * cols + c; + if (i >= num_moveable_blocks_) + break; + APRowId row_id = APRowId(i); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = c * gap; + p_placement.block_y_locs[blk_id] = r * gap; + } + } +} + +void B2BSolver::b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement) { + // Set up the guesses for x and y to help CG converge faster + // A good guess for B2B is the last solved solution. + Eigen::VectorXd x_guess(num_moveable_blocks_); + Eigen::VectorXd y_guess(num_moveable_blocks_); + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + x_guess(row_id_idx) = p_placement.block_x_locs[blk_id]; + y_guess(row_id_idx) = p_placement.block_y_locs[blk_id]; + } + + // Create a timer to keep track of how long each part of the solver take. + vtr::Timer runtime_timer; + + // To solve B2B, we need to do the following: + // 1) Set up the connectivity matrix and constant vectors based on the + // bounds of the current solution (stored in p_placement). + // 2) Solve the system of equations using CG and store the result into + // p_placement. + // 3) Repeat. Note: We need to repeat step 1 and 2 iteratively since + // the bounds are likely to have changed after step 2. + // TODO: As well as having a maximum number of bound updates, should also + // investigate stopping when the HPWL converges. + for (unsigned counter = 0; counter < max_num_bound_updates_; counter++) { + VTR_LOGV(log_verbosity_ >= 10, + "\tPlacement HPWL in b2b loop: %f\n", + p_placement.get_hpwl(netlist_)); + + // Set up the linear system, including anchor points. + float build_linear_system_start_time = runtime_timer.elapsed_sec(); + init_linear_system(p_placement); + if (iteration != 0) + update_linear_system_with_anchors(p_placement, iteration); + total_time_spent_building_linear_system_ += runtime_timer.elapsed_sec() - build_linear_system_start_time; + VTR_ASSERT_SAFE_MSG(!b_x.hasNaN(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG(!b_y.hasNaN(), "b_y has NaN!"); + VTR_ASSERT_SAFE_MSG((b_x.array() >= 0).all(), "b_x has NaN!"); + VTR_ASSERT_SAFE_MSG((b_y.array() >= 0).all(), "b_y has NaN!"); + + // Build the solvers for each dimension. + // Note: Since we have two different connectivity matrices, we need to + // different CG solver objects. + float solve_linear_system_start_time = runtime_timer.elapsed_sec(); + Eigen::VectorXd x, y; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_x; + Eigen::ConjugateGradient, Eigen::Lower | Eigen::Upper> cg_y; + cg_x.compute(A_sparse_x); + cg_y.compute(A_sparse_y); + VTR_ASSERT_SAFE_MSG(cg_x.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_x!"); + VTR_ASSERT_SAFE_MSG(cg_y.info() == Eigen::Success, "Conjugate Gradient failed at compute for A_y!"); + cg_x.setMaxIterations(max_cg_iterations_); + cg_y.setMaxIterations(max_cg_iterations_); + + // Solve the x dimension. + x = cg_x.solveWithGuess(b_x, x_guess); + total_num_cg_iters_ += cg_x.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-x iter: %zu\n", cg_x.iterations()); + + // Solve the y dimension. + y = cg_y.solveWithGuess(b_y, y_guess); + total_num_cg_iters_ += cg_y.iterations(); + VTR_LOGV(log_verbosity_ >= 20, "\t\tNum CG-y iter: %zu\n", cg_y.iterations()); + + total_time_spent_solving_linear_system_ += runtime_timer.elapsed_sec() - solve_linear_system_start_time; + + // Save the result into the partial placement object. + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + // Since we are capping the number of iterations, the solver may not + // have enough time to converge on a solution that is on the device. + // We just clamp the solution to zero for now. + // TODO: Should handle this better. If the solution is very negative + // it may indicate a bug. + if (x[row_id_idx] < 0.0) + x[row_id_idx] = 0.0; + if (y[row_id_idx] < 0.0) + y[row_id_idx] = 0.0; + + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + p_placement.block_x_locs[blk_id] = x[row_id_idx]; + p_placement.block_y_locs[blk_id] = y[row_id_idx]; + } + + // Update the guesses with the most recent answer + x_guess = x; + y_guess = y; + } +} + +namespace { +/** + * @brief Struct used to hold the bounding blocks of an AP net. + */ +struct APNetBounds { + /// @brief The leftmost block in the net. + APBlockId min_x_blk; + /// @brief The rightmost block in the net. + APBlockId max_x_blk; + /// @brief The bottom-most block in the net. + APBlockId min_y_blk; + /// @brief The top-most block in the net. + APBlockId max_y_blk; +}; + +} // namespace + +/** + * @brief Helper method to get the unique bounding blocks of a given net. + * + * In the B2B model, we do not want the same block to be the bounds in a given + * dimension. Therefore, if all blocks share the same x location for example, + * different bounds will be chosen for the x dimension. + */ +static inline APNetBounds get_unique_net_bounds(APNetId net_id, + const PartialPlacement& p_placement, + const APNetlist& netlist) { + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() != 0, + "Cannot get the bounds of an empty net"); + VTR_ASSERT_SAFE_MSG(netlist.net_pins(net_id).size() >= 2, + "Expect nets to have at least 2 pins"); + + APNetBounds bounds; + double max_x_pos = std::numeric_limits::lowest(); + double min_x_pos = std::numeric_limits::max(); + double max_y_pos = std::numeric_limits::lowest(); + double min_y_pos = std::numeric_limits::max(); + + for (APPinId pin_id : netlist.net_pins(net_id)) { + // Update the bounds based on the position of the block that has this pin. + APBlockId blk_id = netlist.pin_block(pin_id); + double x_pos = p_placement.block_x_locs[blk_id]; + double y_pos = p_placement.block_y_locs[blk_id]; + if (x_pos < min_x_pos) { + min_x_pos = x_pos; + bounds.min_x_blk = blk_id; + } + if (y_pos < min_y_pos) { + min_y_pos = y_pos; + bounds.min_y_blk = blk_id; + } + if (x_pos > max_x_pos) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos > max_y_pos) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + + // In the case of a tie, we do not want to have the same blocks as bounds. + // If there is a tie for the max position, and the current min bound is + // not this block, take the incoming block. + if (x_pos == max_x_pos && bounds.min_x_blk != blk_id) { + max_x_pos = x_pos; + bounds.max_x_blk = blk_id; + } + if (y_pos == max_y_pos && bounds.min_y_blk != blk_id) { + max_y_pos = y_pos; + bounds.max_y_blk = blk_id; + } + } + + // Ensure the same block is set as the bounds. + // If there is not a bug in the above code, then this could imply that a + // net only connects to a single APBlock, which does not make sense in this + // context. + VTR_ASSERT_SAFE(bounds.min_x_blk != bounds.max_x_blk); + VTR_ASSERT_SAFE(bounds.min_y_blk != bounds.max_y_blk); + + return bounds; +} + +void B2BSolver::add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b) { + // To make the code below simpler, we assume that the first block is always + // moveable. + if (netlist_.block_mobility(first_blk_id) != APBlockMobility::MOVEABLE) { + if (netlist_.block_mobility(second_blk_id) != APBlockMobility::MOVEABLE) { + // If both blocks are fixed, do not connect them. + return; + } + // If the first block is fixed and the second block is moveable, swap them. + std::swap(first_blk_id, second_blk_id); + } + + // Compute the weight of the connection. + // From the Kraftwerk2 paper: + // w = (2 / (P - 1)) * (1 / distance) + // + // epsilon is needed to prevent numerical instability. If two nodes are on top of each other. + // The denominator of weight is zero, which causes infinity term in the matrix. Another way of + // interpreting epsilon is the minimum distance two nodes are considered to be in placement. + double dist = std::max(std::abs(blk_locs[first_blk_id] - blk_locs[second_blk_id]), distance_epsilon_); + double w = (2.0 / static_cast(num_pins - 1)) * (1.0 / dist); + + // Update the connectivity matrix and the constant vector. + // This is similar to how connections are added for the quadratic formulation. + size_t first_row_id = (size_t)blk_id_to_row_id_[first_blk_id]; + if (netlist_.block_mobility(second_blk_id) == APBlockMobility::MOVEABLE) { + size_t second_row_id = (size_t)blk_id_to_row_id_[second_blk_id]; + triplet_list.emplace_back(first_row_id, first_row_id, w); + triplet_list.emplace_back(second_row_id, second_row_id, w); + triplet_list.emplace_back(first_row_id, second_row_id, -w); + triplet_list.emplace_back(second_row_id, first_row_id, -w); + } else { + triplet_list.emplace_back(first_row_id, first_row_id, w); + b(first_row_id) += w * blk_locs[second_blk_id]; + } +} + +void B2BSolver::init_linear_system(PartialPlacement& p_placement) { + // Reset the linear system + A_sparse_x = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + A_sparse_y = Eigen::SparseMatrix(num_moveable_blocks_, num_moveable_blocks_); + b_x = Eigen::VectorXd::Zero(num_moveable_blocks_); + b_y = Eigen::VectorXd::Zero(num_moveable_blocks_); + + // Create triplet lists to store the sparse positions to update and reserve + // space for them. + size_t num_nets = netlist_.nets().size(); + std::vector> triplet_list_x; + triplet_list_x.reserve(num_nets); + std::vector> triplet_list_y; + triplet_list_y.reserve(num_nets); + + for (APNetId net_id : netlist_.nets()) { + size_t num_pins = netlist_.net_pins(net_id).size(); + VTR_ASSERT_SAFE_MSG(num_pins > 1, "net must have at least 2 pins"); + + // Find the bounding blocks + APNetBounds net_bounds = get_unique_net_bounds(net_id, p_placement, netlist_); + + // Add an edge from every block to their bounds (ignoring the bounds + // themselves for now). + // FIXME: If one block has multiple pins, it may connect to the bounds + // multiple times. Should investigate the effect of this. + for (APPinId pin_id : netlist_.net_pins(net_id)) { + APBlockId blk_id = netlist_.pin_block(pin_id); + if (blk_id != net_bounds.max_x_blk && blk_id != net_bounds.min_x_blk) { + add_connection_to_system(blk_id, net_bounds.max_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(blk_id, net_bounds.min_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); + } + if (blk_id != net_bounds.max_y_blk && blk_id != net_bounds.min_y_blk) { + add_connection_to_system(blk_id, net_bounds.max_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); + add_connection_to_system(blk_id, net_bounds.min_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); + } + } + + // Connect the bounds to each other. Its just easier to put these here + // instead of in the for loop above. + add_connection_to_system(net_bounds.max_x_blk, net_bounds.min_x_blk, num_pins, p_placement.block_x_locs, triplet_list_x, b_x); + add_connection_to_system(net_bounds.max_y_blk, net_bounds.min_y_blk, num_pins, p_placement.block_y_locs, triplet_list_y, b_y); + } + + // Build the sparse connectivity matrices from the triplets. + A_sparse_x.setFromTriplets(triplet_list_x.begin(), triplet_list_x.end()); + A_sparse_y.setFromTriplets(triplet_list_y.begin(), triplet_list_y.end()); +} + +// This function adds anchors for legalized solution. Anchors are treated as fixed node, +// each connecting to a movable node. Number of nodes in a anchor net is always 2. +void B2BSolver::update_linear_system_with_anchors(PartialPlacement& p_placement, + unsigned iteration) { + VTR_ASSERT_SAFE_MSG(iteration != 0, + "no fixed solution to anchor to in the first iteration"); + // Get the anchor weight based on the iteration number. We want the anchor + // weights to get stronger as we get later in global placement. Found that + // an exponential weight term worked well for this. + double coeff_pseudo_anchor = anchor_weight_mult_ * std::exp((double)iteration / anchor_weight_exp_fac_); + + // Add an anchor for each moveable block to its solved position. + // Note: We treat anchors as being a 2-pin net between a moveable block + // and a fixed block where both are the bounds of the net. + for (size_t row_id_idx = 0; row_id_idx < num_moveable_blocks_; row_id_idx++) { + APRowId row_id = APRowId(row_id_idx); + APBlockId blk_id = row_id_to_blk_id_[row_id]; + double dx = std::abs(p_placement.block_x_locs[blk_id] - block_x_locs_legalized[blk_id]); + double dy = std::abs(p_placement.block_y_locs[blk_id] - block_y_locs_legalized[blk_id]); + // Anchor node are always 2 pins. + double pseudo_w_x = coeff_pseudo_anchor * 2.0 / std::max(dx, distance_epsilon_); + double pseudo_w_y = coeff_pseudo_anchor * 2.0 / std::max(dy, distance_epsilon_); + A_sparse_x.coeffRef(row_id_idx, row_id_idx) += pseudo_w_x; + A_sparse_y.coeffRef(row_id_idx, row_id_idx) += pseudo_w_y; + b_x(row_id_idx) += pseudo_w_x * block_x_locs_legalized[blk_id]; + b_y(row_id_idx) += pseudo_w_y * block_y_locs_legalized[blk_id]; + } +} + +void B2BSolver::print_statistics() { + VTR_LOG("B2B Solver Statistics:\n"); + VTR_LOG("\tTotal number of CG iterations: %u\n", total_num_cg_iters_); + VTR_LOG("\tTotal time spent building linear system: %g seconds\n", + total_time_spent_building_linear_system_); + VTR_LOG("\tTotal time spent solving linear system: %g seconds\n", + total_time_spent_solving_linear_system_); +} + #endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/analytical_solver.h b/vpr/src/analytical_place/analytical_solver.h index dee0eb4674a..a5f48e892c2 100644 --- a/vpr/src/analytical_place/analytical_solver.h +++ b/vpr/src/analytical_place/analytical_solver.h @@ -9,6 +9,7 @@ #pragma once #include +#include "ap_flow_enums.h" #include "ap_netlist.h" #include "device_grid.h" #include "vtr_strong_id.h" @@ -31,15 +32,6 @@ class PartialPlacement; class APNetlist; -/** - * @brief Enumeration of all of the solvers currently implemented in VPR. - * - * NOTE: More are coming. - */ -enum class e_analytical_solver { - QP_HYBRID // A solver which optimizes the quadratic HPWL of the design. -}; - /** * @brief A strong ID for the rows in a matrix used during solving. * @@ -68,7 +60,7 @@ class AnalyticalSolver { * Initializes the internal data members of the base class which are useful * for all solvers. */ - AnalyticalSolver(const APNetlist& netlist); + AnalyticalSolver(const APNetlist& netlist, int log_verbosity); /** * @brief Run an iteration of the solver using the given partial placement @@ -90,6 +82,14 @@ class AnalyticalSolver { */ virtual void solve(unsigned iteration, PartialPlacement& p_placement) = 0; + /** + * @brief Print statistics on the analytical solver. + * + * This is expected to be called after global placement to collect cummulative + * information on how the solver performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the solver is optimizing over. It is implied that /// the netlist is not being modified during global placement. @@ -112,14 +112,18 @@ class AnalyticalSolver { /// APBlock it represents. useful when getting the results from the /// solver. vtr::vector row_id_to_blk_id_; + + /// @brief The verbosity of log messages in the Analytical Solver. + int log_verbosity_; }; /** * @brief A factory method which creates an Analytical Solver of the given type. */ -std::unique_ptr make_analytical_solver(e_analytical_solver solver_type, +std::unique_ptr make_analytical_solver(e_ap_analytical_solver solver_type, const APNetlist& netlist, - const DeviceGrid& device_grid); + const DeviceGrid& device_grid, + int log_verbosity); // The Eigen library is used to solve matrix equations in the following solvers. // The solver cannot be built if Eigen is not installed. @@ -263,14 +267,19 @@ class QPHybridSolver : public AnalyticalSolver { /// @brief The current guess for the y positions of the blocks. Eigen::VectorXd guess_y; + /// @brief The total number of CG iterations this solver has performed so far. + unsigned total_num_cg_iters_ = 0; + public: /** * @brief Constructor of the QPHybridSolver * * Initializes internal data and constructs the initial linear system. */ - QPHybridSolver(const APNetlist& netlist, const DeviceGrid& device_grid) - : AnalyticalSolver(netlist) { + QPHybridSolver(const APNetlist& netlist, + const DeviceGrid& device_grid, + int log_verbosity) + : AnalyticalSolver(netlist, log_verbosity) { // Initializing the linear system only depends on the netlist and fixed // block locations. Both are provided by the netlist, allowing this to // be initialized in the constructor. @@ -301,6 +310,258 @@ class QPHybridSolver : public AnalyticalSolver { * this object. */ void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print statistics of the solver. + */ + void print_statistics() final; +}; + +/** + * @brief An Analytical Solver which tries to minimize the linear HPWL objective: + * SUM((xmax - xmin) + (ymax - ymin)) over all nets. + * + * This is implemented using the Bound2Bound method, which iteratively sets up a + * linear system of equations (similar to the QP Hybrid approach above) which + * solves a quadratic objective function. For a net model, each block connects + * to the current bounding blocks in the given dimension and the weight of this + * connection is inversly proportional to the distance of the block to the bound. + * After minimizing this system, the bounds are likely to change; so the system + * needs to be reconstructed and solved iteratively. + * + * This technique was proposed in Kraftwerk2, where they proved that the B2B Net + * Model will, in theory, converge on the linear HPWL solution. + * https://doi.org/10.1109/TCAD.2008.925783 + */ +class B2BSolver : public AnalyticalSolver { + private: + /** + * @brief Enumeration for different initial placements that this class can + * perform in the first iteration. + * + * TODO: Investigate other initial placement techniques, the first iteration + * can be very expensive. + */ + enum class e_initial_placement_type { + LeastDense //< Randomly place blocks as a uniform grid over the device. + }; + + /// @brief Which initial placement algorithm to use in the first iteration. + /// In the first iteration, we need some solution to initialize the + /// bounds. Some papers have found that setting it to a random + /// initial placement is the best approach. + static constexpr e_initial_placement_type initial_placement_ty_ = e_initial_placement_type::LeastDense; + + /// @brief Since the weights in the B2B model divide by the distance between + /// blocks and their bounds, that distance may get very very close to + /// 0. This causes the weight matrix to become numerically unstable. + /// We can gaurd against this by clamping the distance to not be smaller + /// than some epsilon. + /// Decreasing this number may lead to more instability, but can yield + /// a higher quality solution. + static constexpr double distance_epsilon_ = 0.5; + + /// @brief Max number of bound update / solve iterations. Increasing this + /// number will yield better quality at the expense of runtime. + static constexpr unsigned max_num_bound_updates_ = 6; + + /// @brief Max number of iterations the Conjugate Gradient solver can perform. + /// Due to the weights getting very large in the early iterations of + /// Global Placement, the CG solver may take a very long time to + /// converge; but the solution quality will not change much. By + /// default the max iteration is set to 2 * num_moveable_blocks; + /// which causes the first iteration of B2B to become quadratic in the + /// number of moveable blocks if it cannot converge. Found through + /// experimentation that this can be clamped to a much smaller number + /// to prevent this behaviour and get good runtime. + // TODO: Need to investigate this more to find a good number for this. + // TODO: Should this be a proportion of the design size? + static constexpr unsigned max_cg_iterations_ = 200; + + // The following constants are used to configure the anchor weighting. + // The weights of anchors grow exponentially each iteration by the following + // function: + // anchor_w = anchor_weight_mult_ * e^(iter / anchor_weight_exp_fac_) + // The numbers below were empircally found to work well. + + /// @brief Multiplier for the anchorweight. The smaller this number is, the + /// weaker the anchors will be at the start. + static constexpr double anchor_weight_mult_ = 0.01; + + /// @brief Factor for controlling the growth of the exponential term in the + /// weight factor function. Larger numbers will cause the anchor + /// weights to grow slower. + static constexpr double anchor_weight_exp_fac_ = 5.0; + + public: + B2BSolver(const APNetlist& ap_netlist, + const DeviceGrid& device_grid, + int log_verbosity) + : AnalyticalSolver(ap_netlist, log_verbosity) + , device_grid_width_(device_grid.width()) + , device_grid_height_(device_grid.height()) {} + + /** + * @brief Perform an iteration of the B2B solver, storing the result into + * the partial placement object passed in. + * + * In the first iteration (iteration = 0), the partial placement object will + * be ignored, and a random initial placement will be used to initially + * construct the system of equations. In all other iterations, the previous + * solved solution will be used. + * + * The B2B solver will then iteratively solve the system of equations and + * update the system to achieve a good HPWL solution which is close to the + * linear HPWL solution. Due to numerical issues with this algorithm, we will + * likely not converge on the true minimum HPWL solution, but it should be + * close. + * + * See the base class for more information. + * + * @param iteration + * The current iteration of the Global Placer + * @param p_placement + * A "guess" solution. The result will be written into this object. + * In all iterations other than the first, this solution will be used + * as anchor-points in the system. + */ + void solve(unsigned iteration, PartialPlacement& p_placement) final; + + /** + * @brief Print overall statistics on this solver. + * + * This is expected to be called after all iterations of Global Placement + * has been complete. + */ + void print_statistics() final; + + private: + /** + * @brief Run the B2B outer solving loop. + * + * The placement in p_placement should be initialized with the initial + * positions of the blocks that the B2B algorithm should use to build the + * first system of equations. This placement will be iteratively updated + * with better and better solutions as B2B iterates. + * + * If iteration is 0, no anchor-blocks will be added to the system, otherwise + * the solution in block_locs_legalized will be used as anchor-blocks. + */ + void b2b_solve_loop(unsigned iteration, PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a normal distribution. + */ + void initialize_placement_random_normal(PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using a uniform distribution. + */ + void initialize_placement_random_uniform(PartialPlacement& p_placement); + + /** + * @brief Randomly distributes AP blocks using as a uniform grid. + */ + void initialize_placement_least_dense(PartialPlacement& p_placement); + + /** + * @brief Add a weighted connection to the linear system between the first + * and second blocks for a single dimension. + * + * This method is used to construct different linear systems for different + * dimensions (x and y). Since the act of adding weighted connections is the + * same regardless of dimension, this method passes in dimension-specific + * information to be updated. + * + * @param first_blk_id + * @param second_blk_id + * @param num_pins + * The number of pins in the hypernet connecting the two blocks. + * @param blk_locs + * The location of all blocks in a given dimension. + * @param triplet_list + * The triplet list which will be used to construct the connectivity + * matrix for this dimension. + * @param b + * The constant vector for this dimension. + */ + void add_connection_to_system(APBlockId first_blk_id, + APBlockId second_blk_id, + size_t num_pins, + const vtr::vector& blk_locs, + std::vector>& triplet_list, + Eigen::VectorXd& b); + + /** + * @brief Initializes the linear system with the given partial placement. + * + * Blocks will be connected to the bounding blocks of their nets using + * weighted connections, with weight inversly proportional to the distance + * between blocks and the bounds. When solved in a quadratic equation this + * approximates a linear equation. + * + * This will set the connectivity matrices (A) and constant vectors (b) to + * be solved by B2B. + */ + void init_linear_system(PartialPlacement& p_placement); + + /** + * @brief Updates the linear system with anchor-blocks from the legalized + * solution. + */ + void update_linear_system_with_anchors(PartialPlacement& p_placement, + unsigned iteration); + + // The following are variables used to store the system of equations to be + // solved in the x and y dimensions. The equations are of the form: + // Ax = b + // There are two sets of matrices and vectors since the x and y dimensions + // of the objective are independent and can be solved separately. + // These are updated each iteration of the B2B loop. + + /// @brief The coefficient / connectivity matrix for the x dimension. + Eigen::SparseMatrix A_sparse_x; + /// @brief The coefficient / connectivity matrix for the y dimension. + Eigen::SparseMatrix A_sparse_y; + /// @brief The constant vector in the x dimension. + Eigen::VectorXd b_x; + /// @brief The constant vector in the y dimension. + Eigen::VectorXd b_y; + + // The following is the solution of the previous iteration of this solver. + // They are updated at the end of solve() and are used as the starting point + // for the next call to solve. + vtr::vector block_x_locs_solved; + vtr::vector block_y_locs_solved; + + // The following are the legalized solution coming into the analytical solver + // (other than the first iteration). These are stored to be used as anchor + // blocks during the solver. + vtr::vector block_x_locs_legalized; + vtr::vector block_y_locs_legalized; + + /// @brief The width of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_width_; + /// @brief The height of the device grid. Used for randomly generating points + /// on the grid. + size_t device_grid_height_; + + /// @brief The total number of CG iterations that this solver has performed + /// so far. This can be a useful metric for the amount of work the + /// solver performs. + unsigned total_num_cg_iters_ = 0; + + /// @brief The total time spent building the linear systems in the B2B solve + /// loop so far. This includes creating connections between blocks + /// in the connectivity matrix and constant vector as well as adding + /// anchor connections. + float total_time_spent_building_linear_system_ = 0.0f; + + /// @brief The total time spent solving the linear systems in the B2B solve + /// loop so far. This includes creating the CG solver object and + /// actually solving for a solution. + float total_time_spent_solving_linear_system_ = 0.0f; }; #endif // EIGEN_INSTALLED diff --git a/vpr/src/analytical_place/ap_flow_enums.h b/vpr/src/analytical_place/ap_flow_enums.h index 6d925e61e47..91c1407059d 100644 --- a/vpr/src/analytical_place/ap_flow_enums.h +++ b/vpr/src/analytical_place/ap_flow_enums.h @@ -8,15 +8,27 @@ #pragma once /** - * @brief The type of a Global Placer. + * @brief The type of an Analytical Solver. * - * The Analytical Placement flow may implement different Global Placers. This - * enum can select between these different Global Placers. + * The Analytical Placement flow may implement different Analytical Solvers as + * part of the Global Placer. This enum can select between these different + * Analytical Solvers. */ -enum class e_ap_global_placer { - // Global placers based on the the SimPL paper. - SimPL_BiParitioning, ///< Global Placer based on the SimPL technique to Global Placement. Uses a quadratic solver and a bi-partitioning Partial Legalizer. - SimPL_FlowBased ///< Global Placer based on the SimPL technique to Global Placement. Uses a quadratic solver and a multi-commodity-flow-baed Partial Legalizer. +enum class e_ap_analytical_solver { + QP_Hybrid, ///< Analytical Solver which uses the hybrid net model to optimize the quadratic HPWL objective. + LP_B2B ///< Analytical Solver which uses the B2B net model to optimize the linear HPWL objective. +}; + +/** + * @brief The type of a Partial Legalizer. + * + * The Analytical Placement flow may implement different Partial Legalizer as + * part of the Global Placer. This enum can select between these different + * Partial Legalizers. + */ +enum class e_ap_partial_legalizer { + BiPartitioning, ///< Partial Legalizer which forms minimum windows around dense regions and uses bipartitioning to spread blocks over windows. + FlowBased ///> Partial Legalizer which flows blocks from overfilled bins to underfilled bins. }; /** diff --git a/vpr/src/analytical_place/global_placer.cpp b/vpr/src/analytical_place/global_placer.cpp index a89a1fb8ef4..5707f6d4708 100644 --- a/vpr/src/analytical_place/global_placer.cpp +++ b/vpr/src/analytical_place/global_placer.cpp @@ -23,11 +23,11 @@ #include "partial_placement.h" #include "physical_types.h" #include "primitive_vector.h" -#include "vpr_error.h" #include "vtr_log.h" #include "vtr_time.h" -std::unique_ptr make_global_placer(e_ap_global_placer placer_type, +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, const APNetlist& ap_netlist, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -35,33 +35,19 @@ std::unique_ptr make_global_placer(e_ap_global_placer placer_type, const std::vector& logical_block_types, const std::vector& physical_tile_types, int log_verbosity) { - // Based on the placer type passed in, build the global placer. - switch (placer_type) { - case e_ap_global_placer::SimPL_BiParitioning: - return std::make_unique(e_partial_legalizer::BI_PARTITIONING, - ap_netlist, - prepacker, - atom_netlist, - device_grid, - logical_block_types, - physical_tile_types, - log_verbosity); - case e_ap_global_placer::SimPL_FlowBased: - return std::make_unique(e_partial_legalizer::FLOW_BASED, - ap_netlist, - prepacker, - atom_netlist, - device_grid, - logical_block_types, - physical_tile_types, - log_verbosity); - default: - VPR_FATAL_ERROR(VPR_ERROR_AP, - "Unrecognized global placer type"); - } + return std::make_unique(analytical_solver_type, + partial_legalizer_type, + ap_netlist, + prepacker, + atom_netlist, + device_grid, + logical_block_types, + physical_tile_types, + log_verbosity); } -SimPLGlobalPlacer::SimPLGlobalPlacer(e_partial_legalizer partial_legalizer_type, +SimPLGlobalPlacer::SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, const APNetlist& ap_netlist, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -76,9 +62,10 @@ SimPLGlobalPlacer::SimPLGlobalPlacer(e_partial_legalizer partial_legalizer_type, // Build the solver. VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the solver...\n"); - solver_ = make_analytical_solver(e_analytical_solver::QP_HYBRID, + solver_ = make_analytical_solver(analytical_solver_type, ap_netlist_, - device_grid); + device_grid, + log_verbosity_); // Build the density manager used by the partial legalizer. VTR_LOGV(log_verbosity_ >= 10, "\tBuilding the density manager...\n"); @@ -216,6 +203,10 @@ PartialPlacement SimPLGlobalPlacer::place() { print_SimPL_status_header(); // Initialialize the partial placement object. PartialPlacement p_placement(ap_netlist_); + + float total_time_spent_in_solver = 0.0f; + float total_time_spent_in_legalizer = 0.0f; + // Run the global placer. for (size_t i = 0; i < max_num_iterations_; i++) { float iter_start_time = runtime_timer.elapsed_sec(); @@ -232,6 +223,9 @@ PartialPlacement SimPLGlobalPlacer::place() { float legalizer_end_time = runtime_timer.elapsed_sec(); double ub_hpwl = p_placement.get_hpwl(ap_netlist_); + total_time_spent_in_solver += solver_end_time - solver_start_time; + total_time_spent_in_legalizer += legalizer_end_time - legalizer_start_time; + // Print some stats if (log_verbosity_ >= 1) { float iter_end_time = runtime_timer.elapsed_sec(); @@ -248,6 +242,16 @@ PartialPlacement SimPLGlobalPlacer::place() { break; } + // Print statistics on the solver used. + solver_->print_statistics(); + + // Print statistics on the partial legalizer used. + partial_legalizer_->print_statistics(); + + VTR_LOG("Global Placer Statistics:\n"); + VTR_LOG("\tTime spent in solver: %g seconds\n", total_time_spent_in_solver); + VTR_LOG("\tTime spent in legalizer: %g seconds\n", total_time_spent_in_legalizer); + // Print some statistics on the final placement. VTR_LOG("Placement after Global Placement:\n"); print_placement_stats(p_placement, diff --git a/vpr/src/analytical_place/global_placer.h b/vpr/src/analytical_place/global_placer.h index 196de86220c..94f68e260f9 100644 --- a/vpr/src/analytical_place/global_placer.h +++ b/vpr/src/analytical_place/global_placer.h @@ -72,7 +72,8 @@ class GlobalPlacer { /** * @brief A factory method which creates a Global Placer of the given type. */ -std::unique_ptr make_global_placer(e_ap_global_placer placer_type, +std::unique_ptr make_global_placer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, const APNetlist& ap_netlist, const Prepacker& prepacker, const AtomNetlist& atom_netlist, @@ -134,7 +135,8 @@ class SimPLGlobalPlacer : public GlobalPlacer { * * Constructs the solver and partial legalizer. */ - SimPLGlobalPlacer(e_partial_legalizer partial_legalizer_type, + SimPLGlobalPlacer(e_ap_analytical_solver analytical_solver_type, + e_ap_partial_legalizer partial_legalizer_type, const APNetlist& ap_netlist, const Prepacker& prepacker, const AtomNetlist& atom_netlist, diff --git a/vpr/src/analytical_place/partial_legalizer.cpp b/vpr/src/analytical_place/partial_legalizer.cpp index 3d5d8dd25e9..5cadbf8683e 100644 --- a/vpr/src/analytical_place/partial_legalizer.cpp +++ b/vpr/src/analytical_place/partial_legalizer.cpp @@ -42,18 +42,18 @@ #include "vtr_vector.h" #include "vtr_vector_map.h" -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, int log_verbosity) { // Based on the partial legalizer type passed in, build the partial legalizer. switch (legalizer_type) { - case e_partial_legalizer::FLOW_BASED: + case e_ap_partial_legalizer::FlowBased: return std::make_unique(netlist, density_manager, log_verbosity); - case e_partial_legalizer::BI_PARTITIONING: + case e_ap_partial_legalizer::BiPartitioning: return std::make_unique(netlist, density_manager, prepacker, @@ -787,6 +787,15 @@ BiPartitioningPartialLegalizer::BiPartitioningPartialLegalizer( VTR_ASSERT_SAFE(!vtr::isclose(bin_area, 0.f)); return cap / bin_area; }); + + num_windows_partitioned_ = 0; + num_blocks_partitioned_ = 0; +} + +void BiPartitioningPartialLegalizer::print_statistics() { + VTR_LOG("Bi-Partitioning Partial Legalizer Statistics:\n"); + VTR_LOG("\tTotal number of windows partitioned: %u\n", num_windows_partitioned_); + VTR_LOG("\tTotal number of blocks partitioned: %u\n", num_blocks_partitioned_); } void BiPartitioningPartialLegalizer::legalize(PartialPlacement& p_placement) { @@ -1258,6 +1267,9 @@ void BiPartitioningPartialLegalizer::spread_over_windows(std::vector #include #include "ap_netlist_fwd.h" +#include "ap_flow_enums.h" #include "flat_placement_bins.h" #include "flat_placement_density_manager.h" #include "model_grouper.h" @@ -30,15 +31,6 @@ class APNetlist; class Prepacker; struct PartialPlacement; -/** - * @brief Enumeration of all of the partial legalizers currently implemented in - * VPR. - */ -enum class e_partial_legalizer { - FLOW_BASED, // Multi-commodity flow-based partial legalizer. - BI_PARTITIONING // Bi-partitioning partial legalizer. -}; - /** * @brief The Partial Legalizer base class * @@ -76,6 +68,14 @@ class PartialLegalizer { */ virtual void legalize(PartialPlacement& p_placement) = 0; + /** + * @brief Print statistics on the Partial Legalizer. + * + * This is expected to be called at the end of Global Placement to provide + * cummulative information on how much work the partial legalizer performed. + */ + virtual void print_statistics() = 0; + protected: /// @brief The APNetlist the legalizer will be legalizing the placement of. /// It is implied that the netlist is not being modified during @@ -91,7 +91,7 @@ class PartialLegalizer { /** * @brief A factory method which creates a Partial Legalizer of the given type. */ -std::unique_ptr make_partial_legalizer(e_partial_legalizer legalizer_type, +std::unique_ptr make_partial_legalizer(e_ap_partial_legalizer legalizer_type, const APNetlist& netlist, std::shared_ptr density_manager, const Prepacker& prepacker, @@ -243,6 +243,8 @@ class FlowBasedLegalizer : public PartialLegalizer { * legalizer will be stored in this object. */ void legalize(PartialPlacement& p_placement) final; + + void print_statistics() final {} }; /** @@ -388,6 +390,11 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { */ void legalize(PartialPlacement& p_placement) final; + /** + * @brief Print statistics on the BiPartitioning Partial Legalizer. + */ + void print_statistics() final; + private: // ======================================================================== // Identifying spreading windows @@ -514,4 +521,11 @@ class BiPartitioningPartialLegalizer : public PartialLegalizer { /// /// This is populated in the constructor and not modified. PerModelPrefixSum2D capacity_prefix_sum_; + + /// @brief The number of times a window was partitioned in the legalizer. + unsigned num_windows_partitioned_ = 0; + + /// @brief The number of times a block was partitioned from one window into + /// another. This includes blocks which get partitioned multiple times. + unsigned num_blocks_partitioned_ = 0; }; diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 9cdfc5c5ef8..eb9af5943ad 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -547,7 +547,8 @@ static void SetupAnnealSched(const t_options& Options, */ void SetupAPOpts(const t_options& options, t_ap_opts& apOpts) { - apOpts.global_placer_type = options.ap_global_placer.value(); + apOpts.analytical_solver_type = options.ap_analytical_solver.value(); + apOpts.partial_legalizer_type = options.ap_partial_legalizer.value(); apOpts.full_legalizer_type = options.ap_full_legalizer.value(); apOpts.detailed_placer_type = options.ap_detailed_placer.value(); apOpts.log_verbosity = options.ap_verbosity.value(); diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 1524af7ed83..b1de3da9729 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -598,16 +598,28 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts) { } static void ShowAnalyticalPlacerOpts(const t_ap_opts& APOpts) { - VTR_LOG("AnalyticalPlacerOpts.global_placer_type: "); - switch (APOpts.global_placer_type) { - case e_ap_global_placer::SimPL_BiParitioning: - VTR_LOG("quadratic-bipartitioning-lookahead\n"); + VTR_LOG("AnalyticalPlacerOpts.analytical_solver_type: "); + switch (APOpts.analytical_solver_type) { + case e_ap_analytical_solver::QP_Hybrid: + VTR_LOG("qp-hybrid\n"); break; - case e_ap_global_placer::SimPL_FlowBased: - VTR_LOG("quadratic-flowbased-lookahead\n"); + case e_ap_analytical_solver::LP_B2B: + VTR_LOG("lp-b2b\n"); break; default: - VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown global_placer_type\n"); + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown analytical_solver_type\n"); + } + + VTR_LOG("AnalyticalPlacerOpts.partial_legalizer_type: "); + switch (APOpts.partial_legalizer_type) { + case e_ap_partial_legalizer::BiPartitioning: + VTR_LOG("bipartitioning\n"); + break; + case e_ap_partial_legalizer::FlowBased: + VTR_LOG("flow-based\n"); + break; + default: + VPR_FATAL_ERROR(VPR_ERROR_UNKNOWN, "Unknown partial_legalizer_type\n"); } VTR_LOG("AnalyticalPlacerOpts.full_legalizer_type: "); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 3e51cf887ff..23f3ba833bd 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -134,29 +134,29 @@ struct ParseCircuitFormat { } }; -struct ParseAPGlobalPlacer { - ConvertedValue from_str(const std::string& str) { - ConvertedValue conv_value; - if (str == "quadratic-bipartitioning-lookahead") - conv_value.set_value(e_ap_global_placer::SimPL_BiParitioning); - else if (str == "quadratic-flowbased-lookahead") - conv_value.set_value(e_ap_global_placer::SimPL_FlowBased); +struct ParseAPAnalyticalSolver { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "qp-hybrid") + conv_value.set_value(e_ap_analytical_solver::QP_Hybrid); + else if (str == "lp-b2b") + conv_value.set_value(e_ap_analytical_solver::LP_B2B); else { std::stringstream msg; - msg << "Invalid conversion from '" << str << "' to e_ap_global_placer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + msg << "Invalid conversion from '" << str << "' to e_ap_analytical_solver (expected one of: " << argparse::join(default_choices(), ", ") << ")"; conv_value.set_error(msg.str()); } return conv_value; } - ConvertedValue to_str(e_ap_global_placer val) { + ConvertedValue to_str(e_ap_analytical_solver val) { ConvertedValue conv_value; switch (val) { - case e_ap_global_placer::SimPL_BiParitioning: - conv_value.set_value("quadratic-bipartitioning-lookahead"); + case e_ap_analytical_solver::QP_Hybrid: + conv_value.set_value("qp-hybrid"); break; - case e_ap_global_placer::SimPL_FlowBased: - conv_value.set_value("quadratic-flowbased-lookahead"); + case e_ap_analytical_solver::LP_B2B: + conv_value.set_value("lp-b2b"); break; default: VTR_ASSERT(false); @@ -165,7 +165,42 @@ struct ParseAPGlobalPlacer { } std::vector default_choices() { - return {"quadratic-bipartitioning-lookahead", "quadratic-flowbased-lookahead"}; + return {"qp-hybrid", "lp-b2b"}; + } +}; + +struct ParseAPPartialLegalizer { + ConvertedValue from_str(const std::string& str) { + ConvertedValue conv_value; + if (str == "bipartitioning") + conv_value.set_value(e_ap_partial_legalizer::BiPartitioning); + else if (str == "flow-based") + conv_value.set_value(e_ap_partial_legalizer::FlowBased); + else { + std::stringstream msg; + msg << "Invalid conversion from '" << str << "' to e_ap_partial_legalizer (expected one of: " << argparse::join(default_choices(), ", ") << ")"; + conv_value.set_error(msg.str()); + } + return conv_value; + } + + ConvertedValue to_str(e_ap_partial_legalizer val) { + ConvertedValue conv_value; + switch (val) { + case e_ap_partial_legalizer::BiPartitioning: + conv_value.set_value("bipartitioning"); + break; + case e_ap_partial_legalizer::FlowBased: + conv_value.set_value("flow-based"); + break; + default: + VTR_ASSERT(false); + } + return conv_value; + } + + std::vector default_choices() { + return {"bipartitioning", "flow-based"}; } }; @@ -1863,12 +1898,20 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio auto& ap_grp = parser.add_argument_group("analytical placement options"); - ap_grp.add_argument(args.ap_global_placer, "--ap_global_placer") + ap_grp.add_argument(args.ap_analytical_solver, "--ap_analytical_solver") + .help( + "Controls which Analytical Solver the Global Placer will use in the AP Flow.\n" + " * qp-hybrid: olves for a placement that minimizes the quadratic HPWL of the flat placement using a hybrid clique/star net model.\n" + " * lp-b2b: Solves for a placement that minimizes the linear HPWL of theflat placement using the Bound2Bound net model.") + .default_value("qp-hybrid") + .show_in(argparse::ShowIn::HELP_ONLY); + + ap_grp.add_argument(args.ap_partial_legalizer, "--ap_partial_legalizer") .help( - "Controls which Global Placer to use in the AP Flow.\n" - " * quadratic-bipartitioning-lookahead: Use a Global Placer which uses a quadratic solver and a bi-partitioning lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution.\n" - " * quadratic-flowbased-lookahead: Use a Global Placer which uses a quadratic solver and a multi-commodity-flow-based lookahead legalizer. Anchor points are used to spread the solved solution to the legalized solution.") - .default_value("quadratic-bipartitioning-lookahead") + "Controls which Partial Legalizer the Global Placer will use in the AP Flow.\n" + " * bipartitioning: Creates minimum windows around over-dense regions of the device bi-partitions the atoms in these windows such that the region is no longer over-dense and the atoms are in tiles that they can be placed into.\n" + " * flow-based: Flows atoms from regions that are overfilled to regions that are underfilled.") + .default_value("bipartitioning") .show_in(argparse::ShowIn::HELP_ONLY); ap_grp.add_argument(args.ap_full_legalizer, "--ap_full_legalizer") @@ -1876,7 +1919,7 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio "Controls which Full Legalizer to use in the AP Flow.\n" " * naive: Use a Naive Full Legalizer which will try to create clusters exactly where their atoms are placed.\n" " * appack: Use APPack, which takes the Packer in VPR and uses the flat atom placement to create better clusters.\n" - " * basic-min-disturbance: Use the Basic Min. Disturbance Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.\n") + " * basic-min-disturbance: Use the Basic Min. Disturbance Full Legalizer which tries to reconstruct a clustered placement that is as close to the incoming flat placement as possible.") .default_value("appack") .show_in(argparse::ShowIn::HELP_ONLY); diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index c2629ff2fc8..bc6b62660bb 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -97,7 +97,8 @@ struct t_options { argparse::ArgValue netlist_verbosity; /* Analytical Placement options */ - argparse::ArgValue ap_global_placer; + argparse::ArgValue ap_analytical_solver; + argparse::ArgValue ap_partial_legalizer; argparse::ArgValue ap_full_legalizer; argparse::ArgValue ap_detailed_placer; argparse::ArgValue ap_verbosity; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 2bf6e0d5968..56e68526277 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1048,8 +1048,12 @@ struct t_placer_opts { * @param doAnalyticalPlacement * True if analytical placement is supposed to be done in the CAD * flow. False if otherwise. - * @param global_placer_type - * The type of global placer the AP flow will use. + * @param analytical_solver_type + * The type of analytical solver the Global Placer in the AP flow + * will use. + * @param partial_legalizer_type + * The type of partial legalizer the Global Placer in the AP flow + * will use. * @param full_legalizer_type * The type of full legalizer the AP flow will use. * @param detailed_placer_type @@ -1061,7 +1065,9 @@ struct t_placer_opts { struct t_ap_opts { e_stage_action doAP; - e_ap_global_placer global_placer_type; + e_ap_analytical_solver analytical_solver_type; + + e_ap_partial_legalizer partial_legalizer_type; e_ap_full_legalizer full_legalizer_type; diff --git a/vpr/src/pack/appack_context.h b/vpr/src/pack/appack_context.h index a27f2a48ad3..571219da5c4 100644 --- a/vpr/src/pack/appack_context.h +++ b/vpr/src/pack/appack_context.h @@ -67,11 +67,11 @@ struct t_appack_options { // Distance threshold which decides when to use quadratic decay or inverted // sqrt decay. If the distance is less than this threshold, quadratic decay // is used. Inverted sqrt is used otherwise. - static constexpr float dist_th = 5.0f; + static constexpr float dist_th = 2.0f; // Horizontal offset to the inverted sqrt decay. - static constexpr float sqrt_offset = -1.1f; + static constexpr float sqrt_offset = -6.1f; // Scaling factor for the quadratic decay term. - static constexpr float quad_fac = 0.1543f; + static constexpr float quad_fac = 0.4f; // =========== Candidate selection distance ============================ // // When selecting candidates, what distance from the cluster will we diff --git a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt index a78ab6d191c..86b9b48c086 100644 --- a/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt +++ b/vtr_flow/parse/qor_config/qor_ap_fixed_chan_width.txt @@ -2,13 +2,22 @@ # channel width. vpr_status;output.txt;vpr_status=(.*) -total_wirelength;vpr.out;\s*Total wirelength: (\d+) -# Final critical path delay (least slack): 6.34202 ns, Fmax: 157.678 MHz crit_path_delay;vpr.out;Critical path: (.*) ns +post_gp_hpwl;vpr.out;\s*Placement HPWL: (.*) +post_fl_hpwl;vpr.out;Initial placement BB estimate of wirelength: (.*) +total_wirelength;vpr.out;\s*Total wirelength: (\d+) +post_gp_overfilled_bins;vpr.out;\s*Number of overfilled bins: (\d+) +post_gp_avg_overfill;vpr.out;\s*Average overfill magnitude: (.*) +post_gp_num_misplaced_blocks;vpr.out;\s*Number of blocks in an incompatible bin: (\d+) +post_fl_cluster_err;vpr.out;\s*Percent of clusters with reconstruction errors: (.*) +post_fl_atom_err;vpr.out;\s*Percent of atoms misplaced from the flat placement: (.*) +post_fl_total_disp;vpr.out;\s*Total displacement of initial placement from flat placement: (.*) +post_fl_avg_disp;vpr.out;\s*Average atom displacement of initial placement from flat placement: (.*) +post_fl_max_disp;vpr.out;\s*Max atom displacement of initial placement from flat placement: (.*) ap_runtime;vpr.out;Analytical Placement took (.*) seconds -pack_runtime;vpr.out;Packing took (.*) seconds -# TODO: Figure out how to match Placement and not Analytical Placement better. -place_runtime;vpr.out;^(?!.*\bAnalytical\b).*Placement took (.*) seconds +ap_gp_runtime;vpr.out;AP Global Placer took (.*) seconds +ap_fl_runtime;vpr.out;AP Full Legalizer took (.*) seconds +ap_dp_runtime;vpr.out;AP Detailed Placer took (.*) seconds route_runtime;vpr.out;Routing took (.*) seconds total_runtime;vpr.out;The entire flow of VPR took (.*) seconds num_clb;vpr.out;Netlist clb blocks:\s*(\d+) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt index 51ac95b4bb3..b04ccbfb07b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 12.75 vpr 74.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 9 -1 -1 success v8.0.0-12195-g2852c5c90-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T15:16:21 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76140 9 19 897 28 0 769 115 16 16 256 -1 mcnc_medium -1 -1 7811 11275 1900 6527 2848 74.4 MiB 5.67 0.01 5.4441 -89.4017 -5.4441 nan 0.05 0.00169024 0.00134115 0.0906291 0.0756413 74.4 MiB 5.67 74.4 MiB 1.53 13429 17.4857 3546 4.61719 7318 28860 1236755 231996 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 22 28900 206586 -1 5.92192 nan -99.1488 -5.92192 0 0 0.19 -1 -1 74.4 MiB 0.37 0.21961 0.189275 74.4 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.70 vpr 75.92 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12195-g2852c5c90-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T15:16:21 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77740 256 245 954 501 0 681 555 22 22 484 -1 mcnc_large -1 -1 8642 59835 1195 13074 45566 75.9 MiB 0.83 0.01 4.3707 -800.06 -4.3707 nan 0.07 0.00194025 0.00173789 0.06298 0.0566432 75.9 MiB 0.83 75.9 MiB 0.46 12260 18.0029 3322 4.87812 3257 7834 457668 94304 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.824 nan -894.955 -4.824 0 0 0.22 -1 -1 75.9 MiB 0.17 0.149574 0.137611 75.9 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 62.05 vpr 103.91 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 291 10 -1 -1 success v8.0.0-12195-g2852c5c90-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T15:16:21 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 106408 10 10 2659 20 0 2325 311 22 22 484 -1 mcnc_large -1 -1 35152 67703 18956 43513 5234 103.9 MiB 28.40 0.03 7.09459 -68.0907 -7.09459 nan 0.15 0.00522308 0.00414435 0.397341 0.324914 103.9 MiB 28.40 103.9 MiB 4.96 53423 22.9776 13699 5.89204 19342 81325 5114569 727307 2.15576e+07 1.56832e+07 3.51389e+06 7260.09 25 64568 594370 -1 7.24024 nan -70.1425 -7.24024 0 0 0.62 -1 -1 103.9 MiB 1.47 0.843066 0.71523 103.9 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 13.05 vpr 75.95 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12195-g2852c5c90-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T15:16:21 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77772 41 35 1006 76 0 831 163 16 16 256 -1 mcnc_medium -1 -1 8494 13513 1513 6134 5866 75.9 MiB 5.80 0.01 5.24005 -154.078 -5.24005 nan 0.05 0.00201943 0.00160412 0.0782205 0.0654816 75.9 MiB 5.80 75.9 MiB 1.54 13918 16.7485 3647 4.38869 7079 29528 1142046 195093 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.64371 nan -165.597 -5.64371 0 0 0.19 -1 -1 75.9 MiB 0.36 0.212972 0.184851 75.9 MiB -1 0.05 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.77 vpr 74.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76396 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 9839 6247 7389 972 4547 1870 74.6 MiB 2.20 0.01 6.7004 4.99315 -83.7713 -4.99315 nan 0.05 0.00168075 0.00131529 0.069867 0.0582907 74.6 MiB 2.20 74.6 MiB 1.47 10351 17.3674 2658 4.45973 4983 24549 876704 142398 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 21 28900 206586 -1 5.24195 nan -86.4657 -5.24195 0 0 0.19 -1 -1 74.6 MiB 0.30 0.197254 0.170966 74.6 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.44 vpr 75.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77428 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8861 7710 48308 501 10956 36851 75.6 MiB 0.71 0.01 5.66617 3.99454 -786.077 -3.99454 nan 0.07 0.00197152 0.00174969 0.0530321 0.0479107 75.6 MiB 0.71 75.6 MiB 0.42 10509 17.7218 2866 4.83305 2497 5294 323267 70757 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.32952 nan -840.706 -4.32952 0 0 0.21 -1 -1 75.6 MiB 0.15 0.14443 0.133018 75.6 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 19.91 vpr 103.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105740 10 10 2659 20 0 1307 308 22 22 484 -1 mcnc_large -1 -1 35312 24799 56414 14526 36721 5167 103.3 MiB 8.03 0.02 8.69664 6.54963 -63.5707 -6.54963 nan 0.16 0.00636919 0.00502924 0.415039 0.340756 103.3 MiB 8.03 103.3 MiB 4.34 38222 29.2441 9668 7.39709 8731 55064 2361022 305508 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.82732 nan -65.5299 -6.82732 0 0 0.64 -1 -1 103.3 MiB 0.90 0.78483 0.672604 103.3 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.61 vpr 75.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77656 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6547 9953 802 4830 4321 75.8 MiB 2.17 0.01 6.80812 4.95652 -141.202 -4.95652 nan 0.05 0.00225321 0.00180797 0.0702671 0.059411 75.8 MiB 2.17 75.8 MiB 1.41 10473 17.2253 2735 4.49836 4191 21028 669477 115260 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.15955 nan -146.607 -5.15955 0 0 0.19 -1 -1 75.8 MiB 0.29 0.203166 0.17797 75.8 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt index f9888561aa3..8ffc6a4a5ef 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 18.75 vpr 75.08 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76880 9 19 897 28 0 769 115 16 16 256 -1 mcnc_medium -1 -1 7781 7927 1041 4888 1998 75.1 MiB 8.49 0.00 5.26771 -87.3979 -5.26771 nan 0.07 0.00145318 0.00120431 0.0949999 0.0830081 75.1 MiB 8.49 75.1 MiB 2.39 13434 17.4922 3475 4.52474 7093 28842 1188919 203711 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 23 28900 206586 -1 5.71261 nan -95.5795 -5.71261 0 0 0.39 -1 -1 75.1 MiB 0.37 0.230347 0.204562 75.1 MiB -1 0.07 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 4.20 vpr 76.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78040 256 245 954 501 0 681 555 22 22 484 -1 mcnc_large -1 -1 8645 46155 520 10044 35591 76.2 MiB 1.26 0.02 4.22842 -791.908 -4.22842 nan 0.13 0.00324274 0.00298957 0.0892817 0.0813978 76.2 MiB 1.26 76.2 MiB 1.23 12137 17.8223 3273 4.80617 3335 8120 476273 103444 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.53302 nan -861.08 -4.53302 0 0 0.36 -1 -1 76.2 MiB 0.33 0.245742 0.227797 76.2 MiB -1 0.13 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 79.07 vpr 104.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 291 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 106820 10 10 2659 20 0 2325 311 22 22 484 -1 mcnc_large -1 -1 34854 66650 18085 43254 5311 104.3 MiB 40.00 0.04 6.83404 -66.0421 -6.83404 nan 0.24 0.0118021 0.00931383 0.817421 0.662705 104.3 MiB 40.00 104.3 MiB 9.54 53952 23.2052 13843 5.95398 18928 79526 5166116 753331 2.15576e+07 1.56832e+07 3.51389e+06 7260.09 23 64568 594370 -1 7.23867 nan -69.2309 -7.23867 0 0 1.06 -1 -1 104.3 MiB 1.94 1.44039 1.21281 104.3 MiB -1 0.24 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 21.04 vpr 76.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77844 41 35 1006 76 0 831 163 16 16 256 -1 mcnc_medium -1 -1 8267 12178 1040 5903 5235 76.0 MiB 9.43 0.01 5.26834 -151.935 -5.26834 nan 0.07 0.0028483 0.00231985 0.108866 0.0944881 76.0 MiB 9.43 76.0 MiB 2.55 13808 16.6161 3630 4.36823 7616 32394 1282541 221555 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 25 28900 206586 -1 5.51169 nan -162.882 -5.51169 0 0 0.33 -1 -1 76.0 MiB 0.67 0.361937 0.321485 76.0 MiB -1 0.07 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.72 vpr 74.57 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76360 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 9839 6247 7389 972 4547 1870 74.6 MiB 2.18 0.01 6.7004 4.99315 -83.7713 -4.99315 nan 0.05 0.0018762 0.00147138 0.0720998 0.0603721 74.6 MiB 2.18 74.6 MiB 1.44 10351 17.3674 2658 4.45973 4983 24549 876704 142398 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 21 28900 206586 -1 5.24195 nan -86.4657 -5.24195 0 0 0.20 -1 -1 74.6 MiB 0.32 0.20208 0.17579 74.6 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.35 vpr 75.37 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77180 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8861 7710 48308 501 10956 36851 75.4 MiB 0.67 0.01 5.66617 3.99454 -786.077 -3.99454 nan 0.07 0.00210079 0.00187399 0.05383 0.0485745 75.4 MiB 0.67 75.4 MiB 0.38 10509 17.7218 2866 4.83305 2497 5294 323267 70757 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.32952 nan -840.706 -4.32952 0 0 0.21 -1 -1 75.4 MiB 0.16 0.145073 0.133469 75.4 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.23 vpr 102.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105404 10 10 2659 20 0 1307 308 22 22 484 -1 mcnc_large -1 -1 35312 24799 56414 14526 36721 5167 102.9 MiB 8.02 0.02 8.69664 6.54963 -63.5707 -6.54963 nan 0.16 0.00680001 0.00542795 0.412826 0.338791 102.9 MiB 8.02 102.9 MiB 4.35 38222 29.2441 9668 7.39709 8731 55064 2361022 305508 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.82732 nan -65.5299 -6.82732 0 0 0.66 -1 -1 102.9 MiB 0.95 0.799071 0.685614 102.9 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.66 vpr 75.70 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77520 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6547 9953 802 4830 4321 75.7 MiB 2.22 0.01 6.80812 4.95652 -141.202 -4.95652 nan 0.06 0.00252936 0.00207931 0.0740057 0.062639 75.7 MiB 2.22 75.7 MiB 1.44 10473 17.2253 2735 4.49836 4191 21028 669477 115260 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.15955 nan -146.607 -5.15955 0 0 0.19 -1 -1 75.7 MiB 0.28 0.201998 0.177319 75.7 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/golden_results.txt deleted file mode 100644 index f132845c781..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/golden_results.txt +++ /dev/null @@ -1,5 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.94 vpr 74.77 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76564 9 19 897 28 0 624 108 16 16 256 -1 mcnc_medium -1 -1 10315 6596 9617 1559 5516 2542 74.8 MiB 1.83 0.01 6.75959 5.07271 -83.5391 -5.07271 nan 0.05 0.00162447 0.001265 0.077793 0.0643277 74.8 MiB 1.83 74.8 MiB 1.37 11052 17.7400 2817 4.52167 5101 22566 851127 138852 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.37355 nan -88.7113 -5.37355 0 0 0.20 -1 -1 74.8 MiB 0.27 0.190594 0.164391 74.8 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.43 vpr 75.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 256 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76860 256 245 954 501 0 589 560 22 22 484 -1 mcnc_large -1 -1 10234 7797 51314 1070 11670 38574 75.1 MiB 0.67 0.01 6.53248 4.02447 -785.149 -4.02447 nan 0.07 0.00226809 0.00205398 0.0618196 0.0559082 75.1 MiB 0.67 75.1 MiB 0.37 10533 17.8829 2862 4.85908 2507 5465 336298 76364 2.15576e+07 3.17975e+06 1.49107e+06 3080.73 19 47664 245996 -1 4.35047 nan -842.961 -4.35047 0 0 0.22 -1 -1 75.1 MiB 0.19 0.175627 0.161726 75.1 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 18.05 vpr 102.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 283 10 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 104988 10 10 2659 20 0 1537 303 22 22 484 -1 mcnc_large -1 -1 38269 26758 56238 15119 35900 5219 102.5 MiB 7.03 0.02 10.0331 6.59208 -63.1998 -6.59208 nan 0.16 0.00681329 0.00553283 0.410131 0.342368 102.5 MiB 7.03 102.5 MiB 4.80 40340 26.2459 10213 6.64476 10566 57669 2722491 354615 2.15576e+07 1.5252e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.59758 nan -64.3078 -6.59758 0 0 0.64 -1 -1 102.5 MiB 0.98 0.800154 0.691255 102.5 MiB -1 0.16 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.80 vpr 75.61 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77428 41 35 1006 76 0 667 163 16 16 256 -1 mcnc_medium -1 -1 11495 7037 12623 1276 5735 5612 75.6 MiB 1.80 0.01 6.34209 4.94158 -140.443 -4.94158 nan 0.05 0.00182801 0.00144126 0.0708206 0.0592281 75.6 MiB 1.80 75.6 MiB 1.33 11301 16.9430 2961 4.43928 4738 21343 723412 125961 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.29948 nan -148.755 -5.29948 0 0 0.19 -1 -1 75.6 MiB 0.26 0.191646 0.16645 75.6 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt similarity index 97% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt index fbe0c8d91e1..914133ac93b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/config.txt @@ -50,5 +50,5 @@ qor_parse_file=qor_ap_fixed_chan_width.txt pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt # Pass the script params while writing the vpr constraints. -script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_global_placer quadratic-flowbased-lookahead --route +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer bipartitioning --route diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..76ac8eda722 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.68 vpr 74.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76740 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 9839 6247 7389 972 4547 1870 74.9 MiB 2.16 0.01 6.7004 4.99315 -83.7713 -4.99315 nan 0.06 0.00214464 0.00172131 0.0732342 0.0613589 74.9 MiB 2.16 74.9 MiB 1.42 10351 17.3674 2658 4.45973 4983 24549 876704 142398 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 21 28900 206586 -1 5.24195 nan -86.4657 -5.24195 0 0 0.19 -1 -1 74.9 MiB 0.31 0.201417 0.17499 74.9 MiB -1 0.06 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.33 vpr 75.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77296 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8861 7710 48308 501 10956 36851 75.5 MiB 0.67 0.01 5.66617 3.99454 -786.077 -3.99454 nan 0.07 0.00199472 0.00176773 0.0526584 0.0474492 75.5 MiB 0.67 75.5 MiB 0.37 10509 17.7218 2866 4.83305 2497 5294 323267 70757 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.32952 nan -840.706 -4.32952 0 0 0.22 -1 -1 75.5 MiB 0.15 0.142754 0.131235 75.5 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.32 vpr 103.19 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105664 10 10 2659 20 0 1307 308 22 22 484 -1 mcnc_large -1 -1 35312 24799 56414 14526 36721 5167 103.2 MiB 8.00 0.03 8.69664 6.54963 -63.5707 -6.54963 nan 0.16 0.00648813 0.00512928 0.419681 0.344675 103.2 MiB 8.00 103.2 MiB 4.33 38222 29.2441 9668 7.39709 8731 55064 2361022 305508 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.82732 nan -65.5299 -6.82732 0 0 0.63 -1 -1 103.2 MiB 0.89 0.786213 0.672787 103.2 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.60 vpr 75.71 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77524 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6547 9953 802 4830 4321 75.7 MiB 2.15 0.01 6.80812 4.95652 -141.202 -4.95652 nan 0.05 0.00198848 0.00157732 0.0678735 0.057204 75.7 MiB 2.15 75.7 MiB 1.32 10473 17.2253 2735 4.49836 4191 21028 669477 115260 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.15955 nan -146.607 -5.15955 0 0 0.21 -1 -1 75.7 MiB 0.27 0.191818 0.168051 75.7 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/golden_results.txt deleted file mode 100644 index d98be68bb97..00000000000 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer/config/golden_results.txt +++ /dev/null @@ -1,5 +0,0 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 12.26 vpr 74.48 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76264 9 19 897 28 0 630 108 16 16 256 -1 mcnc_medium -1 -1 6565 7818 1081 4671 2066 74.5 MiB 5.53 0.01 5.04055 -81.6216 -5.04055 nan 0.05 0.00237703 0.00196651 0.0753183 0.0633752 74.5 MiB 5.53 74.5 MiB 1.46 10582 16.8235 2731 4.34181 5264 23670 835413 141193 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.34071 nan -86.8247 -5.34071 0 0 0.19 -1 -1 74.5 MiB 0.29 0.19668 0.17074 74.5 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.59 vpr 75.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 256 -1 -1 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77208 256 245 954 501 0 596 564 22 22 484 -1 mcnc_large -1 -1 8266 49473 1118 9288 39067 75.4 MiB 0.70 0.01 4.19633 -820.149 -4.19633 nan 0.07 0.00207963 0.00186636 0.0556309 0.0503754 75.4 MiB 0.70 75.4 MiB 0.42 11056 18.5503 2991 5.01846 2630 5914 340811 70997 2.15576e+07 3.39532e+06 1.49107e+06 3080.73 19 47664 245996 -1 4.75302 nan -902.006 -4.75302 0 0 0.30 -1 -1 75.4 MiB 0.19 0.170049 0.156797 75.4 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 59.90 vpr 102.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 284 10 -1 -1 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 104568 10 10 2659 20 0 1509 304 22 22 484 -1 mcnc_large -1 -1 26895 54417 14441 34837 5139 102.1 MiB 28.13 0.03 6.48343 -63.7016 -6.48343 nan 0.16 0.00678833 0.00548171 0.424707 0.35422 102.1 MiB 28.13 102.1 MiB 4.72 41140 27.2631 10400 6.89198 10359 55686 2689428 360851 2.15576e+07 1.53059e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.73969 nan -65.312 -6.73969 0 0 0.61 -1 -1 102.1 MiB 0.98 0.805898 0.695455 102.1 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.28 vpr 75.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 88 41 -1 -1 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77336 41 35 1006 76 0 645 164 16 16 256 -1 mcnc_medium -1 -1 7089 12708 1302 5817 5589 75.5 MiB 5.50 0.01 4.92327 -146.963 -4.92327 nan 0.05 0.00180838 0.00143702 0.0735806 0.0616535 75.5 MiB 5.50 75.5 MiB 1.34 11364 17.6186 2949 4.57209 4867 22805 800791 135845 1.05632e+07 4.74267e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.21321 nan -154.92 -5.21321 0 0 0.19 -1 -1 75.5 MiB 0.29 0.202844 0.176479 75.5 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt similarity index 97% rename from vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt index d5c911fe715..75c1001ec87 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/config.txt @@ -50,5 +50,5 @@ qor_parse_file=qor_ap_fixed_chan_width.txt pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt # Pass the script params while writing the vpr constraints. -script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_global_placer quadratic-bipartitioning-lookahead --route +script_params=-starting_stage vpr -track_memory_usage --analytical_place --ap_partial_legalizer flow-based --route diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt new file mode 100644 index 00000000000..d0b6abf9c30 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 12.58 vpr 74.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76572 9 19 897 28 0 586 109 16 16 256 -1 mcnc_medium -1 -1 9900 6360 7909 1107 4684 2118 74.8 MiB 5.64 0.01 6.03601 5.03307 -83.5288 -5.03307 nan 0.06 0.00203466 0.00167958 0.0818482 0.0685737 74.8 MiB 5.64 74.8 MiB 1.47 10594 18.1094 2702 4.61880 4742 22493 795427 129384 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 19 28900 206586 -1 5.43777 nan -90.0079 -5.43777 0 0 0.22 -1 -1 74.8 MiB 0.30 0.213641 0.187016 74.8 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.28 vpr 75.49 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 52 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77304 256 245 954 501 0 592 553 22 22 484 -1 mcnc_large -1 -1 8675 7625 18705 208 2044 16453 75.5 MiB 0.54 0.01 5.29347 4.17001 -789.106 -4.17001 nan 0.07 0.00210785 0.00187171 0.0283921 0.0260381 75.5 MiB 0.54 75.5 MiB 0.37 10188 17.2095 2783 4.70101 2438 5152 286148 62961 2.15576e+07 2.80249e+06 1.49107e+06 3080.73 26 47664 245996 -1 4.27306 nan -834.262 -4.27306 0 0 0.24 -1 -1 75.5 MiB 0.21 0.164997 0.152139 75.5 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 56.71 vpr 103.44 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 285 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105924 10 10 2659 20 0 1252 305 22 22 484 -1 mcnc_large -1 -1 34943 24219 57761 15196 37297 5268 103.4 MiB 26.54 0.02 10.2208 6.43021 -61.984 -6.43021 nan 0.18 0.00650587 0.0051602 0.428973 0.354156 103.4 MiB 26.54 103.4 MiB 4.46 38021 30.3682 9597 7.66534 9409 61511 2810186 334080 2.15576e+07 1.53598e+07 3.51389e+06 7260.09 21 64568 594370 -1 6.57906 nan -64.2422 -6.57906 0 0 0.63 -1 -1 103.4 MiB 1.08 0.852224 0.731336 103.4 MiB -1 0.17 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 12.80 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 83 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77460 41 35 1006 76 0 603 159 16 16 256 -1 mcnc_medium -1 -1 10923 6527 10479 906 5084 4489 75.6 MiB 5.79 0.01 6.34107 4.93251 -140.282 -4.93251 nan 0.05 0.00182476 0.00143138 0.0648361 0.0543319 75.6 MiB 5.79 75.6 MiB 1.33 10310 17.0978 2713 4.49917 3971 19813 634767 109350 1.05632e+07 4.4732e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.2466 nan -147.136 -5.2466 0 0 0.19 -1 -1 75.6 MiB 0.25 0.189748 0.165607 75.6 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt new file mode 100644 index 00000000000..48b5feea72d --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver lp-b2b + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..df573c79e04 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.71 vpr 74.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76544 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 9839 6247 7389 972 4547 1870 74.8 MiB 2.21 0.01 6.7004 4.99315 -83.7713 -4.99315 nan 0.06 0.00213564 0.00171905 0.0809811 0.0682891 74.8 MiB 2.21 74.8 MiB 1.44 10351 17.3674 2658 4.45973 4983 24549 876704 142398 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 21 28900 206586 -1 5.24195 nan -86.4657 -5.24195 0 0 0.20 -1 -1 74.8 MiB 0.32 0.211188 0.183562 74.8 MiB -1 0.06 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.44 vpr 75.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76924 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8861 7710 48308 501 10956 36851 75.1 MiB 0.70 0.01 5.66617 3.99454 -786.077 -3.99454 nan 0.08 0.00215311 0.00192204 0.0567913 0.0510815 75.1 MiB 0.70 75.1 MiB 0.39 10509 17.7218 2866 4.83305 2497 5294 323267 70757 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.32952 nan -840.706 -4.32952 0 0 0.23 -1 -1 75.1 MiB 0.16 0.148757 0.136485 75.1 MiB -1 0.08 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 19.59 vpr 103.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105688 10 10 2659 20 0 1307 308 22 22 484 -1 mcnc_large -1 -1 35312 24799 56414 14526 36721 5167 103.2 MiB 7.81 0.02 8.69664 6.54963 -63.5707 -6.54963 nan 0.15 0.00541808 0.00416684 0.353796 0.285792 103.2 MiB 7.81 103.2 MiB 4.26 38222 29.2441 9668 7.39709 8731 55064 2361022 305508 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.82732 nan -65.5299 -6.82732 0 0 0.65 -1 -1 103.2 MiB 0.85 0.705686 0.600054 103.2 MiB -1 0.15 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.61 vpr 75.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77676 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6547 9953 802 4830 4321 75.9 MiB 2.16 0.01 6.80812 4.95652 -141.202 -4.95652 nan 0.06 0.00238669 0.00192567 0.0737126 0.0623663 75.9 MiB 2.16 75.9 MiB 1.39 10473 17.2253 2735 4.49836 4191 21028 669477 115260 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.15955 nan -146.607 -5.15955 0 0 0.20 -1 -1 75.9 MiB 0.30 0.208025 0.182647 75.9 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt index 2fa4914a366..7a545550ccd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/mcnc/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 16.01 vpr 75.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 9 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76852 9 19 897 28 0 769 115 16 16 256 -1 mcnc_medium -1 -1 7781 7927 1041 4888 1998 75.1 MiB 6.19 0.00 5.26771 -87.3979 -5.26771 nan 0.05 0.00162477 0.00137429 0.0734224 0.0645735 75.1 MiB 6.19 75.1 MiB 1.65 13434 17.4922 3475 4.52474 7093 28842 1188919 203711 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 23 28900 206586 -1 5.71261 nan -95.5795 -5.71261 0 0 0.17 -1 -1 75.1 MiB 0.42 0.221458 0.197544 75.1 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.16 vpr 76.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77968 256 245 954 501 0 681 555 22 22 484 -1 mcnc_large -1 -1 8645 46155 520 10044 35591 76.1 MiB 1.05 0.01 4.22842 -791.908 -4.22842 nan 0.10 0.00287585 0.00261019 0.0756409 0.0692945 76.1 MiB 1.05 76.1 MiB 1.02 12137 17.8223 3273 4.80617 3335 8120 476273 103444 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 17 47664 245996 -1 4.53302 nan -861.08 -4.53302 0 0 0.33 -1 -1 76.1 MiB 0.30 0.220363 0.204959 76.1 MiB -1 0.10 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 63.02 vpr 104.09 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 291 10 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 106588 10 10 2659 20 0 2325 311 22 22 484 -1 mcnc_large -1 -1 34854 66650 18085 43254 5311 104.1 MiB 34.65 0.02 6.83404 -66.0421 -6.83404 nan 0.18 0.00650378 0.00526486 0.573656 0.469611 104.1 MiB 34.65 104.1 MiB 6.46 53952 23.2052 13843 5.95398 18928 79526 5166116 753331 2.15576e+07 1.56832e+07 3.51389e+06 7260.09 23 64568 594370 -1 7.23867 nan -69.2309 -7.23867 0 0 1.00 -1 -1 104.1 MiB 1.52 1.02595 0.866125 104.1 MiB -1 0.18 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 16.59 vpr 76.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12163-g0dba7016b-dirty Release VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-19T17:54:19 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 77996 41 35 1006 76 0 831 163 16 16 256 -1 mcnc_medium -1 -1 8267 12178 1040 5903 5235 76.2 MiB 6.82 0.01 5.26834 -151.935 -5.26834 nan 0.05 0.00161857 0.00134251 0.0802541 0.070176 76.2 MiB 6.82 76.2 MiB 1.60 13808 16.6161 3630 4.36823 7616 32394 1282541 221555 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 25 28900 206586 -1 5.51169 nan -162.882 -5.51169 0 0 0.30 -1 -1 76.2 MiB 0.42 0.233738 0.207219 76.2 MiB -1 0.05 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.82 vpr 74.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76728 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 9839 6247 7389 972 4547 1870 74.9 MiB 2.18 0.01 6.7004 4.99315 -83.7713 -4.99315 nan 0.06 0.00210781 0.0016687 0.0768908 0.0646007 74.9 MiB 2.18 74.9 MiB 1.43 10351 17.3674 2658 4.45973 4983 24549 876704 142398 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 21 28900 206586 -1 5.24195 nan -86.4657 -5.24195 0 0 0.20 -1 -1 74.9 MiB 0.33 0.209556 0.182397 74.9 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.41 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77432 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8861 7710 48308 501 10956 36851 75.6 MiB 0.68 0.01 5.66617 3.99454 -786.077 -3.99454 nan 0.07 0.00218714 0.00195673 0.057178 0.0517705 75.6 MiB 0.68 75.6 MiB 0.38 10509 17.7218 2866 4.83305 2497 5294 323267 70757 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.32952 nan -840.706 -4.32952 0 0 0.23 -1 -1 75.6 MiB 0.16 0.150727 0.138982 75.6 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.54 vpr 103.28 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105756 10 10 2659 20 0 1307 308 22 22 484 -1 mcnc_large -1 -1 35312 24799 56414 14526 36721 5167 103.3 MiB 8.22 0.03 8.69664 6.54963 -63.5707 -6.54963 nan 0.18 0.00695297 0.00560648 0.444013 0.367195 103.3 MiB 8.22 103.3 MiB 4.42 38222 29.2441 9668 7.39709 8731 55064 2361022 305508 2.15576e+07 1.55215e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.82732 nan -65.5299 -6.82732 0 0 0.67 -1 -1 103.3 MiB 1.04 0.868938 0.749348 103.3 MiB -1 0.18 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.65 vpr 75.66 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77472 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6547 9953 802 4830 4321 75.7 MiB 2.18 0.01 6.80812 4.95652 -141.202 -4.95652 nan 0.06 0.0024294 0.00197246 0.0735715 0.0622781 75.7 MiB 2.18 75.7 MiB 1.39 10473 17.2253 2735 4.49836 4191 21028 669477 115260 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.15955 nan -146.607 -5.15955 0 0 0.20 -1 -1 75.7 MiB 0.28 0.201805 0.177346 75.7 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt index 1dc75c004fa..9536e9d1509 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer/config/golden_results.txt @@ -1,5 +1,5 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 13.06 vpr 74.56 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 115 9 -1 -1 success v8.0.0-12205-g352410e1e release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T18:56:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76352 9 19 897 28 0 862 143 16 16 256 -1 mcnc_medium -1 -1 8740 6484 484 4674 1326 74.6 MiB 5.69 0.01 5.71055 -93.0818 -5.71055 nan 0.05 0.00163128 0.00128656 0.0529537 0.0455932 74.6 MiB 5.69 74.6 MiB 1.69 13882 16.1419 3757 4.36860 8788 36930 1403133 252224 1.05632e+07 6.19781e+06 1.26944e+06 4958.75 25 28900 206586 -1 5.84903 nan -97.6295 -5.84903 0 0 0.20 -1 -1 74.6 MiB 0.45 0.190785 0.166345 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.54 vpr 76.24 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 168 256 -1 -1 success v8.0.0-12205-g352410e1e release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T18:56:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78072 256 245 954 501 0 934 669 22 22 484 -1 mcnc_large -1 -1 8646 59149 2103 19783 37263 76.2 MiB 1.24 0.02 4.41285 -872.895 -4.41285 nan 0.07 0.00204611 0.00183978 0.0532044 0.0481567 76.2 MiB 1.24 76.2 MiB 0.87 12994 13.9122 3553 3.80407 4003 9607 387559 84557 2.15576e+07 9.05419e+06 1.49107e+06 3080.73 14 47664 245996 -1 4.66146 nan -911.054 -4.66146 0 0 0.22 -1 -1 76.2 MiB 0.17 0.139146 0.128285 76.2 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 61.29 vpr 104.03 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 379 10 -1 -1 success v8.0.0-12205-g352410e1e release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T18:56:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 106528 10 10 2659 20 0 2595 399 22 22 484 -1 mcnc_large -1 -1 37873 70863 15817 49808 5238 104.0 MiB 27.99 0.03 7.14825 -67.4219 -7.14825 nan 0.15 0.00522836 0.00406387 0.309815 0.254243 104.0 MiB 27.99 104.0 MiB 4.71 55926 21.5514 14543 5.60424 19534 81513 5132271 733522 2.15576e+07 2.04258e+07 3.51389e+06 7260.09 23 64568 594370 -1 7.3503 nan -70.8138 -7.3503 0 0 0.63 -1 -1 104.0 MiB 1.49 0.721698 0.61866 104.0 MiB -1 0.14 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 13.28 vpr 75.96 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 136 41 -1 -1 success v8.0.0-12205-g352410e1e release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-25T18:56:34 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77788 41 35 1006 76 0 962 212 16 16 256 -1 mcnc_medium -1 -1 9491 11570 630 6850 4090 76.0 MiB 5.91 0.01 5.55489 -161.245 -5.55489 nan 0.05 0.00220043 0.00177406 0.0576525 0.0496575 76.0 MiB 5.91 76.0 MiB 1.78 14801 15.3857 3972 4.12890 7562 33341 1123036 194382 1.05632e+07 7.32958e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.76401 nan -170.253 -5.76401 0 0 0.19 -1 -1 76.0 MiB 0.37 0.189038 0.166171 76.0 MiB -1 0.05 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 6.15 vpr 74.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 118 9 -1 -1 success v8.0.0-12319-g3c3593acf-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T15:52:41 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76260 9 19 897 28 0 845 146 16 16 256 -1 mcnc_medium -1 -1 12365 8270 9746 863 6880 2003 74.5 MiB 2.23 0.01 7.18456 5.4961 -93.6165 -5.4961 nan 0.07 0.00254639 0.00222259 0.086132 0.0740221 74.5 MiB 2.23 74.5 MiB 1.72 13345 15.8116 3487 4.13152 6463 26620 919798 160217 1.05632e+07 6.35949e+06 1.26944e+06 4958.75 18 28900 206586 -1 6.05887 nan -98.9369 -6.05887 0 0 0.19 -1 -1 74.5 MiB 0.39 0.222236 0.195695 74.5 MiB -1 0.07 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 3.65 vpr 75.46 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 168 256 -1 -1 success v8.0.0-12319-g3c3593acf-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T15:52:41 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77272 256 245 954 501 0 936 669 22 22 484 -1 mcnc_large -1 -1 10542 8747 59149 2154 19729 37266 75.5 MiB 1.24 0.02 5.38138 4.38501 -874.556 -4.38501 nan 0.07 0.00209694 0.00188497 0.0563663 0.0509566 75.5 MiB 1.24 75.5 MiB 0.87 12756 13.6282 3483 3.72115 4006 10114 404499 85551 2.15576e+07 9.05419e+06 1.49107e+06 3080.73 18 47664 245996 -1 4.63091 nan -907.495 -4.63091 0 0 0.22 -1 -1 75.5 MiB 0.21 0.162322 0.149228 75.5 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 21.09 vpr 102.94 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 377 10 -1 -1 success v8.0.0-12319-g3c3593acf-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T15:52:41 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105412 10 10 2659 20 0 2571 397 22 22 484 -1 mcnc_large -1 -1 44776 36231 76213 17980 52338 5895 102.9 MiB 7.51 0.03 9.34127 7.28862 -69.7369 -7.28862 nan 0.16 0.00642442 0.0053304 0.412862 0.342414 102.9 MiB 7.51 102.9 MiB 4.84 52320 20.3501 13584 5.28355 17236 73425 3531835 478455 2.15576e+07 2.0318e+07 3.51389e+06 7260.09 18 64568 594370 -1 7.60969 nan -72.5685 -7.60969 0 0 0.71 -1 -1 102.9 MiB 1.19 0.795821 0.685077 102.9 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 6.66 vpr 75.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 128 41 -1 -1 success v8.0.0-12319-g3c3593acf-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-31T15:52:41 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77240 41 35 1006 76 0 955 204 16 16 256 -1 mcnc_medium -1 -1 12185 8976 13404 939 7582 4883 75.4 MiB 2.59 0.01 7.09065 5.41162 -159.473 -5.41162 nan 0.06 0.0020802 0.00165481 0.0756766 0.0645647 75.4 MiB 2.59 75.4 MiB 1.96 14222 14.8921 3712 3.88691 6941 30823 1007954 175223 1.05632e+07 6.89843e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.78622 nan -170.237 -5.78622 0 0 0.33 -1 -1 75.4 MiB 0.35 0.203674 0.178783 75.4 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt index cc6c8605186..af96344e4d4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks/config/golden_results.txt @@ -1,6 +1,6 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.01 vpr 82.36 MiB -1 -1 9.68 47504 3 0.64 -1 -1 38420 -1 -1 47 196 1 0 success v8.0.0-12284-g51bddabcb-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-20T13:31:45 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 84332 196 193 800 0 1 602 437 20 20 400 -1 vtr_extra_small -1 -1 10070 3652 132997 35694 84550 12753 82.4 MiB 1.72 0.01 3.2653 2.38057 -1112.29 -2.38057 2.38057 0.06 0.00193977 0.00167903 0.171366 0.148678 82.4 MiB 1.72 82.4 MiB 0.91 5647 9.52277 1600 2.69814 1586 2429 170107 42789 2.07112e+07 3.08102e+06 1.26946e+06 3173.65 12 38988 203232 -1 2.67914 2.67914 -1215.24 -2.67914 0 0 0.19 -1 -1 82.4 MiB 0.11 0.257849 0.228742 82.4 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.43 vpr 77.15 MiB -1 -1 0.25 22148 3 0.07 -1 -1 36668 -1 -1 68 99 1 0 success v8.0.0-12284-g51bddabcb-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-20T13:31:45 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 79000 99 130 264 0 1 224 298 20 20 400 -1 vtr_extra_small -1 -1 3122 687 77908 28584 34410 14914 77.1 MiB 0.68 0.01 3.02031 1.87385 -123.342 -1.87385 1.87385 0.06 0.00108168 0.000960787 0.0635174 0.0563103 77.1 MiB 0.68 77.1 MiB 0.30 1330 8.06061 400 2.42424 409 668 26732 7858 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 11 39388 210115 -1 1.99317 1.99317 -137.96 -1.99317 0 0 0.19 -1 -1 77.1 MiB 0.04 0.0899682 0.0807575 77.1 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 44.46 vpr 128.95 MiB -1 -1 3.76 64528 8 3.02 -1 -1 44620 -1 -1 248 385 2 1 success v8.0.0-12284-g51bddabcb-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-20T13:31:45 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 132040 385 362 3324 0 1 2366 998 30 30 900 -1 vtr_small -1 -1 70396 30779 584243 232629 326108 25506 128.9 MiB 15.88 0.07 12.6272 9.30433 -9557.78 -9.30433 9.30433 0.27 0.00915945 0.00804694 1.17687 1.02821 128.9 MiB 15.88 128.9 MiB 8.51 42328 18.0043 10832 4.60740 9932 32198 1817849 333160 4.8774e+07 1.48577e+07 6.56785e+06 7297.61 14 120772 1084977 -1 9.70184 9.70184 -9948.19 -9.70184 0 0 1.27 -1 -1 128.9 MiB 0.82 1.65611 1.47053 128.9 MiB -1 0.27 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.31 vpr 85.20 MiB -1 -1 2.11 35716 16 0.42 -1 -1 38820 -1 -1 61 45 3 1 success v8.0.0-12284-g51bddabcb-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-20T13:31:45 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 87240 45 32 936 0 1 769 142 20 20 400 -1 vtr_extra_small -1 -1 14278 6632 31222 9013 20166 2043 85.2 MiB 3.44 0.01 14.223 10.6451 -7116.98 -10.6451 10.6451 0.08 0.00250891 0.00209652 0.234093 0.194408 85.2 MiB 3.44 85.2 MiB 2.40 11049 14.4243 2887 3.76893 3469 9247 708024 169456 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 18 44576 305072 -1 10.6885 10.6885 -7341.62 -10.6885 0 0 0.34 -1 -1 85.2 MiB 0.28 0.384243 0.329459 85.2 MiB -1 0.08 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.20 vpr 76.85 MiB -1 -1 0.46 26500 4 0.11 -1 -1 36476 -1 -1 15 11 0 0 success v8.0.0-12284-g51bddabcb-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-20T13:31:45 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78692 11 2 140 0 2 87 28 20 20 400 -1 vtr_extra_small -1 -1 1104 346 1498 346 953 199 76.8 MiB 0.42 0.00 3.08719 2.10685 -179.409 -2.10685 1.95087 0.06 0.000442371 0.000365901 0.0198711 0.0167916 76.8 MiB 0.42 76.8 MiB 0.28 569 7.02469 145 1.79012 164 245 5326 1432 2.07112e+07 808410 1.12964e+06 2824.09 7 37792 180905 -1 2.08145 1.90829 -178.671 -2.08145 0 0 0.16 -1 -1 76.8 MiB 0.02 0.0370597 0.0326026 76.8 MiB -1 0.06 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 16.33 vpr 82.46 MiB -1 -1 10.16 48020 3 0.64 -1 -1 38552 -1 -1 46 196 1 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 84436 196 193 800 0 1 606 436 20 20 400 -1 vtr_extra_small -1 -1 9829 3239 157376 44151 98003 15222 82.5 MiB 2.10 0.01 3.87827 2.52163 -1133.67 -2.52163 2.52163 0.06 0.002017 0.00173055 0.210521 0.182408 82.5 MiB 2.10 82.5 MiB 0.87 5218 8.74037 1504 2.51926 1515 2128 128299 36993 2.07112e+07 3.02712e+06 1.26946e+06 3173.65 11 38988 203232 -1 2.90309 2.90309 -1205.75 -2.90309 0 0 0.18 -1 -1 82.5 MiB 0.10 0.294107 0.259915 82.5 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.48 vpr 77.02 MiB -1 -1 0.24 22420 3 0.07 -1 -1 36672 -1 -1 68 99 1 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78868 99 130 264 0 1 224 298 20 20 400 -1 vtr_extra_small -1 -1 3051 762 77908 26433 37944 13531 77.0 MiB 0.69 0.00 3.13126 2.14271 -127.438 -2.14271 2.14271 0.06 0.000599581 0.000526946 0.0505604 0.0445917 77.0 MiB 0.69 77.0 MiB 0.29 1373 8.32121 408 2.47273 425 676 35940 10433 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 9 39388 210115 -1 2.05745 2.05745 -145.265 -2.05745 0 0 0.19 -1 -1 77.0 MiB 0.03 0.0708635 0.0633859 77.0 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 47.81 vpr 129.08 MiB -1 -1 3.74 64920 8 3.05 -1 -1 44504 -1 -1 247 385 2 1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 132176 385 362 3324 0 1 2387 997 30 30 900 -1 vtr_small -1 -1 68874 30723 563511 215274 323610 24627 129.1 MiB 17.32 0.08 15.1664 9.11387 -10195.4 -9.11387 9.11387 0.30 0.0106976 0.00955175 1.31381 1.15591 129.1 MiB 17.32 129.1 MiB 8.18 42014 17.7125 10760 4.53626 10048 33532 1783063 328457 4.8774e+07 1.48038e+07 6.56785e+06 7297.61 18 120772 1084977 -1 9.65738 9.65738 -10521.1 -9.65738 0 0 1.28 -1 -1 129.1 MiB 0.96 1.90612 1.70334 129.1 MiB -1 0.29 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 12.76 vpr 85.32 MiB -1 -1 2.10 35728 16 0.41 -1 -1 38820 -1 -1 61 45 3 1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 87364 45 32 936 0 1 779 142 20 20 400 -1 vtr_extra_small -1 -1 14169 6524 30112 8711 19109 2292 85.3 MiB 4.17 0.01 14.9863 11.2623 -7220.41 -11.2623 11.2623 0.09 0.00257114 0.0021362 0.231372 0.192892 85.3 MiB 4.17 85.3 MiB 2.66 11118 14.3273 2853 3.67655 3314 8781 707817 174136 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 12 44576 305072 -1 11.748 11.748 -7583.52 -11.748 0 0 0.36 -1 -1 85.3 MiB 0.24 0.355928 0.306193 85.3 MiB -1 0.09 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.34 vpr 76.38 MiB -1 -1 0.52 26528 4 0.11 -1 -1 36476 -1 -1 15 11 0 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78208 11 2 140 0 2 80 28 20 20 400 -1 vtr_extra_small -1 -1 1035 345 1582 426 934 222 76.4 MiB 0.45 0.00 2.87093 2.12187 -178.898 -2.12187 1.95781 0.06 0.000430111 0.000354656 0.0199202 0.0167969 76.4 MiB 0.45 76.4 MiB 0.27 532 7.18919 137 1.85135 148 243 5764 1450 2.07112e+07 808410 1.12964e+06 2824.09 7 37792 180905 -1 2.26141 1.98907 -189.802 -2.26141 0 0 0.16 -1 -1 76.4 MiB 0.02 0.0369341 0.0324268 76.4 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt index 6597f69926e..e59d01b3795 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.57 vpr 74.60 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76392 9 19 897 28 0 624 108 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 1.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.6 MiB 1.65 74.6 MiB 1.48 14371 23.0674 3784 6.07384 4075 16657 665456 103737 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.63192 nan -103.794 -6.63192 0 0 0.19 -1 -1 74.6 MiB 0.27 0.120295 0.107523 74.6 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 1.93 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 256 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77456 256 245 954 501 0 589 560 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 75.6 MiB 0.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.6 MiB 0.38 75.6 MiB 0.37 12828 21.7793 3449 5.85569 2290 4763 363294 72848 2.15576e+07 3.17975e+06 1.49107e+06 3080.73 12 47664 245996 -1 6.32147 nan -1032.91 -6.32147 0 0 0.22 -1 -1 75.6 MiB 0.16 0.08541 0.0798207 75.6 MiB -1 0.07 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.34 vpr 75.52 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12284-g0a886e4da-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-19T20:42:32 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77332 41 35 1006 76 0 667 163 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.5 MiB 1.46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.5 MiB 1.46 75.5 MiB 1.27 15928 23.8801 4303 6.45127 4201 18009 720686 116311 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 16 28900 206586 -1 6.42149 nan -177.756 -6.42149 0 0 0.20 -1 -1 75.5 MiB 0.28 0.122598 0.110096 75.5 MiB -1 0.05 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.23 vpr 74.45 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76232 9 19 897 28 0 597 109 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 74.4 MiB 1.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 74.4 MiB 1.93 74.4 MiB 1.44 13980 23.4564 3661 6.14262 3967 18277 723411 109638 1.05632e+07 4.36541e+06 1.26944e+06 4958.75 16 28900 206586 -1 6.68067 nan -103.979 -6.68067 0 0 0.19 -1 -1 74.4 MiB 0.26 0.111246 0.0995686 74.4 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.00 vpr 75.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77440 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 -1 -1 -1 -1 -1 -1 75.6 MiB 0.40 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.6 MiB 0.40 75.6 MiB 0.38 11588 19.5413 3140 5.29511 2222 4779 316744 66420 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 12 47664 245996 -1 5.87415 nan -919.091 -5.87415 0 0 0.27 -1 -1 75.6 MiB 0.15 0.0834843 0.0777053 75.6 MiB -1 0.07 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.17 vpr 75.38 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77188 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 -1 -1 -1 -1 -1 -1 75.4 MiB 1.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 75.4 MiB 1.86 75.4 MiB 1.35 14800 24.3421 3955 6.50493 3799 17906 688546 108664 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 17 28900 206586 -1 6.8204 nan -173.521 -6.8204 0 0 0.22 -1 -1 75.4 MiB 0.28 0.12506 0.111964 75.4 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt new file mode 100644 index 00000000000..8e0fbf318b0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/config.txt @@ -0,0 +1,54 @@ +############################################################################### +# Configuration file for running the MCNC benchmarks through the AP flow. +# +# The AP flow requires that each circuit contains fixed blocks and is fixed +# to a specific device size. The device sizes here were chosen to match the +# device sizes of the default VTR flow. +############################################################################### + +# Path to directory of circuits to use +circuits_dir=benchmarks/blif/wiremap6 + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Add circuits to list to sweep +circuit_list_add=apex4.pre-vpr.blif +circuit_list_add=des.pre-vpr.blif +circuit_list_add=ex1010.pre-vpr.blif +circuit_list_add=seq.pre-vpr.blif + +# Constrain the circuits to their devices +circuit_constraint_list_add=(apex4.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(seq.pre-vpr.blif, device=mcnc_medium) +circuit_constraint_list_add=(des.pre-vpr.blif, device=mcnc_large) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, device=mcnc_large) + +# Constrain the IOs +circuit_constraint_list_add=(apex4.pre-vpr.blif, constraints=../../../../../mcnc/constraints/apex4_io_constraint.xml) +circuit_constraint_list_add=(seq.pre-vpr.blif, constraints=../../../../../mcnc/constraints/seq_io_constraint.xml) +circuit_constraint_list_add=(des.pre-vpr.blif, constraints=../../../../../mcnc/constraints/des_io_constraint.xml) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, constraints=../../../../../mcnc/constraints/ex1010_io_constraint.xml) + +# Constrain the circuits to their channel widths +# 1.3 * minW +circuit_constraint_list_add=(apex4.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(seq.pre-vpr.blif, route_chan_width=78) +circuit_constraint_list_add=(des.pre-vpr.blif, route_chan_width=44) +circuit_constraint_list_add=(ex1010.pre-vpr.blif, route_chan_width=114) + +# Parse info and how to parse +parse_file=vpr_fixed_chan_width.txt + +# How to parse QoR info +qor_parse_file=qor_ap_fixed_chan_width.txt + +# Pass requirements +pass_requirements_file=pass_requirements_ap_fixed_chan_width.txt + +# Pass the script params while writing the vpr constraints. +script_params=-starting_stage vpr -track_memory_usage --analytical_place --route --ap_analytical_solver qp-hybrid + diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt new file mode 100644 index 00000000000..d2a0a509bc2 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver/config/golden_results.txt @@ -0,0 +1,5 @@ + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.03 vpr 74.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76012 9 19 897 28 0 622 110 16 16 256 -1 mcnc_medium -1 -1 10056 6578 8526 1277 4985 2264 74.2 MiB 1.85 0.01 6.41619 5.08637 -85.7733 -5.08637 nan 0.06 0.00194816 0.00154879 0.0785561 0.0654131 74.2 MiB 1.85 74.2 MiB 1.41 10963 17.6538 2801 4.51047 5304 23611 889251 144425 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 22 28900 206586 -1 5.39096 nan -90.1072 -5.39096 0 0 0.20 -1 -1 74.2 MiB 0.37 0.221337 0.1915 74.2 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.46 vpr 75.64 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 56 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77460 256 245 954 501 0 593 557 22 22 484 -1 mcnc_large -1 -1 10436 8112 48647 751 10833 37063 75.6 MiB 0.70 0.01 5.73832 4.11614 -780.807 -4.11614 nan 0.08 0.00198971 0.00178092 0.0536461 0.0483129 75.6 MiB 0.70 75.6 MiB 0.40 10776 18.1720 2929 4.93929 2595 5686 344570 75131 2.15576e+07 3.01806e+06 1.49107e+06 3080.73 16 47664 245996 -1 4.53523 nan -842.42 -4.53523 0 0 0.23 -1 -1 75.6 MiB 0.17 0.153232 0.140665 75.6 MiB -1 0.08 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 16.99 vpr 102.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 291 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 104772 10 10 2659 20 0 1529 311 22 22 484 -1 mcnc_large -1 -1 38077 26865 59279 15488 38368 5423 102.3 MiB 6.54 0.02 9.34272 6.39935 -62.3114 -6.39935 nan 0.15 0.00543975 0.00423229 0.366486 0.296543 102.3 MiB 6.54 102.3 MiB 4.39 39907 26.1001 10095 6.60235 10028 54590 2425227 322477 2.15576e+07 1.56832e+07 3.51389e+06 7260.09 17 64568 594370 -1 6.88776 nan -64.9619 -6.88776 0 0 0.64 -1 -1 102.3 MiB 0.86 0.722489 0.612978 102.3 MiB -1 0.15 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.70 vpr 75.43 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77236 41 35 1006 76 0 667 161 16 16 256 -1 mcnc_medium -1 -1 11200 7059 10649 866 4653 5130 75.4 MiB 1.74 0.01 6.46459 5.0838 -144.876 -5.0838 nan 0.06 0.00215192 0.00170983 0.0745187 0.062897 75.4 MiB 1.74 75.4 MiB 1.30 10747 16.1124 2823 4.23238 4502 20055 655745 115195 1.05632e+07 4.58099e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.53806 nan -153.338 -5.53806 0 0 0.20 -1 -1 75.4 MiB 0.26 0.198685 0.17393 75.4 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt index 008dcd38a4f..d625ba88e73 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time - k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 4.96 vpr 74.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 79 9 -1 -1 success v8.0.0-12313-g365d2b526 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-21T09:41:31 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76040 9 19 897 28 0 623 107 16 16 256 -1 mcnc_medium -1 -1 10045 6450 8456 1313 4865 2278 74.3 MiB 1.89 0.01 6.56432 5.03307 -83.524 -5.03307 nan 0.05 0.00204244 0.00165662 0.0837004 0.0703705 74.3 MiB 1.89 74.3 MiB 1.43 10549 16.9598 2720 4.37299 4745 19339 673268 115030 1.05632e+07 4.25763e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.35405 nan -87.6493 -5.35405 0 0 0.20 -1 -1 74.3 MiB 0.27 0.203126 0.176979 74.3 MiB -1 0.05 - k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.31 vpr 75.04 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 54 256 -1 -1 success v8.0.0-12313-g365d2b526 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-21T09:41:31 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76844 256 245 954 501 0 592 555 22 22 484 -1 mcnc_large -1 -1 10182 8261 32475 449 5759 26267 75.0 MiB 0.60 0.01 5.81056 4.10466 -788.701 -4.10466 nan 0.07 0.00213529 0.00190203 0.0410553 0.0373156 75.0 MiB 0.60 75.0 MiB 0.39 11038 18.6453 2976 5.02703 2516 5569 337853 71532 2.15576e+07 2.91028e+06 1.49107e+06 3080.73 16 47664 245996 -1 4.5805 nan -849.865 -4.5805 0 0 0.26 -1 -1 75.0 MiB 0.17 0.140869 0.130143 75.0 MiB -1 0.07 - k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.62 vpr 102.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 263 10 -1 -1 success v8.0.0-12313-g365d2b526 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-21T09:41:31 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 104716 10 10 2659 20 0 1553 283 22 22 484 -1 mcnc_large -1 -1 37750 27023 51323 13724 33007 4592 102.3 MiB 6.79 0.02 9.4798 6.49062 -63.3158 -6.49062 nan 0.15 0.00558982 0.00437045 0.377565 0.30904 102.3 MiB 6.79 102.3 MiB 4.67 40165 25.8628 10185 6.55827 10819 59199 2817453 375025 2.15576e+07 1.41741e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.92885 nan -65.9061 -6.92885 0 0 0.65 -1 -1 102.3 MiB 0.93 0.743277 0.634821 102.3 MiB -1 0.15 - k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.90 vpr 75.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 82 41 -1 -1 success v8.0.0-12313-g365d2b526 release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-21T09:41:31 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76972 41 35 1006 76 0 666 158 16 16 256 -1 mcnc_medium -1 -1 11362 6922 10833 921 5072 4840 75.2 MiB 1.81 0.01 6.29523 4.75885 -139.918 -4.75885 nan 0.06 0.00245639 0.00201946 0.0743378 0.0630971 75.2 MiB 1.81 75.2 MiB 1.35 11028 16.5586 2899 4.35285 4620 20556 688864 117989 1.05632e+07 4.41931e+06 1.26944e+06 4958.75 17 28900 206586 -1 5.00979 nan -145.985 -5.00979 0 0 0.20 -1 -1 75.2 MiB 0.27 0.20235 0.177701 75.2 MiB -1 0.06 + k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 5.77 vpr 74.67 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 9 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 76464 9 19 897 28 0 597 108 16 16 256 -1 mcnc_medium -1 -1 10024 6243 10131 1651 5757 2723 74.7 MiB 2.28 0.01 6.8229 5.32682 -83.6615 -5.32682 nan 0.05 0.00206038 0.0017022 0.093723 0.0780954 74.7 MiB 2.28 74.7 MiB 1.46 10181 17.0822 2628 4.40940 4073 18938 640743 107003 1.05632e+07 4.31152e+06 1.26944e+06 4958.75 18 28900 206586 -1 5.59905 nan -87.7508 -5.59905 0 0 0.19 -1 -1 74.7 MiB 0.25 0.211734 0.183658 74.7 MiB -1 0.05 + k6_frac_N10_40nm.xml des.pre-vpr.blif common 2.37 vpr 75.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 53 256 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77312 256 245 954 501 0 593 554 22 22 484 -1 mcnc_large -1 -1 8941 7709 48308 545 10829 36934 75.5 MiB 0.68 0.01 5.66617 3.99454 -785.516 -3.99454 nan 0.07 0.00214511 0.00191149 0.0563332 0.0508773 75.5 MiB 0.68 75.5 MiB 0.38 10388 17.5177 2832 4.77572 2536 5560 327505 71090 2.15576e+07 2.85638e+06 1.49107e+06 3080.73 13 47664 245996 -1 4.33616 nan -833.917 -4.33616 0 0 0.22 -1 -1 75.5 MiB 0.16 0.145988 0.134526 75.5 MiB -1 0.07 + k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 20.89 vpr 103.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 270 10 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 105576 10 10 2659 20 0 1302 290 22 22 484 -1 mcnc_large -1 -1 34981 24734 53035 14175 34471 4389 103.1 MiB 8.38 0.03 9.51463 6.78204 -63.5715 -6.78204 nan 0.17 0.00699229 0.0056263 0.426271 0.351528 103.1 MiB 8.38 103.1 MiB 4.63 37980 29.1705 9624 7.39171 9046 58238 2480633 325086 2.15576e+07 1.45514e+07 3.51389e+06 7260.09 18 64568 594370 -1 6.90493 nan -65.9192 -6.90493 0 0 0.66 -1 -1 103.1 MiB 0.97 0.81562 0.700145 103.1 MiB -1 0.16 + k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.71 vpr 75.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 87 41 -1 -1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77664 41 35 1006 76 0 608 163 16 16 256 -1 mcnc_medium -1 -1 10722 6733 9953 785 4940 4228 75.8 MiB 2.14 0.01 6.80812 4.93323 -142.387 -4.93323 nan 0.06 0.00232305 0.00186694 0.0727046 0.0616137 75.8 MiB 2.14 75.8 MiB 1.36 10825 17.8043 2840 4.67105 4600 23438 768869 129758 1.05632e+07 4.68878e+06 1.26944e+06 4958.75 20 28900 206586 -1 5.07748 nan -150.012 -5.07748 0 0 0.23 -1 -1 75.8 MiB 0.32 0.211844 0.185463 75.8 MiB -1 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt index afc11f37559..21c1584247d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_ap/vtr_chain/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 13.83 vpr 82.29 MiB -1 -1 9.44 48140 3 0.65 -1 -1 38720 -1 -1 47 196 1 0 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 84264 196 193 800 389 1 602 437 20 20 400 -1 vtr_extra_small -1 -1 4516 43519 950 11377 31192 82.3 MiB 1.21 0.01 2.50097 -1136.71 -2.50097 2.50097 0.06 0.00195855 0.00169413 0.0632556 0.0555606 82.3 MiB 1.21 82.3 MiB 0.96 6355 10.7167 1757 2.96290 1528 2343 173858 44764 2.07112e+07 3.08102e+06 1.26946e+06 3173.65 13 38988 203232 -1 2.79288 2.79288 -1236.87 -2.79288 0 0 0.19 -1 -1 82.3 MiB 0.11 0.149865 0.13538 82.3 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.03 vpr 77.17 MiB -1 -1 0.24 22276 3 0.07 -1 -1 36668 -1 -1 68 99 1 0 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 79024 99 130 240 229 1 234 298 20 20 400 -1 vtr_extra_small -1 -1 1140 20198 2446 1844 15908 77.2 MiB 0.47 0.00 1.98698 -139.323 -1.98698 1.98698 0.06 0.000584402 0.000516703 0.0153162 0.0137259 77.2 MiB 0.47 77.2 MiB 0.36 1792 10.2400 520 2.97143 456 738 38411 10585 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 10 39388 210115 -1 2.13458 2.13458 -162.955 -2.13458 0 0 0.20 -1 -1 77.2 MiB 0.03 0.036615 0.0333844 77.2 MiB -1 0.06 -k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 10.74 vpr 85.21 MiB -1 -1 2.10 35212 16 0.41 -1 -1 38820 -1 -1 60 45 3 1 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 87256 45 32 936 77 1 795 141 20 20 400 -1 vtr_extra_small -1 -1 7232 10389 572 5361 4456 85.2 MiB 3.15 0.01 11.0809 -6804.8 -11.0809 11.0809 0.08 0.00218888 0.00178883 0.0877567 0.0735568 85.2 MiB 3.15 85.2 MiB 2.69 12312 15.5455 3116 3.93434 3664 10175 858583 200200 2.07112e+07 5.27364e+06 1.91495e+06 4787.38 14 44576 305072 -1 11.8857 11.8857 -7482.44 -11.8857 0 0 0.30 -1 -1 85.2 MiB 0.27 0.217878 0.191569 85.2 MiB -1 0.08 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.23 vpr 76.48 MiB -1 -1 0.47 26240 4 0.11 -1 -1 36476 -1 -1 15 11 0 0 success v8.0.0-12255-g9cbeca773-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-15T13:47:04 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78316 11 2 140 13 2 88 28 20 20 400 -1 vtr_extra_small -1 -1 354 1036 118 484 434 76.5 MiB 0.42 0.00 2.09787 -168.932 -2.09787 1.94131 0.05 0.000441464 0.000365741 0.0143609 0.0122678 76.5 MiB 0.42 76.5 MiB 0.31 556 6.78049 145 1.76829 236 382 8243 2108 2.07112e+07 808410 1.12964e+06 2824.09 10 37792 180905 -1 2.09813 2.00631 -170.542 -2.09813 0 0 0.16 -1 -1 76.5 MiB 0.02 0.0334849 0.0296531 76.5 MiB -1 0.05 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time + k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.02 vpr 82.50 MiB -1 -1 10.13 48012 3 0.64 -1 -1 38596 -1 -1 47 196 1 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 84484 196 193 800 389 1 590 437 20 20 400 -1 vtr_extra_small -1 -1 7934 4257 45176 1066 12361 31749 82.5 MiB 1.47 0.01 3.25822 2.63084 -1156.54 -2.63084 2.63084 0.06 0.00214515 0.0018694 0.0791279 0.0698883 82.5 MiB 1.47 82.5 MiB 0.96 6145 10.5766 1746 3.00516 1575 2431 163711 43682 2.07112e+07 3.08102e+06 1.26946e+06 3173.65 12 38988 203232 -1 2.84041 2.84041 -1246.95 -2.84041 0 0 0.19 -1 -1 82.5 MiB 0.11 0.166836 0.151096 82.5 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.05 vpr 77.07 MiB -1 -1 0.24 22284 3 0.07 -1 -1 36924 -1 -1 68 99 1 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78916 99 130 240 229 1 223 298 20 20 400 -1 vtr_extra_small -1 -1 2057 1081 23183 2599 2547 18037 77.1 MiB 0.48 0.00 2.5581 1.98477 -148.892 -1.98477 1.98477 0.06 0.000599989 0.000530838 0.0172856 0.0154702 77.1 MiB 0.48 77.1 MiB 0.31 1684 10.2683 490 2.98780 435 686 37333 10249 2.07112e+07 4.21279e+06 1.31074e+06 3276.84 10 39388 210115 -1 2.05968 2.05968 -168.156 -2.05968 0 0 0.19 -1 -1 77.1 MiB 0.03 0.0385746 0.0351567 77.1 MiB -1 0.06 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 11.42 vpr 85.57 MiB -1 -1 2.12 35588 16 0.42 -1 -1 39076 -1 -1 61 45 3 1 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 87620 45 32 936 77 1 765 142 20 20 400 -1 vtr_extra_small -1 -1 13887 6788 10872 687 5322 4863 85.6 MiB 3.48 0.01 12.9441 10.2696 -6881.3 -10.2696 10.2696 0.08 0.00237923 0.00194856 0.0922468 0.0768 85.6 MiB 3.48 85.6 MiB 2.41 11409 14.9724 2933 3.84908 3305 8742 695768 173068 2.07112e+07 5.32753e+06 1.91495e+06 4787.38 15 44576 305072 -1 11.0746 11.0746 -7405.05 -11.0746 0 0 0.31 -1 -1 85.6 MiB 0.26 0.232045 0.203408 85.6 MiB -1 0.08 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.26 vpr 76.73 MiB -1 -1 0.47 26628 4 0.16 -1 -1 36348 -1 -1 15 11 0 0 success v8.0.0-12327-g1464a722e-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-03-22T16:35:43 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 78572 11 2 140 13 2 83 28 20 20 400 -1 vtr_extra_small -1 -1 1131 295 1204 201 508 495 76.7 MiB 0.39 0.00 3.41804 2.10685 -161.396 -2.10685 1.95087 0.05 0.000442905 0.000365782 0.0163925 0.0138709 76.7 MiB 0.39 76.7 MiB 0.26 502 6.51948 130 1.68831 152 241 4949 1349 2.07112e+07 808410 1.12964e+06 2824.09 11 37792 180905 -1 2.35801 2.12448 -167.555 -2.35801 0 0 0.16 -1 -1 76.7 MiB 0.02 0.0362038 0.0318097 76.7 MiB -1 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 57ca61bb798..dc70228462c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -1,12 +1,16 @@ regression_tests/vtr_reg_strong/basic_ap regression_tests/vtr_reg_strong/strong_ap/mcnc regression_tests/vtr_reg_strong/strong_ap/vtr_chain -regression_tests/vtr_reg_strong/strong_ap/bipartitioning_global_placer -regression_tests/vtr_reg_strong/strong_ap/flowbased_global_placer +regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer +regression_tests/vtr_reg_strong/strong_ap/flowbased_partial_legalizer regression_tests/vtr_reg_strong/strong_ap/naive_full_legalizer regression_tests/vtr_reg_strong/strong_ap/appack_full_legalizer regression_tests/vtr_reg_strong/strong_ap/annealer_detailed_placer regression_tests/vtr_reg_strong/strong_ap/none_detailed_placer +regression_tests/vtr_reg_strong/strong_ap/no_fixed_blocks +regression_tests/vtr_reg_strong/strong_ap/unrelated_clustering +regression_tests/vtr_reg_strong/strong_ap/qp_hybrid_analytical_solver +regression_tests/vtr_reg_strong/strong_ap/lp_b2b_analytical_solver regression_tests/vtr_reg_strong/strong_absorb_buffers regression_tests/vtr_reg_strong/strong_analysis_only regression_tests/vtr_reg_strong/strong_analytic_placer