diff --git a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h index f65da2908b9..f85ebc72008 100644 --- a/libs/libvtrutil/src/vtr_ndoffsetmatrix.h +++ b/libs/libvtrutil/src/vtr_ndoffsetmatrix.h @@ -2,6 +2,7 @@ #define VTR_ND_OFFSET_MATRIX_H #include #include +#include #include "vtr_assert.h" @@ -309,9 +310,8 @@ class NdOffsetMatrixBase { ///@brief Swap two NdOffsetMatrixBase objects friend void swap(NdOffsetMatrixBase& m1, NdOffsetMatrixBase& m2) { - using std::swap; - swap(m1.dim_ranges_, m2.dim_ranges_); - swap(m1.data_, m2.data_); + std::swap(m1.dim_ranges_, m2.dim_ranges_); + std::swap(m1.data_, m2.data_); } private: @@ -441,7 +441,9 @@ class NdOffsetMatrix : public NdOffsetMatrixBase { VTR_ASSERT_SAFE_MSG(index >= this->dim_ranges_[0].begin_index(), "Index out of range (below dimension minimum)"); VTR_ASSERT_SAFE_MSG(index < this->dim_ranges_[0].end_index(), "Index out of range (above dimension maximum)"); - return this->data_[index]; + int effective_index = index - this->dim_ranges_[0].begin_index(); + + return this->data_[effective_index]; } ///@brief Access an element (mutable) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 13439e200c8..e780005ada1 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -633,8 +633,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts) PlacerOpts->inner_loop_recompute_divider = Options.inner_loop_recompute_divider; PlacerOpts->quench_recompute_divider = Options.quench_recompute_divider; - PlacerOpts->place_cost_exp = 1; - PlacerOpts->td_place_exp_first = Options.place_exp_first; PlacerOpts->td_place_exp_last = Options.place_exp_last; diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index f7af0074b55..c9d3bb23e1e 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -547,8 +547,6 @@ static void ShowPlacerOpts(const t_placer_opts& PlacerOpts, VTR_LOG("Using constraints file '%s'\n", PlacerOpts.constraints_file.c_str()); } - VTR_LOG("PlacerOpts.place_cost_exp: %f\n", PlacerOpts.place_cost_exp); - VTR_LOG("PlacerOpts.place_chan_width: %d\n", PlacerOpts.place_chan_width); if (PlacerOpts.place_algorithm.is_timing_driven()) { diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 2d51c463372..d5698e3eadf 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -1065,7 +1065,6 @@ struct t_placer_opts { t_place_algorithm place_algorithm; t_place_algorithm place_quench_algorithm; float timing_tradeoff; - float place_cost_exp; int place_chan_width; enum e_pad_loc_type pad_loc_type; std::string constraints_file; diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 3e12ef446ba..ff3fd41a78e 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -151,79 +151,48 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, } void NetCostHandler::alloc_and_load_chan_w_factors_for_place_cost_() { - const double place_cost_exp = static_cast(placer_opts_.place_cost_exp); - auto& device_ctx = g_vpr_ctx.device(); - - const int grid_height = device_ctx.grid.height(); - const int grid_width = device_ctx.grid.width(); - - /* Access arrays below as chan?_place_cost_fac_(subhigh, sublow). Since subhigh must be greater than or - * equal to sublow, we will only access the lower half of a matrix, but we allocate the whole matrix anyway - * for simplicity, so we can use the vtr utility matrix functions. */ - chanx_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_height}, {-1, grid_height}}}); - chany_place_cost_fac_ = vtr::NdOffsetMatrix({{{-1, grid_width}, {-1, grid_width}}}); - - // First compute the number of tracks between channel high and channel low, inclusive. - chanx_place_cost_fac_[-1][-1] = 0; - - for (int high = 0; high < grid_height; high++) { - chanx_place_cost_fac_[high][high] = (float)device_ctx.chan_width.x_list[high]; - for (int low = -1; low < high; low++) { - chanx_place_cost_fac_[high][low] = chanx_place_cost_fac_[high - 1][low] + (float)device_ctx.chan_width.x_list[high]; - } - } - - /* Now compute the inverse of the average number of tracks per channel * - * between high and low. The cost function divides by the average * - * number of tracks per channel, so by storing the inverse I convert * - * this to a faster multiplication. Take this final number to the * - * place_cost_exp power -- numbers other than one mean this is no * - * longer a simple "average number of tracks"; it is some power of * - * that, allowing greater penalization of narrow channels. */ - for (int high = -1; high < grid_height; high++) { - for (int low = -1; low <= high; low++) { - /* Since we will divide the wiring cost by the average channel * - * capacity between high and low, having only 0 width channels * - * will result in infinite wiring capacity normalization * - * factor, and extremely bad placer behaviour. Hence we change * - * this to a small (1 track) channel capacity instead. */ - if (chanx_place_cost_fac_[high][low] == 0.0f) { - VTR_LOG_WARN("CHANX place cost fac is 0 at %d %d\n", high, low); - chanx_place_cost_fac_[high][low] = 1.0f; - } + const auto& device_ctx = g_vpr_ctx.device(); - chanx_place_cost_fac_[high][low] = (high - low + 1.) / chanx_place_cost_fac_[high][low]; - chanx_place_cost_fac_[high][low] = pow((double)chanx_place_cost_fac_[high][low], place_cost_exp); - } - } + const int grid_height = (int)device_ctx.grid.height(); + const int grid_width = (int)device_ctx.grid.width(); + + /* These arrays contain accumulative channel width between channel zero and + * the channel specified by the given index. The accumulated channel width + * is inclusive, meaning that it includes both channel zero and channel `idx`. + * To compute the total channel width between channels 'low' and 'high', use the + * following formula: + * acc_chan?_width_[high] - acc_chan?_width_[low - 1] + * This returns the total number of tracks between channels 'low' and 'high', + * including tracks in these channels. + * + * Channel -1 doesn't exist, so we can say it has zero tracks. We need to be able + * to access these arrays with index -1 to handle cases where the lower channel is 0. + */ + acc_chanx_width_ = vtr::NdOffsetMatrix({{{-1, grid_height}}}); + acc_chany_width_ = vtr::NdOffsetMatrix({{{-1, grid_width}}}); - /* Now do the same thing for the y-directed channels. First get the - * number of tracks between channel high and channel low, inclusive. */ - chany_place_cost_fac_[-1][-1] = 0; + // initialize the first element (index -1) with zero + acc_chanx_width_[-1] = 0; + for (int y = 0; y < grid_height; y++) { + acc_chanx_width_[y] = acc_chanx_width_[y - 1] + device_ctx.chan_width.x_list[y]; - for (int high = 0; high < grid_width; high++) { - chany_place_cost_fac_[high][high] = device_ctx.chan_width.y_list[high]; - for (int low = -1; low < high; low++) { - chany_place_cost_fac_[high][low] = chany_place_cost_fac_[high - 1][low] + device_ctx.chan_width.y_list[high]; + /* If the number of tracks in a channel is zero, two consecutive elements take the same + * value. This can lead to a division by zero in get_chanxy_cost_fac_(). To avoid this + * potential issue, we assume that the channel width is at least 1. + */ + if (acc_chanx_width_[y] == acc_chanx_width_[y - 1]) { + acc_chanx_width_[y]++; } } - /* Now compute the inverse of the average number of tracks per channel - * between high and low. Take to specified power. */ - for (int high = -1; high < grid_width; high++) { - for (int low = -1; low <= high; low++) { - /* Since we will divide the wiring cost by the average channel * - * capacity between high and low, having only 0 width channels * - * will result in infinite wiring capacity normalization * - * factor, and extremely bad placer behaviour. Hence we change * - * this to a small (1 track) channel capacity instead. */ - if (chany_place_cost_fac_[high][low] == 0.0f) { - VTR_LOG_WARN("CHANY place cost fac is 0 at %d %d\n", high, low); - chany_place_cost_fac_[high][low] = 1.0f; - } + // initialize the first element (index -1) with zero + acc_chany_width_[-1] = 0; + for (int x = 0; x < grid_width; x++) { + acc_chany_width_[x] = acc_chany_width_[x - 1] + device_ctx.chan_width.y_list[x]; - chany_place_cost_fac_[high][low] = (high - low + 1.) / chany_place_cost_fac_[high][low]; - chany_place_cost_fac_[high][low] = pow((double)chany_place_cost_fac_[high][low], place_cost_exp); + // to avoid a division by zero + if (acc_chany_width_[x] == acc_chany_width_[x - 1]) { + acc_chany_width_[x]++; } } @@ -239,33 +208,32 @@ void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { const size_t grid_height = device_ctx.grid.height(); const size_t grid_width = device_ctx.grid.width(); - - acc_tile_num_inter_die_conn_ = vtr::NdMatrix({grid_width, grid_height}, 0.); + acc_tile_num_inter_die_conn_ = vtr::NdMatrix({grid_width, grid_height}, 0); vtr::NdMatrix tile_num_inter_die_conn({grid_width, grid_height}, 0.); /* - * Step 1: iterate over the rr-graph, recording how many edges go between layers at each (x,y) location - * in the device. We count all these edges, regardless of which layers they connect. Then we divide by - * the number of layers - 1 to get the average cross-layer edge count per (x,y) location -- this mirrors - * what we do for the horizontal and vertical channels where we assume the channel width doesn't change - * along the length of the channel. It lets us be more memory-efficient for 3D devices, and could be revisited + * Step 1: iterate over the rr-graph, recording how many edges go between layers at each (x,y) location + * in the device. We count all these edges, regardless of which layers they connect. Then we divide by + * the number of layers - 1 to get the average cross-layer edge count per (x,y) location -- this mirrors + * what we do for the horizontal and vertical channels where we assume the channel width doesn't change + * along the length of the channel. It lets us be more memory-efficient for 3D devices, and could be revisited * if someday we have architectures with widely varying connectivity between different layers in a stack. - */ + */ /* - * To calculate the accumulative number of inter-die connections we first need to get the number of - * inter-die connection per location. To be able to work for the cases that RR Graph is read instead - * of being made from the architecture file, we calculate this number by iterating over the RR graph. Once - * tile_num_inter_die_conn is populated, we can start populating acc_tile_num_inter_die_conn_. First, - * we populate the first row and column. Then, we iterate over the rest of blocks and get the number of - * inter-die connections by adding up the number of inter-die block at that location + the accumulation - * for the block below and left to it. Then, since the accumulated number of inter-die connection to - * the block on the lower left connection of the block is added twice, that part needs to be removed. - */ - for (const auto& src_rr_node : rr_graph.nodes()) { - for (const auto& rr_edge_idx : rr_graph.edges(src_rr_node)) { - const auto& sink_rr_node = rr_graph.edge_sink_node(src_rr_node, rr_edge_idx); + * To calculate the accumulative number of inter-die connections we first need to get the number of + * inter-die connection per location. To be able to work for the cases that RR Graph is read instead + * of being made from the architecture file, we calculate this number by iterating over the RR graph. Once + * tile_num_inter_die_conn is populated, we can start populating acc_tile_num_inter_die_conn_. First, + * we populate the first row and column. Then, we iterate over the rest of blocks and get the number of + * inter-die connections by adding up the number of inter-die block at that location + the accumulation + * for the block below and left to it. Then, since the accumulated number of inter-die connection to + * the block on the lower left connection of the block is added twice, that part needs to be removed. + */ + for (const RRNodeId src_rr_node : rr_graph.nodes()) { + for (const t_edge_size rr_edge_idx : rr_graph.edges(src_rr_node)) { + const RRNodeId sink_rr_node = rr_graph.edge_sink_node(src_rr_node, rr_edge_idx); if (rr_graph.node_layer(src_rr_node) != rr_graph.node_layer(sink_rr_node)) { // We assume that the nodes driving the inter-layer connection or being driven by it // are not stretched across multiple tiles @@ -290,20 +258,20 @@ void NetCostHandler::alloc_and_load_for_fast_vertical_cost_update_() { // Initialize the first row and column for (size_t x = 1; x < device_ctx.grid.width(); x++) { acc_tile_num_inter_die_conn_[x][0] = acc_tile_num_inter_die_conn_[x-1][0] + - tile_num_inter_die_conn[x][0]; + tile_num_inter_die_conn[x][0]; } for (size_t y = 1; y < device_ctx.grid.height(); y++) { acc_tile_num_inter_die_conn_[0][y] = acc_tile_num_inter_die_conn_[0][y-1] + - tile_num_inter_die_conn[0][y]; + tile_num_inter_die_conn[0][y]; } for (size_t x_high = 1; x_high < device_ctx.grid.width(); x_high++) { for (size_t y_high = 1; y_high < device_ctx.grid.height(); y_high++) { acc_tile_num_inter_die_conn_[x_high][y_high] = acc_tile_num_inter_die_conn_[x_high-1][y_high] + - acc_tile_num_inter_die_conn_[x_high][y_high-1] + - tile_num_inter_die_conn[x_high][y_high] - - acc_tile_num_inter_die_conn_[x_high-1][y_high-1]; + acc_tile_num_inter_die_conn_[x_high][y_high-1] + + tile_num_inter_die_conn[x_high][y_high] - + acc_tile_num_inter_die_conn_[x_high-1][y_high-1]; } } } @@ -1421,7 +1389,7 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { const t_bb& bb = use_ts ? ts_bb_coord_new_[net_id] : placer_state_.move().bb_coords[net_id]; - double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); + const double crossing = wirelength_crossing_count(cluster_ctx.clb_nlist.net_pins(net_id).size()); /* Could insert a check for xmin == xmax. In that case, assume * * connection will be made with no bends and hence no x-cost. * @@ -1437,8 +1405,9 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { */ double ncost; - ncost = (bb.xmax - bb.xmin + 1) * chanx_place_cost_fac_[bb.ymax][bb.ymin - 1]; - ncost += (bb.ymax - bb.ymin + 1) * chany_place_cost_fac_[bb.xmax][bb.xmin - 1]; + const auto [chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb); + ncost = (bb.xmax - bb.xmin + 1) * chanx_cost_fac; + ncost += (bb.ymax - bb.ymin + 1) * chany_cost_fac; if (is_multi_layer_) { ncost += (bb.layer_max - bb.layer_min) * get_chanz_cost_factor_(bb); } @@ -1448,6 +1417,7 @@ double NetCostHandler::get_net_cube_bb_cost_(ClusterNetId net_id, bool use_ts) { return ncost; } + double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use_ts) { const auto& move_ctx = placer_state_.move(); @@ -1469,7 +1439,7 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use /* Adjust the bounding box half perimeter by the wirelength correction * factor based on terminal count, which is 1 for the source + the number * of sinks on this layer. */ - double crossing = wirelength_crossing_count(layer_pin_sink_count[layer_num] + 1); + const double crossing = wirelength_crossing_count(layer_pin_sink_count[layer_num] + 1); /* Could insert a check for xmin == xmax. In that case, assume * * connection will be made with no bends and hence no x-cost. * @@ -1484,11 +1454,10 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id , bool use * chan?_place_cost_fac_ objects can handle -1 indices internally. */ - ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * crossing - * chanx_place_cost_fac_[bb[layer_num].ymax][bb[layer_num].ymin - 1]; - - ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * crossing - * chany_place_cost_fac_[bb[layer_num].xmax][bb[layer_num].xmin - 1]; + const auto[chanx_cost_fac, chany_cost_fac] = get_chanxy_cost_fac_(bb[layer_num]); + ncost += (bb[layer_num].xmax - bb[layer_num].xmin + 1) * chanx_cost_fac; + ncost += (bb[layer_num].ymax - bb[layer_num].ymin + 1) * chany_cost_fac; + ncost *= crossing; } return ncost; @@ -1546,8 +1515,6 @@ double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) { } float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { - float place_cost_exp = placer_opts_.place_cost_exp; - int num_inter_dir_conn; if (bb.xmin == 0 && bb.ymin == 0) { @@ -1571,7 +1538,6 @@ float NetCostHandler::get_chanz_cost_factor_(const t_bb& bb) { } else { int bb_num_tiles = (bb.xmax - bb.xmin + 1) * (bb.ymax - bb.ymin + 1); z_cost_factor = bb_num_tiles / static_cast(num_inter_dir_conn); - z_cost_factor = pow((double)z_cost_factor, (double)place_cost_exp); } return z_cost_factor; diff --git a/vpr/src/place/net_cost_handler.h b/vpr/src/place/net_cost_handler.h index fd6c7a46767..e386e95eba4 100644 --- a/vpr/src/place/net_cost_handler.h +++ b/vpr/src/place/net_cost_handler.h @@ -122,9 +122,9 @@ class NetCostHandler { private: ///@brief Specifies whether the bounding box is computed using cube method or per-layer method. - bool cube_bb_ = false; + bool cube_bb_; ///@brief Determines whether the FPGA has multiple dies (layers) - bool is_multi_layer_ = false; + bool is_multi_layer_; ///@brief A reference to the placer's state to be updated by this object. PlacerState& placer_state_; ///@brief Contains some parameter that determine how the placement cost is computed. @@ -195,8 +195,9 @@ class NetCostHandler { * number of tracks in that direction; for other cost functions they * will never be used. */ - vtr::NdOffsetMatrix chanx_place_cost_fac_; // [-1...device_ctx.grid.width()-1] - vtr::NdOffsetMatrix chany_place_cost_fac_; // [-1...device_ctx.grid.height()-1] + vtr::NdOffsetMatrix acc_chanx_width_; // [-1...device_ctx.grid.width()-1] + vtr::NdOffsetMatrix acc_chany_width_; // [-1...device_ctx.grid.height()-1] + /** * @brief The matrix below is used to calculate a chanz_place_cost_fac based on the average channel width in * the cross-die-layer direction over a 2D (x,y) region. We don't assume the inter-die connectivity is the same at all (x,y) locations, so we @@ -445,13 +446,13 @@ class NetCostHandler { * @param bb_coord_new The new bb calculated by this function */ inline void update_bb_same_layer_(ClusterNetId net_id, - const t_physical_tile_loc& pin_old_loc, - const t_physical_tile_loc& pin_new_loc, - const std::vector& curr_bb_edge, - const std::vector& curr_bb_coord, - vtr::NdMatrixProxy bb_pin_sink_count_new, - std::vector& bb_edge_new, - std::vector& bb_coord_new); + const t_physical_tile_loc& pin_old_loc, + const t_physical_tile_loc& pin_new_loc, + const std::vector& curr_bb_edge, + const std::vector& curr_bb_coord, + vtr::NdMatrixProxy bb_pin_sink_count_new, + std::vector& bb_edge_new, + std::vector& bb_coord_new); /** * @brief Computes the bounding box from scratch using 2D bounding boxes (per-layer mode) @@ -509,6 +510,27 @@ class NetCostHandler { */ double get_net_wirelength_from_layer_bb_(ClusterNetId net_id); + /** + * @brief Computes the inverse of average channel width for horizontal and + * vertical channels within a bounding box. + * @tparam BBT This can be either t_bb or t_2D_bb. + * @param bb The bounding box for which the inverse of average channel width + * within the bounding box is computed. + * @return std::pair + * first -> The inverse of average channel width for horizontal channels. + * second -> The inverse of average channel width for vertical channels. + */ + template + std::pair get_chanxy_cost_fac_(const BBT& bb) { + const int total_chanx_width = acc_chanx_width_[bb.ymax] - acc_chanx_width_[bb.ymin - 1]; + const double inverse_average_chanx_width = (bb.ymax - bb.ymin + 1.0) / total_chanx_width; + + const int total_chany_width = acc_chany_width_[bb.xmax] - acc_chany_width_[bb.xmin - 1]; + const double inverse_average_chany_width = (bb.xmax - bb.xmin + 1.0) / total_chany_width; + + return {inverse_average_chanx_width, inverse_average_chany_width}; + } + /** * @brief Calculate the chanz cost factor based on the inverse of the average number of inter-die connections * in the given bounding box. This cost factor increases the placement cost for blocks that require inter-layer @@ -516,9 +538,9 @@ class NetCostHandler { * distributed across tiles, the cost factor will be the same for all bounding boxes, but it will still * weight z-directed vs. x- and y-directed connections appropriately. * - * @param bounding_box Bounding box of the net which chanz cost factor is to be calculated + * @param bb Bounding box of the net which chanz cost factor is to be calculated * @return ChanZ cost factor */ - float get_chanz_cost_factor_(const t_bb& bounding_box); + float get_chanz_cost_factor_(const t_bb& bb); }; diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index 0241f19b910..5c2fe15f28f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -2,4 +2,4 @@ k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.91 vpr 65.59 MiB -1 -1 0.21 21296 3 0.05 -1 -1 39652 -1 -1 69 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67160 99 130 353 483 1 220 299 13 13 169 clb auto 26.9 MiB 0.03 692 29270 3600 8725 16945 65.6 MiB 0.03 0.00 30 1400 11 3.33e+06 2.19e+06 408126. 2414.95 1.08 k4_N10_memSize16384_memData64.xml diffeq1.v common 4.43 vpr 69.27 MiB -1 -1 0.31 26352 23 0.22 -1 -1 41100 -1 -1 71 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70936 162 96 1200 1141 1 688 334 13 13 169 clb auto 30.2 MiB 0.11 5199 75604 21039 49822 4743 69.3 MiB 0.10 0.00 54 10333 34 3.33e+06 2.58e+06 696024. 4118.48 2.85 k4_N10_memSize16384_memData64.xml single_wire.v common 0.25 vpr 63.52 MiB -1 -1 0.05 19840 1 0.01 -1 -1 35512 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65048 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.26 vpr 63.64 MiB -1 -1 0.06 19968 1 0.01 -1 -1 35756 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65172 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 9 4 1 4 63.6 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01 + k4_N10_memSize16384_memData64.xml single_ff.v common 0.26 vpr 63.64 MiB -1 -1 0.06 19968 1 0.01 -1 -1 35756 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65172 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 9 4 1 4 63.6 MiB 0.00 0.00 18 5 1 30000 30000 3112.78 345.864 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt index 9c8e3fb5217..fc925eb26dd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic_odin/basic_no_timing/config/golden_results.txt @@ -2,4 +2,4 @@ k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.31 vpr 65.73 MiB 0.02 9472 -1 -1 4 0.19 -1 -1 42360 -1 -1 72 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67304 99 130 378 508 1 260 302 13 13 169 clb auto 27.0 MiB 0.03 975 80250 22205 36468 21577 65.7 MiB 0.08 0.00 36 1771 10 3.33e+06 2.28e+06 481319. 2848.04 0.42 k4_N10_memSize16384_memData64.xml diffeq1.v common 3.61 vpr 69.33 MiB 0.02 9472 -1 -1 23 0.20 -1 -1 41432 -1 -1 72 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70992 162 96 1214 1147 1 676 335 13 13 169 clb auto 30.4 MiB 0.12 4968 89886 25356 58643 5887 69.3 MiB 0.12 0.00 52 9486 14 3.33e+06 2.61e+06 671819. 3975.26 2.33 k4_N10_memSize16384_memData64.xml single_wire.v common 0.21 vpr 63.40 MiB 0.01 5888 -1 -1 1 0.01 -1 -1 35384 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64920 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.4 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 - k4_N10_memSize16384_memData64.xml single_ff.v common 0.20 vpr 63.39 MiB 0.01 5760 -1 -1 1 0.01 -1 -1 33768 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64916 2 1 3 4 1 3 4 3 3 9 -1 auto 25.1 MiB 0.00 6 9 4 1 4 63.4 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01 + k4_N10_memSize16384_memData64.xml single_ff.v common 0.20 vpr 63.39 MiB 0.01 5760 -1 -1 1 0.01 -1 -1 33768 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64916 2 1 3 4 1 3 4 3 3 9 -1 auto 25.1 MiB 0.00 6 9 4 1 4 63.4 MiB 0.00 0.00 18 5 1 30000 30000 3112.78 345.864 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt index 28a1bb52736..c5e2acb803a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.48876 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.6599674 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index e7a944100ab..70910d2d59a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,8 +1,8 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.30 vpr 57.61 MiB -1 -1 0.06 19388 1 0.02 -1 -1 33516 -1 -1 1 2 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 58988 2 1 3 4 1 3 4 3 3 9 -1 auto 19.1 MiB 0.00 4 9 6 3 0 57.6 MiB 0.00 0.00 0.55447 -0.91031 -0.55447 0.55447 0.00 1.4209e-05 1.0635e-05 0.000112608 8.885e-05 -1 2 1 18000 18000 14049.7 1561.07 0.00 0.00111531 0.00103596 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.30 vpr 57.69 MiB -1 -1 0.06 19244 1 0.02 -1 -1 33536 -1 -1 1 2 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 59076 2 1 3 4 1 3 4 3 3 9 -1 auto 19.2 MiB 0.00 6 9 5 2 2 57.7 MiB 0.00 0.00 0.48631 -0.91031 -0.48631 0.48631 0.00 1.4475e-05 1.0195e-05 0.000102982 7.9111e-05 -1 4 1 18000 18000 15707.9 1745.32 0.00 0.00110914 0.00104203 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 26.57 parmys 203.92 MiB -1 -1 21.33 208816 2 1.49 -1 -1 61188 -1 -1 155 5 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61088 5 156 191 347 1 163 316 15 15 225 clb auto 21.3 MiB 0.03 22 75566 54444 2848 18274 59.7 MiB 0.07 0.00 1.49664 -15.129 -1.49664 1.49664 0.00 0.000225009 0.000209684 0.0166386 0.0154931 -1 38 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0221087 0.0205962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 26.99 parmys 204.15 MiB -1 -1 21.52 209052 2 1.49 -1 -1 60656 -1 -1 155 5 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 60972 5 156 191 347 1 163 316 15 15 225 clb auto 21.3 MiB 0.03 25 77716 55619 3345 18752 59.5 MiB 0.13 0.00 1.47823 -14.9031 -1.47823 1.47823 0.00 0.000388878 0.000358886 0.0289108 0.0266306 -1 38 3 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0351201 0.0324031 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 26.57 parmys 203.92 MiB -1 -1 21.33 208816 2 1.49 -1 -1 61188 -1 -1 155 5 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 61088 5 156 191 347 1 163 316 15 15 225 clb auto 21.3 MiB 0.03 22 75566 54444 2848 18274 59.7 MiB 0.07 0.00 1.49664 -15.129 -1.49664 1.49664 0.00 0.000225009 0.000209684 0.0166386 0.0154931 -1 57 6 3.042e+06 2.79e+06 863192. 3836.41 0.01 0.0221087 0.0205962 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 26.99 parmys 204.15 MiB -1 -1 21.52 209052 2 1.49 -1 -1 60656 -1 -1 155 5 -1 -1 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 60972 5 156 191 347 1 163 316 15 15 225 clb auto 21.3 MiB 0.03 25 77716 55619 3345 18752 59.5 MiB 0.13 0.00 1.47823 -14.9031 -1.47823 1.47823 0.00 0.000388878 0.000358886 0.0289108 0.0266306 -1 57 3 3.042e+06 2.79e+06 892591. 3967.07 0.01 0.0351201 0.0324031 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.35 vpr 63.08 MiB -1 -1 0.08 19324 1 0.02 -1 -1 33472 -1 -1 1 2 0 0 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64592 2 1 3 4 1 3 4 3 3 9 -1 auto 24.5 MiB 0.00 4 9 6 2 1 63.1 MiB 0.00 0.00 0.55247 -0.90831 -0.55247 0.55247 0.00 1.3129e-05 9.703e-06 0.000103951 8.1123e-05 -1 2 2 53894 53894 12370.0 1374.45 0.00 0.00116445 0.00109439 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.35 vpr 62.96 MiB -1 -1 0.08 19876 1 0.02 -1 -1 33484 -1 -1 1 2 0 0 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64468 2 1 3 4 1 3 4 3 3 9 -1 auto 24.3 MiB 0.00 6 9 5 2 2 63.0 MiB 0.00 0.00 0.48631 -0.90831 -0.48631 0.48631 0.00 1.5477e-05 1.1104e-05 0.000110622 8.6576e-05 -1 8 1 53894 53894 14028.3 1558.70 0.00 0.00113491 0.00106717 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 6.10 vpr 71.24 MiB -1 -1 1.09 28164 2 0.15 -1 -1 37372 -1 -1 32 311 15 0 success 84e0337 release IPO VTR_ASSERT_LEVEL=3 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2024-08-22T23:40:08 gh-actions-runner-vtr-auto-spawned3 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 72952 311 156 972 1128 1 953 514 28 28 784 memory auto 33.0 MiB 0.48 8979 193966 70726 114124 9116 71.2 MiB 1.31 0.03 4.11528 -4394.91 -4.11528 4.11528 0.00 0.00488787 0.00418834 0.465058 0.395185 -1 13380 12 4.25198e+07 9.94461e+06 2.96205e+06 3778.13 0.38 0.643724 0.557601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 5d73f4813a6..70dd1dd8ee6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 vpr 60.11 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61552 3 1 5 6 1 4 5 3 3 9 -1 auto 21.6 MiB 0.00 9 12 1 9 2 60.1 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.0349e-05 7.103e-06 8.7732e-05 6.8547e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.00111687 0.00105846 379 725 -1 6 1 3 3 36 25 0.605178 0.605178 -1.1507 -0.605178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00107362 0.00104552 - k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61420 2 1 4 5 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.4366e-05 1.0429e-05 0.000128779 0.000106057 20 9 1 53894 53894 4880.82 542.314 0.00 0.00110538 0.00104614 379 725 -1 5 1 2 2 25 19 0.940178 0.940178 -1.48482 -0.940178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106677 0.00104008 + k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:42:01 fv-az1118-845 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61420 2 1 4 5 1 3 4 3 3 9 -1 auto 21.6 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.4366e-05 1.0429e-05 0.000128779 0.000106057 20 9 1 53894 53894 4880.82 542.314 0.00 0.00110538 0.00104614 379 725 -1 15 1 2 2 25 19 1.6923204 1.6923204 -2.22723 -1.6923204 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106677 0.00104008 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index 0a6d9b6d152..b9704023605 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -4,4 +4,4 @@ k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.26 vpr 62.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64360 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 20 30 10 18 2 62.9 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 3.7729e-05 2.5928e-05 0.000260113 0.000177741 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00195031 0.00174505 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00183013 0.00171342 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.26 vpr 62.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64484 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 20 30 11 18 1 63.0 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 3.8442e-05 2.5618e-05 0.00023637 0.000176478 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00229296 0.00202345 564 862 -1 15 8 21 21 324 150 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00192818 0.00176248 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.26 vpr 62.90 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64408 5 3 11 14 2 9 10 4 4 16 clb auto 24.4 MiB 0.01 20 30 8 18 4 62.9 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 4.1447e-05 3.1048e-05 0.000250166 0.000200113 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.01 0.0023527 0.00209277 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00169051 0.00161308 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.25 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64488 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 21 100 23 56 21 63.0 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.0426e-05 2.4245e-05 0.000455896 0.00036643 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00222626 0.00202944 564 862 -1 20 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00168704 0.00161249 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.25 vpr 62.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:43:23 fv-az801-114 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64488 5 3 11 14 2 9 10 4 4 16 clb auto 24.5 MiB 0.00 21 100 23 56 21 63.0 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.0426e-05 2.4245e-05 0.000455896 0.00036643 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00222626 0.00202944 564 862 -1 36 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00168704 0.00161249 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 0dd1983f59b..3a406d5970c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,12 +1,12 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time EArch.xml styr.blif common_--target_ext_pin_util_1 1.22 vpr 64.26 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65800 10 10 168 178 1 73 31 6 6 36 clb auto 25.7 MiB 0.14 407 463 89 357 17 64.3 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000635562 0.000587698 0.00980998 0.00922481 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.42 0.143103 0.121539 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0295304 0.0261483 EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.36 vpr 64.14 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65684 10 10 168 178 1 73 31 6 6 36 clb auto 25.5 MiB 0.12 407 463 89 357 17 64.1 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000630926 0.000582868 0.00981682 0.00922691 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.199297 0.168347 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0297651 0.0264108 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.77 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66168 10 10 168 178 1 162 111 14 14 196 clb auto 25.8 MiB 0.83 1425 5963 761 4903 299 64.6 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.41 0.000628333 0.000580338 0.0171828 0.0159216 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 295730. 1508.82 1.29 0.0929065 0.0799229 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.09 0.06 0.06 -1 -1 0.09 0.0204062 0.0180589 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.77 vpr 64.62 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66168 10 10 168 178 1 162 111 14 14 196 clb auto 25.8 MiB 0.83 1425 5963 761 4903 299 64.6 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.41 0.000628333 0.000580338 0.0171828 0.0159216 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 384449. 1961.47 1.29 0.0929065 0.0799229 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.09 0.06 0.06 -1 -1 0.09 0.0204062 0.0180589 EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.26 vpr 64.21 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65752 10 10 168 178 1 75 33 7 7 49 clb auto 25.7 MiB 0.17 406 657 105 529 23 64.2 MiB 0.02 0.00 2.37613 -26.9385 -2.37613 2.37613 0.06 0.000635754 0.000588385 0.0117044 0.0109781 -1 -1 -1 -1 26 1250 31 1.07788e+06 700622 75813.7 1547.22 0.30 0.101986 0.0876865 3816 13734 -1 911 16 447 1582 77100 25463 2.91114 2.91114 -35.9881 -2.91114 0 0 91376.6 1864.83 0.02 0.05 0.01 -1 -1 0.02 0.0271559 0.0242615 EArch.xml styr.blif common_--target_ext_pin_util_0.0 3.71 vpr 64.85 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66408 10 10 168 178 1 163 124 14 14 196 clb auto 26.0 MiB 0.97 1418 6922 992 5687 243 64.9 MiB 0.05 0.00 3.05445 -36.9858 -3.05445 3.05445 0.42 0.000635632 0.000586828 0.0170342 0.0157603 -1 -1 -1 -1 24 2880 12 9.20055e+06 5.60498e+06 355930. 1815.97 1.01 0.0998456 0.0858149 18592 71249 -1 2826 12 527 2385 139582 29980 3.66329 3.66329 -43.9798 -3.66329 0 0 449262. 2292.15 0.11 0.05 0.07 -1 -1 0.11 0.0202055 0.0179411 EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.33 vpr 64.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65708 10 10 168 178 1 73 31 6 6 36 clb auto 25.6 MiB 0.14 407 463 89 357 17 64.2 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000637222 0.000589815 0.00986031 0.00927104 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.54 0.202892 0.171821 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.03 0.01 -1 -1 0.01 0.0188685 0.0172348 EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.41 vpr 64.06 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65600 10 10 168 178 1 73 31 6 6 36 clb auto 25.5 MiB 0.16 407 463 89 357 17 64.1 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000644635 0.000597098 0.0102053 0.0096131 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.20199 0.170925 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0296093 0.026251 -EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.94 vpr 64.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66364 10 10 168 178 1 162 111 14 14 196 clb auto 26.0 MiB 0.88 1425 5963 761 4903 299 64.8 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.42 0.00065084 0.000601408 0.0175552 0.0162626 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 295730. 1508.82 1.31 0.0953188 0.0822017 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.10 0.06 0.06 -1 -1 0.10 0.0213208 0.0188927 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.94 vpr 64.81 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66364 10 10 168 178 1 162 111 14 14 196 clb auto 26.0 MiB 0.88 1425 5963 761 4903 299 64.8 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.42 0.00065084 0.000601408 0.0175552 0.0162626 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 384449. 1961.47 1.31 0.0953188 0.0822017 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.10 0.06 0.06 -1 -1 0.10 0.0213208 0.0188927 EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.36 vpr 63.78 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65308 10 10 168 178 1 73 31 6 6 36 clb auto 25.2 MiB 0.13 407 463 89 357 17 63.8 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000634693 0.000587229 0.00982727 0.00924077 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.200884 0.169805 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0297589 0.0264115 EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.17 vpr 25.53 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 26140 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 23.4 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.17 vpr 25.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11548-gf337eb353 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:12:21 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 26476 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 24.0 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt index 28a1bb52736..ce46084d4cd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_clock_buf/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.48876 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm_clk_buf.xml multiclock_buf.blif common 1.65996 0.545 -1 -1 -1 0.545 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.293 -1 -1 -1 0.293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt index f922c82810e..24a98bd463d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61424 3 1 5 6 1 4 5 3 3 9 -1 auto 21.5 MiB 0.00 9 12 1 9 2 60.0 MiB 0.00 0.00 0.52647 -0.88231 -0.52647 0.52647 0.00 1.035e-05 7.094e-06 8.8915e-05 6.9209e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.0011057 0.00104635 379 725 -1 6 1 3 3 36 25 0.605178 0.605178 -1.1507 -0.605178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00105006 0.00102258 - k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61424 2 1 4 5 1 3 4 3 3 9 -1 auto 21.5 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0129e-05 6.963e-06 0.000104936 8.568e-05 20 9 1 53894 53894 4880.82 542.314 0.00 0.00111784 0.00105927 379 725 -1 5 1 2 2 25 19 0.940178 0.940178 -1.48482 -0.940178 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106769 0.00103834 + k6_frac_N10_40nm.xml conn_order.eblif common 0.12 vpr 59.98 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success e1c7cb1 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-24T03:47:29 fv-az775-518 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 61424 2 1 4 5 1 3 4 3 3 9 -1 auto 21.5 MiB 0.00 6 9 2 3 4 60.0 MiB 0.00 0.00 0.69084 -1.21731 -0.69084 0.69084 0.00 1.0129e-05 6.963e-06 0.000104936 8.568e-05 20 9 1 53894 53894 4880.82 542.314 0.00 0.00111784 0.00105927 379 725 -1 15 1 2 2 25 19 1.701722 1.701722 -2.22723 -1.701722 0 0 6579.40 731.044 0.00 0.00 0.00 -1 -1 0.00 0.00106769 0.00103834 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt index e6e7c8778e5..3813343ed35 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time x_gaussian_y_uniform.xml stereovision3.v common 1.42 vpr 65.81 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37836 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67388 11 30 262 292 2 110 54 7 7 49 clb auto 27.0 MiB 0.12 431 2298 449 1774 75 65.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000483914 0.000384949 0.0147089 0.012636 -1 -1 -1 -1 12 326 3 1.07788e+06 700622 -1 -1 0.20 0.0742174 0.0638404 2680 3516 -1 316 3 175 255 10988 5508 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0145719 0.0139138 x_uniform_y_gaussian.xml stereovision3.v common 1.44 vpr 65.54 MiB 0.05 9856 -1 -1 4 0.17 -1 -1 37820 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67108 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.11 392 1890 346 1476 68 65.5 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000458868 0.000376323 0.0123402 0.0106294 -1 -1 -1 -1 12 287 5 1.07788e+06 700622 -1 -1 0.21 0.0867101 0.074128 2680 3516 -1 268 3 167 248 10043 4782 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.015461 0.0147632 - x_gaussian_y_gaussian.xml stereovision3.v common 1.50 vpr 65.58 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37476 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67156 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.12 398 2196 430 1697 69 65.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000468656 0.000387965 0.0139473 0.0119918 -1 -1 -1 -1 12 284 8 1.07788e+06 700622 -1 -1 0.28 0.0788417 0.0678402 2680 3516 -1 273 3 184 266 11521 5744 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0151497 0.0144591 + x_gaussian_y_gaussian.xml stereovision3.v common 1.50 vpr 65.58 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37476 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67156 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.12 398 2196 430 1697 69 65.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000468656 0.000387965 0.0139473 0.0119918 -1 -1 -1 -1 16 284 8 1.07788e+06 700622 -1 -1 0.28 0.0788417 0.0678402 2680 3516 -1 273 3 184 266 11521 5744 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0151497 0.0144591 x_delta_y_uniform.xml stereovision3.v common 1.67 vpr 65.78 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 40712 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67356 11 30 262 292 2 110 54 7 7 49 clb auto 27.0 MiB 0.11 474 1992 348 1574 70 65.8 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000450631 0.000369149 0.0127092 0.0109666 -1 -1 -1 -1 48 367 4 1.07788e+06 700622 -1 -1 0.46 0.187113 0.157611 2680 3516 -1 363 2 162 240 11458 5656 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0141159 0.0135524 x_delta_y_delta.xml stereovision3.v common 1.41 vpr 65.68 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 38292 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67260 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.12 411 2094 373 1653 68 65.7 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000478875 0.000382715 0.0140865 0.0122714 -1 -1 -1 -1 48 306 4 1.07788e+06 700622 -1 -1 0.20 0.107373 0.0919185 2680 3516 -1 300 3 176 263 11898 5867 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.014938 0.0142467 x_uniform_y_delta.xml stereovision3.v common 1.47 vpr 65.57 MiB 0.05 9984 -1 -1 4 0.17 -1 -1 37488 -1 -1 13 11 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67144 11 30 262 292 2 110 54 7 7 49 clb auto 26.9 MiB 0.11 405 2196 394 1718 84 65.6 MiB 0.03 0.00 1.91988 -135.359 -1.91988 1.85222 0.01 0.000448588 0.000370342 0.0136716 0.0117962 -1 -1 -1 -1 58 286 2 1.07788e+06 700622 -1 -1 0.28 0.112457 0.0956247 2680 3516 -1 286 2 161 239 8848 4226 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.00 0.03 0.00 -1 -1 0.00 0.0140539 0.0134498 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt index 962dab28b44..1ae1f7fe791 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_sdc/config/golden_results.txt @@ -4,4 +4,4 @@ k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.25 vpr 63.10 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64612 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 10 18 2 63.1 MiB 0.00 0.00 0.645658 -2.18842 -0.645658 0.571 0.01 3.9483e-05 2.7812e-05 0.000241821 0.000190264 -1 -1 -1 -1 8 17 3 107788 107788 4794.78 299.674 0.01 0.00193712 0.00176247 564 862 -1 14 5 15 15 285 110 0.571526 0.571 -1.89284 -0.571526 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00179303 0.00167797 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.25 vpr 62.99 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64500 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 11 18 1 63.0 MiB 0.00 0.00 1.64534 -5.31677 -1.64534 0.571 0.01 4.3501e-05 2.9475e-05 0.000247333 0.000183292 -1 -1 -1 -1 8 17 8 107788 107788 4794.78 299.674 0.01 0.00222242 0.00195057 564 862 -1 15 8 21 21 324 150 1.57153 0.571 -4.91875 -1.57153 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.0019705 0.00180493 k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.25 vpr 63.02 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64536 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 20 30 8 18 4 63.0 MiB 0.00 0.00 1.44871 -2.90839 -1.44871 0.571 0.01 4.0285e-05 2.9986e-05 0.000237512 0.000186077 -1 -1 -1 -1 8 33 10 107788 107788 4794.78 299.674 0.01 0.00230311 0.00203041 564 862 -1 19 2 11 11 275 141 1.39454 0.571 -2.72425 -1.39454 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00171065 0.00163028 - k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.24 vpr 62.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64376 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 21 100 23 56 21 62.9 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.1088e-05 2.4636e-05 0.000450966 0.000361847 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00226169 0.0020643 564 862 -1 20 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164492 0.00157611 + k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.24 vpr 62.87 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success 30aea82 Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.5.0-1025-azure x86_64 2024-10-28T23:46:21 fv-az1380-902 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64376 5 3 11 14 2 9 10 4 4 16 clb auto 24.7 MiB 0.00 21 100 23 56 21 62.9 MiB 0.00 0.00 0.145339 0 0 0.571 0.01 3.1088e-05 2.4636e-05 0.000450966 0.000361847 -1 -1 -1 -1 8 22 3 107788 107788 4794.78 299.674 0.01 0.00226169 0.0020643 564 862 -1 36 2 9 9 213 106 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.00 0.00 -1 -1 0.00 0.00164492 0.00157611 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt index 7a574b24ac2..1135db78e8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_target_pin_util/config/golden_results.txt @@ -1,12 +1,12 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time EArch.xml styr.blif common_--target_ext_pin_util_1 1.35 vpr 63.50 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65020 10 10 168 178 1 73 31 6 6 36 clb auto 24.8 MiB 0.14 407 463 89 357 17 63.5 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000639236 0.000591353 0.00984498 0.00926038 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.203286 0.17206 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0294657 0.0261082 EArch.xml styr.blif common_--target_ext_pin_util_0.7 1.36 vpr 63.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64884 10 10 168 178 1 73 31 6 6 36 clb auto 24.6 MiB 0.14 407 463 89 357 17 63.4 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000639716 0.000592026 0.0099357 0.0093488 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.201688 0.170527 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0298547 0.02646 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.94 vpr 64.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65592 10 10 168 178 1 162 111 14 14 196 clb auto 24.9 MiB 0.89 1425 5963 761 4903 299 64.1 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.42 0.000636581 0.000587323 0.0172709 0.0159953 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 295730. 1508.82 1.35 0.0957477 0.0825025 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.10 0.06 0.06 -1 -1 0.10 0.0212067 0.0187473 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 3.94 vpr 64.05 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65592 10 10 168 178 1 162 111 14 14 196 clb auto 24.9 MiB 0.89 1425 5963 761 4903 299 64.1 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.42 0.000636581 0.000587323 0.0172709 0.0159953 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 384449. 1961.47 1.35 0.0957477 0.0825025 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.10 0.06 0.06 -1 -1 0.10 0.0212067 0.0187473 EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.23 vpr 63.33 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64852 10 10 168 178 1 75 33 7 7 49 clb auto 24.6 MiB 0.17 406 657 105 529 23 63.3 MiB 0.02 0.00 2.37613 -26.9385 -2.37613 2.37613 0.06 0.00063646 0.000588776 0.0117407 0.0110135 -1 -1 -1 -1 26 1250 31 1.07788e+06 700622 75813.7 1547.22 0.31 0.101863 0.0875653 3816 13734 -1 911 16 447 1582 77100 25463 2.91114 2.91114 -35.9881 -2.91114 0 0 91376.6 1864.83 0.02 0.05 0.01 -1 -1 0.02 0.0271153 0.0242202 EArch.xml styr.blif common_--target_ext_pin_util_0.0 3.63 vpr 64.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 104 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65544 10 10 168 178 1 163 124 14 14 196 clb auto 25.2 MiB 0.96 1418 6922 992 5687 243 64.0 MiB 0.05 0.00 3.05445 -36.9858 -3.05445 3.05445 0.41 0.000641634 0.000592847 0.017123 0.0158404 -1 -1 -1 -1 24 2880 12 9.20055e+06 5.60498e+06 355930. 1815.97 1.01 0.0995734 0.0854586 18592 71249 -1 2826 12 527 2385 139582 29980 3.66329 3.66329 -43.9798 -3.66329 0 0 449262. 2292.15 0.11 0.05 0.07 -1 -1 0.11 0.020324 0.0180622 EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7 1.38 vpr 63.12 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64640 10 10 168 178 1 73 31 6 6 36 clb auto 24.5 MiB 0.14 407 463 89 357 17 63.1 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000633422 0.000585646 0.0098961 0.00929741 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.202108 0.171036 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0303475 0.0269842 EArch.xml styr.blif common_--target_ext_pin_util_clb_0.7_0.8 1.35 vpr 63.32 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64836 10 10 168 178 1 73 31 6 6 36 clb auto 24.7 MiB 0.14 407 463 89 357 17 63.3 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000638094 0.000590083 0.00989619 0.00930981 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.200907 0.169845 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0298866 0.0264679 -EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.84 vpr 63.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65376 10 10 168 178 1 162 111 14 14 196 clb auto 24.8 MiB 0.87 1425 5963 761 4903 299 63.8 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.41 0.000641613 0.000592378 0.0171905 0.0159105 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 295730. 1508.82 1.29 0.0945882 0.0814975 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.09 0.06 0.06 -1 -1 0.09 0.0210426 0.0186659 +EArch.xml styr.blif common_--target_ext_pin_util_clb_0.1_0.8 3.84 vpr 63.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 91 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 65376 10 10 168 178 1 162 111 14 14 196 clb auto 24.8 MiB 0.87 1425 5963 761 4903 299 63.8 MiB 0.05 0.00 3.12847 -37.0503 -3.12847 3.12847 0.41 0.000641613 0.000592378 0.0171905 0.0159105 -1 -1 -1 -1 20 2956 16 9.20055e+06 4.90435e+06 384449. 1961.47 1.29 0.0945882 0.0814975 18004 60473 -1 2785 13 638 2511 146344 31166 3.597 3.597 -45.2096 -3.597 0 0 387483. 1976.95 0.09 0.06 0.06 -1 -1 0.09 0.0210426 0.0186659 EArch.xml styr.blif common_--target_ext_pin_util_io_0.1,0.1_clb_0.7_0.8,1.0 1.34 vpr 63.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 64912 10 10 168 178 1 73 31 6 6 36 clb auto 24.7 MiB 0.14 407 463 89 357 17 63.4 MiB 0.02 0.00 2.36035 -27.3667 -2.36035 2.36035 0.04 0.000641471 0.000587156 0.009815 0.00922212 -1 -1 -1 -1 32 838 28 646728 592834 58122.9 1614.52 0.53 0.200614 0.16952 2724 10283 -1 702 19 470 1535 59936 21931 2.39503 2.39503 -32.2138 -2.39503 0 0 70489.2 1958.03 0.01 0.05 0.01 -1 -1 0.01 0.0302449 0.0267933 EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.12 vpr 24.80 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 25396 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 22.7 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.14 vpr 24.97 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-11548-gf337eb353-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-10-12T10:23:35 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 25568 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 22.9 MiB 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1