From b4be0a53c9a6dea7a4631c2b490303b1c797f629 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Tue, 16 Jul 2024 07:24:02 -0700 Subject: [PATCH 01/12] changed the architecture parser to allow definition of mux_inc and mux_dec for specifiying different switches for wires with different direction --- libs/libarchfpga/src/physical_types.h | 14 +++- libs/libarchfpga/src/read_xml_arch_file.cpp | 88 +++++++++++++++++---- 2 files changed, 82 insertions(+), 20 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 422fb107535..47c197690c9 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1561,6 +1561,12 @@ enum e_Fc_type { * relation to the switches from the architecture file, * * not the expanded list of switches that is built * * at the end of build_rr_graph * + * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for * + * decremental tracks if it is specified in the * + * architecture file. * + * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for * + * decremental tracks if it is specified in the * + * architecture file * * * * @param arch_opin_between_dice_switch: Index of the switch type that * * connects output pins (OPINs) *to* this segment from * @@ -1579,14 +1585,14 @@ enum e_Fc_type { * Cmetal: Capacitance of a routing track, per unit logic block length. * * Rmetal: Resistance of a routing track, per unit logic block length. * * (UDSD by AY) drivers: How do signals driving a routing track connect to * - * the track? + * the track? * * seg_index: The index of the segment as stored in the appropriate Segs list* * Upon loading the architecture, we use this field to keep track * * the segment's index in the unified segment_inf vector. This is * * useful when building the rr_graph for different Y & X channels * - * in terms of track distribution and segment type. * + * in terms of track distribution and segment type. * * res_type: Determines the routing network to which the segment belongs. * - * Possible values are: + * Possible values are: * * - GENERAL: The segment is part of the general routing * * resources. * * - GCLK: The segment is part of the global routing network. * @@ -1600,6 +1606,8 @@ struct t_segment_inf { int length; short arch_wire_switch; short arch_opin_switch; + short arch_wire_switch_dec; + short arch_opin_switch_dec; short arch_opin_between_dice_switch = -1; float frac_cb; float frac_sb; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 359a5410b0c..f3a9ffaa683 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -3766,6 +3766,10 @@ static void ProcessSegments(pugi::xml_node Parent, //Unidir requires the following tags expected_subtags.emplace_back("mux"); expected_subtags.emplace_back("mux_inter_die"); + //with the following two tags, we can allow the architecture file to define + //different muxes with different delays for wires with different directions + expected_subtags.emplace_back("mux_inc"); + expected_subtags.emplace_back("mux_dec"); } else { @@ -3796,28 +3800,78 @@ static void ProcessSegments(pugi::xml_node Parent, /* Get the wire and opin switches, or mux switch if unidir */ if (UNI_DIRECTIONAL == Segs[i].directionality) { //Get the switch name for same die wire and track connections - SubElem = get_single_child(Node, "mux", loc_data); - tmp = get_attribute(SubElem, "name", loc_data).value(); - - /* Match names */ - for (j = 0; j < NumSwitches; ++j) { - if (0 == strcmp(tmp, Switches[j].name.c_str())) { - break; /* End loop so j is where we want it */ + SubElem = get_single_child(Node, "mux", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + + //check if tag is defined in the architecture, otherwise we should look for and + if(tmp){ + /* Match names */ + for (j = 0; j < NumSwitches; ++j) { + if (0 == strcmp(tmp, Switches[j].name.c_str())) { + break; /* End loop so j is where we want it */ + } } + if (j >= NumSwitches) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "'%s' is not a valid mux name.\n", tmp); + } + + /* Unidir muxes must have the same switch + * for wire and opin fanin since there is + * really only the mux in unidir. */ + Segs[i].arch_wire_switch = j; + Segs[i].arch_opin_switch = j; } - if (j >= NumSwitches) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), - "'%s' is not a valid mux name.\n", tmp); - } + else { //if a general mux is not defined, we should look for specific mux for each direction in the architecture file + SubElem = get_single_child(Node, "mux_inc", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if(!tmp){ + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else{ + /* Match names */ + for (j = 0; j < NumSwitches; ++j) { + if (0 == strcmp(tmp, Switches[j].name.c_str())) { + break; /* End loop so j is where we want it */ + } + } + if (j >= NumSwitches) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "'%s' is not a valid mux name.\n", tmp); + } - /* Unidir muxes must have the same switch - * for wire and opin fanin since there is - * really only the mux in unidir. */ - Segs[i].arch_wire_switch = j; - Segs[i].arch_opin_switch = j; + /* Unidir muxes must have the same switch + * for wire and opin fanin since there is + * really only the mux in unidir. */ + Segs[i].arch_wire_switch = j; + Segs[i].arch_opin_switch = j; + } - } + SubElem = get_single_child(Node, "mux_dec", loc_data, ReqOpt::OPTIONAL); + tmp = get_attribute(SubElem, "name", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if(!tmp){ + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "if mux is not specified in a wire segment, both mux_inc and mux_dec should be specified"); + } else{ + /* Match names */ + for (j = 0; j < NumSwitches; ++j) { + if (0 == strcmp(tmp, Switches[j].name.c_str())) { + break; /* End loop so j is where we want it */ + } + } + if (j >= NumSwitches) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(SubElem), + "'%s' is not a valid mux name.\n", tmp); + } + /* Unidir muxes must have the same switch + * for wire and opin fanin since there is + * really only the mux in unidir. */ + Segs[i].arch_wire_switch_dec = j; + Segs[i].arch_opin_switch_dec = j; + } + } + } else { VTR_ASSERT(BI_DIRECTIONAL == Segs[i].directionality); SubElem = get_single_child(Node, "wire_switch", loc_data); From 5ea2e5399a30372e13ac3b74bce4069caadbaaf1 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Tue, 16 Jul 2024 08:12:52 -0700 Subject: [PATCH 02/12] changed the RR graph switch selection for wires with different directions --- vpr/src/route/rr_graph2.cpp | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index f77839736a4..4e44d105968 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -300,7 +300,8 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, * as they will not be staggered by different segment start points. */ int cur_track, ntracks, itrack, length, j, index; - int arch_wire_switch, arch_opin_switch, fac, num_sets, tmp; + int fac, num_sets, tmp; + int arch_wire_switch, arch_opin_switch, arch_wire_switch_dec, arch_opin_switch_dec; int arch_opin_between_dice_switch; int group_start, first_track; std::unique_ptr sets_per_seg_type; @@ -352,8 +353,10 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, arch_wire_switch = segment_inf[i].arch_wire_switch; arch_opin_switch = segment_inf[i].arch_opin_switch; + arch_wire_switch_dec = segment_inf[i].arch_wire_switch_dec; + arch_opin_switch_dec = segment_inf[i].arch_opin_switch_dec; arch_opin_between_dice_switch = segment_inf[i].arch_opin_between_dice_switch; - VTR_ASSERT((arch_wire_switch == arch_opin_switch) || (directionality != UNI_DIRECTIONAL)); + VTR_ASSERT((arch_wire_switch == arch_opin_switch && arch_wire_switch_dec == arch_opin_switch_dec) || (directionality != UNI_DIRECTIONAL)); /* Set up the tracks of same type */ group_start = 0; @@ -416,8 +419,6 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].Cmetal = segment_inf[i].Cmetal; //seg_details[cur_track].Cmetal_per_m = segment_inf[i].Cmetal_per_m; - seg_details[cur_track].arch_wire_switch = arch_wire_switch; - seg_details[cur_track].arch_opin_switch = arch_opin_switch; seg_details[cur_track].arch_opin_between_dice_switch = arch_opin_between_dice_switch; if (BI_DIRECTIONAL == directionality) { @@ -427,6 +428,18 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, seg_details[cur_track].direction = (itrack % 2) ? Direction::DEC : Direction::INC; } + //check for directionality to set the wire_switch and opin_switch + //if not specified in the architecture file, we will use a same mux for both directions + if (seg_details[cur_track].direction == Direction::INC || arch_wire_switch_dec == -1){ + seg_details[cur_track].arch_opin_switch = arch_opin_switch; + seg_details[cur_track].arch_wire_switch = arch_wire_switch; + } + else { + VTR_ASSERT(seg_details[cur_track].direction == Direction::DEC); + seg_details[cur_track].arch_opin_switch = arch_opin_switch_dec; + seg_details[cur_track].arch_wire_switch = arch_wire_switch_dec; + } + seg_details[cur_track].index = i; seg_details[cur_track].abs_index = segment_inf[i].seg_index; From 4610a9d8e131cc7e5d1d04ea5e92070f72ca25f8 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Tue, 16 Jul 2024 14:26:23 -0700 Subject: [PATCH 03/12] added the extra missing condition for bidir segments --- vpr/src/route/rr_graph2.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/rr_graph2.cpp b/vpr/src/route/rr_graph2.cpp index 4e44d105968..751556fd3f4 100644 --- a/vpr/src/route/rr_graph2.cpp +++ b/vpr/src/route/rr_graph2.cpp @@ -430,7 +430,7 @@ t_seg_details* alloc_and_load_seg_details(int* max_chan_width, //check for directionality to set the wire_switch and opin_switch //if not specified in the architecture file, we will use a same mux for both directions - if (seg_details[cur_track].direction == Direction::INC || arch_wire_switch_dec == -1){ + if (seg_details[cur_track].direction == Direction::INC || seg_details[cur_track].direction == Direction::BIDIR || arch_wire_switch_dec == -1){ seg_details[cur_track].arch_opin_switch = arch_opin_switch; seg_details[cur_track].arch_wire_switch = arch_wire_switch; } From f11aaea3f642d2112065688e362b6fabf5048e46 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 10:19:02 -0400 Subject: [PATCH 04/12] update documentation for segment definition in the architecture file --- doc/src/arch/reference.rst | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index 8a0510c2772..8e1cc975e75 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -2036,6 +2036,26 @@ The ```` tag and its contents are described below. Tag must be included and ``name`` must be the same as the name you give in `` + + :req_param name: + Name of the mux switch type used to drive the incremental wires in this segment from both block outputs and other wires. + Incremental wires are tracks within this segment that are heading in the "right" direction on the x-axis and the "top" direction on the y-axis. + This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired. + + .. note:: For UNIDIRECTIONAL only. + +.. arch:tag:: + + :req_param name: + Name of the mux switch type used to drive the decremental wires in this segment from both block outputs and other wires. + Incremental wires are tracks within this segment that are heading in the "left" direction on the x-axis and the "bottom" direction on the y-axis. + This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired. + + .. note:: For UNIDIRECTIONAL only. + + .. note:: For unidirectional segments, either tag or both and should be defined in the architecture file. If only the tag is defined, we assume that the same mux drives both incremental and decremental wires within this segment. + .. arch:tag:: :req_param name: Name of the switch type used by other wires to drive this type of segment by default. This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired. From 762ac7c0d9b84131c9c318372fbc43b9fd36b2c7 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 11:03:16 -0400 Subject: [PATCH 05/12] added a simple architecture to test different mux for inc and dec wires --- ...N10_40nm_diff_switch_for_inc_dec_wires.xml | 288 ++++++++++++++++++ 1 file changed, 288 insertions(+) create mode 100644 vtr_flow/arch/timing/k6_N10_40nm_diff_switch_for_inc_dec_wires.xml diff --git a/vtr_flow/arch/timing/k6_N10_40nm_diff_switch_for_inc_dec_wires.xml b/vtr_flow/arch/timing/k6_N10_40nm_diff_switch_for_inc_dec_wires.xml new file mode 100644 index 00000000000..27a00e767f6 --- /dev/null +++ b/vtr_flow/arch/timing/k6_N10_40nm_diff_switch_for_inc_dec_wires.xml @@ -0,0 +1,288 @@ + + + + + + + + + + + + + + + + + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + io.outpad io.inpad io.clock + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From bada3f40f9c16c8afe2656746f9401ca486407d5 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 11:20:36 -0400 Subject: [PATCH 06/12] added a single task to compare diff mux for inc/dec with normal architecture --- .../config/config.txt | 28 +++++++++++++++++++ .../config/golden_results.txt | 3 ++ 2 files changed, 31 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/config.txt new file mode 100644 index 00000000000..6aa68196bfc --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/config.txt @@ -0,0 +1,28 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=stereovision0.v + +# Add architectures to list to sweep +arch_list_add=k6_N10_40nm.xml +arch_list_add=k6_N10_40nm_diff_switch_for_inc_dec_wires.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params = -crit_path_router_iterations 150 \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt new file mode 100644 index 00000000000..aeff2922e33 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -0,0 +1,3 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 140.15 vpr 272.04 MiB -1 -1 12.85 119508 5 37.98 -1 -1 65828 -1 -1 1307 169 -1 -1 success v8.0.0-10642-gf11aaea3f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-18T10:51:58 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks 278564 169 197 21166 21363 1 7566 1673 39 39 1521 clb auto 140.8 MiB 3.95 53142 974519 347458 607168 19893 272.0 MiB 10.23 0.10 3.63366 -15348.4 -3.63366 3.63366 9.71 0.0315035 0.026913 3.45179 2.89228 44 69063 46 7.37824e+07 7.04408e+07 4.68145e+06 3077.88 43.27 19.1637 16.0718 125110 968779 -1 63965 24 33902 65662 2813140 489196 3.57565 3.57565 -16119.5 -3.57565 0 0 6.05227e+06 3979.14 1.97 2.96 0.84 -1 -1 1.97 2.09287 1.80452 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 138.68 vpr 271.91 MiB -1 -1 12.57 119440 5 36.46 -1 -1 65388 -1 -1 1307 169 -1 -1 success v8.0.0-10642-gf11aaea3f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-18T10:51:58 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks 278432 169 197 21166 21363 1 7566 1673 39 39 1521 clb auto 140.7 MiB 3.96 53142 974519 347458 607168 19893 271.9 MiB 11.12 0.11 3.63366 -15348.4 -3.63366 3.63366 9.48 0.037164 0.0323029 4.04546 3.42407 44 69063 46 7.37824e+07 7.04408e+07 4.68145e+06 3077.88 43.94 19.9593 16.7643 125110 968779 -1 63965 24 33902 65662 2813140 489196 3.57565 3.57565 -16119.5 -3.57565 0 0 6.05227e+06 3979.14 2.02 2.80 0.83 -1 -1 2.02 1.87812 1.62699 From 87ad1b92b10ed300c3091f2dc918ed5c5a4eeca0 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 13:01:35 -0400 Subject: [PATCH 07/12] added a similar task for odin --- .../config/config.txt | 28 +++++++++++++++++++ .../config/golden_results.txt | 3 ++ 2 files changed, 31 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/config.txt new file mode 100644 index 00000000000..5836533b276 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/config.txt @@ -0,0 +1,28 @@ +############################################## +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=stereovision0.v + +# Add architectures to list to sweep +arch_list_add=k6_N10_40nm.xml +arch_list_add=k6_N10_40nm_diff_switch_for_inc_dec_wires.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +# Script parameters +script_params = -start odin -crit_path_router_iterations 150 \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt new file mode 100644 index 00000000000..873a4df06d4 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires/config/golden_results.txt @@ -0,0 +1,3 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_40nm.xml stereovision0.v common 170.85 vpr 277.04 MiB 2.40 125884 -1 -1 5 83.06 -1 -1 75508 -1 -1 1297 157 -1 -1 success v8.0.0-10644-gbada3f40f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-18T12:52:25 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks 283692 157 197 21024 21221 1 7547 1651 39 39 1521 clb auto 144.7 MiB 3.96 51912 967297 355681 587577 24039 277.0 MiB 10.10 0.10 3.27987 -14557.4 -3.27987 3.27987 9.63 0.0317477 0.0266474 3.48443 2.90114 46 64729 31 7.37824e+07 6.99019e+07 4.88195e+06 3209.70 35.95 15.7549 13.2195 126630 998267 -1 62442 28 35421 67860 2863040 490307 3.17524 3.17524 -15310.6 -3.17524 0 0 6.27360e+06 4124.65 1.97 3.27 0.83 -1 -1 1.97 2.34241 2.01697 +k6_N10_40nm_diff_switch_for_inc_dec_wires.xml stereovision0.v common 170.38 vpr 277.10 MiB 2.43 126080 -1 -1 5 82.80 -1 -1 75404 -1 -1 1297 157 -1 -1 success v8.0.0-10644-gbada3f40f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-18T12:52:25 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/inc_dec_wires/vtr-verilog-to-routing/vtr_flow/tasks 283748 157 197 21024 21221 1 7547 1651 39 39 1521 clb auto 144.6 MiB 4.05 51912 967297 355681 587577 24039 277.1 MiB 10.27 0.10 3.27987 -14557.4 -3.27987 3.27987 9.61 0.0323462 0.0271905 3.52052 2.92391 46 64729 31 7.37824e+07 6.99019e+07 4.88195e+06 3209.70 34.80 15.1519 12.6486 126630 998267 -1 62442 28 35421 67860 2863040 490307 3.17524 3.17524 -15310.6 -3.17524 0 0 6.27360e+06 4124.65 1.87 3.85 0.81 -1 -1 1.87 2.71824 2.34292 From b8ef971c29ebf6907378a13910e82f10e4074a9a Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 13:02:51 -0400 Subject: [PATCH 08/12] update task list for both strong and strong_odin --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 + .../tasks/regression_tests/vtr_reg_strong_odin/task_list.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 322e7de030d..3fd9485c892 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -20,6 +20,7 @@ regression_tests/vtr_reg_strong/strong_dedicated_clock regression_tests/vtr_reg_strong/strong_default_fc_pinlocs regression_tests/vtr_reg_strong/strong_depop regression_tests/vtr_reg_strong/strong_detailed_timing +regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires regression_tests/vtr_reg_strong/strong_eblif_vpr regression_tests/vtr_reg_strong/strong_eblif_vpr_write regression_tests/vtr_reg_strong/strong_echo_files diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt index ab44aee0cf4..37eedf040f0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong_odin/task_list.txt @@ -20,6 +20,7 @@ regression_tests/vtr_reg_strong_odin/strong_dedicated_clock regression_tests/vtr_reg_strong_odin/strong_default_fc_pinlocs regression_tests/vtr_reg_strong_odin/strong_depop regression_tests/vtr_reg_strong_odin/strong_detailed_timing +regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires regression_tests/vtr_reg_strong_odin/strong_eblif_vpr regression_tests/vtr_reg_strong_odin/strong_eblif_vpr_write regression_tests/vtr_reg_strong_odin/strong_echo_files From 4cea89ff944810eacd0471b6987696d1ef5ecf04 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 13:22:33 -0400 Subject: [PATCH 09/12] update the tag within wire segments --- doc/src/arch/reference.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/src/arch/reference.rst b/doc/src/arch/reference.rst index 8e1cc975e75..e1ba9e6726d 100644 --- a/doc/src/arch/reference.rst +++ b/doc/src/arch/reference.rst @@ -2031,6 +2031,8 @@ The ```` tag and its contents are described below. .. arch:tag:: :req_param name: Name of the mux switch type used to drive this type of segment by default, from both block outputs and other wires. This information is used during rr-graph construction, and a custom switch block can override this switch type for specific connections if desired. + The switch type specified with the tag will be used for both the incrementing and decrementing wires within this segment. + If more control is needed, the mux_inc and mux_dec tags can be used to assign different muxes to drive incremental and decremental wires within the segment. .. note:: For UNIDIRECTIONAL only. From 4d2affa84d36a61f64f987226c97970088270eb3 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Thu, 18 Jul 2024 13:29:55 -0400 Subject: [PATCH 10/12] initialize the dec muxes to -1 to avoid any random values if not specified --- libs/libarchfpga/src/physical_types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 47c197690c9..2bd65530b94 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1606,8 +1606,8 @@ struct t_segment_inf { int length; short arch_wire_switch; short arch_opin_switch; - short arch_wire_switch_dec; - short arch_opin_switch_dec; + short arch_wire_switch_dec = -1; + short arch_opin_switch_dec = -1; short arch_opin_between_dice_switch = -1; float frac_cb; float frac_sb; From ba408fd4fe81e907b268f55a6cf6a826f4162eb1 Mon Sep 17 00:00:00 2001 From: sara_mahmoudi Date: Mon, 22 Jul 2024 13:02:12 -0700 Subject: [PATCH 11/12] Fixed a typo in task list --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 3fd9485c892..06cc6351f9c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -20,7 +20,7 @@ regression_tests/vtr_reg_strong/strong_dedicated_clock regression_tests/vtr_reg_strong/strong_default_fc_pinlocs regression_tests/vtr_reg_strong/strong_depop regression_tests/vtr_reg_strong/strong_detailed_timing -regression_tests/vtr_reg_strong_odin/strong_diff_mux_for_inc_dec_wires +regression_tests/vtr_reg_strong/strong_diff_mux_for_inc_dec_wires regression_tests/vtr_reg_strong/strong_eblif_vpr regression_tests/vtr_reg_strong/strong_eblif_vpr_write regression_tests/vtr_reg_strong/strong_echo_files @@ -85,4 +85,4 @@ regression_tests/vtr_reg_strong/strong_timing_fail regression_tests/vtr_reg_strong/strong_timing_no_fail regression_tests/vtr_reg_strong/strong_noc regression_tests/vtr_reg_strong/strong_flat_router -regression_tests/vtr_reg_strong/strong_routing_constraints \ No newline at end of file +regression_tests/vtr_reg_strong/strong_routing_constraints From 30f61a87f92582b3680d82ec8b9a98fb475f1b99 Mon Sep 17 00:00:00 2001 From: saaramahmoudi Date: Mon, 26 Aug 2024 07:41:19 -0700 Subject: [PATCH 12/12] changed documentation, VB suggestions applied --- libs/libarchfpga/src/physical_types.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 0bd2a11078c..949024ada33 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -1569,11 +1569,14 @@ enum e_Fc_type { * at the end of build_rr_graph * * @param arch_wire_switch_dec: Same as arch_wire_switch but used only for * * decremental tracks if it is specified in the * - * architecture file. * + * architecture file. If -1, this value was not set in * + * the architecture file and arch_wire_switch should be * + * used for "DEC_DIR" wire segments. * * @param arch_opin_switch_dec: Same as arch_opin_switch but used only for * * decremental tracks if it is specified in the * - * architecture file * - * * + * architecture file. If -1, this value was not set in * + * the architecture file and arch_opin_switch should be * + * used for "DEC_DIR" wire segments. * * @param arch_opin_between_dice_switch: Index of the switch type that * * connects output pins (OPINs) *to* this segment from * * *another die (layer)*. Note that this index is in *