diff --git a/yosys/.github/workflows/codeql.yml b/yosys/.github/workflows/codeql.yml index 2a046703bc0..4a77d223429 100644 --- a/yosys/.github/workflows/codeql.yml +++ b/yosys/.github/workflows/codeql.yml @@ -14,10 +14,10 @@ jobs: run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev - name: Checkout repository - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Initialize CodeQL - uses: github/codeql-action/init@v2 + uses: github/codeql-action/init@v3 with: languages: cpp queries: security-extended,security-and-quality @@ -26,4 +26,4 @@ jobs: run: make yosys -j6 - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v2 + uses: github/codeql-action/analyze@v3 diff --git a/yosys/.github/workflows/emcc.yml b/yosys/.github/workflows/emcc.yml index 295d9554b81..7c6409c1be2 100644 --- a/yosys/.github/workflows/emcc.yml +++ b/yosys/.github/workflows/emcc.yml @@ -6,13 +6,13 @@ jobs: emcc: runs-on: ubuntu-latest steps: - - uses: mymindstorm/setup-emsdk@v11 - - uses: actions/checkout@v3 + - uses: mymindstorm/setup-emsdk@v14 + - uses: actions/checkout@v4 - name: Build run: | make config-emcc make YOSYS_VER=latest - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@v4 with: name: yosysjs path: yosysjs-latest.zip diff --git a/yosys/.github/workflows/test-linux.yml b/yosys/.github/workflows/test-linux.yml index eee556794af..28c17a6c0e0 100644 --- a/yosys/.github/workflows/test-linux.yml +++ b/yosys/.github/workflows/test-linux.yml @@ -43,6 +43,7 @@ jobs: sudo apt-get install $CC $CXX echo "CC=$CC" >> $GITHUB_ENV echo "CXX=$CXX" >> $GITHUB_ENV + echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV env: CC: ${{ matrix.compiler }} @@ -78,19 +79,22 @@ jobs: $CXX --version - name: Checkout Yosys - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get iverilog shell: bash run: | git clone https://github.com/steveicarus/iverilog.git + cd iverilog + git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874 + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Cache iverilog id: cache-iverilog - uses: actions/cache@v3 + uses: actions/cache@v4 with: path: .local/ - key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }} + key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }} - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' @@ -107,10 +111,14 @@ jobs: shell: bash run: | make config-${CC%%-*} - make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC + make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC - name: Run tests if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11') shell: bash run: | make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC + + - name: Log yosys-config output + run: | + ./yosys-config || true diff --git a/yosys/.github/workflows/test-macos.yml b/yosys/.github/workflows/test-macos.yml index 04845723467..17e2ae33155 100644 --- a/yosys/.github/workflows/test-macos.yml +++ b/yosys/.github/workflows/test-macos.yml @@ -8,7 +8,7 @@ jobs: strategy: matrix: os: - - { id: macos-11, name: 'Big Sur' } + - { id: macos-13, name: 'Ventura' } cpp_std: - 'c++11' - 'c++17' @@ -35,19 +35,22 @@ jobs: cc --version - name: Checkout Yosys - uses: actions/checkout@v3 + uses: actions/checkout@v4 - name: Get iverilog shell: bash run: | git clone https://github.com/steveicarus/iverilog.git + cd iverilog + git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874 + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Cache iverilog id: cache-iverilog - uses: actions/cache@v3 + uses: actions/cache@v4 with: path: .local/ - key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }} + key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }} - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' diff --git a/yosys/.github/workflows/version.yml b/yosys/.github/workflows/version.yml index c2a1756e9c6..47a7fe1a39f 100644 --- a/yosys/.github/workflows/version.yml +++ b/yosys/.github/workflows/version.yml @@ -10,7 +10,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: fetch-depth: 0 - name: Take last commit diff --git a/yosys/.github/workflows/vs.yml b/yosys/.github/workflows/vs.yml index 428770e7200..799c5f259f4 100644 --- a/yosys/.github/workflows/vs.yml +++ b/yosys/.github/workflows/vs.yml @@ -6,10 +6,10 @@ jobs: yosys-vcxsrc: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - name: Build run: make vcxsrc YOSYS_VER=latest - - uses: actions/upload-artifact@v3 + - uses: actions/upload-artifact@v4 with: name: vcxsrc path: yosys-win32-vcxsrc-latest.zip @@ -18,7 +18,7 @@ jobs: runs-on: windows-2019 needs: yosys-vcxsrc steps: - - uses: actions/download-artifact@v3 + - uses: actions/download-artifact@v4 with: name: vcxsrc path: . diff --git a/yosys/.github/workflows/wasi.yml b/yosys/.github/workflows/wasi.yml new file mode 100644 index 00000000000..d6d200d92c2 --- /dev/null +++ b/yosys/.github/workflows/wasi.yml @@ -0,0 +1,30 @@ +name: WASI Build + +on: [push, pull_request] + +jobs: + wasi: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - name: Build + run: | + WASI_SDK=wasi-sdk-19.0 + WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz + if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi + + mkdir -p build + cat > build/Makefile.conf <> aig_gates; vector aig_latchin, aig_latchinit, aig_outputs; + vector bit2aig_stack; + size_t next_loop_check = 1024; int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0; int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0; @@ -81,6 +83,23 @@ struct AigerWriter return it->second; } + if (bit2aig_stack.size() == next_loop_check) { + for (size_t i = 0; i < next_loop_check; ++i) + { + SigBit report_bit = bit2aig_stack[i]; + if (report_bit != bit) + continue; + for (size_t j = i; j < next_loop_check; ++j) { + report_bit = bit2aig_stack[j]; + if (report_bit.is_wire() && report_bit.wire->name.isPublic()) + break; + } + log_error("Found combinational logic loop while processing signal %s.\n", log_signal(report_bit)); + } + next_loop_check *= 2; + } + bit2aig_stack.push_back(bit); + // NB: Cannot use iterator returned from aig_map.insert() // since this function is called recursively @@ -101,6 +120,8 @@ struct AigerWriter a = initstate_ff; } + bit2aig_stack.pop_back(); + if (bit == State::Sx || bit == State::Sz) log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n"); diff --git a/yosys/backends/btor/test_cells.sh b/yosys/backends/btor/test_cells.sh index 0a011932d22..f8bd797825e 100755 --- a/yosys/backends/btor/test_cells.sh +++ b/yosys/backends/btor/test_cells.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex diff --git a/yosys/backends/cxxrtl/cxxrtl_backend.cc b/yosys/backends/cxxrtl/cxxrtl_backend.cc index 1b13985ab4e..c60b43d3faa 100644 --- a/yosys/backends/cxxrtl/cxxrtl_backend.cc +++ b/yosys/backends/cxxrtl/cxxrtl_backend.cc @@ -24,6 +24,7 @@ #include "kernel/celltypes.h" #include "kernel/mem.h" #include "kernel/log.h" +#include "kernel/fmt.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -217,7 +218,7 @@ bool is_internal_cell(RTLIL::IdString type) bool is_effectful_cell(RTLIL::IdString type) { - return type.isPublic(); + return type.in(ID($print), ID($check)); } bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell) @@ -281,6 +282,7 @@ struct FlowGraph { CONNECT, CELL_SYNC, CELL_EVAL, + EFFECT_SYNC, PROCESS_SYNC, PROCESS_CASE, MEM_RDPORT, @@ -290,6 +292,7 @@ struct FlowGraph { Type type; RTLIL::SigSig connect = {}; const RTLIL::Cell *cell = nullptr; + std::vector cells; const RTLIL::Process *process = nullptr; const Mem *mem = nullptr; int portidx; @@ -477,6 +480,15 @@ struct FlowGraph { return node; } + Node *add_effect_sync_node(std::vector cells) + { + Node *node = new Node; + node->type = Node::Type::EFFECT_SYNC; + node->cells = cells; + nodes.push_back(node); + return node; + } + // Processes void add_case_rule_defs_uses(Node *node, const RTLIL::CaseRule *case_) { @@ -616,6 +628,20 @@ std::string escape_cxx_string(const std::string &input) return output; } +std::string basename(const std::string &filepath) +{ +#ifdef _WIN32 + const std::string dir_seps = "\\/"; +#else + const std::string dir_seps = "/"; +#endif + size_t sep_pos = filepath.find_last_of(dir_seps); + if (sep_pos != std::string::npos) + return filepath.substr(sep_pos + 1); + else + return filepath; +} + template std::string get_hdl_name(T *object) { @@ -681,6 +707,7 @@ struct CxxrtlWorker { bool split_intf = false; std::string intf_filename; std::string design_ns = "cxxrtl_design"; + std::string print_output = "std::cout"; std::ostream *impl_f = nullptr; std::ostream *intf_f = nullptr; @@ -1189,6 +1216,144 @@ struct CxxrtlWorker { } } + void dump_print(const RTLIL::Cell *cell) + { + Fmt fmt; + fmt.parse_rtlil(cell); + + f << indent << "if ("; + dump_sigspec_rhs(cell->getPort(ID::EN)); + f << " == value<1>{1u}) {\n"; + inc_indent(); + dict fmt_args; + f << indent << "struct : public lazy_fmt {\n"; + inc_indent(); + f << indent << "std::string operator() () const override {\n"; + inc_indent(); + fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) { + if (sig.size() == 0) + f << "value<0>()"; + else { + std::string arg_name = "arg" + std::to_string(fmt_args.size()); + fmt_args[arg_name] = sig; + f << arg_name; + } + }, "performer"); + dec_indent(); + f << indent << "}\n"; + f << indent << "struct performer *performer;\n"; + for (auto arg : fmt_args) + f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n"; + dec_indent(); + f << indent << "} formatter;\n"; + f << indent << "formatter.performer = performer;\n"; + for (auto arg : fmt_args) { + f << indent << "formatter." << arg.first << " = "; + dump_sigspec_rhs(arg.second); + f << ";\n"; + } + f << indent << "if (performer) {\n"; + inc_indent(); + f << indent << "static const metadata_map attributes = "; + dump_metadata_map(cell->attributes); + f << ";\n"; + f << indent << "performer->on_print(formatter, attributes);\n"; + dec_indent(); + f << indent << "} else {\n"; + inc_indent(); + f << indent << print_output << " << formatter();\n"; + dec_indent(); + f << indent << "}\n"; + dec_indent(); + f << indent << "}\n"; + } + + void dump_effect(const RTLIL::Cell *cell) + { + Fmt fmt; + fmt.parse_rtlil(cell); + + f << indent << "if ("; + dump_sigspec_rhs(cell->getPort(ID::EN)); + f << ") {\n"; + inc_indent(); + dict fmt_args; + f << indent << "struct : public lazy_fmt {\n"; + inc_indent(); + f << indent << "std::string operator() () const override {\n"; + inc_indent(); + fmt.emit_cxxrtl(f, indent, [&](const RTLIL::SigSpec &sig) { + if (sig.size() == 0) + f << "value<0>()"; + else { + std::string arg_name = "arg" + std::to_string(fmt_args.size()); + fmt_args[arg_name] = sig; + f << arg_name; + } + }, "performer"); + dec_indent(); + f << indent << "}\n"; + f << indent << "struct performer *performer;\n"; + for (auto arg : fmt_args) + f << indent << "value<" << arg.second.size() << "> " << arg.first << ";\n"; + dec_indent(); + f << indent << "} formatter;\n"; + f << indent << "formatter.performer = performer;\n"; + for (auto arg : fmt_args) { + f << indent << "formatter." << arg.first << " = "; + dump_sigspec_rhs(arg.second); + f << ";\n"; + } + if (cell->hasPort(ID::A)) { + f << indent << "bool condition = (bool)"; + dump_sigspec_rhs(cell->getPort(ID::A)); + f << ";\n"; + } + f << indent << "if (performer) {\n"; + inc_indent(); + f << indent << "static const metadata_map attributes = "; + dump_metadata_map(cell->attributes); + f << ";\n"; + if (cell->type == ID($print)) { + f << indent << "performer->on_print(formatter, attributes);\n"; + } else if (cell->type == ID($check)) { + std::string flavor = cell->getParam(ID::FLAVOR).decode_string(); + f << indent << "performer->on_check("; + if (flavor == "assert") + f << "flavor::ASSERT"; + else if (flavor == "assume") + f << "flavor::ASSUME"; + else if (flavor == "live") + f << "flavor::ASSERT_EVENTUALLY"; + else if (flavor == "fair") + f << "flavor::ASSUME_EVENTUALLY"; + else if (flavor == "cover") + f << "flavor::COVER"; + else log_assert(false); + f << ", condition, formatter, attributes);\n"; + } else log_assert(false); + dec_indent(); + f << indent << "} else {\n"; + inc_indent(); + if (cell->type == ID($print)) { + f << indent << print_output << " << formatter();\n"; + } else if (cell->type == ID($check)) { + std::string flavor = cell->getParam(ID::FLAVOR).decode_string(); + if (flavor == "assert" || flavor == "assume") { + f << indent << "if (!condition) {\n"; + inc_indent(); + f << indent << "std::cerr << formatter();\n"; + dec_indent(); + f << indent << "}\n"; + f << indent << "CXXRTL_ASSERT(condition && \"Check failed\");\n"; + } + } else log_assert(false); + dec_indent(); + f << indent << "}\n"; + dec_indent(); + f << indent << "}\n"; + } + void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false) { std::vector inlined_cells; @@ -1202,6 +1367,38 @@ struct CxxrtlWorker { f << " = "; dump_cell_expr(cell, for_debug); f << ";\n"; + // Effectful cells + } else if (is_effectful_cell(cell->type)) { + log_assert(!for_debug); + + // Sync effectful cells are grouped into EFFECT_SYNC nodes in the FlowGraph. + log_assert(!cell->getParam(ID::TRG_ENABLE).as_bool() || (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0)); + + if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell + f << indent << "auto " << mangle(cell) << "_next = "; + dump_sigspec_rhs(cell->getPort(ID::EN)); + f << ".concat("; + if (cell->type == ID($print)) + dump_sigspec_rhs(cell->getPort(ID::ARGS)); + else if (cell->type == ID($check)) + dump_sigspec_rhs(cell->getPort(ID::A)); + else log_assert(false); + f << ").val();\n"; + + f << indent << "if (" << mangle(cell) << " != " << mangle(cell) << "_next) {\n"; + inc_indent(); + dump_effect(cell); + f << indent << mangle(cell) << " = " << mangle(cell) << "_next;\n"; + dec_indent(); + f << indent << "}\n"; + } else { // initial effectful cell + f << indent << "if (!" << mangle(cell) << ") {\n"; + inc_indent(); + dump_effect(cell); + f << indent << mangle(cell) << " = value<1>{1u};\n"; + dec_indent(); + f << indent << "}\n"; + } // Flip-flops } else if (is_ff_cell(cell->type)) { log_assert(!for_debug); @@ -1298,7 +1495,7 @@ struct CxxrtlWorker { f << indent; dump_sigspec_lhs(cell->getPort(ID::Q)); f << " = "; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_rhs(cell->getPort(ID::Q)); f << ".update("; dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int())); f << ", "; @@ -1310,7 +1507,7 @@ struct CxxrtlWorker { f << indent; dump_sigspec_lhs(cell->getPort(ID::Q)); f << " = "; - dump_sigspec_lhs(cell->getPort(ID::Q)); + dump_sigspec_rhs(cell->getPort(ID::Q)); f << ".update("; dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int())); f << ", "; @@ -1382,11 +1579,11 @@ struct CxxrtlWorker { }; if (buffered_inputs) { // If we have any buffered inputs, there's no chance of converging immediately. - f << indent << mangle(cell) << access << "eval();\n"; + f << indent << mangle(cell) << access << "eval(performer);\n"; f << indent << "converged = false;\n"; assign_from_outputs(/*cell_converged=*/false); } else { - f << indent << "if (" << mangle(cell) << access << "eval()) {\n"; + f << indent << "if (" << mangle(cell) << access << "eval(performer)) {\n"; inc_indent(); assign_from_outputs(/*cell_converged=*/true); dec_indent(); @@ -1580,6 +1777,47 @@ struct CxxrtlWorker { } } + void dump_cell_effect_sync(std::vector &cells) + { + log_assert(!cells.empty()); + const auto &trg = cells[0]->getPort(ID::TRG); + const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY); + + f << indent << "if ("; + for (int i = 0; i < trg.size(); i++) { + RTLIL::SigBit trg_bit = trg[i]; + trg_bit = sigmaps[trg_bit.wire->module](trg_bit); + log_assert(trg_bit.wire); + + if (i != 0) + f << " || "; + + if (trg_polarity[i] == State::S1) + f << "posedge_"; + else + f << "negedge_"; + f << mangle(trg_bit); + } + f << ") {\n"; + inc_indent(); + std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) { + return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int(); + }); + for (auto cell : cells) { + log_assert(cell->getParam(ID::TRG_ENABLE).as_bool()); + log_assert(cell->getPort(ID::TRG) == trg); + log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity); + + std::vector inlined_cells; + collect_cell_eval(cell, /*for_debug=*/false, inlined_cells); + dump_inlined_cells(inlined_cells); + dump_effect(cell); + } + dec_indent(); + + f << indent << "}\n"; + } + void dump_mem_rdport(const Mem *mem, int portidx, bool for_debug = false) { auto &port = mem->rd_ports[portidx]; @@ -1899,6 +2137,10 @@ struct CxxrtlWorker { } } for (auto cell : module->cells()) { + // Async and initial effectful cells have additional state, which must be reset as well. + if (is_effectful_cell(cell->type)) + if (!cell->getParam(ID::TRG_ENABLE).as_bool() || cell->getParam(ID::TRG_WIDTH).as_int() == 0) + f << indent << mangle(cell) << " = {};\n"; if (is_internal_cell(cell->type)) continue; f << indent << mangle(cell); @@ -1946,6 +2188,9 @@ struct CxxrtlWorker { case FlowGraph::Node::Type::CELL_EVAL: dump_cell_eval(node.cell); break; + case FlowGraph::Node::Type::EFFECT_SYNC: + dump_cell_effect_sync(node.cells); + break; case FlowGraph::Node::Type::PROCESS_CASE: dump_process_case(node.process); break; @@ -2009,25 +2254,65 @@ struct CxxrtlWorker { if (wire_type.type == WireType::MEMBER && edge_wires[wire]) f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n"; if (wire_type.is_buffered()) - f << indent << "if (" << mangle(wire) << ".commit()) changed = true;\n"; + f << indent << "if (" << mangle(wire) << ".commit(observer)) changed = true;\n"; } if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto &mem : mod_memories[module]) { if (!writable_memories.count({module, mem.memid})) continue; - f << indent << "if (" << mangle(&mem) << ".commit()) changed = true;\n"; + f << indent << "if (" << mangle(&mem) << ".commit(observer)) changed = true;\n"; } for (auto cell : module->cells()) { if (is_internal_cell(cell->type)) continue; const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; - f << indent << "if (" << mangle(cell) << access << "commit()) changed = true;\n"; + f << indent << "if (" << mangle(cell) << access << "commit(observer)) changed = true;\n"; } } f << indent << "return changed;\n"; dec_indent(); } + void dump_metadata_map(const dict &metadata_map) + { + if (metadata_map.empty()) { + f << "metadata_map()"; + return; + } + f << "metadata_map({\n"; + inc_indent(); + for (auto metadata_item : metadata_map) { + if (!metadata_item.first.isPublic()) + continue; + if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) { + f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */\n"; + continue; + } + f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", "; + // In Yosys, a real is a type of string. + if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) { + f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint; + } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) { + f << escape_cxx_string(metadata_item.second.decode_string()); + } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) { + f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")"; + } else { + f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")"; + } + f << " },\n"; + } + dec_indent(); + f << indent << "})"; + } + + void dump_debug_attrs(const RTLIL::AttrObject *object) + { + dict attributes = object->attributes; + // Inherently necessary to get access to the object, so a waste of space to emit. + attributes.erase(ID::hdlname); + dump_metadata_map(attributes); + } + void dump_debug_info_method(RTLIL::Module *module) { size_t count_public_wires = 0; @@ -2113,7 +2398,9 @@ struct CxxrtlWorker { } f << "debug_item::" << flag; } - f << "));\n"; + f << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_member_wires++; break; } @@ -2128,7 +2415,9 @@ struct CxxrtlWorker { f << "debug_eval_outline"; else f << "debug_alias()"; - f << ", " << mangle(aliasee) << ", " << wire->start_offset << "));\n"; + f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), "; + dump_debug_attrs(aliasee); + f << ");\n"; count_alias_wires++; break; } @@ -2138,14 +2427,18 @@ struct CxxrtlWorker { dump_const(debug_wire_type.sig_subst.as_const()); f << ";\n"; f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "));\n"; + f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_const_wires++; break; } case WireType::OUTLINE: { // Localized or inlined, but rematerializable wire f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "));\n"; + f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), "; + dump_debug_attrs(wire); + f << ");\n"; count_inline_wires++; break; } @@ -2162,7 +2455,13 @@ struct CxxrtlWorker { continue; f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem)); f << ", debug_item(" << mangle(&mem) << ", "; - f << mem.start_offset << "));\n"; + f << mem.start_offset << "), "; + if (mem.packed) { + dump_debug_attrs(mem.cell); + } else { + dump_debug_attrs(mem.mem); + } + f << ");\n"; } for (auto cell : module->cells()) { if (is_internal_cell(cell->type)) @@ -2190,33 +2489,6 @@ struct CxxrtlWorker { } } - void dump_metadata_map(const dict &metadata_map) - { - if (metadata_map.empty()) { - f << "metadata_map()"; - return; - } - f << "metadata_map({\n"; - inc_indent(); - for (auto metadata_item : metadata_map) { - if (!metadata_item.first.begins_with("\\")) - continue; - f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", "; - if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) { - f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint; - } else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) { - f << escape_cxx_string(metadata_item.second.decode_string()); - } else { - f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED); - if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED)) - f << "u"; - } - f << " },\n"; - } - dec_indent(); - f << indent << "})"; - } - void dump_module_intf(RTLIL::Module *module) { dump_attrs(module); @@ -2234,20 +2506,27 @@ struct CxxrtlWorker { dump_reset_method(module); f << indent << "}\n"; f << "\n"; - f << indent << "bool eval() override {\n"; + // No default argument, to prevent unintentional `return bb_foo::eval();` calls that drop performer. + f << indent << "bool eval(performer *performer) override {\n"; dump_eval_method(module); f << indent << "}\n"; f << "\n"; - f << indent << "bool commit() override {\n"; + f << indent << "template\n"; + f << indent << "bool commit(ObserverT &observer) {\n"; dump_commit_method(module); f << indent << "}\n"; f << "\n"; + f << indent << "bool commit() override {\n"; + f << indent << indent << "observer observer;\n"; + f << indent << indent << "return commit<>(observer);\n"; + f << indent << "}\n"; if (debug_info) { + f << "\n"; f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n"; dump_debug_info_method(module); f << indent << "}\n"; - f << "\n"; } + f << "\n"; f << indent << "static std::unique_ptr<" << mangle(module); f << template_params(module, /*is_decl=*/false) << "> "; f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n"; @@ -2291,6 +2570,15 @@ struct CxxrtlWorker { f << "\n"; bool has_cells = false; for (auto cell : module->cells()) { + // Async and initial effectful cells have additional state, which requires storage. + if (is_effectful_cell(cell->type)) { + if (cell->getParam(ID::TRG_ENABLE).as_bool() && cell->getParam(ID::TRG_WIDTH).as_int() == 0) + f << indent << "value<1> " << mangle(cell) << ";\n"; // async initial cell + if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($print)) + f << indent << "value<" << (1 + cell->getParam(ID::ARGS_WIDTH).as_int()) << "> " << mangle(cell) << ";\n"; // {EN, ARGS} + if (!cell->getParam(ID::TRG_ENABLE).as_bool() && cell->type == ID($check)) + f << indent << "value<2> " << mangle(cell) << ";\n"; // {EN, A} + } if (is_internal_cell(cell->type)) continue; dump_attrs(cell); @@ -2319,8 +2607,18 @@ struct CxxrtlWorker { f << indent << "};\n"; f << "\n"; f << indent << "void reset() override;\n"; - f << indent << "bool eval() override;\n"; - f << indent << "bool commit() override;\n"; + f << "\n"; + f << indent << "bool eval(performer *performer = nullptr) override;\n"; + f << "\n"; + f << indent << "template\n"; + f << indent << "bool commit(ObserverT &observer) {\n"; + dump_commit_method(module); + f << indent << "}\n"; + f << "\n"; + f << indent << "bool commit() override {\n"; + f << indent << indent << "observer observer;\n"; + f << indent << indent << "return commit<>(observer);\n"; + f << indent << "}\n"; if (debug_info) { if (debug_eval) { f << "\n"; @@ -2349,27 +2647,23 @@ struct CxxrtlWorker { dump_reset_method(module); f << indent << "}\n"; f << "\n"; - f << indent << "bool " << mangle(module) << "::eval() {\n"; + f << indent << "bool " << mangle(module) << "::eval(performer *performer) {\n"; dump_eval_method(module); f << indent << "}\n"; - f << "\n"; - f << indent << "bool " << mangle(module) << "::commit() {\n"; - dump_commit_method(module); - f << indent << "}\n"; - f << "\n"; if (debug_info) { if (debug_eval) { + f << "\n"; f << indent << "void " << mangle(module) << "::debug_eval() {\n"; dump_debug_eval_method(module); f << indent << "}\n"; - f << "\n"; } + f << "\n"; f << indent << "CXXRTL_EXTREMELY_COLD\n"; f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n"; dump_debug_info_method(module); f << indent << "}\n"; - f << "\n"; } + f << "\n"; } void dump_design(RTLIL::Design *design) @@ -2409,7 +2703,7 @@ struct CxxrtlWorker { f << "#define " << include_guard << "\n"; f << "\n"; if (top_module != nullptr && debug_info) { - f << "#include \n"; + f << "#include \n"; f << "\n"; f << "#ifdef __cplusplus\n"; f << "extern \"C\" {\n"; @@ -2427,7 +2721,7 @@ struct CxxrtlWorker { } f << "#ifdef __cplusplus\n"; f << "\n"; - f << "#include \n"; + f << "#include \n"; f << "\n"; f << "using namespace cxxrtl;\n"; f << "\n"; @@ -2444,17 +2738,17 @@ struct CxxrtlWorker { } if (split_intf) - f << "#include \"" << intf_filename << "\"\n"; + f << "#include \"" << basename(intf_filename) << "\"\n"; else - f << "#include \n"; + f << "#include \n"; f << "\n"; f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n"; f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; - f << "#include \n"; + f << "#include \n"; f << "#endif\n"; f << "\n"; f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; - f << "#include \n"; + f << "#include \n"; f << "#endif\n"; f << "\n"; f << "using namespace cxxrtl_yosys;\n"; @@ -2601,6 +2895,16 @@ struct CxxrtlWorker { register_edge_signal(sigmap, cell->getPort(ID::CLK), cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn); } + + // Effectful cells may be triggered on posedge/negedge events. + if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) { + for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) { + RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1); + if (is_valid_clock(trg)) + register_edge_signal(sigmap, trg, + cell->parameters[ID::TRG_POLARITY][i] == RTLIL::S1 ? RTLIL::STp : RTLIL::STn); + } + } } for (auto &mem : memories) { @@ -2734,8 +3038,12 @@ struct CxxrtlWorker { // Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users. pool worklist; for (auto node : flow.nodes) { - if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type)) - worklist.insert(node); // node has effects + if (node->type == FlowGraph::Node::Type::CELL_EVAL && !is_internal_cell(node->cell->type)) + worklist.insert(node); // node evaluates a submodule + else if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type)) + worklist.insert(node); // node has async effects + else if (node->type == FlowGraph::Node::Type::EFFECT_SYNC) + worklist.insert(node); // node has sync effects else if (node->type == FlowGraph::Node::Type::MEM_WRPORTS) worklist.insert(node); // node is memory write else if (node->type == FlowGraph::Node::Type::PROCESS_SYNC && is_memwr_process(node->process)) @@ -2792,9 +3100,23 @@ struct CxxrtlWorker { } // Emit reachable nodes in eval(). + // Accumulate sync effectful cells per trigger condition. + dict, std::vector> effect_sync_cells; for (auto node : node_order) - if (live_nodes[node]) - schedule[module].push_back(*node); + if (live_nodes[node]) { + if (node->type == FlowGraph::Node::Type::CELL_EVAL && + is_effectful_cell(node->cell->type) && + node->cell->getParam(ID::TRG_ENABLE).as_bool() && + node->cell->getParam(ID::TRG_WIDTH).as_int() != 0) + effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell); + else + schedule[module].push_back(*node); + } + + for (auto &it : effect_sync_cells) { + auto node = flow.add_effect_sync_node(it.second); + schedule[module].push_back(*node); + } // For maximum performance, the state of the simulation (which is the same as the set of its double buffered // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain @@ -3098,7 +3420,9 @@ struct CxxrtlBackend : public Backend { log(" value<8> p_i_data;\n"); log(" wire<8> p_o_data;\n"); log("\n"); - log(" bool eval() override;\n"); + log(" bool eval(performer *performer) override;\n"); + log(" template\n"); + log(" bool commit(ObserverT &observer);\n"); log(" bool commit() override;\n"); log("\n"); log(" static std::unique_ptr\n"); @@ -3111,11 +3435,11 @@ struct CxxrtlBackend : public Backend { log(" namespace cxxrtl_design {\n"); log("\n"); log(" struct stderr_debug : public bb_p_debug {\n"); - log(" bool eval() override {\n"); + log(" bool eval(performer *performer) override {\n"); log(" if (posedge_p_clk() && p_en)\n"); log(" fprintf(stderr, \"debug: %%02x\\n\", p_i_data.data[0]);\n"); log(" p_o_data.next = p_i_data;\n"); - log(" return bb_p_debug::eval();\n"); + log(" return bb_p_debug::eval(performer);\n"); log(" }\n"); log(" };\n"); log("\n"); @@ -3213,6 +3537,11 @@ struct CxxrtlBackend : public Backend { log(" place the generated code into namespace . if not specified,\n"); log(" \"cxxrtl_design\" is used.\n"); log("\n"); + log(" -print-output \n"); + log(" $print cells in the generated code direct their output to .\n"); + log(" must be one of \"std::cout\", \"std::cerr\". if not specified,\n"); + log(" \"std::cout\" is used. explicitly provided performer overrides this.\n"); + log("\n"); log(" -nohierarchy\n"); log(" use design hierarchy as-is. in most designs, a top module should be\n"); log(" present as it is exposed through the C API and has unbuffered outputs\n"); @@ -3351,6 +3680,14 @@ struct CxxrtlBackend : public Backend { worker.design_ns = args[++argidx]; continue; } + if (args[argidx] == "-print-output" && argidx+1 < args.size()) { + worker.print_output = args[++argidx]; + if (!(worker.print_output == "std::cout" || worker.print_output == "std::cerr")) { + log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output.c_str()); + worker.print_output = "std::cout"; + } + continue; + } break; } extra_args(f, filename, args, argidx); diff --git a/yosys/backends/cxxrtl/runtime/README.txt b/yosys/backends/cxxrtl/runtime/README.txt new file mode 100644 index 00000000000..9ae7051cdcc --- /dev/null +++ b/yosys/backends/cxxrtl/runtime/README.txt @@ -0,0 +1,18 @@ +This directory contains the runtime components of CXXRTL and should be placed on the include path +when building the simulation using the `-I${YOSYS}/backends/cxxrtl/runtime` option. These components +are not used in the Yosys binary; they are only built as a part of the simulation binary. + +The interfaces declared in `cxxrtl_capi*.h` contain the stable C API. These interfaces will not be +changed in backward-incompatible ways unless no other option is available, and any breaking changes +will be made in a way that causes the downstream code to fail in a visible way. The ABI of these +interfaces is considered stable as well, and it will not use features complicating its use via +libraries such as libffi or ctypes. + +The implementations in `cxxrtl_capi*.cc` are considered private; they are still placed in the include +path to enable build-system-less builds (where the CXXRTL runtime component is included in the C++ +file of the simulation toplevel). + +The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice. + +For clarity, all of the files in this directory and its subdirectories have unique names regardless +of the directory where they are placed. \ No newline at end of file diff --git a/yosys/backends/cxxrtl/cxxrtl_capi.cc b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc similarity index 62% rename from yosys/backends/cxxrtl/cxxrtl_capi.cc rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc index 227173ba87f..593e067a181 100644 --- a/yosys/backends/cxxrtl/cxxrtl_capi.cc +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc @@ -16,10 +16,10 @@ * */ -// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`. +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi.h`. -#include -#include +#include +#include struct _cxxrtl_handle { std::unique_ptr module; @@ -90,3 +90,46 @@ void cxxrtl_enum(cxxrtl_handle handle, void *data, void cxxrtl_outline_eval(cxxrtl_outline outline) { outline->eval(); } + +int cxxrtl_attr_type(cxxrtl_attr_set attrs_, const char *name) { + auto attrs = (cxxrtl::metadata_map*)attrs_; + if (!attrs->count(name)) + return CXXRTL_ATTR_NONE; + switch (attrs->at(name).value_type) { + case cxxrtl::metadata::UINT: + return CXXRTL_ATTR_UNSIGNED_INT; + case cxxrtl::metadata::SINT: + return CXXRTL_ATTR_SIGNED_INT; + case cxxrtl::metadata::STRING: + return CXXRTL_ATTR_STRING; + case cxxrtl::metadata::DOUBLE: + return CXXRTL_ATTR_DOUBLE; + default: + // Present unsupported attribute type the same way as no attribute at all. + return CXXRTL_ATTR_NONE; + } +} + +uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::UINT); + return attrs[name].as_uint(); +} + +int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::SINT); + return attrs[name].as_sint(); +} + +const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::STRING); + return attrs[name].as_string().c_str(); +} + +double cxxrtl_attr_get_double(cxxrtl_attr_set attrs_, const char *name) { + auto &attrs = *(cxxrtl::metadata_map*)attrs_; + assert(attrs.count(name) && attrs.at(name).value_type == cxxrtl::metadata::DOUBLE); + return attrs[name].as_double(); +} diff --git a/yosys/backends/cxxrtl/cxxrtl_capi.h b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h similarity index 82% rename from yosys/backends/cxxrtl/cxxrtl_capi.h rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h index 2df2b7287f4..e5c84bf656a 100644 --- a/yosys/backends/cxxrtl/cxxrtl_capi.h +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h @@ -249,6 +249,15 @@ struct cxxrtl_object { // this field to NULL. struct _cxxrtl_outline *outline; + // Opaque reference to an attribute set. + // + // See the documentation of `cxxrtl_attr_set` for details. When creating a `cxxrtl_object`, set + // this field to NULL. + // + // The lifetime of the pointers returned by `cxxrtl_attr_*` family of functions is the same as + // the lifetime of this structure. + struct _cxxrtl_attr_set *attrs; + // More description fields may be added in the future, but the existing ones will never change. }; @@ -304,6 +313,62 @@ typedef struct _cxxrtl_outline *cxxrtl_outline; // re-evaluated, otherwise the bits read from that object are meaningless. void cxxrtl_outline_eval(cxxrtl_outline outline); +// Opaque reference to an attribute set. +// +// An attribute set is a map between attribute names (always strings) and values (which may have +// several different types). To find out the type of an attribute, use `cxxrtl_attr_type`, and +// to retrieve the value of an attribute, use `cxxrtl_attr_as_string`. +typedef struct _cxxrtl_attr_set *cxxrtl_attr_set; + +// Type of an attribute. +enum cxxrtl_attr_type { + // Attribute is not present. + CXXRTL_ATTR_NONE = 0, + + // Attribute has an unsigned integer value. + CXXRTL_ATTR_UNSIGNED_INT = 1, + + // Attribute has an unsigned integer value. + CXXRTL_ATTR_SIGNED_INT = 2, + + // Attribute has a string value. + CXXRTL_ATTR_STRING = 3, + + // Attribute has a double precision floating point value. + CXXRTL_ATTR_DOUBLE = 4, + + // More attribute types may be defined in the future, but the existing values will never change. +}; + +// Determine the presence and type of an attribute in an attribute set. +// +// This function returns one of the possible `cxxrtl_attr_type` values. +int cxxrtl_attr_type(cxxrtl_attr_set attrs, const char *name); + +// Retrieve an unsigned integer valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_UNSIGNED_INT`. +// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type. +uint64_t cxxrtl_attr_get_unsigned_int(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a signed integer valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_SIGNED_INT`. +// If assertions are disabled, returns 0 if the attribute is missing or has an incorrect type. +int64_t cxxrtl_attr_get_signed_int(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a string valued attribute from an attribute set. The returned string is zero-terminated. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_STRING`. If assertions +// are disabled, returns NULL if the attribute is missing or has an incorrect type. +const char *cxxrtl_attr_get_string(cxxrtl_attr_set attrs, const char *name); + +// Retrieve a double precision floating point valued attribute from an attribute set. +// +// This function asserts that `cxxrtl_attr_type(attrs, name) == CXXRTL_ATTR_DOUBLE`. If assertions +// are disabled, returns NULL if the attribute is missing or has an incorrect type. +double cxxrtl_attr_get_double(cxxrtl_attr_set attrs, const char *name); + #ifdef __cplusplus } #endif diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc similarity index 95% rename from yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc index 52a9198b869..0949a9363eb 100644 --- a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.cc +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc @@ -16,10 +16,10 @@ * */ -// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.h`. +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl/capi/cxxrtl_capi_vcd.h`. -#include -#include +#include +#include extern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle); diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.h b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h similarity index 97% rename from yosys/backends/cxxrtl/cxxrtl_vcd_capi.h rename to yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h index d55afe2230e..844f3cb8c83 100644 --- a/yosys/backends/cxxrtl/cxxrtl_vcd_capi.h +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h @@ -16,8 +16,8 @@ * */ -#ifndef CXXRTL_VCD_CAPI_H -#define CXXRTL_VCD_CAPI_H +#ifndef CXXRTL_CAPI_VCD_H +#define CXXRTL_CAPI_VCD_H // This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`. // @@ -27,7 +27,7 @@ #include #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/yosys/backends/cxxrtl/cxxrtl.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h similarity index 81% rename from yosys/backends/cxxrtl/cxxrtl.h rename to yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 5d0596f0d61..ee55011e86d 100644 --- a/yosys/backends/cxxrtl/cxxrtl.h +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -38,8 +39,10 @@ #include #include #include +#include -#include +// `cxxrtl::debug_item` has to inherit from `cxxrtl_object` to satisfy strict aliasing requirements. +#include #ifndef __has_attribute # define __has_attribute(x) 0 @@ -144,7 +147,7 @@ struct value : public expr_base> { // These functions ensure that a conversion is never out of range, and should be always used, if at all // possible, instead of direct manipulation of the `data` member. For very large types, .slice() and // .concat() can be used to split them into more manageable parts. - template + template::value, int>::type = 0> CXXRTL_ALWAYS_INLINE IntegerT get() const { static_assert(std::numeric_limits::is_integer && !std::numeric_limits::is_signed, @@ -157,15 +160,32 @@ struct value : public expr_base> { return result; } - template + template::value, int>::type = 0> CXXRTL_ALWAYS_INLINE - void set(IntegerT other) { + IntegerT get() const { + auto unsigned_result = get::type>(); + IntegerT result; + memcpy(&result, &unsigned_result, sizeof(IntegerT)); + return result; + } + + template::value, int>::type = 0> + CXXRTL_ALWAYS_INLINE + void set(IntegerT value) { static_assert(std::numeric_limits::is_integer && !std::numeric_limits::is_signed, "set() requires T to be an unsigned integral type"); static_assert(std::numeric_limits::digits >= Bits, "set() requires the value to be at least as wide as T is"); for (size_t n = 0; n < chunks; n++) - data[n] = (other >> (n * chunk::bits)) & chunk::mask; + data[n] = (value >> (n * chunk::bits)) & chunk::mask; + } + + template::value, int>::type = 0> + CXXRTL_ALWAYS_INLINE + void set(IntegerT value) { + typename std::make_unsigned::type unsigned_value; + memcpy(&unsigned_value, &value, sizeof(IntegerT)); + set(unsigned_value); } // Operations with compile-time parameters. @@ -418,6 +438,7 @@ struct value : public expr_base> { carry = (shift_bits == 0) ? 0 : data[n] >> (chunk::bits - shift_bits); } + result.data[result.chunks - 1] &= result.msb_mask; return result; } @@ -428,12 +449,12 @@ struct value : public expr_base> { // Detect shifts definitely large than Bits early. for (size_t n = 1; n < amount.chunks; n++) if (amount.data[n] != 0) - return {}; + return (Signed && is_neg()) ? value().bit_not() : value(); // Past this point we can use the least significant chunk as the shift size. size_t shift_chunks = amount.data[0] / chunk::bits; size_t shift_bits = amount.data[0] % chunk::bits; if (shift_chunks >= chunks) - return {}; + return (Signed && is_neg()) ? value().bit_not() : value(); value result; chunk::type carry = 0; for (size_t n = 0; n < chunks - shift_chunks; n++) { @@ -442,12 +463,13 @@ struct value : public expr_base> { : data[chunks - 1 - n] << (chunk::bits - shift_bits); } if (Signed && is_neg()) { - size_t top_chunk_idx = (Bits - shift_bits) / chunk::bits; - size_t top_chunk_bits = (Bits - shift_bits) % chunk::bits; + size_t top_chunk_idx = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) / chunk::bits; + size_t top_chunk_bits = amount.data[0] > Bits ? 0 : (Bits - amount.data[0]) % chunk::bits; for (size_t n = top_chunk_idx + 1; n < chunks; n++) result.data[n] = chunk::mask; - if (shift_bits != 0) + if (amount.data[0] != 0) result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits; + result.data[result.chunks - 1] &= result.msb_mask; } return result; } @@ -472,6 +494,7 @@ struct value : public expr_base> { carry = (shift_bits == 0) ? 0 : data[result.chunks + shift_chunks - 1 - n] << (chunk::bits - shift_bits); } + result.data[result.chunks - 1] &= result.msb_mask; return result; } @@ -507,12 +530,14 @@ struct value : public expr_base> { size_t count = 0; for (size_t n = 0; n < chunks; n++) { chunk::type x = data[chunks - 1 - n]; - if (x == 0) { - count += (n == 0 ? Bits % chunk::bits : chunk::bits); - } else { - // This loop implements the find first set idiom as recognized by LLVM. - for (; x != 0; count++) + // First add to `count` as if the chunk is zero + constexpr size_t msb_chunk_bits = Bits % chunk::bits != 0 ? Bits % chunk::bits : chunk::bits; + count += (n == 0 ? msb_chunk_bits : chunk::bits); + // If the chunk isn't zero, correct the `count` value and return + if (x != 0) { + for (; x != 0; count--) x >>= 1; + break; } } return count; @@ -541,7 +566,7 @@ struct value : public expr_base> { } value neg() const { - return value { 0u }.sub(*this); + return value().sub(*this); } bool ucmp(const value &other) const { @@ -575,6 +600,38 @@ struct value : public expr_base> { result.data[result.chunks - 1] &= result.msb_mask; return result; } + + std::pair, value> udivmod(value divisor) const { + value quotient; + value dividend = *this; + if (dividend.ucmp(divisor)) + return {/*quotient=*/value{0u}, /*remainder=*/dividend}; + int64_t divisor_shift = divisor.ctlz() - dividend.ctlz(); + assert(divisor_shift >= 0); + divisor = divisor.shl(value{(chunk::type) divisor_shift}); + for (size_t step = 0; step <= divisor_shift; step++) { + quotient = quotient.shl(value{1u}); + if (!dividend.ucmp(divisor)) { + dividend = dividend.sub(divisor); + quotient.set_bit(0, true); + } + divisor = divisor.shr(value{1u}); + } + return {quotient, /*remainder=*/dividend}; + } + + std::pair, value> sdivmod(const value &other) const { + value quotient; + value remainder; + value dividend = sext(); + value divisor = other.template sext(); + if (dividend.is_neg()) dividend = dividend.neg(); + if (divisor.is_neg()) divisor = divisor.neg(); + std::tie(quotient, remainder) = dividend.udivmod(divisor); + if (dividend.is_neg() != divisor.is_neg()) quotient = quotient.neg(); + if (dividend.is_neg()) remainder = remainder.neg(); + return {quotient.template trunc(), remainder.template trunc()}; + } }; // Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here. @@ -741,8 +798,13 @@ struct wire { next.template set(other); } - bool commit() { + // This method intentionally takes a mandatory argument (to make it more difficult to misuse in + // black box implementations, leading to missed observer events). It is generic over its argument + // to allow the `on_update` method to be non-virtual. + template + bool commit(ObserverT &observer) { if (curr != next) { + observer.on_update(curr.chunks, curr.data, next.data); curr = next; return true; } @@ -816,12 +878,17 @@ struct memory { write { index, val, mask, priority }); } - bool commit() { + // See the note for `wire::commit()`. + template + bool commit(ObserverT &observer) { bool changed = false; for (const write &entry : write_queue) { value elem = data[entry.index]; elem = elem.update(entry.val, entry.mask); - changed |= (data[entry.index] != elem); + if (data[entry.index] != elem) { + observer.on_update(value::chunks, data[0].data, elem.data, entry.index); + changed |= true; + } data[entry.index] = elem; } write_queue.clear(); @@ -840,14 +907,14 @@ struct metadata { // In debug mode, using the wrong .as_*() function will assert. // In release mode, using the wrong .as_*() function will safely return a default value. - const unsigned uint_value = 0; - const signed sint_value = 0; + const uint64_t uint_value = 0; + const int64_t sint_value = 0; const std::string string_value = ""; const double double_value = 0.0; metadata() : value_type(MISSING) {} - metadata(unsigned value) : value_type(UINT), uint_value(value) {} - metadata(signed value) : value_type(SINT), sint_value(value) {} + metadata(uint64_t value) : value_type(UINT), uint_value(value) {} + metadata(int64_t value) : value_type(SINT), sint_value(value) {} metadata(const std::string &value) : value_type(STRING), string_value(value) {} metadata(const char *value) : value_type(STRING), string_value(value) {} metadata(double value) : value_type(DOUBLE), double_value(value) {} @@ -855,12 +922,12 @@ struct metadata { metadata(const metadata &) = default; metadata &operator=(const metadata &) = delete; - unsigned as_uint() const { + uint64_t as_uint() const { assert(value_type == UINT); return uint_value; } - signed as_sint() const { + int64_t as_sint() const { assert(value_type == SINT); return sint_value; } @@ -878,6 +945,199 @@ struct metadata { typedef std::map metadata_map; +struct performer; + +// An object that allows formatting a string lazily. +struct lazy_fmt { + virtual std::string operator() () const = 0; +}; + +// Flavor of a `$check` cell. +enum class flavor { + // Corresponds to a `$assert` cell in other flows, and a Verilog `assert ()` statement. + ASSERT, + // Corresponds to a `$assume` cell in other flows, and a Verilog `assume ()` statement. + ASSUME, + // Corresponds to a `$live` cell in other flows, and a Verilog `assert (eventually)` statement. + ASSERT_EVENTUALLY, + // Corresponds to a `$fair` cell in other flows, and a Verilog `assume (eventually)` statement. + ASSUME_EVENTUALLY, + // Corresponds to a `$cover` cell in other flows, and a Verilog `cover ()` statement. + COVER, +}; + +// An object that can be passed to a `eval()` method in order to act on side effects. The default behavior implemented +// below is the same as the behavior of `eval(nullptr)`, except that `-print-output` option of `write_cxxrtl` is not +// taken into account. +struct performer { + // Called by generated formatting code to evaluate a Verilog `$time` expression. + virtual int64_t vlog_time() const { return 0; } + + // Called by generated formatting code to evaluate a Verilog `$realtime` expression. + virtual double vlog_realtime() const { return vlog_time(); } + + // Called when a `$print` cell is triggered. + virtual void on_print(const lazy_fmt &formatter, const metadata_map &attributes) { + std::cout << formatter(); + } + + // Called when a `$check` cell is triggered. + virtual void on_check(flavor type, bool condition, const lazy_fmt &formatter, const metadata_map &attributes) { + if (type == flavor::ASSERT || type == flavor::ASSUME) { + if (!condition) + std::cerr << formatter(); + CXXRTL_ASSERT(condition && "Check failed"); + } + } +}; + +// An object that can be passed to a `commit()` method in order to produce a replay log of every state change in +// the simulation. Unlike `performer`, `observer` does not use virtual calls as their overhead is unacceptable, and +// a comparatively heavyweight template-based solution is justified. +struct observer { + // Called when the `commit()` method for a wire is about to update the `chunks` chunks at `base` with `chunks` chunks + // at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to the wire chunk count and + // `base` points to the first chunk. + void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) {} + + // Called when the `commit()` method for a memory is about to update the `chunks` chunks at `&base[chunks * index]` + // with `chunks` chunks at `value` that have a different bit pattern. It is guaranteed that `chunks` is equal to + // the memory element chunk count and `base` points to the first chunk of the first element of the memory. + void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) {} +}; + +// Must be kept in sync with `struct FmtPart` in kernel/fmt.h! +// Default member initializers would make this a non-aggregate-type in C++11, so they are commented out. +struct fmt_part { + enum { + STRING = 0, + INTEGER = 1, + CHARACTER = 2, + VLOG_TIME = 3, + } type; + + // STRING type + std::string str; + + // INTEGER/CHARACTER types + // + value val; + + // INTEGER/CHARACTER/VLOG_TIME types + enum { + RIGHT = 0, + LEFT = 1, + } justify; // = RIGHT; + char padding; // = '\0'; + size_t width; // = 0; + + // INTEGER type + unsigned base; // = 10; + bool signed_; // = false; + bool plus; // = false; + + // VLOG_TIME type + bool realtime; // = false; + // + int64_t itime; + // + double ftime; + + // Format the part as a string. + // + // The values of `vlog_time` and `vlog_realtime` are used for Verilog `$time` and `$realtime`, correspondingly. + template + std::string render(value val, performer *performer = nullptr) + { + // We might want to replace some of these bit() calls with direct + // chunk access if it turns out to be slow enough to matter. + std::string buf; + switch (type) { + case STRING: + return str; + + case CHARACTER: { + buf.reserve(Bits/8); + for (int i = 0; i < Bits; i += 8) { + char ch = 0; + for (int j = 0; j < 8 && i + j < int(Bits); j++) + if (val.bit(i + j)) + ch |= 1 << j; + if (ch != 0) + buf.append({ch}); + } + std::reverse(buf.begin(), buf.end()); + break; + } + + case INTEGER: { + size_t width = Bits; + if (base != 10) { + width = 0; + for (size_t index = 0; index < Bits; index++) + if (val.bit(index)) + width = index + 1; + } + + if (base == 2) { + for (size_t i = width; i > 0; i--) + buf += (val.bit(i - 1) ? '1' : '0'); + } else if (base == 8 || base == 16) { + size_t step = (base == 16) ? 4 : 3; + for (size_t index = 0; index < width; index += step) { + uint8_t value = val.bit(index) | (val.bit(index + 1) << 1) | (val.bit(index + 2) << 2); + if (step == 4) + value |= val.bit(index + 3) << 3; + buf += "0123456789abcdef"[value]; + } + std::reverse(buf.begin(), buf.end()); + } else if (base == 10) { + bool negative = signed_ && val.is_neg(); + if (negative) + val = val.neg(); + if (val.is_zero()) + buf += '0'; + value<(Bits > 4 ? Bits : 4)> xval = val.template zext<(Bits > 4 ? Bits : 4)>(); + while (!xval.is_zero()) { + value<(Bits > 4 ? Bits : 4)> quotient, remainder; + if (Bits >= 4) + std::tie(quotient, remainder) = xval.udivmod(value<(Bits > 4 ? Bits : 4)>{10u}); + else + std::tie(quotient, remainder) = std::make_pair(value<(Bits > 4 ? Bits : 4)>{0u}, xval); + buf += '0' + remainder.template trunc<4>().template get(); + xval = quotient; + } + if (negative || plus) + buf += negative ? '-' : '+'; + std::reverse(buf.begin(), buf.end()); + } else assert(false && "Unsupported base for fmt_part"); + break; + } + + case VLOG_TIME: { + if (performer) { + buf = realtime ? std::to_string(performer->vlog_realtime()) : std::to_string(performer->vlog_time()); + } else { + buf = realtime ? std::to_string(0.0) : std::to_string(0); + } + break; + } + } + + std::string str; + assert(width == 0 || padding != '\0'); + if (justify == RIGHT && buf.size() < width) { + size_t pad_width = width - buf.size(); + if (padding == '0' && (buf.front() == '+' || buf.front() == '-')) { + str += buf.front(); + buf.erase(0, 1); + } + str += std::string(pad_width, padding); + } + str += buf; + if (justify == LEFT && buf.size() < width) + str += std::string(width - buf.size(), padding); + return str; + } +}; + // Tag class to disambiguate values/wires and their aliases. struct debug_alias {}; @@ -889,6 +1149,9 @@ using debug_outline = ::_cxxrtl_outline; // // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used // in the C API, or it would not be possible to cast between the pointers to these. +// +// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created +// from external C code. struct debug_item : ::cxxrtl_object { // Object types. enum : uint32_t { @@ -924,6 +1187,7 @@ struct debug_item : ::cxxrtl_object { curr = item.data; next = item.data; outline = nullptr; + attrs = nullptr; } template @@ -939,6 +1203,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -955,6 +1220,7 @@ struct debug_item : ::cxxrtl_object { curr = item.curr.data; next = item.next.data; outline = nullptr; + attrs = nullptr; } template @@ -970,6 +1236,7 @@ struct debug_item : ::cxxrtl_object { curr = item.data ? item.data[0].data : nullptr; next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -985,6 +1252,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1001,6 +1269,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.curr.data); next = nullptr; outline = nullptr; + attrs = nullptr; } template @@ -1016,6 +1285,7 @@ struct debug_item : ::cxxrtl_object { curr = const_cast(item.data); next = nullptr; outline = &group; + attrs = nullptr; } template @@ -1036,10 +1306,28 @@ struct debug_item : ::cxxrtl_object { }; static_assert(std::is_standard_layout::value, "debug_item is not compatible with C layout"); +} // namespace cxxrtl + +typedef struct _cxxrtl_attr_set { + cxxrtl::metadata_map map; +} *cxxrtl_attr_set; + +namespace cxxrtl { + +// Representation of an attribute set in the C++ interface. +using debug_attrs = ::_cxxrtl_attr_set; + struct debug_items { std::map> table; - - void add(const std::string &name, debug_item &&item) { + std::map> attrs_table; + + void add(const std::string &name, debug_item &&item, metadata_map &&item_attrs = {}) { + std::unique_ptr &attrs = attrs_table[name]; + if (attrs.get() == nullptr) + attrs = std::unique_ptr(new debug_attrs); + for (auto attr : item_attrs) + attrs->map.insert(attr); + item.attrs = attrs.get(); std::vector &parts = table[name]; parts.emplace_back(item); std::sort(parts.begin(), parts.end(), @@ -1067,6 +1355,10 @@ struct debug_items { const debug_item &operator [](const std::string &name) const { return at(name); } + + const metadata_map &attrs(const std::string &name) const { + return attrs_table.at(name)->map; + } }; // Tag class to disambiguate the default constructor used by the toplevel module that calls reset(), @@ -1088,14 +1380,14 @@ struct module { virtual void reset() = 0; - virtual bool eval() = 0; - virtual bool commit() = 0; + virtual bool eval(performer *performer = nullptr) = 0; + virtual bool commit() = 0; // commit observer isn't available since it avoids virtual calls - size_t step() { + size_t step(performer *performer = nullptr) { size_t deltas = 0; bool converged = false; do { - converged = eval(); + converged = eval(performer); deltas++; } while (commit() && !converged); return deltas; @@ -1520,35 +1812,23 @@ CXXRTL_ALWAYS_INLINE std::pair, value> divmod_uu(const value &a, const value &b) { constexpr size_t Bits = max(BitsY, max(BitsA, BitsB)); value quotient; + value remainder; value dividend = a.template zext(); value divisor = b.template zext(); - if (dividend.ucmp(divisor)) - return {/*quotient=*/value { 0u }, /*remainder=*/dividend.template trunc()}; - uint32_t divisor_shift = dividend.ctlz() - divisor.ctlz(); - divisor = divisor.shl(value<32> { divisor_shift }); - for (size_t step = 0; step <= divisor_shift; step++) { - quotient = quotient.shl(value<1> { 1u }); - if (!dividend.ucmp(divisor)) { - dividend = dividend.sub(divisor); - quotient.set_bit(0, true); - } - divisor = divisor.shr(value<1> { 1u }); - } - return {quotient.template trunc(), /*remainder=*/dividend.template trunc()}; + std::tie(quotient, remainder) = dividend.udivmod(divisor); + return {quotient.template trunc(), remainder.template trunc()}; } template CXXRTL_ALWAYS_INLINE std::pair, value> divmod_ss(const value &a, const value &b) { - value ua = a.template sext(); - value ub = b.template sext(); - if (ua.is_neg()) ua = ua.neg(); - if (ub.is_neg()) ub = ub.neg(); - value y, r; - std::tie(y, r) = divmod_uu(ua, ub); - if (a.is_neg() != b.is_neg()) y = y.neg(); - if (a.is_neg()) r = r.neg(); - return {y, r}; + constexpr size_t Bits = max(BitsY, max(BitsA, BitsB)); + value quotient; + value remainder; + value dividend = a.template sext(); + value divisor = b.template sext(); + std::tie(quotient, remainder) = dividend.sdivmod(divisor); + return {quotient.template trunc(), remainder.template trunc()}; } template diff --git a/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h new file mode 100644 index 00000000000..d824fdb83c8 --- /dev/null +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h @@ -0,0 +1,783 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 Catherine + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CXXRTL_REPLAY_H +#define CXXRTL_REPLAY_H + +#if !defined(WIN32) +#include +#define O_BINARY 0 +#else +#include +#endif + +#include +#include +#include +#include +#include + +#include +#include + +// Theory of operation +// =================== +// +// Log format +// ---------- +// +// The replay log is a simple data format based on a sequence of 32-bit words. The following BNF-like grammar describes +// enough detail to understand the overall structure of the log data and be able to read hex dumps. For a greater +// degree of detail see the source code. The format is considered fully internal to CXXRTL and is subject to change +// without notice. +// +// ::= + +// ::= 0x52585843 0x00004c54 +// ::= * +// ::= * +// ::= 0xc0000000 ... +// ::= 0xc0000001 ... +// ::= 0x0??????? + | 0x1??????? + | 0x2??????? | 0x3??????? +// , ::= 0x???????? +// ::= 0xFFFFFFFF +// +// The replay log contains sample data, however, it does not cover the entire design. Rather, it only contains sample +// data for the subset of debug items containing _design state_: inputs and registers/latches. This keeps its size to +// a minimum, and recording speed to a maximum. The player samples any missing data by setting the design state items +// to the same values they had during recording, and re-evaluating the design. +// +// Limits +// ------ +// +// The log may contain: +// +// * Up to 2**28-1 debug items containing design state. +// * Up to 2**32 chunks per debug item. +// * Up to 2**32 rows per memory. +// * Up to 2**32 samples. +// +// Of these limits, the last two are most likely to be eventually exceeded by practical recordings. However, other +// performance considerations will likely limit the size of such practical recordings first, so the log data format +// will undergo a breaking change at that point. +// +// Operations +// ---------- +// +// As suggested by the name "replay log", this format is designed for recording (writing) once and playing (reading) +// many times afterwards, such that reading the format can be done linearly and quickly. The log format is designed to +// support three primary read operations: +// +// 1. Initialization +// 2. Rewinding (to time T) +// 3. Replaying (for N samples) +// +// During initialization, the player establishes the mapping between debug item names and their 28-bit identifiers in +// the log. It is done once. +// +// During rewinding, the player begins reading at the latest non-incremental sample that still lies before the requested +// sample time. It continues reading incremental samples after that point until it reaches the requested sample time. +// This process is very cheap as the design is not evaluated; it is essentially a (convoluted) memory copy operation. +// +// During replaying, the player evaluates the design at the current time, which causes all debug items to assume +// the values they had before recording. This process is expensive. Once done, the player advances to the next state +// by reading the next (complete or incremental) sample, as above. Since a range of samples is replayed, this process +// is repeated several times in a row. +// +// In principle, when replaying, the player could only read the state of the inputs and the time delta and use a normal +// eval/commit loop to progress the simulation, which is fully deterministic so its calculated design state should be +// exactly the same as the recorded design state. In practice, it is both faster and more reliable (in presence of e.g. +// user-defined black boxes) to read the recorded values instead of calculating them. +// +// Note: The operations described above are conceptual and do not correspond exactly to methods on `cxxrtl::player`. +// The `cxxrtl::player::replay()` method does not evaluate the design. This is so that delta cycles could be ignored +// if they are not of interest while replaying. + +namespace cxxrtl { + +// A spool stores CXXRTL design state changes in a file. +class spool { +public: + // Unique pointer to a specific sample within a replay log. (Timestamps are not unique.) + typedef uint32_t pointer_t; + + // Numeric identifier assigned to a debug item within a replay log. Range limited to [1, MAXIMUM_IDENT]. + typedef uint32_t ident_t; + + static constexpr uint16_t VERSION = 0x0400; + + static constexpr uint64_t HEADER_MAGIC = 0x00004c5452585843; + static constexpr uint64_t VERSION_MASK = 0xffff000000000000; + + static constexpr uint32_t PACKET_DEFINE = 0xc0000000; + + static constexpr uint32_t PACKET_SAMPLE = 0xc0000001; + enum sample_flag : uint32_t { + EMPTY = 0, + INCREMENTAL = 1, + }; + + static constexpr uint32_t MAXIMUM_IDENT = 0x0fffffff; + static constexpr uint32_t CHANGE_MASK = 0x30000000; + + static constexpr uint32_t PACKET_CHANGE = 0x00000000/* | ident */; + static constexpr uint32_t PACKET_CHANGEI = 0x10000000/* | ident */; + static constexpr uint32_t PACKET_CHANGEL = 0x20000000/* | ident */; + static constexpr uint32_t PACKET_CHANGEH = 0x30000000/* | ident */; + + static constexpr uint32_t PACKET_END = 0xffffffff; + + // Writing spools. + + class writer { + int fd; + size_t position; + std::vector buffer; + + // These functions aren't overloaded because of implicit numeric conversions. + + void emit_word(uint32_t word) { + if (position + 1 == buffer.size()) + flush(); + buffer[position++] = word; + } + + void emit_dword(uint64_t dword) { + emit_word(dword >> 0); + emit_word(dword >> 32); + } + + void emit_ident(ident_t ident) { + assert(ident <= MAXIMUM_IDENT); + emit_word(ident); + } + + void emit_size(size_t size) { + assert(size <= std::numeric_limits::max()); + emit_word(size); + } + + // Same implementation as `emit_size()`, different declared intent. + void emit_index(size_t index) { + assert(index <= std::numeric_limits::max()); + emit_word(index); + } + + void emit_string(std::string str) { + // Align to a word boundary, and add at least one terminating \0. + str.resize(str.size() + (sizeof(uint32_t) - (str.size() + sizeof(uint32_t)) % sizeof(uint32_t))); + for (size_t index = 0; index < str.size(); index += sizeof(uint32_t)) { + uint32_t word; + memcpy(&word, &str[index], sizeof(uint32_t)); + emit_word(word); + } + } + + void emit_time(const time ×tamp) { + const value &raw_timestamp(timestamp); + emit_word(raw_timestamp.data[0]); + emit_word(raw_timestamp.data[1]); + emit_word(raw_timestamp.data[2]); + } + + public: + // Creates a writer, and transfers ownership of `fd`, which must be open for appending. + // + // The buffer size is currently fixed to a "reasonably large" size, determined empirically by measuring writer + // performance on a representative design; large but not so large it would e.g. cause address space exhaustion + // on 32-bit platforms. + writer(spool &spool) : fd(spool.take_write()), position(0), buffer(32 * 1024 * 1024) { + assert(fd != -1); +#if !defined(WIN32) + int result = ftruncate(fd, 0); +#else + int result = _chsize_s(fd, 0); +#endif + assert(result == 0); + } + + writer(writer &&moved) : fd(moved.fd), position(moved.position), buffer(moved.buffer) { + moved.fd = -1; + moved.position = 0; + } + + writer(const writer &) = delete; + writer &operator=(const writer &) = delete; + + // Both write() calls and fwrite() calls are too expensive to perform implicitly. The API consumer must determine + // the optimal time to flush the writer and do that explicitly for best performance. + void flush() { + assert(fd != -1); + size_t data_size = position * sizeof(uint32_t); + size_t data_written = write(fd, buffer.data(), data_size); + assert(data_size == data_written); + position = 0; + } + + ~writer() { + if (fd != -1) { + flush(); + close(fd); + } + } + + void write_magic() { + // `CXXRTL` followed by version in binary. This header will read backwards on big-endian machines, which allows + // detection of this case, both visually and programmatically. + emit_dword(((uint64_t)VERSION << 48) | HEADER_MAGIC); + } + + void write_define(ident_t ident, const std::string &name, size_t part_index, size_t chunks, size_t depth) { + emit_word(PACKET_DEFINE); + emit_ident(ident); + emit_string(name); + emit_index(part_index); + emit_size(chunks); + emit_size(depth); + } + + void write_sample(bool incremental, pointer_t pointer, const time ×tamp) { + uint32_t flags = (incremental ? sample_flag::INCREMENTAL : 0); + emit_word(PACKET_SAMPLE); + emit_word(flags); + emit_word(pointer); + emit_time(timestamp); + } + + void write_change(ident_t ident, size_t chunks, const chunk_t *data) { + assert(ident <= MAXIMUM_IDENT); + + if (chunks == 1 && *data == 0) { + emit_word(PACKET_CHANGEL | ident); + } else if (chunks == 1 && *data == 1) { + emit_word(PACKET_CHANGEH | ident); + } else { + emit_word(PACKET_CHANGE | ident); + for (size_t offset = 0; offset < chunks; offset++) + emit_word(data[offset]); + } + } + + void write_change(ident_t ident, size_t chunks, const chunk_t *data, size_t index) { + assert(ident <= MAXIMUM_IDENT); + + emit_word(PACKET_CHANGEI | ident); + emit_index(index); + for (size_t offset = 0; offset < chunks; offset++) + emit_word(data[offset]); + } + + void write_end() { + emit_word(PACKET_END); + } + }; + + // Reading spools. + + class reader { + FILE *f; + + uint32_t absorb_word() { + // If we're at end of file, `fread` will not write to `word`, and `PACKET_END` will be returned. + uint32_t word = PACKET_END; + fread(&word, sizeof(word), 1, f); + return word; + } + + uint64_t absorb_dword() { + uint32_t lo = absorb_word(); + uint32_t hi = absorb_word(); + return ((uint64_t)hi << 32) | lo; + } + + ident_t absorb_ident() { + ident_t ident = absorb_word(); + assert(ident <= MAXIMUM_IDENT); + return ident; + } + + size_t absorb_size() { + return absorb_word(); + } + + size_t absorb_index() { + return absorb_word(); + } + + std::string absorb_string() { + std::string str; + do { + size_t end = str.size(); + str.resize(end + 4); + uint32_t word = absorb_word(); + memcpy(&str[end], &word, sizeof(uint32_t)); + } while (str.back() != '\0'); + // Strings have no embedded zeroes besides the terminating one(s). + return str.substr(0, str.find('\0')); + } + + time absorb_time() { + value raw_timestamp; + raw_timestamp.data[0] = absorb_word(); + raw_timestamp.data[1] = absorb_word(); + raw_timestamp.data[2] = absorb_word(); + return time(raw_timestamp); + } + + public: + typedef uint64_t pos_t; + + // Creates a reader, and transfers ownership of `fd`, which must be open for reading. + reader(spool &spool) : f(fdopen(spool.take_read(), "r")) { + assert(f != nullptr); + } + + reader(reader &&moved) : f(moved.f) { + moved.f = nullptr; + } + + reader(const reader &) = delete; + reader &operator=(const reader &) = delete; + + ~reader() { + if (f != nullptr) + fclose(f); + } + + pos_t position() { + return ftell(f); + } + + void rewind(pos_t position) { + fseek(f, position, SEEK_SET); + } + + void read_magic() { + uint64_t magic = absorb_dword(); + assert((magic & ~VERSION_MASK) == HEADER_MAGIC); + assert((magic >> 48) == VERSION); + } + + bool read_define(ident_t &ident, std::string &name, size_t &part_index, size_t &chunks, size_t &depth) { + uint32_t header = absorb_word(); + if (header == PACKET_END) + return false; + assert(header == PACKET_DEFINE); + ident = absorb_ident(); + name = absorb_string(); + part_index = absorb_index(); + chunks = absorb_size(); + depth = absorb_size(); + return true; + } + + bool read_sample(bool &incremental, pointer_t &pointer, time ×tamp) { + uint32_t header = absorb_word(); + if (header == PACKET_END) + return false; + assert(header == PACKET_SAMPLE); + uint32_t flags = absorb_word(); + incremental = (flags & sample_flag::INCREMENTAL); + pointer = absorb_word(); + timestamp = absorb_time(); + return true; + } + + bool read_change_header(uint32_t &header, ident_t &ident) { + header = absorb_word(); + if (header == PACKET_END) + return false; + assert((header & ~(CHANGE_MASK | MAXIMUM_IDENT)) == 0); + ident = header & MAXIMUM_IDENT; + return true; + } + + void read_change_data(uint32_t header, size_t chunks, size_t depth, chunk_t *data) { + uint32_t index = 0; + switch (header & CHANGE_MASK) { + case PACKET_CHANGEL: + *data = 0; + return; + case PACKET_CHANGEH: + *data = 1; + return; + case PACKET_CHANGE: + break; + case PACKET_CHANGEI: + index = absorb_word(); + assert(index < depth); + break; + default: + assert(false && "Unrecognized change packet"); + } + for (size_t offset = 0; offset < chunks; offset++) + data[chunks * index + offset] = absorb_word(); + } + }; + + // Opening spools. For certain uses of the record/replay mechanism, two distinct open files (two open files, i.e. + // two distinct file pointers, and not just file descriptors, which share the file pointer if duplicated) are used, + // for a reader and writer thread. This class manages the lifetime of the descriptors for these files. When only + // one of them is used, the other is closed harmlessly when the spool is destroyed. +private: + std::atomic writefd; + std::atomic readfd; + +public: + spool(const std::string &filename) + : writefd(open(filename.c_str(), O_CREAT|O_BINARY|O_WRONLY|O_APPEND, 0644)), + readfd(open(filename.c_str(), O_BINARY|O_RDONLY)) { + assert(writefd.load() != -1 && readfd.load() != -1); + } + + spool(spool &&moved) : writefd(moved.writefd.exchange(-1)), readfd(moved.readfd.exchange(-1)) {} + + spool(const spool &) = delete; + spool &operator=(const spool &) = delete; + + ~spool() { + if (int fd = writefd.exchange(-1)) + close(fd); + if (int fd = readfd.exchange(-1)) + close(fd); + } + + // Atomically acquire a write file descriptor for the spool. Can be called once, and will return -1 the next time + // it is called. Thread-safe. + int take_write() { + return writefd.exchange(-1); + } + + // Atomically acquire a read file descriptor for the spool. Can be called once, and will return -1 the next time + // it is called. Thread-safe. + int take_read() { + return readfd.exchange(-1); + } +}; + +// A CXXRTL recorder samples design state, producing complete or incremental updates, and writes them to a spool. +class recorder { + struct variable { + spool::ident_t ident; /* <= spool::MAXIMUM_IDENT */ + size_t chunks; + size_t depth; /* == 1 for wires */ + chunk_t *curr; + bool memory; + }; + + spool::writer writer; + std::vector variables; + std::vector inputs; // values of inputs must be recorded explicitly, as their changes are not observed + std::unordered_map ident_lookup; + bool streaming = false; // whether variable definitions have been written + spool::pointer_t pointer = 0; + time timestamp; + +public: + template + recorder(Args &&...args) : writer(std::forward(args)...) {} + + void start(module &module) { + debug_items items; + module.debug_info(items); + start(items); + } + + void start(const debug_items &items) { + assert(!streaming); + + writer.write_magic(); + for (auto item : items.table) + for (size_t part_index = 0; part_index < item.second.size(); part_index++) { + auto &part = item.second[part_index]; + if ((part.flags & debug_item::INPUT) || (part.flags & debug_item::DRIVEN_SYNC) || + (part.type == debug_item::MEMORY)) { + variable var; + var.ident = variables.size() + 1; + var.chunks = (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8); + var.depth = part.depth; + var.curr = part.curr; + var.memory = (part.type == debug_item::MEMORY); + ident_lookup[var.curr] = var.ident; + + assert(variables.size() < spool::MAXIMUM_IDENT); + if (part.flags & debug_item::INPUT) + inputs.push_back(variables.size()); + variables.push_back(var); + + writer.write_define(var.ident, item.first, part_index, var.chunks, var.depth); + } + } + writer.write_end(); + streaming = true; + } + + const time &latest_time() { + return timestamp; + } + + const time &advance_time(const time &delta) { + assert(!delta.is_negative()); + timestamp += delta; + return timestamp; + } + + void record_complete() { + assert(streaming); + + writer.write_sample(/*incremental=*/false, pointer++, timestamp); + for (auto var : variables) { + assert(var.ident != 0); + if (!var.memory) + writer.write_change(var.ident, var.chunks, var.curr); + else + for (size_t index = 0; index < var.depth; index++) + writer.write_change(var.ident, var.chunks, &var.curr[var.chunks * index], index); + } + writer.write_end(); + } + + // This function is generic over ModuleT to encourage observer callbacks to be inlined into the commit function. + template + bool record_incremental(ModuleT &module) { + assert(streaming); + + struct { + std::unordered_map *ident_lookup; + spool::writer *writer; + + CXXRTL_ALWAYS_INLINE + void on_update(size_t chunks, const chunk_t *base, const chunk_t *value) { + writer->write_change(ident_lookup->at(base), chunks, value); + } + + CXXRTL_ALWAYS_INLINE + void on_update(size_t chunks, const chunk_t *base, const chunk_t *value, size_t index) { + writer->write_change(ident_lookup->at(base), chunks, value, index); + } + } record_observer = { &ident_lookup, &writer }; + + writer.write_sample(/*incremental=*/true, pointer++, timestamp); + for (auto input_index : inputs) { + variable &var = variables.at(input_index); + assert(!var.memory); + writer.write_change(var.ident, var.chunks, var.curr); + } + bool changed = module.commit(record_observer); + writer.write_end(); + return changed; + } + + void flush() { + writer.flush(); + } +}; + +// A CXXRTL player reads samples from a spool, and changes the design state accordingly. To start reading samples, +// a spool must have been initialized: the recorder must have been started and an initial complete sample must have +// been written. +class player { + struct variable { + size_t chunks; + size_t depth; /* == 1 for wires */ + chunk_t *curr; + }; + + spool::reader reader; + std::unordered_map variables; + bool streaming = false; // whether variable definitions have been read + bool initialized = false; // whether a sample has ever been read + spool::pointer_t pointer = 0; + time timestamp; + + std::map> index_by_pointer; + std::map> index_by_timestamp; + + bool peek_sample(spool::pointer_t &pointer, time ×tamp) { + bool incremental; + auto position = reader.position(); + bool success = reader.read_sample(incremental, pointer, timestamp); + reader.rewind(position); + return success; + } + +public: + template + player(Args &&...args) : reader(std::forward(args)...) {} + + void start(module &module) { + debug_items items; + module.debug_info(items); + start(items); + } + + void start(const debug_items &items) { + assert(!streaming); + + reader.read_magic(); + while (true) { + spool::ident_t ident; + std::string name; + size_t part_index; + size_t chunks; + size_t depth; + if (!reader.read_define(ident, name, part_index, chunks, depth)) + break; + assert(variables.count(ident) == 0); + assert(items.count(name) != 0); + assert(part_index < items.count(name)); + + const debug_item &part = items.parts_at(name).at(part_index); + assert(chunks == (part.width + sizeof(chunk_t) * 8 - 1) / (sizeof(chunk_t) * 8)); + assert(depth == part.depth); + + variable &var = variables[ident]; + var.chunks = chunks; + var.depth = depth; + var.curr = part.curr; + } + assert(variables.size() > 0); + streaming = true; + + // Establish the initial state of the design. + initialized = replay(); + assert(initialized); + } + + // Returns the pointer of the current sample. + spool::pointer_t current_pointer() { + assert(initialized); + return pointer; + } + + // Returns the time of the current sample. + const time ¤t_time() { + assert(initialized); + return timestamp; + } + + // Returns `true` if there is a next sample to read, and sets `pointer` to its pointer if there is. + bool get_next_pointer(spool::pointer_t &pointer) { + assert(streaming); + time timestamp; + return peek_sample(pointer, timestamp); + } + + // Returns `true` if there is a next sample to read, and sets `timestamp` to its time if there is. + bool get_next_time(time ×tamp) { + assert(streaming); + uint32_t pointer; + return peek_sample(pointer, timestamp); + } + + // If this function returns `true`, then `current_pointer() == at_pointer`, and the module contains values that + // correspond to this pointer in the replay log. To obtain a valid pointer, call `current_pointer()`; while pointers + // are monotonically increasing for each consecutive sample, using arithmetic operations to create a new pointer is + // not allowed. + bool rewind_to(spool::pointer_t at_pointer) { + assert(initialized); + + // The pointers in the replay log start from one that is greater than `at_pointer`. In this case the pointer will + // never be reached. + assert(index_by_pointer.size() > 0); + if (at_pointer < index_by_pointer.rbegin()->first) + return false; + + // Find the last complete sample whose pointer is less than or equal to `at_pointer`. Note that the comparison + // function used here is `std::greater`, inverting the direction of `lower_bound`. + auto position_it = index_by_pointer.lower_bound(at_pointer); + assert(position_it != index_by_pointer.end()); + reader.rewind(position_it->second); + + // Replay samples until eventually arriving to `at_pointer` or encountering end of file. + while(replay()) { + if (pointer == at_pointer) + return true; + } + return false; + } + + // If this function returns `true`, then `current_time() <= at_or_before_timestamp`, and the module contains values + // that correspond to `current_time()` in the replay log. If `current_time() == at_or_before_timestamp` and there + // are several consecutive samples with the same time, the module contains values that correspond to the first of + // these samples. + bool rewind_to_or_before(const time &at_or_before_timestamp) { + assert(initialized); + + // The timestamps in the replay log start from one that is greater than `at_or_before_timestamp`. In this case + // the timestamp will never be reached. Otherwise, this function will always succeed. + assert(index_by_timestamp.size() > 0); + if (at_or_before_timestamp < index_by_timestamp.rbegin()->first) + return false; + + // Find the last complete sample whose timestamp is less than or equal to `at_or_before_timestamp`. Note that + // the comparison function used here is `std::greater`, inverting the direction of `lower_bound`. + auto position_it = index_by_timestamp.lower_bound(at_or_before_timestamp); + assert(position_it != index_by_timestamp.end()); + reader.rewind(position_it->second); + + // Replay samples until eventually arriving to or past `at_or_before_timestamp` or encountering end of file. + while (replay()) { + if (timestamp == at_or_before_timestamp) + break; + + time next_timestamp; + if (!get_next_time(next_timestamp)) + break; + if (next_timestamp > at_or_before_timestamp) + break; + } + return true; + } + + // If this function returns `true`, then `current_pointer()` and `current_time()` are updated for the next sample + // and the module now contains values that correspond to that sample. If it returns `false`, there was no next sample + // to read. + bool replay() { + assert(streaming); + + bool incremental; + auto position = reader.position(); + if (!reader.read_sample(incremental, pointer, timestamp)) + return false; + + // The very first sample that is read must be a complete sample. This is required for the rewind functions to work. + assert(initialized || !incremental); + + // It is possible (though not very useful) to have several complete samples with the same timestamp in a row. + // Ensure that we associate the timestamp with the position of the first such complete sample. (This condition + // works because the player never jumps over a sample.) + if (!incremental && !index_by_pointer.count(pointer)) { + assert(!index_by_timestamp.count(timestamp)); + index_by_pointer[pointer] = position; + index_by_timestamp[timestamp] = position; + } + + uint32_t header; + spool::ident_t ident; + variable var; + while (reader.read_change_header(header, ident)) { + variable &var = variables.at(ident); + reader.read_change_data(header, var.chunks, var.depth, var.curr); + } + return true; + } +}; + +} + +#endif diff --git a/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h new file mode 100644 index 00000000000..f37c2b65640 --- /dev/null +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h @@ -0,0 +1,231 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 Catherine + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CXXRTL_TIME_H +#define CXXRTL_TIME_H + +#include +#include + +#include + +namespace cxxrtl { + +// A timestamp or a difference in time, stored as a 96-bit number of femtoseconds (10e-15 s). The range and resolution +// of this format can represent any VCD timestamp within approx. ±1255321.2 years, without the need for a timescale. +class time { +public: + static constexpr size_t bits = 96; // 3 chunks + +private: + static constexpr size_t resolution_digits = 15; + + static_assert(sizeof(chunk_t) == 4, "a chunk is expected to be 32-bit"); + static constexpr value resolution = value { + chunk_t(1000000000000000ull & 0xffffffffull), chunk_t(1000000000000000ull >> 32), 0u + }; + + // Signed number of femtoseconds from the beginning of time. + value raw; + +public: + constexpr time() {} + + explicit constexpr time(const value &raw) : raw(raw) {} + explicit operator const value &() const { return raw; } + + static constexpr time maximum() { + return time(value { 0xffffffffu, 0xffffffffu, 0x7fffffffu }); + } + + time(int64_t secs, int64_t femtos) { + value<64> secs_val; + secs_val.set(secs); + value<64> femtos_val; + femtos_val.set(femtos); + raw = secs_val.sext().mul(resolution).add(femtos_val.sext()); + } + + bool is_zero() const { + return raw.is_zero(); + } + + // Extracts the sign of the value. + bool is_negative() const { + return raw.is_neg(); + } + + // Extracts the number of whole seconds. Negative if the value is negative. + int64_t secs() const { + return raw.sdivmod(resolution).first.trunc<64>().get(); + } + + // Extracts the number of femtoseconds in the fractional second. Negative if the value is negative. + int64_t femtos() const { + return raw.sdivmod(resolution).second.trunc<64>().get(); + } + + bool operator==(const time &other) const { + return raw == other.raw; + } + + bool operator!=(const time &other) const { + return raw != other.raw; + } + + bool operator>(const time &other) const { + return other.raw.scmp(raw); + } + + bool operator>=(const time &other) const { + return !raw.scmp(other.raw); + } + + bool operator<(const time &other) const { + return raw.scmp(other.raw); + } + + bool operator<=(const time &other) const { + return !other.raw.scmp(raw); + } + + time operator+(const time &other) const { + return time(raw.add(other.raw)); + } + + time &operator+=(const time &other) { + *this = *this + other; + return *this; + } + + time operator-() const { + return time(raw.neg()); + } + + time operator-(const time &other) const { + return *this + (-other); + } + + time &operator-=(const time &other) { + *this = *this - other; + return *this; + } + + operator std::string() const { + char buf[48]; // x=2**95; len(f"-{x/1_000_000_000_000_000}.{x^1_000_000_000_000_000}") == 48 + int64_t secs = this->secs(); + int64_t femtos = this->femtos(); + snprintf(buf, sizeof(buf), "%s%" PRIi64 ".%015" PRIi64, + is_negative() ? "-" : "", secs >= 0 ? secs : -secs, femtos >= 0 ? femtos : -femtos); + return buf; + } + +#if __cplusplus >= 201603L + [[nodiscard("ignoring parse errors")]] +#endif + bool parse(const std::string &str) { + enum { + parse_sign_opt, + parse_integral, + parse_fractional, + } state = parse_sign_opt; + bool negative = false; + int64_t integral = 0; + int64_t fractional = 0; + size_t frac_digits = 0; + for (auto chr : str) { + switch (state) { + case parse_sign_opt: + state = parse_integral; + if (chr == '+' || chr == '-') { + negative = (chr == '-'); + break; + } + /* fallthrough */ + case parse_integral: + if (chr >= '0' && chr <= '9') { + integral *= 10; + integral += chr - '0'; + } else if (chr == '.') { + state = parse_fractional; + } else { + return false; + } + break; + case parse_fractional: + if (chr >= '0' && chr <= '9' && frac_digits < resolution_digits) { + fractional *= 10; + fractional += chr - '0'; + frac_digits++; + } else { + return false; + } + break; + } + } + if (frac_digits == 0) + return false; + while (frac_digits++ < resolution_digits) + fractional *= 10; + *this = negative ? -time { integral, fractional} : time { integral, fractional }; + return true; + } +}; + +// Out-of-line definition required until C++17. +constexpr value time::resolution; + +std::ostream &operator<<(std::ostream &os, const time &val) { + os << (std::string)val; + return os; +} + +// These literals are (confusingly) compatible with the ones from `std::chrono`: the `std::chrono` literals do not +// have an underscore (e.g. 1ms) and the `cxxrtl::time` literals do (e.g. 1_ms). This syntactic difference is +// a requirement of the C++ standard. Despite being compatible the literals should not be mixed in the same namespace. +namespace time_literals { + +time operator""_s(unsigned long long seconds) { + return time { (int64_t)seconds, 0 }; +} + +time operator""_ms(unsigned long long milliseconds) { + return time { 0, (int64_t)milliseconds * 1000000000000 }; +} + +time operator""_us(unsigned long long microseconds) { + return time { 0, (int64_t)microseconds * 1000000000 }; +} + +time operator""_ns(unsigned long long nanoseconds) { + return time { 0, (int64_t)nanoseconds * 1000000 }; +} + +time operator""_ps(unsigned long long picoseconds) { + return time { 0, (int64_t)picoseconds * 1000 }; +} + +time operator""_fs(unsigned long long femtoseconds) { + return time { 0, (int64_t)femtoseconds }; +} + +}; + +}; + +#endif diff --git a/yosys/backends/cxxrtl/cxxrtl_vcd.h b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h similarity index 99% rename from yosys/backends/cxxrtl/cxxrtl_vcd.h rename to yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h index b76922bbd8a..cb2ccf5fc26 100644 --- a/yosys/backends/cxxrtl/cxxrtl_vcd.h +++ b/yosys/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h @@ -19,7 +19,7 @@ #ifndef CXXRTL_VCD_H #define CXXRTL_VCD_H -#include +#include namespace cxxrtl { diff --git a/yosys/backends/firrtl/test.sh b/yosys/backends/firrtl/test.sh index fe7e3a32912..dd675e91712 100644 --- a/yosys/backends/firrtl/test.sh +++ b/yosys/backends/firrtl/test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex cd ../../ diff --git a/yosys/backends/simplec/test00.sh b/yosys/backends/simplec/test00.sh index ede75727378..9895a97e46b 100644 --- a/yosys/backends/simplec/test00.sh +++ b/yosys/backends/simplec/test00.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex ../../yosys -p 'synth -top test; write_simplec -verbose -i8 test00_uut.c' test00_uut.v clang -o test00_tb test00_tb.c diff --git a/yosys/backends/smt2/smtbmc.py b/yosys/backends/smt2/smtbmc.py index 02e15a1b502..34657be264a 100644 --- a/yosys/backends/smt2/smtbmc.py +++ b/yosys/backends/smt2/smtbmc.py @@ -17,7 +17,7 @@ # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. # -import os, sys, getopt, re, bisect +import os, sys, getopt, re, bisect, json ##yosys-sys-path## from smtio import SmtIo, SmtOpts, MkVcd from ywio import ReadWitness, WriteWitness, WitnessValues @@ -56,6 +56,7 @@ keep_going = False check_witness = False detect_loops = False +incremental = None so = SmtOpts() @@ -185,6 +186,9 @@ def help(): check if states are unique in temporal induction counter examples (this feature is experimental and incomplete) + --incremental + run in incremental mode (experimental) + """ + so.helpmsg()) def usage(): @@ -196,7 +200,7 @@ def usage(): opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:higcm:", so.longopts + ["help", "final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "yw=", "btorwit=", "presat", "dump-vcd=", "dump-yw=", "dump-vlogtb=", "vlogtb-top=", "dump-smtc=", "dump-all", "noinfo", "append=", - "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops"]) + "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops", "incremental"]) except: usage() @@ -282,6 +286,9 @@ def usage(): check_witness = True elif o == "--detect-loops": detect_loops = True + elif o == "--incremental": + from smtbmc_incremental import Incremental + incremental = Incremental() elif so.handle(o, a): pass else: @@ -290,7 +297,7 @@ def usage(): if len(args) != 1: usage() -if sum([tempind, gentrace, covermode]) > 1: +if sum([tempind, gentrace, covermode, incremental is not None]) > 1: usage() constr_final_start = None @@ -444,8 +451,10 @@ def replace_netref(match): smt.produce_models = False def print_msg(msg): - print("%s %s" % (smt.timestamp(), msg)) - sys.stdout.flush() + if incremental: + incremental.print_msg(msg) + else: + print("%s %s" % (smt.timestamp(), msg), flush=True) print_msg("Solver: %s" % (so.solver)) @@ -640,10 +649,9 @@ def print_msg(msg): num_steps = max(num_steps, step+2) step += 1 -if inywfile is not None: - if not got_topt: - skip_steps = 0 - num_steps = 0 +def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False): + if map_steps is None: + map_steps = {} with open(inywfile, "r") as f: inyw = ReadWitness(f) @@ -662,10 +670,14 @@ def print_msg(msg): addr_re = re.compile(r'\\\[[0-9]+\]$') bits_re = re.compile(r'[01?]*$') + max_t = -1 + for t, step in inyw.steps(): present_signals, missing = step.present_signals(inyw.sigmap) for sig in present_signals: bits = step[sig] + if skip_x: + bits = bits.replace('x', '?') if not bits_re.match(bits): raise ValueError("unsupported bit value in Yosys witness file") @@ -684,7 +696,7 @@ def print_msg(msg): if common_end <= common_offset: continue - smt_expr = smt.witness_net_expr(topmod, f"s{t}", wire) + smt_expr = smt.witness_net_expr(topmod, f"s{map_steps.get(t, t)}", wire) if not smt_bool: slice_high = common_end - offset - 1 @@ -714,7 +726,7 @@ def print_msg(msg): for mem in smt_mems[sig.memory_path]: width, size, bv = mem["width"], mem["size"], mem["statebv"] - smt_expr = smt.net_expr(topmod, f"s{t}", mem["smtpath"]) + smt_expr = smt.net_expr(topmod, f"s{map_steps.get(t, t)}", mem["smtpath"]) if bv: word_low = sig.memory_addr * width @@ -738,11 +750,21 @@ def print_msg(msg): smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice) constr_assumes[t].append((inywfile, smt_constr)) + max_t = t - if not got_topt: - if not check_witness: - skip_steps = max(skip_steps, t) - num_steps = max(num_steps, t+1) + return max_t + +if inywfile is not None: + if not got_topt: + skip_steps = 0 + num_steps = 0 + + max_t = ywfile_constraints(inywfile, constr_assumes) + + if not got_topt: + if not check_witness: + skip_steps = max(skip_steps, max_t) + num_steps = max(num_steps, max_t+1) if btorwitfile is not None: with open(btorwitfile, "r") as f: @@ -841,7 +863,7 @@ def print_msg(msg): skip_steps = step num_steps = step+1 -def collect_mem_trace_data(steps_start, steps_stop, vcd=None): +def collect_mem_trace_data(steps, vcd=None): mem_trace_data = dict() for mempath in sorted(smt.hiermems(topmod)): @@ -849,16 +871,16 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None): expr_id = list() expr_list = list() - for i in range(steps_start, steps_stop): + for seq, i in enumerate(steps): for j in range(rports): - expr_id.append(('R', i-steps_start, j, 'A')) - expr_id.append(('R', i-steps_start, j, 'D')) + expr_id.append(('R', seq, j, 'A')) + expr_id.append(('R', seq, j, 'D')) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dA" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "R%dD" % j)) for j in range(wports): - expr_id.append(('W', i-steps_start, j, 'A')) - expr_id.append(('W', i-steps_start, j, 'D')) - expr_id.append(('W', i-steps_start, j, 'M')) + expr_id.append(('W', seq, j, 'A')) + expr_id.append(('W', seq, j, 'D')) + expr_id.append(('W', seq, j, 'M')) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dA" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dD" % j)) expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, "W%dM" % j)) @@ -943,14 +965,14 @@ def collect_mem_trace_data(steps_start, steps_stop, vcd=None): netpath[-1] += "<%0*x>" % ((len(addr)+3) // 4, int_addr) vcd.add_net([topmod] + netpath, width) - for i in range(steps_start, steps_stop): + for seq, i in enumerate(steps): if i not in mem_trace_data: mem_trace_data[i] = list() - mem_trace_data[i].append((netpath, int_addr, "".join(tdata[i-steps_start]))) + mem_trace_data[i].append((netpath, int_addr, "".join(tdata[seq]))) return mem_trace_data -def write_vcd_trace(steps_start, steps_stop, index): +def write_vcd_trace(steps, index, seq_time=False): filename = vcdfile.replace("%", index) print_msg("Writing trace to VCD file: %s" % (filename)) @@ -971,10 +993,10 @@ def write_vcd_trace(steps_start, steps_stop, index): vcd.add_clock([topmod] + netpath, edge) path_list.append(netpath) - mem_trace_data = collect_mem_trace_data(steps_start, steps_stop, vcd) + mem_trace_data = collect_mem_trace_data(steps, vcd) - for i in range(steps_start, steps_stop): - vcd.set_time(i) + for seq, i in enumerate(steps): + vcd.set_time(seq if seq_time else i) value_list = smt.get_net_bin_list(topmod, path_list, "s%d" % i) for path, value in zip(path_list, value_list): vcd.set_net([topmod] + path, value) @@ -982,7 +1004,14 @@ def write_vcd_trace(steps_start, steps_stop, index): for path, addr, value in mem_trace_data[i]: vcd.set_net([topmod] + path, value) - vcd.set_time(steps_stop) + if seq_time: + end_time = len(steps) + elif steps: + end_time = steps[-1] + 1 + else: + end_time = 0 + + vcd.set_time(end_time) def detect_state_loop(steps_start, steps_stop): print_msg(f"Checking for loops in found induction counter example") @@ -1027,7 +1056,7 @@ def escape_identifier(identifier): -def write_vlogtb_trace(steps_start, steps_stop, index): +def write_vlogtb_trace(steps, index): filename = vlogtbfile.replace("%", index) print_msg("Writing trace to Verilog testbench: %s" % (filename)) @@ -1092,7 +1121,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print(" initial begin", file=f) regs = sorted(smt.hiernets(vlogtb_topmod, regs_only=True)) - regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps_start))) + regvals = smt.get_net_bin_list(vlogtb_topmod, regs, vlogtb_state.replace("@@step_idx@@", str(steps[0]))) print("`ifndef VERILATOR", file=f) print(" #1;", file=f) @@ -1107,7 +1136,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): anyconsts = sorted(smt.hieranyconsts(vlogtb_topmod)) for info in anyconsts: if info[3] is not None: - modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps_start)), info[0]) + modstate = smt.net_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(steps[0])), info[0]) value = smt.bv2bin(smt.get("(|%s| %s)" % (info[1], modstate))) print(" UUT.%s = %d'b%s;" % (".".join(escape_identifier(info[0] + [info[3]])), len(value), value), file=f); @@ -1117,7 +1146,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): addr_expr_list = list() data_expr_list = list() - for i in range(steps_start, steps_stop): + for i in steps: for j in range(rports): addr_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j)) data_expr_list.append(smt.mem_expr(vlogtb_topmod, vlogtb_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j)) @@ -1138,7 +1167,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print("", file=f) anyseqs = sorted(smt.hieranyseqs(vlogtb_topmod)) - for i in range(steps_start, steps_stop): + for i in steps: pi_names = [[name] for name, _ in primary_inputs if name not in clock_inputs] pi_values = smt.get_net_bin_list(vlogtb_topmod, pi_names, vlogtb_state.replace("@@step_idx@@", str(i))) @@ -1170,14 +1199,14 @@ def write_vlogtb_trace(steps_start, steps_stop, index): print(" end", file=f) print(" always @(posedge clock) begin", file=f) - print(" genclock <= cycle < %d;" % (steps_stop-1), file=f) + print(" genclock <= cycle < %d;" % (steps[-1]), file=f) print(" cycle <= cycle + 1;", file=f) print(" end", file=f) print("endmodule", file=f) -def write_constr_trace(steps_start, steps_stop, index): +def write_constr_trace(steps, index): filename = outconstr.replace("%", index) print_msg("Writing trace to constraints file: %s" % (filename)) @@ -1194,7 +1223,7 @@ def write_constr_trace(steps_start, steps_stop, index): constr_prefix = smtctop[1] + "." if smtcinit: - steps_start = steps_stop - 1 + steps = [steps[-1]] with open(filename, "w") as f: primary_inputs = list() @@ -1203,13 +1232,13 @@ def write_constr_trace(steps_start, steps_stop, index): width = smt.modinfo[constr_topmod].wsize[name] primary_inputs.append((name, width)) - if steps_start == 0 or smtcinit: + if steps[0] == 0 or smtcinit: print("initial", file=f) else: - print("state %d" % steps_start, file=f) + print("state %d" % steps[0], file=f) regnames = sorted(smt.hiernets(constr_topmod, regs_only=True)) - regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps_start))) + regvals = smt.get_net_list(constr_topmod, regnames, constr_state.replace("@@step_idx@@", str(steps[0]))) for name, val in zip(regnames, regvals): print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f) @@ -1220,7 +1249,7 @@ def write_constr_trace(steps_start, steps_stop, index): addr_expr_list = list() data_expr_list = list() - for i in range(steps_start, steps_stop): + for i in steps: for j in range(rports): addr_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dA" % j)) data_expr_list.append(smt.mem_expr(constr_topmod, constr_state.replace("@@step_idx@@", str(i)), mempath, "R%dD" % j)) @@ -1236,7 +1265,7 @@ def write_constr_trace(steps_start, steps_stop, index): for addr, data in addr_data.items(): print("assume (= (select [%s%s] %s) %s)" % (constr_prefix, ".".join(mempath), addr, data), file=f) - for k in range(steps_start, steps_stop): + for k in steps: if not smtcinit: print("", file=f) print("state %d" % k, file=f) @@ -1247,11 +1276,14 @@ def write_constr_trace(steps_start, steps_stop, index): for name, val in zip(pi_names, pi_values): print("assume (= [%s%s] %s)" % (constr_prefix, ".".join(name), val), file=f) -def write_yw_trace(steps_start, steps_stop, index, allregs=False): - filename = outywfile.replace("%", index) - print_msg("Writing trace to Yosys witness file: %s" % (filename)) +def write_yw_trace(steps, index, allregs=False, filename=None): + if filename is None: + if outywfile is None: + return + filename = outywfile.replace("%", index) + print_msg("Writing trace to Yosys witness file: %s" % (filename)) - mem_trace_data = collect_mem_trace_data(steps_start, steps_stop) + mem_trace_data = collect_mem_trace_data(steps) with open(filename, "w") as f: inits, seqs, clocks, mems = smt.hierwitness(topmod, allregs) @@ -1295,18 +1327,28 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False): sig = yw.add_sig(word_path, overlap_start, overlap_end - overlap_start, True) mem_init_values.append((sig, overlap_bits.replace("x", "?"))) - for k in range(steps_start, steps_stop): + exprs = [] + all_sigs = [] + + for i, k in enumerate(steps): step_values = WitnessValues() - if k == steps_start: + if not i: for sig, value in mem_init_values: step_values[sig] = value sigs = inits + seqs else: sigs = seqs + exprs.extend(smt.witness_net_expr(topmod, f"s{k}", sig) for sig in sigs) + + all_sigs.append(sigs) + + bvs = iter(smt.get_list(exprs)) + + for sigs in all_sigs: for sig in sigs: - value = smt.bv2bin(smt.get(smt.witness_net_expr(topmod, f"s{k}", sig))) + value = smt.bv2bin(next(bvs)) step_values[sig["sig"]] = value yw.step(step_values) @@ -1314,17 +1356,24 @@ def write_yw_trace(steps_start, steps_stop, index, allregs=False): def write_trace(steps_start, steps_stop, index, allregs=False): + if steps_stop is None: + steps = steps_start + seq_time = True + else: + steps = list(range(steps_start, steps_stop)) + seq_time = False + if vcdfile is not None: - write_vcd_trace(steps_start, steps_stop, index) + write_vcd_trace(steps, index, seq_time=seq_time) if vlogtbfile is not None: - write_vlogtb_trace(steps_start, steps_stop, index) + write_vlogtb_trace(steps, index) if outconstr is not None: - write_constr_trace(steps_start, steps_stop, index) + write_constr_trace(steps, index) if outywfile is not None: - write_yw_trace(steps_start, steps_stop, index, allregs) + write_yw_trace(steps, index, allregs) def print_failed_asserts_worker(mod, state, path, extrainfo, infomap, infokey=()): @@ -1596,7 +1645,11 @@ def smt_check_sat(expected=["sat", "unsat"]): smt_forall_assert() return smt.check_sat(expected=expected) -if tempind: + +if incremental: + incremental.mainloop() + +elif tempind: retstatus = "FAILED" skip_counter = step_size for step in range(num_steps, -1, -1): @@ -1954,5 +2007,6 @@ def smt_check_sat(expected=["sat", "unsat"]): smt.write("(exit)") smt.wait() -print_msg("Status: %s" % retstatus) -sys.exit(0 if retstatus == "PASSED" else 1) +if not incremental: + print_msg("Status: %s" % retstatus) + sys.exit(0 if retstatus == "PASSED" else 1) diff --git a/yosys/backends/smt2/smtbmc_incremental.py b/yosys/backends/smt2/smtbmc_incremental.py new file mode 100644 index 00000000000..1a2a4570312 --- /dev/null +++ b/yosys/backends/smt2/smtbmc_incremental.py @@ -0,0 +1,426 @@ +from collections import defaultdict +import json +import typing +from functools import partial + +if typing.TYPE_CHECKING: + import smtbmc +else: + import sys + + smtbmc = sys.modules["__main__"] + + +class InteractiveError(Exception): + pass + + +class Incremental: + def __init__(self): + self.traceidx = 0 + + self.state_set = set() + self.map_cache = {} + + self._cached_hierwitness = {} + self._witness_index = None + + self._yw_constraints = {} + + def setup(self): + generic_assert_map = smtbmc.get_assert_map( + smtbmc.topmod, "state", smtbmc.topmod + ) + self.inv_generic_assert_map = { + tuple(data[1:]): key for key, data in generic_assert_map.items() + } + assert len(self.inv_generic_assert_map) == len(generic_assert_map) + + def print_json(self, **kwargs): + print(json.dumps(kwargs), flush=True) + + def print_msg(self, msg): + self.print_json(msg=msg) + + def get_cached_assert(self, step, name): + try: + assert_map = self.map_cache[step] + except KeyError: + assert_map = self.map_cache[step] = smtbmc.get_assert_map( + smtbmc.topmod, f"s{step}", smtbmc.topmod + ) + return assert_map[self.inv_generic_assert_map[name]][0] + + def arg_step(self, cmd, declare=False, name="step", optional=False): + step = cmd.get(name, None) + if step is None and optional: + return None + if not isinstance(step, int): + if optional: + raise InteractiveError(f"{name} must be an integer") + else: + raise InteractiveError(f"integer {name} argument required") + if declare and step in self.state_set: + raise InteractiveError(f"step {step} already declared") + if not declare and step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + return step + + def expr_arg_len(self, expr, min_len, max_len=-1): + if max_len == -1: + max_len = min_len + arg_len = len(expr) - 1 + + if min_len is not None and arg_len < min_len: + if min_len == max_len: + raise ( + f"{json.dumps(expr[0])} expression must have " + f"{min_len} argument{'s' if min_len != 1 else ''}" + ) + else: + raise ( + f"{json.dumps(expr[0])} expression must have at least " + f"{min_len} argument{'s' if min_len != 1 else ''}" + ) + if max_len is not None and arg_len > max_len: + raise ( + f"{json.dumps(expr[0])} expression can have at most " + f"{min_len} argument{'s' if max_len != 1 else ''}" + ) + + def expr_step(self, expr, smt_out): + self.expr_arg_len(expr, 1) + step = expr[1] + if step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + smt_out.append(f"s{step}") + return "module", smtbmc.topmod + + def expr_mod_constraint(self, expr, smt_out): + self.expr_arg_len(expr, 1) + position = len(smt_out) + smt_out.append(None) + arg_sort = self.expr(expr[1], smt_out, required_sort=["module", None]) + module = arg_sort[1] + suffix = expr[0][3:] + smt_out[position] = f"(|{module}{suffix}| " + smt_out.append(")") + return "Bool" + + def expr_mod_constraint2(self, expr, smt_out): + self.expr_arg_len(expr, 2) + + position = len(smt_out) + smt_out.append(None) + arg_sort = self.expr(expr[1], smt_out, required_sort=["module", None]) + smt_out.append(" ") + self.expr(expr[2], smt_out, required_sort=arg_sort) + module = arg_sort[1] + suffix = expr[0][3:] + smt_out[position] = f"(|{module}{suffix}| " + smt_out.append(")") + return "Bool" + + def expr_not(self, expr, smt_out): + self.expr_arg_len(expr, 1) + + smt_out.append("(not ") + self.expr(expr[1], smt_out, required_sort="Bool") + smt_out.append(")") + return "Bool" + + def expr_eq(self, expr, smt_out): + self.expr_arg_len(expr, 2) + + smt_out.append("(= ") + arg_sort = self.expr(expr[1], smt_out) + if ( + smtbmc.smt.unroll + and isinstance(arg_sort, (list, tuple)) + and arg_sort[0] == "module" + ): + raise InteractiveError("state equality not supported in unroll mode") + + smt_out.append(" ") + self.expr(expr[2], smt_out, required_sort=arg_sort) + smt_out.append(")") + return "Bool" + + def expr_andor(self, expr, smt_out): + if len(expr) == 1: + smt_out.push({"and": "true", "or": "false"}[expr[0]]) + elif len(expr) == 2: + arg_sort = self.expr(expr[1], smt_out) + if arg_sort != "Bool": + raise InteractiveError( + f"arguments of {json.dumps(expr[0])} must have sort Bool" + ) + else: + sep = f"({expr[0]} " + for arg in expr[1:]: + smt_out.append(sep) + sep = " " + self.expr(arg, smt_out, required_sort="Bool") + smt_out.append(")") + return "Bool" + + def expr_yw(self, expr, smt_out): + if len(expr) == 2: + name = None + step = expr[1] + elif len(expr) == 3: + name = expr[1] + step = expr[2] + + if step not in self.state_set: + raise InteractiveError(f"step {step} not declared") + + if name not in self._yw_constraints: + raise InteractiveError(f"no yw file loaded as name {name!r}") + + constraints = self._yw_constraints[name].get(step, []) + + if len(constraints) == 0: + smt_out.append("true") + elif len(constraints) == 1: + smt_out.append(constraints[0]) + else: + sep = "(and " + for constraint in constraints: + smt_out.append(sep) + sep = " " + smt_out.append(constraint) + smt_out.append(")") + + return "Bool" + + def expr_smtlib(self, expr, smt_out): + self.expr_arg_len(expr, 2) + + smtlib_expr = expr[1] + sort = expr[2] + + if not isinstance(smtlib_expr, str): + raise InteractiveError( + "raw SMT-LIB expression has to be a string, " + f"got {json.dumps(smtlib_expr)}" + ) + + if not isinstance(sort, str): + raise InteractiveError( + f"raw SMT-LIB sort has to be a string, got {json.dumps(sort)}" + ) + + smt_out.append(smtlib_expr) + return sort + + def expr_label(self, expr, smt_out): + if len(expr) != 3: + raise InteractiveError( + f'expected ["!", label, sub_expr], got {json.dumps(expr)}' + ) + label = expr[1] + subexpr = expr[2] + + if not isinstance(label, str): + raise InteractiveError(f"expression label has to be a string") + + smt_out.append("(! ") + smt_out.appedd(label) + smt_out.append(" ") + + sort = self.expr(subexpr, smt_out) + + smt_out.append(")") + + return sort + + expr_handlers = { + "step": expr_step, + "mod_h": expr_mod_constraint, + "mod_is": expr_mod_constraint, + "mod_i": expr_mod_constraint, + "mod_a": expr_mod_constraint, + "mod_u": expr_mod_constraint, + "mod_t": expr_mod_constraint2, + "not": expr_not, + "and": expr_andor, + "or": expr_andor, + "=": expr_eq, + "yw": expr_yw, + "smtlib": expr_smtlib, + "!": expr_label, + } + + def expr(self, expr, smt_out, required_sort=None): + if not isinstance(expr, (list, tuple)) or not expr: + raise InteractiveError( + f"expression must be a non-empty JSON array, found: {json.dumps(expr)}" + ) + name = expr[0] + + handler = self.expr_handlers.get(name) + if handler: + sort = handler(self, expr, smt_out) + + if required_sort is not None: + if isinstance(required_sort, (list, tuple)): + if ( + not isinstance(sort, (list, tuple)) + or len(sort) != len(required_sort) + or any( + r is not None and r != s + for r, s in zip(required_sort, sort) + ) + ): + raise InteractiveError( + f"required sort {json.dumps(required_sort)} " + f"found sort {json.dumps(sort)}" + ) + return sort + raise InteractiveError(f"unknown expression {json.dumps(expr[0])}") + + def expr_smt(self, expr, required_sort): + smt_out = [] + self.expr(expr, smt_out, required_sort=required_sort) + out = "".join(smt_out) + return out + + def cmd_new_step(self, cmd): + step = self.arg_step(cmd, declare=True) + self.state_set.add(step) + smtbmc.smt_state(step) + + def cmd_assert(self, cmd): + name = cmd.get("cmd") + + assert_fn = { + "assert_antecedent": smtbmc.smt_assert_antecedent, + "assert_consequent": smtbmc.smt_assert_consequent, + "assert": smtbmc.smt_assert, + }[name] + + assert_fn(self.expr_smt(cmd.get("expr"), "Bool")) + + def cmd_push(self, cmd): + smtbmc.smt_push() + + def cmd_pop(self, cmd): + smtbmc.smt_pop() + + def cmd_check(self, cmd): + return smtbmc.smt_check_sat() + + def cmd_smtlib(self, cmd): + command = cmd.get("command") + if not isinstance(command, str): + raise InteractiveError( + f"raw SMT-LIB command must be a string, found {json.dumps(command)}" + ) + smtbmc.smt.write(command) + + def cmd_design_hierwitness(self, cmd=None): + allregs = (cmd is None) or bool(cmd.get("allreges", False)) + if self._cached_hierwitness[allregs] is not None: + return self._cached_hierwitness[allregs] + inits, seqs, clocks, mems = smtbmc.smt.hierwitness(smtbmc.topmod, allregs) + self._cached_hierwitness[allregs] = result = dict( + inits=inits, seqs=seqs, clocks=clocks, mems=mems + ) + return result + + def cmd_write_yw_trace(self, cmd): + steps = cmd.get("steps") + allregs = bool(cmd.get("allregs", False)) + + if steps is None: + steps = sorted(self.state_set) + + path = cmd.get("path") + + smtbmc.write_yw_trace(steps, self.traceidx, allregs=allregs, filename=path) + + if path is None: + self.traceidx += 1 + + def cmd_read_yw_trace(self, cmd): + steps = cmd.get("steps") + path = cmd.get("path") + name = cmd.get("name") + skip_x = cmd.get("skip_x", False) + if path is None: + raise InteractiveError("path required") + + constraints = defaultdict(list) + + if steps is None: + steps = sorted(self.state_set) + + map_steps = {i: int(j) for i, j in enumerate(steps)} + + last_step = smtbmc.ywfile_constraints( + path, constraints, map_steps=map_steps, skip_x=skip_x + ) + + self._yw_constraints[name] = { + map_steps.get(i, i): [smtexpr for cexfile, smtexpr in constraint_list] + for i, constraint_list in constraints.items() + } + + return dict(last_step=last_step) + + def cmd_ping(self, cmd): + return cmd + + cmd_handlers = { + "new_step": cmd_new_step, + "assert": cmd_assert, + "assert_antecedent": cmd_assert, + "assert_consequent": cmd_assert, + "push": cmd_push, + "pop": cmd_pop, + "check": cmd_check, + "smtlib": cmd_smtlib, + "design_hierwitness": cmd_design_hierwitness, + "write_yw_trace": cmd_write_yw_trace, + "read_yw_trace": cmd_read_yw_trace, + "ping": cmd_ping, + } + + def handle_command(self, cmd): + if not isinstance(cmd, dict) or "cmd" not in cmd: + raise InteractiveError('object with "cmd" key required') + + name = cmd.get("cmd", None) + + handler = self.cmd_handlers.get(name) + if handler: + return handler(self, cmd) + else: + raise InteractiveError(f"unknown command: {name}") + + def mainloop(self): + self.setup() + while True: + try: + cmd = input().strip() + if not cmd or cmd.startswith("#") or cmd.startswith("//"): + continue + try: + cmd = json.loads(cmd) + except json.decoder.JSONDecodeError as e: + self.print_json(err=f"invalid JSON: {e}") + continue + except EOFError: + break + + try: + result = self.handle_command(cmd) + except InteractiveError as e: + self.print_json(err=str(e)) + continue + except Exception as e: + self.print_json(err=f"internal error: {e}") + raise + else: + self.print_json(ok=result) diff --git a/yosys/backends/smt2/test_cells.sh b/yosys/backends/smt2/test_cells.sh index 34adb7af3c1..3f84d65a21a 100644 --- a/yosys/backends/smt2/test_cells.sh +++ b/yosys/backends/smt2/test_cells.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex diff --git a/yosys/backends/smt2/witness.py b/yosys/backends/smt2/witness.py index 7d5a2469eb5..b7e25851cbb 100644 --- a/yosys/backends/smt2/witness.py +++ b/yosys/backends/smt2/witness.py @@ -33,10 +33,14 @@ def cli(): Display a Yosys witness trace in a human readable format. """) @click.argument("input", type=click.File("r")) -def display(input): +@click.option("--skip-x", help="Treat x bits as unassigned.", is_flag=True) +def display(input, skip_x): click.echo(f"Reading Yosys witness trace {input.name!r}...") inyw = ReadWitness(input) + if skip_x: + inyw.skip_x() + def output(): yield click.style("*** RTLIL bit-order below may differ from source level declarations ***", fg="red") @@ -84,26 +88,69 @@ def stats(input): Transform a Yosys witness trace. Currently no transformations are implemented, so it is only useful for testing. +If two or more inputs are provided they will be concatenated together into the output. """) -@click.argument("input", type=click.File("r")) +@click.argument("inputs", type=click.File("r"), nargs=-1) @click.argument("output", type=click.File("w")) -def yw2yw(input, output): - click.echo(f"Copying yosys witness trace from {input.name!r} to {output.name!r}...") - inyw = ReadWitness(input) +@click.option("--append", "-p", type=int, multiple=True, + help="Number of steps (+ve or -ve) to append to end of input trace. " + +"Can be defined multiple times, following the same order as input traces. ") +@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True) +def yw2yw(inputs, output, append, skip_x): + if len(inputs) == 0: + raise click.ClickException(f"no inputs specified") + outyw = WriteWitness(output, "yosys-witness yw2yw") + join_inputs = len(inputs) > 1 + inyws = {} + + if not append: + # default to 0 + append = [0] * len(inputs) + if len(append) != len(inputs): + print(f"Mismatch in number of --append values ({len(append)}) and input traces ({len(inputs)}).") + sys.exit(1) + + for (input, p) in zip(inputs, append): + if (join_inputs): + click.echo(f"Loading signals from yosys witness trace {input.name!r}...") + inyw = ReadWitness(input) + if p: + click.echo(f" appending {p} steps") + if (p + len(inyw) <= 0): + click.echo(f" skipping {input.name!r} (only {len(inyw)} steps to skip)") + continue + inyw.append_steps(p) + inyws[input] = inyw + for clock in inyw.clocks: + if clock not in outyw.clocks: + outyw.add_clock(clock["path"], clock["offset"], clock["edge"]) - for clock in inyw.clocks: - outyw.add_clock(clock["path"], clock["offset"], clock["edge"]) + for sig in inyw.signals: + if sig not in outyw.signals: + outyw.add_sig(sig.path, sig.offset, sig.width, sig.init_only) - for sig in inyw.signals: - outyw.add_sig(sig.path, sig.offset, sig.width, sig.init_only) + init_values = sum([inyw.init_step() for inyw in inyws.values()], start=WitnessValues()) - for t, values in inyw.steps(): - outyw.step(values) + first_witness = True + for (input, inyw) in inyws.items(): + click.echo(f"Copying yosys witness trace from {input.name!r} to {output.name!r}...") + + if first_witness: + outyw.step(init_values, skip_x=skip_x) + else: + outyw.step(inyw.first_step(), skip_x=skip_x) + + for t, values in inyw.steps(1): + outyw.step(values, skip_x=skip_x) + + click.echo(f" copied {t + 1} time steps.") + first_witness = False outyw.end_trace() - click.echo(f"Copied {outyw.t + 1} time steps.") + if join_inputs: + click.echo(f"Copied {outyw.t} total time steps.") class AigerMap: @@ -135,7 +182,9 @@ def __init__(self, mapfile): @click.argument("input", type=click.File("r")) @click.argument("mapfile", type=click.File("r")) @click.argument("output", type=click.File("w")) -def aiw2yw(input, mapfile, output): +@click.option("--skip-x", help="Leave input x bits unassigned.", is_flag=True) +@click.option("--present-only", help="Only include bits present in at least one time step.", is_flag=True) +def aiw2yw(input, mapfile, output, skip_x, present_only): input_name = input.name click.echo(f"Converting AIGER witness trace {input_name!r} to Yosys witness trace {output.name!r}...") click.echo(f"Using Yosys witness AIGER map file {mapfile.name!r}") @@ -163,16 +212,23 @@ def aiw2yw(input, mapfile, output): if not re.match(r'[0]*$', ffline): raise click.ClickException(f"{input_name}: non-default initial state not supported") - outyw = WriteWitness(output, 'yosys-witness aiw2yw') + if not present_only: + outyw = WriteWitness(output, "yosys-witness aiw2yw") - for clock in aiger_map.clocks: - outyw.add_clock(clock["path"], clock["offset"], clock["edge"]) + for clock in aiger_map.clocks: + outyw.add_clock(clock["path"], clock["offset"], clock["edge"]) - for (path, offset), id in aiger_map.sigmap.bit_to_id.items(): - outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs) + for (path, offset), id in aiger_map.sigmap.bit_to_id.items(): + outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs) missing = set() + seen = set() + + buffered_steps = [] + + skip = "x?" if skip_x else "?" + t = -1 while True: inline = next(input, None) if inline is None: @@ -184,17 +240,20 @@ def aiw2yw(input, mapfile, output): if inline.startswith("#"): continue - if not re.match(r'[01x]*$', ffline): + t += 1 + + if not re.match(r"[01x]*$", inline): raise click.ClickException(f"{input_name}: unexpected data in AIGER witness file") if len(inline) != aiger_map.input_count: raise click.ClickException( - f"{input_name}: {mapfile.name}: number of inputs does not match, " - f"{len(inline)} in witness, {aiger_map.input_count} in map file") + f"{input_name}: {mapfile.name}: number of inputs does not match, " + f"{len(inline)} in witness, {aiger_map.input_count} in map file" + ) values = WitnessValues() for i, v in enumerate(inline): - if outyw.t > 0 and i in aiger_map.init_inputs: + if v in skip or (t > 0 and i in aiger_map.init_inputs): continue try: @@ -202,11 +261,29 @@ def aiw2yw(input, mapfile, output): except IndexError: bit = None if bit is None: - missing.insert(i) + missing.add(i) + elif present_only: + seen.add(i) values[bit] = v - outyw.step(values) + if present_only: + buffered_steps.append(values) + else: + outyw.step(values) + + if present_only: + outyw = WriteWitness(output, "yosys-witness aiw2yw") + + for clock in aiger_map.clocks: + outyw.add_clock(clock["path"], clock["offset"], clock["edge"]) + + for (path, offset), id in aiger_map.sigmap.bit_to_id.items(): + if id in seen: + outyw.add_sig(path, offset, init_only=id in aiger_map.init_inputs) + + for values in buffered_steps: + outyw.step(values) outyw.end_trace() diff --git a/yosys/backends/smt2/ywio.py b/yosys/backends/smt2/ywio.py index 39cfac41e25..023a2d351b3 100644 --- a/yosys/backends/smt2/ywio.py +++ b/yosys/backends/smt2/ywio.py @@ -165,8 +165,8 @@ def pretty(self): else: return f"{pretty_path(self.path)}[{self.offset}]" - def __eq__(self): - return self.sort_key + def __eq__(self, other): + return self.sort_key == other.sort_key def __hash__(self): return hash(self.sort_key) @@ -294,6 +294,16 @@ def present_signals(self, sigmap): return sorted(signals), missing_signals + def __add__(self, other: "WitnessValues"): + new = WitnessValues() + new += self + new += other + return new + + def __iadd__(self, other: "WitnessValues"): + for key, value in other.values.items(): + self.values.setdefault(key, value) + return self class WriteWitness: def __init__(self, f, generator): @@ -341,11 +351,14 @@ def write_header(self): self.out.name("steps") self.out.begin_array() - def step(self, values): + def step(self, values, skip_x=False): if not self.header_written: self.write_header() - self.out.value({"bits": values.pack(self.sigmap)}) + packed = values.pack(self.sigmap) + if skip_x: + packed = packed.replace('x', '?') + self.out.value({"bits": packed}) self.t += 1 @@ -380,14 +393,40 @@ def __init__(self, f): self.bits = [step["bits"] for step in data["steps"]] + def skip_x(self): + self.bits = [step.replace('x', '?') for step in self.bits] + + def init_step(self): + return self.step(0) + + def non_init_bits(self): + if len(self) > 1: + return len(self.bits[1]) + else: + return sum([sig.width for sig in self.signals if not sig.init_only]) + + def first_step(self): + values = WitnessValues() + # may have issues when non_init_bits is 0 + values.unpack(WitnessSigMap([sig for sig in self.signals if not sig.init_only]), self.bits[0][-self.non_init_bits():]) + return values + def step(self, t): values = WitnessValues() values.unpack(self.sigmap, self.bits[t]) return values - def steps(self): - for i in range(len(self.bits)): + def steps(self, start=0): + for i in range(start, len(self.bits)): yield i, self.step(i) + def append_steps(self, t): + if not t: + pass + elif t < 0: + self.bits = self.bits[:t] + else: + self.bits.extend(["0"*self.non_init_bits()]*t) + def __len__(self): return len(self.bits) diff --git a/yosys/backends/smv/test_cells.sh b/yosys/backends/smv/test_cells.sh index 145b9c33b92..1347b70446b 100644 --- a/yosys/backends/smv/test_cells.sh +++ b/yosys/backends/smv/test_cells.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex diff --git a/yosys/backends/verilog/verilog_backend.cc b/yosys/backends/verilog/verilog_backend.cc index 5ff191a9c16..988eef6588f 100644 --- a/yosys/backends/verilog/verilog_backend.cc +++ b/yosys/backends/verilog/verilog_backend.cc @@ -27,6 +27,7 @@ #include "kernel/sigtools.h" #include "kernel/ff.h" #include "kernel/mem.h" +#include "kernel/fmt.h" #include #include #include @@ -375,7 +376,7 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) } } -void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool regattr = false, bool as_comment = false) +void dump_attributes(std::ostream &f, std::string indent, dict &attributes, std::string term = "\n", bool modattr = false, bool regattr = false, bool as_comment = false) { if (noattr) return; @@ -391,13 +392,13 @@ void dump_attributes(std::ostream &f, std::string indent, dictsecond, -1, 0, false, as_comment); - f << stringf(" %s%c", as_comment ? "*/" : "*)", term); + f << stringf(" %s%s", as_comment ? "*/" : "*)", term.c_str()); } } void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) { - dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); + dump_attributes(f, indent, wire->attributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); #if 0 if (wire->port_input && !wire->port_output) f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); @@ -988,7 +989,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = %s ", op.c_str()); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", true); f << stringf(";\n"); } @@ -1000,11 +1001,63 @@ void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell f << stringf(" = "); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %s ", op.c_str()); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", true); f << stringf(";\n"); } +void dump_cell_expr_print(std::ostream &f, std::string indent, const RTLIL::Cell *cell) +{ + Fmt fmt; + fmt.parse_rtlil(cell); + std::vector args = fmt.emit_verilog(); + + f << stringf("%s" "$write(", indent.c_str()); + bool first = true; + for (auto &arg : args) { + if (first) { + first = false; + } else { + f << ", "; + } + switch (arg.type) { + case VerilogFmtArg::STRING: + dump_const(f, RTLIL::Const(arg.str)); + break; + case VerilogFmtArg::INTEGER: + f << (arg.signed_ ? "$signed(" : "$unsigned("); + dump_sigspec(f, arg.sig); + f << ")"; + break; + case VerilogFmtArg::TIME: + if (arg.realtime) + f << "$realtime"; + else + f << "$time"; + break; + default: log_abort(); + } + } + f << stringf(");\n"); +} + +void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell *cell) +{ + std::string flavor = cell->getParam(ID(FLAVOR)).decode_string(); + if (flavor == "assert") + f << stringf("%s" "assert (", indent.c_str()); + else if (flavor == "assume") + f << stringf("%s" "assume (", indent.c_str()); + else if (flavor == "live") + f << stringf("%s" "assert (eventually ", indent.c_str()); + else if (flavor == "fair") + f << stringf("%s" "assume (eventually ", indent.c_str()); + else if (flavor == "cover") + f << stringf("%s" "cover (", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(");\n"); +} + bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) { if (cell->type == ID($_NOT_)) { @@ -1012,7 +1065,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); f << stringf("~"); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); + dump_cell_expr_port(f, cell, "A", false); + f << stringf(";\n"); + return true; + } + + if (cell->type == ID($_BUF_)) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::Y)); + f << stringf(" = "); dump_cell_expr_port(f, cell, "A", false); f << stringf(";\n"); return true; @@ -1032,7 +1094,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("|"); if (cell->type.in(ID($_XOR_), ID($_XNOR_))) f << stringf("^"); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); f << stringf(" "); if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) f << stringf("~("); @@ -1049,7 +1111,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = "); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", false); f << stringf(" : "); dump_cell_expr_port(f, cell, "A", false); @@ -1063,7 +1125,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = !("); dump_cell_expr_port(f, cell, "S", false); f << stringf(" ? "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", false); f << stringf(" : "); dump_cell_expr_port(f, cell, "A", false); @@ -1079,7 +1141,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(cell->type == ID($_AOI3_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &"); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); f << stringf(" "); dump_cell_expr_port(f, cell, "C", false); f << stringf(");\n"); @@ -1094,7 +1156,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); dump_cell_expr_port(f, cell, "B", false); f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &"); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); f << stringf(" ("); dump_cell_expr_port(f, cell, "C", false); f << stringf(cell->type == ID($_AOI4_) ? " & " : " | "); @@ -1196,7 +1258,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = $signed(%s) / ", buf_num.c_str()); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); f << stringf("$signed(%s);\n", buf_b.c_str()); return true; } else { @@ -1219,7 +1281,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); dump_cell_expr_port(f, cell, "A", true); f << stringf(" %% "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "B", true); f << stringf(";\n"); @@ -1294,7 +1356,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = "); dump_sigspec(f, cell->getPort(ID::S)); f << stringf(" ? "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); dump_sigspec(f, cell->getPort(ID::A)); @@ -1403,7 +1465,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = "); dump_const(f, cell->parameters.at(ID::LUT)); f << stringf(" >> "); - dump_attributes(f, "", cell->attributes, ' '); + dump_attributes(f, "", cell->attributes, " "); dump_sigspec(f, cell->getPort(ID::A)); f << stringf(";\n"); return true; @@ -1753,6 +1815,55 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == ID($print)) + { + // Sync $print cells are accumulated and handled in dump_module. + if (cell->getParam(ID::TRG_ENABLE).as_bool()) + return true; + + f << stringf("%s" "always @*\n", indent.c_str()); + + f << stringf("%s" " if (", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::EN)); + f << stringf(")\n"); + + dump_cell_expr_print(f, indent + " ", cell); + return true; + } + + if (cell->type == ID($check)) + { + // Sync $check cells are accumulated and handled in dump_module. + if (cell->getParam(ID::TRG_ENABLE).as_bool()) + return true; + + f << stringf("%s" "always @*\n", indent.c_str()); + + f << stringf("%s" " if (", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::EN)); + f << stringf(") begin\n"); + + std::string flavor = cell->getParam(ID::FLAVOR).decode_string(); + if (flavor == "assert" || flavor == "assume") { + Fmt fmt; + fmt.parse_rtlil(cell); + if (!fmt.parts.empty()) { + f << stringf("%s" " if (!", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(")\n"); + dump_cell_expr_print(f, indent + " ", cell); + } + } else { + f << stringf("%s" " /* message omitted */\n", indent.c_str()); + } + + dump_cell_expr_check(f, indent + " ", cell); + + f << stringf("%s" " end\n", indent.c_str()); + + return true; + } + // FIXME: $fsm return false; @@ -1778,7 +1889,8 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) if (it != cell->parameters.begin()) f << stringf(","); f << stringf("\n%s .%s(", indent.c_str(), id(it->first).c_str()); - dump_const(f, it->second); + if (it->second.size() > 0) + dump_const(f, it->second); f << stringf(")"); } f << stringf("\n%s" ")", indent.c_str()); @@ -1841,6 +1953,58 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) } } +void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec &trg, const RTLIL::Const &polarity, std::vector &cells) +{ + if (trg.size() == 0) { + f << stringf("%s" "initial begin\n", indent.c_str()); + } else { + f << stringf("%s" "always @(", indent.c_str()); + for (int i = 0; i < trg.size(); i++) { + if (i != 0) + f << " or "; + if (polarity[i]) + f << "posedge "; + else + f << "negedge "; + dump_sigspec(f, trg[i]); + } + f << ") begin\n"; + } + + std::sort(cells.begin(), cells.end(), [](const RTLIL::Cell *a, const RTLIL::Cell *b) { + return a->getParam(ID::PRIORITY).as_int() > b->getParam(ID::PRIORITY).as_int(); + }); + for (auto cell : cells) { + f << stringf("%s" " if (", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::EN)); + f << stringf(") begin\n"); + + if (cell->type == ID($print)) { + dump_cell_expr_print(f, indent + " ", cell); + } else if (cell->type == ID($check)) { + std::string flavor = cell->getParam(ID::FLAVOR).decode_string(); + if (flavor == "assert" || flavor == "assume") { + Fmt fmt; + fmt.parse_rtlil(cell); + if (!fmt.parts.empty()) { + f << stringf("%s" " if (!", indent.c_str()); + dump_sigspec(f, cell->getPort(ID::A)); + f << stringf(")\n"); + dump_cell_expr_print(f, indent + " ", cell); + } + } else { + f << stringf("%s" " /* message omitted */\n", indent.c_str()); + } + + dump_cell_expr_check(f, indent + " ", cell); + } + + f << stringf("%s" " end\n", indent.c_str()); + } + + f << stringf("%s" "end\n", indent.c_str()); +} + void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) { if (simple_lhs) { @@ -1864,13 +2028,8 @@ void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw); -void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false) +void dump_case_actions(std::ostream &f, std::string indent, RTLIL::CaseRule *cs) { - int number_of_stmts = cs->switches.size() + cs->actions.size(); - - if (!omit_trailing_begin && number_of_stmts >= 2) - f << stringf("%s" "begin\n", indent.c_str()); - for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) { if (it->first.size() == 0) continue; @@ -1880,7 +2039,64 @@ void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bo dump_sigspec(f, it->second); f << stringf(";\n"); } +} + +bool dump_proc_switch_ifelse(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw) +{ + for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { + if ((*it)->compare.size() == 0) { + break; + } else if ((*it)->compare.size() == 1) { + int case_index = it - sw->cases.begin(); + SigSpec compare = (*it)->compare.at(0); + if (case_index >= compare.size()) + return false; + if (compare[case_index] != State::S1) + return false; + for (int bit_index = 0; bit_index < compare.size(); bit_index++) + if (bit_index != case_index && compare[bit_index] != State::Sa) + return false; + } else { + return false; + } + } + + dump_attributes(f, indent, sw->attributes); + f << indent; + auto sig_it = sw->signal.begin(); + for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it, ++sig_it) { + if (it != sw->cases.begin()) { + if ((*it)->compare.empty()) + f << " else begin\n"; + else + f << " else "; + } + if (!(*it)->compare.empty()) { + f << stringf("if ("); + dump_sigspec(f, *sig_it); + f << stringf(") begin\n"); + } + + dump_case_actions(f, indent, (*it)); + for (auto it2 = (*it)->switches.begin(); it2 != (*it)->switches.end(); ++it2) + dump_proc_switch(f, indent + " ", *it2); + + f << indent << "end"; + if ((*it)->compare.empty()) + break; + } + f << "\n"; + return true; +} +void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bool omit_trailing_begin = false) +{ + int number_of_stmts = cs->switches.size() + cs->actions.size(); + + if (!omit_trailing_begin && number_of_stmts >= 2) + f << stringf("%s" "begin\n", indent.c_str()); + + dump_case_actions(f, indent, cs); for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it) dump_proc_switch(f, indent + " ", *it); @@ -1903,17 +2119,18 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw return; } + if (dump_proc_switch_ifelse(f, indent, sw)) + return; + dump_attributes(f, indent, sw->attributes); f << stringf("%s" "casez (", indent.c_str()); dump_sigspec(f, sw->signal); f << stringf(")\n"); - bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { - dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); + bool got_default = false; + dump_attributes(f, indent + " ", (*it)->attributes, "\n", /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { - if (got_default) - continue; f << stringf("%s default", indent.c_str()); got_default = true; } else { @@ -1926,6 +2143,19 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw } f << stringf(":\n"); dump_case_body(f, indent + " ", *it); + + if (got_default) { + // If we followed up the default with more cases the Verilog + // semantics would be to match those *before* the default, but + // the RTLIL semantics are to match those *after* the default + // (so they can never be selected). Exit now. + break; + } + } + + if (sw->cases.empty()) { + // Verilog does not allow empty cases. + f << stringf("%s default: ;\n", indent.c_str()); } f << stringf("%s" "endcase\n", indent.c_str()); @@ -2022,6 +2252,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) { + std::map, std::vector> sync_effect_cells; + reg_wires.clear(); reset_auto_counter(module); active_module = module; @@ -2052,6 +2284,11 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) std::set> reg_bits; for (auto cell : module->cells()) { + if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) { + sync_effect_cells[make_pair(cell->getPort(ID::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell); + continue; + } + if (!RTLIL::builtin_ff_cell_types().count(cell->type) || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_))) continue; @@ -2075,7 +2312,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } } - dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); + dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; int cnt = 0; @@ -2107,6 +2344,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) for (auto cell : module->cells()) dump_cell(f, indent + " ", cell); + for (auto &it : sync_effect_cells) + dump_sync_effect(f, indent + " ", it.first.first, it.first.second, it.second); + for (auto it = module->processes.begin(); it != module->processes.end(); ++it) dump_process(f, indent + " ", it->second); diff --git a/yosys/docs/source/CHAPTER_CellLib.rst b/yosys/docs/source/CHAPTER_CellLib.rst index c8904086879..3b6f1b4d387 100644 --- a/yosys/docs/source/CHAPTER_CellLib.rst +++ b/yosys/docs/source/CHAPTER_CellLib.rst @@ -120,7 +120,7 @@ All binary RTL cells have two input ports ``\A`` and ``\B`` and one output port :verilog:`Y = A >>> B` $sshr :verilog:`Y = A - B` $sub :verilog:`Y = A && B` $logic_and :verilog:`Y = A * B` $mul :verilog:`Y = A || B` $logic_or :verilog:`Y = A / B` $div - :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod + :verilog:`Y = A === B` $eqx :verilog:`Y = A % B` $mod :verilog:`Y = A !== B` $nex ``N/A`` $divfloor :verilog:`Y = A ** B` $pow ``N/A`` $modfoor ======================= ============= ======================= ========= @@ -621,12 +621,141 @@ Add information about ``$specify2``, ``$specify3``, and ``$specrule`` cells. Formal verification cells ~~~~~~~~~~~~~~~~~~~~~~~~~ -Add information about ``$assert``, ``$assume``, ``$live``, ``$fair``, +Add information about ``$check``, ``$assert``, ``$assume``, ``$live``, ``$fair``, ``$cover``, ``$equiv``, ``$initstate``, ``$anyconst``, ``$anyseq``, ``$anyinit``, ``$allconst``, ``$allseq`` cells. Add information about ``$ff`` and ``$_FF_`` cells. +Debugging cells +~~~~~~~~~~~~~~~ + +The ``$print`` cell is used to log the values of signals, akin to (and +translatable to) the ``$display`` and ``$write`` family of tasks in Verilog. It +has the following parameters: + +``\FORMAT`` + The internal format string. The syntax is described below. + +``\ARGS_WIDTH`` + The width (in bits) of the signal on the ``\ARGS`` port. + +``\TRG_ENABLE`` + True if triggered on specific signals defined in ``\TRG``; false if + triggered whenever ``\ARGS`` or ``\EN`` change and ``\EN`` is 1. + +If ``\TRG_ENABLE`` is true, the following parameters also apply: + +``\TRG_WIDTH`` + The number of bits in the ``\TRG`` port. + +``\TRG_POLARITY`` + For each bit in ``\TRG``, 1 if that signal is positive-edge triggered, 0 if + negative-edge triggered. + +``\PRIORITY`` + When multiple ``$print`` or ``$$check`` cells fire on the same trigger, they\ + execute in descending priority order. + +Ports: + +``\TRG`` + The signals that control when this ``$print`` cell is triggered. + If the width of this port is zero and ``\TRG_ENABLE`` is true, the cell is + triggered during initial evaluation (time zero) only. + +``\EN`` + Enable signal for the whole cell. + +``\ARGS`` + The values to be displayed, in format string order. + +Format string syntax +^^^^^^^^^^^^^^^^^^^^ + +The format string syntax resembles Python f-strings. Regular text is passed +through unchanged until a format specifier is reached, starting with a ``{``. + +Format specifiers have the following syntax. Unless noted, all items are +required: + +``{`` + Denotes the start of the format specifier. + +size + Signal size in bits; this many bits are consumed from the ``\ARGS`` port by + this specifier. + +``:`` + Separates the size from the remaining items. + +justify + ``>`` for right-justified, ``<`` for left-justified. + +padding + ``0`` for zero-padding, or a space for space-padding. + +width\ *?* + (optional) The number of characters wide to pad to. + +base + * ``b`` for base-2 integers (binary) + * ``o`` for base-8 integers (octal) + * ``d`` for base-10 integers (decimal) + * ``h`` for base-16 integers (hexadecimal) + * ``c`` for ASCII characters/strings + * ``t`` and ``r`` for simulation time (corresponding to :verilog:`$time` and :verilog:`$realtime`) + +For integers, this item may follow: + +``+``\ *?* + (optional, decimals only) Include a leading plus for non-negative numbers. + This can assist with symmetry with negatives in tabulated output. + +signedness + ``u`` for unsigned, ``s`` for signed. This distinction is only respected + when rendering decimals. + +ASCII characters/strings have no special options, but the signal size must be +divisible by 8. + +For simulation time, the signal size must be zero. + +Finally: + +``}`` + Denotes the end of the format specifier. + +Some example format specifiers: + ++ ``{8:>02hu}`` - 8-bit unsigned integer rendered as hexadecimal, + right-justified, zero-padded to 2 characters wide. ++ ``{32:< 15d+s}`` - 32-bit signed integer rendered as decimal, left-justified, + space-padded to 15 characters wide, positive values prefixed with ``+``. ++ ``{16:< 10hu}`` - 16-bit unsigned integer rendered as hexadecimal, + left-justified, space-padded to 10 characters wide. ++ ``{0:>010t}`` - simulation time, right-justified, zero-padded to 10 characters + wide. + +To include literal ``{`` and ``}`` characters in your format string, use ``{{`` +and ``}}`` respectively. + +It is an error for a format string to consume more or less bits from ``\ARGS`` +than the port width. + +Values are never truncated, regardless of the specified width. + +Note that further restrictions on allowable combinations of options may apply +depending on the backend used. + +For example, Verilog does not have a format specifier that allows zero-padding a +string (i.e. more than 1 ASCII character), though zero-padding a single +character is permitted. + +Thus, while the RTLIL format specifier ``{8:>02c}`` translates to ``%02c``, +``{16:>02c}`` cannot be represented in Verilog and will fail to emit. In this +case, ``{16:> 02c}`` must be used, which translates to ``%2s``. + .. _sec:celllib_gates: Gates diff --git a/yosys/examples/python-api/pass.py b/yosys/examples/python-api/pass.py index d67cf4a23c5..dbef0a13fb9 100755 --- a/yosys/examples/python-api/pass.py +++ b/yosys/examples/python-api/pass.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 -from pyosys import libyosys as ys +import libyosys as ys import matplotlib.pyplot as plt import numpy as np diff --git a/yosys/frontends/ast/ast.cc b/yosys/frontends/ast/ast.cc index a027295e979..fe075b27062 100644 --- a/yosys/frontends/ast/ast.cc +++ b/yosys/frontends/ast/ast.cc @@ -45,7 +45,7 @@ namespace AST { // instantiate global variables (private API) namespace AST_INTERNAL { - bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_nomem2reg, flag_mem2reg, flag_noblackbox, flag_lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_autowire; AstNode *current_ast, *current_ast_mod; std::map current_scope; @@ -229,6 +229,10 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch id2ast = NULL; basic_prep = false; lookahead = false; + in_lvalue_from_above = false; + in_param_from_above = false; + in_lvalue = false; + in_param = false; if (child1) children.push_back(child1); @@ -238,6 +242,8 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch children.push_back(child3); if (child4) children.push_back(child4); + + fixup_hierarchy_flags(); } // create a (deep recursive) copy of a node @@ -249,6 +255,10 @@ AstNode *AstNode::clone() const it = it->clone(); for (auto &it : that->attributes) it.second = it.second->clone(); + + that->set_in_lvalue_flag(false); + that->set_in_param_flag(false); + that->fixup_hierarchy_flags(); // fixup to set flags on cloned children return that; } @@ -256,10 +266,13 @@ AstNode *AstNode::clone() const void AstNode::cloneInto(AstNode *other) const { AstNode *tmp = clone(); + tmp->in_lvalue_from_above = other->in_lvalue_from_above; + tmp->in_param_from_above = other->in_param_from_above; other->delete_children(); *other = *tmp; tmp->children.clear(); tmp->attributes.clear(); + other->fixup_hierarchy_flags(); delete tmp; } @@ -351,6 +364,10 @@ void AstNode::dumpAst(FILE *f, std::string indent) const if (is_enum) { fprintf(f, " type=enum"); } + if (in_lvalue) + fprintf(f, " in_lvalue"); + if (in_param) + fprintf(f, " in_param"); fprintf(f, "\n"); for (auto &it : attributes) { @@ -641,11 +658,20 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const if (0) { case AST_NEG: txt = "-"; } if (0) { case AST_LOGIC_NOT: txt = "!"; } if (0) { case AST_SELFSZ: txt = "@selfsz@"; } + if (0) { case AST_TO_SIGNED: txt = "signed'"; } + if (0) { case AST_TO_UNSIGNED: txt = "unsigned'"; } fprintf(f, "%s(", txt.c_str()); children[0]->dumpVlog(f, ""); fprintf(f, ")"); break; + case AST_CAST_SIZE: + children[0]->dumpVlog(f, ""); + fprintf(f, "'("); + children[1]->dumpVlog(f, ""); + fprintf(f, ")"); + break; + if (0) { case AST_BIT_AND: txt = "&"; } if (0) { case AST_BIT_OR: txt = "|"; } if (0) { case AST_BIT_XOR: txt = "^"; } @@ -824,6 +850,25 @@ AstNode *AstNode::mkconst_str(const std::string &str) return node; } +// create a temporary register +AstNode *AstNode::mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed) +{ + AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(range_left, true), mkconst_int(range_right, true))); + wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); + if (nosync) + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); + wire->is_signed = is_signed; + wire->is_logic = true; + mod->children.push_back(wire); + while (wire->simplify(true, 1, -1, false)) { } + + AstNode *ident = new AstNode(AST_IDENTIFIER); + ident->str = wire->str; + ident->id2ast = wire; + + return ident; +} + bool AstNode::bits_only_01() const { for (auto bit : bits) @@ -1061,7 +1106,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d // simplify this module or interface using the current design as context // for lookup up ports and wires within cells set_simplify_design_context(design); - while (ast->simplify(!flag_noopt, false, 0, -1, false, false)) { } + while (ast->simplify(!flag_noopt, 0, -1, false)) { } set_simplify_design_context(nullptr); if (flag_dump_ast2) { @@ -1091,7 +1136,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d ast->attributes.erase(ID::whitebox); } AstNode *n = ast->attributes.at(ID::lib_whitebox); - ast->attributes[ID::whitebox] = n; + ast->set_attribute(ID::whitebox, n); ast->attributes.erase(ID::lib_whitebox); } } @@ -1150,7 +1195,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d ast->children.swap(new_children); if (ast->attributes.count(ID::blackbox) == 0) { - ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false); + ast->set_attribute(ID::blackbox, AstNode::mkconst_int(1, false)); } } @@ -1275,11 +1320,12 @@ static void rename_in_package_stmts(AstNode *pkg) } // create AstModule instances for all modules in the AST tree and add them to 'design' -void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, +void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; current_ast_mod = nullptr; + flag_nodisplay = nodisplay; flag_dump_ast1 = dump_ast1; flag_dump_ast2 = dump_ast2; flag_no_dump_ptr = no_dump_ptr; @@ -1298,6 +1344,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_pwires = pwires; flag_autowire = autowire; + ast->fixup_hierarchy_flags(true); + log_assert(current_ast->type == AST_DESIGN); for (AstNode *child : current_ast->children) { @@ -1361,7 +1409,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump } else if (child->type == AST_PACKAGE) { // process enum/other declarations - child->simplify(true, false, 1, -1, false, false); + child->simplify(true, 1, -1, false); rename_in_package_stmts(child); design->verilog_packages.push_back(child->clone()); current_scope.clear(); @@ -1748,7 +1796,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictclone(); if (!new_ast->attributes.count(ID::hdlname)) - new_ast->attributes[ID::hdlname] = AstNode::mkconst_str(stripped_name); + new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name)); para_counter = 0; for (auto child : new_ast->children) { @@ -1795,6 +1843,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictchildren.push_back(defparam); } + new_ast->fixup_hierarchy_flags(true); (*new_ast_out) = new_ast; return modname; } diff --git a/yosys/frontends/ast/ast.h b/yosys/frontends/ast/ast.h index 8893d5e010c..c447461312a 100644 --- a/yosys/frontends/ast/ast.h +++ b/yosys/frontends/ast/ast.h @@ -30,6 +30,7 @@ #define AST_H #include "kernel/rtlil.h" +#include "kernel/fmt.h" #include #include @@ -220,6 +221,13 @@ namespace AST std::string filename; AstSrcLocType location; + // are we embedded in an lvalue, param? + // (see fixup_hierarchy_flags) + bool in_lvalue; + bool in_param; + bool in_lvalue_from_above; + bool in_param_from_above; + // creating and deleting nodes AstNode(AstNodeType type = AST_NONE, AstNode *child1 = nullptr, AstNode *child2 = nullptr, AstNode *child3 = nullptr, AstNode *child4 = nullptr); AstNode *clone() const; @@ -250,7 +258,7 @@ namespace AST // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() - bool simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); + bool simplify(bool const_fold, int stage, int width_hint, bool sign_hint); void replace_result_wire_name_in_function(const std::string &from, const std::string &to); AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init); void expand_genblock(const std::string &prefix); @@ -277,7 +285,9 @@ namespace AST bool replace_variables(std::map &variables, AstNode *fcall, bool must_succeed); AstNode *eval_const_function(AstNode *fcall, bool must_succeed); bool is_simple_const_expr(); - std::string process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint); + + // helper for parsing format strings + Fmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false); bool is_recursive_function() const; std::pair get_tern_choice(); @@ -311,6 +321,9 @@ namespace AST static AstNode *mkconst_str(const std::vector &v); static AstNode *mkconst_str(const std::string &str); + // helper function to create an AST node for a temporary register + AstNode *mktemp_logic(const std::string &name, AstNode *mod, bool nosync, int range_left, int range_right, bool is_signed); + // helper function for creating sign-extended const objects RTLIL::Const bitsAsConst(int width, bool is_signed); RTLIL::Const bitsAsConst(int width = -1); @@ -340,12 +353,30 @@ namespace AST // to evaluate widths of dynamic ranges) AstNode *clone_at_zero(); + void set_attribute(RTLIL::IdString key, AstNode *node) + { + attributes[key] = node; + node->set_in_param_flag(true); + } + + // helper to set in_lvalue/in_param flags from the hierarchy context (the actual flag + // can be overridden based on the intrinsic properties of this node, i.e. based on its type) + void set_in_lvalue_flag(bool flag, bool no_descend = false); + void set_in_param_flag(bool flag, bool no_descend = false); + + // fix up the hierarchy flags (in_lvalue/in_param) of this node and its children + // + // to keep the flags in sync, fixup_hierarchy_flags(true) needs to be called once after + // parsing the AST to walk the full tree, then plain fixup_hierarchy_flags() performs + // localized fixups after modifying children/attributes of a particular node + void fixup_hierarchy_flags(bool force_descend = false); + // helper to print errors from simplify/genrtlil code [[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3)); }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library @@ -401,7 +432,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; + extern bool flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit; extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_pwires, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map current_scope; diff --git a/yosys/frontends/ast/genrtlil.cc b/yosys/frontends/ast/genrtlil.cc index 3aa19b70687..03697ebf314 100644 --- a/yosys/frontends/ast/genrtlil.cc +++ b/yosys/frontends/ast/genrtlil.cc @@ -163,6 +163,28 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const return wire; } +static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, + const AstNode *node, const char *to_add_kind) +{ + auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) { + std::string src = existing->get_string_attribute(ID::src); + std::string location_str = "earlier"; + if (!src.empty()) + location_str = "at " + src; + node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n", + to_add_kind, id.c_str(), existing_kind, location_str.c_str()); + }; + + if (const RTLIL::Wire *wire = module->wire(id)) + already_exists(wire, "signal"); + if (const RTLIL::Cell *cell = module->cell(id)) + already_exists(cell, "cell"); + if (module->processes.count(id)) + already_exists(module->processes.at(id), "process"); + if (module->memories.count(id)) + already_exists(module->memories.at(id), "memory"); +} + // helper class for rewriting simple lookahead references in AST always blocks struct AST_INTERNAL::LookaheadRewriter { @@ -176,10 +198,11 @@ struct AST_INTERNAL::LookaheadRewriter AstNode *wire = new AstNode(AST_WIRE); for (auto c : node->id2ast->children) wire->children.push_back(c->clone()); + wire->fixup_hierarchy_flags(); wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); wire->is_logic = true; - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } current_ast_mod->children.push_back(wire); lookaheadids[node->str] = make_pair(node->id2ast, wire); wire->genRTLIL(); @@ -315,7 +338,10 @@ struct AST_INTERNAL::ProcessGenerator // Buffer for generating the init action RTLIL::SigSpec init_lvalue, init_rvalue; - ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg) + // The most recently assigned $print or $check cell \PRIORITY. + int last_effect_priority; + + ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), last_effect_priority(0) { // rewrite lookahead references LookaheadRewriter la_rewriter(always); @@ -693,8 +719,149 @@ struct AST_INTERNAL::ProcessGenerator ast->input_error("Found parameter declaration in block without label!\n"); break; - case AST_NONE: case AST_TCALL: + if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" || + ast->str == "$write" || ast->str == "$writeb" || ast->str == "$writeh" || ast->str == "$writeo") { + std::stringstream sstr; + sstr << ast->str << "$" << ast->filename << ":" << ast->location.first_line << "$" << (autoidx++); + + Wire *en = current_module->addWire(sstr.str() + "_EN", 1); + set_src_attr(en, ast); + proc->root_case.actions.push_back(SigSig(en, false)); + current_case->actions.push_back(SigSig(en, true)); + + RTLIL::SigSpec triggers; + RTLIL::Const polarity; + for (auto sync : proc->syncs) { + if (sync->type == RTLIL::STp) { + triggers.append(sync->signal); + polarity.bits.push_back(RTLIL::S1); + } else if (sync->type == RTLIL::STn) { + triggers.append(sync->signal); + polarity.bits.push_back(RTLIL::S0); + } + } + + RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($print)); + set_src_attr(cell, ast); + cell->setParam(ID::TRG_WIDTH, triggers.size()); + cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty()); + cell->setParam(ID::TRG_POLARITY, polarity); + cell->setParam(ID::PRIORITY, --last_effect_priority); + cell->setPort(ID::TRG, triggers); + cell->setPort(ID::EN, en); + + int default_base = 10; + if (ast->str.back() == 'b') + default_base = 2; + else if (ast->str.back() == 'o') + default_base = 8; + else if (ast->str.back() == 'h') + default_base = 16; + + std::vector args; + for (auto node : ast->children) { + int width; + bool is_signed; + node->detectSignWidth(width, is_signed, nullptr); + + VerilogFmtArg arg = {}; + arg.filename = node->filename; + arg.first_line = node->location.first_line; + if (node->type == AST_CONSTANT && node->is_string) { + arg.type = VerilogFmtArg::STRING; + arg.str = node->bitsAsConst().decode_string(); + // and in case this will be used as an argument... + arg.sig = node->bitsAsConst(); + arg.signed_ = false; + } else if (node->type == AST_IDENTIFIER && node->str == "$time") { + arg.type = VerilogFmtArg::TIME; + } else if (node->type == AST_IDENTIFIER && node->str == "$realtime") { + arg.type = VerilogFmtArg::TIME; + arg.realtime = true; + } else { + arg.type = VerilogFmtArg::INTEGER; + arg.sig = node->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap()); + arg.signed_ = is_signed; + } + args.push_back(arg); + } + + Fmt fmt; + fmt.parse_verilog(args, /*sformat_like=*/false, default_base, /*task_name=*/ast->str, current_module->name); + if (ast->str.substr(0, 8) == "$display") + fmt.append_string("\n"); + fmt.emit_rtlil(cell); + } else if (!ast->str.empty()) { + log_file_error(ast->filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str()); + } + break; + + // generate $check cells + case AST_ASSERT: + case AST_ASSUME: + case AST_LIVE: + case AST_FAIR: + case AST_COVER: + { + std::string flavor, desc; + if (ast->type == AST_ASSERT) { flavor = "assert"; desc = "assert ()"; } + if (ast->type == AST_ASSUME) { flavor = "assume"; desc = "assume ()"; } + if (ast->type == AST_LIVE) { flavor = "live"; desc = "assert (eventually)"; } + if (ast->type == AST_FAIR) { flavor = "fair"; desc = "assume (eventually)"; } + if (ast->type == AST_COVER) { flavor = "cover"; desc = "cover ()"; } + + IdString cellname; + if (ast->str.empty()) + cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(ast->filename).c_str(), ast->location.first_line, autoidx++); + else + cellname = ast->str; + check_unique_id(current_module, cellname, ast, "procedural assertion"); + + RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap()); + if (GetSize(check) != 1) + check = current_module->ReduceBool(NEW_ID, check); + + Wire *en = current_module->addWire(cellname.str() + "_EN", 1); + set_src_attr(en, ast); + proc->root_case.actions.push_back(SigSig(en, false)); + current_case->actions.push_back(SigSig(en, true)); + + RTLIL::SigSpec triggers; + RTLIL::Const polarity; + for (auto sync : proc->syncs) { + if (sync->type == RTLIL::STp) { + triggers.append(sync->signal); + polarity.bits.push_back(RTLIL::S1); + } else if (sync->type == RTLIL::STn) { + triggers.append(sync->signal); + polarity.bits.push_back(RTLIL::S0); + } + } + + RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); + set_src_attr(cell, ast); + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + cell->attributes[attr.first] = attr.second->asAttrConst(); + } + cell->setParam(ID::FLAVOR, flavor); + cell->setParam(ID::TRG_WIDTH, triggers.size()); + cell->setParam(ID::TRG_ENABLE, (always->type == AST_INITIAL) || !triggers.empty()); + cell->setParam(ID::TRG_POLARITY, polarity); + cell->setParam(ID::PRIORITY, --last_effect_priority); + cell->setPort(ID::TRG, triggers); + cell->setPort(ID::EN, en); + cell->setPort(ID::A, check); + + // No message is emitted to ensure Verilog code roundtrips correctly. + Fmt fmt; + fmt.emit_rtlil(cell); + break; + } + + case AST_NONE: case AST_FOR: break; @@ -845,7 +1012,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; } else { if (id_ast->children[0]->type != AST_CONSTANT) - while (id_ast->simplify(true, false, 1, -1, false, true)) { } + while (id_ast->simplify(true, 1, -1, false)) { } if (id_ast->children[0]->type == AST_CONSTANT) this_width = id_ast->children[0]->bits.size(); else @@ -889,8 +1056,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun else if (!range->range_valid) { AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (left_at_zero_ast->simplify(true, 1, -1, false)) { } + while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; @@ -906,7 +1073,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_TO_BITS: - while (children[0]->simplify(true, false, 1, -1, false, false) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("Left operand of tobits expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); @@ -928,7 +1095,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_CAST_SIZE: - while (children.at(0)->simplify(true, false, 1, -1, false, false)) { } + while (children.at(0)->simplify(true, 1, -1, false)) { } if (children.at(0)->type != AST_CONSTANT) input_error("Static cast with non constant expression!\n"); children.at(1)->detectSignWidthWorker(width_hint, sign_hint); @@ -950,7 +1117,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_REPLICATE: - while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("Left operand of replicate expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); @@ -1062,7 +1229,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_PREFIX: // Prefix nodes always resolve to identifiers in generate loops, so we // can simply perform the resolution to determine the sign and width. - simplify(true, false, 1, -1, false, false); + simplify(true, 1, -1, false); log_assert(type == AST_IDENTIFIER); detectSignWidthWorker(width_hint, sign_hint, found_real); break; @@ -1070,7 +1237,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_FCALL: if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") { if (GetSize(children) == 1) { - while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, 1, -1, false) == true) { } if (children[0]->type != AST_CONSTANT) input_error("System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); @@ -1117,8 +1284,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun log_assert(range->type == AST_RANGE && range->children.size() == 2); AstNode *left = range->children.at(0)->clone(); AstNode *right = range->children.at(1)->clone(); - while (left->simplify(true, false, 1, -1, false, true)) { } - while (right->simplify(true, false, 1, -1, false, true)) { } + left->set_in_param_flag(true); + right->set_in_param_flag(true); + while (left->simplify(true, 1, -1, false)) { } + while (right->simplify(true, 1, -1, false)) { } if (left->type != AST_CONSTANT || right->type != AST_CONSTANT) input_error("Function %s has non-constant width!", RTLIL::unescape_id(str).c_str()); @@ -1158,28 +1327,6 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real width_hint, kWidthLimit); } -static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, - const AstNode *node, const char *to_add_kind) -{ - auto already_exists = [&](const RTLIL::AttrObject *existing, const char *existing_kind) { - std::string src = existing->get_string_attribute(ID::src); - std::string location_str = "earlier"; - if (!src.empty()) - location_str = "at " + src; - node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n", - to_add_kind, id.c_str(), existing_kind, location_str.c_str()); - }; - - if (const RTLIL::Wire *wire = module->wire(id)) - already_exists(wire, "signal"); - if (const RTLIL::Cell *cell = module->cell(id)) - already_exists(cell, "cell"); - if (module->processes.count(id)) - already_exists(module->processes.at(id), "process"); - if (module->memories.count(id)) - already_exists(module->memories.at(id), "memory"); -} - // create RTLIL from an AST node // all generated cells, wires and processes are added to the module pointed to by 'current_module' // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned. @@ -1462,8 +1609,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!children[0]->range_valid) { AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (left_at_zero_ast->simplify(true, 1, -1, false)) { } + while (right_at_zero_ast->simplify(true, 1, -1, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; @@ -1471,7 +1618,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); if (member_node) - fake_ast->children[0]->attributes[ID::wiretype] = member_node->clone(); + fake_ast->children[0]->set_attribute(ID::wiretype, member_node->clone()); int fake_ast_width = 0; bool fake_ast_sign = true; @@ -1656,7 +1803,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (width_hint < 0) detectSignWidth(width_hint, sign_hint); RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint); - RTLIL::SigSpec right = children[1]->genRTLIL(); + // for $shift and $shiftx, the second operand can be negative + RTLIL::SigSpec right = children[1]->genRTLIL(-1, type == AST_SHIFT || type == AST_SHIFTX); int width = width_hint > 0 ? width_hint : left.size(); is_signed = children[0]->is_signed; return binop2rtlil(this, type_name, width, left, right); @@ -1860,48 +2008,50 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } break; - // generate $assert cells + // generate $check cells case AST_ASSERT: case AST_ASSUME: case AST_LIVE: case AST_FAIR: case AST_COVER: { - IdString celltype; - if (type == AST_ASSERT) celltype = ID($assert); - if (type == AST_ASSUME) celltype = ID($assume); - if (type == AST_LIVE) celltype = ID($live); - if (type == AST_FAIR) celltype = ID($fair); - if (type == AST_COVER) celltype = ID($cover); - - log_assert(children.size() == 2); - - RTLIL::SigSpec check = children[0]->genRTLIL(); - if (GetSize(check) != 1) - check = current_module->ReduceBool(NEW_ID, check); - - RTLIL::SigSpec en = children[1]->genRTLIL(); - if (GetSize(en) != 1) - en = current_module->ReduceBool(NEW_ID, en); + std::string flavor, desc; + if (type == AST_ASSERT) { flavor = "assert"; desc = "assert property ()"; } + if (type == AST_ASSUME) { flavor = "assume"; desc = "assume property ()"; } + if (type == AST_LIVE) { flavor = "live"; desc = "assert property (eventually)"; } + if (type == AST_FAIR) { flavor = "fair"; desc = "assume property (eventually)"; } + if (type == AST_COVER) { flavor = "cover"; desc = "cover property ()"; } IdString cellname; if (str.empty()) - cellname = stringf("%s$%s:%d$%d", celltype.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); + cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); else cellname = str; - check_unique_id(current_module, cellname, this, "procedural assertion"); - RTLIL::Cell *cell = current_module->addCell(cellname, celltype); - set_src_attr(cell, this); + RTLIL::SigSpec check = children[0]->genRTLIL(); + if (GetSize(check) != 1) + check = current_module->ReduceBool(NEW_ID, check); + + RTLIL::Cell *cell = current_module->addCell(cellname, ID($check)); + set_src_attr(cell, this); for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - + cell->setParam(ID(FLAVOR), flavor); + cell->parameters[ID::TRG_WIDTH] = 0; + cell->parameters[ID::TRG_ENABLE] = 0; + cell->parameters[ID::TRG_POLARITY] = 0; + cell->parameters[ID::PRIORITY] = 0; + cell->setPort(ID::TRG, RTLIL::SigSpec()); + cell->setPort(ID::EN, RTLIL::S1); cell->setPort(ID::A, check); - cell->setPort(ID::EN, en); + + // No message is emitted to ensure Verilog code roundtrips correctly. + Fmt fmt; + fmt.emit_rtlil(cell); } break; diff --git a/yosys/frontends/ast/simplify.cc b/yosys/frontends/ast/simplify.cc index 64191cd7ebf..8e0de299470 100644 --- a/yosys/frontends/ast/simplify.cc +++ b/yosys/frontends/ast/simplify.cc @@ -35,149 +35,153 @@ #include #include #include +// For std::gcd in C++17 +// #include YOSYS_NAMESPACE_BEGIN using namespace AST; using namespace AST_INTERNAL; -// Process a format string and arguments for $display, $write, $sprintf, etc - -std::string AstNode::process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint) { - // Other arguments are placeholders. Process the string as we go through it - std::string sout; - for (size_t i = 0; i < sformat.length(); i++) - { - // format specifier - if (sformat[i] == '%') - { - // If there's no next character, that's a problem - if (i+1 >= sformat.length()) - input_error("System task `%s' called with `%%' at end of string.\n", str.c_str()); - - char cformat = sformat[++i]; - - // %% is special, does not need a matching argument - if (cformat == '%') - { - sout += '%'; - continue; - } - - bool got_len = false; - bool got_zlen = false; - int len_value = 0; - - while ('0' <= cformat && cformat <= '9') - { - if (!got_len && cformat == '0') - got_zlen = true; - - got_len = true; - len_value = 10*len_value + (cformat - '0'); +// gcd computed by Euclidian division. +// To be replaced by C++17 std::gcd +template I gcd(I a, I b) { + while (b != 0) { + I tmp = b; + b = a%b; + a = tmp; + } + return std::abs(a); +} - cformat = sformat[++i]; - } +void AstNode::set_in_lvalue_flag(bool flag, bool no_descend) +{ + if (flag != in_lvalue_from_above) { + in_lvalue_from_above = flag; + if (!no_descend) + fixup_hierarchy_flags(); + } +} - // Simplify the argument - AstNode *node_arg = nullptr; +void AstNode::set_in_param_flag(bool flag, bool no_descend) +{ + if (flag != in_param_from_above) { + in_param_from_above = flag; + if (!no_descend) + fixup_hierarchy_flags(); + } +} - // Everything from here on depends on the format specifier - switch (cformat) - { - case 's': - case 'S': - case 'd': - case 'D': - if (got_len && len_value != 0) - goto unsupported_format; - YS_FALLTHROUGH - case 'x': - case 'X': - if (next_arg >= GetSize(children)) - input_error("Missing argument for %%%c format specifier in system task `%s'.\n", - cformat, str.c_str()); - - node_arg = children[next_arg++]; - while (node_arg->simplify(true, false, stage, width_hint, sign_hint, false)) { } - if (node_arg->type != AST_CONSTANT) - input_error("Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); - break; +void AstNode::fixup_hierarchy_flags(bool force_descend) +{ + // With forced descend, we disable the implicit + // descend from within the set_* functions, instead + // we do an explicit descend at the end of this function - case 'm': - case 'M': - if (got_len) - goto unsupported_format; - break; + in_param = in_param_from_above; - case 'l': - case 'L': - if (got_len) - goto unsupported_format; - break; + switch (type) { + case AST_PARAMETER: + case AST_LOCALPARAM: + case AST_DEFPARAM: + case AST_PARASET: + case AST_PREFIX: + in_param = true; + for (auto child : children) + child->set_in_param_flag(true, force_descend); + break; - default: - unsupported_format: - input_error("System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); - break; - } + case AST_REPLICATE: + case AST_WIRE: + case AST_GENIF: + case AST_GENCASE: + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + if (children.size() >= 1) + children[0]->set_in_param_flag(true, force_descend); + break; - switch (cformat) - { - case 's': - case 'S': - sout += node_arg->bitsAsConst().decode_string(); - break; + case AST_GENFOR: + case AST_FOR: + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + if (children.size() >= 2) + children[1]->set_in_param_flag(true, force_descend); + break; - case 'd': - case 'D': - sout += stringf("%d", node_arg->bitsAsConst().as_int()); - break; + default: + in_param = in_param_from_above; + for (auto child : children) + child->set_in_param_flag(in_param, force_descend); + } - case 'x': - case 'X': - { - Const val = node_arg->bitsAsConst(); + for (auto attr : attributes) + attr.second->set_in_param_flag(true, force_descend); - while (GetSize(val) % 4 != 0) - val.bits.push_back(State::S0); + in_lvalue = in_lvalue_from_above; - int len = GetSize(val) / 4; - for (int i = len; i < len_value; i++) - sout += got_zlen ? '0' : ' '; + switch (type) { + case AST_ASSIGN: + case AST_ASSIGN_EQ: + case AST_ASSIGN_LE: + if (children.size() >= 1) + children[0]->set_in_lvalue_flag(true, force_descend); + if (children.size() >= 2) + children[1]->set_in_lvalue_flag(in_lvalue, force_descend); + break; - for (int i = len-1; i >= 0; i--) { - Const digit = val.extract(4*i, 4); - if (digit.is_fully_def()) - sout += stringf(cformat == 'x' ? "%x" : "%X", digit.as_int()); - else - sout += cformat == 'x' ? "x" : "X"; - } - } - break; + default: + for (auto child : children) + child->set_in_lvalue_flag(in_lvalue, force_descend); + } - case 'm': - case 'M': - sout += log_id(current_module->name); - break; + if (force_descend) { + for (auto child : children) + child->fixup_hierarchy_flags(true); + for (auto attr : attributes) + attr.second->fixup_hierarchy_flags(true); + } +} - case 'l': - case 'L': - sout += log_id(current_module->name); - break; +// Process a format string and arguments for $display, $write, $sprintf, etc - default: - log_abort(); - } +Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at, bool may_fail) { + std::vector args; + for (size_t index = first_arg_at; index < children.size(); index++) { + AstNode *node_arg = children[index]; + while (node_arg->simplify(true, stage, -1, false)) { } + + VerilogFmtArg arg = {}; + arg.filename = filename; + arg.first_line = location.first_line; + if (node_arg->type == AST_CONSTANT && node_arg->is_string) { + arg.type = VerilogFmtArg::STRING; + arg.str = node_arg->bitsAsConst().decode_string(); + // and in case this will be used as an argument... + arg.sig = node_arg->bitsAsConst(); + arg.signed_ = false; + } else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$time") { + arg.type = VerilogFmtArg::TIME; + } else if (node_arg->type == AST_IDENTIFIER && node_arg->str == "$realtime") { + arg.type = VerilogFmtArg::TIME; + arg.realtime = true; + } else if (node_arg->type == AST_CONSTANT) { + arg.type = VerilogFmtArg::INTEGER; + arg.sig = node_arg->bitsAsConst(); + arg.signed_ = node_arg->is_signed; + } else if (may_fail) { + log_file_info(filename, location.first_line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); + return Fmt(); + } else { + log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); } - - // not a format specifier - else - sout += sformat[i]; + args.push_back(arg); } - return sout; -} + Fmt fmt; + fmt.parse_verilog(args, sformat_like, default_base, /*task_name=*/str, current_module->name); + return fmt; +} void AstNode::annotateTypedEnums(AstNode *template_node) { @@ -192,7 +196,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node) log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); - while (enum_node->simplify(true, false, 1, -1, false, true)) { } + while (enum_node->simplify(true, 1, -1, false)) { } //get width from 1st enum item: log_assert(enum_node->children.size() >= 1); AstNode *enum_item0 = enum_node->children[0]; @@ -216,8 +220,8 @@ void AstNode::annotateTypedEnums(AstNode *template_node) log_assert(enum_item->children[1]->type == AST_RANGE); is_signed = enum_item->children[1]->is_signed; } else { - log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n", - enum_item->children.size(), + log_error("enum_item children size==%zu, expected 1 or 2 for %s (%s)\n", + (size_t) enum_item->children.size(), enum_item->str.c_str(), enum_node->str.c_str() ); } @@ -233,22 +237,11 @@ void AstNode::annotateTypedEnums(AstNode *template_node) RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed); enum_item_str.append(val.as_string()); //set attribute for available val to enum item name mappings - attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str); + set_attribute(enum_item_str.c_str(), mkconst_str(enum_item->str)); } } } -static bool name_has_dot(const std::string &name, std::string &struct_name) -{ - // check if plausible struct member name \sss.mmm - std::string::size_type pos; - if (name.substr(0, 1) == "\\" && (pos = name.find('.', 0)) != std::string::npos) { - struct_name = name.substr(0, pos); - return true; - } - return false; -} - static AstNode *make_range(int left, int right, bool is_signed = false) { // generate a pre-validated range node for a fixed signal range. @@ -558,17 +551,15 @@ static int get_max_offset(AstNode *node) static AstNode *make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes) { // create a wire for the packed struct - auto wnode = new AstNode(AST_WIRE); + int offset = get_max_offset(template_node); + auto wnode = new AstNode(AST_WIRE, make_range(offset, 0)); wnode->str = name; wnode->is_logic = true; wnode->range_valid = true; wnode->is_signed = template_node->is_signed; for (auto &pair : attributes) { - wnode->attributes[pair.first] = pair.second->clone(); + wnode->set_attribute(pair.first, pair.second->clone()); } - int offset = get_max_offset(template_node); - auto range = make_range(offset, 0); - wnode->children.push_back(range); // make sure this node is the one in scope for this name current_scope[name] = wnode; // add all the struct members to scope under the wire's name @@ -628,7 +619,7 @@ const RTLIL::Module* AstNode::lookup_cell_module() auto reprocess_after = [this] (const std::string &modname) { if (!attributes.count(ID::reprocess_after)) - attributes[ID::reprocess_after] = AstNode::mkconst_str(modname); + set_attribute(ID::reprocess_after, AstNode::mkconst_str(modname)); }; const AstNode *celltype = nullptr; @@ -793,7 +784,7 @@ AstNode *AstNode::clone_at_zero() pointee->type != AST_MEMORY) break; - YS_FALLTHROUGH; + YS_FALLTHROUGH case AST_MEMRD: detectSignWidth(width_hint, sign_hint); return mkconst_int(0, sign_hint, width_hint); @@ -808,6 +799,11 @@ AstNode *AstNode::clone_at_zero() it = it->clone_at_zero(); for (auto &it : that->attributes) it.second = it.second->clone(); + + that->set_in_lvalue_flag(false); + that->set_in_param_flag(false); + that->fixup_hierarchy_flags(); + return that; } @@ -823,8 +819,8 @@ static bool try_determine_range_width(AstNode *range, int &result_width) AstNode *left_at_zero_ast = range->children[0]->clone_at_zero(); AstNode *right_at_zero_ast = range->children[1]->clone_at_zero(); - while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} - while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} + while (left_at_zero_ast->simplify(true, 1, -1, false)) {} + while (right_at_zero_ast->simplify(true, 1, -1, false)) {} bool ok = false; if (left_at_zero_ast->type == AST_CONSTANT @@ -846,8 +842,7 @@ static void mark_auto_nosync(AstNode *block, const AstNode *wire) { log_assert(block->type == AST_BLOCK); log_assert(wire->type == AST_WIRE); - block->attributes[auto_nosync_prefix + wire->str] = AstNode::mkconst_int(1, - false); + block->set_attribute(auto_nosync_prefix + wire->str, AstNode::mkconst_int(1, false)); } // block names can be prefixed with an explicit scope during elaboration @@ -888,7 +883,7 @@ static void check_auto_nosync(AstNode *node) // mark the wire with `nosync` AstNode *wire = it->second; log_assert(wire->type == AST_WIRE); - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); } // remove the attributes we've "consumed" @@ -909,7 +904,7 @@ static void check_auto_nosync(AstNode *node) // // this function also does all name resolving and sets the id2ast member of all // nodes that link to a different node using names and lexical scoping. -bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) +bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hint) { static int recursion_counter = 0; static bool deep_recursion_warning = false; @@ -927,8 +922,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin #if 0 log("-------------\n"); log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this); - log("const_fold=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", - int(const_fold), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); + log("const_fold=%d, stage=%d, width_hint=%d, sign_hint=%d\n", + int(const_fold), int(stage), int(width_hint), int(sign_hint)); // dumpAst(NULL, "> "); #endif @@ -937,7 +932,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin log_assert(type == AST_MODULE || type == AST_INTERFACE); deep_recursion_warning = true; - while (simplify(const_fold, in_lvalue, 1, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, 1, width_hint, sign_hint)) { } if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg)) { @@ -1016,11 +1011,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin reg->is_signed = node->is_signed; for (auto &it : node->attributes) if (it.first != ID::mem2reg) - reg->attributes.emplace(it.first, it.second->clone()); + reg->set_attribute(it.first, it.second->clone()); reg->filename = node->filename; reg->location = node->location; children.push_back(reg); - while (reg->simplify(true, false, 1, -1, false, false)) { } + while (reg->simplify(true, 1, -1, false)) { } } } @@ -1034,7 +1029,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin delete node; } - while (simplify(const_fold, in_lvalue, 2, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, 2, width_hint, sign_hint)) { } recursion_counter--; return false; } @@ -1057,35 +1052,37 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin str = std::string(); } - if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) { - log_file_warning(filename, location.first_line, "System task `%s' outside initial block is unsupported.\n", str.c_str()); - delete_children(); - str = std::string(); - } - - // print messages if this a call to $display() or $write() - // This code implements only a small subset of Verilog-2005 $display() format specifiers, - // but should be good enough for most uses - if ((type == AST_TCALL) && ((str == "$display") || (str == "$write"))) + if ((type == AST_TCALL) && + (str == "$display" || str == "$displayb" || str == "$displayh" || str == "$displayo" || + str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo")) { - int nargs = GetSize(children); - if (nargs < 1) - input_error("System task `%s' got %d arguments, expected >= 1.\n", - str.c_str(), int(children.size())); - - // First argument is the format string - AstNode *node_string = children[0]; - while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { } - if (node_string->type != AST_CONSTANT) - input_error("Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); - std::string sformat = node_string->bitsAsConst().decode_string(); - std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); - // Finally, print the message (only include a \n for $display, not for $write) - log("%s", sout.c_str()); - if (str == "$display") - log("\n"); - delete_children(); - str = std::string(); + if (!current_always) { + log_file_warning(filename, location.first_line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str()); + delete_children(); + str = std::string(); + } else { + // simplify the expressions and convert them to a special cell later in genrtlil + for (auto node : children) + while (node->simplify(true, stage, -1, false)) {} + + if (current_always->type == AST_INITIAL && !flag_nodisplay && stage == 2) { + int default_base = 10; + if (str.back() == 'b') + default_base = 2; + else if (str.back() == 'o') + default_base = 8; + else if (str.back() == 'h') + default_base = 16; + + // when $display()/$write() functions are used in an initial block, print them during synthesis + Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true); + if (str.substr(0, 8) == "$display") + fmt.append_string("\n"); + log("%s", fmt.render().c_str()); + } + + return false; + } } // activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.) @@ -1094,10 +1091,6 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM || current_scope[str]->type == AST_ENUM_ITEM)) const_fold = true; - // in certain cases a function must be evaluated constant. this is what in_param controls. - if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_PREFIX) - in_param = true; - std::map backup_scope; // create name resolution entries for all objects with names @@ -1117,7 +1110,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (!c->is_simple_const_expr()) { if (attributes.count(ID::dynports)) delete attributes.at(ID::dynports); - attributes[ID::dynports] = AstNode::mkconst_int(1, true); + set_attribute(ID::dynports, AstNode::mkconst_int(1, true)); } } } @@ -1166,7 +1159,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin for (auto &it : node->attributes) { if (first_node->attributes.count(it.first) > 0) delete first_node->attributes[it.first]; - first_node->attributes[it.first] = it.second->clone(); + first_node->set_attribute(it.first, it.second->clone()); } children.erase(children.begin()+(i--)); did_something = true; @@ -1200,12 +1193,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) - while (node->simplify(true, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) + while (node->simplify(true, 1, -1, false)) did_something = true; if (node->type == AST_ENUM) { for (auto enode : node->children){ log_assert(enode->type==AST_ENUM_ITEM); - while (node->simplify(true, false, 1, -1, false, in_param)) + while (node->simplify(true, 1, -1, false)) did_something = true; } } @@ -1270,7 +1263,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin for (AstNode *child : children) { // simplify any parameters to constants if (child->type == AST_PARASET) - while (child->simplify(true, false, 1, -1, false, true)) { } + while (child->simplify(true, 1, -1, false)) { } // look for patterns which _may_ indicate ambiguity requiring // resolution of the underlying module @@ -1363,6 +1356,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin asgn->children.push_back(arg); asgn->children.push_back(ident); } + asgn->fixup_hierarchy_flags(); } @@ -1384,9 +1378,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin case AST_ASSIGN_EQ: case AST_ASSIGN_LE: case AST_ASSIGN: - while (!children[0]->basic_prep && children[0]->simplify(false, true, stage, -1, false, in_param) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true) did_something = true; - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true) did_something = true; children[0]->detectSignWidth(backup_width_hint, backup_sign_hint); children[1]->detectSignWidth(width_hint, sign_hint); @@ -1422,7 +1416,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (!basic_prep) { for (auto *node : children) { // resolve any ranges - while (!node->basic_prep && node->simplify(true, false, stage, -1, false, false)) { + while (!node->basic_prep && node->simplify(true, stage, -1, false)) { did_something = true; } } @@ -1455,7 +1449,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; // Remove type reference delete children[0]; @@ -1484,7 +1478,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // Copy clones of children from template for (auto template_child : template_node->children) { @@ -1501,7 +1495,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); if (!basic_prep) { for (auto item_node : children) { - while (!item_node->basic_prep && item_node->simplify(false, false, stage, -1, false, in_param)) + while (!item_node->basic_prep && item_node->simplify(false, stage, -1, false)) did_something = true; } // allocate values (called more than once) @@ -1516,16 +1510,16 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (children[0]->type == AST_IDENTIFIER && current_scope.count(children[0]->str) > 0) { auto item_node = current_scope[children[0]->str]; if (item_node->type == AST_STRUCT || item_node->type == AST_UNION) { - attributes[ID::wiretype] = item_node->clone(); + set_attribute(ID::wiretype, item_node->clone()); size_packed_struct(attributes[ID::wiretype], 0); add_members_to_scope(attributes[ID::wiretype], str); } } - while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, true) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false) == true) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, true) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false) == true) did_something = true; if (!children[1]->range_valid) input_error("Non-constant width range on parameter decl.\n"); @@ -1533,11 +1527,11 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } break; case AST_ENUM_ITEM: - while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(false, stage, -1, false)) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false)) did_something = true; if (!children[1]->range_valid) input_error("Non-constant width range on enum item decl.\n"); @@ -1596,7 +1590,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin width_hint = -1; sign_hint = true; for (auto child : children) { - while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, stage, -1, false) == true) did_something = true; child->detectSignWidthWorker(width_hint, sign_hint); } @@ -1631,10 +1625,10 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (detect_width_simple && width_hint < 0) { if (type == AST_REPLICATE) - while (children[0]->simplify(true, in_lvalue, stage, -1, false, true) == true) + while (children[0]->simplify(true, stage, -1, false) == true) did_something = true; for (auto child : children) - while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, stage, -1, false) == true) did_something = true; detectSignWidth(width_hint, sign_hint); } @@ -1644,18 +1638,18 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (type == AST_TERNARY) { if (width_hint < 0) { - while (!children[0]->basic_prep && children[0]->simplify(true, in_lvalue, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(true, stage, -1, false)) did_something = true; bool backup_unevaluated_tern_branch = unevaluated_tern_branch; AstNode *chosen = get_tern_choice().first; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2]; - while (!children[1]->basic_prep && children[1]->simplify(false, in_lvalue, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, stage, -1, false)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1]; - while (!children[2]->basic_prep && children[2]->simplify(false, in_lvalue, stage, -1, false, in_param)) + while (!children[2]->basic_prep && children[2]->simplify(false, stage, -1, false)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch; @@ -1687,7 +1681,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (const_fold && type == AST_CASE) { detectSignWidth(width_hint, sign_hint); - while (children[0]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (children[0]->simplify(const_fold, stage, width_hint, sign_hint)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); @@ -1701,7 +1695,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin goto keep_const_cond; if (v->type == AST_BLOCK) continue; - while (v->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (v->simplify(const_fold, stage, width_hint, sign_hint)) { } if (v->type == AST_CONSTANT && v->bits_only_01()) { RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint); RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1); @@ -1758,20 +1752,13 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin unevaluated_tern_branch = chosen && chosen != children[i]; } while (did_something_here && i < children.size()) { - bool const_fold_here = const_fold, in_lvalue_here = in_lvalue; + bool const_fold_here = const_fold; int width_hint_here = width_hint; bool sign_hint_here = sign_hint; - bool in_param_here = in_param; if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE)) - const_fold_here = true, in_param_here = true; - if (i == 0 && (type == AST_GENIF || type == AST_GENCASE)) - in_param_here = true; - if (i == 1 && (type == AST_FOR || type == AST_GENFOR)) - in_param_here = true; + const_fold_here = true; if (type == AST_PARAMETER || type == AST_LOCALPARAM) const_fold_here = true; - if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE)) - in_lvalue_here = true; if (type == AST_BLOCK) { current_block = this; current_block_child = children[i]; @@ -1786,7 +1773,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin width_hint_here = -1, sign_hint_here = false; if (children_are_self_determined) width_hint_here = -1, sign_hint_here = false; - did_something_here = children[i]->simplify(const_fold_here, in_lvalue_here, stage, width_hint_here, sign_hint_here, in_param_here); + did_something_here = children[i]->simplify(const_fold_here, stage, width_hint_here, sign_hint_here); if (did_something_here) did_something = true; } @@ -1806,7 +1793,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } } for (auto &attr : attributes) { - while (attr.second->simplify(true, false, stage, -1, false, true)) + while (attr.second->simplify(true, stage, -1, false)) did_something = true; } if (type == AST_CASE && stage == 2) { @@ -1884,7 +1871,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin log_assert(children.size() == 1); auto type_node = children[0]; log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION); - while (type_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { + while (type_node->simplify(const_fold, stage, width_hint, sign_hint)) { did_something = true; } log_assert(!type_node->is_custom_type); @@ -1906,12 +1893,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { // replace instance with wire representing the packed structure newNode = make_packed_struct(template_node, str, attributes); - newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // add original input/output attribute to resolved wire newNode->is_input = this->is_input; newNode->is_output = this->is_output; @@ -1936,7 +1923,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // if an enum then add attributes to support simulator tracing annotateTypedEnums(template_node); @@ -1950,6 +1937,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *rng = make_range(0, 0); children.insert(children.begin(), rng); } + fixup_hierarchy_flags(); did_something = true; } log_assert(!is_custom_type); @@ -1971,12 +1959,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, stage, width_hint, sign_hint)) {}; if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure newNode = make_packed_struct(template_node, str, attributes); - newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); newNode->type = type; current_scope[str] = this; // copy param value, it needs to be 1st value @@ -1998,9 +1986,10 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin range_swapped = template_node->range_swapped; range_left = template_node->range_left; range_right = template_node->range_right; - attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); for (auto template_child : template_node->children) children.push_back(template_child->clone()); + fixup_hierarchy_flags(); did_something = true; } log_assert(!is_custom_type); @@ -2013,7 +2002,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin input_error("Index in generate block prefix syntax is not constant!\n"); } if (children[1]->type == AST_PREFIX) - children[1]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param); + children[1]->simplify(const_fold, stage, width_hint, sign_hint); log_assert(children[1]->type == AST_IDENTIFIER); newNode = children[1]->clone(); const char *second_part = children[1]->str.c_str(); @@ -2120,6 +2109,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } delete children[1]; children[1] = new AstNode(AST_RANGE, AstNode::mkconst_int(0, true), AstNode::mkconst_int(total_size-1, true)); + fixup_hierarchy_flags(); did_something = true; } @@ -2154,6 +2144,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin else children[0] = new AstNode(AST_RANGE, index_expr); + fixup_hierarchy_flags(); did_something = true; } @@ -2169,6 +2160,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children[0]->realvalue, log_signal(constvalue)); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); + fixup_hierarchy_flags(); did_something = true; } if (children[0]->type == AST_CONSTANT) { @@ -2178,6 +2170,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *old_child_0 = children[0]; children[0] = mkconst_bits(sig.as_const().bits, is_signed); delete old_child_0; + fixup_hierarchy_flags(); } children[0]->is_signed = is_signed; } @@ -2191,23 +2184,37 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin delete children[0]; children[0] = new AstNode(AST_REALVALUE); children[0]->realvalue = as_realvalue; + fixup_hierarchy_flags(); did_something = true; } } if (type == AST_IDENTIFIER && !basic_prep) { // check if a plausible struct member sss.mmmm - std::string sname; - if (name_has_dot(str, sname)) { - if (current_scope.count(str) > 0) { - auto item_node = current_scope[str]; - if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) { + if (!str.empty() && str[0] == '\\' && current_scope.count(str)) { + auto item_node = current_scope[str]; + if (item_node->type == AST_STRUCT_ITEM || item_node->type == AST_STRUCT || item_node->type == AST_UNION) { + // Traverse any hierarchical path until the full name for the referenced struct/union is found. + std::string sname; + bool found_sname = false; + for (std::string::size_type pos = 0; (pos = str.find('.', pos)) != std::string::npos; pos++) { + sname = str.substr(0, pos); + if (current_scope.count(sname)) { + auto stype = current_scope[sname]->type; + if (stype == AST_WIRE || stype == AST_PARAMETER || stype == AST_LOCALPARAM) { + found_sname = true; + break; + } + } + } + + if (found_sname) { // structure member, rewrite this node to reference the packed struct wire auto range = make_struct_member_range(this, item_node); newNode = new AstNode(AST_IDENTIFIER, range); newNode->str = sname; // save type and original number of dimensions for $size() etc. - newNode->attributes[ID::wiretype] = item_node->clone(); + newNode->set_attribute(ID::wiretype, item_node->clone()); if (!item_node->multirange_dimensions.empty() && children.size() > 0) { if (children[0]->type == AST_RANGE) newNode->integer = 1; @@ -2301,9 +2308,9 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); wire->str = wire_id; if (current_block) - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *data = clone(); delete data->children[1]; @@ -2345,7 +2352,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin AstNode *body = children[1]; // eval count expression - while (count->simplify(true, false, stage, 32, true, false)) { } + while (count->simplify(true, stage, 32, true)) { } if (count->type != AST_CONSTANT) input_error("Repeat loops outside must have constant repeat counts!\n"); @@ -2401,7 +2408,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin int expr_width_hint = -1; bool expr_sign_hint = true; varbuf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (varbuf->simplify(true, false, stage, 32, true, false)) { } + while (varbuf->simplify(true, stage, 32, true)) { } } if (varbuf->type != AST_CONSTANT) @@ -2442,7 +2449,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, false)) { } + while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { } } if (buf->type != AST_CONSTANT) @@ -2477,7 +2484,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -2489,11 +2496,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin // eval 3rd expression buf = next_ast->children[1]->clone(); + buf->set_in_param_flag(true); { int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, true)) { } + while (buf->simplify(true, stage, expr_width_hint, expr_sign_hint)) { } } if (buf->type != AST_CONSTANT) @@ -2545,7 +2553,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin std::vector new_children; for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { - children[i]->simplify(false, false, stage, -1, false, false); + children[i]->simplify(false, stage, -1, false); current_ast_mod->children.push_back(children[i]); current_scope[children[i]->str] = children[i]; } else @@ -2564,7 +2572,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } for (size_t i = 0; i < children.size(); i++) { - children[i]->simplify(const_fold, false, stage, -1, false, false); + children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(children[i]); } @@ -2576,7 +2584,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (type == AST_GENIF && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2600,7 +2608,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2616,7 +2624,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (type == AST_GENCASE && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2650,7 +2658,8 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin continue; buf = child->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, true)) { } + buf->set_in_param_flag(true); + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); @@ -2678,7 +2687,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, stage, -1, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2756,6 +2765,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children.push_back(children_list.at(0)); children.back()->was_checked = true; children.push_back(node); + fixup_hierarchy_flags(); did_something = true; } else if (str == "buf" || str == "not") @@ -2806,6 +2816,7 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin children.push_back(children_list[0]); children.back()->was_checked = true; children.push_back(node); + fixup_hierarchy_flags(); did_something = true; } } @@ -2824,27 +2835,12 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin if (!children[0]->id2ast->range_valid) goto skip_dynamic_range_lvalue_expansion; - int source_width = children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1; - int source_offset = children[0]->id2ast->range_right; - int result_width = 1; - int stride = 1; AST::AstNode *member_node = get_struct_member(children[0]); - if (member_node) { - // Clamp chunk to range of member within struct/union. - log_assert(!source_offset && !children[0]->id2ast->range_swapped); - source_width = member_node->range_left - member_node->range_right + 1; - - // When the (* nowrshmsk *) attribute is set, a CASE block is generated below - // to select the indexed bit slice. When a multirange array is indexed, the - // start of each possible slice is separated by the bit stride of the last - // index dimension, and we can optimize the CASE block accordingly. - // The dimension of the original array expression is saved in the 'integer' field. - int dims = children[0]->integer; - stride = source_width; - for (int dim = 0; dim < dims; dim++) { - stride /= get_struct_range_width(member_node, dim); - } - } + int wire_width = member_node ? + member_node->range_left - member_node->range_right + 1 : + children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1; + int wire_offset = children[0]->id2ast->range_right; + int result_width = 1; AstNode *shift_expr = NULL; AstNode *range = children[0]->children[0]; @@ -2857,227 +2853,192 @@ bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hin else shift_expr = range->children[0]->clone(); - bool use_case_method = false; - - if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) { - AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk); - while (node->simplify(true, false, stage, -1, false, false)) { } - if (node->type != AST_CONSTANT) - input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); - if (node->asAttrConst().as_bool()) - use_case_method = true; - } + bool use_case_method = children[0]->id2ast->get_bool_attribute(ID::nowrshmsk); if (!use_case_method && current_always->detect_latch(children[0]->str)) use_case_method = true; - if (use_case_method) - { + if (use_case_method) { // big case block + int stride = 1; + long long bitno_div = stride; + + int case_width_hint; + bool case_sign_hint; + shift_expr->detectSignWidth(case_width_hint, case_sign_hint); + int max_width = case_width_hint; + + if (member_node) { // Member in packed struct/union + // Clamp chunk to range of member within struct/union. + log_assert(!wire_offset && !children[0]->id2ast->range_swapped); + + // When the (* nowrshmsk *) attribute is set, a CASE block is generated below + // to select the indexed bit slice. When a multirange array is indexed, the + // start of each possible slice is separated by the bit stride of the last + // index dimension, and we can optimize the CASE block accordingly. + // The dimension of the original array expression is saved in the 'integer' field. + int dims = children[0]->integer; + stride = wire_width; + for (int dim = 0; dim < dims; dim++) { + stride /= get_struct_range_width(member_node, dim); + } + bitno_div = stride; + } else { + // Extract (index)*(width) from non_opt_range pattern ((@selfsz@((index)*(width)))+(0)). + AstNode *lsb_expr = + shift_expr->type == AST_ADD && shift_expr->children[0]->type == AST_SELFSZ && + shift_expr->children[1]->type == AST_CONSTANT && shift_expr->children[1]->integer == 0 ? + shift_expr->children[0]->children[0] : + shift_expr; + + // Extract stride from indexing of two-dimensional packed arrays and + // variable slices on the form dst[i*stride +: width] = src. + if (lsb_expr->type == AST_MUL && + (lsb_expr->children[0]->type == AST_CONSTANT || + lsb_expr->children[1]->type == AST_CONSTANT)) + { + int stride_ix = lsb_expr->children[1]->type == AST_CONSTANT; + stride = (int)lsb_expr->children[stride_ix]->integer; + bitno_div = stride != 0 ? stride : 1; + + // Check whether i*stride can overflow. + int i_width; + bool i_sign; + lsb_expr->children[1 - stride_ix]->detectSignWidth(i_width, i_sign); + int stride_width; + bool stride_sign; + lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign); + max_width = std::max(i_width, stride_width); + // Stride width calculated from actual stride value. + stride_width = std::ceil(std::log2(std::abs(stride))); + + if (i_width + stride_width > max_width) { + // For (truncated) i*stride to be within the range of dst, the following must hold: + // i*stride ≡ bitno (mod shift_mod), i.e. + // i*stride = k*shift_mod + bitno + // + // The Diophantine equation on the form ax + by = c: + // stride*i - shift_mod*k = bitno + // has solutions iff c is a multiple of d = gcd(a, b), i.e. + // bitno mod gcd(stride, shift_mod) = 0 + // + // long long is at least 64 bits in C++11 + long long shift_mod = 1ll << (max_width - case_sign_hint); + // std::gcd requires C++17 + // bitno_div = std::gcd(stride, shift_mod); + bitno_div = gcd((long long)stride, shift_mod); + } + } + } + + // long long is at least 64 bits in C++11 + long long max_offset = (1ll << (max_width - case_sign_hint)) - 1; + long long min_offset = case_sign_hint ? -(1ll << (max_width - 1)) : 0; + + // A temporary register holds the result of the (possibly complex) rvalue expression, + // avoiding repetition in each AST_COND below. + int rvalue_width; + bool rvalue_sign; + children[1]->detectSignWidth(rvalue_width, rvalue_sign); + AstNode *rvalue = mktemp_logic("$bitselwrite$rvalue$", current_ast_mod, true, rvalue_width - 1, 0, rvalue_sign); + AstNode *caseNode = new AstNode(AST_CASE, shift_expr); + newNode = new AstNode(AST_BLOCK, + new AstNode(AST_ASSIGN_EQ, rvalue, children[1]->clone()), + caseNode); + did_something = true; - newNode = new AstNode(AST_CASE, shift_expr); - for (int i = 0; i < source_width; i += stride) { - int start_bit = source_offset + i; - int end_bit = std::min(start_bit+result_width,source_width) - 1; - AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true)); + for (int i = 1 - result_width; i < wire_width; i++) { + // Out of range indexes are handled in genrtlil.cc + int start_bit = wire_offset + i; + int end_bit = start_bit + result_width - 1; + // Check whether the current index can be generated by shift_expr. + if (start_bit < min_offset || start_bit > max_offset) + continue; + if (start_bit%bitno_div != 0 || (stride == 0 && start_bit != 0)) + continue; + + AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, case_sign_hint, max_width)); AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); if (member_node) - lvalue->attributes[ID::wiretype] = member_node->clone(); + lvalue->set_attribute(ID::wiretype, member_node->clone()); lvalue->children.push_back(new AstNode(AST_RANGE, mkconst_int(end_bit, true), mkconst_int(start_bit, true))); - cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); - newNode->children.push_back(cond); + cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, rvalue->clone()))); + caseNode->children.push_back(cond); } - } - else - { - // mask and shift operations, disabled for now - - AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); - wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false); - wire_mask->is_logic = true; - while (wire_mask->simplify(true, false, 1, -1, false, false)) { } - current_ast_mod->children.push_back(wire_mask); - - AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); - wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); - wire_data->is_logic = true; - while (wire_data->simplify(true, false, 1, -1, false, false)) { } - current_ast_mod->children.push_back(wire_data); - - int shamt_width_hint = -1; - bool shamt_sign_hint = true; - shift_expr->detectSignWidth(shamt_width_hint, shamt_sign_hint); - - AstNode *wire_sel = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(shamt_width_hint-1, true), mkconst_int(0, true))); - wire_sel->str = stringf("$bitselwrite$sel$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); - wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false); - wire_sel->is_logic = true; - wire_sel->is_signed = shamt_sign_hint; - while (wire_sel->simplify(true, false, 1, -1, false, false)) { } - current_ast_mod->children.push_back(wire_sel); - - did_something = true; - newNode = new AstNode(AST_BLOCK); + } else { + // mask and shift operations + // dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb) AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); if (member_node) - lvalue->attributes[ID::wiretype] = member_node->clone(); - - AstNode *ref_mask = new AstNode(AST_IDENTIFIER); - ref_mask->str = wire_mask->str; - ref_mask->id2ast = wire_mask; - ref_mask->was_checked = true; - - AstNode *ref_data = new AstNode(AST_IDENTIFIER); - ref_data->str = wire_data->str; - ref_data->id2ast = wire_data; - ref_data->was_checked = true; - - AstNode *ref_sel = new AstNode(AST_IDENTIFIER); - ref_sel->str = wire_sel->str; - ref_sel->id2ast = wire_sel; - ref_sel->was_checked = true; + lvalue->set_attribute(ID::wiretype, member_node->clone()); AstNode *old_data = lvalue->clone(); if (type == AST_ASSIGN_LE) old_data->lookahead = true; - AstNode *s = new AstNode(AST_ASSIGN_EQ, ref_sel->clone(), shift_expr); - newNode->children.push_back(s); + int shift_width_hint; + bool shift_sign_hint; + shift_expr->detectSignWidth(shift_width_hint, shift_sign_hint); + + // All operations are carried out in a new block. + newNode = new AstNode(AST_BLOCK); + + // Temporary register holding the result of the bit- or part-select position expression. + AstNode *pos = mktemp_logic("$bitselwrite$pos$", current_ast_mod, true, shift_width_hint - 1, 0, shift_sign_hint); + newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, pos, shift_expr)); - AstNode *shamt = ref_sel; + // Calculate lsb from position. + AstNode *shift_val = pos->clone(); - // convert to signed while preserving the sign and value - shamt = new AstNode(AST_CAST_SIZE, mkconst_int(shamt_width_hint + 1, true), shamt); - shamt = new AstNode(AST_TO_SIGNED, shamt); + // If the expression is signed, we must add an extra bit for possible negation of the most negative number. + // If the expression is unsigned, we must add an extra bit for sign. + shift_val = new AstNode(AST_CAST_SIZE, mkconst_int(shift_width_hint + 1, true), shift_val); + if (!shift_sign_hint) + shift_val = new AstNode(AST_TO_SIGNED, shift_val); // offset the shift amount by the lower bound of the dimension - int start_bit = source_offset; - shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true)); + if (wire_offset != 0) + shift_val = new AstNode(AST_SUB, shift_val, mkconst_int(wire_offset, true)); // reflect the shift amount if the dimension is swapped if (children[0]->id2ast->range_swapped) - shamt = new AstNode(AST_SUB, mkconst_int(source_width - result_width, true), shamt); + shift_val = new AstNode(AST_SUB, mkconst_int(wire_width - result_width, true), shift_val); // AST_SHIFT uses negative amounts for shifting left - shamt = new AstNode(AST_NEG, shamt); - - AstNode *t; + shift_val = new AstNode(AST_NEG, shift_val); - t = mkconst_bits(std::vector(result_width, State::S1), false); - t = new AstNode(AST_SHIFT, t, shamt->clone()); - t = new AstNode(AST_ASSIGN_EQ, ref_mask->clone(), t); - newNode->children.push_back(t); - - t = new AstNode(AST_BIT_AND, mkconst_bits(std::vector(result_width, State::S1), false), children[1]->clone()); - t = new AstNode(AST_SHIFT, t, shamt); - t = new AstNode(AST_ASSIGN_EQ, ref_data->clone(), t); - newNode->children.push_back(t); - - t = new AstNode(AST_BIT_AND, old_data, new AstNode(AST_BIT_NOT, ref_mask)); - t = new AstNode(AST_BIT_OR, t, ref_data); - t = new AstNode(type, lvalue, t); - newNode->children.push_back(t); + // dst = (dst & ~(width'1 << lsb)) | unsigned'(width'(src)) << lsb) + did_something = true; + AstNode *bitmask = mkconst_bits(std::vector(result_width, State::S1), false); + newNode->children.push_back( + new AstNode(type, + lvalue, + new AstNode(AST_BIT_OR, + new AstNode(AST_BIT_AND, + old_data, + new AstNode(AST_BIT_NOT, + new AstNode(AST_SHIFT, + bitmask, + shift_val->clone()))), + new AstNode(AST_SHIFT, + new AstNode(AST_TO_UNSIGNED, + new AstNode(AST_CAST_SIZE, + mkconst_int(result_width, true), + children[1]->clone())), + shift_val)))); + + newNode->fixup_hierarchy_flags(true); } goto apply_newNode; } skip_dynamic_range_lvalue_expansion:; - if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL) - { - std::stringstream sstr; - sstr << "$formal$" << RTLIL::encode_filename(filename) << ":" << location.first_line << "$" << (autoidx++); - std::string id_check = sstr.str() + "_CHECK", id_en = sstr.str() + "_EN"; - - AstNode *wire_check = new AstNode(AST_WIRE); - wire_check->str = id_check; - wire_check->was_checked = true; - current_ast_mod->children.push_back(wire_check); - current_scope[wire_check->str] = wire_check; - while (wire_check->simplify(true, false, 1, -1, false, false)) { } - - AstNode *wire_en = new AstNode(AST_WIRE); - wire_en->str = id_en; - wire_en->was_checked = true; - current_ast_mod->children.push_back(wire_en); - if (current_always_clocked) { - current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1))))); - current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en; - current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true; - } - current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, 1, -1, false, false)) { } - - AstNode *check_defval; - if (type == AST_LIVE || type == AST_FAIR) { - check_defval = new AstNode(AST_REDUCE_BOOL, children[0]->clone()); - } else { - std::vector x_bit; - x_bit.push_back(RTLIL::State::Sx); - check_defval = mkconst_bits(x_bit, false); - } - - AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), check_defval); - assign_check->children[0]->str = id_check; - assign_check->children[0]->was_checked = true; - - AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1)); - assign_en->children[0]->str = id_en; - assign_en->children[0]->was_checked = true; - - AstNode *default_signals = new AstNode(AST_BLOCK); - default_signals->children.push_back(assign_check); - default_signals->children.push_back(assign_en); - current_top_block->children.insert(current_top_block->children.begin(), default_signals); - - if (type == AST_LIVE || type == AST_FAIR) { - assign_check = nullptr; - } else { - assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone())); - assign_check->children[0]->str = id_check; - assign_check->children[0]->was_checked = true; - } - - if (current_always == nullptr || current_always->type != AST_INITIAL) { - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1)); - } else { - assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_FCALL)); - assign_en->children[1]->str = "\\$initstate"; - } - assign_en->children[0]->str = id_en; - assign_en->children[0]->was_checked = true; - - newNode = new AstNode(AST_BLOCK); - if (assign_check != nullptr) - newNode->children.push_back(assign_check); - newNode->children.push_back(assign_en); - - AstNode *assertnode = new AstNode(type); - assertnode->location = location; - assertnode->str = str; - assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); - assertnode->children.push_back(new AstNode(AST_IDENTIFIER)); - assertnode->children[0]->str = id_check; - assertnode->children[1]->str = id_en; - assertnode->attributes.swap(attributes); - current_ast_mod->children.push_back(assertnode); - - goto apply_newNode; - } - - if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1) - { - children.push_back(mkconst_int(1, false, 1)); - did_something = true; - } - // found right-hand side identifier for memory -> replace with memory read port if (stage > 1 && type == AST_IDENTIFIER && id2ast != NULL && id2ast->type == AST_MEMORY && !in_lvalue && children.size() == 1 && children[0]->type == AST_RANGE && children[0]->children.size() == 1) { @@ -3105,8 +3066,8 @@ skip_dynamic_range_lvalue_expansion:; wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; - wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); - while (wire_tmp->simplify(true, false, 1, -1, false, false)) { } + wire_tmp->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); + while (wire_tmp->simplify(true, 1, -1, false)) { } wire_tmp->is_logic = true; AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER); @@ -3176,7 +3137,7 @@ skip_dynamic_range_lvalue_expansion:; wire_addr->was_checked = true; current_ast_mod->children.push_back(wire_addr); current_scope[wire_addr->str] = wire_addr; - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); assign_addr->children[0]->str = id_addr; @@ -3202,7 +3163,7 @@ skip_dynamic_range_lvalue_expansion:; wire_data->is_signed = mem_signed; current_ast_mod->children.push_back(wire_data); current_scope[wire_data->str] = wire_data; - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } AstNode *assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); assign_data->children[0]->str = id_data; @@ -3218,7 +3179,7 @@ skip_dynamic_range_lvalue_expansion:; wire_en->was_checked = true; current_ast_mod->children.push_back(wire_en); current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, 1, -1, false, false)) { } + while (wire_en->simplify(true, 1, -1, false)) { } AstNode *assign_en_first = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en_first->children[0]->str = id_en; @@ -3346,7 +3307,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *wire = new AstNode(AST_WIRE); wire->str = stringf("$initstate$%d_wire", myidx); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER))); cell->str = stringf("$initstate$%d", myidx); @@ -3355,7 +3316,7 @@ skip_dynamic_range_lvalue_expansion:; cell->children[1]->children[0]->str = wire->str; cell->children[1]->children[0]->id2ast = wire; current_ast_mod->children.push_back(cell); - while (cell->simplify(true, false, 1, -1, false, false)) { } + while (cell->simplify(true, 1, -1, false)) { } newNode = new AstNode(AST_IDENTIFIER); newNode->str = wire->str; @@ -3381,7 +3342,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) == 2) { AstNode *buf = children[1]->clone(); - while (buf->simplify(true, false, stage, -1, false, false)) { } + while (buf->simplify(true, stage, -1, false)) { } if (buf->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); @@ -3416,7 +3377,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(reg); - while (reg->simplify(true, false, 1, -1, false, false)) { } + while (reg->simplify(true, 1, -1, false)) { } AstNode *regid = new AstNode(AST_IDENTIFIER); regid->str = reg->str; @@ -3492,7 +3453,7 @@ skip_dynamic_range_lvalue_expansion:; RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } if (buf->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); @@ -3524,7 +3485,7 @@ skip_dynamic_range_lvalue_expansion:; if (children.size() == 2) { AstNode *buf = children[1]->clone(); // Evaluate constant expression - while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, stage, width_hint, sign_hint)) { } dim = buf->asInt(false); delete buf; } @@ -3682,7 +3643,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 1) { - while (children[0]->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (children[0]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[0]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3693,7 +3654,7 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 2) { - while (children[1]->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (children[1]->simplify(true, stage, width_hint, sign_hint)) { } if (!children[1]->isConst()) input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); @@ -3735,13 +3696,8 @@ skip_dynamic_range_lvalue_expansion:; } if (str == "\\$sformatf") { - AstNode *node_string = children[0]; - while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { } - if (node_string->type != AST_CONSTANT) - input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); - std::string sformat = node_string->bitsAsConst().decode_string(); - std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); - newNode = AstNode::mkconst_str(sout); + Fmt fmt = processFormat(stage, /*sformat_like=*/true); + newNode = AstNode::mkconst_str(fmt.render()); goto apply_newNode; } @@ -3755,7 +3711,7 @@ skip_dynamic_range_lvalue_expansion:; // Determine which bits to count for (size_t i = 1; i < children.size(); i++) { AstNode *node = children[i]; - while (node->simplify(true, false, stage, -1, false, false)) { } + while (node->simplify(true, stage, -1, false)) { } if (node->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); if (node->bits.size() != 1) @@ -3850,7 +3806,7 @@ skip_dynamic_range_lvalue_expansion:; argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); - while (args.back()->simplify(true, false, stage, -1, false, true)) { } + while (args.back()->simplify(true, stage, -1, false)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) input_error("Failed to evaluate DPI function with non-constant argument.\n"); @@ -3887,12 +3843,12 @@ skip_dynamic_range_lvalue_expansion:; RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); - while (node_filename->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_filename->simplify(true, stage, width_hint, sign_hint)) { } if (node_filename->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); AstNode *node_memory = children[1]->clone(); - while (node_memory->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_memory->simplify(true, stage, width_hint, sign_hint)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); @@ -3900,7 +3856,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) > 2) { AstNode *node_addr = children[2]->clone(); - while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); start_addr = int(node_addr->asInt(false)); @@ -3908,7 +3864,7 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) > 3) { AstNode *node_addr = children[3]->clone(); - while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, stage, width_hint, sign_hint)) { } if (node_addr->type != AST_CONSTANT) input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); finish_addr = int(node_addr->asInt(false)); @@ -3960,13 +3916,14 @@ skip_dynamic_range_lvalue_expansion:; bool require_const_eval = decl->has_const_only_constructs(); bool all_args_const = true; for (auto child : children) { - while (child->simplify(true, false, 1, -1, false, true)) { } + while (child->simplify(true, 1, -1, false)) { } if (child->type != AST_CONSTANT && child->type != AST_REALVALUE) all_args_const = false; } if (all_args_const) { AstNode *func_workspace = decl->clone(); + func_workspace->set_in_param_flag(true); func_workspace->str = prefix_id(prefix, "$result"); newNode = func_workspace->eval_const_function(this, in_param || require_const_eval); delete func_workspace; @@ -4004,7 +3961,7 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire->str] = wire; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *lvalue = new AstNode(AST_IDENTIFIER); lvalue->str = wire->str; @@ -4050,7 +4007,7 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } AstNode *wire_id = new AstNode(AST_IDENTIFIER); wire_id->str = wire->str; @@ -4093,7 +4050,7 @@ skip_dynamic_range_lvalue_expansion:; for (auto c : child->children) wire->children.push_back(c->clone()); } else if (!child->children.empty()) { - while (child->simplify(true, false, stage, -1, false, false)) { } + while (child->simplify(true, stage, -1, false)) { } if (GetSize(child->children) == GetSize(wire->children) - contains_value) { for (int i = 0; i < GetSize(child->children); i++) if (*child->children.at(i) != *wire->children.at(i + contains_value)) @@ -4111,9 +4068,9 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; wire->is_reg = true; - wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); if (child->type == AST_ENUM_ITEM) - wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type]; + wire->set_attribute(ID::enum_base_type, child->attributes[ID::enum_base_type]); wire_cache[child->str] = wire; @@ -4121,7 +4078,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(wire); } - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } if ((child->is_input || child->is_output) && arg_count < children.size()) { @@ -4152,8 +4109,9 @@ skip_dynamic_range_lvalue_expansion:; range->children.push_back(mkconst_int(0, true)); } } + wire->fixup_hierarchy_flags(); // updates the sizing - while (wire->simplify(true, false, 1, -1, false, false)) { } + while (wire->simplify(true, 1, -1, false)) { } delete arg; continue; } @@ -4471,6 +4429,7 @@ replace_fcall_later:; newNode->filename = filename; newNode->location = location; newNode->cloneInto(this); + fixup_hierarchy_flags(); delete newNode; did_something = true; } @@ -4686,6 +4645,8 @@ void AstNode::expand_genblock(const std::string &prefix) switch (child->type) { case AST_WIRE: case AST_MEMORY: + case AST_STRUCT: + case AST_UNION: case AST_PARAMETER: case AST_LOCALPARAM: case AST_FUNCTION: @@ -5061,18 +5022,18 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->str = id_addr; wire_addr->is_reg = true; wire_addr->was_checked = true; - wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; wire_data->is_reg = true; wire_data->was_checked = true; wire_data->is_signed = mem_signed; - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } log_assert(block != NULL); size_t assign_idx = 0; @@ -5099,6 +5060,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, cond_node->children[1]->children.push_back(assign_reg); case_node->children.push_back(cond_node); } + + // fixup on the full hierarchy below case_node + case_node->fixup_hierarchy_flags(true); + block->children.insert(block->children.begin()+assign_idx+2, case_node); children[0]->delete_children(); @@ -5108,6 +5073,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, type = AST_ASSIGN_EQ; children[0]->was_checked = true; + fixup_hierarchy_flags(); did_something = true; } @@ -5178,9 +5144,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->is_reg = true; wire_addr->was_checked = true; if (block) - wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_addr->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, 1, -1, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; @@ -5188,9 +5154,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_data->was_checked = true; wire_data->is_signed = mem_signed; if (block) - wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); + wire_data->set_attribute(ID::nosync, AstNode::mkconst_int(1, false)); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, 1, -1, false)) { } AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone()); assign_addr->children[0]->str = id_addr; @@ -5222,6 +5188,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, cond_node->children[1]->children.push_back(assign_reg); case_node->children.push_back(cond_node); + // fixup on the full hierarchy below case_node + case_node->fixup_hierarchy_flags(true); + if (block) { size_t assign_idx = 0; @@ -5233,10 +5202,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, } else { - AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK)); - proc->children[0]->children.push_back(case_node); + AstNode *proc = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK, case_node)); mod->children.push_back(proc); mod->children.push_back(assign_addr); + mod->fixup_hierarchy_flags(); } delete_children(); @@ -5245,8 +5214,10 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, str = id_data; } - if (bit_part_sel) + if (bit_part_sel) { children.push_back(bit_part_sel); + fixup_hierarchy_flags(); + } did_something = true; } @@ -5368,7 +5339,7 @@ bool AstNode::replace_variables(std::map &varia } if (!children.at(0)->replace_variables(variables, fcall, must_succeed)) return false; - while (simplify(true, false, 1, -1, false, true)) { } + while (simplify(true, 1, -1, false)) { } if (!children.at(0)->range_valid) { if (!must_succeed) return false; @@ -5409,6 +5380,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) { block->children.push_back(child->clone()); } + block->set_in_param_flag(true); while (!block->children.empty()) { @@ -5423,7 +5395,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_WIRE) { - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } if (!stmt->range_valid) { if (!must_succeed) goto finished; @@ -5467,7 +5439,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_LOCALPARAM) { - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } current_scope[stmt->str] = stmt; @@ -5484,7 +5456,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed)) goto finished; - while (stmt->simplify(true, false, 1, -1, false, true)) { } + while (stmt->simplify(true, 1, -1, false)) { } if (stmt->type != AST_ASSIGN_EQ) continue; @@ -5551,7 +5523,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *cond = stmt->children.at(0)->clone(); if (!cond->replace_variables(variables, fcall, must_succeed)) goto finished; - while (cond->simplify(true, false, 1, -1, false, true)) { } + cond->set_in_param_flag(true); + while (cond->simplify(true, 1, -1, false)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) @@ -5576,7 +5549,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *num = stmt->children.at(0)->clone(); if (!num->replace_variables(variables, fcall, must_succeed)) goto finished; - while (num->simplify(true, false, 1, -1, false, true)) { } + num->set_in_param_flag(true); + while (num->simplify(true, 1, -1, false)) { } if (num->type != AST_CONSTANT) { if (!must_succeed) @@ -5599,7 +5573,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *expr = stmt->children.at(0)->clone(); if (!expr->replace_variables(variables, fcall, must_succeed)) goto finished; - while (expr->simplify(true, false, 1, -1, false, true)) { } + expr->set_in_param_flag(true); + while (expr->simplify(true, 1, -1, false)) { } AstNode *sel_case = NULL; for (size_t i = 1; i < stmt->children.size(); i++) @@ -5619,7 +5594,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; cond = new AstNode(AST_EQ, expr->clone(), cond); - while (cond->simplify(true, false, 1, -1, false, true)) { } + cond->set_in_param_flag(true); + while (cond->simplify(true, 1, -1, false)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) @@ -5654,6 +5630,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) block->children.erase(block->children.begin()); block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end()); stmt->children.clear(); + block->fixup_hierarchy_flags(); delete stmt; continue; } @@ -5688,7 +5665,7 @@ void AstNode::allocateDefaultEnumValues() int last_enum_int = -1; for (auto node : children) { log_assert(node->type==AST_ENUM_ITEM); - node->attributes[ID::enum_base_type] = mkconst_str(str); + node->set_attribute(ID::enum_base_type, mkconst_str(str)); for (size_t i = 0; i < node->children.size(); i++) { switch (node->children[i]->type) { case AST_NONE: diff --git a/yosys/frontends/blif/blifparse.cc b/yosys/frontends/blif/blifparse.cc index ebbe082a2e8..731656866ea 100644 --- a/yosys/frontends/blif/blifparse.cc +++ b/yosys/frontends/blif/blifparse.cc @@ -256,6 +256,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool continue; } + if (!strcmp(cmd, ".area") || !strcmp(cmd, ".delay") || !strcmp(cmd, ".wire_load_slope") || !strcmp(cmd, ".wire") || + !strcmp(cmd, ".input_arrival") || !strcmp(cmd, ".default_input_arrival") || !strcmp(cmd, ".output_required") || + !strcmp(cmd, ".default_output_required") || !strcmp(cmd, ".input_drive") || !strcmp(cmd, ".default_input_drive") || + !strcmp(cmd, ".max_input_load") || !strcmp(cmd, ".default_max_input_load") || !strcmp(cmd, ".output_load") || + !strcmp(cmd, ".default_output_load")) + { + log_warning("Blif delay constraints (%s) are not supported.", cmd); + continue; + } + if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) { char *p; diff --git a/yosys/frontends/verific/verific.cc b/yosys/frontends/verific/verific.cc index b0d789d8fa3..dff9c777b84 100644 --- a/yosys/frontends/verific/verific.cc +++ b/yosys/frontends/verific/verific.cc @@ -52,6 +52,7 @@ USING_YOSYS_NAMESPACE #ifdef VERIFIC_VHDL_SUPPORT #include "vhdl_file.h" #include "VhdlUnits.h" +#include "NameSpace.h" #endif #ifdef VERIFIC_EDIF_SUPPORT @@ -74,7 +75,7 @@ USING_YOSYS_NAMESPACE # error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific." #endif -#if YOSYSHQ_VERIFIC_API_VERSION < 20210801 +#if YOSYSHQ_VERIFIC_API_VERSION < 20230901 # error "Please update your version of YosysHQ flavored Verific." #endif @@ -114,7 +115,9 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile), full_message.c_str()); + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, + linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str()); } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); @@ -125,7 +128,7 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil verific_error_msg = message; } -void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)) +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)) { Message::SetConsoleOutput(0); Message::RegisterCallBackMsg(msg_func); @@ -251,13 +254,24 @@ static const RTLIL::Const verific_const(const char *value, bool allow_string = t return c; } +static const std::string verific_unescape(const char *value) +{ + std::string val = std::string(value); + if (val.size()>1 && val[0]=='\"' && val.back()=='\"') + return val.substr(1,val.size()-2); + return value; +} + void VerificImporter::import_attributes(dict &attributes, DesignObj *obj, Netlist *nl) { + if (!obj) + return; + MapIter mi; Att *attr; if (obj->Linefile()) - attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); + attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); FOREACH_ATTRIBUTE(obj, mi, attr) { if (attr->Key()[0] == ' ' || attr->Value() == nullptr) @@ -329,36 +343,46 @@ void VerificImporter::import_attributes(dict &att } } +RTLIL::SigBit VerificImporter::netToSigBit(Verific::Net *net) { + if (net && net->IsGnd()) + return RTLIL::State::S0; + else if (net && net->IsPwr()) + return RTLIL::State::S1; + else if (net && net->IsX()) + return RTLIL::State::Sx; + else if (net) + return net_map_at(net); + else + return RTLIL::State::Sz; +} + RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst) { RTLIL::SigSpec sig; - for (int i = int(inst->InputSize())-1; i >= 0; i--) - if (inst->GetInputBit(i)) - sig.append(net_map_at(inst->GetInputBit(i))); - else - sig.append(RTLIL::State::Sz); + for (int i = int(inst->InputSize())-1; i >= 0; i--) { + Net *net = inst->GetInputBit(i); + sig.append(netToSigBit(net)); + } return sig; } RTLIL::SigSpec VerificImporter::operatorInput1(Instance *inst) { RTLIL::SigSpec sig; - for (int i = int(inst->Input1Size())-1; i >= 0; i--) - if (inst->GetInput1Bit(i)) - sig.append(net_map_at(inst->GetInput1Bit(i))); - else - sig.append(RTLIL::State::Sz); + for (int i = int(inst->Input1Size())-1; i >= 0; i--) { + Net *net = inst->GetInput1Bit(i); + sig.append(netToSigBit(net)); + } return sig; } RTLIL::SigSpec VerificImporter::operatorInput2(Instance *inst) { RTLIL::SigSpec sig; - for (int i = int(inst->Input2Size())-1; i >= 0; i--) - if (inst->GetInput2Bit(i)) - sig.append(net_map_at(inst->GetInput2Bit(i))); - else - sig.append(RTLIL::State::Sz); + for (int i = int(inst->Input2Size())-1; i >= 0; i--) { + Net *net = inst->GetInput2Bit(i); + sig.append(netToSigBit(net)); + } return sig; } @@ -1103,6 +1127,43 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == OPER_YOSYSHQ_SET_TAG) + { + RTLIL::SigSpec sig_expr = operatorInport(inst, "expr"); + RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask"); + RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask"); + RTLIL::SigSpec sig_o = operatorOutput(inst); + std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : ""; + module->connect(sig_o, module->SetTag(new_verific_id(inst), tag, sig_expr, sig_set_mask, sig_clr_mask)); + return true; + } + if (inst->Type() == OPER_YOSYSHQ_GET_TAG) + { + std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : ""; + module->connect(operatorOutput(inst),module->GetTag(new_verific_id(inst), tag, operatorInput(inst))); + return true; + } + if (inst->Type() == OPER_YOSYSHQ_OVERWRITE_TAG) + { + RTLIL::SigSpec sig_signal = operatorInport(inst, "signal"); + RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask"); + RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask"); + std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : ""; + module->addOverwriteTag(new_verific_id(inst), tag, sig_signal, sig_set_mask, sig_clr_mask); + return true; + } + if (inst->Type() == OPER_YOSYSHQ_ORIGINAL_TAG) + { + std::string tag = inst->GetAtt("tag") ? verific_unescape(inst->GetAttValue("tag")) : ""; + module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst))); + return true; + } + if (inst->Type() == OPER_YOSYSHQ_FUTURE_FF) + { + module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst))); + return true; + } + #undef IN #undef IN1 #undef IN2 @@ -1230,9 +1291,24 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma log("Importing module %s.\n", RTLIL::id2cstr(module->name)); } import_attributes(module->attributes, nl, nl); + module->set_string_attribute(ID::hdlname, nl->CellBaseName()); +#ifdef VERIFIC_VHDL_SUPPORT + if (nl->IsFromVhdl()) { + NameSpace name_space(0); + char *architecture_name = name_space.ReName(nl->Name()) ; + module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name()); + } +#endif + const char *param_name ; + const char *param_value ; + MapIter mi; + FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) { + module->avail_parameters(RTLIL::escape_id(param_name)); + module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value); + } SetIter si; - MapIter mi, mi2; + MapIter mi2; Port *port; PortBus *portbus; Net *net; @@ -1284,7 +1360,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl); - + SetIter si ; + Port *port ; + FOREACH_PORT_OF_PORTBUS(portbus, si, port) { + import_attributes(wire->attributes, port->GetNet(), nl); + break; + } bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; if (portbus_input) wire->port_input = true; @@ -2039,7 +2120,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a if (sva_at_only) do { Instance *inst_mux = net->Driver(); - if (inst_mux->Type() != PRIM_MUX) + if (inst_mux == nullptr || inst_mux->Type() != PRIM_MUX) break; bool pwr1 = inst_mux->GetInput1()->IsPwr(); @@ -2443,51 +2524,71 @@ std::string verific_import(Design *design, const std::mapGetModule(top.c_str(), 1); - if (veri_module) { - veri_modules.InsertLast(veri_module); - if (veri_module->IsConfiguration()) { - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); - VeriLibrary *lib = veri_module->GetLibrary() ; - if (module_name && module_name->IsHierName()) { - VeriName *prefix = module_name->GetPrefix() ; - const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) +#endif + { + Array veri_modules, vhdl_units; + + if (veri_lib) { + VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); + if (veri_module) { + veri_modules.InsertLast(veri_module); + if (veri_module->IsConfiguration()) { + VeriConfiguration *cfg = (VeriConfiguration*)veri_module; + VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); + VeriLibrary *lib = veri_module->GetLibrary() ; + if (module_name && module_name->IsHierName()) { + VeriName *prefix = module_name->GetPrefix() ; + const char *lib_name = (prefix) ? prefix->GetName() : 0 ; + if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + } + if (lib && module_name) + top = lib->GetModule(module_name->GetName(), 1)->GetName(); } - if (lib && module_name) - top = lib->GetModule(module_name->GetName(), 1)->GetName(); } - } - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (!static_elaborate) +#endif + { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } + } } - } #ifdef VERIFIC_VHDL_SUPPORT - if (vhdl_lib) { - VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); - if (vhdl_unit) - vhdl_units.InsertLast(vhdl_unit); - } + if (vhdl_lib) { + VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); + if (vhdl_unit) + vhdl_units.InsertLast(vhdl_unit); + } +#endif + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (static_elaborate) { + VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params); + verific_error_msg.clear(); + continue; + } #endif - netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); + + netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); + } } Netlist *nl; @@ -2500,7 +2601,7 @@ std::string verific_import(Design *design, const std::mapAddAtt(new Att(" \\top", NULL)); nl_todo.emplace(nl->CellBaseName(), nl); - cell_name = nl->Owner()->Name(); + cell_name = nl->CellBaseName(); } if (top.empty()) cell_name = top; @@ -2522,7 +2623,7 @@ std::string verific_import(Design *design, const std::mapfirst) == 0) { VerificImporter importer(false, false, false, false, false, false, false); nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name); + importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name); } nl_todo.erase(it); } @@ -2724,6 +2825,9 @@ struct VerificPass : public Pass { log(" -extnets\n"); log(" Resolve references to external nets by adding module ports as needed.\n"); log("\n"); + log(" -no-split-complex-ports\n"); + log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n"); + log("\n"); log(" -autocover\n"); log(" Generate automatic cover statements for all asserts\n"); log("\n"); @@ -2951,6 +3055,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("db_infer_wide_operators", 1); RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); + // Properly respect order of read and write for rams + RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1); + RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); @@ -3008,6 +3115,7 @@ struct VerificPass : public Pass { int argidx = 1; std::string work = "work"; bool is_work_set = false; + (void)is_work_set; veri_file::RegisterCallBackVerificStream(&verific_read_cb); if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || @@ -3085,7 +3193,20 @@ struct VerificPass : public Pass { } veri_file::RemoveAllLOptions(); - veri_file::AddLOption("work"); + for (int i = argidx; i < GetSize(args); i++) + { + if (args[i] == "-work" && i+1 < GetSize(args)) { + work = args[++i]; + is_work_set = true; + continue; + } + if (args[i] == "-L" && i+1 < GetSize(args)) { + ++i; + continue; + } + break; + } + veri_file::AddLOption(work.c_str()); for (int i = argidx; i < GetSize(args); i++) { if (args[i] == "-work" && i+1 < GetSize(args)) { @@ -3093,7 +3214,7 @@ struct VerificPass : public Pass { continue; } if (args[i] == "-L" && i+1 < GetSize(args)) { - if (args[++i] == "work") + if (args[++i] == work) veri_file::RemoveAllLOptions(); continue; } @@ -3440,6 +3561,7 @@ struct VerificPass : public Pass { bool mode_nosva = false, mode_names = false, mode_verific = false; bool mode_autocover = false, mode_fullinit = false; bool flatten = false, extnets = false, mode_cells = false; + bool split_complex_ports = true; string dumpfile; string ppfile; Map parameters(STRING_HASH); @@ -3457,6 +3579,10 @@ struct VerificPass : public Pass { flatten = true; continue; } + if (args[argidx] == "-no-split-complex-ports") { + split_complex_ports = false; + continue; + } if (args[argidx] == "-extnets") { extnets = true; continue; @@ -3526,15 +3652,16 @@ struct VerificPass : public Pass { std::set top_mod_names; + if (mode_all) + { + #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - VerificExtensions::ElaborateAndRewrite(work, ¶meters); - verific_error_msg.clear(); + VerificExtensions::ElaborateAndRewrite(work, ¶meters); + verific_error_msg.clear(); #endif - if (!ppfile.empty()) - veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - if (mode_all) - { log("Running hier_tree::ElaborateAll().\n"); VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); @@ -3559,67 +3686,93 @@ struct VerificPass : public Pass { if (argidx == GetSize(args)) cmd_error(args, argidx, "No top module specified.\n"); - VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); + Array *netlists = nullptr; + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) +#endif + { + + VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); #ifdef VERIFIC_VHDL_SUPPORT - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); #endif - Array veri_modules, vhdl_units; - for (; argidx < GetSize(args); argidx++) - { - const char *name = args[argidx].c_str(); - top_mod_names.insert(name); - - VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; - if (veri_module) { - if (veri_module->IsConfiguration()) { - log("Adding Verilog configuration '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); - - top_mod_names.erase(name); - - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name; - int i; - FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { - VeriLibrary *lib = veri_module->GetLibrary() ; - if (module_name && module_name->IsHierName()) { - VeriName *prefix = module_name->GetPrefix() ; - const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + Array veri_modules, vhdl_units; + for (int i = argidx; i < GetSize(args); i++) + { + const char *name = args[i].c_str(); + top_mod_names.insert(name); + + VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; + if (veri_module) { + if (veri_module->IsConfiguration()) { + log("Adding Verilog configuration '%s' to elaboration queue.\n", name); + veri_modules.InsertLast(veri_module); + + top_mod_names.erase(name); + + VeriConfiguration *cfg = (VeriConfiguration*)veri_module; + VeriName *module_name; + int i; + FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { + VeriLibrary *lib = veri_module->GetLibrary() ; + if (module_name && module_name->IsHierName()) { + VeriName *prefix = module_name->GetPrefix() ; + const char *lib_name = (prefix) ? prefix->GetName() : 0 ; + if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; + } + if (lib && module_name) + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } - if (lib && module_name) - top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); + } else { + log("Adding Verilog module '%s' to elaboration queue.\n", name); + veri_modules.InsertLast(veri_module); } - } else { - log("Adding Verilog module '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); + continue; } - continue; - } #ifdef VERIFIC_VHDL_SUPPORT - VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; - if (vhdl_unit) { - log("Adding VHDL unit '%s' to elaboration queue.\n", name); - vhdl_units.InsertLast(vhdl_unit); - continue; + VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; + if (vhdl_unit) { + log("Adding VHDL unit '%s' to elaboration queue.\n", name); + vhdl_units.InsertLast(vhdl_unit); + continue; + } +#endif + log_error("Can't find module/unit '%s'.\n", name); } + +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (static_elaborate) { + VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, ¶meters); + verific_error_msg.clear(); #endif - log_error("Can't find module/unit '%s'.\n", name); - } + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - if (veri_lib) { - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - VeriModule *veri_module; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + continue; } +#endif + const char *lib_name = nullptr; + SetIter si; + FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { + VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); + if (veri_lib) { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + VeriModule *veri_module; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } + } + } + + log("Running hier_tree::Elaborate().\n"); + netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); } - log("Running hier_tree::Elaborate().\n"); - Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); Netlist *nl; int i; @@ -3669,8 +3822,10 @@ struct VerificPass : public Pass { worker.run(nl.second); } - for (auto nl : nl_todo) - nl.second->ChangePortBusStructures(1 /* hierarchical */); + if (split_complex_ports) { + for (auto nl : nl_todo) + nl.second->ChangePortBusStructures(1 /* hierarchical */); + } if (!dumpfile.empty()) { VeriWrite veri_writer; @@ -3684,7 +3839,7 @@ struct VerificPass : public Pass { VerificImporter importer(mode_gates, mode_keep, mode_nosva, mode_names, mode_verific, mode_autocover, mode_fullinit); nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name())); + importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName())); } nl_todo.erase(it); } diff --git a/yosys/frontends/verific/verific.h b/yosys/frontends/verific/verific.h index 44485751c7e..0b9616e1944 100644 --- a/yosys/frontends/verific/verific.h +++ b/yosys/frontends/verific/verific.h @@ -83,6 +83,7 @@ struct VerificImporter RTLIL::IdString new_verific_id(Verific::DesignObj *obj); void import_attributes(dict &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr); + RTLIL::SigBit netToSigBit(Verific::Net *net); RTLIL::SigSpec operatorInput(Verific::Instance *inst); RTLIL::SigSpec operatorInput1(Verific::Instance *inst); RTLIL::SigSpec operatorInput2(Verific::Instance *inst); diff --git a/yosys/frontends/verilog/verilog_frontend.cc b/yosys/frontends/verilog/verilog_frontend.cc index 9b277c6b977..5c59fe3afac 100644 --- a/yosys/frontends/verilog/verilog_frontend.cc +++ b/yosys/frontends/verilog/verilog_frontend.cc @@ -100,6 +100,10 @@ struct VerilogFrontend : public Frontend { log(" -assert-assumes\n"); log(" treat all assume() statements like assert() statements\n"); log("\n"); + log(" -nodisplay\n"); + log(" suppress output from display system tasks ($display et. al).\n"); + log(" This does not affect the output from a later 'sim' command.\n"); + log("\n"); log(" -debug\n"); log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n"); log("\n"); @@ -235,6 +239,7 @@ struct VerilogFrontend : public Frontend { } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { + bool flag_nodisplay = false; bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; bool flag_no_dump_ptr = false; @@ -308,6 +313,10 @@ struct VerilogFrontend : public Frontend { assert_assumes_mode = true; continue; } + if (arg == "-nodisplay") { + flag_nodisplay = true; + continue; + } if (arg == "-debug") { flag_dump_ast1 = true; flag_dump_ast2 = true; @@ -510,7 +519,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, + AST::process(design, current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); diff --git a/yosys/frontends/verilog/verilog_lexer.l b/yosys/frontends/verilog/verilog_lexer.l index 24998666828..8a37343022f 100644 --- a/yosys/frontends/verilog/verilog_lexer.l +++ b/yosys/frontends/verilog/verilog_lexer.l @@ -386,7 +386,7 @@ and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { supply0 { return TOK_SUPPLY0; } supply1 { return TOK_SUPPLY1; } -"$"(display|write|strobe|monitor|time|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) { +"$"(display[bho]?|write[bho]?|strobe|monitor|time|realtime|stop|finish|dumpfile|dumpvars|dumpon|dumpoff|dumpall) { yylval->string = new std::string(yytext); return TOK_ID; } diff --git a/yosys/frontends/verilog/verilog_parser.y b/yosys/frontends/verilog/verilog_parser.y index 98bdbf9e5c5..039e83491e7 100644 --- a/yosys/frontends/verilog/verilog_parser.y +++ b/yosys/frontends/verilog/verilog_parser.y @@ -292,6 +292,65 @@ static void rewriteGenForDeclInit(AstNode *loop) substitute(incr); } +static void ensureAsgnExprAllowed() +{ + if (!sv_mode) + frontend_verilog_yyerror("Assignments within expressions are only supported in SystemVerilog mode."); + if (ast_stack.back()->type != AST_BLOCK) + frontend_verilog_yyerror("Assignments within expressions are only permitted within procedures."); +} + +// add a pre/post-increment/decrement statement +static const AstNode *addIncOrDecStmt(dict *stmt_attr, AstNode *lhs, + dict *op_attr, AST::AstNodeType op, + YYLTYPE begin, YYLTYPE end) +{ + AstNode *one = AstNode::mkconst_int(1, true); + AstNode *rhs = new AstNode(op, lhs->clone(), one); + if (op_attr != nullptr) + append_attr(rhs, op_attr); + AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); + SET_AST_NODE_LOC(stmt, begin, end); + if (stmt_attr != nullptr) + append_attr(stmt, stmt_attr); + ast_stack.back()->children.push_back(stmt); + return stmt; +} + +// create a pre/post-increment/decrement expression, and add the corresponding statement +static AstNode *addIncOrDecExpr(AstNode *lhs, dict *attr, AST::AstNodeType op, YYLTYPE begin, YYLTYPE end, bool undo) +{ + ensureAsgnExprAllowed(); + const AstNode *stmt = addIncOrDecStmt(nullptr, lhs, attr, op, begin, end); + log_assert(stmt->type == AST_ASSIGN_EQ); + AstNode *expr = stmt->children[0]->clone(); + if (undo) { + AstNode *minus_one = AstNode::mkconst_int(-1, true, 1); + expr = new AstNode(op, expr, minus_one); + } + SET_AST_NODE_LOC(expr, begin, end); + return expr; +} + +// add a binary operator assignment statement, e.g., a += b +static const AstNode *addAsgnBinopStmt(dict *attr, AstNode *lhs, AST::AstNodeType op, AstNode *rhs, YYLTYPE begin, YYLTYPE end) +{ + SET_AST_NODE_LOC(rhs, end, end); + if (op == AST_SHIFT_LEFT || op == AST_SHIFT_RIGHT || + op == AST_SHIFT_SLEFT || op == AST_SHIFT_SRIGHT) { + rhs = new AstNode(AST_TO_UNSIGNED, rhs); + SET_AST_NODE_LOC(rhs, end, end); + } + rhs = new AstNode(op, lhs->clone(), rhs); + AstNode *stmt = new AstNode(AST_ASSIGN_EQ, lhs, rhs); + SET_AST_NODE_LOC(rhs, begin, end); + SET_AST_NODE_LOC(stmt, begin, end); + ast_stack.back()->children.push_back(stmt); + if (attr != nullptr) + append_attr(stmt, attr); + return lhs; +} + %} %define api.prefix {frontend_verilog_yy} @@ -358,7 +417,7 @@ static void rewriteGenForDeclInit(AstNode *loop) %type integer_atom_type integer_vector_type %type attr case_attr %type struct_union -%type asgn_binop +%type asgn_binop inc_or_dec_op %type genvar_identifier %type specify_target @@ -1830,7 +1889,7 @@ struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_toke ; member_type_token: - member_type + member_type | hierarchical_type_id { addWiretypeNode($1, astbuf1); } @@ -2425,7 +2484,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5); - SET_AST_NODE_LOC(node, @1, @6); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2438,7 +2497,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5); - SET_AST_NODE_LOC(node, @1, @6); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2451,7 +2510,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6); - SET_AST_NODE_LOC(node, @1, @7); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2464,7 +2523,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6); - SET_AST_NODE_LOC(node, @1, @7); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2474,7 +2533,7 @@ assert: } | opt_sva_label TOK_COVER opt_property '(' expr ')' ';' { AstNode *node = new AstNode(AST_COVER, $5); - SET_AST_NODE_LOC(node, @1, @6); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2483,7 +2542,7 @@ assert: } | opt_sva_label TOK_COVER opt_property '(' ')' ';' { AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false)); - SET_AST_NODE_LOC(node, @1, @5); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @5); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2492,7 +2551,7 @@ assert: } | opt_sva_label TOK_COVER ';' { AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false)); - SET_AST_NODE_LOC(node, @1, @2); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @2); if ($1 != nullptr) { node->str = *$1; delete $1; @@ -2504,7 +2563,7 @@ assert: delete $5; } else { AstNode *node = new AstNode(AST_ASSUME, $5); - SET_AST_NODE_LOC(node, @1, @6); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2519,7 +2578,7 @@ assert: delete $6; } else { AstNode *node = new AstNode(AST_FAIR, $6); - SET_AST_NODE_LOC(node, @1, @7); + SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7); if ($1 != nullptr) node->str = *$1; ast_stack.back()->children.push_back(node); @@ -2610,17 +2669,11 @@ simple_behavioral_stmt: SET_AST_NODE_LOC(node, @2, @5); append_attr(node, $1); } | - attr lvalue TOK_INCREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true))); - ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @2, @3); - append_attr(node, $1); + attr lvalue attr inc_or_dec_op { + addIncOrDecStmt($1, $2, $3, $4, @1, @4); } | - attr lvalue TOK_DECREMENT { - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true))); - ast_stack.back()->children.push_back(node); - SET_AST_NODE_LOC(node, @2, @3); - append_attr(node, $1); + attr inc_or_dec_op attr lvalue { + addIncOrDecStmt($1, $4, $3, $2, @1, @4); } | attr lvalue OP_LE delay expr { AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5); @@ -2629,18 +2682,7 @@ simple_behavioral_stmt: append_attr(node, $1); } | attr lvalue asgn_binop delay expr { - AstNode *expr_node = $5; - if ($3 == AST_SHIFT_LEFT || $3 == AST_SHIFT_RIGHT || - $3 == AST_SHIFT_SLEFT || $3 == AST_SHIFT_SRIGHT) { - expr_node = new AstNode(AST_TO_UNSIGNED, expr_node); - SET_AST_NODE_LOC(expr_node, @5, @5); - } - AstNode *op_node = new AstNode($3, $2->clone(), expr_node); - AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, op_node); - SET_AST_NODE_LOC(op_node, @2, @5); - SET_AST_NODE_LOC(node, @2, @5); - ast_stack.back()->children.push_back(node); - append_attr(node, $1); + addAsgnBinopStmt($1, $2, $3, $5, @2, @5); }; asgn_binop: @@ -2657,6 +2699,12 @@ asgn_binop: TOK_SSHL_ASSIGN { $$ = AST_SHIFT_SLEFT; } | TOK_SSHR_ASSIGN { $$ = AST_SHIFT_SRIGHT; } ; +inc_or_dec_op: + // NOTE: These should only be permitted in SV mode, but Yosys has + // allowed them in all modes since support for them was added in 2017. + TOK_INCREMENT { $$ = AST_ADD; } | + TOK_DECREMENT { $$ = AST_SUB; } ; + for_initialization: TOK_ID '=' expr { AstNode *ident = new AstNode(AST_IDENTIFIER); @@ -2721,6 +2769,7 @@ behavioral_stmt: ast_stack.push_back(node); append_attr(node, $1); } opt_arg_list ';'{ + SET_AST_NODE_LOC(ast_stack.back(), @2, @5); ast_stack.pop_back(); } | attr TOK_MSG_TASKS { @@ -2731,6 +2780,7 @@ behavioral_stmt: ast_stack.push_back(node); append_attr(node, $1); } opt_arg_list ';'{ + SET_AST_NODE_LOC(ast_stack.back(), @2, @5); ast_stack.pop_back(); } | attr TOK_BEGIN { @@ -3147,6 +3197,14 @@ expr: $$->children.push_back($6); SET_AST_NODE_LOC($$, @1, @$); append_attr($$, $3); + } | + inc_or_dec_op attr rvalue { + $$ = addIncOrDecExpr($3, $2, $1, @1, @3, false); + } | + // TODO: Attributes are allowed in the middle here, but they create some + // non-trivial conflicts that don't seem worth solving for now. + rvalue inc_or_dec_op { + $$ = addIncOrDecExpr($1, nullptr, $2, @1, @2, true); }; basic_expr: @@ -3434,6 +3492,17 @@ basic_expr: frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode."); $$ = new AstNode(AST_CAST_SIZE, $1, $4); SET_AST_NODE_LOC($$, @1, @4); + } | + '(' expr '=' expr ')' { + ensureAsgnExprAllowed(); + AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $4); + ast_stack.back()->children.push_back(node); + SET_AST_NODE_LOC(node, @2, @4); + $$ = $2->clone(); + } | + '(' expr asgn_binop expr ')' { + ensureAsgnExprAllowed(); + $$ = addAsgnBinopStmt(nullptr, $2, $3, $4, @2, @4)-> clone(); }; concat_list: diff --git a/yosys/kernel/cellaigs.cc b/yosys/kernel/cellaigs.cc index 332f821b76c..5dda4503fdd 100644 --- a/yosys/kernel/cellaigs.cc +++ b/yosys/kernel/cellaigs.cc @@ -385,17 +385,17 @@ Aig::Aig(Cell *cell) goto optimize; } - if (cell->type.in({ID($lt), ID($gt), ID($le), ID($ge)})) + if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) { int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))) + 1; vector A = mk.inport_vec(ID::A, width); vector B = mk.inport_vec(ID::B, width); - if (cell->type.in({ID($gt), ID($ge)})) + if (cell->type.in(ID($gt), ID($ge))) std::swap(A, B); - int carry = mk.bool_node(!cell->type.in({ID($le), ID($ge)})); + int carry = mk.bool_node(!cell->type.in(ID($le), ID($ge))); for (auto &n : B) n = mk.not_gate(n); vector Y = mk.adder(A, B, carry); diff --git a/yosys/kernel/celltypes.h b/yosys/kernel/celltypes.h index 63e7408c142..77cb3e324c2 100644 --- a/yosys/kernel/celltypes.h +++ b/yosys/kernel/celltypes.h @@ -101,6 +101,13 @@ struct CellTypes setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool(), true); setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool(), true); setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool(), true); + setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool()); + setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool()); + setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y}); + setup_type(ID($get_tag), {ID::A}, {ID::Y}); + setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool()); + setup_type(ID($original_tag), {ID::A}, {ID::Y}); + setup_type(ID($future_ff), {ID::A}, {ID::Y}); } void setup_internals_eval() diff --git a/yosys/kernel/constids.inc b/yosys/kernel/constids.inc index 39211d0c753..7db21debb0e 100644 --- a/yosys/kernel/constids.inc +++ b/yosys/kernel/constids.inc @@ -22,6 +22,8 @@ X(always_ff) X(always_latch) X(anyconst) X(anyseq) +X(ARGS) +X(ARGS_WIDTH) X(ARST) X(ARST_POLARITY) X(ARST_VALUE) @@ -86,6 +88,8 @@ X(equiv_merged) X(equiv_region) X(extract_order) X(F) +X(FLAVOR) +X(FORMAT) X(force_downto) X(force_upto) X(fsm_encoding) @@ -137,6 +141,7 @@ X(nomem2reg) X(nomeminit) X(nosync) X(nowrshmsk) +X(no_ram) X(no_rw_check) X(O) X(OFFSET) @@ -205,6 +210,7 @@ X(syn_romstyle) X(S_WIDTH) X(T) X(TABLE) +X(TAG) X(techmap_autopurge) X(_TECHMAP_BITS_CONNMAP_) X(_TECHMAP_CELLNAME_) @@ -233,6 +239,10 @@ X(TRANS_NUM) X(TRANSPARENCY_MASK) X(TRANSPARENT) X(TRANS_TABLE) +X(TRG) +X(TRG_ENABLE) +X(TRG_POLARITY) +X(TRG_WIDTH) X(T_RISE_MAX) X(T_RISE_MIN) X(T_RISE_TYP) diff --git a/yosys/kernel/driver.cc b/yosys/kernel/driver.cc index ef8e7792473..8d9ecc91adc 100644 --- a/yosys/kernel/driver.cc +++ b/yosys/kernel/driver.cc @@ -51,40 +51,51 @@ #if !defined(_WIN32) || defined(__MINGW32__) # include -#else +#endif + +USING_YOSYS_NAMESPACE + char *optarg; -int optind = 1, optcur = 1; +int optind = 1, optcur = 1, optopt = 0; int getopt(int argc, char **argv, const char *optstring) { - if (optind >= argc || argv[optind][0] != '-') + if (optind >= argc) return -1; + if (argv[optind][0] != '-' || argv[optind][1] == 0) { + optopt = 1; + optarg = argv[optind++]; + return optopt; + } + bool takes_arg = false; - int opt = argv[optind][optcur]; + optopt = argv[optind][optcur]; + + if (optopt == '-') { + ++optind; + return -1; + } + for (int i = 0; optstring[i]; i++) - if (opt == optstring[i] && optstring[i + 1] == ':') + if (optopt == optstring[i] && optstring[i + 1] == ':') takes_arg = true; if (!takes_arg) { if (argv[optind][++optcur] == 0) optind++, optcur = 1; - return opt; + return optopt; } if (argv[optind][++optcur]) { optarg = argv[optind++] + optcur; optcur = 1; - return opt; + return optopt; } optarg = argv[++optind]; optind++, optcur = 1; - return opt; + return optopt; } -#endif - - -USING_YOSYS_NAMESPACE #ifdef EMSCRIPTEN # include @@ -215,6 +226,7 @@ int main(int argc, char **argv) std::string backend_command = "auto"; std::vector vlog_defines; std::vector passes_commands; + std::vector frontend_files; std::vector plugin_filenames; std::string output_filename = ""; std::string scriptfile = ""; @@ -231,14 +243,6 @@ int main(int argc, char **argv) bool mode_v = false; bool mode_q = false; -#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) - if (getenv("HOME") != NULL) { - yosys_history_file = stringf("%s/.yosys_history", getenv("HOME")); - read_history(yosys_history_file.c_str()); - yosys_history_offset = where_history(); - } -#endif - if (argc == 2 && (!strcmp(argv[1], "-h") || !strcmp(argv[1], "-help") || !strcmp(argv[1], "--help"))) { printf("\n"); @@ -509,6 +513,9 @@ int main(int argc, char **argv) case 'C': run_tcl_shell = true; break; + case '\001': + frontend_files.push_back(optarg); + break; default: fprintf(stderr, "Run '%s -h' for help.\n", argv[0]); exit(1); @@ -523,6 +530,36 @@ int main(int argc, char **argv) if (print_banner) yosys_banner(); +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + std::string state_dir; + #if defined(_WIN32) + if (getenv("HOMEDRIVE") != NULL && getenv("HOMEPATH") != NULL) { + state_dir = stringf("%s%s/.local/state", getenv("HOMEDRIVE"), getenv("HOMEPATH")); + } else { + log_debug("$HOMEDRIVE and/or $HOMEPATH is empty. No history file will be created.\n"); + } + #else + if (getenv("XDG_STATE_HOME") == NULL || getenv("XDG_STATE_HOME")[0] == '\0') { + if (getenv("HOME") != NULL) { + state_dir = stringf("%s/.local/state", getenv("HOME")); + } else { + log_debug("$HOME is empty. No history file will be created.\n"); + } + } else { + state_dir = stringf("%s", getenv("XDG_STATE_HOME")); + } + #endif + + if (!state_dir.empty()) { + std::string yosys_dir = state_dir + "/yosys"; + create_directory(yosys_dir); + + yosys_history_file = yosys_dir + "/history"; + read_history(yosys_history_file.c_str()); + yosys_history_offset = where_history(); + } +#endif + if (print_stats) log_hasher = new SHA1; @@ -554,6 +591,8 @@ int main(int argc, char **argv) for (auto &fn : plugin_filenames) load_plugin(fn, {}); + log_suppressed(); + if (!vlog_defines.empty()) { std::string vdef_cmd = "read -define"; for (auto vdef : vlog_defines) @@ -561,17 +600,33 @@ int main(int argc, char **argv) run_pass(vdef_cmd); } - while (optind < argc) - if (run_frontend(argv[optind++], frontend_command)) + if (scriptfile.empty() || !scriptfile_tcl) { + // Without a TCL script, arguments following '--' are also treated as frontend files + for (int i = optind; i < argc; ++i) + frontend_files.push_back(argv[i]); + } + + for (auto it = frontend_files.begin(); it != frontend_files.end(); ++it) { + if (run_frontend((*it).c_str(), frontend_command)) run_shell = false; + } if (!topmodule.empty()) run_pass("hierarchy -top " + topmodule); - if (!scriptfile.empty()) { if (scriptfile_tcl) { #ifdef YOSYS_ENABLE_TCL - if (Tcl_EvalFile(yosys_get_tcl_interp(), scriptfile.c_str()) != TCL_OK) + int tcl_argc = argc - optind; + std::vector script_args; + Tcl_Interp *interp = yosys_get_tcl_interp(); + for (int i = optind; i < argc; ++i) + script_args.push_back(Tcl_NewStringObj(argv[i], strlen(argv[i]))); + + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argc", 4), NULL, Tcl_NewIntObj(tcl_argc), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv", 4), NULL, Tcl_NewListObj(tcl_argc, script_args.data()), 0); + Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv0", 5), NULL, Tcl_NewStringObj(scriptfile.c_str(), scriptfile.length()), 0); + + if (Tcl_EvalFile(interp, scriptfile.c_str()) != TCL_OK) log_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp())); #else log_error("Can't exectue TCL script: this version of yosys is not built with TCL support enabled.\n"); diff --git a/yosys/kernel/fmt.cc b/yosys/kernel/fmt.cc new file mode 100644 index 00000000000..18eb7cb7193 --- /dev/null +++ b/yosys/kernel/fmt.cc @@ -0,0 +1,746 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "libs/bigint/BigUnsigned.hh" +#include "kernel/fmt.h" + +USING_YOSYS_NAMESPACE + +void Fmt::append_string(const std::string &str) { + FmtPart part = {}; + part.type = FmtPart::STRING; + part.str = str; + parts.push_back(part); +} + +void Fmt::parse_rtlil(const RTLIL::Cell *cell) { + std::string fmt = cell->getParam(ID(FORMAT)).decode_string(); + RTLIL::SigSpec args = cell->getPort(ID(ARGS)); + parts.clear(); + + FmtPart part; + for (size_t i = 0; i < fmt.size(); i++) { + if (fmt.substr(i, 2) == "}}") { + part.str += '}'; + ++i; + } else if (fmt.substr(i, 2) == "{{") { + part.str += '{'; + ++i; + } else if (fmt[i] == '}') + log_assert(false && "Unexpected '}' in format string"); + else if (fmt[i] == '{') { + if (!part.str.empty()) { + part.type = FmtPart::STRING; + parts.push_back(part); + part = {}; + } + + if (++i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + + size_t arg_size = 0; + for (; i < fmt.size(); i++) { + if (fmt[i] >= '0' && fmt[i] <= '9') { + arg_size *= 10; + arg_size += fmt[i] - '0'; + } else if (fmt[i] == ':') { + ++i; + break; + } else { + log_assert(false && "Unexpected character in format substitution"); + } + } + if (i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + + if ((size_t)args.size() < arg_size) + log_assert(false && "Format part overruns arguments"); + part.sig = args.extract(0, arg_size); + args.remove(0, arg_size); + + if (fmt[i] == '>') + part.justify = FmtPart::RIGHT; + else if (fmt[i] == '<') + part.justify = FmtPart::LEFT; + else + log_assert(false && "Unexpected justification in format substitution"); + if (++i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + + if (fmt[i] == '0' || fmt[i] == ' ') + part.padding = fmt[i]; + else + log_assert(false && "Unexpected padding in format substitution"); + if (++i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + + for (; i < fmt.size(); i++) { + if (fmt[i] >= '0' && fmt[i] <= '9') { + part.width *= 10; + part.width += fmt[i] - '0'; + continue; + } else if (fmt[i] == 'b') { + part.type = FmtPart::INTEGER; + part.base = 2; + } else if (fmt[i] == 'o') { + part.type = FmtPart::INTEGER; + part.base = 8; + } else if (fmt[i] == 'd') { + part.type = FmtPart::INTEGER; + part.base = 10; + } else if (fmt[i] == 'h') { + part.type = FmtPart::INTEGER; + part.base = 16; + } else if (fmt[i] == 'c') { + part.type = FmtPart::CHARACTER; + } else if (fmt[i] == 't') { + part.type = FmtPart::VLOG_TIME; + } else if (fmt[i] == 'r') { + part.type = FmtPart::VLOG_TIME; + part.realtime = true; + } else { + log_assert(false && "Unexpected character in format substitution"); + } + ++i; + break; + } + if (i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + + if (part.type == FmtPart::INTEGER) { + if (fmt[i] == '+') { + part.plus = true; + if (++i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + } + + if (fmt[i] == 'u') + part.signed_ = false; + else if (fmt[i] == 's') + part.signed_ = true; + else + log_assert(false && "Unexpected character in format substitution"); + if (++i == fmt.size()) + log_assert(false && "Unexpected end in format substitution"); + } + + if (fmt[i] != '}') + log_assert(false && "Expected '}' after format substitution"); + + parts.push_back(part); + part = {}; + } else { + part.str += fmt[i]; + } + } + if (!part.str.empty()) { + part.type = FmtPart::STRING; + parts.push_back(part); + } +} + +void Fmt::emit_rtlil(RTLIL::Cell *cell) const { + std::string fmt; + RTLIL::SigSpec args; + + for (auto &part : parts) { + switch (part.type) { + case FmtPart::STRING: + for (char c : part.str) { + if (c == '{') + fmt += "{{"; + else if (c == '}') + fmt += "}}"; + else + fmt += c; + } + break; + + case FmtPart::VLOG_TIME: + log_assert(part.sig.size() == 0); + YS_FALLTHROUGH + case FmtPart::CHARACTER: + log_assert(part.sig.size() % 8 == 0); + YS_FALLTHROUGH + case FmtPart::INTEGER: + args.append(part.sig); + fmt += '{'; + fmt += std::to_string(part.sig.size()); + fmt += ':'; + if (part.justify == FmtPart::RIGHT) + fmt += '>'; + else if (part.justify == FmtPart::LEFT) + fmt += '<'; + else log_abort(); + log_assert(part.width == 0 || part.padding != '\0'); + fmt += part.padding != '\0' ? part.padding : ' '; + if (part.width > 0) + fmt += std::to_string(part.width); + if (part.type == FmtPart::INTEGER) { + switch (part.base) { + case 2: fmt += 'b'; break; + case 8: fmt += 'o'; break; + case 10: fmt += 'd'; break; + case 16: fmt += 'h'; break; + default: log_abort(); + } + if (part.plus) + fmt += '+'; + fmt += part.signed_ ? 's' : 'u'; + } else if (part.type == FmtPart::CHARACTER) { + fmt += 'c'; + } else if (part.type == FmtPart::VLOG_TIME) { + if (part.realtime) + fmt += 'r'; + else + fmt += 't'; + } else log_abort(); + fmt += '}'; + break; + + default: log_abort(); + } + } + + cell->setParam(ID(FORMAT), fmt); + cell->setParam(ID(ARGS_WIDTH), args.size()); + cell->setPort(ID(ARGS), args); +} + +static size_t compute_required_decimal_places(size_t size, bool signed_) +{ + BigUnsigned max; + if (!signed_) + max.setBit(size, true); + else + max.setBit(size - 1, true); + size_t places = 0; + while (!max.isZero()) { + places++; + max /= 10; + } + if (signed_) + places++; + return places; +} + +static size_t compute_required_nondecimal_places(size_t size, unsigned base) +{ + log_assert(base != 10); + BigUnsigned max; + max.setBit(size - 1, true); + size_t places = 0; + while (!max.isZero()) { + places++; + max /= base; + } + return places; +} + +// Only called for integers, either when: +// +// (a) passed without a format string (e.g. "$display(a);"), or +// +// (b) the corresponding format specifier has no leading zero, e.g. "%b", +// "%20h", "%-10d". +// +// In these cases, for binary/octal/hex, we always zero-pad to the size of the +// signal; i.e. whether "%h" or "%10h" or "%-20h" is used, if the corresponding +// signal is 32'h1234, "00001234" will always be a substring of the output. +// +// For case (a), we have no specified width, so there is nothing more to do. +// +// For case (b), because we are only called with no leading zero on the +// specifier, any specified width beyond the signal size is therefore space +// padding, whatever the justification. +// +// For decimal, we do no zero-padding, instead space-padding to the size +// required for the signal's largest value. This is per other Verilog +// implementations, and intuitively makes sense as decimal representations lack +// a discrete mapping of digits to bit groups. Decimals may also show sign and +// must accommodate this, whereas other representations do not. +void Fmt::apply_verilog_automatic_sizing_and_add(FmtPart &part) +{ + if (part.base == 10) { + size_t places = compute_required_decimal_places(part.sig.size(), part.signed_); + part.padding = ' '; + part.width = std::max(part.width, places); + parts.push_back(part); + return; + } + + part.padding = '0'; + + size_t places = compute_required_nondecimal_places(part.sig.size(), part.base); + if (part.width < places) { + part.justify = FmtPart::RIGHT; + part.width = places; + parts.push_back(part); + } else if (part.width == places) { + parts.push_back(part); + } else if (part.width > places) { + auto gap = std::string(part.width - places, ' '); + part.width = places; + + if (part.justify == FmtPart::RIGHT) { + append_string(gap); + parts.push_back(part); + } else { + part.justify = FmtPart::RIGHT; + parts.push_back(part); + append_string(gap); + } + } +} + +void Fmt::parse_verilog(const std::vector &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name) +{ + parts.clear(); + + auto arg = args.begin(); + for (; arg != args.end(); ++arg) { + switch (arg->type) { + case VerilogFmtArg::INTEGER: { + FmtPart part = {}; + part.type = FmtPart::INTEGER; + part.sig = arg->sig; + part.base = default_base; + part.signed_ = arg->signed_; + apply_verilog_automatic_sizing_and_add(part); + break; + } + + case VerilogFmtArg::TIME: { + FmtPart part = {}; + part.type = FmtPart::VLOG_TIME; + part.realtime = arg->realtime; + part.padding = ' '; + part.width = 20; + parts.push_back(part); + break; + } + + case VerilogFmtArg::STRING: { + if (arg == args.begin() || !sformat_like) { + const auto fmtarg = arg; + const std::string &fmt = fmtarg->str; + FmtPart part = {}; + for (size_t i = 0; i < fmt.size(); i++) { + if (fmt[i] != '%') { + part.str += fmt[i]; + } else if (fmt.substr(i, 2) == "%%") { + i++; + part.str += '%'; + } else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") { + i++; + part.str += module_name.str(); + } else if (fmt.substr(i, 2) == "%m" || fmt.substr(i, 2) == "%M") { + i++; + part.str += module_name.str(); + } else { + if (!part.str.empty()) { + part.type = FmtPart::STRING; + parts.push_back(part); + part = {}; + } + if (++i == fmt.size()) { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + } + + if (++arg == args.end()) { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1); + } + part.sig = arg->sig; + part.signed_ = arg->signed_; + + for (; i < fmt.size(); i++) { + if (fmt[i] == '-') { + // left justify; not in IEEE 1800-2017 or verilator but iverilog has it + part.justify = FmtPart::LEFT; + } else if (fmt[i] == '+') { + // always show sign; not in IEEE 1800-2017 or verilator but iverilog has it + part.plus = true; + } else break; + } + if (i == fmt.size()) { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + } + + bool has_leading_zero = false, has_width = false; + for (; i < fmt.size(); i++) { + if (fmt[i] >= '0' && fmt[i] <= '9') { + if (fmt[i] == '0' && !has_width) { + has_leading_zero = true; + } else { + has_width = true; + part.width *= 10; + part.width += fmt[i] - '0'; + } + continue; + } else if (fmt[i] == 'b' || fmt[i] == 'B') { + part.type = FmtPart::INTEGER; + part.base = 2; + } else if (fmt[i] == 'o' || fmt[i] == 'O') { + part.type = FmtPart::INTEGER; + part.base = 8; + } else if (fmt[i] == 'd' || fmt[i] == 'D') { + part.type = FmtPart::INTEGER; + part.base = 10; + } else if (fmt[i] == 'h' || fmt[i] == 'H' || + fmt[i] == 'x' || fmt[i] == 'X') { + // hex digits always printed in lowercase for %h%x as well as %H%X + part.type = FmtPart::INTEGER; + part.base = 16; + } else if (fmt[i] == 'c' || fmt[i] == 'C') { + part.type = FmtPart::CHARACTER; + part.sig.extend_u0(8); + // %10c and %010c not fully defined in IEEE 1800-2017 and do different things in iverilog + } else if (fmt[i] == 's' || fmt[i] == 'S') { + part.type = FmtPart::CHARACTER; + if ((part.sig.size() % 8) != 0) + part.sig.extend_u0((part.sig.size() + 7) / 8 * 8); + // %10s and %010s not fully defined in IEEE 1800-2017 and do the same thing in iverilog + part.padding = ' '; + } else if (fmt[i] == 't' || fmt[i] == 'T') { + if (arg->type == VerilogFmtArg::TIME) { + part.type = FmtPart::VLOG_TIME; + part.realtime = arg->realtime; + if (!has_width && !has_leading_zero) + part.width = 20; + } else { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + } + } else { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + } + break; + } + if (i == fmt.size()) { + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + } + + if (part.padding == '\0') + part.padding = (has_leading_zero && part.justify == FmtPart::RIGHT) ? '0' : ' '; + + if (part.type == FmtPart::INTEGER && part.base != 10 && part.plus) + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + + if (part.type == FmtPart::INTEGER && !has_leading_zero) + apply_verilog_automatic_sizing_and_add(part); + else + parts.push_back(part); + part = {}; + } + } + if (!part.str.empty()) { + part.type = FmtPart::STRING; + parts.push_back(part); + } + } else { + FmtPart part = {}; + part.type = FmtPart::STRING; + part.str = arg->str; + parts.push_back(part); + } + break; + } + + default: log_abort(); + } + } +} + +std::vector Fmt::emit_verilog() const +{ + std::vector args; + VerilogFmtArg fmt = {}; + fmt.type = VerilogFmtArg::STRING; + + for (auto &part : parts) { + switch (part.type) { + case FmtPart::STRING: + for (char c : part.str) { + if (c == '%') + fmt.str += "%%"; + else + fmt.str += c; + } + break; + + case FmtPart::INTEGER: { + VerilogFmtArg arg = {}; + arg.type = VerilogFmtArg::INTEGER; + arg.sig = part.sig; + arg.signed_ = part.signed_; + args.push_back(arg); + + fmt.str += '%'; + if (part.plus) + fmt.str += '+'; + if (part.justify == FmtPart::LEFT) + fmt.str += '-'; + if (part.width == 0) { + fmt.str += '0'; + } else if (part.width > 0) { + log_assert(part.padding == ' ' || part.padding == '0'); + if (part.base != 10 || part.padding == '0') + fmt.str += '0'; + fmt.str += std::to_string(part.width); + } + switch (part.base) { + case 2: fmt.str += 'b'; break; + case 8: fmt.str += 'o'; break; + case 10: fmt.str += 'd'; break; + case 16: fmt.str += 'h'; break; + default: log_abort(); + } + break; + } + + case FmtPart::CHARACTER: { + VerilogFmtArg arg; + arg.type = VerilogFmtArg::INTEGER; + arg.sig = part.sig; + args.push_back(arg); + + fmt.str += '%'; + if (part.justify == FmtPart::LEFT) + fmt.str += '-'; + if (part.sig.size() == 8) { + if (part.width > 0) { + log_assert(part.padding == '0' || part.padding == ' '); + if (part.padding == '0') + fmt.str += part.padding; + fmt.str += std::to_string(part.width); + } + fmt.str += 'c'; + } else { + log_assert(part.sig.size() % 8 == 0); + if (part.width > 0) { + log_assert(part.padding == ' '); // no zero padding + fmt.str += std::to_string(part.width); + } + fmt.str += 's'; + } + break; + } + + case FmtPart::VLOG_TIME: { + VerilogFmtArg arg; + arg.type = VerilogFmtArg::TIME; + if (part.realtime) + arg.realtime = true; + args.push_back(arg); + + fmt.str += '%'; + if (part.plus) + fmt.str += '+'; + if (part.justify == FmtPart::LEFT) + fmt.str += '-'; + log_assert(part.padding == ' ' || part.padding == '0'); + if (part.padding == '0' && part.width > 0) + fmt.str += '0'; + fmt.str += std::to_string(part.width); + fmt.str += 't'; + break; + } + + default: log_abort(); + } + } + + args.insert(args.begin(), fmt); + return args; +} + +std::string escape_cxx_string(const std::string &input) +{ + std::string output = "\""; + for (auto c : input) { + if (::isprint(c)) { + if (c == '\\') + output.push_back('\\'); + output.push_back(c); + } else { + char l = c & 0xf, h = (c >> 4) & 0xf; + output.append("\\x"); + output.push_back((h < 10 ? '0' + h : 'a' + h - 10)); + output.push_back((l < 10 ? '0' + l : 'a' + l - 10)); + } + } + output.push_back('"'); + if (output.find('\0') != std::string::npos) { + output.insert(0, "std::string {"); + output.append(stringf(", %zu}", input.size())); + } + return output; +} + +void Fmt::emit_cxxrtl(std::ostream &os, std::string indent, std::function emit_sig, const std::string &context) const +{ + os << indent << "std::string buf;\n"; + for (auto &part : parts) { + os << indent << "buf += fmt_part { "; + os << "fmt_part::"; + switch (part.type) { + case FmtPart::STRING: os << "STRING"; break; + case FmtPart::INTEGER: os << "INTEGER"; break; + case FmtPart::CHARACTER: os << "CHARACTER"; break; + case FmtPart::VLOG_TIME: os << "VLOG_TIME"; break; + } + os << ", "; + os << escape_cxx_string(part.str) << ", "; + os << "fmt_part::"; + switch (part.justify) { + case FmtPart::LEFT: os << "LEFT"; break; + case FmtPart::RIGHT: os << "RIGHT"; break; + } + os << ", "; + os << "(char)" << (int)part.padding << ", "; + os << part.width << ", "; + os << part.base << ", "; + os << part.signed_ << ", "; + os << part.plus << ", "; + os << part.realtime; + os << " }.render("; + emit_sig(part.sig); + os << ", " << context << ");\n"; + } + os << indent << "return buf;\n"; +} + +std::string Fmt::render() const +{ + std::string str; + + for (auto &part : parts) { + switch (part.type) { + case FmtPart::STRING: + str += part.str; + break; + + case FmtPart::INTEGER: + case FmtPart::CHARACTER: + case FmtPart::VLOG_TIME: { + std::string buf; + if (part.type == FmtPart::INTEGER) { + RTLIL::Const value = part.sig.as_const(); + + if (part.base != 10) { + size_t minimum_size = 0; + for (size_t index = 0; index < (size_t)value.size(); index++) + if (value[index] != State::S0) + minimum_size = index + 1; + value = value.extract(0, minimum_size); + } + + if (part.base == 2) { + buf = value.as_string(); + } else if (part.base == 8 || part.base == 16) { + size_t step = (part.base == 16) ? 4 : 3; + for (size_t index = 0; index < (size_t)value.size(); index += step) { + RTLIL::Const subvalue = value.extract(index, min(step, value.size() - index)); + bool has_x = false, all_x = true, has_z = false, all_z = true; + for (State bit : subvalue) { + if (bit == State::Sx) + has_x = true; + else + all_x = false; + if (bit == State::Sz) + has_z = true; + else + all_z = false; + } + if (all_x) + buf += 'x'; + else if (all_z) + buf += 'z'; + else if (has_x) + buf += 'X'; + else if (has_z) + buf += 'Z'; + else + buf += "0123456789abcdef"[subvalue.as_int()]; + } + std::reverse(buf.begin(), buf.end()); + } else if (part.base == 10) { + bool has_x = false, all_x = true, has_z = false, all_z = true; + for (State bit : value) { + if (bit == State::Sx) + has_x = true; + else + all_x = false; + if (bit == State::Sz) + has_z = true; + else + all_z = false; + } + if (all_x) + buf += 'x'; + else if (all_z) + buf += 'z'; + else if (has_x) + buf += 'X'; + else if (has_z) + buf += 'Z'; + else { + bool negative = part.signed_ && value[value.size() - 1]; + RTLIL::Const absvalue; + if (negative) + absvalue = RTLIL::const_neg(value, {}, part.signed_, {}, value.size() + 1); + else + absvalue = value; + log_assert(absvalue.is_fully_def()); + if (absvalue.is_fully_zero()) + buf += '0'; + while (!absvalue.is_fully_zero()) { + buf += '0' + RTLIL::const_mod(absvalue, 10, false, false, 4).as_int(); + absvalue = RTLIL::const_div(absvalue, 10, false, false, absvalue.size()); + } + if (negative || part.plus) + buf += negative ? '-' : '+'; + std::reverse(buf.begin(), buf.end()); + } + } else log_abort(); + } else if (part.type == FmtPart::CHARACTER) { + buf = part.sig.as_const().decode_string(); + } else if (part.type == FmtPart::VLOG_TIME) { + // We only render() during initial, so time is always zero. + buf = "0"; + } + + log_assert(part.width == 0 || part.padding != '\0'); + if (part.justify == FmtPart::RIGHT && buf.size() < part.width) { + size_t pad_width = part.width - buf.size(); + if (part.padding == '0' && (!buf.empty() && (buf.front() == '+' || buf.front() == '-'))) { + str += buf.front(); + buf.erase(0, 1); + } + str += std::string(pad_width, part.padding); + } + str += buf; + if (part.justify == FmtPart::LEFT && buf.size() < part.width) + str += std::string(part.width - buf.size(), part.padding); + break; + } + } + } + + return str; +} diff --git a/yosys/kernel/fmt.h b/yosys/kernel/fmt.h new file mode 100644 index 00000000000..3bedb786ec4 --- /dev/null +++ b/yosys/kernel/fmt.h @@ -0,0 +1,107 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef FMT_H +#define FMT_H + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +// Verilog format argument, such as the arguments in: +// $display("foo %d bar %01x", 4'b0, $signed(2'b11)) +struct VerilogFmtArg { + enum { + STRING = 0, + INTEGER = 1, + TIME = 2, + } type; + + // All types + std::string filename; + unsigned first_line; + + // STRING type + std::string str; + + // INTEGER type + RTLIL::SigSpec sig; + bool signed_ = false; + + // TIME type + bool realtime = false; +}; + +// RTLIL format part, such as the substitutions in: +// "foo {4:> 4du} bar {2:<01hs}" +// Must be kept in sync with `struct fmt_part` in backends/cxxrtl/runtime/cxxrtl/cxxrtl.h! +struct FmtPart { + enum { + STRING = 0, + INTEGER = 1, + CHARACTER = 2, + VLOG_TIME = 3, + } type; + + // STRING type + std::string str; + + // INTEGER/CHARACTER types + RTLIL::SigSpec sig; + + // INTEGER/CHARACTER/VLOG_TIME types + enum { + RIGHT = 0, + LEFT = 1, + } justify = RIGHT; + char padding = '\0'; + size_t width = 0; + + // INTEGER type + unsigned base = 10; + bool signed_ = false; + bool plus = false; + + // VLOG_TIME type + bool realtime = false; +}; + +struct Fmt { +public: + std::vector parts; + + void append_string(const std::string &str); + + void parse_rtlil(const RTLIL::Cell *cell); + void emit_rtlil(RTLIL::Cell *cell) const; + + void parse_verilog(const std::vector &args, bool sformat_like, int default_base, RTLIL::IdString task_name, RTLIL::IdString module_name); + std::vector emit_verilog() const; + + void emit_cxxrtl(std::ostream &os, std::string indent, std::function emit_sig, const std::string &context) const; + + std::string render() const; + +private: + void apply_verilog_automatic_sizing_and_add(FmtPart &part); +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/yosys/kernel/hashlib.h b/yosys/kernel/hashlib.h index b3f99bf730f..e8ddddd3357 100644 --- a/yosys/kernel/hashlib.h +++ b/yosys/kernel/hashlib.h @@ -17,6 +17,8 @@ #include #include +#include + namespace hashlib { const int hashtable_size_trigger = 2; @@ -90,6 +92,12 @@ template<> struct hash_ops : hash_int_ops return a; } }; +template<> struct hash_ops : hash_int_ops +{ + static inline unsigned int hash(uint64_t a) { + return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); + } +}; template<> struct hash_ops { static inline bool cmp(const std::string &a, const std::string &b) { @@ -365,7 +373,7 @@ class dict } public: - class const_iterator : public std::iterator> + class const_iterator { friend class dict; protected: @@ -373,6 +381,11 @@ class dict int index; const_iterator(const dict *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef std::pair value_type; + typedef ptrdiff_t difference_type; + typedef std::pair* pointer; + typedef std::pair& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } const_iterator operator+=(int amt) { index -= amt; return *this; } @@ -383,7 +396,7 @@ class dict const std::pair *operator->() const { return &ptr->entries[index].udata; } }; - class iterator : public std::iterator> + class iterator { friend class dict; protected: @@ -391,6 +404,11 @@ class dict int index; iterator(dict *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef std::pair value_type; + typedef ptrdiff_t difference_type; + typedef std::pair* pointer; + typedef std::pair& reference; iterator() { } iterator operator++() { index--; return *this; } iterator operator+=(int amt) { index -= amt; return *this; } @@ -404,7 +422,7 @@ class dict operator const_iterator() const { return const_iterator(ptr, index); } }; - dict() + constexpr dict() { } @@ -794,7 +812,7 @@ class pool } public: - class const_iterator : public std::iterator + class const_iterator { friend class pool; protected: @@ -802,6 +820,11 @@ class pool int index; const_iterator(const pool *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; const_iterator() { } const_iterator operator++() { index--; return *this; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -810,7 +833,7 @@ class pool const K *operator->() const { return &ptr->entries[index].udata; } }; - class iterator : public std::iterator + class iterator { friend class pool; protected: @@ -818,6 +841,11 @@ class pool int index; iterator(pool *ptr, int index) : ptr(ptr), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; iterator() { } iterator operator++() { index--; return *this; } bool operator==(const iterator &other) const { return index == other.index; } @@ -829,7 +857,7 @@ class pool operator const_iterator() const { return const_iterator(ptr, index); } }; - pool() + constexpr pool() { } @@ -988,7 +1016,7 @@ class pool return !operator==(other); } - bool hash() const { + unsigned int hash() const { unsigned int hashval = mkhash_init; for (auto &it : entries) hashval ^= ops.hash(it.udata); @@ -1015,7 +1043,7 @@ class idict pool database; public: - class const_iterator : public std::iterator + class const_iterator { friend class idict; protected: @@ -1023,6 +1051,11 @@ class idict int index; const_iterator(const idict &container, int index) : container(container), index(index) { } public: + typedef std::forward_iterator_tag iterator_category; + typedef K value_type; + typedef ptrdiff_t difference_type; + typedef K* pointer; + typedef K& reference; const_iterator() { } const_iterator operator++() { index++; return *this; } bool operator==(const const_iterator &other) const { return index == other.index; } @@ -1031,6 +1064,10 @@ class idict const K *operator->() const { return &container[index]; } }; + constexpr idict() + { + } + int operator()(const K &key) { int hash = database.do_hash(key); @@ -1101,6 +1138,10 @@ class mfp public: typedef typename idict::const_iterator const_iterator; + constexpr mfp() + { + } + int operator()(const K &key) const { int i = database(key); diff --git a/yosys/kernel/log.cc b/yosys/kernel/log.cc index 73e7f16eca5..9a61e8f08b3 100644 --- a/yosys/kernel/log.cc +++ b/yosys/kernel/log.cc @@ -59,7 +59,7 @@ bool log_quiet_warnings = false; int log_verbose_level; string log_last_error; void (*log_error_atexit)() = NULL; -void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg) = NULL; +void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg) = NULL; int log_make_debug = 0; int log_force_debug = 0; diff --git a/yosys/kernel/log.h b/yosys/kernel/log.h index 78a2e434c7a..e4f06c69d19 100644 --- a/yosys/kernel/log.h +++ b/yosys/kernel/log.h @@ -131,8 +131,8 @@ void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(for void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); -void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)); -extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg); +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); +extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); diff --git a/yosys/kernel/mem.cc b/yosys/kernel/mem.cc index 628f6210499..01c866770f5 100644 --- a/yosys/kernel/mem.cc +++ b/yosys/kernel/mem.cc @@ -148,6 +148,9 @@ void Mem::emit() { for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++) wr_port_xlat.push_back(i); for (auto &port : rd_ports) { + for (auto attr: port.attributes) + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -210,6 +213,9 @@ void Mem::emit() { cell->setPort(ID::RD_ADDR, rd_addr); cell->setPort(ID::RD_DATA, rd_data); for (auto &port : wr_ports) { + for (auto attr: port.attributes) + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (port.cell) { module->remove(port.cell); port.cell = nullptr; @@ -246,6 +252,9 @@ void Mem::emit() { cell->setPort(ID::WR_ADDR, wr_addr); cell->setPort(ID::WR_DATA, wr_data); for (auto &init : inits) { + for (auto attr: init.attributes) + if (!cell->has_attribute(attr.first)) + cell->attributes.insert(attr); if (init.cell) { module->remove(init.cell); init.cell = nullptr; @@ -1252,12 +1261,12 @@ void Mem::prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals) { // If transparent with only one, emulate it, and remove the collision-X // flag that emulate_transparency will set (to align with the other port). if (rport.transparency_mask[idx1]) { - emulate_transparency(i, idx1, initvals); + emulate_transparency(idx1, i, initvals); rport.collision_x_mask[idx1] = false; continue; } if (rport.transparency_mask[idx2]) { - emulate_transparency(i, idx2, initvals); + emulate_transparency(idx2, i, initvals); rport.collision_x_mask[idx2] = false; continue; } diff --git a/yosys/kernel/register.cc b/yosys/kernel/register.cc index 9ffb17c1a97..1853e94d56b 100644 --- a/yosys/kernel/register.cc +++ b/yosys/kernel/register.cc @@ -108,9 +108,8 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he void Pass::run_register() { - if (pass_register.count(pass_name)) + if (pass_register.count(pass_name) && !replace_existing_pass()) log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); - pass_register[pass_name] = this; } @@ -447,13 +446,12 @@ Frontend::Frontend(std::string name, std::string short_help) : void Frontend::run_register() { - if (pass_register.count(pass_name)) + if (pass_register.count(pass_name) && !replace_existing_pass()) log_error("Unable to register pass '%s', pass already exists!\n", pass_name.c_str()); pass_register[pass_name] = this; - if (frontend_register.count(frontend_name)) + if (frontend_register.count(frontend_name) && !replace_existing_pass()) log_error("Unable to register frontend '%s', frontend already exists!\n", frontend_name.c_str()); - frontend_register[frontend_name] = this; } diff --git a/yosys/kernel/register.h b/yosys/kernel/register.h index 15750af2a40..08ce4b28787 100644 --- a/yosys/kernel/register.h +++ b/yosys/kernel/register.h @@ -70,6 +70,7 @@ struct Pass virtual void on_register(); virtual void on_shutdown(); + virtual bool replace_existing_pass() const { return false; } }; struct ScriptPass : Pass diff --git a/yosys/kernel/rtlil.cc b/yosys/kernel/rtlil.cc index 7011429ff5a..125730f2924 100644 --- a/yosys/kernel/rtlil.cc +++ b/yosys/kernel/rtlil.cc @@ -313,18 +313,33 @@ RTLIL::Const RTLIL::Const::from_string(const std::string &str) std::string RTLIL::Const::decode_string() const { - std::string string; - string.reserve(GetSize(bits)/8); - for (int i = 0; i < GetSize(bits); i += 8) { + const int n = GetSize(bits); + const int n_over_8 = n / 8; + std::string s; + s.reserve(n_over_8); + int i = n_over_8 * 8; + if (i < n) { char ch = 0; - for (int j = 0; j < 8 && i + j < int (bits.size()); j++) - if (bits[i + j] == RTLIL::State::S1) + for (int j = 0; j < (n - i); j++) { + if (bits[i + j] == RTLIL::State::S1) { ch |= 1 << j; + } + } + if (ch != 0) + s.append({ch}); + } + i -= 8; + for (; i >= 0; i -= 8) { + char ch = 0; + for (int j = 0; j < 8; j++) { + if (bits[i + j] == RTLIL::State::S1) { + ch |= 1 << j; + } + } if (ch != 0) - string.append({ch}); + s.append({ch}); } - std::reverse(string.begin(), string.end()); - return string; + return s; } bool RTLIL::Const::is_fully_zero() const @@ -1053,6 +1068,12 @@ namespace { error(__LINE__); } + std::string param_string(const RTLIL::IdString &name) + { + param(name); + return cell->parameters.at(name).decode_string(); + } + void port(const RTLIL::IdString& name, int width) { auto it = cell->connections_.find(name); @@ -1720,6 +1741,34 @@ namespace { return; } + if (cell->type == ID($print)) { + param(ID(FORMAT)); + param_bool(ID::TRG_ENABLE); + param(ID::TRG_POLARITY); + param(ID::PRIORITY); + port(ID::EN, 1); + port(ID::TRG, param(ID::TRG_WIDTH)); + port(ID::ARGS, param(ID::ARGS_WIDTH)); + check_expected(); + return; + } + + if (cell->type == ID($check)) { + std::string flavor = param_string(ID(FLAVOR)); + if (!(flavor == "assert" || flavor == "assume" || flavor == "live" || flavor == "fair" || flavor == "cover")) + error(__LINE__); + param(ID(FORMAT)); + param_bool(ID::TRG_ENABLE); + param(ID::TRG_POLARITY); + param(ID::PRIORITY); + port(ID::A, 1); + port(ID::EN, 1); + port(ID::TRG, param(ID::TRG_WIDTH)); + port(ID::ARGS, param(ID::ARGS_WIDTH)); + check_expected(); + return; + } + if (cell->type == ID($_BUF_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } if (cell->type == ID($_NOT_)) { port(ID::A,1); port(ID::Y,1); check_expected(); return; } if (cell->type == ID($_AND_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } @@ -1816,6 +1865,40 @@ namespace { ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_))) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type.in(ID($set_tag))) { + param(ID::WIDTH); + param(ID::TAG); + port(ID::A, param(ID::WIDTH)); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type.in(ID($get_tag),ID($original_tag))) { + param(ID::WIDTH); + param(ID::TAG); + port(ID::A, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type.in(ID($overwrite_tag))) { + param(ID::WIDTH); + param(ID::TAG); + port(ID::A, param(ID::WIDTH)); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type.in(ID($future_ff))) { + param(ID::WIDTH); + port(ID::A, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + check_expected(); + return; + } error(__LINE__); } }; @@ -2096,17 +2179,10 @@ void RTLIL::Module::remove(const pool &wires) } void operator()(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs) { - log_assert(GetSize(lhs) == GetSize(rhs)); - lhs.unpack(); - rhs.unpack(); - for (int i = 0; i < GetSize(lhs); i++) { - RTLIL::SigBit &lhs_bit = lhs.bits_[i]; - RTLIL::SigBit &rhs_bit = rhs.bits_[i]; - if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) { - lhs_bit = State::Sx; - rhs_bit = State::Sx; - } - } + // If a deleted wire occurs on the lhs or rhs we just remove that part + // of the assignment + lhs.remove2(*wires_p, &rhs); + rhs.remove2(*wires_p, &lhs); } }; @@ -2631,6 +2707,19 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &s return cell; } +RTLIL::Cell* RTLIL::Module::addFa(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src) +{ + RTLIL::Cell *cell = addCell(name, ID($fa)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->setPort(ID::A, sig_a); + cell->setPort(ID::B, sig_b); + cell->setPort(ID::C, sig_c); + cell->setPort(ID::X, sig_x); + cell->setPort(ID::Y, sig_y); + cell->set_src_attribute(src); + return cell; +} + RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($slice)); @@ -3234,6 +3323,80 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string return sig; } +RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + Cell *cell = addCell(name, ID($set_tag)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->parameters[ID::TAG] = tag; + cell->setPort(ID::A, sig_a); + cell->setPort(ID::SET, sig_s); + cell->setPort(ID::CLR, sig_c); + cell->setPort(ID::Y, sig); + cell->set_src_attribute(src); + return sig; +} + +RTLIL::Cell* RTLIL::Module::addSetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src) +{ + Cell *cell = addCell(name, ID($set_tag)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->parameters[ID::TAG] = tag; + cell->setPort(ID::A, sig_a); + cell->setPort(ID::SET, sig_s); + cell->setPort(ID::CLR, sig_c); + cell->setPort(ID::Y, sig_y); + cell->set_src_attribute(src); + return cell; +} + +RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + Cell *cell = addCell(name, ID($get_tag)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->parameters[ID::TAG] = tag; + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, sig); + cell->set_src_attribute(src); + return sig; +} + +RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src) +{ + RTLIL::Cell *cell = addCell(name, ID($overwrite_tag)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->parameters[ID::TAG] = tag; + cell->setPort(ID::A, sig_a); + cell->setPort(ID::SET, sig_s); + cell->setPort(ID::CLR, sig_c); + cell->set_src_attribute(src); + return cell; +} + +RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, sig_a.size()); + Cell *cell = addCell(name, ID($original_tag)); + cell->parameters[ID::WIDTH] = sig_a.size(); + cell->parameters[ID::TAG] = tag; + cell->setPort(ID::A, sig_a); + cell->setPort(ID::Y, sig); + cell->set_src_attribute(src); + return sig; +} + +RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size()); + Cell *cell = addCell(name, ID($future_ff)); + cell->parameters[ID::WIDTH] = sig_e.size(); + cell->setPort(ID::A, sig_e); + cell->setPort(ID::Y, sig); + cell->set_src_attribute(src); + return sig; +} + RTLIL::Wire::Wire() { static unsigned int hashidx_count = 123456789; @@ -3545,6 +3708,9 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit) RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const { + log_assert(offset >= 0); + log_assert(length >= 0); + log_assert(offset + length <= width); RTLIL::SigChunk ret; if (wire) { ret.wire = wire; @@ -3911,13 +4077,17 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec unpack(); other->unpack(); + dict pattern_to_with; for (int i = 0; i < GetSize(pattern.bits_); i++) { if (pattern.bits_[i].wire != NULL) { - for (int j = 0; j < GetSize(bits_); j++) { - if (bits_[j] == pattern.bits_[i]) { - other->bits_[j] = with.bits_[i]; - } - } + pattern_to_with.emplace(pattern.bits_[i], i); + } + } + + for (int j = 0; j < GetSize(bits_); j++) { + auto it = pattern_to_with.find(bits_[j]); + if (it != pattern_to_with.end()) { + other->bits_[j] = with.bits_[it->second]; } } @@ -4086,6 +4256,34 @@ void RTLIL::SigSpec::remove2(const std::set &pattern, RTLIL::SigS check(); } +void RTLIL::SigSpec::remove2(const pool &pattern, RTLIL::SigSpec *other) +{ + if (other) + cover("kernel.rtlil.sigspec.remove_other"); + else + cover("kernel.rtlil.sigspec.remove"); + + unpack(); + + if (other != NULL) { + log_assert(width_ == other->width_); + other->unpack(); + } + + for (int i = GetSize(bits_) - 1; i >= 0; i--) { + if (bits_[i].wire != NULL && pattern.count(bits_[i].wire)) { + bits_.erase(bits_.begin() + i); + width_--; + if (other != NULL) { + other->bits_.erase(other->bits_.begin() + i); + other->width_--; + } + } + } + + check(); +} + RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const { if (other) @@ -4225,6 +4423,9 @@ void RTLIL::SigSpec::remove(int offset, int length) RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { + log_assert(offset >= 0); + log_assert(length >= 0); + log_assert(offset + length <= width_); unpack(); cover("kernel.rtlil.sigspec.extract_pos"); return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); diff --git a/yosys/kernel/rtlil.h b/yosys/kernel/rtlil.h index a69ce480baf..928bc044049 100644 --- a/yosys/kernel/rtlil.h +++ b/yosys/kernel/rtlil.h @@ -308,10 +308,14 @@ namespace RTLIL bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; } char operator[](size_t i) const { - const char *p = c_str(); + const char *p = c_str(); +#ifndef NDEBUG for (; i != 0; i--, p++) log_assert(*p != 0); return *p; +#else + return *(p + i); +#endif } std::string substr(size_t pos = 0, size_t len = std::string::npos) const { @@ -799,8 +803,14 @@ struct RTLIL::SigBit unsigned int hash() const; }; -struct RTLIL::SigSpecIterator : public std::iterator +struct RTLIL::SigSpecIterator { + typedef std::input_iterator_tag iterator_category; + typedef RTLIL::SigBit value_type; + typedef ptrdiff_t difference_type; + typedef RTLIL::SigBit* pointer; + typedef RTLIL::SigBit& reference; + RTLIL::SigSpec *sig_p; int index; @@ -810,8 +820,14 @@ struct RTLIL::SigSpecIterator : public std::iterator +struct RTLIL::SigSpecConstIterator { + typedef std::input_iterator_tag iterator_category; + typedef RTLIL::SigBit value_type; + typedef ptrdiff_t difference_type; + typedef RTLIL::SigBit* pointer; + typedef RTLIL::SigBit& reference; + const RTLIL::SigSpec *sig_p; int index; @@ -908,6 +924,7 @@ struct RTLIL::SigSpec void remove(const pool &pattern, RTLIL::SigSpec *other) const; void remove2(const pool &pattern, RTLIL::SigSpec *other); void remove2(const std::set &pattern, RTLIL::SigSpec *other); + void remove2(const pool &pattern, RTLIL::SigSpec *other); void remove(int offset, int length = 1); void remove_const(); @@ -917,6 +934,9 @@ struct RTLIL::SigSpec RTLIL::SigSpec extract(int offset, int length = 1) const; RTLIL::SigSpec extract_end(int offset) const { return extract(offset, width_ - offset); } + RTLIL::SigBit lsb() const { log_assert(width_); return (*this)[0]; }; + RTLIL::SigBit msb() const { log_assert(width_); return (*this)[width_ - 1]; }; + void append(const RTLIL::SigSpec &signal); inline void append(Wire *wire) { append(RTLIL::SigSpec(wire)); } inline void append(const RTLIL::SigChunk &chunk) { append(RTLIL::SigSpec(chunk)); } @@ -1298,6 +1318,8 @@ struct RTLIL::Module : public RTLIL::AttrObject RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = ""); + RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); @@ -1465,6 +1487,13 @@ struct RTLIL::Module : public RTLIL::AttrObject RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); + RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = ""); + RTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, const std::string &src = ""); + RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = ""); + RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = ""); + RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = ""); + RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = ""); + #ifdef WITH_PYTHON static std::map *get_all_modules(void); #endif diff --git a/yosys/kernel/utils.h b/yosys/kernel/utils.h index d37f045ff7c..8fa223824da 100644 --- a/yosys/kernel/utils.h +++ b/yosys/kernel/utils.h @@ -128,41 +128,103 @@ struct stackmap // A simple class for topological sorting // ------------------------------------------------ -template> -struct TopoSort +template , typename OPS = hash_ops> class TopoSort { - bool analyze_loops, found_loops; - std::map, C> database; - std::set> loops; + public: + // We use this ordering of the edges in the adjacency matrix for + // exact compatibility with an older implementation. + struct IndirectCmp { + IndirectCmp(const std::vector &nodes) : node_cmp_(), nodes_(nodes) {} + bool operator()(int a, int b) const + { + log_assert(static_cast(a) < nodes_.size()); + log_assert(static_cast(b) < nodes_.size()); + return node_cmp_(nodes_[a], nodes_[b]); + } + const C node_cmp_; + const std::vector &nodes_; + }; + + bool analyze_loops; + std::map node_to_index; + std::vector> edges; std::vector sorted; + std::set> loops; - TopoSort() + TopoSort() : indirect_cmp(nodes) { analyze_loops = true; found_loops = false; } - void node(T n) + int node(T n) { - if (database.count(n) == 0) - database[n] = std::set(); + auto rv = node_to_index.emplace(n, static_cast(nodes.size())); + if (rv.second) { + nodes.push_back(n); + edges.push_back(std::set(indirect_cmp)); + } + return rv.first->second; } - void edge(T left, T right) + void edge(int l_index, int r_index) { edges[r_index].insert(l_index); } + + void edge(T left, T right) { edge(node(left), node(right)); } + + bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); } + + bool sort() { - node(left); - database[right].insert(left); + log_assert(GetSize(node_to_index) == GetSize(edges)); + log_assert(GetSize(nodes) == GetSize(edges)); + + loops.clear(); + sorted.clear(); + found_loops = false; + + std::vector marked_cells(edges.size(), false); + std::vector active_cells(edges.size(), false); + std::vector active_stack; + sorted.reserve(edges.size()); + + for (const auto &it : node_to_index) + sort_worker(it.second, marked_cells, active_cells, active_stack); + + log_assert(GetSize(sorted) == GetSize(nodes)); + + return !found_loops; } - void sort_worker(const T &n, std::set &marked_cells, std::set &active_cells, std::vector &active_stack) + // Build the more expensive representation of edges for + // a few passes that use it directly. + std::map, C> get_database() { - if (active_cells.count(n)) { + std::map, C> database; + for (size_t i = 0; i < nodes.size(); ++i) { + std::set converted_edge_set; + for (int other_node : edges[i]) { + converted_edge_set.insert(nodes[other_node]); + } + database.emplace(nodes[i], converted_edge_set); + } + return database; + } + + private: + bool found_loops; + std::vector nodes; + const IndirectCmp indirect_cmp; + + void sort_worker(const int root_index, std::vector &marked_cells, std::vector &active_cells, std::vector &active_stack) + { + if (active_cells[root_index]) { found_loops = true; if (analyze_loops) { std::set loop; - for (int i = GetSize(active_stack)-1; i >= 0; i--) { - loop.insert(active_stack[i]); - if (active_stack[i] == n) + for (int i = GetSize(active_stack) - 1; i >= 0; i--) { + const int index = active_stack[i]; + loop.insert(nodes[index]); + if (index == root_index) break; } loops.insert(loop); @@ -170,42 +232,24 @@ struct TopoSort return; } - if (marked_cells.count(n)) + if (marked_cells[root_index]) return; - if (!database.at(n).empty()) - { + if (!edges[root_index].empty()) { if (analyze_loops) - active_stack.push_back(n); - active_cells.insert(n); + active_stack.push_back(root_index); + active_cells[root_index] = true; - for (auto &left_n : database.at(n)) + for (int left_n : edges[root_index]) sort_worker(left_n, marked_cells, active_cells, active_stack); if (analyze_loops) active_stack.pop_back(); - active_cells.erase(n); + active_cells[root_index] = false; } - marked_cells.insert(n); - sorted.push_back(n); - } - - bool sort() - { - loops.clear(); - sorted.clear(); - found_loops = false; - - std::set marked_cells; - std::set active_cells; - std::vector active_stack; - - for (auto &it : database) - sort_worker(it.first, marked_cells, active_cells, active_stack); - - log_assert(GetSize(sorted) == GetSize(database)); - return !found_loops; + marked_cells[root_index] = true; + sorted.push_back(nodes[root_index]); } }; diff --git a/yosys/kernel/yosys.cc b/yosys/kernel/yosys.cc index bd8dded4b5f..c7f5bebdab7 100644 --- a/yosys/kernel/yosys.cc +++ b/yosys/kernel/yosys.cc @@ -175,48 +175,6 @@ int ceil_log2(int x) #endif } -std::string stringf(const char *fmt, ...) -{ - std::string string; - va_list ap; - - va_start(ap, fmt); - string = vstringf(fmt, ap); - va_end(ap); - - return string; -} - -std::string vstringf(const char *fmt, va_list ap) -{ - std::string string; - char *str = NULL; - -#if defined(_WIN32 )|| defined(__CYGWIN__) - int sz = 64, rc; - while (1) { - va_list apc; - va_copy(apc, ap); - str = (char*)realloc(str, sz); - rc = vsnprintf(str, sz, fmt, apc); - va_end(apc); - if (rc >= 0 && rc < sz) - break; - sz *= 2; - } -#else - if (vasprintf(&str, fmt, ap) < 0) - str = NULL; -#endif - - if (str != NULL) { - string = str; - free(str); - } - - return string; -} - int readsome(std::istream &f, char *s, int n) { int rc = int(f.readsome(s, n)); @@ -478,6 +436,25 @@ std::string make_temp_dir(std::string template_str) #endif } +bool check_directory_exists(const std::string& dirname) +{ +#if defined(_WIN32) + struct _stat info; + if (_stat(dirname.c_str(), &info) != 0) + { + return false; + } + return (info.st_mode & _S_IFDIR) != 0; +#else + struct stat info; + if (stat(dirname.c_str(), &info) != 0) + { + return false; + } + return (info.st_mode & S_IFDIR) != 0; +#endif +} + #ifdef _WIN32 bool check_file_exists(std::string filename, bool) { @@ -523,6 +500,48 @@ void remove_directory(std::string dirname) #endif } +bool create_directory(const std::string& dirname) +{ +#if defined(_WIN32) + int ret = _mkdir(dirname.c_str()); +#else + mode_t mode = 0755; + int ret = mkdir(dirname.c_str(), mode); +#endif + if (ret == 0) + return true; + + switch (errno) + { + case ENOENT: + // parent didn't exist, try to create it + { + std::string::size_type pos = dirname.find_last_of('/'); + if (pos == std::string::npos) +#if defined(_WIN32) + pos = dirname.find_last_of('\\'); + if (pos == std::string::npos) +#endif + return false; + if (!create_directory( dirname.substr(0, pos) )) + return false; + } + // now, try to create again +#if defined(_WIN32) + return 0 == _mkdir(dirname.c_str()); +#else + return 0 == mkdir(dirname.c_str(), mode); +#endif + + case EEXIST: + // done! + return check_directory_exists(dirname); + + default: + return false; + } +} + std::string escape_filename_spaces(const std::string& filename) { std::string out; @@ -823,10 +842,10 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a int yosys_tcl_iterp_init(Tcl_Interp *interp) { - if (Tcl_Init(interp)!=TCL_OK) + if (Tcl_Init(interp)!=TCL_OK) log_warning("Tcl_Init() call failed - %s\n",Tcl_ErrnoMsg(Tcl_GetErrno())); Tcl_CreateCommand(interp, "yosys", tcl_yosys_cmd, NULL, NULL); - return TCL_OK ; + return TCL_OK ; } void yosys_tcl_activate_repl() @@ -1395,8 +1414,12 @@ void shell(RTLIL::Design *design) if ((command = fgets(command_buffer, 4096, stdin)) == NULL) break; #endif - if (command[strspn(command, " \t\r\n")] == 0) + if (command[strspn(command, " \t\r\n")] == 0) { +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + free(command); +#endif continue; + } #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) add_history(command); #endif @@ -1418,10 +1441,17 @@ void shell(RTLIL::Design *design) log_reset_stack(); } design->check(); +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + if (command) + free(command); +#endif } if (command == NULL) printf("exit\n"); - +#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) + else + free(command); +#endif recursion_counter--; log_cmd_error_throw = false; } diff --git a/yosys/kernel/yosys.h b/yosys/kernel/yosys.h index 29415ff842e..0a4641d1819 100644 --- a/yosys/kernel/yosys.h +++ b/yosys/kernel/yosys.h @@ -66,6 +66,8 @@ #include #include #include +#include +#include #ifdef WITH_PYTHON #include @@ -272,8 +274,64 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); } void yosys_banner(); int ceil_log2(int x) YS_ATTRIBUTE(const); + +inline std::string vstringf(const char *fmt, va_list ap) +{ + // For the common case of strings shorter than 128, save a heap + // allocation by using a stack allocated buffer. + const int kBufSize = 128; + char buf[kBufSize]; + buf[0] = '\0'; + va_list apc; + va_copy(apc, ap); + int n = vsnprintf(buf, kBufSize, fmt, apc); + va_end(apc); + if (n < kBufSize) + return std::string(buf); + + std::string string; + char *str = NULL; +#if defined(_WIN32 )|| defined(__CYGWIN__) + int sz = 2 * kBufSize, rc; + while (1) { + va_copy(apc, ap); + str = (char*)realloc(str, sz); + rc = vsnprintf(str, sz, fmt, apc); + va_end(apc); + if (rc >= 0 && rc < sz) + break; + sz *= 2; + } + if (str != NULL) { + string = str; + free(str); + } + return string; +#else + if (vasprintf(&str, fmt, ap) < 0) + str = NULL; + if (str != NULL) { + string = str; + free(str); + } + return string; +#endif +} + std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2)); -std::string vstringf(const char *fmt, va_list ap); + +inline std::string stringf(const char *fmt, ...) +{ + std::string string; + va_list ap; + + va_start(ap, fmt); + string = vstringf(fmt, ap); + va_end(ap); + + return string; +} + int readsome(std::istream &f, char *s, int n); std::string next_token(std::string &text, const char *sep = " \t\r\n", bool long_strings = false); std::vector split_tokens(const std::string &text, const char *sep = " \t\r\n"); @@ -285,8 +343,10 @@ std::string get_base_tmpdir(); std::string make_temp_file(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX"); std::string make_temp_dir(std::string template_str = get_base_tmpdir() + "/yosys_XXXXXX"); bool check_file_exists(std::string filename, bool is_exec = false); +bool check_directory_exists(const std::string& dirname); bool is_absolute_path(std::string filename); void remove_directory(std::string dirname); +bool create_directory(const std::string& dirname); std::string escape_filename_spaces(const std::string& filename); template int GetSize(const T &obj) { return obj.size(); } diff --git a/yosys/libs/bigint/run-testsuite b/yosys/libs/bigint/run-testsuite index ff737291641..8436ebda057 100755 --- a/yosys/libs/bigint/run-testsuite +++ b/yosys/libs/bigint/run-testsuite @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash bad= diff --git a/yosys/libs/fst/fstapi.cc b/yosys/libs/fst/fstapi.cc index da0d959a0de..592b5cae6a7 100644 --- a/yosys/libs/fst/fstapi.cc +++ b/yosys/libs/fst/fstapi.cc @@ -348,17 +348,17 @@ static void *fstMmap2(size_t __len, int __fd, fst_off_t __off) #ifdef FST_DO_MISALIGNED_OPS #define fstGetUint32(x) (*(uint32_t *)(x)) #else -static uint32_t fstGetUint32(unsigned char *mem) +static inline uint32_t fstGetUint32(unsigned char *mem) { - uint32_t u32; - unsigned char *buf = (unsigned char *)(&u32); + union { + uint8_t u8[sizeof(uint32_t)]; + uint32_t u32; + } u; - buf[0] = mem[0]; - buf[1] = mem[1]; - buf[2] = mem[2]; - buf[3] = mem[3]; + for (size_t i=0; i < sizeof(u.u8); i++) + u.u8[i] = mem[i]; - return (*(uint32_t *)buf); + return u.u32; } #endif @@ -4334,7 +4334,7 @@ int fstReaderInit(struct fstReaderContext *xc) hdr_incomplete = (xc->start_time == 0) && (xc->end_time == 0); fstFread(&dcheck, 8, 1, xc->f); - xc->double_endian_match = (dcheck == FST_DOUBLE_ENDTEST); + xc->double_endian_match = (dcheck == (double)FST_DOUBLE_ENDTEST); if (!xc->double_endian_match) { union { diff --git a/yosys/misc/py_wrap_generator.py b/yosys/misc/py_wrap_generator.py index 7fe78e03a58..a65d24d9218 100644 --- a/yosys/misc/py_wrap_generator.py +++ b/yosys/misc/py_wrap_generator.py @@ -1257,6 +1257,7 @@ def from_string(str_def, containing_file, class_, line_number, namespace): func.is_static = False func.is_inline = False func.is_virtual = False + func.is_const = False func.ret_attr_type = attr_types.default func.is_operator = False func.member_of = None @@ -1334,6 +1335,11 @@ def from_string(str_def, containing_file, class_, line_number, namespace): found = find_closing(str_def, "(", ")") if found == -1: return None + + post_qualifiers = str_def[found + 1:].lstrip().replace("{", " {") + " " + if post_qualifiers.startswith("const "): + func.is_const = True + str_def = str_def[0:found] if func.name in blacklist_methods: return None @@ -1379,6 +1385,12 @@ def mangled_name(self): def gen_alias(self): self.alias = self.mangled_name + def gen_post_qualifiers(self, derived=False): + if self.member_of != None and self.member_of.link_type == link_types.derive and self.is_virtual and derived: + # we drop the qualifiers when deriving callbacks to be implemented in Python + return '' + return ' const' if self.is_const else '' + def gen_decl(self): if self.duplicate: return "" @@ -1392,7 +1404,7 @@ def gen_decl(self): text += ", " if len(self.args) > 0: text = text[:-2] - text += ");\n" + text += f"){self.gen_post_qualifiers()};\n" return text def gen_decl_virtual(self): @@ -1411,12 +1423,18 @@ def gen_decl_virtual(self): if len(self.args) > 0: text = text[:-2] text += ")" - if len(self.args) == 0: + if len(self.args) == 0 and self.ret_type.name == "void": text += "{}" else: text += "\n\t\t{" for arg in self.args: text += "\n\t\t\t(void)" + arg.gen_varname() + ";" + if self.ret_type.name == "void": + pass + elif self.ret_type.name == "bool": + text += "\n\t\t\treturn false;" + else: + raise NotImplementedError(self.ret_type.name) text += "\n\t\t}\n" text += "\n\t\tvirtual " if self.is_static: @@ -1427,7 +1445,7 @@ def gen_decl_virtual(self): text += ", " if len(self.args) > 0: text = text[:-2] - text += ") override;\n" + text += f"){self.gen_post_qualifiers()} override;\n" return text def gen_decl_hash_py(self): @@ -1452,7 +1470,7 @@ def gen_def(self): text += ", " if len(self.args) > 0: text = text[:-2] - text +=")\n\t{" + text += f"){self.gen_post_qualifiers()}\n\t{{" for arg in self.args: text += arg.gen_translation() text += "\n\t\t" @@ -1507,16 +1525,17 @@ def gen_def_virtual(self): text += ", " if len(self.args) > 0: text = text[:-2] - text += ")\n\t{" + text += f"){self.gen_post_qualifiers()}\n\t{{" for arg in self.args: text += arg.gen_translation_cpp() - text += "\n\t\t" + return_stmt = "return " if self.ret_type.name != "void" else "" + text += f"\n\t\t{return_stmt}" if self.member_of == None: text += "::" + self.namespace + "::" + self.alias + "(" elif self.is_static: text += self.member_of.namespace + "::" + self.member_of.name + "::" + self.name + "(" else: - text += "py_" + self.alias + "(" + text += f"const_cast<{self.member_of.name}*>(this)->py_" + self.alias + "(" for arg in self.args: text += arg.gen_call_cpp() + ", " if len(self.args) > 0: @@ -1547,11 +1566,13 @@ def gen_default_impl(self): call_string = call_string[0:-2] call_string += ");" + return_stmt = "return " if self.ret_type.name != "void" else "" + text += ")\n\t\t{" - text += "\n\t\t\tif(boost::python::override py_" + self.alias + " = this->get_override(\"py_" + self.alias + "\"))" - text += "\n\t\t\t\t" + call_string + text += "\n\t\t\tif (boost::python::override py_" + self.alias + " = this->get_override(\"py_" + self.alias + "\"))" + text += f"\n\t\t\t\t{return_stmt}" + call_string text += "\n\t\t\telse" - text += "\n\t\t\t\t" + self.member_of.name + "::" + call_string + text += f"\n\t\t\t\t{return_stmt}" + self.member_of.name + "::" + call_string text += "\n\t\t}" text += "\n\n\t\t" + self.ret_type.gen_text() + " default_py_" + self.alias + "(" @@ -1559,8 +1580,8 @@ def gen_default_impl(self): text += arg.gen_listitem() + ", " if len(self.args) > 0: text = text[:-2] - text += ")\n\t\t{" - text += "\n\t\t\tthis->" + self.member_of.name + "::" + call_string + text += f")\n\t\t{{" + text += f"\n\t\t\t{return_stmt}this->" + self.member_of.name + "::" + call_string text += "\n\t\t}" return text @@ -1584,9 +1605,9 @@ def gen_boost_py(self): for a in self.args: text += a.gen_listitem_hash() + ", " if len(self.args) > 0: - text = text[0:-2] + ")>" + text = text[0:-2] + f"){self.gen_post_qualifiers(True)}>" else: - text += "void)>" + text += f"void){self.gen_post_qualifiers(True)}>" if self.is_operator: text += "(\"" + wrappable_operators[self.name.replace("operator","")] + "\"" diff --git a/yosys/passes/cmds/Makefile.inc b/yosys/passes/cmds/Makefile.inc index 29b3a1132ad..d7e572462b0 100644 --- a/yosys/passes/cmds/Makefile.inc +++ b/yosys/passes/cmds/Makefile.inc @@ -46,3 +46,5 @@ OBJS += passes/cmds/printattrs.o OBJS += passes/cmds/sta.o OBJS += passes/cmds/clean_zerowidth.o OBJS += passes/cmds/xprop.o +OBJS += passes/cmds/dft_tag.o +OBJS += passes/cmds/future.o diff --git a/yosys/passes/cmds/autoname.cc b/yosys/passes/cmds/autoname.cc index 6019c61534f..737bd3e58be 100644 --- a/yosys/passes/cmds/autoname.cc +++ b/yosys/passes/cmds/autoname.cc @@ -24,8 +24,8 @@ PRIVATE_NAMESPACE_BEGIN int autoname_worker(Module *module, const dict& wire_score) { - dict> proposed_cell_names; - dict> proposed_wire_names; + dict> proposed_cell_names; + dict> proposed_wire_names; int best_score = -1; for (auto cell : module->selected_cells()) { @@ -36,7 +36,7 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); - IdString new_name(bit.wire->name.str() + suffix); + string new_name(bit.wire->name.str() + suffix); int score = wire_score.at(bit.wire); if (cell->output(conn.first)) score = 0; score = 10000*score + new_name.size(); @@ -54,7 +54,7 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) suffix = stringf("_%s", log_id(conn.first)); - IdString new_name(cell->name.str() + suffix); + string new_name(cell->name.str() + suffix); int score = wire_score.at(bit.wire); if (cell->output(conn.first)) score = 0; score = 10000*score + new_name.size(); @@ -71,7 +71,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_cell_names) { if (best_score*2 < it.second.first) continue; - IdString n = module->uniquify(it.second.second); + IdString n = module->uniquify(IdString(it.second.second)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } @@ -79,7 +79,7 @@ int autoname_worker(Module *module, const dict& wire_score) for (auto &it : proposed_wire_names) { if (best_score*2 < it.second.first) continue; - IdString n = module->uniquify(it.second.second); + IdString n = module->uniquify(IdString(it.second.second)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } diff --git a/yosys/passes/cmds/chformal.cc b/yosys/passes/cmds/chformal.cc index da97ff71d69..e027103bb03 100644 --- a/yosys/passes/cmds/chformal.cc +++ b/yosys/passes/cmds/chformal.cc @@ -23,6 +23,52 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +static RTLIL::IdString formal_flavor(RTLIL::Cell *cell) +{ + if (cell->type != ID($check)) + return cell->type; + + std::string flavor_param = cell->getParam(ID(FLAVOR)).decode_string(); + if (flavor_param == "assert") + return ID($assert); + else if (flavor_param == "assume") + return ID($assume); + else if (flavor_param == "cover") + return ID($cover); + else if (flavor_param == "live") + return ID($live); + else if (flavor_param == "fair") + return ID($fair); + else + log_abort(); +} + +static void set_formal_flavor(RTLIL::Cell *cell, RTLIL::IdString flavor) +{ + if (cell->type != ID($check)) { + cell->type = flavor; + return; + } + + if (flavor == ID($assert)) + cell->setParam(ID(FLAVOR), std::string("assert")); + else if (flavor == ID($assume)) + cell->setParam(ID(FLAVOR), std::string("assume")); + else if (flavor == ID($cover)) + cell->setParam(ID(FLAVOR), std::string("cover")); + else if (flavor == ID($live)) + cell->setParam(ID(FLAVOR), std::string("live")); + else if (flavor == ID($fair)) + cell->setParam(ID(FLAVOR), std::string("fair")); + else + log_abort(); +} + +static bool is_triggered_check_cell(RTLIL::Cell * cell) +{ + return cell->type == ID($check) && cell->getParam(ID(TRG_ENABLE)).as_bool(); +} + struct ChformalPass : public Pass { ChformalPass() : Pass("chformal", "change formal constraints of the design") { } void help() override @@ -41,13 +87,18 @@ struct ChformalPass : public Pass { log(" -fair $fair cells, representing assume(s_eventually ...)\n"); log(" -cover $cover cells, representing cover() statements\n"); log("\n"); + log(" Additionally chformal will operate on $check cells corresponding to the\n"); + log(" selected constraint types.\n"); + log("\n"); log("Exactly one of the following modes must be specified:\n"); log("\n"); log(" -remove\n"); log(" remove the cells and thus constraints from the design\n"); log("\n"); log(" -early\n"); - log(" bypass FFs that only delay the activation of a constraint\n"); + log(" bypass FFs that only delay the activation of a constraint. When inputs\n"); + log(" of the bypassed FFs do not remain stable between clock edges, this may\n"); + log(" result in unexpected behavior.\n"); log("\n"); log(" -delay \n"); log(" delay activation of the constraint by clock cycles\n"); @@ -69,6 +120,11 @@ struct ChformalPass : public Pass { log(" -fair2live\n"); log(" change the roles of cells as indicated. these options can be combined\n"); log("\n"); + log(" -lower\n"); + log(" convert each $check cell into an $assert, $assume, $live, $fair or\n"); + log(" $cover cell. If the $check cell contains a message, also produce a\n"); + log(" $print cell.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { @@ -146,6 +202,10 @@ struct ChformalPass : public Pass { mode = 'c'; continue; } + if (mode == 0 && args[argidx] == "-lower") { + mode = 'l'; + continue; + } break; } extra_args(args, argidx, design); @@ -166,7 +226,7 @@ struct ChformalPass : public Pass { vector constr_cells; for (auto cell : module->selected_cells()) - if (constr_types.count(cell->type)) + if (constr_types.count(formal_flavor(cell))) constr_cells.push_back(cell); if (mode == 'r') @@ -216,6 +276,18 @@ struct ChformalPass : public Pass { } for (auto cell : constr_cells) + { + if (is_triggered_check_cell(cell)) { + if (cell->getParam(ID::TRG_WIDTH).as_int() != 1) + continue; + cell->setPort(ID::TRG, SigSpec()); + cell->setParam(ID::TRG_ENABLE, false); + cell->setParam(ID::TRG_WIDTH, 0); + cell->setParam(ID::TRG_POLARITY, false); + } + + IdString flavor = formal_flavor(cell); + while (true) { SigSpec A = sigmap(cell->getPort(ID::A)); @@ -225,8 +297,8 @@ struct ChformalPass : public Pass { break; if (!init_zero.count(EN)) { - if (cell->type == ID($cover)) break; - if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break; + if (flavor == ID($cover)) break; + if (flavor.in(ID($assert), ID($assume)) && !init_one.count(A)) break; } const auto &A_map = ffmap.at(A); @@ -238,25 +310,31 @@ struct ChformalPass : public Pass { cell->setPort(ID::A, A_map.first); cell->setPort(ID::EN, EN_map.first); } + } } else if (mode == 'd') { for (auto cell : constr_cells) - for (int i = 0; i < mode_arg; i++) { - SigSpec orig_a = cell->getPort(ID::A); - SigSpec orig_en = cell->getPort(ID::EN); + if (is_triggered_check_cell(cell)) + log_error("Cannot delay edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell)); - Wire *new_a = module->addWire(NEW_ID); - Wire *new_en = module->addWire(NEW_ID); - new_en->attributes[ID::init] = State::S0; + for (int i = 0; i < mode_arg; i++) + { + SigSpec orig_a = cell->getPort(ID::A); + SigSpec orig_en = cell->getPort(ID::EN); + + Wire *new_a = module->addWire(NEW_ID); + Wire *new_en = module->addWire(NEW_ID); + new_en->attributes[ID::init] = State::S0; - module->addFf(NEW_ID, orig_a, new_a); - module->addFf(NEW_ID, orig_en, new_en); + module->addFf(NEW_ID, orig_a, new_a); + module->addFf(NEW_ID, orig_en, new_en); - cell->setPort(ID::A, new_a); - cell->setPort(ID::EN, new_en); + cell->setPort(ID::A, new_a); + cell->setPort(ID::EN, new_en); + } } } else @@ -278,21 +356,76 @@ struct ChformalPass : public Pass { if (mode =='p') { for (auto cell : constr_cells) - module->addCover(NEW_ID_SUFFIX("coverenable"), - cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); + { + if (cell->type == ID($check)) { + Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check)); + cover->attributes = cell->attributes; + cover->parameters = cell->parameters; + cover->setParam(ID(FLAVOR), Const("cover")); + + for (auto const &conn : cell->connections()) + if (!conn.first.in(ID::A, ID::EN)) + cover->setPort(conn.first, conn.second); + cover->setPort(ID::A, cell->getPort(ID::EN)); + cover->setPort(ID::EN, State::S1); + } else { + module->addCover(NEW_ID_SUFFIX("coverenable"), + cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); + } + } } else if (mode == 'c') { - for (auto cell : constr_cells) - if (assert2assume && cell->type == ID($assert)) - cell->type = ID($assume); - else if (assume2assert && cell->type == ID($assume)) - cell->type = ID($assert); - else if (live2fair && cell->type == ID($live)) - cell->type = ID($fair); - else if (fair2live && cell->type == ID($fair)) - cell->type = ID($live); + for (auto cell : constr_cells) { + IdString flavor = formal_flavor(cell); + if (assert2assume && flavor == ID($assert)) + set_formal_flavor(cell, ID($assume)); + else if (assume2assert && flavor == ID($assume)) + set_formal_flavor(cell, ID($assert)); + else if (live2fair && flavor == ID($live)) + set_formal_flavor(cell, ID($fair)); + else if (fair2live && flavor == ID($fair)) + set_formal_flavor(cell, ID($live)); + } + } + else + if (mode == 'l') + { + for (auto cell : constr_cells) { + if (cell->type != ID($check)) + continue; + + if (is_triggered_check_cell(cell)) + log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", log_id(cell)); + + + Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell)); + + plain_cell->attributes = cell->attributes; + + SigBit sig_a = cell->getPort(ID::A); + SigBit sig_en = cell->getPort(ID::EN); + + plain_cell->setPort(ID::A, sig_a); + plain_cell->setPort(ID::EN, sig_en); + + if (plain_cell->type.in(ID($assert), ID($assume))) + sig_a = module->Not(NEW_ID, sig_a); + + SigBit combined_en = module->And(NEW_ID, sig_a, sig_en); + + module->swap_names(cell, plain_cell); + + if (cell->getPort(ID::ARGS).empty()) { + module->remove(cell); + } else { + cell->type = ID($print); + cell->setPort(ID::EN, combined_en); + cell->unsetPort(ID::A); + cell->unsetParam(ID(FLAVOR)); + } + } } } } diff --git a/yosys/passes/cmds/dft_tag.cc b/yosys/passes/cmds/dft_tag.cc new file mode 100644 index 00000000000..2b2340dab53 --- /dev/null +++ b/yosys/passes/cmds/dft_tag.cc @@ -0,0 +1,1015 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2022 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/celltypes.h" +#include "kernel/ff.h" +#include "kernel/modtools.h" +#include "kernel/sigtools.h" +#include "kernel/yosys.h" +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct DftTagOptions { + bool tag_public = false; + bool overwrite_only = false; +}; + +struct DftTagWorker { + Module *module; + DftTagOptions options; + ModWalker modwalker; + SigMap &sigmap; + FfInitVals initvals; + + struct tag_set { + int index = 0; + + tag_set(int index = 0) : index(index) {} + + bool operator<(const tag_set &other) const { return index < other.index; } + bool operator==(const tag_set &other) const { return index == other.index; } + + unsigned int hash() const { return hash_ops::hash(index); } + + bool empty() const { return index == 0; } + }; + + idict> tag_sets; + + pool tmp_tag_set; + dict, tag_set> tag_set_union_cache; + + dict tagged_signals; + + dict> tag_groups; + dict group_of_tag; + pool all_tags; + + pool pending_cells; + std::deque pending_cell_queue; + + dict, SigBit> tag_signals; + + // Uses SigSpec instead of SigBit so we can use coarse grained cells to combine the individual tags + dict, SigSpec> tag_group_signals; + + pool warned_cells; + + DftTagWorker(Module *module, DftTagOptions options) : + module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap) + { + modwalker.setup(module); + initvals.set(&modwalker.sigmap, module); + tag_sets(tmp_tag_set); + } + + void resolve_overwrites() + { + std::vector overwrite_cells; + std::vector original_cells; + + bool design_changed = false; + + for (auto cell : module->cells()) { + if (cell->type == ID($overwrite_tag)) + overwrite_cells.push_back(cell); + + if (cell->type == ID($original_tag)) + original_cells.push_back(cell); + } + + for (auto cell : overwrite_cells) { + log_debug("Applying $overwrite_tag %s for signal %s\n", log_id(cell->name), log_signal(cell->getPort(ID::A))); + SigSpec orig_signal = cell->getPort(ID::A); + SigSpec interposed_signal = divert_users(orig_signal); + auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal); + modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections + design_changed = true; + } + + for (auto cell : overwrite_cells) { + module->remove(cell); + } + for (auto cell : original_cells) { + cell->type = ID($get_tag); + } + + if (design_changed) + modwalker.setup(module); + } + + SigSpec divert_users(SigSpec signal) + { + SigSpec signal_mapped = sigmap(signal); + signal_mapped.sort_and_unify(); + if (GetSize(signal_mapped) < GetSize(signal)) + log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal)); + SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal)); + for (int i = 0; i < GetSize(new_wire); ++i) + divert_users(signal[i], new_wire[i]); + return new_wire; + } + + void divert_users(SigBit driver_bit, SigBit interposed_bit) + { + dict, SigSpec> updated_ports; + // TODO also check module outputs + auto found = modwalker.signal_consumers.find(driver_bit); + if (found == modwalker.signal_consumers.end()) + return; + for (auto &consumer : found->second) { + if (consumer.cell->type.in(ID($original_tag))) + continue; + if (sigmap(consumer.cell->getPort(consumer.port)[consumer.offset]) != driver_bit) + continue; + std::pair key = {consumer.cell, consumer.port}; + auto found_port = updated_ports.find(key); + if (found_port == updated_ports.end()) { + updated_ports.emplace(key, consumer.cell->getPort(consumer.port)); + } + updated_ports[key][consumer.offset] = interposed_bit; + } + for (auto &update : updated_ports) { + update.first.first->setPort(update.first.second, update.second); + modwalker.add_cell(update.first.first); // Make sure the next $overwrite_tag sees the new connections + } + } + + const pool &tag_pool(tag_set set) { return tag_sets[set.index]; } + + tag_set singleton(IdString tag) + { + tmp_tag_set.clear(); + tmp_tag_set.emplace(tag); + return tag_sets(tmp_tag_set); + } + + tag_set merge(tag_set a, tag_set b) + { + if (b < a) + std::swap(a, b); + if (a.empty() || a == b) + return b; + auto found = tag_set_union_cache.find(std::make_pair(a, b)); + if (found == tag_set_union_cache.end()) { + tmp_tag_set.clear(); + auto &a_tags = tag_pool(a); + auto &b_tags = tag_pool(b); + tmp_tag_set.insert(a_tags.begin(), a_tags.end()); + tmp_tag_set.insert(b_tags.begin(), b_tags.end()); + tag_set result = tag_sets(tmp_tag_set); + tag_set_union_cache.emplace(std::make_pair(a, b), result); + return result; + } + return found->second; + } + + tag_set tags(SigBit bit) + { + sigmap.apply(bit); + auto found = tagged_signals.find(bit); + if (found != tagged_signals.end()) + return found->second; + return tag_set(); + } + + tag_set tags(SigSpec sig) + { + tag_set result; + for (auto bit : sig) + result = merge(result, tags(bit)); + return result; + } + + tag_set tags(Cell *cell) + { + tag_set result; + for (auto &conn : cell->connections()) { + if (cell->input(conn.first)) + result = merge(result, tags(conn.second)); + } + return result; + } + + void add_tags(SigBit bit, tag_set new_tags) + { + sigmap.apply(bit); + auto &tags = tagged_signals[bit]; + tag_set merged_tags = merge(tags, new_tags); + if (merged_tags == tags) + return; + tags = merged_tags; + auto it = modwalker.signal_consumers.find(bit); + if (it == modwalker.signal_consumers.end()) + return; + for (auto &consumer : it->second) + if (pending_cells.insert(consumer.cell).second) + pending_cell_queue.push_back(consumer.cell); + } + + void add_tags(SigSpec sig, tag_set new_tags) + { + for (auto bit : sigmap(sig)) + add_tags(bit, new_tags); + } + + void add_tags(Cell *cell, tag_set new_tags) + { + for (auto &conn : cell->connections()) + if (cell->output(conn.first)) + add_tags(conn.second, new_tags); + } + + void forward_tags(SigSpec dst, SigSpec src) + { + log_assert(GetSize(dst) == GetSize(src)); + for (int i = 0; i < GetSize(dst); i++) + add_tags(dst[i], tags(src[i])); + } + + void propagate_tags() + { + for (auto cell : module->cells()) { + if (cell->type == ID($set_tag)) { + pending_cells.insert(cell); + pending_cell_queue.push_back(cell); + } + } + + while (!pending_cell_queue.empty()) { + Cell *cell = pending_cell_queue.front(); + pending_cell_queue.pop_front(); + pending_cells.erase(cell); + + propagate_tags(cell); + } + } + + SigBit tag_signal(IdString tag, SigBit bit) + { + sigmap.apply(bit); + if (!bit.is_wire()) + return State::S0; // Constant value - no tags + + auto found = tag_signals.find(std::make_pair(tag, bit)); + if (found != tag_signals.end()) + return found->second; + + if (!tag_pool(tags(bit)).count(tag)) + return State::S0; // Statically known to not have this tag + + // TODO handle module inputs + auto drivers = modwalker.signal_drivers.find(bit); + if (drivers == modwalker.signal_drivers.end() || drivers->second.empty()) + return State::S0; // No driver - no tags + + log_assert(drivers->second.size() == 1); + auto driver = *drivers->second.begin(); + + emit_tag_signals(tag, driver.cell); + + found = tag_signals.find(std::make_pair(tag, bit)); + log_assert(found != tag_signals.end()); + return found->second; + } + + SigSpec tag_signal(IdString tag, SigSpec sig) + { + SigSpec result; + for (auto bit : sig) + result.append(tag_signal(tag, bit)); + return result; + } + + SigSpec tag_group_signal(IdString tag_group, SigSpec sig) + { + sigmap.apply(sig); + if (sig.is_fully_const() || tag_groups.count(tag_group) == 0) + return Const(0, GetSize(sig)); + + auto found = tag_group_signals.find(std::make_pair(tag_group, sig)); + if (found != tag_group_signals.end()) + return found->second; + + SigSpec combined; + + for (auto &tag : tag_groups[tag_group]) { + auto tag_sig = tag_signal(tag, sig); + + if (!GetSize(combined)) + combined = tag_sig; + else + combined = autoOr(NEW_ID, combined, tag_sig); + } + + if (!GetSize(combined)) + combined = Const(0, GetSize(sig)); + + tag_group_signals.emplace(std::make_pair(tag_group, sig), combined); + return combined; + } + + void emit_tag_signal(IdString tag, SigBit bit, SigBit tag_bit) + { + sigmap.apply(bit); + sigmap.apply(tag_bit); + + if (!tag_pool(tags(bit)).count(tag)) + return; + + auto key = std::make_pair(tag, bit); + auto found = tag_signals.find(key); + if (found != tag_signals.end()) { + module->connect(found->second, tag_bit); + return; + } + tag_signals.emplace(key, tag_bit); + } + + void emit_tag_signal(IdString tag, SigSpec sig, SigSpec tag_sig) + { + log_assert(GetSize(sig) == GetSize(tag_sig)); + for (int i = 0; i < GetSize(sig); i++) + emit_tag_signal(tag, sig[i], tag_sig[i]); + } + + void emit_tag_signals(IdString tag, Cell *cell) + { + if (!pending_cells.insert(cell).second) { + // We have a cycle, emit placeholder wires which will be connected + // when the outer call for this tag/cell returns + for (auto &conn : cell->connections()) + if (cell->output(conn.first)) + emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second))); + + return; + } + + process_cell(tag, cell); + + pending_cells.erase(cell); + } + + void propagate_tags(Cell *cell) + { + if (cell->type == ID($set_tag)) { + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + if (all_tags.insert(tag).second) { + auto group_sep = tag.str().find(':'); + IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag; + tag_groups[tag_group].insert(tag); + group_of_tag[tag] = tag_group; + } + + auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(ID::A); + // TODO handle constant set/clr masks + add_tags(sig_y, singleton(tag)); + forward_tags(sig_y, sig_a); + return; + } + + if (cell->type == ID($get_tag)) { + return; + } + + if (cell->type.in(ID($not), ID($pos))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + if (cell->type.in(ID($not), ID($or))) { + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + } + forward_tags(sig_y, sig_a); + return; + } + + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + auto sig_b = cell->getPort(ID::B); + if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); + } + forward_tags(sig_y, sig_a); + forward_tags(sig_y, sig_b); + return; + } + + if (cell->type.in(ID($mux), ID($bwmux))) { + auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(ID::A); + auto &sig_b = cell->getPort(ID::B); + auto sig_s = cell->getPort(ID::S); + + if (cell->type == ID($mux)) + sig_s = SigSpec(sig_s[0], GetSize(sig_y)); + + forward_tags(sig_y, sig_a); + forward_tags(sig_y, sig_b); + forward_tags(sig_y, sig_s); + return; + } + + if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + FfData ff(&initvals, cell); + + if (ff.has_clk || ff.has_gclk) + forward_tags(ff.sig_q, ff.sig_d); + return; + } + + // Single output but, sensitive to all inputs + if (cell->type.in( + ID($le), ID($lt), ID($ge), ID($gt), + ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), + ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and), + ID($eq), ID($ne) + )) { + auto &sig_y = cell->getPort(ID::Y); + + add_tags(sig_y[0], tags(cell)); + return; + } + + + // Fallback, propagate tags from all inputs to all outputs + add_tags(cell, tags(cell)); + + if (cell->type.in( + ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_), + ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_), + + ID($assert), ID($assume) + )) { + return; + } + + // This isn't a correctness concern (unless cell is a module generating + // tags), but we may end up generating a lot of extra logic when + // reaching this + if (!warned_cells.insert(cell).second) + return; + if (cell->type.isPublic()) + log_warning("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type)); + else + log_debug("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type)); + } + + void process_cell(IdString tag, Cell *cell) + { + if (cell->type == ID($set_tag)) { + IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + + auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A)); + auto &sig_y = cell->getPort(ID::Y); + + if (cell_tag == tag) { + auto &sig_set = cell->getPort(ID::SET); + auto &sig_clr = cell->getPort(ID::CLR); + tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr)); + tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set); + } + + emit_tag_signal(tag, sig_y, tag_sig_a); + return; + } + + if (cell->type == ID($get_tag)) { + log_assert(false); + } + + if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + if (cell->type.in(ID($not), ID($or))) { + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + } + emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a)); + return; + } + + if (cell->type.in( + ID($and), ID($or), + ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_) + )) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + auto sig_b = cell->getPort(ID::B); + if (cell->type.in(ID($and), ID($or))) { + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); + } + + bool inv_a = false; + bool inv_b = false; + + if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_))) + inv_a ^= true, inv_b ^= true; + if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) + inv_b ^= true; + + if (inv_a) + sig_a = autoNot(NEW_ID, sig_a); + if (inv_b) + sig_b = autoNot(NEW_ID, sig_b); + + auto group_sig_a = tag_group_signal(tag, sig_a); + auto group_sig_b = tag_group_signal(tag, sig_b); + + auto tag_sig_a = tag_signal(tag, sig_a); + auto tag_sig_b = tag_signal(tag, sig_b); + + + // Does this input allow propagating (doesn't fix output or same tag group) + sig_a = autoOr(NEW_ID, sig_a, group_sig_a); + sig_b = autoOr(NEW_ID, sig_b, group_sig_b); + + // Mask input tags by whether the other side allows propagation + tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b); + tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a); + + + auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + auto sig_b = cell->getPort(ID::B); + if (cell->type.in(ID($xor), ID($xnor))) { + sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool()); + } + + auto tag_sig_a = tag_signal(tag, sig_a); + auto tag_sig_b = tag_signal(tag, sig_b); + + auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + + if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) { + auto &sig_y = cell->getPort(ID::Y); + auto &sig_a = cell->getPort(ID::A); + auto &sig_b = cell->getPort(ID::B); + auto sig_s = cell->getPort(ID::S); + + if (cell->type == ID($mux)) + sig_s = SigSpec(sig_s[0], GetSize(sig_y)); + + auto group_sig_a = tag_group_signal(tag, sig_a); + auto group_sig_b = tag_group_signal(tag, sig_b); + auto group_sig_s = tag_group_signal(tag, sig_s); + + auto prop_s = autoOr(NEW_ID, + autoXor(NEW_ID, sig_a, sig_b), + autoOr(NEW_ID, group_sig_a, group_sig_b)); + + auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s); + auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s); + + auto tag_sig_a = tag_signal(tag, sig_a); + auto tag_sig_b = tag_signal(tag, sig_b); + auto tag_sig_s = tag_signal(tag, sig_s); + + tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a); + tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b); + tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s); + + auto tag_sig = autoOr(NEW_ID, tag_sig_s, + autoOr(NEW_ID, tag_sig_a, tag_sig_b)); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + auto sig_b = cell->getPort(ID::B); + int width = std::max(GetSize(sig_a), GetSize(sig_b)); + sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); + + auto group_sig_a = tag_group_signal(tag, sig_a); + auto group_sig_b = tag_group_signal(tag, sig_b); + + auto tag_sig_a = tag_signal(tag, sig_a); + auto tag_sig_b = tag_signal(tag, sig_b); + + auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + // The output can only be affected by the tagged inputs if all group-untagged bits are equal + + auto masked_a = autoOr(NEW_ID, sig_a, group_sig); + auto masked_b = autoOr(NEW_ID, sig_b, group_sig); + + auto prop = autoEq(NEW_ID, masked_a, masked_b); + + auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + tag_sig.extend_u0(GetSize(sig_y), false); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + + if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + auto sig_b = cell->getPort(ID::B); + int width = std::max(GetSize(sig_a), GetSize(sig_b)); + sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool()); + sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool()); + + if (cell->type.in(ID($gt), ID($le))) + std::swap(sig_a, sig_b); + + auto group_sig_a = tag_group_signal(tag, sig_a); + auto group_sig_b = tag_group_signal(tag, sig_b); + + auto tag_sig_a = tag_signal(tag, sig_a); + auto tag_sig_b = tag_signal(tag, sig_b); + + auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b); + // The output can only be affected by the tagged inputs if the greatest possible sig_a is + // greater or equal to the least possible sig_b + auto masked_a = autoOr(NEW_ID, sig_a, group_sig); + auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig)); + + auto prop = autoGe(NEW_ID, masked_a, masked_b); + + auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b})); + tag_sig.extend_u0(GetSize(sig_y), false); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) { + auto &sig_y = cell->getPort(ID::Y); + auto sig_a = cell->getPort(ID::A); + + auto group_sig_a = tag_group_signal(tag, sig_a); + auto tag_sig_a = tag_signal(tag, sig_a); + + if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) + sig_a = autoNot(NEW_ID, sig_a); + + auto filled = autoOr(NEW_ID, sig_a, group_sig_a); + + auto prop = autoReduceAnd(NEW_ID, filled); + auto tagged = autoReduceOr(NEW_ID, tag_sig_a); + auto tag_sig = autoAnd(NEW_ID, prop, tagged); + tag_sig.extend_u0(GetSize(sig_y), false); + emit_tag_signal(tag, sig_y, tag_sig); + return; + } + + if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) { + FfData ff(&initvals, cell); + // TODO handle some more variants + if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) { + if (ff.has_clk && !tags(ff.sig_clk).empty()) + log_warning("Tags on CLK input ignored for %s (%s)\n", log_id(cell), log_id(cell->type)); + + int width = ff.width; + + auto sig_q = ff.sig_q; + auto sig_d = ff.sig_d; + + ff.name = NEW_ID; + ff.cell = nullptr; + ff.sig_d = tag_signal(tag, ff.sig_d); + ff.sig_q = module->addWire(NEW_ID, width); + ff.is_anyinit = false; + ff.val_init = Const(0, width); + ff.emit(); + + emit_tag_signal(tag, sig_q, ff.sig_q); + return; + } else { + log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type)); + + // For unhandled FFs, the default propagation would cause combinational loops + emit_tag_signal(tag, ff.sig_q, Const(0, ff.width)); + return; + } + } + + // Fallback + SigSpec tag_input; + + for (auto &conn : cell->connections()) { + if (cell->input(conn.first)) { + auto tag_sig = tag_signal(tag, conn.second); + tag_input.append(tag_sig); + } + } + + SigBit any_tagged = autoReduceOr(NEW_ID, tag_input); + + for (auto &conn : cell->connections()) { + if (cell->output(conn.first)) { + emit_tag_signal(tag, conn.second, SigSpec(any_tagged, GetSize(conn.second))); + } + } + + // As fallback we propagate all tags from all inputs to all outputs, + // which is an over-approximation (unless the cell is a module that + // generates tags itself in which case it could be arbitrary). + if (warned_cells.insert(cell).second) + log_warning("Unhandled cell %s (%s) while emitting tag signals\n", log_id(cell), log_id(cell->type)); + } + + void emit_tags() + { + warned_cells.clear(); + std::vector get_tag_cells; + for (auto cell : module->selected_cells()) + if (cell->type == ID($get_tag)) + get_tag_cells.push_back(cell); + + for (auto cell : get_tag_cells) { + auto &sig_a = cell->getPort(ID::A); + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + + tag_signal(tag, sig_a); + } + + if (options.tag_public) + { + std::vector public_wires; + + for (auto wire : module->selected_wires()) + if (wire->name.isPublic()) + public_wires.push_back(wire); + + for (auto wire : public_wires) { + for (auto tag : tag_pool(tags(SigSpec(wire)))) { + auto tag_sig = tag_signal(tag, SigSpec(wire)); + if (tag_sig.is_fully_zero()) + continue; + + int index = 0; + auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index); + auto hdlname = wire->get_hdlname_attribute(); + + if (!hdlname.empty()) + hdlname.back() += index ? + stringf(":%s_%d", tag.c_str() + 1, index) : + stringf(":%s", tag.c_str() + 1); + + auto tag_wire = module->addWire(name, wire->width); + + tag_wire->set_bool_attribute(ID::keep); + tag_wire->set_bool_attribute(ID(dft_tag)); + if (!hdlname.empty()) + tag_wire->set_hdlname_attribute(hdlname); + + module->connect(tag_wire, tag_sig); + } + } + } + } + + void replace_dft_cells() + { + std::vector get_tag_cells; + std::vector set_tag_cells; + for (auto cell : module->cells()) { + if (cell->type == ID($get_tag)) + get_tag_cells.push_back(cell); + + if (cell->type == ID($set_tag)) + set_tag_cells.push_back(cell); + + log_assert(!cell->type.in(ID($overwrite_tag), ID($original_tag))); + } + + for (auto cell : set_tag_cells) { + auto &sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(ID::Y); + module->connect(sig_y, sig_a); + module->remove(cell); + } + + for (auto cell : get_tag_cells) { + auto &sig_a = cell->getPort(ID::A); + auto &sig_y = cell->getPort(ID::Y); + IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str()); + + auto tag_sig = tag_signal(tag, sig_a); + module->connect(sig_y, tag_sig); + module->remove(cell); + } + } + + + SigSpec autoAnd(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a.is_fully_zero() || sig_b.is_fully_ones() || sig_a == sig_b) + return sig_a; + if (sig_a.is_fully_ones() || sig_b.is_fully_zero()) + return sig_b; + + return module->And(name, sig_a, sig_b); + } + + SigSpec autoOr(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a.is_fully_ones() || sig_b.is_fully_zero() || sig_a == sig_b) + return sig_a; + if (sig_a.is_fully_zero() || sig_b.is_fully_ones()) + return sig_b; + + return module->Or(name, sig_a, sig_b); + } + + SigSpec autoXor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a == sig_b) + return Const(State::S0, GetSize(sig_a)); + if (sig_a.is_fully_zero()) + return sig_b; + if (sig_b.is_fully_zero()) + return sig_a; + if (sig_a.is_fully_ones()) + return autoNot(name, sig_b); + if (sig_b.is_fully_ones()) + return autoNot(name, sig_a); + return module->Xor(name, sig_a, sig_b); + } + + SigSpec autoXnor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a == sig_b) + return Const(State::S1, GetSize(sig_a)); + if (sig_a.is_fully_ones()) + return sig_b; + if (sig_b.is_fully_ones()) + return sig_a; + if (sig_a.is_fully_zero()) + return autoNot(name, sig_b); + if (sig_b.is_fully_zero()) + return autoNot(name, sig_a); + return module->Xnor(name, sig_a, sig_b); + } + + SigSpec autoNot(IdString name, const SigSpec &sig_a) + { + if (sig_a.is_fully_const()) { + auto const_val = sig_a.as_const(); + for (auto &bit : const_val.bits) + bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit; + return const_val; + } + return module->Not(name, sig_a); + } + + SigSpec autoEq(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a == sig_b) + return State::S1; + for (int i = 0; i < GetSize(sig_a); i++) { + auto bit_a = sig_a[i]; + auto bit_b = sig_b[i]; + if (bit_a.is_wire() || bit_b.is_wire()) + continue; + if ((bit_a.data == State::S0 && bit_b.data == State::S1) || + (bit_a.data == State::S1 && bit_b.data == State::S0)) + return State::S0; + } + + return module->Eq(name, sig_a, sig_b); + } + + SigSpec autoGe(IdString name, const SigSpec &sig_a, const SigSpec &sig_b) + { + log_assert(GetSize(sig_a) == GetSize(sig_b)); + if (sig_a == sig_b || sig_a.is_fully_ones()) + return State::S1; + if (sig_b.is_fully_zero()) + return State::S1; + + return module->Ge(name, sig_a, sig_b); + } + + SigSpec autoReduceAnd(IdString name, const SigSpec &sig_a) + { + if (GetSize(sig_a) == 0) + return State::S1; + + if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a))) + return sig_a[0]; + for (auto bit : sig_a) + if (!bit.is_wire() && bit.data == State::S0) + return State::S0; + if (sig_a.is_fully_ones()) + return State::S1; + return module->ReduceAnd(name, sig_a); + } + + SigSpec autoReduceOr(IdString name, const SigSpec &sig_a) + { + if (GetSize(sig_a) == 0) + return State::S0; + + if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a))) + return sig_a[0]; + for (auto bit : sig_a) + if (!bit.is_wire() && bit.data == State::S1) + return State::S1; + if (sig_a.is_fully_zero()) + return State::S0; + return module->ReduceOr(name, sig_a); + } +}; + +struct DftTagPass : public Pass { + DftTagPass() : Pass("dft_tag", "create tagging logic for data flow tracking") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" dft_tag [options] [selection]\n"); + log("\n"); + log("This pass... TODO\n"); + log("\n"); + log(" -overwrite-only\n"); + log(" Only process $overwrite_tag and $original_tag cells.\n"); + log(" -tag-public\n"); + log(" For each public wire that may carry tagged data, create a new public\n"); + log(" wire (named :) that carries the tag bits. Note\n"); + log(" that without this, tagging logic will only be emitted as required\n"); + log(" for uses of $get_tag.\n"); + log("\n"); + } + + void execute(std::vector args, RTLIL::Design *design) override + { + DftTagOptions options; + + log_header(design, "Executing DFT_TAG pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-tag-public") { + options.tag_public = true; + continue; + } + if (args[argidx] == "-overwrite-only") { + options.overwrite_only = true; + continue; + } + break; + } + + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + DftTagWorker worker(module, options); + + log_debug("Resolve overwrite_tag and original_tag.\n"); + worker.resolve_overwrites(); + + if (options.overwrite_only) + continue; + + log_debug("Propagate tagged signals.\n"); + worker.propagate_tags(); + + log_debug("Emit tag signals and logic.\n"); + worker.emit_tags(); + + log_debug("Replace dft cells.\n"); + worker.replace_dft_cells(); + } + } +} DftTagPass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/passes/cmds/future.cc b/yosys/passes/cmds/future.cc new file mode 100644 index 00000000000..b03613c9bd2 --- /dev/null +++ b/yosys/passes/cmds/future.cc @@ -0,0 +1,140 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 Jannis Harder + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/celltypes.h" +#include "kernel/ff.h" +#include "kernel/ffinit.h" +#include "kernel/modtools.h" +#include "kernel/sigtools.h" +#include "kernel/utils.h" +#include "kernel/yosys.h" +#include + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct FutureOptions { +}; + +struct FutureWorker { + Module *module; + FutureOptions options; + ModWalker modwalker; + SigMap &sigmap; + FfInitVals initvals; + + dict future_ff_signals; + + FutureWorker(Module *module, FutureOptions options) : + module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap) + { + modwalker.setup(module); + initvals.set(&modwalker.sigmap, module); + + std::vector replaced_cells; + for (auto cell : module->selected_cells()) { + if (cell->type != ID($future_ff)) + continue; + + module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A))); + replaced_cells.push_back(cell); + } + + for (auto cell : replaced_cells) { + module->remove(cell); + } + } + + SigSpec future_ff(SigSpec sig) + { + for (auto &bit : sig) { + bit = future_ff(bit); + } + return sig; + } + + SigBit future_ff(SigBit bit) + { + if (!bit.is_wire()) + return bit; + + auto found = future_ff_signals.find(bit); + if (found != future_ff_signals.end()) + return found->second; + + auto found_driver = modwalker.signal_drivers.find(bit); + if (found_driver == modwalker.signal_drivers.end() || found_driver->second.size() < 1) + log_error("No driver for future_ff target signal %s found\n", log_signal(bit)); + if (found_driver->second.size() > 1) + log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit)); + auto driver = *found_driver->second.begin(); + if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit)) + log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type)); + + FfData ff(&initvals, driver.cell); + + if (!ff.has_clk && !ff.has_gclk) + log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit), + log_id(driver.cell->type)); + + ff.unmap_ce_srst(); + + // We insert all bits into the mapping, because unmap_ce_srst might + // have removed the cell which is still present in the modwalker data. + // By inserting all bits driven by th FF we ensure that we'll never use + // that stale modwalker data again. + + for (int i = 0; i < ff.width; ++i) { + future_ff_signals.emplace(ff.sig_q[i], ff.sig_d[i]); + } + + return future_ff_signals.at(bit); + } +}; + +struct FuturePass : public Pass { + FuturePass() : Pass("future", "resolve future sampled value functions") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" future [options] [selection]\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + FutureOptions options; + + log_header(design, "Executing FUTURE pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + + break; + } + + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) { + FutureWorker worker(module, options); + } + } +} FuturePass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/passes/cmds/glift.cc b/yosys/passes/cmds/glift.cc index 439ded07685..8553b02a541 100644 --- a/yosys/passes/cmds/glift.cc +++ b/yosys/passes/cmds/glift.cc @@ -582,7 +582,7 @@ struct GliftPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (topo_modules.database.count(tpl) == 0) + if (!topo_modules.has_node(tpl)) worklist.push_back(tpl); topo_modules.edge(tpl, module); non_top_modules.insert(cell->type); diff --git a/yosys/passes/cmds/plugin.cc b/yosys/passes/cmds/plugin.cc index 08b4aa8c4ee..4ad7c165b1e 100644 --- a/yosys/passes/cmds/plugin.cc +++ b/yosys/passes/cmds/plugin.cc @@ -103,7 +103,6 @@ void load_plugin(std::string filename, std::vector aliases) loaded_plugins[orig_filename] = hdl; Pass::init_register(); - } } diff --git a/yosys/passes/cmds/scc.cc b/yosys/passes/cmds/scc.cc index 81881832cd7..197bd931966 100644 --- a/yosys/passes/cmds/scc.cc +++ b/yosys/passes/cmds/scc.cc @@ -27,7 +27,6 @@ #include "kernel/log.h" #include #include -#include USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -39,18 +38,18 @@ struct SccWorker SigMap sigmap; CellTypes ct, specifyCells; - std::set workQueue; - std::map> cellToNextCell; - std::map cellToPrevSig, cellToNextSig; + pool workQueue; + dict> cellToNextCell; + dict cellToPrevSig, cellToNextSig; - std::map> cellLabels; - std::map cellDepth; - std::set cellsOnStack; + dict> cellLabels; + dict cellDepth; + pool cellsOnStack; std::vector cellStack; int labelCounter; - std::map cell2scc; - std::vector> sccList; + dict cell2scc; + std::vector> sccList; void run(RTLIL::Cell *cell, int depth, int maxDepth) { @@ -85,7 +84,7 @@ struct SccWorker else { log("Found an SCC:"); - std::set scc; + pool scc; while (cellsOnStack.count(cell) > 0) { RTLIL::Cell *c = cellStack.back(); cellStack.pop_back(); @@ -199,11 +198,11 @@ struct SccWorker for (auto cell : workQueue) { - cellToNextCell[cell] = sigToNextCells.find(cellToNextSig[cell]); + sigToNextCells.find(cellToNextSig[cell], cellToNextCell[cell]); if (!nofeedbackMode && cellToNextCell[cell].count(cell)) { log("Found an SCC:"); - std::set scc; + pool scc; log(" %s", RTLIL::id2cstr(cell->name)); cell2scc[cell] = sccList.size(); scc.insert(cell); @@ -231,7 +230,7 @@ struct SccWorker { for (int i = 0; i < int(sccList.size()); i++) { - std::set &cells = sccList[i]; + pool &cells = sccList[i]; RTLIL::SigSpec prevsig, nextsig, sig; for (auto cell : cells) { @@ -295,7 +294,7 @@ struct SccPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - std::map setAttr; + dict setAttr; bool allCellTypes = false; bool selectMode = false; bool nofeedbackMode = false; diff --git a/yosys/passes/cmds/show.cc b/yosys/passes/cmds/show.cc index 0dc5c452c09..8c2695dbe7f 100644 --- a/yosys/passes/cmds/show.cc +++ b/yosys/passes/cmds/show.cc @@ -539,7 +539,7 @@ struct ShowWorker std::string proc_src = RTLIL::unescape_id(proc->name); if (proc->attributes.count(ID::src) > 0) proc_src = proc->attributes.at(ID::src).decode_string(); - fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\"];\n", pidx, findLabel(proc->name.str()), proc_src.c_str()); + fprintf(f, "p%d [shape=box, style=rounded, label=\"PROC %s\\n%s\", %s];\n", pidx, findLabel(proc->name.str()), proc_src.c_str(), findColor(proc->name).c_str()); } for (auto &conn : module->connections()) @@ -575,7 +575,7 @@ struct ShowWorker } else { net_conn_map[right_node].in.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); net_conn_map[left_node].out.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); - fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\", %s];\n", single_idx_count++, findColor(conn).c_str()); + fprintf(f, "x%d [shape=point, %s];\n", single_idx_count++, findColor(conn).c_str()); } } } diff --git a/yosys/passes/cmds/stat.cc b/yosys/passes/cmds/stat.cc index f0021cf8769..d34373c1c0e 100644 --- a/yosys/passes/cmds/stat.cc +++ b/yosys/passes/cmds/stat.cc @@ -366,7 +366,7 @@ struct StatPass : public Pass { log(" use cell area information from the provided liberty file\n"); log("\n"); log(" -tech \n"); - log(" print area estemate for the specified technology. Currently supported\n"); + log(" print area estimate for the specified technology. Currently supported\n"); log(" values for : xilinx, cmos\n"); log("\n"); log(" -width\n"); diff --git a/yosys/passes/cmds/xprop.cc b/yosys/passes/cmds/xprop.cc index 5e78ff9fce4..310d6d773d5 100644 --- a/yosys/passes/cmds/xprop.cc +++ b/yosys/passes/cmds/xprop.cc @@ -493,8 +493,9 @@ struct XpropWorker auto sig_b = cell->getPort(ID::B); auto name = cell->name; + auto type = cell->type; module->remove(cell); - if (cell->type == ID($eqx)) + if (type == ID($eqx)) module->addEq(name, sig_a, sig_b, sig_y); else module->addNe(name, sig_a, sig_b, sig_y); @@ -534,7 +535,7 @@ struct XpropWorker auto enc_b = encoded(sig_b); auto enc_y = encoded(sig_y, true); - if (cell->type.in(ID($or), ID($_OR_))) + if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_))) enc_a.invert(), enc_b.invert(), enc_y.invert(); if (cell->type.in(ID($_NAND_), ID($_NOR_))) enc_y.invert(); @@ -1027,12 +1028,25 @@ struct XpropWorker for (auto wire : module->selected_wires()) { if (wire->port_input || wire->port_output || !wire->name.isPublic()) continue; - auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str())); - auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str())); + int index_d = 0; + int index_x = 0; + auto name_d = module->uniquify(stringf("%s_d", wire->name.c_str()), index_d); + auto name_x = module->uniquify(stringf("%s_x", wire->name.c_str()), index_x); + + auto hdlname = wire->get_hdlname_attribute(); auto wire_d = module->addWire(name_d, GetSize(wire)); auto wire_x = module->addWire(name_x, GetSize(wire)); + if (!hdlname.empty()) { + auto hdlname_d = hdlname; + auto hdlname_x = hdlname; + hdlname_d.back() += index_d ? stringf("_d_%d", index_d) : "_d"; + hdlname_x.back() += index_x ? stringf("_x_%d", index_x) : "_x"; + wire_d->set_hdlname_attribute(hdlname_d); + wire_x->set_hdlname_attribute(hdlname_x); + } + auto enc = encoded(wire); module->connect(wire_d, enc.is_1); module->connect(wire_x, enc.is_x); diff --git a/yosys/passes/equiv/equiv_simple.cc b/yosys/passes/equiv/equiv_simple.cc index 7621341a7c3..2c9d829140b 100644 --- a/yosys/passes/equiv/equiv_simple.cc +++ b/yosys/passes/equiv/equiv_simple.cc @@ -60,7 +60,7 @@ struct EquivSimpleWorker for (auto &conn : cell->connections()) if (yosys_celltypes.cell_input(cell->type, conn.first)) for (auto bit : sigmap(conn.second)) { - if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) { + if (RTLIL::builtin_ff_cell_types().count(cell->type)) { if (!conn.first.in(ID::CLK, ID::C)) next_seed.insert(bit); } else @@ -133,11 +133,9 @@ struct EquivSimpleWorker for (auto bit_a : seed_a) find_input_cone(next_seed_a, full_cells_cone_a, full_bits_cone_a, no_stop_cells, no_stop_bits, nullptr, bit_a); - next_seed_a.clear(); for (auto bit_b : seed_b) find_input_cone(next_seed_b, full_cells_cone_b, full_bits_cone_b, no_stop_cells, no_stop_bits, nullptr, bit_b); - next_seed_b.clear(); pool short_cells_cone_a, short_cells_cone_b; pool short_bits_cone_a, short_bits_cone_b; @@ -145,10 +143,12 @@ struct EquivSimpleWorker if (short_cones) { + next_seed_a.clear(); for (auto bit_a : seed_a) find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a); next_seed_a.swap(seed_a); + next_seed_b.clear(); for (auto bit_b : seed_b) find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b); next_seed_b.swap(seed_b); @@ -364,7 +364,7 @@ struct EquivSimplePass : public Pass { unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module)); for (auto cell : module->cells()) { - if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) + if (!ct.cell_known(cell->type)) continue; for (auto &conn : cell->connections()) if (yosys_celltypes.cell_output(cell->type, conn.first)) diff --git a/yosys/passes/hierarchy/hierarchy.cc b/yosys/passes/hierarchy/hierarchy.cc index bf013750365..6fcda5d7644 100644 --- a/yosys/passes/hierarchy/hierarchy.cc +++ b/yosys/passes/hierarchy/hierarchy.cc @@ -655,12 +655,23 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) log("Removed %d unused modules.\n", del_counter); } +bool set_keep_print(std::map &cache, RTLIL::Module *mod) +{ + if (cache.count(mod) == 0) + for (auto c : mod->cells()) { + RTLIL::Module *m = mod->design->module(c->type); + if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) + return cache[mod] = true; + } + return cache[mod]; +} + bool set_keep_assert(std::map &cache, RTLIL::Module *mod) { if (cache.count(mod) == 0) for (auto c : mod->cells()) { RTLIL::Module *m = mod->design->module(c->type); - if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) + if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($check), ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) return cache[mod] = true; } return cache[mod]; @@ -762,6 +773,11 @@ struct HierarchyPass : public Pass { log(" -nodefaults\n"); log(" do not resolve input port default values\n"); log("\n"); + log(" -nokeep_prints\n"); + log(" per default this pass sets the \"keep\" attribute on all modules\n"); + log(" that directly or indirectly display text on the terminal.\n"); + log(" This option disables this behavior.\n"); + log("\n"); log(" -nokeep_asserts\n"); log(" per default this pass sets the \"keep\" attribute on all modules\n"); log(" that directly or indirectly contain one or more formal properties.\n"); @@ -818,6 +834,7 @@ struct HierarchyPass : public Pass { bool keep_positionals = false; bool keep_portwidths = false; bool nodefaults = false; + bool nokeep_prints = false; bool nokeep_asserts = false; std::vector generate_cells; std::vector generate_ports; @@ -893,6 +910,10 @@ struct HierarchyPass : public Pass { nodefaults = true; continue; } + if (args[argidx] == "-nokeep_prints") { + nokeep_prints = true; + continue; + } if (args[argidx] == "-nokeep_asserts") { nokeep_asserts = true; continue; @@ -985,6 +1006,18 @@ struct HierarchyPass : public Pass { if (mod->get_bool_attribute(ID::top)) top_mod = mod; + if (top_mod == nullptr) + { + std::vector abstract_ids; + for (auto module : design->modules()) + if (module->name.begins_with("$abstract")) + abstract_ids.push_back(module->name); + for (auto abstract_id : abstract_ids) + design->module(abstract_id)->derive(design, {}); + for (auto abstract_id : abstract_ids) + design->remove(design->module(abstract_id)); + } + if (top_mod == nullptr && auto_top_mode) { log_header(design, "Finding top of design hierarchy..\n"); dict db; @@ -1091,6 +1124,15 @@ struct HierarchyPass : public Pass { } } + if (!nokeep_prints) { + std::map cache; + for (auto mod : design->modules()) + if (set_keep_print(cache, mod)) { + log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod)); + mod->set_bool_attribute(ID::keep); + } + } + if (!nokeep_asserts) { std::map cache; for (auto mod : design->modules()) diff --git a/yosys/passes/memory/memlib.md b/yosys/passes/memory/memlib.md index fdc2d4bed27..855aa1345fb 100644 --- a/yosys/passes/memory/memlib.md +++ b/yosys/passes/memory/memlib.md @@ -267,7 +267,7 @@ The address is always `abits` wide. If a non-narrowest width is used, the appro bits will be tied to 0. -### Port `width` prooperty +### Port `width` property If the RAM has `per_port` widths, the available width selection can be further described on per-port basis, by using one of the following properties: diff --git a/yosys/passes/memory/memory_libmap.cc b/yosys/passes/memory/memory_libmap.cc index 6e5a806fd0e..2e683b8eb95 100644 --- a/yosys/passes/memory/memory_libmap.cc +++ b/yosys/passes/memory/memory_libmap.cc @@ -481,18 +481,58 @@ void MemMapping::dump_config(MemConfig &cfg) { } } +std::pair search_for_attribute(Mem mem, IdString attr) { + // priority of attributes: + // 1. attributes on memory itself + // 2. attributes on a read or write port + // 3. attributes on data signal of a read or write port + // 4. attributes on address signal of a read or write port + + if (mem.has_attribute(attr)) + return std::make_pair(true, mem.attributes.at(attr)); + + for (auto &port: mem.rd_ports) + if (port.has_attribute(attr)) + return std::make_pair(true, port.attributes.at(attr)); + for (auto &port: mem.wr_ports) + if (port.has_attribute(attr)) + return std::make_pair(true, port.attributes.at(attr)); + + for (auto &port: mem.rd_ports) + for (SigBit bit: port.data) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + for (auto &port: mem.wr_ports) + for (SigBit bit: port.data) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + + for (auto &port: mem.rd_ports) + for (SigBit bit: port.addr) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + for (auto &port: mem.wr_ports) + for (SigBit bit: port.addr) + if (bit.is_wire() && bit.wire->has_attribute(attr)) + return std::make_pair(true, bit.wire->attributes.at(attr)); + + return std::make_pair(false, Const()); +} + // Go through memory attributes to determine user-requested mapping style. void MemMapping::determine_style() { kind = RamKind::Auto; style = ""; - if (mem.get_bool_attribute(ID::lram)) { + auto find_attr = search_for_attribute(mem, ID::lram); + if (find_attr.first && find_attr.second.as_bool()) { kind = RamKind::Huge; log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid)); return; } for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) { - if (mem.has_attribute(attr)) { - Const val = mem.attributes.at(attr); + find_attr = search_for_attribute(mem, attr); + if (find_attr.first) { + Const val = find_attr.second; if (val == 1) { kind = RamKind::NotLogic; log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid)); @@ -526,8 +566,11 @@ void MemMapping::determine_style() { return; } } - if (mem.get_bool_attribute(ID::logic_block)) - kind = RamKind::Logic; + for (auto attr: {ID::logic_block, ID::no_ram}){ + find_attr = search_for_attribute(mem, attr); + if (find_attr.first && find_attr.second.as_bool()) + kind = RamKind::Logic; + } } // Determine whether the memory can be mapped entirely to soft logic. @@ -647,7 +690,7 @@ bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_po // Perform write port assignment, validating clock options as we go. void MemMapping::assign_wr_ports() { - log_reject(stringf("Assigning write ports... (candidate configs: %lu)", cfgs.size())); + log_reject(stringf("Assigning write ports... (candidate configs: %zu)", (size_t) cfgs.size())); for (auto &port: mem.wr_ports) { if (!port.clk_enable) { // Async write ports not supported. @@ -667,7 +710,7 @@ void MemMapping::assign_wr_ports() { if (used >= GetSize(pg.names)) { log_reject(*cfg.def, pg, "not enough unassigned ports remaining"); continue; - } + } for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) { auto &def = pg.variants[pvi]; // Make sure the target is a write port. @@ -696,7 +739,7 @@ void MemMapping::assign_wr_ports() { // Perform read port assignment, validating clock and rden options as we go. void MemMapping::assign_rd_ports() { - log_reject(stringf("Assigning read ports... (candidate configs: %lu)", cfgs.size())); + log_reject(stringf("Assigning read ports... (candidate configs: %zu)", (size_t) cfgs.size())); for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) { auto &port = mem.rd_ports[pidx]; MemConfigs new_cfgs; @@ -857,7 +900,7 @@ void MemMapping::assign_rd_ports() { // Validate transparency restrictions, determine where to add soft transparency logic. void MemMapping::handle_trans() { - log_reject(stringf("Handling transparency... (candidate configs: %lu)", cfgs.size())); + log_reject(stringf("Handling transparency... (candidate configs: %zu)", (size_t) cfgs.size())); if (mem.emulate_read_first_ok()) { MemConfigs new_cfgs; for (auto &cfg: cfgs) { @@ -2114,7 +2157,7 @@ struct MemoryLibMapPass : public Pass { log(" memory_libmap -lib [-D ] [selection]\n"); log("\n"); log("This pass takes a description of available RAM cell types and maps\n"); - log("all selected memories to one of them, or leaves them to be mapped to FFs.\n"); + log("all selected memories to one of them, or leaves them to be mapped to FFs.\n"); log("\n"); log(" -lib \n"); log(" Selects a library file containing RAM cell definitions. This option\n"); diff --git a/yosys/passes/opt/opt_clean.cc b/yosys/passes/opt/opt_clean.cc index cb2490dc72e..2b24944cf08 100644 --- a/yosys/passes/opt/opt_clean.cc +++ b/yosys/passes/opt/opt_clean.cc @@ -76,9 +76,15 @@ struct keep_cache_t if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) return true; + if (cell->type.in(ID($overwrite_tag))) + return true; + if (!ignore_specify && cell->type.in(ID($specify2), ID($specify3), ID($specrule))) return true; + if (cell->type == ID($print) || cell->type == ID($check)) + return true; + if (cell->has_keep_attr()) return true; @@ -234,6 +240,7 @@ int count_nontrivial_wire_attrs(RTLIL::Wire *w) return count; } +// Should we pick `s2` over `s1` to represent a signal? bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPool &conns, pool &direct_wires) { RTLIL::Wire *w1 = s1.wire; @@ -286,9 +293,10 @@ bool check_public_name(RTLIL::IdString id) bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose) { + // `register_signals` and `connected_signals` will help us decide later on + // on picking representatives out of groups of connected signals SigPool register_signals; SigPool connected_signals; - if (!purge_mode) for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; @@ -303,20 +311,27 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos } SigMap assign_map(module); - pool direct_sigs; + + // construct a pool of wires which are directly driven by a known celltype, + // this will influence our choice of representatives pool direct_wires; - for (auto &it : module->cells_) { - RTLIL::Cell *cell = it.second; - if (ct_all.cell_known(cell->type)) - for (auto &it2 : cell->connections()) - if (ct_all.cell_output(cell->type, it2.first)) - direct_sigs.insert(assign_map(it2.second)); - } - for (auto &it : module->wires_) { - if (direct_sigs.count(assign_map(it.second)) || it.second->port_input) - direct_wires.insert(it.second); + { + pool direct_sigs; + for (auto &it : module->cells_) { + RTLIL::Cell *cell = it.second; + if (ct_all.cell_known(cell->type)) + for (auto &it2 : cell->connections()) + if (ct_all.cell_output(cell->type, it2.first)) + direct_sigs.insert(assign_map(it2.second)); + } + for (auto &it : module->wires_) { + if (direct_sigs.count(assign_map(it.second)) || it.second->port_input) + direct_wires.insert(it.second); + } } + // weight all options for representatives with `compare_signals`, + // the one that wins will be what `assign_map` maps to for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { @@ -326,21 +341,30 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos } } + // we are removing all connections module->connections_.clear(); + // used signals sigmapped SigPool used_signals; + // used signals pre-sigmapped SigPool raw_used_signals; + // used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`) SigPool used_signals_nodrivers; + + // gather the usage information for cells for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; for (auto &it2 : cell->connections_) { - assign_map.apply(it2.second); + assign_map.apply(it2.second); // modify the cell connection in place raw_used_signals.add(it2.second); used_signals.add(it2.second); if (!ct_all.cell_output(cell->type, it2.first)) used_signals_nodrivers.add(it2.second); } } + + // gather the usage information for ports, wires with `keep`, + // also gather init bits dict init_bits; for (auto &it : module->wires_) { RTLIL::Wire *wire = it.second; @@ -368,6 +392,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos } } + // set init attributes on all wires of a connected group for (auto wire : module->wires()) { bool found = false; Const val(State::Sx, wire->width); @@ -382,6 +407,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes[ID::init] = val; } + // now decide for each wire if we should be deleting it pool del_wires_queue; for (auto wire : module->wires()) { @@ -412,6 +438,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos goto delete_this_wire; } else if (!used_signals.check_any(s2)) { + // this path shouldn't be possible: this wire is used directly (otherwise it would get cleaned up above), and indirectly + // used wires are a superset of those used directly + log_assert(false); // delete wires that aren't used by anything indirectly, even though other wires may alias it goto delete_this_wire; } diff --git a/yosys/passes/opt/opt_dff.cc b/yosys/passes/opt/opt_dff.cc index f090d20b2e8..b77be45151b 100644 --- a/yosys/passes/opt/opt_dff.cc +++ b/yosys/passes/opt/opt_dff.cc @@ -353,7 +353,7 @@ struct OptDffWorker // Try a more complex conversion to plain async reset. State val_neutral = ff.pol_set ? State::S0 : State::S1; Const val_arst; - SigSpec sig_arst; + SigBit sig_arst; if (ff.sig_clr[0] == val_neutral) sig_arst = ff.sig_set[0]; else diff --git a/yosys/passes/opt/opt_expr.cc b/yosys/passes/opt/opt_expr.cc index 46773a344b1..3eadd35c6af 100644 --- a/yosys/passes/opt/opt_expr.cc +++ b/yosys/passes/opt/opt_expr.cc @@ -424,13 +424,19 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons for (auto &bit : sig) outbit_to_cell[bit].insert(cell); } - cells.node(cell); + cells.node(cell); } - for (auto &it_right : cell_to_inbit) - for (auto &it_sigbit : it_right.second) - for (auto &it_left : outbit_to_cell[it_sigbit]) - cells.edge(it_left, it_right.first); + // Build the graph for the topological sort. + for (auto &it_right : cell_to_inbit) { + const int r_index = cells.node(it_right.first); + for (auto &it_sigbit : it_right.second) { + for (auto &it_left : outbit_to_cell[it_sigbit]) { + const int l_index = cells.node(it_left); + cells.edge(l_index, r_index); + } + } + } cells.sort(); diff --git a/yosys/passes/opt/opt_ffinv.cc b/yosys/passes/opt/opt_ffinv.cc index 3f7b4bc4a71..d982ef2d239 100644 --- a/yosys/passes/opt/opt_ffinv.cc +++ b/yosys/passes/opt/opt_ffinv.cc @@ -38,6 +38,7 @@ struct OptFfInvWorker // - ... which has no other users // - all users of FF are LUTs bool push_d_inv(FfData &ff) { + log_assert(ff.width == 1); if (index.query_is_input(ff.sig_d)) return false; if (index.query_is_output(ff.sig_d)) @@ -90,7 +91,7 @@ struct OptFfInvWorker int flip_mask = 0; SigSpec sig_a = lut->getPort(ID::A); for (int i = 0; i < GetSize(sig_a); i++) { - if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q)) { + if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) { flip_mask |= 1 << i; } } diff --git a/yosys/passes/opt/opt_lut.cc b/yosys/passes/opt/opt_lut.cc index 3b079d964f4..d0fc6078120 100644 --- a/yosys/passes/opt/opt_lut.cc +++ b/yosys/passes/opt/opt_lut.cc @@ -24,6 +24,10 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +// Type represents the following constraint: Preserve connections to dedicated +// logic cell that has ports connected to LUT inputs. This includes +// the case where both LUT and dedicated logic input are connected to the same +// constant. struct dlogic_t { IdString cell_type; // LUT input idx -> hard cell's port name @@ -163,7 +167,11 @@ struct OptLutWorker legal = false; break; } - if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second))) + + if (lut_dlogic.second->getPort(dlogic_conn.second).size() != 1) + continue; + + if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic.second->getPort(dlogic_conn.second)[0])) { log_debug(" LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic.second->type.c_str(), log_id(module), log_id(lut_dlogic.second)); log_debug(" LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic.second->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic.second->getPort(dlogic_conn.second))); @@ -310,7 +318,7 @@ struct OptLutWorker auto lutA = worklist.pop(); SigSpec lutA_input = sigmap(lutA->getPort(ID::A)); - SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]); + SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]); int lutA_width = lutA->getParam(ID::WIDTH).as_int(); int lutA_arity = luts_arity[lutA]; pool &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; @@ -515,16 +523,6 @@ struct OptLutWorker } }; -static void split(std::vector &tokens, const std::string &text, char sep) -{ - size_t start = 0, end = 0; - while ((end = text.find(sep, start)) != std::string::npos) { - tokens.push_back(text.substr(start, end - start)); - start = end + 1; - } - tokens.push_back(text.substr(start)); -} - struct OptLutPass : public Pass { OptLutPass() : Pass("opt_lut", "optimize LUT cells") { } void help() override @@ -535,11 +533,9 @@ struct OptLutPass : public Pass { log("\n"); log("This pass combines cascaded $lut cells with unused inputs.\n"); log("\n"); - log(" -dlogic :=[:=...]\n"); - log(" preserve connections to dedicated logic cell that has ports\n"); - log(" connected to LUT inputs . this includes\n"); - log(" the case where both LUT and dedicated logic input are connected to\n"); - log(" the same constant.\n"); + log(" -tech ice40\n"); + log(" treat the design as a LUT-mapped circuit for the iCE40 architecture\n"); + log(" and preserve connections to SB_CARRY as appropriate\n"); log("\n"); log(" -limit N\n"); log(" only perform the first N combines, then stop. useful for debugging.\n"); @@ -555,28 +551,28 @@ struct OptLutPass : public Pass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-dlogic" && argidx+1 < args.size()) + if (args[argidx] == "-tech" && argidx+1 < args.size()) { - std::vector tokens; - split(tokens, args[++argidx], ':'); - if (tokens.size() < 2) - log_cmd_error("The -dlogic option requires at least one connection.\n"); - dlogic_t entry; - entry.cell_type = "\\" + tokens[0]; - for (auto it = tokens.begin() + 1; it != tokens.end(); ++it) { - std::vector conn_tokens; - split(conn_tokens, *it, '='); - if (conn_tokens.size() != 2) - log_cmd_error("Invalid format of -dlogic signal mapping.\n"); - IdString logic_port = "\\" + conn_tokens[0]; - int lut_input = atoi(conn_tokens[1].c_str()); - entry.lut_input_port[lut_input] = logic_port; - } - dlogic.push_back(entry); + std::string tech = args[++argidx]; + if (tech != "ice40") + log_cmd_error("Unsupported -tech argument: %s\n", tech.c_str()); + + dlogic = {{ + ID(SB_CARRY), + dict{ + std::make_pair(1, ID(I0)), + std::make_pair(2, ID(I1)), + std::make_pair(3, ID(CI)) + } + }, { + ID(SB_CARRY), + dict{ + std::make_pair(3, ID(CO)) + } + }}; continue; } - if (args[argidx] == "-limit" && argidx + 1 < args.size()) - { + if (args[argidx] == "-limit" && argidx + 1 < args.size()) { limit = atoi(args[++argidx].c_str()); continue; } diff --git a/yosys/passes/opt/opt_lut_ins.cc b/yosys/passes/opt/opt_lut_ins.cc index 2f7c392b29a..652fce1e2d5 100644 --- a/yosys/passes/opt/opt_lut_ins.cc +++ b/yosys/passes/opt/opt_lut_ins.cc @@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass { log("\n"); log(" -tech \n"); log(" Instead of generic $lut cells, operate on LUT cells specific\n"); - log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n"); + log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass { } extra_args(args, argidx, design); - if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin") + if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); for (auto module : design->selected_modules()) @@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass { output = cell->getPort(ID::O); else output = cell->getPort(ID::F); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { if (cell->type == ID(LUT4)) { inputs = { cell->getPort(ID::A), @@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass { if (!doit) continue; log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs)); - if (techname == "ecp5") { + if (techname == "lattice" || techname == "ecp5") { // Pad the LUT to 4 inputs, adding consts from the front. int extra = 4 - GetSize(new_inputs); log_assert(extra >= 0); @@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass { } new_lut[i] = lut[lidx]; } - // For ecp5, and gowin do not replace with a const driver — the nextpnr + // For lattice, and gowin do not replace with a const driver — the nextpnr // packer requires a complete set of LUTs for wide LUT muxes. - if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") { + if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") { // const driver. remove_cells.push_back(cell); module->connect(output, new_lut[0]); @@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass { cell->setParam(ID::LUT, new_lut); cell->setParam(ID::WIDTH, GetSize(new_inputs)); cell->setPort(ID::A, new_inputs); - } else if (techname == "ecp5") { + } else if (techname == "lattice" || techname == "ecp5") { log_assert(GetSize(new_inputs) == 4); cell->setParam(ID::INIT, new_lut); cell->setPort(ID::A, new_inputs[0]); diff --git a/yosys/passes/opt/opt_merge.cc b/yosys/passes/opt/opt_merge.cc index e9d98cd4304..248ba80913b 100644 --- a/yosys/passes/opt/opt_merge.cc +++ b/yosys/passes/opt/opt_merge.cc @@ -41,7 +41,6 @@ struct OptMergeWorker CellTypes ct; int total_count; - SHA1 checksum; static void sort_pmux_conn(dict &conn) { @@ -78,7 +77,7 @@ struct OptMergeWorker return str; } - std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell) + uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell) { vector hash_conn_strings; std::string hash_string = cell->type.str() + "\n"; @@ -149,8 +148,7 @@ struct OptMergeWorker for (auto it : hash_conn_strings) hash_string += it; - checksum.update(hash_string); - return checksum.final(); + return std::hash{}(hash_string); } bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) @@ -268,13 +266,13 @@ struct OptMergeWorker } did_something = false; - dict sharemap; + dict sharemap; for (auto cell : cells) { if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known()) continue; - auto hash = hash_cell_parameters_and_connections(cell); + uint64_t hash = hash_cell_parameters_and_connections(cell); auto r = sharemap.insert(std::make_pair(hash, cell)); if (!r.second) { if (compare_cell_parameters_and_connections(cell, r.first->second)) { diff --git a/yosys/passes/opt/share.cc b/yosys/passes/opt/share.cc index abef719370b..586bd9dfe9d 100644 --- a/yosys/passes/opt/share.cc +++ b/yosys/passes/opt/share.cc @@ -1032,7 +1032,7 @@ struct ShareWorker } bool found_scc = !toposort.sort(); - topo_cell_drivers = std::move(toposort.database); + topo_cell_drivers = toposort.get_database(); if (found_scc && toposort.analyze_loops) for (auto &loop : toposort.loops) { diff --git a/yosys/passes/pmgen/Makefile.inc b/yosys/passes/pmgen/Makefile.inc index a7ef642825c..ed872b7212d 100644 --- a/yosys/passes/pmgen/Makefile.inc +++ b/yosys/passes/pmgen/Makefile.inc @@ -1,5 +1,5 @@ %_pm.h: passes/pmgen/pmgen.py %.pmg - $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) # -------------------------------------- @@ -42,7 +42,9 @@ GENFILES += passes/pmgen/peepopt_pm.h passes/pmgen/peepopt.o: passes/pmgen/peepopt_pm.h $(eval $(call add_extra_objs,passes/pmgen/peepopt_pm.h)) -PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul.pmg +PEEPOPT_PATTERN = passes/pmgen/peepopt_shiftmul_right.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftmul_left.pmg +PEEPOPT_PATTERN += passes/pmgen/peepopt_shiftadd.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) diff --git a/yosys/passes/pmgen/README.md b/yosys/passes/pmgen/README.md index 39560839f0f..3205be1b55e 100644 --- a/yosys/passes/pmgen/README.md +++ b/yosys/passes/pmgen/README.md @@ -212,7 +212,7 @@ second argument, and the matcher will iterate over those options: index port(eq, BA) === bar set eq_ab AB set eq_ba BA - generate + endmatch Notice how `define` can be used to define additional local variables similar to the loop variables defined by `slice` and `choice`. diff --git a/yosys/passes/pmgen/ice40_dsp.pmg b/yosys/passes/pmgen/ice40_dsp.pmg index 4de4791228e..9099dd3c470 100644 --- a/yosys/passes/pmgen/ice40_dsp.pmg +++ b/yosys/passes/pmgen/ice40_dsp.pmg @@ -346,7 +346,7 @@ endmatch code argQ argD { if (clock != SigBit()) { - if (port(ff, \CLK) != clock) + if (port(ff, \CLK)[0] != clock) reject; if (param(ff, \CLK_POLARITY).as_bool() != clock_pol) reject; @@ -393,7 +393,7 @@ endmatch code argQ if (ff) { if (clock != SigBit()) { - if (port(ff, \CLK) != clock) + if (port(ff, \CLK)[0] != clock) reject; if (param(ff, \CLK_POLARITY).as_bool() != clock_pol) reject; diff --git a/yosys/passes/pmgen/peepopt.cc b/yosys/passes/pmgen/peepopt.cc index 9a497c91441..edd3b18a815 100644 --- a/yosys/passes/pmgen/peepopt.cc +++ b/yosys/passes/pmgen/peepopt.cc @@ -24,11 +24,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something; -dict initbits; -pool rminitbits; #include "passes/pmgen/peepopt_pm.h" -#include "generate.h" struct PeepoptPass : public Pass { PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { } @@ -40,38 +37,32 @@ struct PeepoptPass : public Pass { log("\n"); log("This pass applies a collection of peephole optimizers to the current design.\n"); log("\n"); + log("This pass employs the following rules:\n"); + log("\n"); + log(" * muldiv - Replace (A*B)/B with A\n"); + log("\n"); + log(" * shiftmul - Replace A>>(B*C) with A'>>(B<>(B+D) with (A'>>D)>>(B) where D is constant and\n"); + log(" A' is derived from A by padding or cutting inaccessible bits.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { - std::string genmode; - log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-generate" && argidx+1 < args.size()) { - genmode = args[++argidx]; - continue; - } break; } extra_args(args, argidx, design); - if (!genmode.empty()) - { - initbits.clear(); - rminitbits.clear(); - - if (genmode == "shiftmul") - GENERATE_PATTERN(peepopt_pm, shiftmul); - else if (genmode == "muldiv") - GENERATE_PATTERN(peepopt_pm, muldiv); - else - log_abort(); - return; - } - for (auto module : design->selected_modules()) { did_something = true; @@ -79,47 +70,15 @@ struct PeepoptPass : public Pass { while (did_something) { did_something = false; - initbits.clear(); - rminitbits.clear(); peepopt_pm pm(module); - for (auto w : module->wires()) { - auto it = w->attributes.find(ID::init); - if (it != w->attributes.end()) { - SigSpec sig = pm.sigmap(w); - Const val = it->second; - int len = std::min(GetSize(sig), GetSize(val)); - for (int i = 0; i < len; i++) { - if (sig[i].wire == nullptr) - continue; - if (val[i] != State::S0 && val[i] != State::S1) - continue; - initbits[sig[i]] = val[i]; - } - } - } - pm.setup(module->selected_cells()); - pm.run_shiftmul(); + pm.run_shiftadd(); + pm.run_shiftmul_right(); + pm.run_shiftmul_left(); pm.run_muldiv(); - - for (auto w : module->wires()) { - auto it = w->attributes.find(ID::init); - if (it != w->attributes.end()) { - SigSpec sig = pm.sigmap(w); - Const &val = it->second; - int len = std::min(GetSize(sig), GetSize(val)); - for (int i = 0; i < len; i++) { - if (rminitbits.count(sig[i])) - val[i] = State::Sx; - } - } - } - - initbits.clear(); - rminitbits.clear(); } } } diff --git a/yosys/passes/pmgen/peepopt_shiftadd.pmg b/yosys/passes/pmgen/peepopt_shiftadd.pmg new file mode 100644 index 00000000000..e690ff65113 --- /dev/null +++ b/yosys/passes/pmgen/peepopt_shiftadd.pmg @@ -0,0 +1,133 @@ +pattern shiftadd +// +// Transforms add/sub+shift pairs that result from expressions such as data[s*W +C +:W2] +// specifically something like: out[W2-1:0] = data >> (s*W +C) +// will be transformed into: out[W2-1:0] = (data >> C) >> (s*W) +// this can then be optimized using peepopt_shiftmul_right.pmg +// + +match shift + select shift->type.in($shift, $shiftx, $shr) + filter !port(shift, \B).empty() +endmatch + +// the right shift amount +state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale +// zeros at the MSB position make it unsigned +state msb_zeros + +code shift_amount log2scale msb_zeros + shift_amount = port(shift, \B); + + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + + msb_zeros = 0; + while (shift_amount.bits().back() == State::S0) { + msb_zeros = true; + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; + } +endcode + +state var_signed +state var_signal +// offset: signed constant value c in data[var+c +:W1] (constant shift-right amount) +state offset + +match add + // either data[var+c +:W1] or data[var-c +:W1] + select add->type.in($add, $sub) + index port(add, \Y) === shift_amount + + // one must be constant, the other is variable + choice constport {\A, \B} + select !port(add, constport).empty() + select port(add, constport).is_fully_const() + define varport (constport == \A ? \B : \A) + + // if a value of var is able to wrap the output, the transformation might give wrong results + // an addition/substraction can at most flip one more bit than the largest operand (the carry bit) + // as long as the output can show this bit, no wrap should occur (assuming all signed-ness make sense) + select ( GetSize(port(add, \Y)) > max(GetSize(port(add, \A)), GetSize(port(add, \B))) ) + + define varport_A (varport == \A) + define is_sub add->type.in($sub) + + define constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool() + define varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool(); + define offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A)) + + // checking some value boundaries as well: + // data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible) + // data[...+c +:W1] is only fine for +var(add) and var unsigned + // (+c cuts lower C bits, making them inaccessible, a signed var could try to access them) + // either its an add or the variable port is A (it must be positive) + select (add->type.in($add) || varport == \A) + + // -> data[var+c +:W1] (with var signed) is illegal + filter !(!offset_negative && varport_signed) + + // state-variables are assigned at the end only: + // shift the log2scale offset in-front of add to get true value: (var+c)< (var<getPort(varport) +endmatch + +code +{ + // positive constant offset with a signed variable (index) cannot be handled + // the above filter should get rid of this case but 'offset' is calculated differently + // due to limitations of state-variables in pmgen + // it should only differ if previous passes create invalid data + log_assert(!(offset>0 && var_signed)); + + did_something = true; + log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ + log_id(module), log_id(shift), log_id(add), offset); + + SigSpec old_a = port(shift, \A), new_a; + if(offset<0) { + // data >> (...-c) transformed to {data, c'X} >> (...) + SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset ); + new_a.append(padding); + new_a.append(old_a); + } else { + // data >> (...+c) transformed to data[MAX:c] >> (...) + if(offset < GetSize(old_a)) { // some signal bits left? + new_a.append(old_a.extract_end(offset)); + } else { + // warn user in case data is empty (no bits left) + std::string location = shift->get_src_attribute(); + if (location.empty()) + location = shift->name.str(); + if(shift->type.in($shiftx)) + log_warning("at %s: result of indexed part-selection is always constant (selecting from '%s' with index '%s + %d')\n", \ + location.c_str(), log_signal(old_a), log_signal(var_signal), offset); + else + log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d'-bits)\n", \ + location.c_str(), log_signal(old_a), log_signal(var_signal), offset); + } + } + + SigSpec new_b = {var_signal, SigSpec(State::S0, log2scale)}; + if (msb_zeros || !var_signed) + new_b.append(State::S0); + + shift->setPort(\A, new_a); + shift->setParam(\A_WIDTH, GetSize(new_a)); + shift->setPort(\B, new_b); + shift->setParam(\B_WIDTH, GetSize(new_b)); + blacklist(add); + accept; +} +endcode diff --git a/yosys/passes/pmgen/peepopt_shiftmul.pmg b/yosys/passes/pmgen/peepopt_shiftmul.pmg deleted file mode 100644 index d71fbf74449..00000000000 --- a/yosys/passes/pmgen/peepopt_shiftmul.pmg +++ /dev/null @@ -1,92 +0,0 @@ -pattern shiftmul -// -// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] -// - -state shamt - -match shift - select shift->type.in($shift, $shiftx, $shr) -endmatch - -code shamt - shamt = port(shift, \B); - if (shamt.empty()) - reject; - if (shamt[GetSize(shamt)-1] == State::S0) { - do { - shamt.remove(GetSize(shamt)-1); - if (shamt.empty()) - reject; - } while (shamt[GetSize(shamt)-1] == State::S0); - } else - if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) { - reject; - } - if (GetSize(shamt) > 20) - reject; -endcode - -match mul - select mul->type.in($mul) - select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const() - index port(mul, \Y) === shamt - filter !param(mul, \A_SIGNED).as_bool() -endmatch - -code -{ - IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B; - Const const_factor_cnst = port(mul, const_factor_port).as_const(); - int const_factor = const_factor_cnst.as_int(); - - if (GetSize(const_factor_cnst) == 0) - reject; - - if (GetSize(const_factor_cnst) > 20) - reject; - - if (GetSize(port(shift, \Y)) > const_factor) - reject; - - int factor_bits = ceil_log2(const_factor); - SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A); - - if (GetSize(shamt) < factor_bits+GetSize(mul_din)) - reject; - - did_something = true; - log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); - - int new_const_factor = 1 << factor_bits; - SigSpec padding(State::Sx, new_const_factor-const_factor); - SigSpec old_a = port(shift, \A), new_a; - int trunc = 0; - - if (GetSize(old_a) % const_factor != 0) { - trunc = const_factor - GetSize(old_a) % const_factor; - old_a.append(SigSpec(State::Sx, trunc)); - } - - for (int i = 0; i*const_factor < GetSize(old_a); i++) { - SigSpec slice = old_a.extract(i*const_factor, const_factor); - new_a.append(slice); - new_a.append(padding); - } - - if (trunc > 0) - new_a.remove(GetSize(new_a)-trunc, trunc); - - SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; - if (param(shift, \B_SIGNED).as_bool()) - new_b.append(State::S0); - - shift->setPort(\A, new_a); - shift->setParam(\A_WIDTH, GetSize(new_a)); - shift->setPort(\B, new_b); - shift->setParam(\B_WIDTH, GetSize(new_b)); - - blacklist(shift); - accept; -} -endcode diff --git a/yosys/passes/pmgen/peepopt_shiftmul_left.pmg b/yosys/passes/pmgen/peepopt_shiftmul_left.pmg new file mode 100644 index 00000000000..607f8368c53 --- /dev/null +++ b/yosys/passes/pmgen/peepopt_shiftmul_left.pmg @@ -0,0 +1,160 @@ +pattern shiftmul_left +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// + +match shift + select shift->type.in($shift, $shiftx, $shl) + select shift->type.in($shl) || param(shift, \B_SIGNED).as_bool() + filter !port(shift, \B).empty() +endmatch + +match neg + if shift->type.in($shift, $shiftx) + select neg->type == $neg + index port(neg, \Y) === port(shift, \B) + filter !port(shift, \A).empty() +endmatch + +// the left shift amount +state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale + +code shift_amount log2scale + if (neg) { + // case of `$shift`, `$shiftx` + shift_amount = port(neg, \A); + if (!param(neg, \A_SIGNED).as_bool()) + shift_amount.append(State::S0); + } else { + // case of `$shl` + shift_amount = port(shift, \B); + if (!param(shift, \B_SIGNED).as_bool()) + shift_amount.append(State::S0); + } + + // at this point shift_amount is signed, make + // sure we can never go negative + if (shift_amount.bits().back() != State::S0) + reject; + + while (shift_amount.bits().back() == State::S0) { + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; + } + + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + + if (GetSize(shift_amount) > 20) + reject; +endcode + +state mul_din +state mul_const + +match mul + select mul->type.in($mul) + index port(mul, \Y) === shift_amount + filter !param(mul, \A_SIGNED).as_bool() + + choice constport {\A, \B} + filter port(mul, constport).is_fully_const() + + define varport (constport == \A ? \B : \A) + set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const() + // get mul_din unmapped (so no `port()` shorthand) + // because we will be using it to set the \A port + // on the shift cell, and we want to stay close + // to the original design + set mul_din mul->getPort(varport) +endmatch + +code +{ + if (mul_const.empty() || GetSize(mul_const) > 20) + reject; + + // make sure there's no overlap in the signal + // selections by the shiftmul pattern + if (GetSize(port(shift, \A)) > mul_const.as_int()) + reject; + + int factor_bits = ceil_log2(mul_const.as_int()); + // make sure the multiplication never wraps around + if (GetSize(shift_amount) < factor_bits + GetSize(mul_din)) + reject; + + if (neg) { + // make sure the negation never wraps around + if (GetSize(port(shift, \B)) < factor_bits + GetSize(mul_din) + + log2scale + 1) + reject; + } + + did_something = true; + log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + + int const_factor = mul_const.as_int(); + int new_const_factor = 1 << factor_bits; + SigSpec padding(State::Sm, new_const_factor-const_factor); + SigSpec old_y = port(shift, \Y), new_y; + int trunc = 0; + + if (GetSize(old_y) % const_factor != 0) { + trunc = const_factor - GetSize(old_y) % const_factor; + old_y.append(SigSpec(State::Sm, trunc)); + } + + for (int i = 0; i*const_factor < GetSize(old_y); i++) { + SigSpec slice = old_y.extract(i*const_factor, const_factor); + new_y.append(slice); + new_y.append(padding); + } + + if (trunc > 0) + new_y.remove(GetSize(new_y)-trunc, trunc); + + { + // Now replace occurences of Sm in new_y with bits + // of a dummy wire + int padbits = 0; + for (auto bit : new_y) + if (bit == SigBit(State::Sm)) + padbits++; + + SigSpec padwire = module->addWire(NEW_ID, padbits); + + for (int i = new_y.size() - 1; i >= 0; i--) + if (new_y[i] == SigBit(State::Sm)) { + new_y[i] = padwire.bits().back(); + padwire.remove(padwire.size() - 1); + } + } + + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; + + shift->setPort(\Y, new_y); + shift->setParam(\Y_WIDTH, GetSize(new_y)); + if (shift->type == $shl) { + if (param(shift, \B_SIGNED).as_bool()) + new_b.append(State::S0); + shift->setPort(\B, new_b); + shift->setParam(\B_WIDTH, GetSize(new_b)); + } else { + SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1); + module->addNeg(NEW_ID, new_b, b_neg); + shift->setPort(\B, b_neg); + shift->setParam(\B_WIDTH, GetSize(b_neg)); + } + + blacklist(shift); + accept; +} +endcode diff --git a/yosys/passes/pmgen/peepopt_shiftmul_right.pmg b/yosys/passes/pmgen/peepopt_shiftmul_right.pmg new file mode 100644 index 00000000000..108829d4f9d --- /dev/null +++ b/yosys/passes/pmgen/peepopt_shiftmul_right.pmg @@ -0,0 +1,108 @@ +pattern shiftmul_right +// +// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W] +// + +match shift + select shift->type.in($shift, $shiftx, $shr) + filter !port(shift, \B).empty() +endmatch + +// the right shift amount +state shift_amount +// log2 scale factor in interpreting of shift_amount +// due to zero padding on the shift cell's B port +state log2scale + +code shift_amount log2scale + shift_amount = port(shift, \B); + if (shift->type.in($shr) || !param(shift, \B_SIGNED).as_bool()) + shift_amount.append(State::S0); + + // at this point shift_amount is signed, make + // sure we can never go negative + if (shift_amount.bits().back() != State::S0) + reject; + + while (shift_amount.bits().back() == State::S0) { + shift_amount.remove(GetSize(shift_amount) - 1); + if (shift_amount.empty()) reject; + } + + log2scale = 0; + while (shift_amount[0] == State::S0) { + shift_amount.remove(0); + if (shift_amount.empty()) reject; + log2scale++; + } + + if (GetSize(shift_amount) > 20) + reject; +endcode + +state mul_din +state mul_const + +match mul + select mul->type.in($mul) + index port(mul, \Y) === shift_amount + filter !param(mul, \A_SIGNED).as_bool() + + choice constport {\A, \B} + filter port(mul, constport).is_fully_const() + + define varport (constport == \A ? \B : \A) + set mul_const SigSpec({port(mul, constport), SigSpec(State::S0, log2scale)}).as_const() + // get mul_din unmapped (so no `port()` shorthand) + // because we will be using it to set the \A port + // on the shift cell, and we want to stay close + // to the original design + set mul_din mul->getPort(varport) +endmatch + +code +{ + if (mul_const.empty() || GetSize(mul_const) > 20) + reject; + + // make sure there's no overlap in the signal + // selections by the shiftmul pattern + if (GetSize(port(shift, \Y)) > mul_const.as_int()) + reject; + + int factor_bits = ceil_log2(mul_const.as_int()); + // make sure the multiplication never wraps around + if (GetSize(shift_amount) + log2scale < factor_bits + GetSize(mul_din)) + reject; + + did_something = true; + log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul)); + + int const_factor = mul_const.as_int(); + int new_const_factor = 1 << factor_bits; + SigSpec padding(State::Sx, new_const_factor-const_factor); + SigSpec old_a = port(shift, \A), new_a; + + for (int i = 0; i*const_factor < GetSize(old_a); i++) { + if ((i+1)*const_factor < GetSize(old_a)) { + SigSpec slice = old_a.extract(i*const_factor, const_factor); + new_a.append(slice); + new_a.append(padding); + } else { + new_a.append(old_a.extract_end(i*const_factor)); + } + } + + SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; + if (param(shift, \B_SIGNED).as_bool()) + new_b.append(State::S0); + + shift->setPort(\A, new_a); + shift->setParam(\A_WIDTH, GetSize(new_a)); + shift->setPort(\B, new_b); + shift->setParam(\B_WIDTH, GetSize(new_b)); + + blacklist(shift); + accept; +} +endcode diff --git a/yosys/passes/pmgen/xilinx_dsp.pmg b/yosys/passes/pmgen/xilinx_dsp.pmg index 0cd23c09da0..817a15a1e8f 100644 --- a/yosys/passes/pmgen/xilinx_dsp.pmg +++ b/yosys/passes/pmgen/xilinx_dsp.pmg @@ -415,7 +415,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -465,7 +465,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/yosys/passes/pmgen/xilinx_dsp48a.pmg b/yosys/passes/pmgen/xilinx_dsp48a.pmg index dce1b61b005..f3bd9bc9567 100644 --- a/yosys/passes/pmgen/xilinx_dsp48a.pmg +++ b/yosys/passes/pmgen/xilinx_dsp48a.pmg @@ -354,7 +354,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -404,7 +404,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/yosys/passes/pmgen/xilinx_dsp_CREG.pmg b/yosys/passes/pmgen/xilinx_dsp_CREG.pmg index 95379771a2d..49e79dd8723 100644 --- a/yosys/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/yosys/passes/pmgen/xilinx_dsp_CREG.pmg @@ -135,7 +135,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/yosys/passes/pmgen/xilinx_dsp_cascade.pmg b/yosys/passes/pmgen/xilinx_dsp_cascade.pmg index 06601554c6b..29fc27dfed6 100644 --- a/yosys/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/yosys/passes/pmgen/xilinx_dsp_cascade.pmg @@ -46,7 +46,7 @@ pattern xilinx_dsp_cascade udata > unextend udata >> chain longest_chain state next -state clock +state clock state AREG BREG // Variables used for subpatterns @@ -395,7 +395,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ diff --git a/yosys/passes/proc/proc_clean.cc b/yosys/passes/proc/proc_clean.cc index 45872907bd8..95cb0e88ca9 100644 --- a/yosys/passes/proc/proc_clean.cc +++ b/yosys/passes/proc/proc_clean.cc @@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth) { - if (sw->signal.size() > 0 && sw->signal.is_fully_const()) + if (sw->signal.size() > 0 && sw->signal.is_fully_def()) { int found_matching_case_idx = -1; for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++) @@ -41,7 +41,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did break; for (int j = 0; j < int(cs->compare.size()); j++) { RTLIL::SigSpec &val = cs->compare[j]; - if (!val.is_fully_const()) + if (!val.is_fully_def()) continue; if (val == sw->signal) { cs->compare.clear(); diff --git a/yosys/passes/sat/async2sync.cc b/yosys/passes/sat/async2sync.cc index 6fdf470b12b..93c7e96c809 100644 --- a/yosys/passes/sat/async2sync.cc +++ b/yosys/passes/sat/async2sync.cc @@ -41,31 +41,88 @@ struct Async2syncPass : public Pass { log("reset value in the next cycle regardless of the data-in value at the time of\n"); log("the clock edge.\n"); log("\n"); + log(" -nolower\n"); + log(" Do not automatically run 'chformal -lower' to lower $check cells.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override { - // bool flag_noinit = false; + bool flag_nolower = false; log_header(design, "Executing ASYNC2SYNC pass.\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-noinit") { - // flag_noinit = true; - // continue; - // } + if (args[argidx] == "-nolower") { + flag_nolower = true; + continue; + } break; } extra_args(args, argidx, design); + bool have_check_cells = false; + for (auto module : design->selected_modules()) { SigMap sigmap(module); FfInitVals initvals(&sigmap, module); + SigBit initstate; + for (auto cell : vector(module->selected_cells())) { + if (cell->type.in(ID($print), ID($check))) + { + if (cell->type == ID($check)) + have_check_cells = true; + + bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool(); + if (!trg_enable) + continue; + + int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int(); + + if (trg_width > 1) + log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", log_id(cell)); + + if (trg_width == 0) { + if (initstate == State::S0) + initstate = module->Initstate(NEW_ID); + + SigBit sig_en = cell->getPort(ID::EN); + cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); + } else { + SigBit sig_en = cell->getPort(ID::EN); + SigSpec sig_args = cell->getPort(ID::ARGS); + bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool(); + SigBit sig_trg = cell->getPort(ID::TRG); + Wire *sig_en_q = module->addWire(NEW_ID); + Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args)); + sig_en_q->attributes.emplace(ID::init, State::S0); + module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute()); + module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute()); + cell->setPort(ID::EN, sig_en_q); + cell->setPort(ID::ARGS, sig_args_q); + if (cell->type == ID($check)) { + SigBit sig_a = cell->getPort(ID::A); + Wire *sig_a_q = module->addWire(NEW_ID); + sig_a_q->attributes.emplace(ID::init, State::S1); + module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute()); + cell->setPort(ID::A, sig_a_q); + } + } + + cell->setPort(ID::TRG, SigSpec()); + + cell->setParam(ID::TRG_ENABLE, false); + cell->setParam(ID::TRG_WIDTH, 0); + cell->setParam(ID::TRG_POLARITY, false); + cell->set_bool_attribute(ID(trg_on_gclk)); + continue; + } + if (!RTLIL::builtin_ff_cell_types().count(cell->type)) continue; @@ -273,6 +330,12 @@ struct Async2syncPass : public Pass { ff.emit(); } } + + if (have_check_cells && !flag_nolower) { + log_push(); + Pass::call(design, "chformal -lower"); + log_pop(); + } } } Async2syncPass; diff --git a/yosys/passes/sat/clk2fflogic.cc b/yosys/passes/sat/clk2fflogic.cc index 3dc96ecce2a..2c0e13f852e 100644 --- a/yosys/passes/sat/clk2fflogic.cc +++ b/yosys/passes/sat/clk2fflogic.cc @@ -48,6 +48,9 @@ struct Clk2fflogicPass : public Pass { log("reset value in the next cycle regardless of the data-in value at the time of\n"); log("the clock edge.\n"); log("\n"); + log(" -nolower\n"); + log(" Do not automatically run 'chformal -lower' to lower $check cells.\n"); + log("\n"); } // Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted. SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) { @@ -117,21 +120,23 @@ struct Clk2fflogicPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - // bool flag_noinit = false; + bool flag_nolower = false; log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-noinit") { - // flag_noinit = true; - // continue; - // } + if (args[argidx] == "-nolower") { + flag_nolower = true; + continue; + } break; } extra_args(args, argidx, design); + bool have_check_cells = false; + for (auto module : design->selected_modules()) { SigMap sigmap(module); @@ -194,79 +199,137 @@ struct Clk2fflogicPass : public Pass { mem.emit(); } + SigBit initstate; + for (auto cell : vector(module->selected_cells())) { - SigSpec qval; - if (RTLIL::builtin_ff_cell_types().count(cell->type)) { - FfData ff(&initvals, cell); + if (cell->type.in(ID($print), ID($check))) + { + if (cell->type == ID($check)) + have_check_cells = true; - if (ff.has_gclk) { - // Already a $ff or $_FF_ cell. + bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool(); + if (!trg_enable) continue; - } - if (ff.has_clk) { - log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n", - log_id(module), log_id(cell), log_id(cell->type), - log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q)); - } else if (ff.has_aload) { - log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", - log_id(module), log_id(cell), log_id(cell->type), - log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q)); + int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int(); + + if (trg_width == 0) { + if (initstate == State::S0) + initstate = module->Initstate(NEW_ID); + + SigBit sig_en = cell->getPort(ID::EN); + cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate)); } else { - // $sr. - log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n", - log_id(module), log_id(cell), log_id(cell->type), - log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q)); + SigBit sig_en = cell->getPort(ID::EN); + SigSpec sig_args = cell->getPort(ID::ARGS); + Const trg_polarity = cell->getParam(ID(TRG_POLARITY)); + SigSpec sig_trg = cell->getPort(ID::TRG); + + SigSpec sig_trg_sampled; + + for (auto const &bit : sig_trg) + sig_trg_sampled.append(sample_control_edge(module, bit, trg_polarity[GetSize(sig_trg_sampled)] == State::S1, false)); + SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled; + SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled; + + SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled); + + cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined)); + cell->setPort(ID::ARGS, sig_args_sampled); + if (cell->type == ID($check)) { + SigBit sig_a_sampled = sample_data(module, sig_en, State::S1, false, false).sampled; + cell->setPort(ID::A, sig_a_sampled); + } } - ff.remove(); + cell->setPort(ID::TRG, SigSpec()); - if (ff.has_clk) - ff.unmap_ce_srst(); + cell->setParam(ID::TRG_ENABLE, false); + cell->setParam(ID::TRG_WIDTH, 0); + cell->setParam(ID::TRG_POLARITY, false); + cell->set_bool_attribute(ID(trg_on_gclk)); - auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled; + continue; + } - if (ff.has_clk) { - // The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs - auto sampled_d = sample_data(module, ff.sig_d, RTLIL::Const(State::S0, ff.width), ff.is_fine); - auto clk_edge = sample_control_edge(module, ff.sig_clk, ff.pol_clk, ff.is_fine); - next_q = mux(module, next_q, sampled_d.sampled, clk_edge, ff.is_fine); - } + if (!RTLIL::builtin_ff_cell_types().count(cell->type)) + continue; - SampledSig sampled_aload, sampled_ad, sampled_set, sampled_clr, sampled_arst; - // The check for a constant sig_aload is also done by opt_dff, but when using verific and running - // clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids - // generating a lot of extra logic. - bool has_nonconst_aload = ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1); - if (has_nonconst_aload) { - sampled_aload = sample_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine); - // The init value for the sampled ad is never used, so we can set it to fixed zero, reducing uninit'd FFs - sampled_ad = sample_data(module, ff.sig_ad, RTLIL::Const(State::S0, ff.width), ff.is_fine); - } - if (ff.has_sr) { - sampled_set = sample_control(module, ff.sig_set, ff.pol_set, ff.is_fine); - sampled_clr = sample_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine); - } - if (ff.has_arst) - sampled_arst = sample_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine); - - // First perform updates using _only_ sampled values, then again using _only_ current values. Unlike the previous - // implementation, this approach correctly handles all the cases of multiple signals changing simultaneously. - for (int current = 0; current < 2; current++) { - if (has_nonconst_aload) - next_q = mux(module, next_q, sampled_ad[current], sampled_aload[current], ff.is_fine); - if (ff.has_sr) - next_q = bitwise_sr(module, next_q, sampled_set[current], sampled_clr[current], ff.is_fine); - if (ff.has_arst) - next_q = mux(module, next_q, ff.val_arst, sampled_arst[current], ff.is_fine); - } + FfData ff(&initvals, cell); - module->connect(ff.sig_q, next_q); + if (ff.has_gclk) { + // Already a $ff or $_FF_ cell. + continue; } + + if (ff.has_clk) { + log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n", + log_id(module), log_id(cell), log_id(cell->type), + log_signal(ff.sig_clk), log_signal(ff.sig_d), log_signal(ff.sig_q)); + } else if (ff.has_aload) { + log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", + log_id(module), log_id(cell), log_id(cell->type), + log_signal(ff.sig_aload), log_signal(ff.sig_ad), log_signal(ff.sig_q)); + } else { + // $sr. + log("Replacing %s.%s (%s): SET=%s, CLR=%s, Q=%s\n", + log_id(module), log_id(cell), log_id(cell->type), + log_signal(ff.sig_set), log_signal(ff.sig_clr), log_signal(ff.sig_q)); + } + + ff.remove(); + + if (ff.has_clk) + ff.unmap_ce_srst(); + + auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled; + + if (ff.has_clk) { + // The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs + auto sampled_d = sample_data(module, ff.sig_d, RTLIL::Const(State::S0, ff.width), ff.is_fine); + auto clk_edge = sample_control_edge(module, ff.sig_clk, ff.pol_clk, ff.is_fine); + next_q = mux(module, next_q, sampled_d.sampled, clk_edge, ff.is_fine); + } + + SampledSig sampled_aload, sampled_ad, sampled_set, sampled_clr, sampled_arst; + // The check for a constant sig_aload is also done by opt_dff, but when using verific and running + // clk2fflogic before opt_dff (which does more and possibly unwanted optimizations) this check avoids + // generating a lot of extra logic. + bool has_nonconst_aload = ff.has_aload && ff.sig_aload != (ff.pol_aload ? State::S0 : State::S1); + if (has_nonconst_aload) { + sampled_aload = sample_control(module, ff.sig_aload, ff.pol_aload, ff.is_fine); + // The init value for the sampled ad is never used, so we can set it to fixed zero, reducing uninit'd FFs + sampled_ad = sample_data(module, ff.sig_ad, RTLIL::Const(State::S0, ff.width), ff.is_fine); + } + if (ff.has_sr) { + sampled_set = sample_control(module, ff.sig_set, ff.pol_set, ff.is_fine); + sampled_clr = sample_control(module, ff.sig_clr, ff.pol_clr, ff.is_fine); + } + if (ff.has_arst) + sampled_arst = sample_control(module, ff.sig_arst, ff.pol_arst, ff.is_fine); + + // First perform updates using _only_ sampled values, then again using _only_ current values. Unlike the previous + // implementation, this approach correctly handles all the cases of multiple signals changing simultaneously. + for (int current = 0; current < 2; current++) { + if (has_nonconst_aload) + next_q = mux(module, next_q, sampled_ad[current], sampled_aload[current], ff.is_fine); + if (ff.has_sr) + next_q = bitwise_sr(module, next_q, sampled_set[current], sampled_clr[current], ff.is_fine); + if (ff.has_arst) + next_q = mux(module, next_q, ff.val_arst, sampled_arst[current], ff.is_fine); + } + + module->connect(ff.sig_q, next_q); + } } + if (have_check_cells && !flag_nolower) { + log_push(); + Pass::call(design, "chformal -lower"); + log_pop(); + } } } Clk2fflogicPass; diff --git a/yosys/passes/sat/recover_names.cc b/yosys/passes/sat/recover_names.cc index 2d7e7f01cfa..4870e2cac19 100644 --- a/yosys/passes/sat/recover_names.cc +++ b/yosys/passes/sat/recover_names.cc @@ -26,16 +26,10 @@ #include #include +#include USING_YOSYS_NAMESPACE -template<> struct hashlib::hash_ops : hashlib::hash_int_ops -{ - static inline unsigned int hash(uint64_t a) { - return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); - } -}; - PRIVATE_NAMESPACE_BEGIN // xorshift128 params @@ -453,7 +447,7 @@ struct RecoverNamesWorker { pool comb_whiteboxes, buffer_types; // class -> (gold, (gate, inverted)) - dict, dict>> cls2bits; + dict, dict>> cls2bits; void analyse_boxes() { @@ -630,7 +624,7 @@ struct RecoverNamesWorker { if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1)) continue; - log_debug("equivalence class: %016lx\n", cls.first); + log_debug("equivalence class: %016" PRIx64 "\n", cls.first); const pool &gold_bits = cls2bits.at(cls.first).first; const pool &gate_bits = cls2bits.at(cls.first).second; if (gold_bits.empty() || gate_bits.empty()) diff --git a/yosys/passes/sat/sim.cc b/yosys/passes/sat/sim.cc index 325e123201c..aeed16b9784 100644 --- a/yosys/passes/sat/sim.cc +++ b/yosys/passes/sat/sim.cc @@ -25,6 +25,7 @@ #include "kernel/ff.h" #include "kernel/yw.h" #include "kernel/json.h" +#include "kernel/fmt.h" #include @@ -87,6 +88,17 @@ struct TriggeredAssertion { { } }; +struct DisplayOutput { + int step; + SimInstance *instance; + Cell *cell; + std::string output; + + DisplayOutput(int step, SimInstance *instance, Cell *cell, std::string output) : + step(step), instance(instance), cell(cell), output(output) + { } +}; + struct SimShared { bool debug = false; @@ -109,6 +121,9 @@ struct SimShared int next_output_id = 0; int step = 0; std::vector triggered_assertions; + std::vector display_output; + bool serious_asserts = false; + bool initstate = true; }; void zinit(State &v) @@ -168,11 +183,39 @@ struct SimInstance Const data; }; + struct print_state_t + { + bool initial_done; + Const past_trg; + Const past_en; + Const past_args; + + Cell *cell; + Fmt fmt; + + std::tuple _sort_label() const + { + return std::make_tuple( + cell->getParam(ID::TRG_ENABLE).as_bool(), // Group by trigger + cell->getPort(ID::TRG), + cell->getParam(ID::TRG_POLARITY), + -cell->getParam(ID::PRIORITY).as_int(), // Then sort by descending PRIORITY + cell + ); + } + + bool operator<(const print_state_t &other) const + { + return _sort_label() < other._sort_label(); + } + }; + dict ff_database; dict mem_database; pool formal_database; pool initstate_database; dict mem_cells; + std::vector print_database; std::vector memories; @@ -189,9 +232,13 @@ struct SimInstance log_assert(module); if (module->get_blackbox_attribute(true)) - log_error("Cannot simulate blackbox module %s (instanced at %s).\n", + log_error("Cannot simulate blackbox module %s (instantiated at %s).\n", log_id(module->name), hiername().c_str()); + if (module->has_processes()) + log_error("Found processes in simulation hierarchy (in module %s at %s). Run 'proc' first.\n", + log_id(module), hiername().c_str()); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; @@ -289,13 +336,27 @@ struct SimInstance if (shared->fst) fst_memories[name] = shared->fst->getMemoryHandles(scope + "." + RTLIL::unescape_id(name)); } - if (cell->type.in(ID($assert), ID($cover), ID($assume))) { + + if (cell->type.in(ID($assert), ID($cover), ID($assume))) formal_database.insert(cell); - } + if (cell->type == ID($initstate)) initstate_database.insert(cell); + + if (cell->type == ID($print)) { + print_database.emplace_back(); + auto &print = print_database.back(); + print.cell = cell; + print.fmt.parse_rtlil(cell); + print.past_trg = Const(State::Sx, cell->getPort(ID::TRG).size()); + print.past_args = Const(State::Sx, cell->getPort(ID::ARGS).size()); + print.past_en = State::Sx; + print.initial_done = false; + } } + std::sort(print_database.begin(), print_database.end()); + if (shared->zinit) { for (auto &it : ff_database) @@ -519,6 +580,9 @@ struct SimInstance return; } + if (cell->type == ID($print)) + return; + log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell)); } @@ -533,7 +597,7 @@ struct SimInstance Const data = Const(State::Sx, mem.width << port.wide_log2); if (port.clk_enable) - log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid)); + log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid)); if (addr.is_fully_def()) { int addr_int = addr.as_int(); @@ -725,7 +789,31 @@ struct SimInstance return did_something; } - void update_ph3(bool check_assertions) + static void log_source(RTLIL::AttrObject *src) + { + for (auto src : src->get_strpool_attribute(ID::src)) + log(" %s\n", src.c_str()); + } + + void log_cell_w_hierarchy(std::string opening_verbiage, RTLIL::Cell *cell) + { + log_assert(cell->module == module); + bool has_src = cell->has_attribute(ID::src); + log("%s %s%s\n", opening_verbiage.c_str(), + log_id(cell), has_src ? " at" : ""); + log_source(cell); + + struct SimInstance *sim = this; + while (sim->instance) { + has_src = sim->instance->has_attribute(ID::src); + log(" in instance %s of module %s%s\n", log_id(sim->instance), + log_id(sim->instance->type), has_src ? " at" : ""); + log_source(sim->instance); + sim = sim->parent; + } + } + + void update_ph3(bool gclk_trigger) { for (auto &it : ff_database) { @@ -760,7 +848,63 @@ struct SimInstance } } - if (check_assertions) + // Do prints *before* assertions + for (auto &print : print_database) { + Cell *cell = print.cell; + bool triggered = false; + + Const trg = get_state(cell->getPort(ID::TRG)); + bool trg_en = cell->getParam(ID::TRG_ENABLE).as_bool(); + Const en = get_state(cell->getPort(ID::EN)); + Const args = get_state(cell->getPort(ID::ARGS)); + + bool sampled = trg_en && trg.size() > 0; + + if (sampled ? print.past_en.as_bool() : en.as_bool()) { + if (sampled) { + sampled = true; + Const trg_pol = cell->getParam(ID::TRG_POLARITY); + for (int i = 0; i < trg.size(); i++) { + bool pol = trg_pol[i] == State::S1; + State curr = trg[i], past = print.past_trg[i]; + if (pol && curr == State::S1 && past == State::S0) + triggered = true; + if (!pol && curr == State::S0 && past == State::S1) + triggered = true; + } + } else if (trg_en) { + // initial $print (TRG width = 0, TRG_ENABLE = true) + if (!print.initial_done && en != print.past_en) + triggered = true; + } else if (cell->get_bool_attribute(ID(trg_on_gclk))) { + // unified $print for cycle based FV semantics + triggered = gclk_trigger; + } else { + // always @(*) $print + if (args != print.past_args || en != print.past_en) + triggered = true; + } + + if (triggered) { + int pos = 0; + for (auto &part : print.fmt.parts) { + part.sig = (sampled ? print.past_args : args).extract(pos, part.sig.size()); + pos += part.sig.size(); + } + + std::string rendered = print.fmt.render(); + log("%s", rendered.c_str()); + shared->display_output.emplace_back(shared->step, this, cell, rendered); + } + } + + print.past_trg = trg; + print.past_en = en; + print.past_args = args; + print.initial_done = true; + } + + if (gclk_trigger) { for (auto cell : formal_database) { @@ -781,13 +925,18 @@ struct SimInstance if (cell->type == ID($assume) && en == State::S1 && a != State::S1) log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); - if (cell->type == ID($assert) && en == State::S1 && a != State::S1) - log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + if (cell->type == ID($assert) && en == State::S1 && a != State::S1) { + log_cell_w_hierarchy("Failed assertion", cell); + if (shared->serious_asserts) + log_error("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + else + log_warning("Assertion %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str()); + } } } for (auto it : children) - it.second->update_ph3(check_assertions); + it.second->update_ph3(gclk_trigger); } void set_initstate_outputs(State state) @@ -1263,6 +1412,8 @@ struct SimWorker : SimShared set_inports(clock, State::Sx); set_inports(clockn, State::Sx); + top->set_initstate_outputs(initstate ? State::S1 : State::S0); + update(false); register_output_step(0); @@ -1279,6 +1430,9 @@ struct SimWorker : SimShared update(true); register_output_step(10*cycle + 5); + if (cycle == 0) + top->set_initstate_outputs(State::S0); + if (debug) log("\n===== %d =====\n", 10*cycle + 10); else if (verbose) @@ -1860,7 +2014,7 @@ struct SimWorker : SimShared if (yw.steps.empty()) { log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str()); } else { - top->set_initstate_outputs(State::S1); + top->set_initstate_outputs(initstate ? State::S1 : State::S0); set_yw_state(yw, hierarchy, 0); set_yw_clocks(yw, hierarchy, true); initialize_stable_past(); @@ -1927,6 +2081,20 @@ struct SimWorker : SimShared json.end_object(); } json.end_array(); + json.name("display_output"); + json.begin_array(); + for (auto &output : display_output) { + json.begin_object(); + json.entry("step", output.step); + json.entry("path", output.instance->witness_full_path(output.cell)); + auto src = output.cell->get_string_attribute(ID::src); + if (!src.empty()) { + json.entry("src", src); + } + json.entry("output", output.output); + json.end_object(); + } + json.end_array(); json.end_object(); } @@ -2453,6 +2621,9 @@ struct SimPass : public Pass { log(" -n \n"); log(" number of clock cycles to simulate (default: 20)\n"); log("\n"); + log(" -noinitstate\n"); + log(" do not activate $initstate cells during the first cycle\n"); + log("\n"); log(" -a\n"); log(" use all nets in VCD/FST operations, not just those with public names\n"); log("\n"); @@ -2497,6 +2668,10 @@ struct SimPass : public Pass { log(" -sim-gate\n"); log(" co-simulation, x in FST can match any value in simulation\n"); log("\n"); + log(" -assert\n"); + log(" fail the simulation command if, in the course of simulating,\n"); + log(" any of the asserts in the design fail\n"); + log("\n"); log(" -q\n"); log(" disable per-cycle/sample log message\n"); log("\n"); @@ -2549,6 +2724,10 @@ struct SimPass : public Pass { worker.cycles_set = true; continue; } + if (args[argidx] == "-noinitstate") { + worker.initstate = false; + continue; + } if (args[argidx] == "-rstlen" && argidx+1 < args.size()) { worker.rstlen = atoi(args[++argidx].c_str()); continue; @@ -2651,6 +2830,10 @@ struct SimPass : public Pass { worker.sim_mode = SimulationMode::gate; continue; } + if (args[argidx] == "-assert") { + worker.serious_asserts = true; + continue; + } if (args[argidx] == "-x") { worker.ignore_x = true; continue; diff --git a/yosys/passes/techmap/Makefile.inc b/yosys/passes/techmap/Makefile.inc index 1b834fabc3b..97d8b76f3b8 100644 --- a/yosys/passes/techmap/Makefile.inc +++ b/yosys/passes/techmap/Makefile.inc @@ -4,6 +4,7 @@ OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o OBJS += passes/techmap/maccmap.o +OBJS += passes/techmap/booth.o OBJS += passes/techmap/libparse.o ifeq ($(ENABLE_ABC),1) diff --git a/yosys/passes/techmap/abc.cc b/yosys/passes/techmap/abc.cc index 364a8e54458..42287966288 100644 --- a/yosys/passes/techmap/abc.cc +++ b/yosys/passes/techmap/abc.cc @@ -127,10 +127,15 @@ bool clk_polarity, en_polarity, arst_polarity, srst_polarity; RTLIL::SigSpec clk_sig, en_sig, arst_sig, srst_sig; dict pi_map, po_map; +int undef_bits_lost; + int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1) { assign_map.apply(bit); + if (bit == State::Sx) + undef_bits_lost++; + if (signal_map.count(bit) == 0) { gate_t gate; gate.id = signal_list.size(); @@ -702,7 +707,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin std::vector &liberty_files, std::vector &genlib_files, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, bool abc_dress) + const std::vector &cells, bool show_tempdir, bool sop_mode, bool abc_dress, std::vector &dont_use_cells) { module = current_module; map_autoidx = autoidx++; @@ -795,8 +800,13 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin std::string abc_script = stringf("read_blif \"%s/input.blif\"; ", tempdir_name.c_str()); if (!liberty_files.empty() || !genlib_files.empty()) { - for (std::string liberty_file : liberty_files) - abc_script += stringf("read_lib -w \"%s\"; ", liberty_file.c_str()); + std::string dont_use_args; + for (std::string dont_use_cell : dont_use_cells) { + dont_use_args += stringf("-X \"%s\" ", dont_use_cell.c_str()); + } + for (std::string liberty_file : liberty_files) { + abc_script += stringf("read_lib %s -w \"%s\" ; ", dont_use_args.c_str(), liberty_file.c_str()); + } for (std::string liberty_file : genlib_files) abc_script += stringf("read_library \"%s\"; ", liberty_file.c_str()); if (!constr_file.empty()) @@ -880,10 +890,15 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } } + undef_bits_lost = 0; + had_init = false; for (auto c : cells) extract_cell(c, keepff); + if (undef_bits_lost) + log("Replacing %d occurrences of constant undef bits with constant zero bits\n", undef_bits_lost); + for (auto wire : module->wires()) { if (wire->port_id > 0 || wire->get_bool_attribute(ID::keep)) mark_port(wire); @@ -1503,6 +1518,10 @@ struct AbcPass : public Pass { log(" generate netlists for the specified cell library (using the liberty\n"); log(" file format).\n"); log("\n"); + log(" -dont_use \n"); + log(" generate netlists for the specified cell library (using the liberty\n"); + log(" file format).\n"); + log("\n"); log(" -genlib \n"); log(" generate netlists for the specified cell library (using the SIS Genlib\n"); log(" file format).\n"); @@ -1639,7 +1658,7 @@ struct AbcPass : public Pass { std::string exe_file = yosys_abc_executable; std::string script_file, default_liberty_file, constr_file, clk_str; - std::vector liberty_files, genlib_files; + std::vector liberty_files, genlib_files, dont_use_cells; std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; @@ -1722,6 +1741,10 @@ struct AbcPass : public Pass { liberty_files.push_back(args[++argidx]); continue; } + if (arg == "-dont_use" && argidx+1 < args.size()) { + dont_use_cells.push_back(args[++argidx]); + continue; + } if (arg == "-genlib" && argidx+1 < args.size()) { genlib_files.push_back(args[++argidx]); continue; @@ -2028,7 +2051,7 @@ struct AbcPass : public Pass { if (!dff_mode || !clk_str.empty()) { abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, - delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress); + delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress, dont_use_cells); continue; } @@ -2190,7 +2213,7 @@ struct AbcPass : public Pass { srst_polarity = std::get<6>(it.first); srst_sig = assign_map(std::get<7>(it.first)); abc_module(design, mod, script_file, exe_file, liberty_files, genlib_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", - keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress); + keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress, dont_use_cells); assign_map.set(mod); } } diff --git a/yosys/passes/techmap/booth.cc b/yosys/passes/techmap/booth.cc new file mode 100644 index 00000000000..09c20b50712 --- /dev/null +++ b/yosys/passes/techmap/booth.cc @@ -0,0 +1,1191 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 Andy Fox https://www.linkedin.com/in/awfox/ + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* + Booth Pass + ---------- + + Replace $mul with booth encoded multipliers. Two different + architectures used for signed/unsigned. + + References: + Signed architecture: A Low Power Radix-4 Booth Multipliers with Pre-Encoded Mechanism, IEEE Access + https://ieeexplore.ieee.org/document/9121226 + + Unsigned architecture: Gary Bewick, Fast Multiplication algorithms and implementation. Stanford PhD: + http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf + + How to use: + Add booth pass to your yosys script eg: + + read_verilog smultiply5_rtl.v + opt + wreduce + opt + booth + alumacc + maccmap + opt + techmap -map ./techmap.v + dfflibmap -liberty NangateOpenCellLibrary_typical.lib + abc -liberty NangateOpenCellLibrary_typical.lib + stat -liberty NangateOpenCellLibrary_typical.lib + write_verilog -norename booth_final.v + +or in generic synthesis call with -booth argument: +synth -top my_design -booth +*/ + +//FIXME: These debug prints are broken now, should be fixed or removed. +//#define DEBUG_CPA + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct BoothPassWorker { + + RTLIL::Module *module; + SigMap sigmap; + int booth_counter; + bool lowpower = false; + bool mapped_cpa = false; + + BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; } + + // Booth unsigned decoder lsb + SigBit Bur4d_lsb(std::string name, SigBit lsb_i, SigBit one_i, SigBit s_i) + { + SigBit and_op = module->AndGate(NEW_ID_SUFFIX(name), lsb_i, one_i); + return module->XorGate(NEW_ID_SUFFIX(name), and_op, s_i); + } + + // Booth unsigned radix4 decoder + SigBit Bur4d_n(std::string name, SigBit yn_i, SigBit ynm1_i, SigBit one_i, SigBit two_i, SigBit s_i) + { + // ppij = ((yn & one) | (ynm1 & two)) ^ s; + SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), yn_i, one_i); + SigBit an2 = module->AndGate(NEW_ID_SUFFIX(name), ynm1_i, two_i); + SigBit or1 = module->OrGate(NEW_ID_SUFFIX(name), an1, an2); + return module->XorGate(NEW_ID_SUFFIX(name), s_i, or1); + } + + // Booth unsigned radix4 decoder + SigBit Bur4d_msb(std::string name, SigBit msb_i, SigBit two_i, SigBit s_i) + { + // ppij = (msb & two) ^ s; + SigBit an1 = module->AndGate(NEW_ID_SUFFIX(name), msb_i, two_i); + return module->XorGate(NEW_ID_SUFFIX(name), s_i, an1); + } + + // half adder, used in CPA + void BuildHa(std::string name, SigBit a_i, SigBit b_i, SigBit &s_o, SigBit &c_o) + { + s_o = module->XorGate(NEW_ID_SUFFIX(name), a_i, b_i); + c_o = module->AndGate(NEW_ID_SUFFIX(name), a_i, b_i); + } + + // Booth unsigned radix 4 encoder + void BuildBur4e(std::string name, SigBit y0_i, SigBit y1_i, SigBit y2_i, + SigBit &one_o, SigBit &two_o, SigBit &s_o, SigBit &sb_o) + { + one_o = module->XorGate(NEW_ID_SUFFIX(name), y0_i, y1_i); + s_o = y2_i; + sb_o = module->NotGate(NEW_ID_SUFFIX(name), y2_i); + SigBit y1_xnor_y2 = module->XnorGate(NEW_ID_SUFFIX(name), y1_i, y2_i); + two_o = module->NorGate(NEW_ID_SUFFIX(name), y1_xnor_y2, one_o); + } + + void BuildBr4e(std::string name, SigBit y2_m1_i, + SigBit y2_i, // y2i + SigBit y2_p1_i, + SigBit &negi_o, SigBit &twoi_n_o, SigBit &onei_n_o, SigBit &cori_o) + { + auto y2_p1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_p1_i); + auto y2_n = module->NotGate(NEW_ID_SUFFIX(name), y2_i); + auto y2_m1_n = module->NotGate(NEW_ID_SUFFIX(name), y2_m1_i); + + negi_o = y2_p1_i; + + // twoi_n = ~( + // (y2_p1_n & y2_i & y2_m1_i) | + // (y2_p1 & y2_n & y2_m1_n) + // ) + twoi_n_o = module->NorGate(NEW_ID_SUFFIX(name), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_n, module->AndGate(NEW_ID_SUFFIX(name), y2_i, y2_m1_i)), + module->AndGate(NEW_ID_SUFFIX(name), y2_p1_i, module->AndGate(NEW_ID_SUFFIX(name), y2_n, y2_m1_n)) + ); + + // onei_n = ~(y2_m1_i ^ y2_i); + onei_n_o = module->XnorGate(NEW_ID_SUFFIX(name), y2_m1_i, y2_i); + // cori = (y2_m1_n | y2_n) & y2_p1_i; + cori_o = module->AndGate(NEW_ID_SUFFIX(name), module->OrGate(NEW_ID_SUFFIX(name), y2_m1_n, y2_n), y2_p1_i); + } + + // + // signed booth radix 4 decoder + // + void BuildBr4d(std::string name, SigBit nxj_m1_i, SigBit twoi_n_i, SigBit xj_i, SigBit negi_i, SigBit onei_n_i, + SigBit &ppij_o, SigBit &nxj_o) + { + // nxj_in = xnor(xj,negi) + // nxj_o = xnj_in, + // ppij = ~( (nxj_m1_i | twoi_n_i) & (nxj_int | onei_n_i)); + nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), xj_i, negi_i); + ppij_o = module->NandGate(NEW_ID_SUFFIX(name), + module->OrGate(NEW_ID_SUFFIX(name), nxj_m1_i, twoi_n_i), + module->OrGate(NEW_ID_SUFFIX(name), nxj_o, onei_n_i) + ); + } + + /* + In signed case 1st two bits best realised + using non-booth encoded logic. We can save a booth + encoder for the first couple of bits. + */ + void BuildBoothQ1(std::string name, SigBit negi_i, SigBit cori_i, SigBit x0_i, SigBit x1_i, SigBit y0_i, + SigBit y1_i, + SigBit &nxj_o, SigBit &cor_o, SigBit &pp0_o, SigBit &pp1_o) + { + /* + assign NXJO = ~(X1 ^ NEGI); + assign PP0 = (X0 & Y0); + //and terms for multiply + wire pp1_1_int = X1 & Y0; + wire pp1_2_int = X0 & Y1; + //sum generation for pp[1] + assign PP1 = pp1_1_int ^ pp1_2_int; + //correction propagation + assign CORO = (~PP1 & ~PP0)? CORI : 1'b0; + */ + nxj_o = module->XnorGate(NEW_ID_SUFFIX(name), x1_i, negi_i); + pp0_o = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y0_i); + SigBit pp1_1_int = module->AndGate(NEW_ID_SUFFIX(name), x1_i, y0_i); + SigBit pp1_2_int = module->AndGate(NEW_ID_SUFFIX(name), x0_i, y1_i); + pp1_o = module->XorGate(NEW_ID_SUFFIX(name), pp1_1_int, pp1_2_int); + + SigBit pp1_nor_pp0 = module->NorGate(NEW_ID_SUFFIX(name), pp1_o, pp0_o); + cor_o = module->AndGate(NEW_ID_SUFFIX(name), pp1_nor_pp0, cori_i); + } + + void BuildBitwiseFa(Module *mod, std::string name, const SigSpec &sig_a, const SigSpec &sig_b, + const SigSpec &sig_c, const SigSpec &sig_x, const SigSpec &sig_y, + const std::string &src = "") + { + // We can't emit a single wide full-adder cell here since + // there would typically be feedback loops involving the cells' + // input and output ports, and Yosys doesn't cope well with + // those + log_assert(sig_a.size() == sig_b.size()); + log_assert(sig_a.size() == sig_c.size()); + log_assert(sig_a.size() == sig_x.size()); + log_assert(sig_a.size() == sig_y.size()); + + for (int i = 0; i < sig_a.size(); i++) + mod->addFa(stringf("%s[%d]", name.c_str(), i), sig_a[i], sig_b[i], + sig_c[i], sig_x[i], sig_y[i], src); + } + + void run() + { + for (auto cell : module->selected_cells()) { + if (cell->type != ID($mul)) + continue; + + SigSpec A = cell->getPort(ID::A); + SigSpec B = cell->getPort(ID::B); + SigSpec Y = cell->getPort(ID::Y); + int x_sz = GetSize(A), y_sz = GetSize(B), z_sz = GetSize(Y); + + if (x_sz < 4 || y_sz < 4 || z_sz < 8) { + log_debug("Not mapping cell %s sized at %dx%x, %x: size below threshold\n", + log_id(cell), x_sz, y_sz, z_sz); + continue; + } + + log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool()); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + + log("Mapping cell %s to %s Booth multiplier\n", log_id(cell), is_signed ? "signed" : "unsigned"); + + // To simplify the generator size the arguments + // to be the same. Then allow logic synthesis to + // clean things up. Size to biggest + + int x_sz_revised = x_sz; + int y_sz_revised = y_sz; + + if (x_sz != y_sz) { + if (x_sz < y_sz) { + if (y_sz % 2 != 0) { + x_sz_revised = y_sz + 1; + y_sz_revised = y_sz + 1; + } else { + x_sz_revised = y_sz; + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = x_sz + 1; + x_sz_revised = x_sz + 1; + } else { + y_sz_revised = x_sz; + } + } + } else { + if (x_sz % 2 != 0) { + y_sz_revised = y_sz + 1; + x_sz_revised = x_sz + 1; + } + } + + log_assert((x_sz_revised == y_sz_revised) && (x_sz_revised % 2 == 0) && (y_sz_revised % 2 == 0)); + + + A.extend_u0(x_sz_revised, is_signed); + B.extend_u0(y_sz_revised, is_signed); + + // Make sure output domain is big enough to take + // all combinations. + // Later logic synthesis will kill unused + // portions of the output domain. + + int required_op_size = x_sz_revised + y_sz_revised; + + if (required_op_size != z_sz) { + SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size); + SigSpec Y_driver = expanded_Y; + Y_driver.extend_u0(Y.size(), is_signed); + module->connect(Y, Y_driver); + Y = expanded_Y; + } + log_assert(GetSize(Y) == required_op_size); + + if (!lowpower) + CreateBoothMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y, // result + is_signed + ); + else + CreateBoothLowpowerMult(module, + A, // multiplicand + B, // multiplier(scanned) + Y, // result + is_signed + ); + + module->remove(cell); + booth_counter++; + } + } + + SigSig WallaceSum(int width, std::vector summands) + { + for (auto &s : summands) + s.extend_u0(width); + + while (summands.size() > 2) { + std::vector new_summands; + int i; + for (i = 0; i < (int) summands.size() - 2; i += 3) { + SigSpec x = module->addWire(NEW_ID, width); + SigSpec y = module->addWire(NEW_ID, width); + BuildBitwiseFa(module, NEW_ID.str(), summands[i], summands[i + 1], + summands[i + 2], x, y); + new_summands.push_back(y); + new_summands.push_back({x.extract(0, width - 1), State::S0}); + } + + new_summands.insert(new_summands.begin(), summands.begin() + i, summands.end()); + + std::swap(summands, new_summands); + } + + if (!summands.size()) + return SigSig(SigSpec(width, State::S0), SigSpec(width, State::S0)); + else if (summands.size() == 1) + return SigSig(summands[0], SigSpec(width, State::S0)); + else + return SigSig(summands[0], summands[1]); + } + + /* + Build Multiplier. + ------------------------- + Uses a generic booth multiplier + */ + + void CreateBoothMult(RTLIL::Module *module, + SigSpec X, // multiplicand + SigSpec Y, // multiplier + SigSpec Z, + bool is_signed) + { // result + int z_sz = Z.size(); + + SigSpec one_int, two_int, s_int, sb_int; + int encoder_count = 0; + + BuildBoothMultEncoders(Y, one_int, two_int, s_int, sb_int, module, encoder_count, is_signed); + + // Build the decoder rows + // format of each Partial product to be passed to CSA + // tree builder: + // + // Bits to be added + // Shift + // Sign bit to be added + // + std::vector> ppij_int; + + // Row 0: special case 1. Format S/.S.S.C.Data + SigSpec ppij_row_0; + BuildBoothMultDecoderRow0(module, X, s_int, sb_int, one_int, two_int, ppij_row_0, is_signed); + + // data, shift, sign + ppij_int.push_back(std::make_tuple(ppij_row_0, 0, s_int[0])); + + for (int i = 1; i < encoder_count; i++) { + // format 1,S.Data.shift = encoder_ix*2,sign = sb_int[i] + SigSpec ppij_row_n; + + BuildBoothMultDecoderRowN(module, + X, // multiplicand + one_int[i], two_int[i], s_int[i], sb_int[i], ppij_row_n, i, + is_signed + ); + // data, shift, sign + ppij_int.push_back(std::make_tuple(ppij_row_n, i * 2, s_int[i])); + } + + + // Debug dump out partial products + // DebugDumpPP(ppij_int); + + // Summation of Partial Products (Wallace Tree) + std::vector aligned_pp; + aligned_pp.resize(encoder_count + 1); // make an entirely redundant row + // just for sign bit in lsb. (We then filter this out). + + // resize all to be same size as z + for (int i = 0; i < encoder_count + 1; i++) + aligned_pp[i].extend_u0(z_sz); + + AlignPP(z_sz, ppij_int, aligned_pp); + + // Debug: dump out aligned partial products. + // Later on yosys will clean up unused constants + // DebugDumpAlignPP(aligned_pp); + + SigSig wtree_sum = WallaceSum(z_sz, aligned_pp); + + // Debug code: Dump out the csa trees + // DumpCSATrees(debug_csa_trees); + // Build the CPA to do the final accumulation. + log_assert(wtree_sum.second[0] == State::S0); + if (mapped_cpa) + BuildCPA(module, wtree_sum.first, {State::S0, wtree_sum.second.extract_end(1)}, Z); + else + module->addAdd(NEW_ID, wtree_sum.first, {wtree_sum.second.extract_end(1), State::S0}, Z); + } + + /* + Build Row 0 of decoders + */ + + void BuildBoothMultDecoderRow0(RTLIL::Module *module, + SigSpec X, // multiplicand + SigSpec s_int, SigSpec sb_int, SigSpec one_int, + SigSpec two_int, SigSpec &ppij_vec, bool is_signed) + { + (void)sb_int; + (void)module; + int x_sz = GetSize(X); + SigBit ppij; + + // lsb + ppij_vec.append(Bur4d_lsb("row0_lsb_dec", X[0], one_int[0], s_int[0])); + + // 1..xsize -1 + for (int i = 1; i < x_sz; i++) + ppij_vec.append(Bur4d_n(stringf("row0_dec_%d", i), X[i], X[i - 1], + one_int[0], two_int[0], s_int[0])); + + + // The redundant bit. Duplicate decoding of last bit. + if (!is_signed) { + ppij_vec.append(Bur4d_msb("row0_dec_msb", X.msb(), two_int[0], s_int[0])); + } else { + ppij_vec.append(Bur4d_n("row0_dec_msb", X.msb(), X.msb(), + one_int[0], two_int[0], s_int[0])); + } + + // append the sign bits + if (is_signed) { + SigBit e = module->XorGate(NEW_ID, s_int[0], module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int[0], one_int[0]))); + ppij_vec.append({module->NotGate(NEW_ID, e), e, e}); + } else { + // append the sign bits + ppij_vec.append({module->NotGate(NEW_ID, s_int[0]), s_int[0], s_int[0]}); + } + } + + // Build a generic row of decoders. + + void BuildBoothMultDecoderRowN(RTLIL::Module *module, + SigSpec X, // multiplicand + SigSpec one_int, SigSpec two_int, SigSpec s_int, SigSpec sb_int, + SigSpec &ppij_vec, int row_ix, + bool is_signed) + { + (void)module; + int x_sz = GetSize(X); + + // lsb + ppij_vec.append(Bur4d_lsb(stringf("row_%d_lsb_dec", row_ix), X[0], one_int, s_int)); + + // core bits + for (int i = 1; i < x_sz; i++) + ppij_vec.append(Bur4d_n(stringf("row_%d_dec_%d", row_ix, i), X[i], X[i - 1], + one_int, two_int, s_int)); + + if (!is_signed) { // redundant bit + ppij_vec.append(Bur4d_msb("row_dec_red", X[x_sz - 1], two_int, s_int)); + } else { + ppij_vec.append(Bur4d_n(stringf("row_%d_dec_msb", row_ix), X[x_sz - 1], X[x_sz - 1], + one_int, two_int, s_int)); + } + + ppij_vec.append(!is_signed ? sb_int[0] : module->XorGate(NEW_ID, sb_int, module->AndGate(NEW_ID, X.msb(), module->OrGate(NEW_ID, two_int, one_int)))); + ppij_vec.append(State::S1); + } + + void DebugDumpAlignPP(std::vector> &aligned_pp) + { + printf("Aligned & Padded Partial products\n"); + int pp_ix = 0; + for (auto pp_row : aligned_pp) { + printf("PP_%d \t", pp_ix); + for (unsigned i = 0; i < pp_row.size(); i++) + printf("[%d] %s ", i, pp_row[i] == nullptr ? " 0 " : pp_row[i]->name.c_str()); + printf("\n"); + pp_ix++; + } + } + + // Debug routines to inspect intermediate results + void DebugDumpPP(std::vector, int, RTLIL::Wire *>> &ppij_int) + { + printf("Debug dump of partial products\n"); + int pp_ix = 0; + + for (auto pp : ppij_int) { + int shift = get<1>(pp); + RTLIL::Wire *sign_bit = get<2>(pp); + + printf("PP %d\n", pp_ix); + printf("\tShift %d\n", shift); + printf("\tData (0 lsb)\n\t"); + int ix = 0; + + for (auto pp_wire : get<0>(pp)) { + RTLIL::IdString wire_name = pp_wire->name; + + printf(" [%d]:%s ", ix, wire_name.c_str()); + ix++; + } + printf("\n"); + printf("\tSign bit to add in: %s\n", sign_bit->name.c_str()); + + pp_ix++; + } + } + + void DumpCSATrees(std::vector> &debug_csa_trees) + { + int i = 0; + for (auto csa_tree : debug_csa_trees) { + printf("CSA Tree column %d\n", i); + int ix = 0; + for (auto csa_elem : csa_tree) { + printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str()); + if (csa_elem->getPort(ID::A) == State::S0) + printf("\tA set to constant 0\n"); + else if (csa_elem->getPort(ID::A) == State::S1) + printf("\tA set to constant 1\n"); + else + printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str()); + + if (csa_elem->getPort(ID::B) == State::S0) + printf("\tB set to constant 0\n"); + else if (csa_elem->getPort(ID::B) == State::S1) + printf("\tB set to constant 1\n"); + else + printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str()); + + if (csa_elem->getPort(ID::C) == State::S0) + printf("\tC set to constant 0\n"); + else if (csa_elem->getPort(ID::C) == State::S1) + printf("\tC set to constant 1\n"); + else + printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str()); + + printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str()); + printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str()); + + ix++; + } + i++; + } + } + + void BuildCSATree(RTLIL::Module *module, std::vector &bits_to_reduce, SigSpec &s_vec, + SigSpec &c_vec, std::vector> &debug_csa_trees) + { + + if (!(bits_to_reduce.size() > 0)) + return; + + int column_size = bits_to_reduce[0].size(); + int row_size = bits_to_reduce.size(); + SigSpec carry_bits_to_add_to_next_column; + + for (int column_ix = 0; column_ix < column_size; column_ix++) { + + // get the bits in this column. + SigSpec column_bits; + for (int row_ix = 0; row_ix < row_size; row_ix++) { + if (bits_to_reduce[row_ix][column_ix] != State::S0) + column_bits.append(bits_to_reduce[row_ix][column_ix]); + } + for (auto c : carry_bits_to_add_to_next_column) { +#ifdef DEBUG_CSA + printf("\t Propagating column bit %s to column %d from column %d\n", c->name.c_str(), column_ix, column_ix - 1); +#endif + column_bits.append(c); + } + + carry_bits_to_add_to_next_column = {}; + +#ifdef DEBUG_CSA + printf("Column %d Reducing %d bits\n", column_ix, column_bits.size()); + for (auto b : column_bits) { + printf("\t %s\n", b->name.c_str()); + } + printf("\n"); +#endif + + SigBit s, c; +#ifdef DEBUG_CSA + int csa_count_before = debug_csa_trees[column_ix].size(); +#endif + + ReduceBits(module, column_ix, column_bits, s, c, carry_bits_to_add_to_next_column, debug_csa_trees); + + s_vec.append(s); + c_vec.append(c); + +#ifdef DEBUG_CSA + int csa_count_after = debug_csa_trees[column_ix].size(); + + printf("Column %d Created %d csa tree elements\n", column_ix, csa_count_after - csa_count_before); +#endif + } + } + + /* + Alignment: + --------- + + Concept traverse from last row. + Pad row by shift + Add sign bit from prior row to 2 bits right of end of data. + + Example + + SCDDDDDDD- +S + DDDDDDDD_ + + ==> + SCDDDDDDD- + DDDDDDDD_S <-- prior rows sign bit added 2 columns to right on next row. + + Pad out rows with zeros and left the opt pass clean them up. + + */ + void AlignPP(int z_sz, std::vector> &ppij_int, + std::vector &aligned_pp) + { + unsigned aligned_pp_ix = aligned_pp.size() - 1; + + // default is zero for everything (so don't have to think to hard + // about padding). + + for (unsigned i = 0; i < aligned_pp.size(); i++) { + for (int j = 0; j < z_sz; j++) { + aligned_pp[i][j] = State::S0; + } + } + + // for very last row we just have the sign bit + // Note that the aligned_pp is one row bigger + // than the ppij_int. We put the sign bit + // in first column of the last partial product + // which is at index corresponding to size of multiplicand + { + int prior_row_idx = get<1>(ppij_int[aligned_pp_ix - 1]); + SigBit prior_row_sign = get<2>(ppij_int[aligned_pp_ix - 1]); + if (prior_row_idx < z_sz) + aligned_pp[aligned_pp_ix][prior_row_idx] = prior_row_sign; + } + + for (int row_ix = aligned_pp_ix - 1; row_ix >= 0; row_ix--) { + int shift_amount = get<1>(ppij_int[row_ix]); + + // copy in data + int copy_ix = shift_amount; + for (auto w : get<0>(ppij_int[row_ix])) { + if (copy_ix < aligned_pp[row_ix].size()) { + aligned_pp[row_ix][copy_ix] = w; + } + copy_ix++; + } + + // copy in the sign bit from the prior row + if (row_ix > 0) { + // if sign bit on prior row, copy in + // the destination of the sign bit is the (row_ix -1)*2 + // eg destination for sign bit for row 0 is 0. + // eg destination for sign bit for row 1 is 1 + SigBit prior_row_sign = get<2>(ppij_int[row_ix - 1]); + copy_ix = (row_ix - 1) * 2; + aligned_pp[row_ix][copy_ix] = prior_row_sign; + } + } + } + + /* + Build a Carry Propagate Adder + ----------------------------- + First build the sum and carry vectors to be added. + */ + void BuildCPA(RTLIL::Module *module, SigSpec s_vec, SigSpec c_vec, SigSpec result) + { + static int cpa_id; + cpa_id++; + + log_assert(c_vec.size() == s_vec.size()); + log_assert(result.size() == s_vec.size()); + + SigBit carry; + for (int n = 0; n < s_vec.size(); n++) { + std::string carry_name; + + // Base Case: Bit 0 is sum 0 + if (n == 0) { + module->addBufGate(NEW_ID_SUFFIX(stringf("base_buf_%d_%d", cpa_id, n)), s_vec[0], result[0]); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IP 0 %s \n", n, buf->name.c_str(), s_vec[0]->name.c_str()); +#endif + } + + // + // Base Case + // c,s = ha(s_vec[1],c_vec[0]) + // + else if (n == 1) { + std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); + SigBit ha_op; + BuildHa(ha_name, s_vec[n], c_vec[n - 1], ha_op, carry); + module->connect(result[n], ha_op); + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] \n", n, ha_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str()); +#endif + + } + // End Case + else if (n == s_vec.size() - 1) { + // Make the carry results.. Two extra bits after fa. + SigBit carry_out = module->addWire(NEW_ID, 1); + module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + /* A */ s_vec[n], + /* B */ c_vec[n - 1], + /* C */ carry, + /* X */ carry_out, + /* Y */ result[n] + ); + carry = carry_out; + +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str(), carry->name.c_str()); +#endif + if (n + 1 < GetSize(result)) { + // Now make a half adder: c_vec[n] = carry + std::string ha_name = "cpa_" + std::to_string(cpa_id) + "_ha_" + std::to_string(n); + SigBit ha_sum; + SigBit ha_carry; + BuildHa(ha_name, c_vec[n], carry, ha_sum, ha_carry); + if (n + 1 < GetSize(result)) + module->connect(result[n + 1], ha_sum); + if (n + 2 < GetSize(result)) + module->connect(result[n + 2], ha_carry); + } + } + // Step case + else { + SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1); + module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)), + /* A */ s_vec[n], + /* B */ c_vec[n - 1], + /* C */ carry, + /* X */ carry_out, + /* Y */ result[n] + ); + carry = carry_out; +#ifdef DEBUG_CPA + printf("CPA bit [%d] Cell %s IPs [%s] [%s] [%s]\n", n, fa_cell->name.c_str(), s_vec[n]->name.c_str(), + c_vec[n - 1]->name.c_str(), carry->name.c_str()); +#endif + } + } + } + + // Sum the bits in the current column + // Pass the carry bits from each csa to the next + // column for summation. + + void ReduceBits(RTLIL::Module *module, int column_ix, SigSpec column_bits, SigBit &s_result, SigBit &c_result, + SigSpec &carry_bits_to_sum, std::vector> &debug_csa_trees) + { + + int csa_ix = 0; + int column_size = column_bits.size(); + + if (column_size > 0) { + int var_ix = 0; + SigSpec first_csa_ips; + // get the first 3 inputs, if possible + for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) { + if (column_bits[var_ix] != State::S0) + first_csa_ips.append(column_bits[var_ix]); + } + + if (first_csa_ips.size() > 0) { + // build the first csa + auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + + auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + /* A */ first_csa_ips[0], + /* B */ first_csa_ips.size() > 1 ? first_csa_ips[1] : State::S0, + /* C */ first_csa_ips.size() > 2 ? first_csa_ips[2] : State::S0, + /* X */ c_wire, + /* Y */ s_wire + ); + + s_result = s_wire; + c_result = c_wire; + + debug_csa_trees[column_ix].push_back(csa); + csa_ix++; + + if (var_ix <= column_bits.size() - 1) + carry_bits_to_sum.append(c_wire); + + // Now build the rest of the tree if we can + while (var_ix <= column_bits.size() - 1) { + SigSpec csa_ips; + // get the next two variables to sum + for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) { + // skip any empty bits + if (column_bits[var_ix] != State::S0) + csa_ips.append(column_bits[var_ix]); + var_ix++; + } + + if (csa_ips.size() > 0) { + auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1); + auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1); + + auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)), + /* A */ s_result, + /* B */ csa_ips[0], + /* C */ csa_ips.size() > 1 ? csa_ips[1] : State::S0, + /* X */ c_wire, + /* Y */ s_wire + ); + + debug_csa_trees[column_ix].push_back(csa); + csa_ix++; + + if (var_ix <= column_bits.size() - 1) + carry_bits_to_sum.append(c_wire); + + s_result = s_wire; + c_result = c_wire; + } + } + } + } + } + + void BuildBoothMultEncoders(SigSpec Y, SigSpec &one_int, SigSpec &two_int, + SigSpec &s_int, SigSpec &sb_int, RTLIL::Module *module, int &encoder_ix, bool is_signed) + { + int y_sz = GetSize(Y); + + for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) { + std::string enc_name = stringf("bur_enc_%d", encoder_ix); + + two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + + if (y_ix == 0) { + BuildBur4e(enc_name, State::S0, Y[y_ix], + Y[y_ix + 1], one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + sb_int[encoder_ix]); + + y_ix = y_ix + 1; + encoder_ix++; + } else { + // + // step case. If multiplier ends on a boundary + // then add an extra booth encoder bounded by + // zeroes to ensure unsigned works. + // + SigBit y0, y1, y2; + + bool need_padded_cell = false; + + if (y_ix > y_sz - 1) { + y0 = is_signed ? Y.msb() : State::S0; + need_padded_cell = false; + } else { + y0 = Y[y_ix]; + y_ix++; + } + + if (y_ix > y_sz - 1) { + need_padded_cell = false; + y1 = is_signed ? Y.msb() : State::S0; + } else { + y1 = Y[y_ix]; + y_ix++; + } + + if (y_ix > y_sz - 1) { + need_padded_cell = false; + y2 = is_signed ? Y.msb() : State::S0; + } else { + if (y_ix == y_sz - 1) + need_padded_cell = !is_signed; + else + need_padded_cell = false; + y2 = Y[y_ix]; + + BuildBur4e(enc_name, y0, y1, y2, one_int[encoder_ix], two_int[encoder_ix], s_int[encoder_ix], + sb_int[encoder_ix]); + } + + encoder_ix++; + + if (need_padded_cell == true) { + // make extra encoder cell + // y_ix at y0, rest 0 + + std::string enc_name = stringf("br_enc_pad_%d", encoder_ix); + + two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1)); + one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1)); + s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1)); + sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1)); + + SigBit one_o_int, two_o_int, s_o_int, sb_o_int; + BuildBur4e(enc_name, Y[y_ix], State::S0, + State::S0, one_o_int, two_o_int, s_o_int, sb_o_int); + + module->connect(one_int[encoder_ix], one_o_int); + module->connect(two_int[encoder_ix], two_o_int); + module->connect(s_int[encoder_ix], s_o_int); + module->connect(sb_int[encoder_ix], sb_o_int); + y_ix++; + encoder_ix++; + } + } + } + } + + /* + Low-power Multiplier + */ + void CreateBoothLowpowerMult(RTLIL::Module *module, SigSpec X, SigSpec Y, SigSpec Z, bool is_signed) + { // product + int x_sz = X.size(), y_sz = Y.size(), z_sz = Z.size(); + + if (!is_signed) + log_error("Low-power Booth architecture is only supported on signed multipliers.\n"); + + unsigned enc_count = (y_sz / 2) + (((y_sz % 2) != 0) ? 1 : 0); + int dec_count = x_sz + 1; + + int fa_count = x_sz + 4; + int fa_row_count = enc_count - 1; + + log_debug("Mapping %d x %d -> %d multiplier: %d encoders %d decoders\n", x_sz, y_sz, z_sz, enc_count, dec_count); + + SigSpec negi_n_int, twoi_n_int, onei_n_int, cori_n_int; + + negi_n_int.extend_u0(enc_count); + twoi_n_int.extend_u0(enc_count); + onei_n_int.extend_u0(enc_count); + cori_n_int.extend_u0(enc_count); + + for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) { + std::string enc_name = stringf("enc_%d", encoder_ix); + negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1); + twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1); + onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1); + cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1); + + if (encoder_ix == 1) { + BuildBr4e(enc_name, State::S0, Y[0], Y[1], + negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + cori_n_int[encoder_ix - 1]); + + } else { + SigBit y1, y2, y3; + + y1 = Y[(encoder_ix - 1) * 2 - 1]; + + if ((encoder_ix - 1) * 2 >= (unsigned)y_sz) + y2 = State::S0; // constant 0 + else + y2 = Y[(encoder_ix - 1) * 2]; // 0 + + if (((encoder_ix - 1) * 2 + 1) >= (unsigned)y_sz) + y3 = State::S0; // constant 0 + else + y3 = Y[(encoder_ix - 1) * 2 + 1]; //+1 + + BuildBr4e(enc_name, y1, y2, y3, + negi_n_int[encoder_ix - 1], twoi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + cori_n_int[encoder_ix - 1]); + } + } + + // Decoders and PP generation + SigSpec PPij(State::S0, enc_count * dec_count); + SigSpec nxj(State::S0, enc_count * dec_count); + + for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { + for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) { + PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = + module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1); + + nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] = + module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "", + encoder_ix, decoder_ix)), 1); + } + } + + // + // build decoder array + // + for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) { + // pre-decoder + std::string pre_dec_name = "pre_dec_" + std::to_string(encoder_ix) + "_"; + + if (encoder_ix == 1) { + // quadrant 1 optimization + } else { + module->addNotGate(NEW_ID_SUFFIX(stringf("pre_dec_%d", encoder_ix)), + negi_n_int[encoder_ix - 1], + nxj[(encoder_ix - 1) * dec_count] + ); + } + + for (int decoder_ix = 1; decoder_ix < dec_count; decoder_ix++) { + // range 1..8 + + // quadrant 1 optimization. + if ((decoder_ix == 1 || decoder_ix == 2) && encoder_ix == 1) + continue; + + std::string dec_name = stringf("dec_%d_%d", encoder_ix, decoder_ix); + BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1], twoi_n_int[encoder_ix - 1], + X[decoder_ix - 1], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1], nxj[((encoder_ix - 1) * dec_count) + decoder_ix]); + } + + // duplicate end for sign fix + // applies to 9th decoder (xsz+1 decoder). + std::string dec_name = stringf("dec_%d_%d", encoder_ix, x_sz + 1); + SigBit unused_op; + BuildBr4d(dec_name, nxj[((encoder_ix - 1) * dec_count) + dec_count - 1], twoi_n_int[encoder_ix - 1], + X[dec_count - 2], negi_n_int[encoder_ix - 1], onei_n_int[encoder_ix - 1], + PPij[((encoder_ix - 1) * dec_count) + dec_count - 1], unused_op); + } + + // + // instantiate the quadrant 1 cell. This is the upper right + // quadrant which can be realized using non-booth encoded logic. + // + SigBit pp0_o_int, pp1_o_int, nxj_o_int, q1_carry_out; + + BuildBoothQ1("icb_booth_q1_", + negi_n_int[0], // negi + cori_n_int[0], // cori + X[0], X[1], Y[0], Y[1], + nxj_o_int, q1_carry_out, pp0_o_int, pp1_o_int); + + module->connect(Z[0], pp0_o_int); + module->connect(Z[1], pp1_o_int); + module->connect(nxj[(0 * dec_count) + 2], nxj_o_int); + + // + // sum up the partial products + // + int fa_row_ix = 0; + std::vector fa_sum; + std::vector fa_carry; + + for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) { + fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count)); + fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count)); + } + + // full adder creation + // base case: 1st row: Inputs from decoders + // 1st row exception: two localized inverters due to sign extension structure + SigBit d08_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv1"), PPij[(0 * dec_count) + dec_count - 1]); + SigBit d18_inv = module->NotGate(NEW_ID_SUFFIX("bfa_0_exc_inv2"), PPij[(1 * dec_count) + dec_count - 1]); + BuildBitwiseFa(module, NEW_ID_SUFFIX("fa_row_0").str(), + /* A */ {State::S0, d08_inv, PPij[(0 * dec_count) + x_sz], PPij.extract((0 * dec_count) + 2, x_sz - 1)}, + /* B */ {State::S1, d18_inv, PPij.extract((1 * dec_count), x_sz)}, + /* C */ fa_carry[0].extract(1, x_sz + 2), + /* X */ fa_carry[0].extract(2, x_sz + 2), + /* Y */ fa_sum[0].extract(2, x_sz + 2) + ); + module->connect(fa_carry[0][1], q1_carry_out); + + // step case: 2nd and rest of rows. (fa_row_ix == 1...n) + // special because these are driven by a decoder and prior fa. + for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) { + // end two bits: sign extension + SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)), + PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]); + + BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(), + /* A */ {State::S0, fa_carry[fa_row_ix - 1][fa_count - 1], fa_sum[fa_row_ix - 1].extract(2, x_sz + 2)}, + /* B */ {State::S1, d_inv, PPij.extract((fa_row_ix + 1) * dec_count, x_sz), State::S0, State::S0}, + + /* C */ {fa_carry[fa_row_ix].extract(0, x_sz + 3), cori_n_int[fa_row_ix]}, + /* X */ fa_carry[fa_row_ix], + /* Y */ fa_sum[fa_row_ix] + ); + } + + // instantiate the cpa + SigSpec cpa_carry; + if (z_sz > fa_row_count * 2) + cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2); + + // The end case where we pass the last two summands + // from prior row directly to product output + // without using a cpa cell. This is always + // 0,1 index of prior fa row + for (int cpa_ix = 0; cpa_ix < fa_row_count * 2; cpa_ix += 2) { + int fa_row_ix = cpa_ix / 2; + module->connect(Z.extract(cpa_ix, 2), fa_sum[fa_row_ix].extract(0, 2)); + } + + for (int cpa_ix = fa_row_count * 2; cpa_ix < z_sz; cpa_ix++) { + int offset = fa_row_count * 2; + std::string cpa_name = stringf("cpa_%d", cpa_ix - offset); + + SigBit ci = (cpa_ix == offset) ? cori_n_int[enc_count - 1] : cpa_carry[cpa_ix - offset - 1]; + SigBit op; + BuildHa(cpa_name, fa_sum[fa_row_count - 1][cpa_ix - offset + 2], ci, op, cpa_carry[cpa_ix - offset]); + module->connect(Z[cpa_ix], op); + } + } +}; + +struct BoothPass : public Pass { + BoothPass() : Pass("booth", "map $mul cells to Booth multipliers") {} + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" booth [selection]\n"); + log("\n"); + log("This pass replaces multiplier cells with a radix-4 Booth-encoded implementation.\n"); + log("It operates on $mul cells whose width of operands is at least 4x4 and whose\n"); + log("width of result is at least 8.\n"); + log("\n"); + log(" -lowpower\n"); + log(" use an alternative low-power architecture for the generated multiplier\n"); + log(" (signed multipliers only)\n"); + log("\n"); + } + void execute(vector args, RTLIL::Design *design) override + { + log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n"); + + size_t argidx; + bool mapped_cpa = false; + bool lowpower = false; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-mapped_cpa") + // Have an undocumented option which helps with multiplier + // verification using specialized tools (AMulet2 in particular) + mapped_cpa = true; + else if (args[argidx] == "-lowpower") + lowpower = true; + else + break; + } + extra_args(args, argidx, design); + + int total = 0; + + for (auto mod : design->selected_modules()) { + if (!mod->has_processes_warn()) { + BoothPassWorker worker(mod); + worker.mapped_cpa = mapped_cpa; + worker.lowpower = lowpower; + worker.run(); + total += worker.booth_counter; + } + } + + log("Mapped %d multipliers.\n", total); + } +} MultPass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/passes/techmap/extract_fa.cc b/yosys/passes/techmap/extract_fa.cc index 117fdd54cf6..ec1979f3b6d 100644 --- a/yosys/passes/techmap/extract_fa.cc +++ b/yosys/passes/techmap/extract_fa.cc @@ -281,7 +281,7 @@ struct ExtractFaWorker void assign_new_driver(SigBit bit, SigBit new_driver) { Cell *cell = driver.at(bit); - if (sigmap(cell->getPort(ID::Y)) == bit) { + if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) { cell->setPort(ID::Y, module->addWire(NEW_ID)); module->connect(bit, new_driver); } diff --git a/yosys/passes/techmap/flatten.cc b/yosys/passes/techmap/flatten.cc index 7e6df5d2c1f..4ddc4aff1fa 100644 --- a/yosys/passes/techmap/flatten.cc +++ b/yosys/passes/techmap/flatten.cc @@ -312,7 +312,7 @@ struct FlattenPass : public Pass { for (auto cell : module->selected_cells()) { RTLIL::Module *tpl = design->module(cell->type); if (tpl != nullptr) { - if (topo_modules.database.count(tpl) == 0) + if (!topo_modules.has_node(tpl)) worklist.insert(tpl); topo_modules.edge(tpl, module); } diff --git a/yosys/passes/techmap/simplemap.cc b/yosys/passes/techmap/simplemap.cc index 11692b715ea..7461460fed8 100644 --- a/yosys/passes/techmap/simplemap.cc +++ b/yosys/passes/techmap/simplemap.cc @@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -73,7 +73,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -124,7 +124,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -137,7 +137,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -165,7 +165,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -194,7 +194,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -223,7 +223,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -239,20 +239,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + xor_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); - simplemap_lognot(module, not_cell); + not_cell->attributes[ID::src] = cell->attributes[ID::src]; + simplemap_lognot(module, not_cell); module->remove(not_cell); } } @@ -265,7 +265,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, cell->getPort(ID::S)); @@ -282,7 +282,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, sig_s[i]); @@ -298,7 +298,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); @@ -316,7 +316,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); gate->setPort(ID::S, sel[idx]); @@ -339,7 +339,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + gate->attributes[ID::src] = cell->attributes[ID::src]; gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); gate->setPort(ID::S, lut_ctrl[idx]); diff --git a/yosys/techlibs/achronix/synth_achronix.cc b/yosys/techlibs/achronix/synth_achronix.cc index 9a0a7a3b57b..2b969182eaf 100644 --- a/yosys/techlibs/achronix/synth_achronix.cc +++ b/yosys/techlibs/achronix/synth_achronix.cc @@ -26,7 +26,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthAchronixPass : public ScriptPass { - SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { } + SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Achronix Speedster22i FPGAs.") { } void help() override { diff --git a/yosys/techlibs/common/Makefile.inc b/yosys/techlibs/common/Makefile.inc index 47f1ed60456..6b377855e3e 100644 --- a/yosys/techlibs/common/Makefile.inc +++ b/yosys/techlibs/common/Makefile.inc @@ -34,3 +34,4 @@ $(eval $(call add_share_file,share,techlibs/common/abc9_model.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_map.v)) $(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v)) $(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v)) +$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v)) diff --git a/yosys/techlibs/common/cmp2softlogic.v b/yosys/techlibs/common/cmp2softlogic.v new file mode 100644 index 00000000000..e480b4eee99 --- /dev/null +++ b/yosys/techlibs/common/cmp2softlogic.v @@ -0,0 +1,117 @@ +module constgtge(C, A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +output Y; +input C; + +wire [A_WIDTH:0] ch; +genvar n; +generate + if (B_WIDTH > A_WIDTH) begin + // Fail + end else begin + assign ch[0] = C; + for (n = 0; n < A_WIDTH; n = n + 1) begin + if (n < B_WIDTH) begin + assign ch[n + 1] = B[n] ? (ch[n] && A[n]) : (ch[n] || A[n]); + end else begin + assign ch[n + 1] = ch[n] || A[n]; + end + end + assign Y = ch[A_WIDTH]; + end +endgenerate +endmodule + +module constltle(C, A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +output Y; +input C; + +wire [A_WIDTH:0] ch; +genvar n; +generate + if (B_WIDTH > A_WIDTH) begin + // Fail + end else begin + assign ch[0] = C; + for (n = 0; n < A_WIDTH; n = n + 1) begin + if (n < B_WIDTH) begin + assign ch[n + 1] = !B[n] ? (ch[n] && !A[n]) : (ch[n] || !A[n]); + end else begin + assign ch[n + 1] = ch[n] && !A[n]; + end + end + assign Y = ch[A_WIDTH]; + end +endgenerate +endmodule + +(* techmap_celltype = "$ge $gt $le $lt" *) +module _map_const_cmp_(A, B, Y); +parameter A_WIDTH = 0; +parameter B_WIDTH = 0; +parameter Y_WIDTH = 0; +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +(* force_downto *) +output [Y_WIDTH-1:0] Y; + +parameter _TECHMAP_CELLTYPE_ = ""; + +parameter _TECHMAP_CONSTMSK_A_ = 0; +parameter _TECHMAP_CONSTVAL_A_ = 0; +parameter _TECHMAP_CONSTMSK_B_ = 0; +parameter _TECHMAP_CONSTVAL_B_ = 0; + +wire [1023:0] _TECHMAP_DO_ = "opt -fast;"; + +wire [A_WIDTH:0] ch; + +genvar n; +generate + if (Y_WIDTH != 1 || A_SIGNED || B_SIGNED) + wire _TECHMAP_FAIL_ = 1; + else if (&_TECHMAP_CONSTMSK_A_) begin + if (A_WIDTH > B_WIDTH) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le") + constgtge #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH)) + _TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$lt")); + else + constltle #(.A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH)) + _TECHMAP_REPLACE_(.A(B), .B(A), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$gt")); + end else if (&_TECHMAP_CONSTMSK_B_) begin + if (B_WIDTH > A_WIDTH) + wire _TECHMAP_FAIL_ = 1; + else if (_TECHMAP_CELLTYPE_ == "$lt" || _TECHMAP_CELLTYPE_ == "$le") + constltle #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH)) + _TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$le")); + else + constgtge #(.A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH)) + _TECHMAP_REPLACE_(.A(A), .B(B), .Y(Y), + .C(_TECHMAP_CELLTYPE_ == "$ge")); + end else + wire _TECHMAP_FAIL_ = 1; +endgenerate + +endmodule diff --git a/yosys/techlibs/common/prep.cc b/yosys/techlibs/common/prep.cc index c354956bcf4..e9176304d48 100644 --- a/yosys/techlibs/common/prep.cc +++ b/yosys/techlibs/common/prep.cc @@ -189,6 +189,7 @@ struct PrepPass : public ScriptPass run(ifxmode ? "proc -ifx" : "proc"); if (help_mode || flatten) run("flatten", "(if -flatten)"); + run("future"); run(nokeepdc ? "opt_expr" : "opt_expr -keepdc"); run("opt_clean"); run("check"); diff --git a/yosys/techlibs/common/simlib.v b/yosys/techlibs/common/simlib.v index 9cb68e7252f..930d2000b4d 100644 --- a/yosys/techlibs/common/simlib.v +++ b/yosys/techlibs/common/simlib.v @@ -1799,6 +1799,46 @@ end endmodule +// -------------------------------------------------------- + +module \$print (EN, TRG, ARGS); + +parameter PRIORITY = 0; + +parameter FORMAT = ""; +parameter ARGS_WIDTH = 0; + +parameter TRG_ENABLE = 1; +parameter TRG_WIDTH = 0; +parameter TRG_POLARITY = 0; + +input EN; +input [TRG_WIDTH-1:0] TRG; +input [ARGS_WIDTH-1:0] ARGS; + +endmodule + +// -------------------------------------------------------- + +module \$check (A, EN, TRG, ARGS); + +parameter FLAVOR = ""; +parameter PRIORITY = 0; + +parameter FORMAT = ""; +parameter ARGS_WIDTH = 0; + +parameter TRG_ENABLE = 1; +parameter TRG_WIDTH = 0; +parameter TRG_POLARITY = 0; + +input A; +input EN; +input [TRG_WIDTH-1:0] TRG; +input [ARGS_WIDTH-1:0] ARGS; + +endmodule + // -------------------------------------------------------- `ifndef SIMLIB_NOSR @@ -2653,3 +2693,73 @@ endmodule `endif // -------------------------------------------------------- + +module \$set_tag (A, SET, CLR, Y); + +parameter TAG = ""; +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +input [WIDTH-1:0] SET; +input [WIDTH-1:0] CLR; +output [WIDTH-1:0] Y; + +assign Y = A; + +endmodule + +// -------------------------------------------------------- + +module \$get_tag (A, Y); + +parameter TAG = ""; +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +output [WIDTH-1:0] Y; + +assign Y = A; + +endmodule + +// -------------------------------------------------------- + +module \$overwrite_tag (A, SET, CLR); + +parameter TAG = ""; +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +input [WIDTH-1:0] SET; +input [WIDTH-1:0] CLR; + +endmodule + +// -------------------------------------------------------- + +module \$original_tag (A, Y); + +parameter TAG = ""; +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +output [WIDTH-1:0] Y; + +assign Y = A; + +endmodule + +// -------------------------------------------------------- + +module \$future_ff (A, Y); + +parameter WIDTH = 0; + +input [WIDTH-1:0] A; +output [WIDTH-1:0] Y; + +assign Y = A; + +endmodule + +// -------------------------------------------------------- diff --git a/yosys/techlibs/common/synth.cc b/yosys/techlibs/common/synth.cc index 63395c36802..e5013678aa4 100644 --- a/yosys/techlibs/common/synth.cc +++ b/yosys/techlibs/common/synth.cc @@ -17,17 +17,16 @@ * */ -#include "kernel/register.h" #include "kernel/celltypes.h" -#include "kernel/rtlil.h" #include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SynthPass : public ScriptPass -{ - SynthPass() : ScriptPass("synth", "generic synthesis script") { } +struct SynthPass : public ScriptPass { + SynthPass() : ScriptPass("synth", "generic synthesis script") {} void help() override { @@ -60,6 +59,9 @@ struct SynthPass : public ScriptPass log(" -noabc\n"); log(" do not run abc (as if yosys was compiled without ABC support)\n"); log("\n"); + log(" -booth\n"); + log(" run the booth pass to map $mul to Booth encoded multipliers\n"); + log("\n"); log(" -noalumacc\n"); log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n"); log(" their direct form ($add, $sub, etc.).\n"); @@ -93,7 +95,8 @@ struct SynthPass : public ScriptPass } string top_module, fsm_opts, memory_opts, abc; - bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap; + bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth; + int lut; void clear_flags() override @@ -110,6 +113,7 @@ struct SynthPass : public ScriptPass noabc = false; noshare = false; flowmap = false; + booth = false; abc = "abc"; } @@ -119,24 +123,23 @@ struct SynthPass : public ScriptPass clear_flags(); size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-top" && argidx + 1 < args.size()) { top_module = args[++argidx]; continue; } - if (args[argidx] == "-encfile" && argidx+1 < args.size()) { + if (args[argidx] == "-encfile" && argidx + 1 < args.size()) { fsm_opts = " -encfile " + args[++argidx]; continue; } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) { run_from = args[++argidx]; run_to = args[argidx]; } else { run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); + run_to = args[argidx].substr(pos + 1); } continue; } @@ -164,6 +167,11 @@ struct SynthPass : public ScriptPass noalumacc = true; continue; } + if (args[argidx] == "-booth") { + booth = true; + continue; + } + if (args[argidx] == "-nordff") { memory_opts += " -nordff"; continue; @@ -206,8 +214,7 @@ struct SynthPass : public ScriptPass void script() override { - if (check_label("begin")) - { + if (check_label("begin")) { if (help_mode) { run("hierarchy -check [-top | -auto-top]"); } else { @@ -221,16 +228,15 @@ struct SynthPass : public ScriptPass } } - if (check_label("coarse")) - { + if (check_label("coarse")) { run("proc"); - if (help_mode || flatten) + if (flatten || help_mode) run("flatten", " (if -flatten)"); run("opt_expr"); run("opt_clean"); run("check"); run("opt -nodffe -nosdff"); - if (!nofsm) + if (!nofsm || help_mode) run("fsm" + fsm_opts, " (unless -nofsm)"); run("opt"); run("wreduce"); @@ -240,6 +246,8 @@ struct SynthPass : public ScriptPass run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + if (booth || help_mode) + run("booth", " (if -booth)"); if (!noalumacc) run("alumacc", " (unless -noalumacc)"); if (!noshare) @@ -249,50 +257,40 @@ struct SynthPass : public ScriptPass run("opt_clean"); } - if (check_label("fine")) - { + if (check_label("fine")) { run("opt -fast -full"); run("memory_map"); run("opt -full"); run("techmap"); - if (help_mode) - { + if (help_mode) { run("techmap -map +/gate2lut.v", "(if -noabc and -lut)"); run("clean; opt_lut", " (if -noabc and -lut)"); run("flowmap -maxlut K", " (if -flowmap and -lut)"); - } - else if (noabc && lut) - { + } else if (noabc && lut) { run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut)); run("clean; opt_lut"); - } - else if (flowmap) - { + } else if (flowmap) { run(stringf("flowmap -maxlut %d", lut)); } run("opt -fast"); - if (!noabc && !flowmap) { - #ifdef YOSYS_ENABLE_ABC - if (help_mode) - { + if ((!noabc && !flowmap) || help_mode) { +#ifdef YOSYS_ENABLE_ABC + if (help_mode) { run(abc + " -fast", " (unless -noabc, unless -lut)"); run(abc + " -fast -lut k", "(unless -noabc, if -lut)"); - } - else - { + } else { if (lut) run(stringf("%s -fast -lut %d", abc.c_str(), lut)); else run(abc + " -fast"); } run("opt -fast", " (unless -noabc)"); - #endif +#endif } } - if (check_label("check")) - { + if (check_label("check")) { run("hierarchy -check"); run("stat"); run("check"); diff --git a/yosys/techlibs/ecp5/Makefile.inc b/yosys/techlibs/ecp5/Makefile.inc index f9fa79ab9ad..a1c9bfc5233 100644 --- a/yosys/techlibs/ecp5/Makefile.inc +++ b/yosys/techlibs/ecp5/Makefile.inc @@ -1,5 +1,5 @@ -OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o +OBJS += techlibs/ecp5/synth_ecp5.o $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh)) diff --git a/yosys/techlibs/ecp5/synth_ecp5.cc b/yosys/techlibs/ecp5/synth_ecp5.cc index 82e23486844..f6215987f7f 100644 --- a/yosys/techlibs/ecp5/synth_ecp5.cc +++ b/yosys/techlibs/ecp5/synth_ecp5.cc @@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); @@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass retime = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; iopad = false; nodsp = false; no_rw_check = false; @@ -224,7 +224,11 @@ struct SynthEcp5Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-iopad") { @@ -359,7 +363,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -D NO_LUT -map +/ecp5/cells_map.v"); run("opt_expr -undriven -mux_undef"); run("simplemap"); - run("ecp5_gsr"); + run("lattice_gsr"); run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } @@ -404,7 +408,7 @@ struct SynthEcp5Pass : public ScriptPass run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)"); else if (!vpr) run("techmap -map +/ecp5/cells_map.v"); - run("opt_lut_ins -tech ecp5"); + run("opt_lut_ins -tech lattice"); run("clean"); } diff --git a/yosys/techlibs/gowin/brams.txt b/yosys/techlibs/gowin/brams.txt index 0c0d8fa3e3e..435d3b5cf57 100644 --- a/yosys/techlibs/gowin/brams.txt +++ b/yosys/techlibs/gowin/brams.txt @@ -1,13 +1,11 @@ ram block $__GOWIN_SP_ { abits 14; widths 1 2 4 9 18 36 per_port; - byte 9; cost 128; init no_undef; port srsw "A" { clock posedge; clken; - wrbe_separate; option "RESET_MODE" "SYNC" { rdsrst zero ungated; } @@ -30,13 +28,11 @@ ram block $__GOWIN_SP_ { ram block $__GOWIN_DP_ { abits 14; widths 1 2 4 9 18 per_port; - byte 9; cost 128; init no_undef; port srsw "A" "B" { clock posedge; clken; - wrbe_separate; option "RESET_MODE" "SYNC" { rdsrst zero ungated; } @@ -59,7 +55,6 @@ ram block $__GOWIN_DP_ { ram block $__GOWIN_SDP_ { abits 14; widths 1 2 4 9 18 36 per_port; - byte 9; cost 128; init no_undef; port sr "R" { @@ -76,6 +71,5 @@ ram block $__GOWIN_SDP_ { port sw "W" { clock posedge; clken; - wrbe_separate; } } diff --git a/yosys/techlibs/gowin/brams_map.v b/yosys/techlibs/gowin/brams_map.v index 7ffc91bacc1..8e6cc61402d 100644 --- a/yosys/techlibs/gowin/brams_map.v +++ b/yosys/techlibs/gowin/brams_map.v @@ -14,8 +14,7 @@ `define x8_width(width) (width / 9 * 8 + width % 9) `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]} `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]} -`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en) -`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be}) +`define addrbe_always(width, addr) (width < 18 ? addr : width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111}) `define INIT(func) \ @@ -90,7 +89,6 @@ parameter INIT = 0; parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 36; -parameter PORT_A_WR_BE_WIDTH = 4; parameter PORT_A_OPTION_WRITE_MODE = 0; input PORT_A_CLK; @@ -99,15 +97,13 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; -input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; -wire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE); -wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); +wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); generate @@ -129,9 +125,9 @@ if (PORT_A_WIDTH < 9) begin .BLKSEL(3'b000), .CLK(PORT_A_CLK), .CE(PORT_A_CLK_EN), - .WRE(WRE), + .WRE(PORT_A_WR_EN), .RESET(RST), - .OCE(1'b0), + .OCE(1'b1), .AD(AD), .DI(DI), .DO(DO), @@ -155,9 +151,9 @@ end else begin .BLKSEL(3'b000), .CLK(PORT_A_CLK), .CE(PORT_A_CLK_EN), - .WRE(WRE), + .WRE(PORT_A_WR_EN), .RESET(RST), - .OCE(1'b0), + .OCE(1'b1), .AD(AD), .DI(DI), .DO(DO), @@ -176,11 +172,9 @@ parameter INIT = 0; parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_A_WIDTH = 18; -parameter PORT_A_WR_BE_WIDTH = 2; parameter PORT_A_OPTION_WRITE_MODE = 0; parameter PORT_B_WIDTH = 18; -parameter PORT_B_WR_BE_WIDTH = 2; parameter PORT_B_OPTION_WRITE_MODE = 0; input PORT_A_CLK; @@ -189,7 +183,6 @@ input PORT_A_WR_EN; input PORT_A_RD_SRST; input PORT_A_RD_ARST; input [13:0] PORT_A_ADDR; -input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; @@ -199,7 +192,6 @@ input PORT_B_WR_EN; input PORT_B_RD_SRST; input PORT_B_RD_ARST; input [13:0] PORT_B_ADDR; -input [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE; input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA; output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; @@ -207,10 +199,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA; wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST; wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST; -wire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE); -wire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE); -wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE); -wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE); +wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR); +wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR); generate @@ -224,7 +214,7 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin assign PORT_A_RD_DATA = `x8_rd_data(DOA); assign PORT_B_RD_DATA = `x8_rd_data(DOB); - DP #( + DPB #( `INIT(init_slice_x8) .READ_MODE0(1'b0), .READ_MODE1(1'b0), @@ -232,25 +222,27 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin .WRITE_MODE1(PORT_B_OPTION_WRITE_MODE), .BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)), .BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)), - .BLK_SEL(3'b000), + .BLK_SEL_0(3'b000), + .BLK_SEL_1(3'b000), .RESET_MODE(OPTION_RESET_MODE), ) _TECHMAP_REPLACE_ ( - .BLKSEL(3'b000), + .BLKSELA(3'b000), + .BLKSELB(3'b000), .CLKA(PORT_A_CLK), .CEA(PORT_A_CLK_EN), - .WREA(WREA), + .WREA(PORT_A_WR_EN), .RESETA(RSTA), - .OCEA(1'b0), + .OCEA(1'b1), .ADA(ADA), .DIA(DIA), .DOA(DOA), .CLKB(PORT_B_CLK), .CEB(PORT_B_CLK_EN), - .WREB(WREB), + .WREB(PORT_B_WR_EN), .RESETB(RSTB), - .OCEB(1'b0), + .OCEB(1'b1), .ADB(ADB), .DIB(DIB), .DOB(DOB), @@ -266,7 +258,7 @@ end else begin assign PORT_A_RD_DATA = DOA; assign PORT_B_RD_DATA = DOB; - DPX9 #( + DPX9B #( `INIT(init_slice_x9) .READ_MODE0(1'b0), .READ_MODE1(1'b0), @@ -274,25 +266,27 @@ end else begin .WRITE_MODE1(PORT_B_OPTION_WRITE_MODE), .BIT_WIDTH_0(PORT_A_WIDTH), .BIT_WIDTH_1(PORT_B_WIDTH), - .BLK_SEL(3'b000), + .BLK_SEL_0(3'b000), + .BLK_SEL_1(3'b000), .RESET_MODE(OPTION_RESET_MODE), ) _TECHMAP_REPLACE_ ( - .BLKSEL(3'b000), + .BLKSELA(3'b000), + .BLKSELB(3'b000), .CLKA(PORT_A_CLK), .CEA(PORT_A_CLK_EN), - .WREA(WREA), + .WREA(PORT_A_WR_EN), .RESETA(RSTA), - .OCEA(1'b0), + .OCEA(1'b1), .ADA(ADA), .DIA(DIA), .DOA(DOA), .CLKB(PORT_B_CLK), .CEB(PORT_B_CLK_EN), - .WREB(WREB), + .WREB(PORT_B_WR_EN), .RESETB(RSTB), - .OCEB(1'b0), + .OCEB(1'b1), .ADB(ADB), .DIB(DIB), .DOB(DOB), @@ -311,9 +305,7 @@ parameter INIT = 0; parameter OPTION_RESET_MODE = "SYNC"; parameter PORT_R_WIDTH = 18; - parameter PORT_W_WIDTH = 18; -parameter PORT_W_WR_BE_WIDTH = 2; input PORT_R_CLK; input PORT_R_CLK_EN; @@ -326,14 +318,13 @@ input PORT_W_CLK; input PORT_W_CLK_EN; input PORT_W_WR_EN; input [13:0] PORT_W_ADDR; -input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; `DEF_FUNCS wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; -wire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE); -wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE); +wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); +wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN; generate @@ -344,28 +335,28 @@ if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin assign PORT_R_RD_DATA = `x8_rd_data(DO); - SDP #( + SDPB #( `INIT(init_slice_x8) .READ_MODE(1'b0), .BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)), .BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)), - .BLK_SEL(3'b000), + .BLK_SEL_0(3'b000), + .BLK_SEL_1(3'b000), .RESET_MODE(OPTION_RESET_MODE), ) _TECHMAP_REPLACE_ ( - .BLKSEL(3'b000), + .BLKSELA(3'b000), + .BLKSELB(3'b000), .CLKA(PORT_W_CLK), - .CEA(PORT_W_CLK_EN), - .WREA(WRE), + .CEA(WRE), .RESETA(1'b0), .ADA(ADW), .DI(DI), .CLKB(PORT_R_CLK), .CEB(PORT_R_CLK_EN), - .WREB(1'b0), .RESETB(RST), - .OCE(1'b0), + .OCE(1'b1), .ADB(PORT_R_ADDR), .DO(DO), ); @@ -377,28 +368,28 @@ end else begin assign PORT_R_RD_DATA = DO; - SDPX9 #( + SDPX9B #( `INIT(init_slice_x9) .READ_MODE(1'b0), .BIT_WIDTH_0(PORT_W_WIDTH), .BIT_WIDTH_1(PORT_R_WIDTH), - .BLK_SEL(3'b000), + .BLK_SEL_0(3'b000), + .BLK_SEL_1(3'b000), .RESET_MODE(OPTION_RESET_MODE), ) _TECHMAP_REPLACE_ ( - .BLKSEL(3'b000), + .BLKSELA(3'b000), + .BLKSELB(3'b000), .CLKA(PORT_W_CLK), - .CEA(PORT_W_CLK_EN), - .WREA(WRE), + .CEA(WRE), .RESETA(1'b0), .ADA(ADW), .DI(DI), .CLKB(PORT_R_CLK), .CEB(PORT_R_CLK_EN), - .WREB(1'b0), .RESETB(RST), - .OCE(1'b0), + .OCE(1'b1), .ADB(PORT_R_ADDR), .DO(DO), ); diff --git a/yosys/techlibs/gowin/cells_sim.v b/yosys/techlibs/gowin/cells_sim.v index 86bd677e229..b268690803f 100644 --- a/yosys/techlibs/gowin/cells_sim.v +++ b/yosys/techlibs/gowin/cells_sim.v @@ -197,7 +197,7 @@ module DFFE (output reg Q, input D, CLK, CE); end endmodule // DFFE (positive clock edge; clock enable) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -216,7 +216,7 @@ module DFFS (output reg Q, input D, CLK, SET); end endmodule // DFFS (positive clock edge; synchronous set) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFSE (output reg Q, input D, CLK, CE, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -282,7 +282,7 @@ module DFFP (output reg Q, input D, CLK, PRESET); specify (posedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, posedge CLK, 576); endspecify @@ -301,7 +301,7 @@ module DFFPE (output reg Q, input D, CLK, CE, PRESET); specify if (CE) (posedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, posedge CLK &&& CE, 576); $setup(CE, posedge CLK, 63); endspecify @@ -321,7 +321,7 @@ module DFFC (output reg Q, input D, CLK, CLEAR); specify (posedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, posedge CLK, 576); endspecify @@ -340,7 +340,7 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR); specify if (CE) (posedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, posedge CLK &&& CE, 576); $setup(CE, posedge CLK, 63); endspecify @@ -384,7 +384,7 @@ module DFFNE (output reg Q, input D, CLK, CE); end endmodule // DFFNE (negative clock edge; clock enable) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFNS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -403,7 +403,7 @@ module DFFNS (output reg Q, input D, CLK, SET); end endmodule // DFFNS (negative clock edge; synchronous set) -(* abc9_box, lib_whitebox *) +(* abc9_flop, lib_whitebox *) module DFFNSE (output reg Q, input D, CLK, CE, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; @@ -469,7 +469,7 @@ module DFFNP (output reg Q, input D, CLK, PRESET); specify (negedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, negedge CLK, 576); endspecify @@ -488,7 +488,7 @@ module DFFNPE (output reg Q, input D, CLK, CE, PRESET); specify if (CE) (negedge CLK => (Q : D)) = (480, 660); - (posedge PRESET => (Q : 1'b1)) = (1800, 2679); + (PRESET => Q) = (1800, 2679); $setup(D, negedge CLK &&& CE, 576); $setup(CE, negedge CLK, 63); endspecify @@ -508,7 +508,7 @@ module DFFNC (output reg Q, input D, CLK, CLEAR); specify (negedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, negedge CLK, 576); endspecify @@ -527,7 +527,7 @@ module DFFNCE (output reg Q, input D, CLK, CE, CLEAR); specify if (CE) (negedge CLK => (Q : D)) = (480, 660); - (posedge CLEAR => (Q : 1'b0)) = (1800, 2679); + (CLEAR => Q) = (1800, 2679); $setup(D, negedge CLK &&& CE, 576); $setup(CE, negedge CLK, 63); endspecify @@ -957,7 +957,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S1 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; @@ -992,7 +992,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S2 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; @@ -1031,7 +1031,7 @@ end endmodule - +(* abc9_flop, lib_whitebox *) module RAM16S4 (DO, DI, AD, WRE, CLK); parameter INIT_0 = 16'h0000; diff --git a/yosys/techlibs/gowin/synth_gowin.cc b/yosys/techlibs/gowin/synth_gowin.cc index 3b9d7424a7b..85022c1cfa2 100644 --- a/yosys/techlibs/gowin/synth_gowin.cc +++ b/yosys/techlibs/gowin/synth_gowin.cc @@ -78,8 +78,8 @@ struct SynthGowinPass : public ScriptPass log(" -noalu\n"); log(" do not use ALU cells\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -no-rw-check\n"); log(" marks all recognized read ports as \"return don't-care value on\n"); @@ -106,7 +106,7 @@ struct SynthGowinPass : public ScriptPass nodffe = false; nolutram = false; nowidelut = false; - abc9 = false; + abc9 = true; noiopads = false; noalu = false; no_rw_check = false; @@ -130,7 +130,6 @@ struct SynthGowinPass : public ScriptPass } if (args[argidx] == "-json" && argidx+1 < args.size()) { json_file = args[++argidx]; - nobram = true; continue; } if (args[argidx] == "-run" && argidx+1 < args.size()) { @@ -170,7 +169,11 @@ struct SynthGowinPass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-noiopads") { diff --git a/yosys/techlibs/ice40/synth_ice40.cc b/yosys/techlibs/ice40/synth_ice40.cc index 2ae859efe32..4c691c7a5aa 100644 --- a/yosys/techlibs/ice40/synth_ice40.cc +++ b/yosys/techlibs/ice40/synth_ice40.cc @@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -noabc9\n"); + log(" disable use of new ABC9 flow\n"); log("\n"); log(" -flowmap\n"); log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n"); @@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass noabc = false; abc2 = false; vpr = false; - abc9 = false; + abc9 = true; flowmap = false; device_opt = "hx"; no_rw_check = false; @@ -235,7 +235,11 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // removed, ABC9 is on by default. + continue; + } + if (args[argidx] == "-noabc9") { + abc9 = false; continue; } if (args[argidx] == "-dff") { @@ -428,7 +432,7 @@ struct SynthIce40Pass : public ScriptPass run("ice40_wrapcarry -unwrap"); run("techmap -map +/ice40/ff_map.v"); run("clean"); - run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -dlogic SB_CARRY:CO=3"); + run("opt_lut -tech ice40"); } if (check_label("map_cells")) diff --git a/yosys/techlibs/ice40/tests/test_bram.sh b/yosys/techlibs/ice40/tests/test_bram.sh index d4d641a9c82..5c30db64411 100644 --- a/yosys/techlibs/ice40/tests/test_bram.sh +++ b/yosys/techlibs/ice40/tests/test_bram.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex diff --git a/yosys/techlibs/ice40/tests/test_dsp_map.sh b/yosys/techlibs/ice40/tests/test_dsp_map.sh index 3f7f134e4c3..8523a4676e4 100644 --- a/yosys/techlibs/ice40/tests/test_dsp_map.sh +++ b/yosys/techlibs/ice40/tests/test_dsp_map.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex for iter in {1..100} diff --git a/yosys/techlibs/ice40/tests/test_dsp_model.sh b/yosys/techlibs/ice40/tests/test_dsp_model.sh index 1e564d1b297..c79456f7086 100644 --- a/yosys/techlibs/ice40/tests/test_dsp_model.sh +++ b/yosys/techlibs/ice40/tests/test_dsp_model.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v if [ ! -f "test_dsp_model_ref.v" ]; then diff --git a/yosys/techlibs/ice40/tests/test_ffs.sh b/yosys/techlibs/ice40/tests/test_ffs.sh index ff79ec534b7..438629c3e1b 100644 --- a/yosys/techlibs/ice40/tests/test_ffs.sh +++ b/yosys/techlibs/ice40/tests/test_ffs.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex for CLKPOL in 0 1; do for ENABLE_EN in 0 1; do diff --git a/yosys/techlibs/lattice/Makefile.inc b/yosys/techlibs/lattice/Makefile.inc new file mode 100644 index 00000000000..fd9ec2ed5e0 --- /dev/null +++ b/yosys/techlibs/lattice/Makefile.inc @@ -0,0 +1,28 @@ + +OBJS += techlibs/lattice/synth_lattice.o +OBJS += techlibs/lattice/lattice_gsr.o + +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_ff.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_io.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/common_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2d_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/ccu2c_sim.vh)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_ecp5.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo2.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_sim_xo3d.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_ecp5.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo2.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/cells_bb_xo3d.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/lutrams.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_16kd.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_16kd.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_map_8kc.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/brams_8kc.txt)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2c.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/arith_map_ccu2d.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/latches_map.v)) +$(eval $(call add_share_file,share/lattice,techlibs/lattice/dsp_map_18x18.v)) diff --git a/yosys/techlibs/lattice/arith_map_ccu2c.v b/yosys/techlibs/lattice/arith_map_ccu2c.v new file mode 100644 index 00000000000..a5efc35613a --- /dev/null +++ b/yosys/techlibs/lattice/arith_map_ccu2c.v @@ -0,0 +1,90 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_ccu2c_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up2; + input integer N; + begin + round_up2 = ((N + 1) / 2) * 2; + end + endfunction + + localparam Y_WIDTH2 = round_up2(Y_WIDTH); + + (* force_downto *) + wire [Y_WIDTH2-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BX = B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] C = {CO, CI}; + (* force_downto *) + wire [Y_WIDTH2-1:0] FCO, Y1; + + genvar i; + generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice + CCU2C #( + .INIT0(16'b1001011010101010), + .INIT1(16'b1001011010101010), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) ccu2c_i ( + .CIN(C[i]), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1), + .S0(Y[i]), .S1(Y1[i]), + .COUT(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i+1 < Y_WIDTH) begin + assign CO[i+1] = FCO[i]; + assign Y[i+1] = Y1[i]; + end + end endgenerate + + assign X = AA ^ BB; +endmodule diff --git a/yosys/techlibs/machxo2/arith_map.v b/yosys/techlibs/lattice/arith_map_ccu2d.v similarity index 98% rename from yosys/techlibs/machxo2/arith_map.v rename to yosys/techlibs/lattice/arith_map_ccu2d.v index ab4a6b1da6c..31e4afe09a1 100644 --- a/yosys/techlibs/machxo2/arith_map.v +++ b/yosys/techlibs/lattice/arith_map_ccu2d.v @@ -19,7 +19,7 @@ */ (* techmap_celltype = "$alu" *) -module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); +module _80_ccu2d_alu (A, B, CI, BI, X, Y, CO); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; diff --git a/yosys/techlibs/lattice/brams_16kd.txt b/yosys/techlibs/lattice/brams_16kd.txt new file mode 100644 index 00000000000..ccdf490501f --- /dev/null +++ b/yosys/techlibs/lattice/brams_16kd.txt @@ -0,0 +1,52 @@ +ram block $__DP16KD_ { + abits 14; + widths 1 2 4 9 18 per_port; + byte 9; + cost 128; + init no_undef; + port srsw "A" "B" { + clock anyedge; + clken; + wrbe_separate; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} + +ram block $__PDPW16KD_ { + abits 14; + widths 1 2 4 9 18 36 per_port; + byte 9; + cost 128; + init no_undef; + port sr "R" { + clock anyedge; + clken; + option "RESETMODE" "SYNC" { + rdsrst zero ungated; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } + port sw "W" { + width 36; + clock anyedge; + clken; + } +} diff --git a/yosys/techlibs/machxo2/brams.txt b/yosys/techlibs/lattice/brams_8kc.txt similarity index 84% rename from yosys/techlibs/machxo2/brams.txt rename to yosys/techlibs/lattice/brams_8kc.txt index 3afbeda07e6..f254c46aa82 100644 --- a/yosys/techlibs/machxo2/brams.txt +++ b/yosys/techlibs/lattice/brams_8kc.txt @@ -32,6 +32,10 @@ ram block $__PDPW8KC_ { cost 64; init no_undef; port sr "R" { + # width 2 cannot be supported because of quirks + # of the primitive, and memlib requires us to + # remove width 1 as well + width 4 9 18; clock posedge; clken; option "RESETMODE" "SYNC" { diff --git a/yosys/techlibs/lattice/brams_map_16kd.v b/yosys/techlibs/lattice/brams_map_16kd.v new file mode 100644 index 00000000000..da4d8041770 --- /dev/null +++ b/yosys/techlibs/lattice/brams_map_16kd.v @@ -0,0 +1,489 @@ +module $__DP16KD_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_A_WIDTH = 18; +parameter PORT_A_WR_BE_WIDTH = 2; +parameter PORT_A_CLK_POL = 1; +parameter PORT_A_OPTION_WRITEMODE = "NORMAL"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input PORT_A_RD_SRST; +input PORT_A_RD_ARST; +input [13:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +parameter PORT_B_WIDTH = 18; +parameter PORT_B_WR_BE_WIDTH = 2; +parameter PORT_B_CLK_POL = 1; +parameter PORT_B_OPTION_WRITEMODE = "NORMAL"; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input PORT_B_RD_SRST; +input PORT_B_RD_ARST; +input [13:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [17:0] DOA; +wire [17:0] DOB; +wire [17:0] DIA = PORT_A_WR_DATA; +wire [17:0] DIB = PORT_B_WR_DATA; + +assign PORT_A_RD_DATA = DOA; +assign PORT_B_RD_DATA = DOB; + +DP16KD #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .INITVAL_20(init_slice('h20)), + .INITVAL_21(init_slice('h21)), + .INITVAL_22(init_slice('h22)), + .INITVAL_23(init_slice('h23)), + .INITVAL_24(init_slice('h24)), + .INITVAL_25(init_slice('h25)), + .INITVAL_26(init_slice('h26)), + .INITVAL_27(init_slice('h27)), + .INITVAL_28(init_slice('h28)), + .INITVAL_29(init_slice('h29)), + .INITVAL_2A(init_slice('h2a)), + .INITVAL_2B(init_slice('h2b)), + .INITVAL_2C(init_slice('h2c)), + .INITVAL_2D(init_slice('h2d)), + .INITVAL_2E(init_slice('h2e)), + .INITVAL_2F(init_slice('h2f)), + .INITVAL_30(init_slice('h30)), + .INITVAL_31(init_slice('h31)), + .INITVAL_32(init_slice('h32)), + .INITVAL_33(init_slice('h33)), + .INITVAL_34(init_slice('h34)), + .INITVAL_35(init_slice('h35)), + .INITVAL_36(init_slice('h36)), + .INITVAL_37(init_slice('h37)), + .INITVAL_38(init_slice('h38)), + .INITVAL_39(init_slice('h39)), + .INITVAL_3A(init_slice('h3a)), + .INITVAL_3B(init_slice('h3b)), + .INITVAL_3C(init_slice('h3c)), + .INITVAL_3D(init_slice('h3d)), + .INITVAL_3E(init_slice('h3e)), + .INITVAL_3F(init_slice('h3f)), + .DATA_WIDTH_A(PORT_A_WIDTH), + .DATA_WIDTH_B(PORT_B_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .CLKAMUX(PORT_A_CLK_POL ? "CLKA" : "INV"), + .CLKBMUX(PORT_B_CLK_POL ? "CLKB" : "INV"), + .WRITEMODE_A(PORT_A_OPTION_WRITEMODE), + .WRITEMODE_B(PORT_B_OPTION_WRITEMODE), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_A_CLK), + .WEA(PORT_A_WIDTH == 18 ? PORT_A_WR_EN : (PORT_A_WR_EN | PORT_A_WR_BE[0])), + .CEA(PORT_A_CLK_EN), + .OCEA(1'b1), + .RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[0] : PORT_A_ADDR[0]), + .ADA1(PORT_A_WIDTH == 18 ? PORT_A_WR_BE[1] : PORT_A_ADDR[1]), + .ADA2(PORT_A_ADDR[2]), + .ADA3(PORT_A_ADDR[3]), + .ADA4(PORT_A_ADDR[4]), + .ADA5(PORT_A_ADDR[5]), + .ADA6(PORT_A_ADDR[6]), + .ADA7(PORT_A_ADDR[7]), + .ADA8(PORT_A_ADDR[8]), + .ADA9(PORT_A_ADDR[9]), + .ADA10(PORT_A_ADDR[10]), + .ADA11(PORT_A_ADDR[11]), + .ADA12(PORT_A_ADDR[12]), + .ADA13(PORT_A_ADDR[13]), + .DIA0(DIA[0]), + .DIA1(DIA[1]), + .DIA2(DIA[2]), + .DIA3(DIA[3]), + .DIA4(DIA[4]), + .DIA5(DIA[5]), + .DIA6(DIA[6]), + .DIA7(DIA[7]), + .DIA8(DIA[8]), + .DIA9(DIA[9]), + .DIA10(DIA[10]), + .DIA11(DIA[11]), + .DIA12(DIA[12]), + .DIA13(DIA[13]), + .DIA14(DIA[14]), + .DIA15(DIA[15]), + .DIA16(DIA[16]), + .DIA17(DIA[17]), + .DOA0(DOA[0]), + .DOA1(DOA[1]), + .DOA2(DOA[2]), + .DOA3(DOA[3]), + .DOA4(DOA[4]), + .DOA5(DOA[5]), + .DOA6(DOA[6]), + .DOA7(DOA[7]), + .DOA8(DOA[8]), + .DOA9(DOA[9]), + .DOA10(DOA[10]), + .DOA11(DOA[11]), + .DOA12(DOA[12]), + .DOA13(DOA[13]), + .DOA14(DOA[14]), + .DOA15(DOA[15]), + .DOA16(DOA[16]), + .DOA17(DOA[17]), + + .CLKB(PORT_B_CLK), + .WEB(PORT_B_WIDTH == 18 ? PORT_B_WR_EN : (PORT_B_WR_EN | PORT_B_WR_BE[0])), + .CEB(PORT_B_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[0] : PORT_B_ADDR[0]), + .ADB1(PORT_B_WIDTH == 18 ? PORT_B_WR_BE[1] : PORT_B_ADDR[1]), + .ADB2(PORT_B_ADDR[2]), + .ADB3(PORT_B_ADDR[3]), + .ADB4(PORT_B_ADDR[4]), + .ADB5(PORT_B_ADDR[5]), + .ADB6(PORT_B_ADDR[6]), + .ADB7(PORT_B_ADDR[7]), + .ADB8(PORT_B_ADDR[8]), + .ADB9(PORT_B_ADDR[9]), + .ADB10(PORT_B_ADDR[10]), + .ADB11(PORT_B_ADDR[11]), + .ADB12(PORT_B_ADDR[12]), + .ADB13(PORT_B_ADDR[13]), + .DIB0(DIB[0]), + .DIB1(DIB[1]), + .DIB2(DIB[2]), + .DIB3(DIB[3]), + .DIB4(DIB[4]), + .DIB5(DIB[5]), + .DIB6(DIB[6]), + .DIB7(DIB[7]), + .DIB8(DIB[8]), + .DIB9(DIB[9]), + .DIB10(DIB[10]), + .DIB11(DIB[11]), + .DIB12(DIB[12]), + .DIB13(DIB[13]), + .DIB14(DIB[14]), + .DIB15(DIB[15]), + .DIB16(DIB[16]), + .DIB17(DIB[17]), + .DOB0(DOB[0]), + .DOB1(DOB[1]), + .DOB2(DOB[2]), + .DOB3(DOB[3]), + .DOB4(DOB[4]), + .DOB5(DOB[5]), + .DOB6(DOB[6]), + .DOB7(DOB[7]), + .DOB8(DOB[8]), + .DOB9(DOB[9]), + .DOB10(DOB[10]), + .DOB11(DOB[11]), + .DOB12(DOB[12]), + .DOB13(DOB[13]), + .DOB14(DOB[14]), + .DOB15(DOB[15]), + .DOB16(DOB[16]), + .DOB17(DOB[17]), +); + +endmodule + + +module $__PDPW16KD_ (...); + +parameter INIT = 0; +parameter OPTION_RESETMODE = "SYNC"; + +parameter PORT_R_WIDTH = 36; +parameter PORT_R_CLK_POL = 1; + +input PORT_R_CLK; +input PORT_R_CLK_EN; +input PORT_R_RD_SRST; +input PORT_R_RD_ARST; +input [13:0] PORT_R_ADDR; +output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; + +parameter PORT_W_WIDTH = 36; +parameter PORT_W_WR_EN_WIDTH = 4; +parameter PORT_W_CLK_POL = 1; + +input PORT_W_CLK; +input PORT_W_CLK_EN; +input [13:0] PORT_W_ADDR; +input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN; +input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; + +function [319:0] init_slice; + input integer idx; + integer i, j; + init_slice = 0; + for (i = 0; i < 16; i = i + 1) begin + init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18]; + end +endfunction + +wire [35:0] DI = PORT_W_WR_DATA; +wire [35:0] DO; + +assign PORT_R_RD_DATA = PORT_R_WIDTH == 36 ? DO : DO[35:18]; + +DP16KD #( + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), + .INITVAL_20(init_slice('h20)), + .INITVAL_21(init_slice('h21)), + .INITVAL_22(init_slice('h22)), + .INITVAL_23(init_slice('h23)), + .INITVAL_24(init_slice('h24)), + .INITVAL_25(init_slice('h25)), + .INITVAL_26(init_slice('h26)), + .INITVAL_27(init_slice('h27)), + .INITVAL_28(init_slice('h28)), + .INITVAL_29(init_slice('h29)), + .INITVAL_2A(init_slice('h2a)), + .INITVAL_2B(init_slice('h2b)), + .INITVAL_2C(init_slice('h2c)), + .INITVAL_2D(init_slice('h2d)), + .INITVAL_2E(init_slice('h2e)), + .INITVAL_2F(init_slice('h2f)), + .INITVAL_30(init_slice('h30)), + .INITVAL_31(init_slice('h31)), + .INITVAL_32(init_slice('h32)), + .INITVAL_33(init_slice('h33)), + .INITVAL_34(init_slice('h34)), + .INITVAL_35(init_slice('h35)), + .INITVAL_36(init_slice('h36)), + .INITVAL_37(init_slice('h37)), + .INITVAL_38(init_slice('h38)), + .INITVAL_39(init_slice('h39)), + .INITVAL_3A(init_slice('h3a)), + .INITVAL_3B(init_slice('h3b)), + .INITVAL_3C(init_slice('h3c)), + .INITVAL_3D(init_slice('h3d)), + .INITVAL_3E(init_slice('h3e)), + .INITVAL_3F(init_slice('h3f)), + .DATA_WIDTH_A(PORT_W_WIDTH), + .DATA_WIDTH_B(PORT_R_WIDTH), + .REGMODE_A("NOREG"), + .REGMODE_B("NOREG"), + .RESETMODE(OPTION_RESETMODE), + .ASYNC_RESET_RELEASE(OPTION_RESETMODE), + .CSDECODE_A("0b000"), + .CSDECODE_B("0b000"), + .CLKAMUX(PORT_W_CLK_POL ? "CLKA" : "INV"), + .CLKBMUX(PORT_R_CLK_POL ? "CLKB" : "INV"), + .GSR("AUTO") +) _TECHMAP_REPLACE_ ( + .CLKA(PORT_W_CLK), + .WEA(PORT_W_WIDTH >= 18 ? 1'b1 : PORT_W_WR_EN[0]), + .CEA(PORT_W_CLK_EN), + .OCEA(1'b0), + .RSTA(1'b0), + .CSA0(1'b0), + .CSA1(1'b0), + .CSA2(1'b0), + .ADA0(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]), + .ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]), + .ADA2(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[2] : PORT_W_ADDR[2]), + .ADA3(PORT_W_WIDTH >= 36 ? PORT_W_WR_EN[3] : PORT_W_ADDR[3]), + .ADA4(PORT_W_ADDR[4]), + .ADA5(PORT_W_ADDR[5]), + .ADA6(PORT_W_ADDR[6]), + .ADA7(PORT_W_ADDR[7]), + .ADA8(PORT_W_ADDR[8]), + .ADA9(PORT_W_ADDR[9]), + .ADA10(PORT_W_ADDR[10]), + .ADA11(PORT_W_ADDR[11]), + .ADA12(PORT_W_ADDR[12]), + .ADA13(PORT_W_ADDR[13]), + .DIA0(DI[0]), + .DIA1(DI[1]), + .DIA2(DI[2]), + .DIA3(DI[3]), + .DIA4(DI[4]), + .DIA5(DI[5]), + .DIA6(DI[6]), + .DIA7(DI[7]), + .DIA8(DI[8]), + .DIA9(DI[9]), + .DIA10(DI[10]), + .DIA11(DI[11]), + .DIA12(DI[12]), + .DIA13(DI[13]), + .DIA14(DI[14]), + .DIA15(DI[15]), + .DIA16(DI[16]), + .DIA17(DI[17]), + .DIB0(DI[18]), + .DIB1(DI[19]), + .DIB2(DI[20]), + .DIB3(DI[21]), + .DIB4(DI[22]), + .DIB5(DI[23]), + .DIB6(DI[24]), + .DIB7(DI[25]), + .DIB8(DI[26]), + .DIB9(DI[27]), + .DIB10(DI[28]), + .DIB11(DI[29]), + .DIB12(DI[30]), + .DIB13(DI[31]), + .DIB14(DI[32]), + .DIB15(DI[33]), + .DIB16(DI[34]), + .DIB17(DI[35]), + + .CLKB(PORT_R_CLK), + .WEB(1'b0), + .CEB(PORT_R_CLK_EN), + .OCEB(1'b1), + .RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST), + .CSB0(1'b0), + .CSB1(1'b0), + .CSB2(1'b0), + .ADB0(PORT_R_ADDR[0]), + .ADB1(PORT_R_ADDR[1]), + .ADB2(PORT_R_ADDR[2]), + .ADB3(PORT_R_ADDR[3]), + .ADB4(PORT_R_ADDR[4]), + .ADB5(PORT_R_ADDR[5]), + .ADB6(PORT_R_ADDR[6]), + .ADB7(PORT_R_ADDR[7]), + .ADB8(PORT_R_ADDR[8]), + .ADB9(PORT_R_ADDR[9]), + .ADB10(PORT_R_ADDR[10]), + .ADB11(PORT_R_ADDR[11]), + .ADB12(PORT_R_ADDR[12]), + .ADB13(PORT_R_ADDR[13]), + .DOA0(DO[0]), + .DOA1(DO[1]), + .DOA2(DO[2]), + .DOA3(DO[3]), + .DOA4(DO[4]), + .DOA5(DO[5]), + .DOA6(DO[6]), + .DOA7(DO[7]), + .DOA8(DO[8]), + .DOA9(DO[9]), + .DOA10(DO[10]), + .DOA11(DO[11]), + .DOA12(DO[12]), + .DOA13(DO[13]), + .DOA14(DO[14]), + .DOA15(DO[15]), + .DOA16(DO[16]), + .DOA17(DO[17]), + .DOB0(DO[18]), + .DOB1(DO[19]), + .DOB2(DO[20]), + .DOB3(DO[21]), + .DOB4(DO[22]), + .DOB5(DO[23]), + .DOB6(DO[24]), + .DOB7(DO[25]), + .DOB8(DO[26]), + .DOB9(DO[27]), + .DOB10(DO[28]), + .DOB11(DO[29]), + .DOB12(DO[30]), + .DOB13(DO[31]), + .DOB14(DO[32]), + .DOB15(DO[33]), + .DOB16(DO[34]), + .DOB17(DO[35]), +); + +endmodule diff --git a/yosys/techlibs/machxo2/brams_map.v b/yosys/techlibs/lattice/brams_map_8kc.v similarity index 94% rename from yosys/techlibs/machxo2/brams_map.v rename to yosys/techlibs/lattice/brams_map_8kc.v index 6783e5b2902..b57250fc7a6 100644 --- a/yosys/techlibs/machxo2/brams_map.v +++ b/yosys/techlibs/lattice/brams_map_8kc.v @@ -38,8 +38,20 @@ endfunction wire [8:0] DOA; wire [8:0] DOB; -wire [8:0] DIA = PORT_A_WR_DATA; -wire [8:0] DIB = PORT_B_WR_DATA; +wire [8:0] DIA; +wire [8:0] DIB; + +case(PORT_A_WIDTH) + 1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx}; + 2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx}; + default: assign DIA = PORT_A_WR_DATA; +endcase + +case(PORT_B_WIDTH) + 1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx}; + 2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx}; + default: assign DIB = PORT_B_WR_DATA; +endcase assign PORT_A_RD_DATA = DOA; assign PORT_B_RD_DATA = DOB; diff --git a/yosys/techlibs/lattice/ccu2c_sim.vh b/yosys/techlibs/lattice/ccu2c_sim.vh new file mode 100644 index 00000000000..d9eb69ab455 --- /dev/null +++ b/yosys/techlibs/lattice/ccu2c_sim.vh @@ -0,0 +1,61 @@ +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module CCU2C( + (* abc9_carry *) + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + (* abc9_carry *) + output COUT +); + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); + + specify + (A0 => S0) = 379; + (B0 => S0) = 379; + (C0 => S0) = 275; + (D0 => S0) = 141; + (CIN => S0) = 257; + (A0 => S1) = 630; + (B0 => S1) = 630; + (C0 => S1) = 526; + (D0 => S1) = 392; + (A1 => S1) = 379; + (B1 => S1) = 379; + (C1 => S1) = 275; + (D1 => S1) = 141; + (CIN => S1) = 273; + (A0 => COUT) = 516; + (B0 => COUT) = 516; + (C0 => COUT) = 412; + (D0 => COUT) = 278; + (A1 => COUT) = 516; + (B1 => COUT) = 516; + (C1 => COUT) = 412; + (D1 => COUT) = 278; + (CIN => COUT) = 43; + endspecify +endmodule diff --git a/yosys/techlibs/lattice/ccu2d_sim.vh b/yosys/techlibs/lattice/ccu2d_sim.vh new file mode 100644 index 00000000000..5b9c95cc9ef --- /dev/null +++ b/yosys/techlibs/lattice/ccu2d_sim.vh @@ -0,0 +1,33 @@ +// --------------------------------------- +(* lib_whitebox *) +module CCU2D ( + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + output COUT +); + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); +endmodule diff --git a/yosys/techlibs/lattice/cells_bb_ecp5.v b/yosys/techlibs/lattice/cells_bb_ecp5.v new file mode 100644 index 00000000000..fc22495e2ff --- /dev/null +++ b/yosys/techlibs/lattice/cells_bb_ecp5.v @@ -0,0 +1,2175 @@ +// Created by cells_xtra.py from Lattice models + +(* blackbox *) (* keep *) +module GSR (...); + input GSR; +endmodule + +(* blackbox *) +module PUR (...); + parameter RST_PULSE = 1; + input PUR; +endmodule + +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; +endmodule + +(* blackbox *) +module DP16KD (...); + parameter DATA_WIDTH_A = 18; + parameter DATA_WIDTH_B = 18; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter GSR = "ENABLED"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + input DIA17; + input DIA16; + input DIA15; + input DIA14; + input DIA13; + input DIA12; + input DIA11; + input DIA10; + input DIA9; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA13; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB17; + input DIB16; + input DIB15; + input DIB14; + input DIB13; + input DIB12; + input DIB11; + input DIB10; + input DIB9; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB13; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA17; + output DOA16; + output DOA15; + output DOA14; + output DOA13; + output DOA12; + output DOA11; + output DOA10; + output DOA9; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB17; + output DOB16; + output DOB15; + output DOB14; + output DOB13; + output DOB12; + output DOB11; + output DOB10; + output DOB9; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; +endmodule + +(* blackbox *) +module PDPW16KD (...); + parameter DATA_WIDTH_W = 36; + parameter DATA_WIDTH_R = 36; + parameter GSR = "ENABLED"; + parameter REGMODE = "NOREG"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + input DI35; + input DI34; + input DI33; + input DI32; + input DI31; + input DI30; + input DI29; + input DI28; + input DI27; + input DI26; + input DI25; + input DI24; + input DI23; + input DI22; + input DI21; + input DI20; + input DI19; + input DI18; + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE3; + input BE2; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR13; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO35; + output DO34; + output DO33; + output DO32; + output DO31; + output DO30; + output DO29; + output DO28; + output DO27; + output DO26; + output DO25; + output DO24; + output DO23; + output DO22; + output DO21; + output DO20; + output DO19; + output DO18; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module MULT18X18D (...); + parameter REG_INPUTA_CLK = "NONE"; + parameter REG_INPUTA_CE = "CE0"; + parameter REG_INPUTA_RST = "RST0"; + parameter REG_INPUTB_CLK = "NONE"; + parameter REG_INPUTB_CE = "CE0"; + parameter REG_INPUTB_RST = "RST0"; + parameter REG_INPUTC_CLK = "NONE"; + parameter REG_INPUTC_CE = "CE0"; + parameter REG_INPUTC_RST = "RST0"; + parameter REG_PIPELINE_CLK = "NONE"; + parameter REG_PIPELINE_CE = "CE0"; + parameter REG_PIPELINE_RST = "RST0"; + parameter REG_OUTPUT_CLK = "NONE"; + parameter REG_OUTPUT_CE = "CE0"; + parameter REG_OUTPUT_RST = "RST0"; + parameter CLK0_DIV = "ENABLED"; + parameter CLK1_DIV = "ENABLED"; + parameter CLK2_DIV = "ENABLED"; + parameter CLK3_DIV = "ENABLED"; + parameter HIGHSPEED_CLK = "NONE"; + parameter GSR = "ENABLED"; + parameter CAS_MATCH_REG = "FALSE"; + parameter SOURCEB_MODE = "B_SHIFT"; + parameter MULT_BYPASS = "DISABLED"; + parameter RESETMODE = "SYNC"; + input A17; + input A16; + input A15; + input A14; + input A13; + input A12; + input A11; + input A10; + input A9; + input A8; + input A7; + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B17; + input B16; + input B15; + input B14; + input B13; + input B12; + input B11; + input B10; + input B9; + input B8; + input B7; + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + input SIGNEDA; + input SIGNEDB; + input SOURCEA; + input SOURCEB; + input CLK3; + input CLK2; + input CLK1; + input CLK0; + input CE3; + input CE2; + input CE1; + input CE0; + input RST3; + input RST2; + input RST1; + input RST0; + input SRIA17; + input SRIA16; + input SRIA15; + input SRIA14; + input SRIA13; + input SRIA12; + input SRIA11; + input SRIA10; + input SRIA9; + input SRIA8; + input SRIA7; + input SRIA6; + input SRIA5; + input SRIA4; + input SRIA3; + input SRIA2; + input SRIA1; + input SRIA0; + input SRIB17; + input SRIB16; + input SRIB15; + input SRIB14; + input SRIB13; + input SRIB12; + input SRIB11; + input SRIB10; + input SRIB9; + input SRIB8; + input SRIB7; + input SRIB6; + input SRIB5; + input SRIB4; + input SRIB3; + input SRIB2; + input SRIB1; + input SRIB0; + output SROA17; + output SROA16; + output SROA15; + output SROA14; + output SROA13; + output SROA12; + output SROA11; + output SROA10; + output SROA9; + output SROA8; + output SROA7; + output SROA6; + output SROA5; + output SROA4; + output SROA3; + output SROA2; + output SROA1; + output SROA0; + output SROB17; + output SROB16; + output SROB15; + output SROB14; + output SROB13; + output SROB12; + output SROB11; + output SROB10; + output SROB9; + output SROB8; + output SROB7; + output SROB6; + output SROB5; + output SROB4; + output SROB3; + output SROB2; + output SROB1; + output SROB0; + output ROA17; + output ROA16; + output ROA15; + output ROA14; + output ROA13; + output ROA12; + output ROA11; + output ROA10; + output ROA9; + output ROA8; + output ROA7; + output ROA6; + output ROA5; + output ROA4; + output ROA3; + output ROA2; + output ROA1; + output ROA0; + output ROB17; + output ROB16; + output ROB15; + output ROB14; + output ROB13; + output ROB12; + output ROB11; + output ROB10; + output ROB9; + output ROB8; + output ROB7; + output ROB6; + output ROB5; + output ROB4; + output ROB3; + output ROB2; + output ROB1; + output ROB0; + output ROC17; + output ROC16; + output ROC15; + output ROC14; + output ROC13; + output ROC12; + output ROC11; + output ROC10; + output ROC9; + output ROC8; + output ROC7; + output ROC6; + output ROC5; + output ROC4; + output ROC3; + output ROC2; + output ROC1; + output ROC0; + output P35; + output P34; + output P33; + output P32; + output P31; + output P30; + output P29; + output P28; + output P27; + output P26; + output P25; + output P24; + output P23; + output P22; + output P21; + output P20; + output P19; + output P18; + output P17; + output P16; + output P15; + output P14; + output P13; + output P12; + output P11; + output P10; + output P9; + output P8; + output P7; + output P6; + output P5; + output P4; + output P3; + output P2; + output P1; + output P0; + output SIGNEDP; +endmodule + +(* blackbox *) +module ALU54B (...); + parameter REG_INPUTC0_CLK = "NONE"; + parameter REG_INPUTC0_CE = "CE0"; + parameter REG_INPUTC0_RST = "RST0"; + parameter REG_INPUTC1_CLK = "NONE"; + parameter REG_INPUTC1_CE = "CE0"; + parameter REG_INPUTC1_RST = "RST0"; + parameter REG_OPCODEOP0_0_CLK = "NONE"; + parameter REG_OPCODEOP0_0_CE = "CE0"; + parameter REG_OPCODEOP0_0_RST = "RST0"; + parameter REG_OPCODEOP1_0_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CE = "CE0"; + parameter REG_OPCODEOP0_1_RST = "RST0"; + parameter REG_OPCODEOP1_1_CLK = "NONE"; + parameter REG_OPCODEIN_0_CLK = "NONE"; + parameter REG_OPCODEIN_0_CE = "CE0"; + parameter REG_OPCODEIN_0_RST = "RST0"; + parameter REG_OPCODEIN_1_CLK = "NONE"; + parameter REG_OPCODEIN_1_CE = "CE0"; + parameter REG_OPCODEIN_1_RST = "RST0"; + parameter REG_OUTPUT0_CLK = "NONE"; + parameter REG_OUTPUT0_CE = "CE0"; + parameter REG_OUTPUT0_RST = "RST0"; + parameter REG_OUTPUT1_CLK = "NONE"; + parameter REG_OUTPUT1_CE = "CE0"; + parameter REG_OUTPUT1_RST = "RST0"; + parameter REG_FLAG_CLK = "NONE"; + parameter REG_FLAG_CE = "CE0"; + parameter REG_FLAG_RST = "RST0"; + parameter MCPAT_SOURCE = "STATIC"; + parameter MASKPAT_SOURCE = "STATIC"; + parameter MASK01 = "0x00000000000000"; + parameter REG_INPUTCFB_CLK = "NONE"; + parameter REG_INPUTCFB_CE = "CE0"; + parameter REG_INPUTCFB_RST = "RST0"; + parameter CLK0_DIV = "ENABLED"; + parameter CLK1_DIV = "ENABLED"; + parameter CLK2_DIV = "ENABLED"; + parameter CLK3_DIV = "ENABLED"; + parameter MCPAT = "0x00000000000000"; + parameter MASKPAT = "0x00000000000000"; + parameter RNDPAT = "0x00000000000000"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter MULT9_MODE = "DISABLED"; + parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; + parameter LEGACY = "DISABLED"; + input CE3; + input CE2; + input CE1; + input CE0; + input CLK3; + input CLK2; + input CLK1; + input CLK0; + input RST3; + input RST2; + input RST1; + input RST0; + input SIGNEDIA; + input SIGNEDIB; + input SIGNEDCIN; + input A35; + input A34; + input A33; + input A32; + input A31; + input A30; + input A29; + input A28; + input A27; + input A26; + input A25; + input A24; + input A23; + input A22; + input A21; + input A20; + input A19; + input A18; + input A17; + input A16; + input A15; + input A14; + input A13; + input A12; + input A11; + input A10; + input A9; + input A8; + input A7; + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B35; + input B34; + input B33; + input B32; + input B31; + input B30; + input B29; + input B28; + input B27; + input B26; + input B25; + input B24; + input B23; + input B22; + input B21; + input B20; + input B19; + input B18; + input B17; + input B16; + input B15; + input B14; + input B13; + input B12; + input B11; + input B10; + input B9; + input B8; + input B7; + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C53; + input C52; + input C51; + input C50; + input C49; + input C48; + input C47; + input C46; + input C45; + input C44; + input C43; + input C42; + input C41; + input C40; + input C39; + input C38; + input C37; + input C36; + input C35; + input C34; + input C33; + input C32; + input C31; + input C30; + input C29; + input C28; + input C27; + input C26; + input C25; + input C24; + input C23; + input C22; + input C21; + input C20; + input C19; + input C18; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + input CFB53; + input CFB52; + input CFB51; + input CFB50; + input CFB49; + input CFB48; + input CFB47; + input CFB46; + input CFB45; + input CFB44; + input CFB43; + input CFB42; + input CFB41; + input CFB40; + input CFB39; + input CFB38; + input CFB37; + input CFB36; + input CFB35; + input CFB34; + input CFB33; + input CFB32; + input CFB31; + input CFB30; + input CFB29; + input CFB28; + input CFB27; + input CFB26; + input CFB25; + input CFB24; + input CFB23; + input CFB22; + input CFB21; + input CFB20; + input CFB19; + input CFB18; + input CFB17; + input CFB16; + input CFB15; + input CFB14; + input CFB13; + input CFB12; + input CFB11; + input CFB10; + input CFB9; + input CFB8; + input CFB7; + input CFB6; + input CFB5; + input CFB4; + input CFB3; + input CFB2; + input CFB1; + input CFB0; + input MA35; + input MA34; + input MA33; + input MA32; + input MA31; + input MA30; + input MA29; + input MA28; + input MA27; + input MA26; + input MA25; + input MA24; + input MA23; + input MA22; + input MA21; + input MA20; + input MA19; + input MA18; + input MA17; + input MA16; + input MA15; + input MA14; + input MA13; + input MA12; + input MA11; + input MA10; + input MA9; + input MA8; + input MA7; + input MA6; + input MA5; + input MA4; + input MA3; + input MA2; + input MA1; + input MA0; + input MB35; + input MB34; + input MB33; + input MB32; + input MB31; + input MB30; + input MB29; + input MB28; + input MB27; + input MB26; + input MB25; + input MB24; + input MB23; + input MB22; + input MB21; + input MB20; + input MB19; + input MB18; + input MB17; + input MB16; + input MB15; + input MB14; + input MB13; + input MB12; + input MB11; + input MB10; + input MB9; + input MB8; + input MB7; + input MB6; + input MB5; + input MB4; + input MB3; + input MB2; + input MB1; + input MB0; + input CIN53; + input CIN52; + input CIN51; + input CIN50; + input CIN49; + input CIN48; + input CIN47; + input CIN46; + input CIN45; + input CIN44; + input CIN43; + input CIN42; + input CIN41; + input CIN40; + input CIN39; + input CIN38; + input CIN37; + input CIN36; + input CIN35; + input CIN34; + input CIN33; + input CIN32; + input CIN31; + input CIN30; + input CIN29; + input CIN28; + input CIN27; + input CIN26; + input CIN25; + input CIN24; + input CIN23; + input CIN22; + input CIN21; + input CIN20; + input CIN19; + input CIN18; + input CIN17; + input CIN16; + input CIN15; + input CIN14; + input CIN13; + input CIN12; + input CIN11; + input CIN10; + input CIN9; + input CIN8; + input CIN7; + input CIN6; + input CIN5; + input CIN4; + input CIN3; + input CIN2; + input CIN1; + input CIN0; + input OP10; + input OP9; + input OP8; + input OP7; + input OP6; + input OP5; + input OP4; + input OP3; + input OP2; + input OP1; + input OP0; + output R53; + output R52; + output R51; + output R50; + output R49; + output R48; + output R47; + output R46; + output R45; + output R44; + output R43; + output R42; + output R41; + output R40; + output R39; + output R38; + output R37; + output R36; + output R35; + output R34; + output R33; + output R32; + output R31; + output R30; + output R29; + output R28; + output R27; + output R26; + output R25; + output R24; + output R23; + output R22; + output R21; + output R20; + output R19; + output R18; + output R17; + output R16; + output R15; + output R14; + output R13; + output R12; + output R11; + output R10; + output R9; + output R8; + output R7; + output R6; + output R5; + output R4; + output R3; + output R2; + output R1; + output R0; + output CO53; + output CO52; + output CO51; + output CO50; + output CO49; + output CO48; + output CO47; + output CO46; + output CO45; + output CO44; + output CO43; + output CO42; + output CO41; + output CO40; + output CO39; + output CO38; + output CO37; + output CO36; + output CO35; + output CO34; + output CO33; + output CO32; + output CO31; + output CO30; + output CO29; + output CO28; + output CO27; + output CO26; + output CO25; + output CO24; + output CO23; + output CO22; + output CO21; + output CO20; + output CO19; + output CO18; + output CO17; + output CO16; + output CO15; + output CO14; + output CO13; + output CO12; + output CO11; + output CO10; + output CO9; + output CO8; + output CO7; + output CO6; + output CO5; + output CO4; + output CO3; + output CO2; + output CO1; + output CO0; + output EQZ; + output EQZM; + output EQOM; + output EQPAT; + output EQPATB; + output OVER; + output UNDER; + output OVERUNDER; + output SIGNEDR; +endmodule + +(* blackbox *) +module CLKDIVF (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input CLKI; + input RST; + input ALIGNWD; + output CDIVX; +endmodule + +(* blackbox *) +module PCSCLKDIV (...); + parameter GSR = "DISABLED"; + input CLKI; + input RST; + input SEL2; + input SEL1; + input SEL0; + output CDIV1; + output CDIVX; +endmodule + +(* blackbox *) +module DCSC (...); + parameter DCSMODE = "POS"; + input CLK1; + input CLK0; + input SEL1; + input SEL0; + input MODESEL; + output DCSOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) +module ECLKSYNCB (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + +(* blackbox *) +module DELAYF (...); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; + input A; + input LOADN; + input MOVE; + input DIRECTION; + output Z; + output CFLAG; +endmodule + +(* blackbox *) +module DELAYG (...); + parameter DEL_MODE = "USER_DEFINED"; + parameter DEL_VALUE = 0; + input A; + output Z; +endmodule + +(* blackbox *) (* keep *) +module USRMCLK (...); + input USRMCLKI; + input USRMCLKTS; +endmodule + +(* blackbox *) +module DQSBUFM (...); + parameter DQS_LI_DEL_VAL = 4; + parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; + parameter DQS_LO_DEL_VAL = 0; + parameter DQS_LO_DEL_ADJ = "FACTORYONLY"; + parameter GSR = "ENABLED"; + input DQSI; + input READ1; + input READ0; + input READCLKSEL2; + input READCLKSEL1; + input READCLKSEL0; + input DDRDEL; + input ECLK; + input SCLK; + input RST; + input DYNDELAY7; + input DYNDELAY6; + input DYNDELAY5; + input DYNDELAY4; + input DYNDELAY3; + input DYNDELAY2; + input DYNDELAY1; + input DYNDELAY0; + input PAUSE; + input RDLOADN; + input RDMOVE; + input RDDIRECTION; + input WRLOADN; + input WRMOVE; + input WRDIRECTION; + output DQSR90; + output DQSW; + output DQSW270; + output RDPNTR2; + output RDPNTR1; + output RDPNTR0; + output WRPNTR2; + output WRPNTR1; + output WRPNTR0; + output DATAVALID; + output BURSTDET; + output RDCFLAG; + output WRCFLAG; +endmodule + +(* blackbox *) +module DDRDLLA (...); + parameter FORCE_MAX_DELAY = "NO"; + parameter GSR = "ENABLED"; + input CLK; + input RST; + input UDDCNTLN; + input FREEZE; + output DDRDEL; + output LOCK; + output DCNTL7; + output DCNTL6; + output DCNTL5; + output DCNTL4; + output DCNTL3; + output DCNTL2; + output DCNTL1; + output DCNTL0; +endmodule + +(* blackbox *) +module DLLDELD (...); + input A; + input DDRDEL; + input LOADN; + input MOVE; + input DIRECTION; + output Z; + output CFLAG; +endmodule + +(* blackbox *) +module IDDRX1F (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input RST; + output Q0; + output Q1; +endmodule + +(* blackbox *) +module IDDRX2F (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input ECLK; + input RST; + input ALIGNWD; + output Q3; + output Q2; + output Q1; + output Q0; +endmodule + +(* blackbox *) +module IDDR71B (...); + parameter GSR = "ENABLED"; + input D; + input SCLK; + input ECLK; + input RST; + input ALIGNWD; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; +endmodule + +(* blackbox *) +module IDDRX2DQA (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input DQSR90; + input D; + input RST; + input RDPNTR2; + input RDPNTR1; + input RDPNTR0; + input WRPNTR2; + input WRPNTR1; + input WRPNTR0; + output Q3; + output Q2; + output Q1; + output Q0; + output QWL; +endmodule + +(* blackbox *) +module ODDRX1F (...); + parameter GSR = "ENABLED"; + input SCLK; + input RST; + input D0; + input D1; + output Q; +endmodule + +(* blackbox *) +module ODDRX2F (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input RST; + input D3; + input D2; + input D1; + input D0; + output Q; +endmodule + +(* blackbox *) +module ODDR71B (...); + parameter GSR = "ENABLED"; + input SCLK; + input ECLK; + input RST; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + output Q; +endmodule + +(* blackbox *) +module OSHX2A (...); + parameter GSR = "ENABLED"; + input D1; + input D0; + input SCLK; + input ECLK; + input RST; + output Q; +endmodule + +(* blackbox *) +module TSHX2DQA (...); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; + input T1; + input T0; + input SCLK; + input ECLK; + input DQSW270; + input RST; + output Q; +endmodule + +(* blackbox *) +module TSHX2DQSA (...); + parameter GSR = "ENABLED"; + parameter REGSET = "SET"; + input T1; + input T0; + input SCLK; + input ECLK; + input DQSW; + input RST; + output Q; +endmodule + +(* blackbox *) +module ODDRX2DQA (...); + parameter GSR = "ENABLED"; + input D3; + input D2; + input D1; + input D0; + input DQSW270; + input SCLK; + input ECLK; + input RST; + output Q; +endmodule + +(* blackbox *) +module ODDRX2DQSB (...); + parameter GSR = "ENABLED"; + input D3; + input D2; + input D1; + input D0; + input SCLK; + input ECLK; + input DQSW; + input RST; + output Q; +endmodule + +(* blackbox *) +module EHXPLLL (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "DISABLED"; + parameter CLKOS2_ENABLE = "DISABLED"; + parameter CLKOS3_ENABLE = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter OUTDIVIDER_MUXA = "DIVA"; + parameter OUTDIVIDER_MUXB = "DIVB"; + parameter OUTDIVIDER_MUXC = "DIVC"; + parameter OUTDIVIDER_MUXD = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter PLL_LOCK_DELAY = 200; + parameter STDBY_ENABLE = "DISABLED"; + parameter REFIN_RESET = "DISABLED"; + parameter SYNC_ENABLE = "DISABLED"; + parameter INT_LOCK_STICKY = "ENABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input PHASELOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output CLKINTFB; +endmodule + +(* blackbox *) +module DTR (...); + parameter DTR_TEMP = 25; + input STARTPULSE; + output DTROUT7; + output DTROUT6; + output DTROUT5; + output DTROUT4; + output DTROUT3; + output DTROUT2; + output DTROUT1; + output DTROUT0; +endmodule + +(* blackbox *) +module OSCG (...); + parameter DIV = 128; + output OSC; +endmodule + +(* blackbox *) +module EXTREFB (...); + parameter REFCK_PWDNB = "DONTCARE"; + parameter REFCK_RTERM = "DONTCARE"; + parameter REFCK_DCBIAS_EN = "DONTCARE"; + (* iopad_external_pin *) + input REFCLKP; + (* iopad_external_pin *) + input REFCLKN; + output REFCLKO; +endmodule + +(* blackbox *) (* keep *) +module JTAGG (...); + parameter ER1 = "ENABLED"; + parameter ER2 = "ENABLED"; + (* iopad_external_pin *) + input TCK; + (* iopad_external_pin *) + input TMS; + (* iopad_external_pin *) + input TDI; + input JTDO2; + input JTDO1; + (* iopad_external_pin *) + output TDO; + output JTDI; + output JTCK; + output JRTI2; + output JRTI1; + output JSHIFT; + output JUPDATE; + output JRSTN; + output JCE2; + output JCE1; +endmodule + +(* blackbox *) (* keep *) +module DCUA (...); + parameter D_MACROPDB = "DONTCARE"; + parameter D_IB_PWDNB = "DONTCARE"; + parameter D_XGE_MODE = "DONTCARE"; + parameter D_LOW_MARK = "DONTCARE"; + parameter D_HIGH_MARK = "DONTCARE"; + parameter D_BUS8BIT_SEL = "DONTCARE"; + parameter D_CDR_LOL_SET = "DONTCARE"; + parameter D_BITCLK_LOCAL_EN = "DONTCARE"; + parameter D_BITCLK_ND_EN = "DONTCARE"; + parameter D_BITCLK_FROM_ND_EN = "DONTCARE"; + parameter D_SYNC_LOCAL_EN = "DONTCARE"; + parameter D_SYNC_ND_EN = "DONTCARE"; + parameter CH0_UC_MODE = "DONTCARE"; + parameter CH1_UC_MODE = "DONTCARE"; + parameter CH0_PCIE_MODE = "DONTCARE"; + parameter CH1_PCIE_MODE = "DONTCARE"; + parameter CH0_RIO_MODE = "DONTCARE"; + parameter CH1_RIO_MODE = "DONTCARE"; + parameter CH0_WA_MODE = "DONTCARE"; + parameter CH1_WA_MODE = "DONTCARE"; + parameter CH0_INVERT_RX = "DONTCARE"; + parameter CH1_INVERT_RX = "DONTCARE"; + parameter CH0_INVERT_TX = "DONTCARE"; + parameter CH1_INVERT_TX = "DONTCARE"; + parameter CH0_PRBS_SELECTION = "DONTCARE"; + parameter CH1_PRBS_SELECTION = "DONTCARE"; + parameter CH0_GE_AN_ENABLE = "DONTCARE"; + parameter CH1_GE_AN_ENABLE = "DONTCARE"; + parameter CH0_PRBS_LOCK = "DONTCARE"; + parameter CH1_PRBS_LOCK = "DONTCARE"; + parameter CH0_PRBS_ENABLE = "DONTCARE"; + parameter CH1_PRBS_ENABLE = "DONTCARE"; + parameter CH0_ENABLE_CG_ALIGN = "DONTCARE"; + parameter CH1_ENABLE_CG_ALIGN = "DONTCARE"; + parameter CH0_TX_GEAR_MODE = "DONTCARE"; + parameter CH1_TX_GEAR_MODE = "DONTCARE"; + parameter CH0_RX_GEAR_MODE = "DONTCARE"; + parameter CH1_RX_GEAR_MODE = "DONTCARE"; + parameter CH0_PCS_DET_TIME_SEL = "DONTCARE"; + parameter CH1_PCS_DET_TIME_SEL = "DONTCARE"; + parameter CH0_PCIE_EI_EN = "DONTCARE"; + parameter CH1_PCIE_EI_EN = "DONTCARE"; + parameter CH0_TX_GEAR_BYPASS = "DONTCARE"; + parameter CH1_TX_GEAR_BYPASS = "DONTCARE"; + parameter CH0_ENC_BYPASS = "DONTCARE"; + parameter CH1_ENC_BYPASS = "DONTCARE"; + parameter CH0_SB_BYPASS = "DONTCARE"; + parameter CH1_SB_BYPASS = "DONTCARE"; + parameter CH0_RX_SB_BYPASS = "DONTCARE"; + parameter CH1_RX_SB_BYPASS = "DONTCARE"; + parameter CH0_WA_BYPASS = "DONTCARE"; + parameter CH1_WA_BYPASS = "DONTCARE"; + parameter CH0_DEC_BYPASS = "DONTCARE"; + parameter CH1_DEC_BYPASS = "DONTCARE"; + parameter CH0_CTC_BYPASS = "DONTCARE"; + parameter CH1_CTC_BYPASS = "DONTCARE"; + parameter CH0_RX_GEAR_BYPASS = "DONTCARE"; + parameter CH1_RX_GEAR_BYPASS = "DONTCARE"; + parameter CH0_LSM_DISABLE = "DONTCARE"; + parameter CH1_LSM_DISABLE = "DONTCARE"; + parameter CH0_MATCH_2_ENABLE = "DONTCARE"; + parameter CH1_MATCH_2_ENABLE = "DONTCARE"; + parameter CH0_MATCH_4_ENABLE = "DONTCARE"; + parameter CH1_MATCH_4_ENABLE = "DONTCARE"; + parameter CH0_MIN_IPG_CNT = "DONTCARE"; + parameter CH1_MIN_IPG_CNT = "DONTCARE"; + parameter CH0_CC_MATCH_1 = "DONTCARE"; + parameter CH1_CC_MATCH_1 = "DONTCARE"; + parameter CH0_CC_MATCH_2 = "DONTCARE"; + parameter CH1_CC_MATCH_2 = "DONTCARE"; + parameter CH0_CC_MATCH_3 = "DONTCARE"; + parameter CH1_CC_MATCH_3 = "DONTCARE"; + parameter CH0_CC_MATCH_4 = "DONTCARE"; + parameter CH1_CC_MATCH_4 = "DONTCARE"; + parameter CH0_UDF_COMMA_MASK = "DONTCARE"; + parameter CH1_UDF_COMMA_MASK = "DONTCARE"; + parameter CH0_UDF_COMMA_A = "DONTCARE"; + parameter CH1_UDF_COMMA_A = "DONTCARE"; + parameter CH0_UDF_COMMA_B = "DONTCARE"; + parameter CH1_UDF_COMMA_B = "DONTCARE"; + parameter CH0_RX_DCO_CK_DIV = "DONTCARE"; + parameter CH1_RX_DCO_CK_DIV = "DONTCARE"; + parameter CH0_RCV_DCC_EN = "DONTCARE"; + parameter CH1_RCV_DCC_EN = "DONTCARE"; + parameter CH0_REQ_LVL_SET = "DONTCARE"; + parameter CH1_REQ_LVL_SET = "DONTCARE"; + parameter CH0_REQ_EN = "DONTCARE"; + parameter CH1_REQ_EN = "DONTCARE"; + parameter CH0_RTERM_RX = "DONTCARE"; + parameter CH1_RTERM_RX = "DONTCARE"; + parameter CH0_PDEN_SEL = "DONTCARE"; + parameter CH1_PDEN_SEL = "DONTCARE"; + parameter CH0_LDR_RX2CORE_SEL = "DONTCARE"; + parameter CH1_LDR_RX2CORE_SEL = "DONTCARE"; + parameter CH0_LDR_CORE2TX_SEL = "DONTCARE"; + parameter CH1_LDR_CORE2TX_SEL = "DONTCARE"; + parameter CH0_TPWDNB = "DONTCARE"; + parameter CH1_TPWDNB = "DONTCARE"; + parameter CH0_RATE_MODE_TX = "DONTCARE"; + parameter CH1_RATE_MODE_TX = "DONTCARE"; + parameter CH0_RTERM_TX = "DONTCARE"; + parameter CH1_RTERM_TX = "DONTCARE"; + parameter CH0_TX_CM_SEL = "DONTCARE"; + parameter CH1_TX_CM_SEL = "DONTCARE"; + parameter CH0_TDRV_PRE_EN = "DONTCARE"; + parameter CH1_TDRV_PRE_EN = "DONTCARE"; + parameter CH0_TDRV_SLICE0_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE0_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE1_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE1_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE2_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE2_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE3_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE3_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE4_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE4_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE5_SEL = "DONTCARE"; + parameter CH1_TDRV_SLICE5_SEL = "DONTCARE"; + parameter CH0_TDRV_SLICE0_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE0_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE1_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE1_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE2_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE2_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE3_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE3_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE4_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE4_CUR = "DONTCARE"; + parameter CH0_TDRV_SLICE5_CUR = "DONTCARE"; + parameter CH1_TDRV_SLICE5_CUR = "DONTCARE"; + parameter CH0_TDRV_DAT_SEL = "DONTCARE"; + parameter CH1_TDRV_DAT_SEL = "DONTCARE"; + parameter CH0_TX_DIV11_SEL = "DONTCARE"; + parameter CH1_TX_DIV11_SEL = "DONTCARE"; + parameter CH0_RPWDNB = "DONTCARE"; + parameter CH1_RPWDNB = "DONTCARE"; + parameter CH0_RATE_MODE_RX = "DONTCARE"; + parameter CH1_RATE_MODE_RX = "DONTCARE"; + parameter CH0_RLOS_SEL = "DONTCARE"; + parameter CH1_RLOS_SEL = "DONTCARE"; + parameter CH0_RX_LOS_LVL = "DONTCARE"; + parameter CH1_RX_LOS_LVL = "DONTCARE"; + parameter CH0_RX_LOS_CEQ = "DONTCARE"; + parameter CH1_RX_LOS_CEQ = "DONTCARE"; + parameter CH0_RX_LOS_HYST_EN = "DONTCARE"; + parameter CH1_RX_LOS_HYST_EN = "DONTCARE"; + parameter CH0_RX_LOS_EN = "DONTCARE"; + parameter CH1_RX_LOS_EN = "DONTCARE"; + parameter CH0_RX_DIV11_SEL = "DONTCARE"; + parameter CH1_RX_DIV11_SEL = "DONTCARE"; + parameter CH0_SEL_SD_RX_CLK = "DONTCARE"; + parameter CH1_SEL_SD_RX_CLK = "DONTCARE"; + parameter CH0_FF_RX_H_CLK_EN = "DONTCARE"; + parameter CH1_FF_RX_H_CLK_EN = "DONTCARE"; + parameter CH0_FF_RX_F_CLK_DIS = "DONTCARE"; + parameter CH1_FF_RX_F_CLK_DIS = "DONTCARE"; + parameter CH0_FF_TX_H_CLK_EN = "DONTCARE"; + parameter CH1_FF_TX_H_CLK_EN = "DONTCARE"; + parameter CH0_FF_TX_F_CLK_DIS = "DONTCARE"; + parameter CH1_FF_TX_F_CLK_DIS = "DONTCARE"; + parameter CH0_RX_RATE_SEL = "DONTCARE"; + parameter CH1_RX_RATE_SEL = "DONTCARE"; + parameter CH0_TDRV_POST_EN = "DONTCARE"; + parameter CH1_TDRV_POST_EN = "DONTCARE"; + parameter CH0_TX_POST_SIGN = "DONTCARE"; + parameter CH1_TX_POST_SIGN = "DONTCARE"; + parameter CH0_TX_PRE_SIGN = "DONTCARE"; + parameter CH1_TX_PRE_SIGN = "DONTCARE"; + parameter CH0_RXTERM_CM = "DONTCARE"; + parameter CH1_RXTERM_CM = "DONTCARE"; + parameter CH0_RXIN_CM = "DONTCARE"; + parameter CH1_RXIN_CM = "DONTCARE"; + parameter CH0_LEQ_OFFSET_SEL = "DONTCARE"; + parameter CH1_LEQ_OFFSET_SEL = "DONTCARE"; + parameter CH0_LEQ_OFFSET_TRIM = "DONTCARE"; + parameter CH1_LEQ_OFFSET_TRIM = "DONTCARE"; + parameter D_TX_MAX_RATE = "DONTCARE"; + parameter CH0_CDR_MAX_RATE = "DONTCARE"; + parameter CH1_CDR_MAX_RATE = "DONTCARE"; + parameter CH0_TXAMPLITUDE = "DONTCARE"; + parameter CH1_TXAMPLITUDE = "DONTCARE"; + parameter CH0_TXDEPRE = "DONTCARE"; + parameter CH1_TXDEPRE = "DONTCARE"; + parameter CH0_TXDEPOST = "DONTCARE"; + parameter CH1_TXDEPOST = "DONTCARE"; + parameter CH0_PROTOCOL = "DONTCARE"; + parameter CH1_PROTOCOL = "DONTCARE"; + parameter D_ISETLOS = "DONTCARE"; + parameter D_SETIRPOLY_AUX = "DONTCARE"; + parameter D_SETICONST_AUX = "DONTCARE"; + parameter D_SETIRPOLY_CH = "DONTCARE"; + parameter D_SETICONST_CH = "DONTCARE"; + parameter D_REQ_ISET = "DONTCARE"; + parameter D_PD_ISET = "DONTCARE"; + parameter D_DCO_CALIB_TIME_SEL = "DONTCARE"; + parameter CH0_DCOCTLGI = "DONTCARE"; + parameter CH1_DCOCTLGI = "DONTCARE"; + parameter CH0_DCOATDDLY = "DONTCARE"; + parameter CH1_DCOATDDLY = "DONTCARE"; + parameter CH0_DCOATDCFG = "DONTCARE"; + parameter CH1_DCOATDCFG = "DONTCARE"; + parameter CH0_DCOBYPSATD = "DONTCARE"; + parameter CH1_DCOBYPSATD = "DONTCARE"; + parameter CH0_DCOSCALEI = "DONTCARE"; + parameter CH1_DCOSCALEI = "DONTCARE"; + parameter CH0_DCOITUNE4LSB = "DONTCARE"; + parameter CH1_DCOITUNE4LSB = "DONTCARE"; + parameter CH0_DCOIOSTUNE = "DONTCARE"; + parameter CH1_DCOIOSTUNE = "DONTCARE"; + parameter CH0_DCODISBDAVOID = "DONTCARE"; + parameter CH1_DCODISBDAVOID = "DONTCARE"; + parameter CH0_DCOCALDIV = "DONTCARE"; + parameter CH1_DCOCALDIV = "DONTCARE"; + parameter CH0_DCONUOFLSB = "DONTCARE"; + parameter CH1_DCONUOFLSB = "DONTCARE"; + parameter CH0_DCOIUPDNX2 = "DONTCARE"; + parameter CH1_DCOIUPDNX2 = "DONTCARE"; + parameter CH0_DCOSTEP = "DONTCARE"; + parameter CH1_DCOSTEP = "DONTCARE"; + parameter CH0_DCOSTARTVAL = "DONTCARE"; + parameter CH1_DCOSTARTVAL = "DONTCARE"; + parameter CH0_DCOFLTDAC = "DONTCARE"; + parameter CH1_DCOFLTDAC = "DONTCARE"; + parameter CH0_DCOITUNE = "DONTCARE"; + parameter CH1_DCOITUNE = "DONTCARE"; + parameter CH0_DCOFTNRG = "DONTCARE"; + parameter CH1_DCOFTNRG = "DONTCARE"; + parameter CH0_CDR_CNT4SEL = "DONTCARE"; + parameter CH1_CDR_CNT4SEL = "DONTCARE"; + parameter CH0_CDR_CNT8SEL = "DONTCARE"; + parameter CH1_CDR_CNT8SEL = "DONTCARE"; + parameter CH0_BAND_THRESHOLD = "DONTCARE"; + parameter CH1_BAND_THRESHOLD = "DONTCARE"; + parameter CH0_AUTO_FACQ_EN = "DONTCARE"; + parameter CH1_AUTO_FACQ_EN = "DONTCARE"; + parameter CH0_AUTO_CALIB_EN = "DONTCARE"; + parameter CH1_AUTO_CALIB_EN = "DONTCARE"; + parameter CH0_CALIB_CK_MODE = "DONTCARE"; + parameter CH1_CALIB_CK_MODE = "DONTCARE"; + parameter CH0_REG_BAND_OFFSET = "DONTCARE"; + parameter CH1_REG_BAND_OFFSET = "DONTCARE"; + parameter CH0_REG_BAND_SEL = "DONTCARE"; + parameter CH1_REG_BAND_SEL = "DONTCARE"; + parameter CH0_REG_IDAC_SEL = "DONTCARE"; + parameter CH1_REG_IDAC_SEL = "DONTCARE"; + parameter CH0_REG_IDAC_EN = "DONTCARE"; + parameter CH1_REG_IDAC_EN = "DONTCARE"; + parameter D_TXPLL_PWDNB = "DONTCARE"; + parameter D_SETPLLRC = "DONTCARE"; + parameter D_REFCK_MODE = "DONTCARE"; + parameter D_TX_VCO_CK_DIV = "DONTCARE"; + parameter D_PLL_LOL_SET = "DONTCARE"; + parameter D_RG_EN = "DONTCARE"; + parameter D_RG_SET = "DONTCARE"; + parameter D_CMUSETISCL4VCO = "DONTCARE"; + parameter D_CMUSETI4VCO = "DONTCARE"; + parameter D_CMUSETINITVCT = "DONTCARE"; + parameter D_CMUSETZGM = "DONTCARE"; + parameter D_CMUSETP2AGM = "DONTCARE"; + parameter D_CMUSETP1GM = "DONTCARE"; + parameter D_CMUSETI4CPZ = "DONTCARE"; + parameter D_CMUSETI4CPP = "DONTCARE"; + parameter D_CMUSETICP4Z = "DONTCARE"; + parameter D_CMUSETICP4P = "DONTCARE"; + parameter D_CMUSETBIASI = "DONTCARE"; + (* iopad_external_pin *) + (* iopad_external_pin *) + input CH0_HDINP; + (* iopad_external_pin *) + input CH1_HDINP; + (* iopad_external_pin *) + input CH0_HDINN; + (* iopad_external_pin *) + input CH1_HDINN; + input D_TXBIT_CLKP_FROM_ND; + input D_TXBIT_CLKN_FROM_ND; + input D_SYNC_ND; + input D_TXPLL_LOL_FROM_ND; + input CH0_RX_REFCLK; + input CH1_RX_REFCLK; + input CH0_FF_RXI_CLK; + input CH1_FF_RXI_CLK; + input CH0_FF_TXI_CLK; + input CH1_FF_TXI_CLK; + input CH0_FF_EBRD_CLK; + input CH1_FF_EBRD_CLK; + input CH0_FF_TX_D_0; + input CH1_FF_TX_D_0; + input CH0_FF_TX_D_1; + input CH1_FF_TX_D_1; + input CH0_FF_TX_D_2; + input CH1_FF_TX_D_2; + input CH0_FF_TX_D_3; + input CH1_FF_TX_D_3; + input CH0_FF_TX_D_4; + input CH1_FF_TX_D_4; + input CH0_FF_TX_D_5; + input CH1_FF_TX_D_5; + input CH0_FF_TX_D_6; + input CH1_FF_TX_D_6; + input CH0_FF_TX_D_7; + input CH1_FF_TX_D_7; + input CH0_FF_TX_D_8; + input CH1_FF_TX_D_8; + input CH0_FF_TX_D_9; + input CH1_FF_TX_D_9; + input CH0_FF_TX_D_10; + input CH1_FF_TX_D_10; + input CH0_FF_TX_D_11; + input CH1_FF_TX_D_11; + input CH0_FF_TX_D_12; + input CH1_FF_TX_D_12; + input CH0_FF_TX_D_13; + input CH1_FF_TX_D_13; + input CH0_FF_TX_D_14; + input CH1_FF_TX_D_14; + input CH0_FF_TX_D_15; + input CH1_FF_TX_D_15; + input CH0_FF_TX_D_16; + input CH1_FF_TX_D_16; + input CH0_FF_TX_D_17; + input CH1_FF_TX_D_17; + input CH0_FF_TX_D_18; + input CH1_FF_TX_D_18; + input CH0_FF_TX_D_19; + input CH1_FF_TX_D_19; + input CH0_FF_TX_D_20; + input CH1_FF_TX_D_20; + input CH0_FF_TX_D_21; + input CH1_FF_TX_D_21; + input CH0_FF_TX_D_22; + input CH1_FF_TX_D_22; + input CH0_FF_TX_D_23; + input CH1_FF_TX_D_23; + input CH0_FFC_EI_EN; + input CH1_FFC_EI_EN; + input CH0_FFC_PCIE_DET_EN; + input CH1_FFC_PCIE_DET_EN; + input CH0_FFC_PCIE_CT; + input CH1_FFC_PCIE_CT; + input CH0_FFC_SB_INV_RX; + input CH1_FFC_SB_INV_RX; + input CH0_FFC_ENABLE_CGALIGN; + input CH1_FFC_ENABLE_CGALIGN; + input CH0_FFC_SIGNAL_DETECT; + input CH1_FFC_SIGNAL_DETECT; + input CH0_FFC_FB_LOOPBACK; + input CH1_FFC_FB_LOOPBACK; + input CH0_FFC_SB_PFIFO_LP; + input CH1_FFC_SB_PFIFO_LP; + input CH0_FFC_PFIFO_CLR; + input CH1_FFC_PFIFO_CLR; + input CH0_FFC_RATE_MODE_RX; + input CH1_FFC_RATE_MODE_RX; + input CH0_FFC_RATE_MODE_TX; + input CH1_FFC_RATE_MODE_TX; + input CH0_FFC_DIV11_MODE_RX; + input CH1_FFC_DIV11_MODE_RX; + input CH0_FFC_RX_GEAR_MODE; + input CH1_FFC_RX_GEAR_MODE; + input CH0_FFC_TX_GEAR_MODE; + input CH1_FFC_TX_GEAR_MODE; + input CH0_FFC_DIV11_MODE_TX; + input CH1_FFC_DIV11_MODE_TX; + input CH0_FFC_LDR_CORE2TX_EN; + input CH1_FFC_LDR_CORE2TX_EN; + input CH0_FFC_LANE_TX_RST; + input CH1_FFC_LANE_TX_RST; + input CH0_FFC_LANE_RX_RST; + input CH1_FFC_LANE_RX_RST; + input CH0_FFC_RRST; + input CH1_FFC_RRST; + input CH0_FFC_TXPWDNB; + input CH1_FFC_TXPWDNB; + input CH0_FFC_RXPWDNB; + input CH1_FFC_RXPWDNB; + input CH0_LDR_CORE2TX; + input CH1_LDR_CORE2TX; + input D_SCIWDATA0; + input D_SCIWDATA1; + input D_SCIWDATA2; + input D_SCIWDATA3; + input D_SCIWDATA4; + input D_SCIWDATA5; + input D_SCIWDATA6; + input D_SCIWDATA7; + input D_SCIADDR0; + input D_SCIADDR1; + input D_SCIADDR2; + input D_SCIADDR3; + input D_SCIADDR4; + input D_SCIADDR5; + input D_SCIENAUX; + input D_SCISELAUX; + input CH0_SCIEN; + input CH1_SCIEN; + input CH0_SCISEL; + input CH1_SCISEL; + input D_SCIRD; + input D_SCIWSTN; + input D_CYAWSTN; + input D_FFC_SYNC_TOGGLE; + input D_FFC_DUAL_RST; + input D_FFC_MACRO_RST; + input D_FFC_MACROPDB; + input D_FFC_TRST; + input CH0_FFC_CDR_EN_BITSLIP; + input CH1_FFC_CDR_EN_BITSLIP; + input D_SCAN_ENABLE; + input D_SCAN_IN_0; + input D_SCAN_IN_1; + input D_SCAN_IN_2; + input D_SCAN_IN_3; + input D_SCAN_IN_4; + input D_SCAN_IN_5; + input D_SCAN_IN_6; + input D_SCAN_IN_7; + input D_SCAN_MODE; + input D_SCAN_RESET; + input D_CIN0; + input D_CIN1; + input D_CIN2; + input D_CIN3; + input D_CIN4; + input D_CIN5; + input D_CIN6; + input D_CIN7; + input D_CIN8; + input D_CIN9; + input D_CIN10; + input D_CIN11; + output CH0_HDOUTP; + output CH1_HDOUTP; + output CH0_HDOUTN; + output CH1_HDOUTN; + output D_TXBIT_CLKP_TO_ND; + output D_TXBIT_CLKN_TO_ND; + output D_SYNC_PULSE2ND; + output D_TXPLL_LOL_TO_ND; + output CH0_FF_RX_F_CLK; + output CH1_FF_RX_F_CLK; + output CH0_FF_RX_H_CLK; + output CH1_FF_RX_H_CLK; + output CH0_FF_TX_F_CLK; + output CH1_FF_TX_F_CLK; + output CH0_FF_TX_H_CLK; + output CH1_FF_TX_H_CLK; + output CH0_FF_RX_PCLK; + output CH1_FF_RX_PCLK; + output CH0_FF_TX_PCLK; + output CH1_FF_TX_PCLK; + output CH0_FF_RX_D_0; + output CH1_FF_RX_D_0; + output CH0_FF_RX_D_1; + output CH1_FF_RX_D_1; + output CH0_FF_RX_D_2; + output CH1_FF_RX_D_2; + output CH0_FF_RX_D_3; + output CH1_FF_RX_D_3; + output CH0_FF_RX_D_4; + output CH1_FF_RX_D_4; + output CH0_FF_RX_D_5; + output CH1_FF_RX_D_5; + output CH0_FF_RX_D_6; + output CH1_FF_RX_D_6; + output CH0_FF_RX_D_7; + output CH1_FF_RX_D_7; + output CH0_FF_RX_D_8; + output CH1_FF_RX_D_8; + output CH0_FF_RX_D_9; + output CH1_FF_RX_D_9; + output CH0_FF_RX_D_10; + output CH1_FF_RX_D_10; + output CH0_FF_RX_D_11; + output CH1_FF_RX_D_11; + output CH0_FF_RX_D_12; + output CH1_FF_RX_D_12; + output CH0_FF_RX_D_13; + output CH1_FF_RX_D_13; + output CH0_FF_RX_D_14; + output CH1_FF_RX_D_14; + output CH0_FF_RX_D_15; + output CH1_FF_RX_D_15; + output CH0_FF_RX_D_16; + output CH1_FF_RX_D_16; + output CH0_FF_RX_D_17; + output CH1_FF_RX_D_17; + output CH0_FF_RX_D_18; + output CH1_FF_RX_D_18; + output CH0_FF_RX_D_19; + output CH1_FF_RX_D_19; + output CH0_FF_RX_D_20; + output CH1_FF_RX_D_20; + output CH0_FF_RX_D_21; + output CH1_FF_RX_D_21; + output CH0_FF_RX_D_22; + output CH1_FF_RX_D_22; + output CH0_FF_RX_D_23; + output CH1_FF_RX_D_23; + output CH0_FFS_PCIE_DONE; + output CH1_FFS_PCIE_DONE; + output CH0_FFS_PCIE_CON; + output CH1_FFS_PCIE_CON; + output CH0_FFS_RLOS; + output CH1_FFS_RLOS; + output CH0_FFS_LS_SYNC_STATUS; + output CH1_FFS_LS_SYNC_STATUS; + output CH0_FFS_CC_UNDERRUN; + output CH1_FFS_CC_UNDERRUN; + output CH0_FFS_CC_OVERRUN; + output CH1_FFS_CC_OVERRUN; + output CH0_FFS_RXFBFIFO_ERROR; + output CH1_FFS_RXFBFIFO_ERROR; + output CH0_FFS_TXFBFIFO_ERROR; + output CH1_FFS_TXFBFIFO_ERROR; + output CH0_FFS_RLOL; + output CH1_FFS_RLOL; + output CH0_FFS_SKP_ADDED; + output CH1_FFS_SKP_ADDED; + output CH0_FFS_SKP_DELETED; + output CH1_FFS_SKP_DELETED; + output CH0_LDR_RX2CORE; + output CH1_LDR_RX2CORE; + output D_SCIRDATA0; + output D_SCIRDATA1; + output D_SCIRDATA2; + output D_SCIRDATA3; + output D_SCIRDATA4; + output D_SCIRDATA5; + output D_SCIRDATA6; + output D_SCIRDATA7; + output D_SCIINT; + output D_SCAN_OUT_0; + output D_SCAN_OUT_1; + output D_SCAN_OUT_2; + output D_SCAN_OUT_3; + output D_SCAN_OUT_4; + output D_SCAN_OUT_5; + output D_SCAN_OUT_6; + output D_SCAN_OUT_7; + output D_COUT0; + output D_COUT1; + output D_COUT2; + output D_COUT3; + output D_COUT4; + output D_COUT5; + output D_COUT6; + output D_COUT7; + output D_COUT8; + output D_COUT9; + output D_COUT10; + output D_COUT11; + output D_COUT12; + output D_COUT13; + output D_COUT14; + output D_COUT15; + output D_COUT16; + output D_COUT17; + output D_COUT18; + output D_COUT19; + input D_REFCLKI; + output D_FFS_PLOL; +endmodule + diff --git a/yosys/techlibs/lattice/cells_bb_xo2.v b/yosys/techlibs/lattice/cells_bb_xo2.v new file mode 100644 index 00000000000..fdf8331b731 --- /dev/null +++ b/yosys/techlibs/lattice/cells_bb_xo2.v @@ -0,0 +1,571 @@ +// Created by cells_xtra.py from Lattice models + +(* blackbox *) (* keep *) +module GSR (...); + input GSR; +endmodule + +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; +endmodule + +(* blackbox *) +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; +endmodule + +(* blackbox *) +module PDPW8KC (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module SP8KC (...); + parameter DATA_WIDTH = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE = "0b000"; + parameter WRITEMODE = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module FIFO8KB (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + parameter REGMODE = "NOREG"; + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; +endmodule + +(* blackbox *) +module OSCH (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; +endmodule + +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/yosys/techlibs/lattice/cells_bb_xo3.v b/yosys/techlibs/lattice/cells_bb_xo3.v new file mode 100644 index 00000000000..fdf8331b731 --- /dev/null +++ b/yosys/techlibs/lattice/cells_bb_xo3.v @@ -0,0 +1,571 @@ +// Created by cells_xtra.py from Lattice models + +(* blackbox *) (* keep *) +module GSR (...); + input GSR; +endmodule + +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; +endmodule + +(* blackbox *) +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; +endmodule + +(* blackbox *) +module PDPW8KC (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module SP8KC (...); + parameter DATA_WIDTH = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE = "0b000"; + parameter WRITEMODE = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module FIFO8KB (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + parameter REGMODE = "NOREG"; + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; +endmodule + +(* blackbox *) +module OSCH (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; +endmodule + +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/yosys/techlibs/lattice/cells_bb_xo3d.v b/yosys/techlibs/lattice/cells_bb_xo3d.v new file mode 100644 index 00000000000..84d7d960198 --- /dev/null +++ b/yosys/techlibs/lattice/cells_bb_xo3d.v @@ -0,0 +1,572 @@ +// Created by cells_xtra.py from Lattice models + +(* blackbox *) (* keep *) +module GSR (...); + input GSR; +endmodule + +(* blackbox *) (* keep *) +module SGSR (...); + input GSR; + input CLK; +endmodule + +(* blackbox *) +module DP8KC (...); + parameter DATA_WIDTH_A = 9; + parameter DATA_WIDTH_B = 9; + parameter REGMODE_A = "NOREG"; + parameter REGMODE_B = "NOREG"; + parameter CSDECODE_A = "0b000"; + parameter CSDECODE_B = "0b000"; + parameter WRITEMODE_A = "NORMAL"; + parameter WRITEMODE_B = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DIA8; + input DIA7; + input DIA6; + input DIA5; + input DIA4; + input DIA3; + input DIA2; + input DIA1; + input DIA0; + input ADA12; + input ADA11; + input ADA10; + input ADA9; + input ADA8; + input ADA7; + input ADA6; + input ADA5; + input ADA4; + input ADA3; + input ADA2; + input ADA1; + input ADA0; + input CEA; + input OCEA; + input CLKA; + input WEA; + input CSA2; + input CSA1; + input CSA0; + input RSTA; + input DIB8; + input DIB7; + input DIB6; + input DIB5; + input DIB4; + input DIB3; + input DIB2; + input DIB1; + input DIB0; + input ADB12; + input ADB11; + input ADB10; + input ADB9; + input ADB8; + input ADB7; + input ADB6; + input ADB5; + input ADB4; + input ADB3; + input ADB2; + input ADB1; + input ADB0; + input CEB; + input OCEB; + input CLKB; + input WEB; + input CSB2; + input CSB1; + input CSB0; + input RSTB; + output DOA8; + output DOA7; + output DOA6; + output DOA5; + output DOA4; + output DOA3; + output DOA2; + output DOA1; + output DOA0; + output DOB8; + output DOB7; + output DOB6; + output DOB5; + output DOB4; + output DOB3; + output DOB2; + output DOB1; + output DOB0; +endmodule + +(* blackbox *) +module PDPW8KC (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI17; + input DI16; + input DI15; + input DI14; + input DI13; + input DI12; + input DI11; + input DI10; + input DI9; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input ADW8; + input ADW7; + input ADW6; + input ADW5; + input ADW4; + input ADW3; + input ADW2; + input ADW1; + input ADW0; + input BE1; + input BE0; + input CEW; + input CLKW; + input CSW2; + input CSW1; + input CSW0; + input ADR12; + input ADR11; + input ADR10; + input ADR9; + input ADR8; + input ADR7; + input ADR6; + input ADR5; + input ADR4; + input ADR3; + input ADR2; + input ADR1; + input ADR0; + input CER; + input OCER; + input CLKR; + input CSR2; + input CSR1; + input CSR0; + input RST; + output DO17; + output DO16; + output DO15; + output DO14; + output DO13; + output DO12; + output DO11; + output DO10; + output DO9; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module SP8KC (...); + parameter DATA_WIDTH = 9; + parameter REGMODE = "NOREG"; + parameter CSDECODE = "0b000"; + parameter WRITEMODE = "NORMAL"; + parameter GSR = "ENABLED"; + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter INIT_DATA = "STATIC"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + input DI8; + input DI7; + input DI6; + input DI5; + input DI4; + input DI3; + input DI2; + input DI1; + input DI0; + input AD12; + input AD11; + input AD10; + input AD9; + input AD8; + input AD7; + input AD6; + input AD5; + input AD4; + input AD3; + input AD2; + input AD1; + input AD0; + input CE; + input OCE; + input CLK; + input WE; + input CS2; + input CS1; + input CS0; + input RST; + output DO8; + output DO7; + output DO6; + output DO5; + output DO4; + output DO3; + output DO2; + output DO1; + output DO0; +endmodule + +(* blackbox *) +module FIFO8KB (...); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + parameter REGMODE = "NOREG"; + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; + parameter GSR = "DISABLED"; + input DI0; + input DI1; + input DI2; + input DI3; + input DI4; + input DI5; + input DI6; + input DI7; + input DI8; + input DI9; + input DI10; + input DI11; + input DI12; + input DI13; + input DI14; + input DI15; + input DI16; + input DI17; + input CSW0; + input CSW1; + input CSR0; + input CSR1; + input WE; + input RE; + input ORE; + input CLKW; + input CLKR; + input RST; + input RPRST; + input FULLI; + input EMPTYI; + output DO0; + output DO1; + output DO2; + output DO3; + output DO4; + output DO5; + output DO6; + output DO7; + output DO8; + output DO9; + output DO10; + output DO11; + output DO12; + output DO13; + output DO14; + output DO15; + output DO16; + output DO17; + output EF; + output AEF; + output AFF; + output FF; +endmodule + +(* blackbox *) +module CLKDIVC (...); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; + input RST; + input CLKI; + input ALIGNWD; + output CDIV1; + output CDIVX; +endmodule + +(* blackbox *) +module DCMA (...); + input CLK0; + input CLK1; + input SEL; + output DCMOUT; +endmodule + +(* blackbox *) +module ECLKSYNCA (...); + input ECLKI; + input STOP; + output ECLKO; +endmodule + +(* blackbox *) +module ECLKBRIDGECS (...); + input CLK0; + input CLK1; + input SEL; + output ECSOUT; +endmodule + +(* blackbox *) +module DCCA (...); + input CLKI; + input CE; + output CLKO; +endmodule + +(* blackbox *) (* keep *) +module START (...); + input STARTCLK; +endmodule + +(* blackbox *) +module EHXPLLJ (...); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; + input CLKI; + input CLKFB; + input PHASESEL1; + input PHASESEL0; + input PHASEDIR; + input PHASESTEP; + input LOADREG; + input STDBY; + input PLLWAKESYNC; + input RST; + input RESETM; + input RESETC; + input RESETD; + input ENCLKOP; + input ENCLKOS; + input ENCLKOS2; + input ENCLKOS3; + input PLLCLK; + input PLLRST; + input PLLSTB; + input PLLWE; + input PLLDATI7; + input PLLDATI6; + input PLLDATI5; + input PLLDATI4; + input PLLDATI3; + input PLLDATI2; + input PLLDATI1; + input PLLDATI0; + input PLLADDR4; + input PLLADDR3; + input PLLADDR2; + input PLLADDR1; + input PLLADDR0; + output CLKOP; + output CLKOS; + output CLKOS2; + output CLKOS3; + output LOCK; + output INTLOCK; + output REFCLK; + output PLLDATO7; + output PLLDATO6; + output PLLDATO5; + output PLLDATO4; + output PLLDATO3; + output PLLDATO2; + output PLLDATO1; + output PLLDATO0; + output PLLACK; + output DPHSRC; + output CLKINTFB; +endmodule + +(* blackbox *) +module OSCJ (...); + parameter NOM_FREQ = "2.08"; + input STDBY; + output OSC; + output SEDSTDBY; + output OSCESB; +endmodule + +(* blackbox *) (* keep *) +module TSALL (...); + input TSALL; +endmodule + diff --git a/yosys/techlibs/lattice/cells_ff.vh b/yosys/techlibs/lattice/cells_ff.vh new file mode 100644 index 00000000000..6b745f391ee --- /dev/null +++ b/yosys/techlibs/lattice/cells_ff.vh @@ -0,0 +1,40 @@ +// Diamond flip-flops +module FD1P3AX(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3AY(input D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3BX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3DX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3IX(input CD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1P3JX(input PD, D, SP, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module FD1S3AX(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule +module FD1S3AY(input D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(|0), .DI(D), .Q(Q)); endmodule +module FD1S3BX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule +module FD1S3DX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3IX(input CD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(CD), .DI(D), .Q(Q)); endmodule +module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond latches +// module FL1P3AY(); endmodule +// module FL1P3AZ(); endmodule +// module FL1P3BX(); endmodule +// module FL1P3DX(); endmodule +// module FL1P3IY(); endmodule +// module FL1P3JY(); endmodule +// module FL1S3AX(); endmodule +// module FL1S3AY(); endmodule + +// Diamond I/O registers +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule + +// TODO: Diamond I/O latches +// module IFS1S1B(input PD, D, SCLK, output Q); endmodule +// module IFS1S1D(input CD, D, SCLK, output Q); endmodule +// module IFS1S1I(input PD, D, SCLK, output Q); endmodule +// module IFS1S1J(input CD, D, SCLK, output Q); endmodule diff --git a/yosys/techlibs/lattice/cells_io.vh b/yosys/techlibs/lattice/cells_io.vh new file mode 100644 index 00000000000..220460c4467 --- /dev/null +++ b/yosys/techlibs/lattice/cells_io.vh @@ -0,0 +1,14 @@ +// Diamond I/O buffers +module IB ((* iopad_external_pin *) input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module OB (input I, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule +module OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule +module BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule +module OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule diff --git a/yosys/techlibs/machxo2/cells_map.v b/yosys/techlibs/lattice/cells_map.v similarity index 64% rename from yosys/techlibs/machxo2/cells_map.v rename to yosys/techlibs/lattice/cells_map.v index 22994a634df..4944ece4569 100644 --- a/yosys/techlibs/machxo2/cells_map.v +++ b/yosys/techlibs/lattice/cells_map.v @@ -88,30 +88,104 @@ module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - input [WIDTH-1:0] A; - output Y; - - localparam rep = 1<<(4-WIDTH); - wire [3:0] I; - - generate - if(WIDTH == 1) begin - assign I = {1'b0, 1'b0, 1'b0, A[0]}; - end else if(WIDTH == 2) begin - assign I = {1'b0, 1'b0, A[1], A[0]}; - end else if(WIDTH == 3) begin - assign I = {1'b0, A[2], A[1], A[0]}; - end else if(WIDTH == 4) begin - assign I = {A[3], A[2], A[1], A[0]}; - end else begin - wire _TECHMAP_FAIL_ = 1; - end - endgenerate - - LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y)); -endmodule +module \$_ALDFF_NP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFF_PP_ (input C, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_NPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_NPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_PPN_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule +module \$_ALDFFE_PPP_ (input C, E, L, AD, D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(L), .DI(D), .M(AD), .Q(Q)); endmodule + +`include "cells_ff.vh" `include "cells_io.vh" + +`ifndef NO_LUT +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(1'b0), .C(1'b0), .D(A[0])); + end else + if (WIDTH == 2) begin + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(1'b0), .C(A[0]), .D(A[1])); + end else + if (WIDTH == 3) begin + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + LUT4 #(.INIT(INIT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(1'b0), .B(A[0]), .C(A[1]), .D(A[2])); + end else + if (WIDTH == 4) begin + LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + `ifndef NO_PFUMUX + end else + if (WIDTH == 5) begin + wire f0, f1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y)); + end else + if (WIDTH == 6) begin + wire f0, f1, f2, f3, g0, g1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y)); + end else + if (WIDTH == 7) begin + wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1; + LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7), + .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + + PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0)); + PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1)); + PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2)); + PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3)); + L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0)); + L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1)); + L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y)); + `endif + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule +`endif diff --git a/yosys/techlibs/lattice/cells_sim_ecp5.v b/yosys/techlibs/lattice/cells_sim_ecp5.v new file mode 100644 index 00000000000..9439e3a5b31 --- /dev/null +++ b/yosys/techlibs/lattice/cells_sim_ecp5.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2c_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/lattice/cells_sim_xo2.v b/yosys/techlibs/lattice/cells_sim_xo2.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/yosys/techlibs/lattice/cells_sim_xo2.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/lattice/cells_sim_xo3.v b/yosys/techlibs/lattice/cells_sim_xo3.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/yosys/techlibs/lattice/cells_sim_xo3.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/lattice/cells_sim_xo3d.v b/yosys/techlibs/lattice/cells_sim_xo3d.v new file mode 100644 index 00000000000..54414287572 --- /dev/null +++ b/yosys/techlibs/lattice/cells_sim_xo3d.v @@ -0,0 +1,9 @@ +`include "common_sim.vh" +`include "ccu2d_sim.vh" + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/lattice/cells_xtra.py b/yosys/techlibs/lattice/cells_xtra.py new file mode 100644 index 00000000000..c17281cc753 --- /dev/null +++ b/yosys/techlibs/lattice/cells_xtra.py @@ -0,0 +1,856 @@ +#!/usr/bin/env python3 + +# Based on Xilinx cells_xtra.py; modified for Lattice's structure + +from argparse import ArgumentParser +from io import StringIO +from enum import Enum, auto +import os.path +import sys +import re + + +class Cell: + def __init__(self, name, keep=False, port_attrs={}): + self.name = name + self.keep = keep + self.port_attrs = port_attrs + self.found = False + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_OTHER_MODULE = auto() + IN_FUNCTION = auto() + IN_TASK = auto() + +devices = [ + ("cells_bb_ecp5.v", "ecp5u", [ + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("CCU2C"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("PFUMX"), + Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + Cell("SGSR", True), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + Cell("DP16KD"), + Cell("PDPW16KD"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + #Cell("LVDSOB"), + #Cell("IMIPI"), + #Cell("MULT9X9C"), + #Cell("MULT9X9D"), + #Cell("MULT18X18C"), + Cell("MULT18X18D"), + #Cell("ALU24A"), + #Cell("ALU54A"), + #Cell("ALU24B"), + Cell("ALU54B"), + #Cell("PRADD9A"), + #Cell("PRADD18A"), + #Cell("BCINRD"), + #Cell("BCLVDSOB"), + #Cell("INRDB"), + Cell("CLKDIVF"), + Cell("PCSCLKDIV"), + Cell("DCSC"), + Cell("DCCA"), + Cell("ECLKSYNCB"), + Cell("ECLKBRIDGECS"), + #Cell("PLLREFCS"), + Cell("DELAYF"), + Cell("DELAYG"), + #Cell("START"), + Cell("USRMCLK", True), + Cell("DQSBUFM"), + Cell("DDRDLLA"), + Cell("DLLDELD"), + Cell("IDDRX1F"), + Cell("IDDRX2F"), + Cell("IDDR71B"), + Cell("IDDRX2DQA"), + Cell("ODDRX1F"), + Cell("ODDRX2F"), + Cell("ODDR71B"), + Cell("OSHX2A"), + Cell("TSHX2DQA"), + Cell("TSHX2DQSA"), + Cell("ODDRX2DQA"), + Cell("ODDRX2DQSB"), + Cell("EHXPLLL"), + Cell("DTR"), + Cell("OSCG"), + Cell("EXTREFB"), + Cell("JTAGG", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + #Cell("SEDGA"), + Cell("DCUA", True, port_attrs={'CH0_HDINP': ['iopad_external_pin'], 'CH1_HDINP': ['iopad_external_pin'], 'CH0_HDINN': ['iopad_external_pin'], 'CH1_HDINN': ['iopad_external_pin']}), + ]), + ("cells_bb_xo2.v", "machxo2", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + Cell("CLKDIVC"), + Cell("DCMA"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRDQSX1A"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRDQSX1A"), + #Cell("ODDRX71A"), + #Cell("TDDRA"), + #Cell("DQSBUFH"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCH"), + #Cell("EFB"), + Cell("TSALL", True), + ]), + ("cells_bb_xo3.v", "machxo3lf", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + Cell("CLKDIVC"), + Cell("DCMA"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRX71A"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCH"), + #Cell("EFB"), + Cell("TSALL", True), + ]), + ("cells_bb_xo3d.v", "machxo3d", [ + #Cell("AGEB2"), + #Cell("ALEB2"), + #Cell("AND2"), + #Cell("AND3"), + #Cell("AND4"), + #Cell("AND5"), + #Cell("ANEB2"), + #Cell("BB"), + #Cell("BBPD"), + #Cell("BBPU"), + #Cell("BBI3C"), + #Cell("BBW"), + #Cell("CB2"), + #Cell("CD2"), + #Cell("CU2"), + #Cell("FADD2B"), + #Cell("FADSU2"), + #Cell("FD1P3AX"), + #Cell("FD1P3AY"), + #Cell("FD1P3BX"), + #Cell("FD1P3DX"), + #Cell("FD1P3IX"), + #Cell("FD1P3JX"), + #Cell("FD1S1A"), + #Cell("FD1S1AY"), + #Cell("FD1S1B"), + #Cell("FD1S1D"), + #Cell("FD1S1I"), + #Cell("FD1S1J"), + #Cell("FD1S3AX"), + #Cell("FD1S3AY"), + #Cell("FD1S3BX"), + #Cell("FD1S3DX"), + #Cell("FD1S3IX"), + #Cell("FD1S3JX"), + #Cell("FL1P3AY"), + #Cell("FL1P3AZ"), + #Cell("FL1P3BX"), + #Cell("FL1P3DX"), + #Cell("FL1P3IY"), + #Cell("FL1P3JY"), + #Cell("FL1S1A"), + #Cell("FL1S1AY"), + #Cell("FL1S1B"), + #Cell("FL1S1D"), + #Cell("FL1S1I"), + #Cell("FL1S1J"), + #Cell("FL1S3AX"), + #Cell("FL1S3AY"), + #Cell("FSUB2B"), + Cell("GSR", True), + #Cell("IB"), + #Cell("IBPD"), + #Cell("IBPU"), + #Cell("IFS1P3BX"), + #Cell("IFS1P3DX"), + #Cell("IFS1P3IX"), + #Cell("IFS1P3JX"), + #Cell("ILVDS"), + #Cell("INV"), + #Cell("L6MUX21"), + #Cell("LB2P3AX"), + #Cell("LB2P3AY"), + #Cell("LB2P3BX"), + #Cell("LB2P3DX"), + #Cell("LB2P3IX"), + #Cell("LB2P3JX"), + #Cell("LD2P3AX"), + #Cell("LD2P3AY"), + #Cell("LD2P3BX"), + #Cell("LD2P3DX"), + #Cell("LD2P3IX"), + #Cell("LD2P3JX"), + #Cell("LU2P3AX"), + #Cell("LU2P3AY"), + #Cell("LU2P3BX"), + #Cell("LU2P3DX"), + #Cell("LU2P3IX"), + #Cell("LU2P3JX"), + #Cell("MULT2"), + #Cell("MUX161"), + #Cell("MUX21"), + #Cell("MUX321"), + #Cell("MUX41"), + #Cell("MUX81"), + #Cell("ND2"), + #Cell("ND3"), + #Cell("ND4"), + #Cell("ND5"), + #Cell("NR2"), + #Cell("NR3"), + #Cell("NR4"), + #Cell("NR5"), + #Cell("OB"), + #Cell("OBCO"), + #Cell("OBZ"), + #Cell("OBZPU"), + #Cell("OFS1P3BX"), + #Cell("OFS1P3DX"), + #Cell("OFS1P3IX"), + #Cell("OFS1P3JX"), + #Cell("OLVDS"), + #Cell("OR2"), + #Cell("OR3"), + #Cell("OR4"), + #Cell("OR5"), + #Cell("LUT4"), + #Cell("LUT5"), + #Cell("LUT6"), + #Cell("LUT7"), + #Cell("LUT8"), + #Cell("PFUMX"), + #Cell("PUR"), + #Cell("ROM128X1A"), + #Cell("ROM16X1A"), + #Cell("ROM256X1A"), + #Cell("ROM32X1A"), + #Cell("ROM64X1A"), + #Cell("CCU2D"), + #Cell("VHI"), + #Cell("VLO"), + #Cell("XNOR2"), + #Cell("XNOR3"), + #Cell("XNOR4"), + #Cell("XNOR5"), + #Cell("XOR11"), + #Cell("XOR2"), + #Cell("XOR21"), + #Cell("XOR3"), + #Cell("XOR4"), + #Cell("XOR5"), + #Cell("IFS1S1B"), + #Cell("IFS1S1D"), + #Cell("IFS1S1I"), + #Cell("IFS1S1J"), + #Cell("DPR16X4C"), + #Cell("SPR16X4C"), + Cell("SGSR", True), + Cell("DP8KC"), + Cell("PDPW8KC"), + Cell("SP8KC"), + Cell("FIFO8KB"), + Cell("CLKDIVC"), + Cell("DCMA"), + Cell("ECLKSYNCA"), + Cell("ECLKBRIDGECS"), + Cell("DCCA"), + #Cell("JTAGF", True, port_attrs={'TCK': ['iopad_external_pin'], 'TMS': ['iopad_external_pin'], 'TDO': ['iopad_external_pin'], 'TDI': ['iopad_external_pin']}), + Cell("START", True), + #Cell("SEDFA"), + #Cell("SEDFB"), + #Cell("IDDRXE"), + #Cell("IDDRX2E"), + #Cell("IDDRX4B"), + #Cell("IDDRX71A"), + #Cell("ODDRXE"), + #Cell("ODDRX2E"), + #Cell("ODDRX4B"), + #Cell("ODDRX71A"), + #Cell("DQSDLLC"), + #Cell("DELAYE"), + #Cell("DELAYD"), + #Cell("DLLDELC"), + #Cell("CLKFBBUFA"), + #Cell("PCNTR"), + #Cell("BCINRD"), + #Cell("BCLVDSO"), + #Cell("INRDB"), + #Cell("LVDSOB"), + #Cell("PG"), + Cell("EHXPLLJ"), + #Cell("PLLREFCS"), + Cell("OSCJ"), + #Cell("EFBB"), + Cell("TSALL", True), + #Cell("ESBA"), + #Cell("BCSLEWRATEA"), + ]) +] + +def xtract_cells_decl(device, cells, dirs, outf): + fname = os.path.join(dir, device + '.v') + with open(fname) as f: + state = State.OUTSIDE + # Probably the most horrible Verilog "parser" ever written. + cell = None + kind = None + for l in f: + l, _, comment = l.partition('//') + l = l.strip() + m = re.search(r'synthesis .*black_box_pad_pin="([^"]*)"', comment) + if m: + iopad_pin = set(m.group(1).split(",")) + + if l.startswith("module "): + cell_name = l[7:l.find('(')].strip() + cell = None + kind = None + module_ports = [] + iopad_pin = set() + if state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + for c in cells: + if c.name != cell_name: + continue + cell = c + state = State.IN_MODULE + outf.write('(* blackbox *)') + if cell.keep: + outf.write(' (* keep *)\n') + else: + outf.write('\n') + outf.write('module {} (...);\n'.format(cell.name)) + cell.found = True + if cell is None: + state = State.IN_OTHER_MODULE + elif l.startswith('task '): + if state == State.IN_MODULE: + state = State.IN_TASK + elif l.startswith('function '): + if state == State.IN_MODULE: + state = State.IN_FUNCTION + elif l == 'endtask': + if state == State.IN_TASK: + state = State.IN_MODULE + elif l == 'endfunction': + if state == State.IN_FUNCTION: + state = State.IN_MODULE + elif l == 'endmodule': + if state == State.IN_MODULE: + for kind, rng, port in module_ports: + for attr in cell.port_attrs.get(port, []): + outf.write(' (* {} *)\n'.format(attr)) + if port in iopad_pin: + outf.write(' (* iopad_external_pin *)\n') + if rng is None: + outf.write(' {} {};\n'.format(kind, port)) + else: + outf.write(' {} {} {};\n'.format(kind, rng, port)) + outf.write(l + '\n') + outf.write('\n') + elif state != State.IN_OTHER_MODULE: + print('endmodule in weird place in {}.'.format(cell.name, fname)) + sys.exit(1) + state = State.OUTSIDE + elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: + l = l.strip() + if l == "": + continue + if l.endswith((';', ',', ")")): + l = l[:-1] + l = l.replace(")","") + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + kind, _, ports = l.partition(' ') + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() + else: + rng = None + module_ports.append((kind, rng, port)) + elif l.startswith('parameter ') and state == State.IN_MODULE: + l = l.strip() + if l.endswith((';', ',')): + l = l[:-1] + while ' ' in l: + l = l.replace(' ', ' ') + + if "INITVAL" in l: + l = l.replace('"0x', "320'h") + l = l.replace('"', '') + if ';' in l: + print('Weird parameter line in {} [{}].'.format(fname, l)) + sys.exit(1) + outf.write(' {};\n'.format(l)) + elif kind is not None and state == State.IN_MODULE: + l = l.strip() + if l == "": + continue + if l.endswith((';', ',', ")")): + l = l[:-1] + l = l.replace(")","") + if l == "": + continue + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + ports = l + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() + else: + rng = None + module_ports.append((kind, rng, port)) + + if state != State.OUTSIDE: + print('endmodule not found in {}.'.format(fname)) + sys.exit(1) + for cell in cells: + if not cell.found: + print('cell {} not found in {}.'.format(cell.name, fname)) +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Lattice blackbox cell definitions from Lattice Diamond.') + parser.add_argument('diamond_dir', nargs='?', default='/usr/local/diamond/3.12/') + args = parser.parse_args() + + dirs = [ + os.path.join(args.diamond_dir, 'cae_library/synthesis/verilog/'), + ] + for dir in dirs: + if not os.path.isdir(dir): + print('{} is not a directory'.format(dir)) + + for fn, device, cells in devices: + out = StringIO() + xtract_cells_decl(device, cells, dirs, out) + with open(fn, 'w') as f: + f.write('// Created by cells_xtra.py from Lattice models\n') + f.write('\n') + f.write(out.getvalue()) diff --git a/yosys/techlibs/lattice/common_sim.vh b/yosys/techlibs/lattice/common_sim.vh new file mode 100644 index 00000000000..2f8e1db1a82 --- /dev/null +++ b/yosys/techlibs/lattice/common_sim.vh @@ -0,0 +1,411 @@ +// --------------------------------------- + +(* abc9_lut=1, lib_whitebox *) +module LUT4(input A, B, C, D, output Z); + parameter [15:0] INIT = 16'h0000; + wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; + wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; + assign Z = A ? s1[1] : s1[0]; + specify + (A => Z) = 141; + (B => Z) = 275; + (C => Z) = 379; + (D => Z) = 379; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// cost of 5-input LUTs and is not intended to be instantiated +// LUT5 = 2x LUT4 + PFUMX +(* abc9_lut=2 *) +module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z); + specify + (M0 => Z) = 151; + (D => Z) = 239; + (C => Z) = 373; + (B => Z) = 477; + (A => Z) = 477; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// of 6-input LUTs and is not intended to be instantiated +// LUT6 = 2x LUT5 + MUX2 +(* abc9_lut=4 *) +module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z); + specify + (M1 => Z) = 148; + (M0 => Z) = 292; + (D => Z) = 380; + (C => Z) = 514; + (B => Z) = 618; + (A => Z) = 618; + endspecify +endmodule + +// This is a placeholder for ABC9 to extract the area/delay +// of 7-input LUTs and is not intended to be instantiated +// LUT7 = 2x LUT6 + MUX2 +(* abc9_lut=8 *) +module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z); + specify + (M2 => Z) = 148; + (M1 => Z) = 289; + (M0 => Z) = 433; + (D => Z) = 521; + (C => Z) = 655; + (B => Z) = 759; + (A => Z) = 759; + endspecify +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module L6MUX21 (input D0, D1, SD, output Z); + assign Z = SD ? D1 : D0; + specify + (D0 => Z) = 140; + (D1 => Z) = 141; + (SD => Z) = 148; + endspecify +endmodule + +// --------------------------------------- + +module TRELLIS_RAM16X2 ( + input DI0, DI1, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + input RAD0, RAD1, RAD2, RAD3, + output DO0, DO1 +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter INITVAL_0 = 16'h0000; + parameter INITVAL_1 = 16'h0000; + + reg [1:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= {INITVAL_1[i], INITVAL_0[i]}; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + + always @(posedge muxwck) + if (muxwre) + mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0}; + + assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}]; +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module PFUMX (input ALUT, BLUT, C0, output Z); + assign Z = C0 ? ALUT : BLUT; + specify + (ALUT => Z) = 98; + (BLUT => Z) = 98; + (C0 => Z) = 151; + endspecify +endmodule + +// --------------------------------------- +(* abc9_box, lib_whitebox *) +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i +: 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify +endmodule + +// --------------------------------------- + +(* abc9_box, lib_whitebox *) +module DPR16X4C ( + input [3:0] DI, + input WCK, WRE, + input [3:0] RAD, + input [3:0] WAD, + output [3:0] DO +); + // For legacy Lattice compatibility, INITIVAL is a hex + // string rather than a numeric parameter + parameter INITVAL = "0x0000000000000000"; + + function [63:0] convert_initval; + input [143:0] hex_initval; + reg done; + reg [63:0] temp; + reg [7:0] char; + integer i; + begin + done = 1'b0; + temp = 0; + for (i = 0; i < 16; i = i + 1) begin + if (!done) begin + char = hex_initval[8*i +: 8]; + if (char == "x") begin + done = 1'b1; + end else begin + if (char >= "0" && char <= "9") + temp[4*i +: 4] = char - "0"; + else if (char >= "A" && char <= "F") + temp[4*i +: 4] = 10 + char - "A"; + else if (char >= "a" && char <= "f") + temp[4*i +: 4] = 10 + char - "a"; + end + end + end + convert_initval = temp; + end + endfunction + + localparam conv_initval = convert_initval(INITVAL); + + reg [3:0] ram[0:15]; + integer i; + initial begin + for (i = 0; i < 15; i = i + 1) begin + ram[i] <= conv_initval[4*i +: 4]; + end + end + + always @(posedge WCK) + if (WRE) + ram[WAD] <= DI; + + assign DO = ram[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify +endmodule + +// --------------------------------------- + +(* lib_whitebox *) +module LUT2(input A, B, output Z); + parameter [3:0] INIT = 4'h0; + wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; + assign Z = A ? s1[1] : s1[0]; +endmodule + +// --------------------------------------- + +`ifdef YOSYS +(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *) +`endif +module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); + parameter GSR = "ENABLED"; + parameter [127:0] CEMUX = "1"; + parameter CLKMUX = "CLK"; + parameter LSRMUX = "LSR"; + parameter SRMODE = "LSR_OVER_CE"; + parameter REGSET = "RESET"; + parameter [127:0] LSRMODE = "LSR"; + + wire muxce; + generate + case (CEMUX) + "1": assign muxce = 1'b1; + "0": assign muxce = 1'b0; + "INV": assign muxce = ~CE; + default: assign muxce = CE; + endcase + endgenerate + + wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; + wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + wire srval; + generate + if (LSRMODE == "PRLD") + assign srval = M; + else + assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; + endgenerate + + initial Q = srval; + + generate + if (SRMODE == "ASYNC") begin + always @(posedge muxclk, posedge muxlsr) + if (muxlsr) + Q <= srval; + else if (muxce) + Q <= DI; + end else begin + always @(posedge muxclk) + if (muxlsr) + Q <= srval; + else if (muxce) + Q <= DI; + end + endgenerate + + specify + $setup(DI, negedge CLK &&& CLKMUX == "INV", 0); + $setup(CE, negedge CLK &&& CLKMUX == "INV", 0); + $setup(LSR, negedge CLK &&& CLKMUX == "INV", 0); + $setup(DI, posedge CLK &&& CLKMUX != "INV", 0); + $setup(CE, posedge CLK &&& CLKMUX != "INV", 0); + $setup(LSR, posedge CLK &&& CLKMUX != "INV", 0); +`ifndef YOSYS + if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0; + if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0; +`else + if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path + // but for facilitating a bypass box, let's pretend it's + // a simple path +`endif + if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0; + if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0; + endspecify +endmodule + +// --------------------------------------- +(* keep *) +module TRELLIS_IO( + (* iopad_external_pin *) + inout B, + input I, + input T, + output O +); + parameter DIR = "INPUT"; + reg T_pd; + always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T; + + generate + if (DIR == "INPUT") begin + assign B = 1'bz; + assign O = B; + end else if (DIR == "OUTPUT") begin + assign B = T_pd ? 1'bz : I; + assign O = 1'bx; + end else if (DIR == "BIDIR") begin + assign B = T_pd ? 1'bz : I; + assign O = B; + end else begin + ERROR_UNKNOWN_IO_MODE error(); + end + endgenerate + +endmodule + +// --------------------------------------- + +module INV(input A, output Z); + assign Z = !A; +endmodule + +// --------------------------------------- + +module TRELLIS_COMB( + input A, B, C, D, M, + input FCI, F1, FXA, FXB, + input WD, + input WAD0, WAD1, WAD2, WAD3, + input WRE, WCK, + output F, FCO, OFX +); + parameter MODE = "LOGIC"; + parameter INITVAL = 16'h0; + parameter CCU2_INJECT1 = "NO"; + parameter WREMUX = "WRE"; + parameter IS_Z1 = 1'b0; + + generate + if (MODE == "LOGIC") begin: mode_logic + LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F)); + end else if (MODE == "CCU2") begin: mode_ccu2 + wire l4o, l2o; + LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o)); + LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o)); + wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI; + assign F = l4o ^ gated_cin_0; + wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o; + wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI); + end else if (MODE == "DPRAM") begin: mode_dpram + reg [15:0] ram = INITVAL; + always @(posedge WCK) + if (WRE) + ram[{WAD3, WAD2, WAD1, WAD0}] <= WD; + assign F = ram[{A, C, B, D}]; + end else begin + $error("unsupported COMB mode %s", MODE); + end + + if (IS_Z1) + L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX)); + else + PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX)); + endgenerate + +endmodule + +// Constants +module VLO(output Z); + assign Z = 1'b0; +endmodule + +module VHI(output Z); + assign Z = 1'b1; +endmodule + +`ifndef NO_INCLUDES + +`include "cells_ff.vh" +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/lattice/dsp_map_18x18.v b/yosys/techlibs/lattice/dsp_map_18x18.v new file mode 100644 index 00000000000..df54d1d9f9f --- /dev/null +++ b/yosys/techlibs/lattice/dsp_map_18x18.v @@ -0,0 +1,17 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + + parameter A_WIDTH = 18; + parameter B_WIDTH = 18; + parameter Y_WIDTH = 36; + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + + MULT18X18D _TECHMAP_REPLACE_ ( + .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .A4(A[4]), .A5(A[5]), .A6(A[6]), .A7(A[7]), .A8(A[8]), .A9(A[9]), .A10(A[10]), .A11(A[11]), .A12(A[12]), .A13(A[13]), .A14(A[14]), .A15(A[15]), .A16(A[16]), .A17(A[17]), + .B0(B[0]), .B1(B[1]), .B2(B[2]), .B3(B[3]), .B4(B[4]), .B5(B[5]), .B6(B[6]), .B7(B[7]), .B8(B[8]), .B9(B[9]), .B10(B[10]), .B11(B[11]), .B12(B[12]), .B13(B[13]), .B14(B[14]), .B15(B[15]), .B16(B[16]), .B17(B[17]), + .C17(1'b0), .C16(1'b0), .C15(1'b0), .C14(1'b0), .C13(1'b0), .C12(1'b0), .C11(1'b0), .C10(1'b0), .C9(1'b0), .C8(1'b0), .C7(1'b0), .C6(1'b0), .C5(1'b0), .C4(1'b0), .C3(1'b0), .C2(1'b0), .C1(1'b0), .C0(1'b0), + .SIGNEDA(A_SIGNED ? 1'b1 : 1'b0), .SIGNEDB(B_SIGNED ? 1'b1 : 1'b0), .SOURCEA(1'b0), .SOURCEB(1'b0), + + .P0(Y[0]), .P1(Y[1]), .P2(Y[2]), .P3(Y[3]), .P4(Y[4]), .P5(Y[5]), .P6(Y[6]), .P7(Y[7]), .P8(Y[8]), .P9(Y[9]), .P10(Y[10]), .P11(Y[11]), .P12(Y[12]), .P13(Y[13]), .P14(Y[14]), .P15(Y[15]), .P16(Y[16]), .P17(Y[17]), .P18(Y[18]), .P19(Y[19]), .P20(Y[20]), .P21(Y[21]), .P22(Y[22]), .P23(Y[23]), .P24(Y[24]), .P25(Y[25]), .P26(Y[26]), .P27(Y[27]), .P28(Y[28]), .P29(Y[29]), .P30(Y[30]), .P31(Y[31]), .P32(Y[32]), .P33(Y[33]), .P34(Y[34]), .P35(Y[35]) + ); +endmodule diff --git a/yosys/techlibs/lattice/latches_map.v b/yosys/techlibs/lattice/latches_map.v new file mode 100644 index 00000000000..c28f88cf767 --- /dev/null +++ b/yosys/techlibs/lattice/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/yosys/techlibs/ecp5/ecp5_gsr.cc b/yosys/techlibs/lattice/lattice_gsr.cc similarity index 93% rename from yosys/techlibs/ecp5/ecp5_gsr.cc rename to yosys/techlibs/lattice/lattice_gsr.cc index 62b231aab3b..d7d41eca519 100644 --- a/yosys/techlibs/ecp5/ecp5_gsr.cc +++ b/yosys/techlibs/lattice/lattice_gsr.cc @@ -24,13 +24,13 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct Ecp5GsrPass : public Pass { - Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { } +struct LatticeGsrPass : public Pass { + LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" ecp5_gsr [options] [selection]\n"); + log(" lattice_gsr [options] [selection]\n"); log("\n"); log("Trim active low async resets connected to GSR and resolve GSR parameter,\n"); log("if a GSR or SGSR primitive is used in the design.\n"); @@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n"); + log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass { } } -} Ecp5GsrPass; +} LatticeGsrPass; PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/machxo2/lutrams.txt b/yosys/techlibs/lattice/lutrams.txt similarity index 54% rename from yosys/techlibs/machxo2/lutrams.txt rename to yosys/techlibs/lattice/lutrams.txt index c6b0b6c4560..ea42d4fcb5e 100644 --- a/yosys/techlibs/machxo2/lutrams.txt +++ b/yosys/techlibs/lattice/lutrams.txt @@ -1,11 +1,11 @@ -ram distributed $__DPR16X4C_ { +ram distributed $__TRELLIS_DPR16X4_ { abits 4; width 4; cost 4; - init no_undef; + init any; prune_rom; port sw "W" { - clock posedge; + clock anyedge; } port ar "R" { } diff --git a/yosys/techlibs/lattice/lutrams_map.v b/yosys/techlibs/lattice/lutrams_map.v new file mode 100644 index 00000000000..3cb325f041e --- /dev/null +++ b/yosys/techlibs/lattice/lutrams_map.v @@ -0,0 +1,30 @@ +module $__TRELLIS_DPR16X4_(...); + +parameter INIT = 64'bx; +parameter PORT_W_CLK_POL = 1; + +input PORT_W_CLK; +input [3:0] PORT_W_ADDR; +input [3:0] PORT_W_WR_DATA; +input PORT_W_WR_EN; + +input [3:0] PORT_R_ADDR; +output [3:0] PORT_R_RD_DATA; + +localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV"; + +TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") +) _TECHMAP_REPLACE_ ( + .RAD(PORT_R_ADDR), + .DO(PORT_R_RD_DATA), + + .WAD(PORT_W_ADDR), + .DI(PORT_W_WR_DATA), + .WCK(PORT_W_CLK), + .WRE(PORT_W_WR_EN) +); + +endmodule diff --git a/yosys/techlibs/lattice/synth_lattice.cc b/yosys/techlibs/lattice/synth_lattice.cc new file mode 100644 index 00000000000..cc5821ad832 --- /dev/null +++ b/yosys/techlibs/lattice/synth_lattice.cc @@ -0,0 +1,518 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthLatticePass : public ScriptPass +{ + SynthLatticePass() : ScriptPass("synth_lattice", "synthesis for Lattice FPGAs") { } + + void on_register() override + { + RTLIL::constpad["synth_lattice.abc9.W"] = "300"; + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_lattice [options]\n"); + log("\n"); + log("This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -family \n"); + log(" run synthesis for the specified Lattice architecture\n"); + log(" generate the synthesis netlist for the specified family.\n"); + log(" supported values:\n"); + log(" - ecp5: ECP5\n"); + log(" - xo2: MachXO2\n"); + log(" - xo3: MachXO3L/LF\n"); + log(" - xo3d: MachXO3D\n"); + //log(" - xo: MachXO (EXPERIMENTAL)\n"); + //log(" - pm: Platform Manager (EXPERIMENTAL)\n"); + //log(" - pm2: Platform Manager 2 (EXPERIMENTAL)\n"); + //log(" - xp: LatticeXP (EXPERIMENTAL)\n"); + //log(" - xp2: LatticeXP2 (EXPERIMENTAL)\n"); + //log(" - ecp: LatticeECP/EC (EXPERIMENTAL)\n"); + //log(" - sm: LatticeSC/M (EXPERIMENTAL)\n"); + //log(" - ecp2: LatticeECP2/M (EXPERIMENTAL)\n"); + //log(" - ecp3: LatticeECP3 (EXPERIMENTAL)\n"); + //log(" - lifmd: LIFMD (EXPERIMENTAL)\n"); + //log(" - lifmdf: LIFMDF (EXPERIMENTAL)\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -dff\n"); + log(" run 'abc'/'abc9' with -dff option\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with '-dff -D 1' options\n"); + log("\n"); + log(" -noccu2\n"); + log(" do not use CCU2 cells in output netlist\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist\n"); + log("\n"); + log(" -nolutram\n"); + log(" do not use LUT RAM cells in output netlist\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); + log(" (by default enabled on MachXO2/XO3/XO3D)\n"); + log("\n"); + log(" -widelut\n"); + log(" force use of PFU muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -asyncprld\n"); + log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n"); + log("\n"); + log(" -abc2\n"); + log(" run two passes of 'abc' for slightly improved logic density\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log(" -iopad\n"); + log(" insert IO buffers\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not map multipliers to MULT18X18D\n"); + log("\n"); + log(" -no-rw-check\n"); + log(" marks all recognized read ports as \"return don't-care value on\n"); + log(" read/write collision\" (same result as setting the no_rw_check\n"); + log(" attribute on all memories).\n"); + log("\n"); + log(" -cmp2softlogic\n"); + log(" implement constant comparisons in soft logic, do not involve\n"); + log(" hard carry chains\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, edif_file, json_file, family; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; + bool cmp2softlogic; + string postfix, arith_map, brams_map, dsp_map; + + void clear_flags() override + { + top_opt = "-auto-top"; + edif_file = ""; + json_file = ""; + family = ""; + noccu2 = false; + nodffe = false; + nobram = false; + nolutram = false; + nowidelut = false; + asyncprld = false; + flatten = true; + dff = false; + retime = false; + abc2 = false; + abc9 = false; + iopad = false; + nodsp = false; + no_rw_check = false; + postfix = ""; + arith_map = ""; + brams_map = ""; + dsp_map = ""; + have_dsp = false; + cmp2softlogic = false; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + string run_from, run_to; + bool force_widelut = false; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) { + family = args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-flatten") { + flatten = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-dff") { + dff = true; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + if (args[argidx] == "-noccu2") { + noccu2 = true; + continue; + } + if (args[argidx] == "-nodffe") { + nodffe = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-asyncprld") { + asyncprld = true; + continue; + } + if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { + nolutram = true; + continue; + } + if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") { + nowidelut = true; + force_widelut = true; + continue; + } + if (args[argidx] == "-widelut") { + nowidelut = false; + force_widelut = true; + continue; + } + if (args[argidx] == "-abc2") { + abc2 = true; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } + if (args[argidx] == "-iopad") { + iopad = true; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-no-rw-check") { + no_rw_check = true; + continue; + } + if (args[argidx] == "-cmp2softlogic") { + cmp2softlogic = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (family.empty()) + log_cmd_error("Lattice family parameter must be set.\n"); + + if (family == "ecp5") { + postfix = "_ecp5"; + arith_map = "_ccu2c"; + brams_map = "_16kd"; + dsp_map = "_18x18"; + have_dsp = true; + } else if (family == "xo2" || + family == "xo3" || + family == "xo3d" /* || + family == "pm2"*/) { + postfix = "_" + family; + arith_map = "_ccu2d"; + brams_map = "_8kc"; + have_dsp = false; + if (!force_widelut) nowidelut = true; +/* } else if (family == "xo" || + family == "pm") { + } else if (family == "xp" || + family == "xp2" || + family == "ecp" || + family == "sm" || + family == "ecp2" || + family == "ecp3" || + family == "lifmd" || + family == "lifmdf") {*/ + } else + log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str()); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + if (abc9 && retime) + log_cmd_error("-retime option not currently compatible with -abc9!\n"); + + log_header(design, "Executing SYNTH_LATTICE pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + std::string no_rw_check_opt = ""; + if (no_rw_check) + no_rw_check_opt = " -no-rw-check"; + if (help_mode) + no_rw_check_opt = " [-no-rw-check]"; + + if (check_label("begin")) + { + run("read_verilog -lib -specify +/lattice/cells_sim" + postfix + ".v +/lattice/cells_bb" + postfix + ".v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (check_label("coarse")) + { + run("proc"); + if (flatten || help_mode) + run("flatten"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + if (cmp2softlogic) + run("techmap -map +/cmp2softlogic.v"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + if (have_dsp && !nodsp) { + run("techmap -map +/mul2dsp.v -map +/lattice/dsp_map" + dsp_map + ".v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)"); + run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)"); + } + if (family == "xo3" || help_mode) + run("booth", "(only if '-family xo3')"); + run("alumacc"); + run("opt"); + run("memory -nomap" + no_rw_check_opt); + run("opt_clean"); + } + + if (check_label("map_ram")) + { + std::string args = ""; + if (nobram) + args += " -no-auto-block"; + if (nolutram) + args += " -no-auto-distributed"; + if (help_mode) + args += " [-no-auto-block] [-no-auto-distributed]"; + run("memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams" + brams_map + ".txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); + run("techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map" + brams_map + ".v"); + } + + if (check_label("map_ffram")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine -mux_undef"); + } + + if (check_label("map_gates")) + { + if (noccu2) + run("techmap"); + else + run("techmap -map +/techmap.v -map +/lattice/arith_map" + arith_map + ".v"); + if (help_mode || iopad) { + run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); + run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); + run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); + } + run("opt -fast"); + if (retime || help_mode) + run("abc -dff -D 1", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("opt_clean"); + std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; + if (help_mode) { + dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]"; + } else if (!nodffe) { + dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r"; + } + if (help_mode) { + dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]"; + } else if (asyncprld) { + dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x"; + } else { + dfflegalize_args += " -cell $_DLATCH_?_ x"; + } + run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)"); + run("opt_merge"); + if ((abc9 && dff) || help_mode) + run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)"); + run("techmap -D NO_LUT -map +/lattice/cells_map.v"); + run("opt_expr -undriven -mux_undef"); + run("simplemap"); + run("lattice_gsr"); + run("attrmvcp -copy -attr syn_useioff"); + run("opt_clean"); + } + + if (check_label("map_luts")) + { + if (abc2 || help_mode) + run("abc", " (only if -abc2)"); + if (!asyncprld || help_mode) + run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); + + if (abc9) { + std::string abc9_opts; + if (nowidelut) + abc9_opts += " -maxlut 4"; + std::string k = "synth_lattice.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + if (nowidelut) + abc9_opts += " -maxlut 4"; + if (dff) + abc9_opts += " -dff"; + run("abc9" + abc9_opts); + } else { + std::string abc_args = " -dress"; + if (nowidelut) + abc_args += " -lut 4"; + else + abc_args += " -lut 4:7"; + if (dff) + abc_args += " -dff"; + run("abc" + abc_args); + } + run("clean"); + } + + if (check_label("map_cells")) + { + run("techmap -map +/lattice/cells_map.v"); + run("opt_lut_ins -tech lattice"); + run("clean"); + } + + if (check_label("check")) + { + run("autoname"); + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthLatticePass; + +/* +struct SynthEcp5Pass : public Pass +{ + SynthEcp5Pass() : Pass("synth_ecp5", "synthesis for ECP5 FPGAs") { } + + void execute(std::vector args, RTLIL::Design *design) override + { + args[0] = "synth_lattice"; + args.insert(args.begin()+1, std::string()); + args.insert(args.begin()+1, std::string()); + args[1] = "-family"; + args[2] = "ecp5"; + Pass::call(design, args); + } +} SynthEcp5Pass; +*/ + +PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/machxo2/Makefile.inc b/yosys/techlibs/machxo2/Makefile.inc deleted file mode 100644 index cd4e27884fc..00000000000 --- a/yosys/techlibs/machxo2/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ - -OBJS += techlibs/machxo2/synth_machxo2.o - -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v)) - -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt)) -$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v)) - -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v)) diff --git a/yosys/techlibs/machxo2/cells_bb.v b/yosys/techlibs/machxo2/cells_bb.v deleted file mode 100644 index 3d047b1692a..00000000000 --- a/yosys/techlibs/machxo2/cells_bb.v +++ /dev/null @@ -1,227 +0,0 @@ -(* blackbox *) -module EHXPLLJ ( - input CLKI, CLKFB, - input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, - input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, - input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, - input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, - input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, - output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, - output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, - output DPHSRC, CLKINTFB -); - parameter CLKI_DIV = 1; - parameter CLKFB_DIV = 1; - parameter CLKOP_DIV = 8; - parameter CLKOS_DIV = 8; - parameter CLKOS2_DIV = 8; - parameter CLKOS3_DIV = 8; - parameter CLKOP_ENABLE = "ENABLED"; - parameter CLKOS_ENABLE = "ENABLED"; - parameter CLKOS2_ENABLE = "ENABLED"; - parameter CLKOS3_ENABLE = "ENABLED"; - parameter VCO_BYPASS_A0 = "DISABLED"; - parameter VCO_BYPASS_B0 = "DISABLED"; - parameter VCO_BYPASS_C0 = "DISABLED"; - parameter VCO_BYPASS_D0 = "DISABLED"; - parameter CLKOP_CPHASE = 0; - parameter CLKOS_CPHASE = 0; - parameter CLKOS2_CPHASE = 0; - parameter CLKOS3_CPHASE = 0; - parameter CLKOP_FPHASE = 0; - parameter CLKOS_FPHASE = 0; - parameter CLKOS2_FPHASE = 0; - parameter CLKOS3_FPHASE = 0; - parameter FEEDBK_PATH = "CLKOP"; - parameter FRACN_ENABLE = "DISABLED"; - parameter FRACN_DIV = 0; - parameter CLKOP_TRIM_POL = "RISING"; - parameter CLKOP_TRIM_DELAY = 0; - parameter CLKOS_TRIM_POL = "RISING"; - parameter CLKOS_TRIM_DELAY = 0; - parameter PLL_USE_WB = "DISABLED"; - parameter PREDIVIDER_MUXA1 = 0; - parameter PREDIVIDER_MUXB1 = 0; - parameter PREDIVIDER_MUXC1 = 0; - parameter PREDIVIDER_MUXD1 = 0; - parameter OUTDIVIDER_MUXA2 = "DIVA"; - parameter OUTDIVIDER_MUXB2 = "DIVB"; - parameter OUTDIVIDER_MUXC2 = "DIVC"; - parameter OUTDIVIDER_MUXD2 = "DIVD"; - parameter PLL_LOCK_MODE = 0; - parameter STDBY_ENABLE = "DISABLED"; - parameter DPHASE_SOURCE = "DISABLED"; - parameter PLLRST_ENA = "DISABLED"; - parameter MRST_ENA = "DISABLED"; - parameter DCRST_ENA = "DISABLED"; - parameter DDRST_ENA = "DISABLED"; - parameter INTFB_WAKE = "DISABLED"; -endmodule - -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY -); -endmodule - -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); -endmodule - -(* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); -endmodule - -(* blackbox *) -module PDPW8KC ( - input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, - input BE1, BE0, - input CEW, CLKW, CSW2, CSW1, CSW0, - input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, - input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, - output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); - parameter DATA_WIDTH_W = 18; - parameter DATA_WIDTH_R = 9; - - parameter GSR = "ENABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_W = "0b000"; - parameter CSDECODE_R = "0b000"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; - -endmodule - -(* blackbox *) -module SP8KC ( - input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, - input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, - input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, - output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 -); - parameter DATA_WIDTH = 9; - parameter GSR = "ENABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE = "0b000"; - - parameter WRITEMODE = "NORMAL"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_DATA = "STATIC"; -endmodule - -(* blackbox *) -module FIFO8KB ( - input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, - input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, - output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, - input EF, AEF, AFF, FF -); - parameter DATA_WIDTH_W = 18; - parameter DATA_WIDTH_R = 18; - - parameter GSR = "DISABLED"; - - parameter REGMODE = "NOREG"; - - parameter RESETMODE = "ASYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_W = "0b00"; - parameter CSDECODE_R = "0b00"; - - parameter AEPOINTER = "0b00000000000000"; - parameter AEPOINTER1 = "0b00000000000000"; - parameter AFPOINTER = "0b00000000000000"; - parameter AFPOINTER1 = "0b00000000000000"; - parameter FULLPOINTER = "0b00000000000000"; - parameter FULLPOINTER1 = "0b00000000000000"; -endmodule diff --git a/yosys/techlibs/machxo2/cells_sim.v b/yosys/techlibs/machxo2/cells_sim.v deleted file mode 100644 index 8e0e411791c..00000000000 --- a/yosys/techlibs/machxo2/cells_sim.v +++ /dev/null @@ -1,385 +0,0 @@ -module LUT2(input A, B, output Z); - parameter [3:0] INIT = 4'h0; - wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; - assign Z = A ? s1[1] : s1[0]; -endmodule - -module LUT4 #( - parameter [15:0] INIT = 0 -) ( - input A, B, C, D, - output Z -); - // This form of LUT propagates as few x's as possible. - wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0]; - wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0]; - assign Z = A ? s1[1] : s1[0]; -endmodule - -module TRELLIS_FF #( - parameter GSR = "ENABLED", - parameter CEMUX = "1", - parameter CLKMUX = "0", - parameter LSRMUX = "LSR", - parameter LSRONMUX = "LSRMUX", - parameter SRMODE = "LSR_OVER_CE", - parameter REGSET = "SET", - parameter REGMODE = "FF" -) ( - input CLK, DI, LSR, CE, - output reg Q -); - - wire muxce; - generate - case (CEMUX) - "1": assign muxce = 1'b1; - "0": assign muxce = 1'b0; - "INV": assign muxce = ~CE; - default: assign muxce = CE; - endcase - endgenerate - - wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; - wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0; - wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; - wire srval = (REGSET == "SET") ? 1'b1 : 1'b0; - - initial Q = srval; - - generate - if (REGMODE == "FF") begin - if (SRMODE == "ASYNC") begin - always @(posedge muxclk, posedge muxlsron) - if (muxlsron) - Q <= srval; - else if (muxce) - Q <= DI; - end else begin - always @(posedge muxclk) - if (muxlsron) - Q <= srval; - else if (muxce) - Q <= DI; - end - end else if (REGMODE == "LATCH") begin - ERROR_UNSUPPORTED_FF_MODE error(); - end else begin - ERROR_UNKNOWN_FF_MODE error(); - end - endgenerate -endmodule - -/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */ -module PFUMX (input ALUT, BLUT, C0, output Z); - assign Z = C0 ? ALUT : BLUT; -endmodule - -/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */ -module L6MUX21 (input D0, D1, SD, output Z); - assign Z = SD ? D1 : D0; -endmodule - -/* For consistency, input order matches TRELLIS_SLICE even though the BELs in -prjtrellis were filled in clockwise order from bottom left. */ -module TRELLIS_SLICE #( - parameter MODE = "LOGIC", - parameter GSR = "ENABLED", - parameter SRMODE = "LSR_OVER_CE", - parameter CEMUX = "1", - parameter CLKMUX = "0", - parameter LSRMUX = "LSR", - parameter LSRONMUX = "LSRMUX", - parameter LUT0_INITVAL = 16'hFFFF, - parameter LUT1_INITVAL = 16'hFFFF, - parameter REGMODE = "FF", - parameter REG0_SD = "1", - parameter REG1_SD = "1", - parameter REG0_REGSET = "SET", - parameter REG1_REGSET = "SET", - parameter CCU2_INJECT1_0 = "YES", - parameter CCU2_INJECT1_1 = "YES", - parameter WREMUX = "INV" -) ( - input A0, B0, C0, D0, - input A1, B1, C1, D1, - input M0, M1, - input FCI, FXA, FXB, - - input CLK, LSR, CE, - input DI0, DI1, - - input WD0, WD1, - input WAD0, WAD1, WAD2, WAD3, - input WRE, WCK, - - output F0, Q0, - output F1, Q1, - output FCO, OFX0, OFX1, - - output WDO0, WDO1, WDO2, WDO3, - output WADO0, WADO1, WADO2, WADO3 -); - - generate - if (MODE == "LOGIC") begin - L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - wire k0; - wire k1; - PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0)); - - LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0)); - LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1)); - - assign F0 = k0; - assign F1 = k1; - end else if (MODE == "CCU2") begin - ERROR_UNSUPPORTED_SLICE_MODE error(); - end else if (MODE == "DPRAM") begin - ERROR_UNSUPPORTED_SLICE_MODE error(); - end else begin - ERROR_UNKNOWN_SLICE_MODE error(); - end - endgenerate - - /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F - outputs (in other words, feeds back into TRELLIS_SLICE). */ - wire di0 = (REG0_SD == "1") ? DI0 : M0; - wire di1 = (REG1_SD == "1") ? DI1 : M1; - - TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), - .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), - .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); - TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), - .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), - .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); -endmodule - -module TRELLIS_IO #( - parameter DIR = "INPUT" -) ( - (* iopad_external_pin *) - inout B, - input I, T, - output O -); - generate - if (DIR == "INPUT") begin - assign O = B; - end else if (DIR == "OUTPUT") begin - assign B = T ? 1'bz : I; - end else if (DIR == "BIDIR") begin - assign B = T ? 1'bz : I; - assign O = B; - end else begin - ERROR_UNKNOWN_IO_MODE error(); - end - endgenerate -endmodule - -(* abc9_box, lib_whitebox *) -module TRELLIS_DPR16X4 ( - input [3:0] DI, - input [3:0] WAD, - input WRE, - input WCK, - input [3:0] RAD, - output [3:0] DO -); - parameter WCKMUX = "WCK"; - parameter WREMUX = "WRE"; - parameter [63:0] INITVAL = 64'h0000000000000000; - - reg [3:0] mem[15:0]; - - integer i; - initial begin - for (i = 0; i < 16; i = i + 1) - mem[i] <= INITVAL[4*i +: 4]; - end - - wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; - - reg muxwre; - always @(*) - case (WREMUX) - "1": muxwre = 1'b1; - "0": muxwre = 1'b0; - "INV": muxwre = ~WRE; - default: muxwre = WRE; - endcase - - always @(posedge muxwck) - if (muxwre) - mem[WAD] <= DI; - - assign DO = mem[RAD]; - - specify - // TODO - (RAD *> DO) = 0; - endspecify -endmodule - -(* abc9_box, lib_whitebox *) -module DPR16X4C ( - input [3:0] DI, - input WCK, WRE, - input [3:0] RAD, - input [3:0] WAD, - output [3:0] DO -); - parameter INITVAL = "0x0000000000000000"; - - function [63:0] convert_initval; - input [143:0] hex_initval; - reg done; - reg [63:0] temp; - reg [7:0] char; - integer i; - begin - done = 1'b0; - temp = 0; - for (i = 0; i < 16; i = i + 1) begin - if (!done) begin - char = hex_initval[8*i +: 8]; - if (char == "x") begin - done = 1'b1; - end else begin - if (char >= "0" && char <= "9") - temp[4*i +: 4] = char - "0"; - else if (char >= "A" && char <= "F") - temp[4*i +: 4] = 10 + char - "A"; - else if (char >= "a" && char <= "f") - temp[4*i +: 4] = 10 + char - "a"; - end - end - end - convert_initval = temp; - end - endfunction - - localparam conv_initval = convert_initval(INITVAL); - - reg [3:0] ram[0:15]; - integer i; - initial begin - for (i = 0; i < 15; i = i + 1) begin - ram[i] <= conv_initval[4*i +: 4]; - end - end - - always @(posedge WCK) - if (WRE) - ram[WAD] <= DI; - - assign DO = ram[RAD]; -endmodule - -// --------------------------------------- -(* lib_whitebox *) -module CCU2D ( - input CIN, - input A0, B0, C0, D0, A1, B1, C1, D1, - output S0, S1, - output COUT -); - parameter [15:0] INIT0 = 16'h0000; - parameter [15:0] INIT1 = 16'h0000; - parameter INJECT1_0 = "YES"; - parameter INJECT1_1 = "YES"; - - // First half - wire LUT4_0, LUT2_0; - LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); - LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); - wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; - assign S0 = LUT4_0 ^ gated_cin_0; - - wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; - wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); - - // Second half - wire LUT4_1, LUT2_1; - LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); - LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); - wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; - assign S1 = LUT4_1 ^ gated_cin_1; - - wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; - assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); -endmodule - -(* blackbox *) -module DP8KC( - input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, - input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0, - input CEA, OCEA, CLKA, WEA, RSTA, - input CSA2, CSA1, CSA0, - output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, - - input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, - input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, - input CEB, OCEB, CLKB, WEB, RSTB, - input CSB2, CSB1, CSB0, - output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 -); - parameter DATA_WIDTH_A = 9; - parameter DATA_WIDTH_B = 9; - - parameter REGMODE_A = "NOREG"; - parameter REGMODE_B = "NOREG"; - - parameter RESETMODE = "SYNC"; - parameter ASYNC_RESET_RELEASE = "SYNC"; - - parameter CSDECODE_A = "0b000"; - parameter CSDECODE_B = "0b000"; - - parameter WRITEMODE_A = "NORMAL"; - parameter WRITEMODE_B = "NORMAL"; - - parameter GSR = "ENABLED"; - parameter INIT_DATA = "STATIC"; - - parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; -endmodule - -`ifndef NO_INCLUDES - -`include "cells_io.vh" - -`endif diff --git a/yosys/techlibs/machxo2/lutrams_map.v b/yosys/techlibs/machxo2/lutrams_map.v deleted file mode 100644 index b55253fb868..00000000000 --- a/yosys/techlibs/machxo2/lutrams_map.v +++ /dev/null @@ -1,23 +0,0 @@ -module $__DPR16X4C_ (...); - parameter INIT = 64'b0; - - input PORT_W_CLK; - input [3:0] PORT_W_ADDR; - input [3:0] PORT_W_WR_DATA; - input PORT_W_WR_EN; - - input [3:0] PORT_R_ADDR; - output [3:0] PORT_R_RD_DATA; - - DPR16X4C #( - .INITVAL($sformatf("0x%08x", INIT)) - ) _TECHMAP_REPLACE_ ( - .RAD(PORT_R_ADDR), - .DO(PORT_R_RD_DATA), - - .WAD(PORT_W_ADDR), - .DI(PORT_W_WR_DATA), - .WCK(PORT_W_CLK), - .WRE(PORT_W_WR_EN) - ); -endmodule diff --git a/yosys/techlibs/machxo2/synth_machxo2.cc b/yosys/techlibs/machxo2/synth_machxo2.cc deleted file mode 100644 index 2b684a7d8fd..00000000000 --- a/yosys/techlibs/machxo2/synth_machxo2.cc +++ /dev/null @@ -1,297 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2020 William D. Jones - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/register.h" -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct SynthMachXO2Pass : public ScriptPass -{ - SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { } - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_machxo2 [options]\n"); - log("\n"); - log("This command runs synthesis for MachXO2 FPGAs.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module\n"); - log("\n"); - log(" -blif \n"); - log(" write the design to the specified BLIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -edif \n"); - log(" write the design to the specified EDIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -json \n"); - log(" write the design to the specified JSON file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use block RAM cells in output netlist\n"); - log("\n"); - log(" -nolutram\n"); - log(" do not use LUT RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -noiopad\n"); - log(" do not insert IO buffers\n"); - log("\n"); - log(" -ccu2\n"); - log(" use CCU2 cells in output netlist\n"); - log("\n"); - log(" -vpr\n"); - log(" generate an output netlist (and BLIF file) suitable for VPR\n"); - log(" (this feature is experimental and incomplete)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); - help_script(); - log("\n"); - } - - string top_opt, blif_file, edif_file, json_file; - bool ccu2, nobram, nolutram, flatten, vpr, noiopad; - - void clear_flags() override - { - top_opt = "-auto-top"; - blif_file = ""; - edif_file = ""; - json_file = ""; - ccu2 = false; - nobram = false; - nolutram = false; - flatten = true; - vpr = false; - noiopad = false; - } - - void execute(std::vector args, RTLIL::Design *design) override - { - string run_from, run_to; - clear_flags(); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { - top_opt = "-top " + args[++argidx]; - continue; - } - if (args[argidx] == "-blif" && argidx+1 < args.size()) { - blif_file = args[++argidx]; - continue; - } - if (args[argidx] == "-edif" && argidx+1 < args.size()) { - edif_file = args[++argidx]; - continue; - } - if (args[argidx] == "-json" && argidx+1 < args.size()) { - json_file = args[++argidx]; - continue; - } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); - if (pos == std::string::npos) - break; - run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); - continue; - } - if (args[argidx] == "-flatten") { - flatten = true; - continue; - } - if (args[argidx] == "-noflatten") { - flatten = false; - continue; - } - if (args[argidx] == "-nobram") { - nobram = true; - continue; - } - if (args[argidx] == "-nolutram") { - nolutram = true; - continue; - } - if (args[argidx] == "-noiopad") { - noiopad = true; - continue; - } - if (args[argidx] == "-ccu2") { - ccu2 = true; - continue; - } - if (args[argidx] == "-vpr") { - vpr = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - if (!design->full_selection()) - log_cmd_error("This command only operates on fully selected designs!\n"); - - log_header(design, "Executing SYNTH_MACHXO2 pass.\n"); - log_push(); - - run_script(design, run_from, run_to); - - log_pop(); - } - - void script() override - { - if (check_label("begin")) - { - run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); - } - - if (check_label("flatten", "(unless -noflatten)")) - { - if (flatten || help_mode) { - run("proc"); - run("flatten"); - run("tribuf -logic"); - run("deminout"); - } - } - - if (check_label("coarse")) - { - run("synth -run coarse"); - } - - if (check_label("map_ram")) - { - std::string args = ""; - if (nobram) - args += " -no-auto-block"; - if (nolutram) - args += " -no-auto-distributed"; - if (help_mode) - args += " [-no-auto-block] [-no-auto-distributed]"; - run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)"); - run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v"); - } - - if (check_label("fine")) - { - run("opt -fast -mux_undef -undriven -fine"); - run("memory_map"); - run("opt -undriven -fine"); - } - - if (check_label("map_gates", "(unless -noiopad)")) - { - if (!ccu2) - run("techmap"); - else - run("techmap -map +/techmap.v -map +/machxo2/arith_map.v"); - if (!noiopad || help_mode) - { - run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); - run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); - run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); - } - } - - if (check_label("map_ffs")) - { - run("opt_clean"); - std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; - run("dfflegalize" + dfflegalize_args); - run("techmap -D NO_LUT -map +/machxo2/cells_map.v"); - run("opt_expr -undriven -mux_undef"); - run("simplemap"); - run("ecp5_gsr"); - run("attrmvcp -copy -attr syn_useioff"); - run("opt_clean"); - } - - if (check_label("map_luts")) - { - run("abc -lut 4 -dress"); - run("clean"); - } - - if (check_label("map_cells")) - { - run("techmap -map +/machxo2/cells_map.v"); - run("clean"); - } - - if (check_label("check")) - { - run("hierarchy -check"); - run("stat"); - run("blackbox =A:whitebox"); - } - - if (check_label("blif")) - { - if (!blif_file.empty() || help_mode) { - if (vpr || help_mode) { - run(stringf("opt_clean -purge"), - " (vpr mode)"); - run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str()), - " (vpr mode)"); - } - if (!vpr) - run(stringf("write_blif -gates -attr -param %s", - help_mode ? "" : blif_file.c_str()), - " (non-vpr mode)"); - } - } - - if (check_label("edif")) - { - if (!edif_file.empty() || help_mode) - run(stringf("write_edif %s", help_mode ? "" : edif_file.c_str())); - } - - if (check_label("json")) - { - if (!json_file.empty() || help_mode) - run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); - } - } -} SynthMachXO2Pass; - -PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/nexus/brams_map.v b/yosys/techlibs/nexus/brams_map.v index cec56cec4ab..dbcee5c41c7 100644 --- a/yosys/techlibs/nexus/brams_map.v +++ b/yosys/techlibs/nexus/brams_map.v @@ -134,8 +134,8 @@ DP16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_A($sformatf("X%d", PORT_A_WIDTH)), - .DATA_WIDTH_B($sformatf("X%d", PORT_B_WIDTH)), + .DATA_WIDTH_A($sformatf("X%0d", PORT_A_WIDTH)), + .DATA_WIDTH_B($sformatf("X%0d", PORT_B_WIDTH)), .OUTREG_A("BYPASSED"), .OUTREG_B("BYPASSED"), .RESETMODE_A(PORT_A_OPTION_RESETMODE), @@ -298,8 +298,8 @@ PDPSC16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)), - .DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)), + .DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)), + .DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)), .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), @@ -389,8 +389,8 @@ PDP16K #( .INITVAL_3D($sformatf("0x%080x", init_slice('h3d))), .INITVAL_3E($sformatf("0x%080x", init_slice('h3e))), .INITVAL_3F($sformatf("0x%080x", init_slice('h3f))), - .DATA_WIDTH_W($sformatf("X%d", PORT_W_WIDTH)), - .DATA_WIDTH_R($sformatf("X%d", PORT_R_WIDTH)), + .DATA_WIDTH_W($sformatf("X%0d", PORT_W_WIDTH)), + .DATA_WIDTH_R($sformatf("X%0d", PORT_R_WIDTH)), .OUTREG("BYPASSED"), .RESETMODE(PORT_R_OPTION_RESETMODE), .ASYNC_RST_RELEASE(PORT_R_OPTION_RESETMODE), diff --git a/yosys/techlibs/quicklogic/.gitignore b/yosys/techlibs/quicklogic/.gitignore new file mode 100644 index 00000000000..e52f3282f7f --- /dev/null +++ b/yosys/techlibs/quicklogic/.gitignore @@ -0,0 +1 @@ +/*_pm.h diff --git a/yosys/techlibs/quicklogic/Makefile.inc b/yosys/techlibs/quicklogic/Makefile.inc index 51eb28d44bd..ade1443713c 100644 --- a/yosys/techlibs/quicklogic/Makefile.inc +++ b/yosys/techlibs/quicklogic/Makefile.inc @@ -1,13 +1,43 @@ +techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v: techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ $@ + OBJS += techlibs/quicklogic/synth_quicklogic.o +OBJS += techlibs/quicklogic/ql_bram_merge.o +OBJS += techlibs/quicklogic/ql_bram_types.o +OBJS += techlibs/quicklogic/ql_dsp_simd.o +OBJS += techlibs/quicklogic/ql_dsp_io_regs.o + +# -------------------------------------- + +OBJS += techlibs/quicklogic/ql_dsp_macc.o +GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v +techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h +$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h)) + +# -------------------------------------- + +$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) + +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v)) - -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) +$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v)) \ No newline at end of file diff --git a/yosys/techlibs/quicklogic/cells_sim.v b/yosys/techlibs/quicklogic/common/cells_sim.v similarity index 100% rename from yosys/techlibs/quicklogic/cells_sim.v rename to yosys/techlibs/quicklogic/common/cells_sim.v diff --git a/yosys/techlibs/quicklogic/lut_sim.v b/yosys/techlibs/quicklogic/lut_sim.v deleted file mode 100644 index 851ce4d6845..00000000000 --- a/yosys/techlibs/quicklogic/lut_sim.v +++ /dev/null @@ -1,76 +0,0 @@ -(* abc9_lut=1, lib_whitebox *) -module LUT1 ( - output O, - input I0 -); - parameter [1:0] INIT = 0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 698; // FS -> FZ - endspecify - - assign O = I0 ? INIT[1] : INIT[0]; -endmodule - -// TZ TSL TAB -(* abc9_lut=2, lib_whitebox *) -module LUT2 ( - output O, - input I0, I1 -); - parameter [3:0] INIT = 4'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - endspecify - - wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=2, lib_whitebox *) -module LUT3 ( - output O, - input I0, I1, I2 -); - parameter [7:0] INIT = 8'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ - endspecify - - wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=4, lib_whitebox *) -module LUT4 ( - output O, - input I0, I1, I2, I3 -); - parameter [15:0] INIT = 16'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 995; // TBS -> CZ - (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ - (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ - (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ - endspecify - - wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule diff --git a/yosys/techlibs/quicklogic/abc9_map.v b/yosys/techlibs/quicklogic/pp3/abc9_map.v similarity index 100% rename from yosys/techlibs/quicklogic/abc9_map.v rename to yosys/techlibs/quicklogic/pp3/abc9_map.v diff --git a/yosys/techlibs/quicklogic/abc9_model.v b/yosys/techlibs/quicklogic/pp3/abc9_model.v similarity index 100% rename from yosys/techlibs/quicklogic/abc9_model.v rename to yosys/techlibs/quicklogic/pp3/abc9_model.v diff --git a/yosys/techlibs/quicklogic/abc9_unmap.v b/yosys/techlibs/quicklogic/pp3/abc9_unmap.v similarity index 100% rename from yosys/techlibs/quicklogic/abc9_unmap.v rename to yosys/techlibs/quicklogic/pp3/abc9_unmap.v diff --git a/yosys/techlibs/quicklogic/pp3_cells_map.v b/yosys/techlibs/quicklogic/pp3/cells_map.v similarity index 100% rename from yosys/techlibs/quicklogic/pp3_cells_map.v rename to yosys/techlibs/quicklogic/pp3/cells_map.v diff --git a/yosys/techlibs/quicklogic/pp3_cells_sim.v b/yosys/techlibs/quicklogic/pp3/cells_sim.v similarity index 76% rename from yosys/techlibs/quicklogic/pp3_cells_sim.v rename to yosys/techlibs/quicklogic/pp3/cells_sim.v index 5820d7a9ec0..201a7d33331 100644 --- a/yosys/techlibs/quicklogic/pp3_cells_sim.v +++ b/yosys/techlibs/quicklogic/pp3/cells_sim.v @@ -327,3 +327,80 @@ module qlal4s3b_cell_macro ( ); endmodule + +(* abc9_lut=1, lib_whitebox *) +module LUT1 ( + output O, + input I0 +); + parameter [1:0] INIT = 0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 698; // FS -> FZ + endspecify + + assign O = I0 ? INIT[1] : INIT[0]; +endmodule + +// TZ TSL TAB +(* abc9_lut=2, lib_whitebox *) +module LUT2 ( + output O, + input I0, I1 +); + parameter [3:0] INIT = 4'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + endspecify + + wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=2, lib_whitebox *) +module LUT3 ( + output O, + input I0, I1, I2 +); + parameter [7:0] INIT = 8'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ + endspecify + + wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=4, lib_whitebox *) +module LUT4 ( + output O, + input I0, I1, I2, I3 +); + parameter [15:0] INIT = 16'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 995; // TBS -> CZ + (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ + (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ + (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ + endspecify + + wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule diff --git a/yosys/techlibs/quicklogic/pp3_ffs_map.v b/yosys/techlibs/quicklogic/pp3/ffs_map.v similarity index 100% rename from yosys/techlibs/quicklogic/pp3_ffs_map.v rename to yosys/techlibs/quicklogic/pp3/ffs_map.v diff --git a/yosys/techlibs/quicklogic/pp3_latches_map.v b/yosys/techlibs/quicklogic/pp3/latches_map.v similarity index 100% rename from yosys/techlibs/quicklogic/pp3_latches_map.v rename to yosys/techlibs/quicklogic/pp3/latches_map.v diff --git a/yosys/techlibs/quicklogic/pp3_lut_map.v b/yosys/techlibs/quicklogic/pp3/lut_map.v similarity index 100% rename from yosys/techlibs/quicklogic/pp3_lut_map.v rename to yosys/techlibs/quicklogic/pp3/lut_map.v diff --git a/yosys/techlibs/quicklogic/ql_bram_merge.cc b/yosys/techlibs/quicklogic/ql_bram_merge.cc new file mode 100644 index 00000000000..bed1ba572df --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_bram_merge.cc @@ -0,0 +1,216 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + + +struct QlBramMergeWorker { + + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; + + RTLIL::Module *module; + dict> mergeable_groups; + + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } + + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } + + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } + + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); + + // Remove the old cells + module->remove(bram1); + module->remove(bram2); + + } + + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } + +}; + +struct QlBramMergePass : public Pass { + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } + + + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/quicklogic/ql_bram_types.cc b/yosys/techlibs/quicklogic/ql_bram_types.cc new file mode 100644 index 00000000000..cf42703aaac --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_bram_types.cc @@ -0,0 +1,165 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + +struct QlBramTypesPass : public Pass { + + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_types [selection]\n"); + log("\n"); + log(" This pass changes the type of TDP36K cells to different types based on the\n"); + log(" configuration of the cell.\n"); + log("\n"); + } + + int width_for_mode(int mode){ + // 1: mode = 3'b101; + // 2: mode = 3'b110; + // 4: mode = 3'b100; + // 8,9: mode = 3'b001; + // 16, 18: mode = 3'b010; + // 32, 36: mode = 3'b011; + switch (mode) + { + case 1: + return 9; + case 2: + return 18; + case 3: + return 36; + case 4: + return 4; + case 5: + return 1; + case 6: + return 2; + default: + log_error("Invalid mode: %x", mode); + } + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_TYPES pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + for (RTLIL::Cell* cell: module->selected_cells()) + { + if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) + continue; + + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); + + bool split = mode_bits.extract(80).as_bool(); + + bool FMODE1_i = mode_bits.extract(13).as_bool(); + bool FMODE2_i = mode_bits.extract(54).as_bool(); + if (FMODE1_i != FMODE2_i) { + log_debug("Can't change type of mixed use TDP36K block: FMODE1_i = %s, FMODE2_i = %s\n", FMODE1_i ? "true" : "false", FMODE2_i ? "true" : "false"); + continue; + } + bool is_fifo = FMODE1_i; + + bool SYNC_FIFO1_i = mode_bits.extract(0).as_bool(); + bool SYNC_FIFO2_i = mode_bits.extract(41).as_bool(); + if (SYNC_FIFO1_i != SYNC_FIFO2_i) { + log_debug("Can't change type of mixed use TDP36K block: SYNC_FIFO1_i = %s, SYNC_FIFO2_i = %s\n", SYNC_FIFO1_i ? "true" : "false", SYNC_FIFO2_i ? "true" : "false"); + continue; + } + bool sync_fifo = SYNC_FIFO1_i; + + int RMODE_A1_i = mode_bits.extract(1, 3).as_int(); + int RMODE_B1_i = mode_bits.extract(4, 3).as_int(); + int WMODE_A1_i = mode_bits.extract(7, 3).as_int(); + int WMODE_B1_i = mode_bits.extract(10, 3).as_int(); + + int RMODE_A2_i = mode_bits.extract(42, 3).as_int(); + int RMODE_B2_i = mode_bits.extract(45, 3).as_int(); + int WMODE_A2_i = mode_bits.extract(48, 3).as_int(); + int WMODE_B2_i = mode_bits.extract(51, 3).as_int(); + + // TODO: should these be a warning or an error? + if (RMODE_A1_i != WMODE_A1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A1_i), width_for_mode(WMODE_A1_i)); + continue; + } + if (RMODE_B1_i != WMODE_B1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B1_i), width_for_mode(WMODE_B1_i)); + continue; + } + if (RMODE_A2_i != WMODE_A2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A2_i), width_for_mode(WMODE_A2_i)); + continue; + } + if (RMODE_B2_i != WMODE_B2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B2_i), width_for_mode(WMODE_B2_i)); + continue; + } + + // TODO: For nonsplit blocks, should RMODE_A1_i == RMODE_A2_i etc be checked/enforced? + + std::string type = "TDP36K"; + if (is_fifo) { + type += "_FIFO_"; + if (sync_fifo) + type += "SYNC_"; + else + type += "ASYNC_"; + } else + type += "_BRAM_"; + + if (split) { + type += stringf("A1_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B1_X%d_", width_for_mode(RMODE_B1_i)); + type += stringf("A2_X%d_", width_for_mode(RMODE_A2_i)); + type += stringf("B2_X%d_", width_for_mode(RMODE_B2_i)); + type += "split"; + } else { + type += stringf("A_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B_X%d_", width_for_mode(RMODE_B1_i)); + type += "nonsplit"; + } + + cell->type = RTLIL::escape_id(type); + log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type)); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc b/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc new file mode 100644 index 00000000000..ecf163dbf6b --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -0,0 +1,157 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_REGISTER_INPUTS_ID 92 +#define MODE_BITS_OUTPUT_SELECT_START_ID 81 +#define MODE_BITS_OUTPUT_SELECT_WIDTH 3 + +// ============================================================================ + +struct QlDspIORegs : public Pass { + SigMap sigmap; + + // .......................................... + + QlDspIORegs() : Pass("ql_dsp_io_regs", "change types of QL_DSP2 depending on configuration") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_dsp_io_regs [options] [selection]\n"); + log("\n"); + log("This pass looks for QL_DSP2 cells and changes their cell type depending on their\n"); + log("configuration.\n"); + } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_io_regs_pass(module); + } + } + + void ql_dsp_io_regs_pass(RTLIL::Module *module) + { + static const std::vector ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b), + ID(saturate_enable), ID(shift_right), ID(round)}; + static const std::vector ports2del_mult_acc = {ID(acc_fir), ID(dly_b)}; + + + sigmap.set(module); + + for (auto cell : module->cells()) { + if (cell->type != ID(QL_DSP2)) + continue; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!cell->get_bool_attribute(ID(is_inferred))) + continue; + + // Get DSP configuration + for (auto cfg_port : {ID(register_inputs), ID(output_select)}) + if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const()) + log_error("Missing or non-constant '%s' port on DSP cell %s\n", + log_id(cfg_port), log_id(cell)); + int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); + int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int(); + + // Get the feedback port + if (!cell->hasPort(ID(feedback))) + log_error("Missing 'feedback' port on %s", log_id(cell)); + SigSpec feedback = sigmap(cell->getPort(ID(feedback))); + + // Check the top two bits on 'feedback' to be constant zero. + // That's what we are expecting from inference. + if (feedback.extract(1, 2) != SigSpec(0, 2)) + log_error("Unexpected feedback configuration on %s\n", log_id(cell)); + + // Build new type name + std::string new_type = "\\QL_DSP2_MULT"; + + // Decide if we should be deleting the clock port + bool del_clk = true; + + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + del_clk = false; + new_type += "ACC"; + break; + default: + break; + } + + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + + // Set new type name + cell->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + cell->unsetPort(ID(clk)); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + for (auto port : ports2del_mult) + cell->unsetPort(port); + break; + case 1: + case 2: + case 3: + case 5: + case 7: + for (auto port : ports2del_mult_acc) + cell->unsetPort(port); + break; + } + } + } +} QlDspIORegs; + +PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/quicklogic/ql_dsp_macc.cc b/yosys/techlibs/quicklogic/ql_dsp_macc.cc new file mode 100644 index 00000000000..f0669da6c9b --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_dsp_macc.cc @@ -0,0 +1,214 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "techlibs/quicklogic/ql_dsp_macc_pm.h" + +// ============================================================================ + +static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) +{ + auto &st = pm.st_ql_dsp_macc; + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool()); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + log_debug("\trejected: too wide (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } + + type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports"); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type)); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) + if (cell) + log(" %s (%s)\n", log_id(cell), log_id(cell->type)); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type); + + // Set attributes + cell->set_bool_attribute(ID(is_inferred), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a, sig_b, sig_z; + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + if (a_width < b_width) + std::swap(sig_a, sig_b); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, ab_signed); + sig_b.extend_u0(tgt_b_width, ab_signed); + cell->setPort(ID(a_i), sig_a); + cell->setPort(ID(b_i), sig_b); + + // Connect output data port, pad if needed + if ((size_t) GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(ID(z_o), sig_z); + + // Connect clock, reset and enable + cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(ID(reset_i), rst); + cell->setPort(ID(load_acc_i), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux_in_pattern) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab.in(ID(A), ID(B))); + if (st.mux_ab == ID(A)) + sig_s = pm.module->Not(NEW_ID, sig_s); + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(ID(feedback_i), sig_f); + } + // No acc clear/load + else { + cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3)); + + bool subtract = (st.add->type == ID($sub)); + cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); +} + +struct QlDspMacc : public Pass { + QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_dsp_macc [selection]\n"); + log("\n"); + log("This pass looks for a multiply-accumulate pattern based on which it infers a\n"); + log("QuickLogic DSP cell.\n"); + log("\n"); + } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) + ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + } + +} QlDspMacc; + +PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/quicklogic/ql_dsp_macc.pmg b/yosys/techlibs/quicklogic/ql_dsp_macc.pmg new file mode 100644 index 00000000000..df18596d109 --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_dsp_macc.pmg @@ -0,0 +1,77 @@ +pattern ql_dsp_macc +// Rough sketch: (mux is optional) +// +// /-----------------------\ +// | | +// \ / | +// mul ----> add -----> mux -----> ff -+----> +// | /\ +// | | +// -------------- + +state add_ba +state mux_ab + +// Is the output taken from before or after the FF? +state output_registered + +// Is there a mux in the pattern? +state mux_in_pattern + +code mux_in_pattern + mux_in_pattern = false; + branch; + mux_in_pattern = true; +endcode + +// The multiplier is at the center of our pattern +match mul + select mul->type.in($mul) + // It has either two or three consumers depending on whether there's a mux + // in the pattern or not + select nusers(port(mul, \Y)) <= 3 + filter nusers(port(mul, \Y)) == (mux_in_pattern ? 3 : 2) +endmatch + +code output_registered + output_registered = false; + branch; + output_registered = true; +endcode + +match add + select add->type.in($add, $sub) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + // One input to the adder is fed by the multiplier + index port(add, AB) === port(mul, \Y) + // Save the other input port, it needs to be fed by the flip-flop + set add_ba BA + // Adder has either two or three consumers; it will have three consumers + // IFF there's no mux in the pattern and the multiplier-accumulator result + // is taken unregistered + filter nusers(port(add, \Y)) == (!mux_in_pattern && !output_registered ? 3 : 2) +endmatch + +match mux + if mux_in_pattern + select mux->type.in($mux) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(mux, AB) === port(mul, \Y) + index port(mux, BA) === port(add, \Y) + filter nusers(port(mux, \Y)) == (output_registered ? 2 : 3) + set mux_ab AB +endmatch + +match ff + select ff->type.in($dff, $adff, $dffe, $adffe) + select param(ff, \CLK_POLARITY).as_bool() + index port(ff, \D) === mux_in_pattern ? port(mux, \Y) : port(add, \Y); + index port(ff, \Q) === port(add, add_ba) + filter nusers(port(ff, \Q)) == (output_registered ? 3 : 2) +endmatch + +code + accept; +endcode diff --git a/yosys/techlibs/quicklogic/ql_dsp_simd.cc b/yosys/techlibs/quicklogic/ql_dsp_simd.cc new file mode 100644 index 00000000000..9df979c3362 --- /dev/null +++ b/yosys/techlibs/quicklogic/ql_dsp_simd.cc @@ -0,0 +1,276 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + + +// ============================================================================ + +struct QlDspSimdPass : public Pass { + + QlDspSimdPass() : Pass("ql_dsp_simd", "merge QuickLogic K6N10f DSP pairs to operate in SIMD mode") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_dsp_simd [selection]\n"); + log("\n"); + log("This pass identifies K6N10f DSP cells with identical configuration and pack pairs\n"); + log("of them together into other DSP cells that can perform SIMD operation.\n"); + } + + // .......................................... + + /// Describes DSP config unique to a whole DSP cell + struct DspConfig { + // Port connections + dict connections; + + DspConfig() = default; + + DspConfig(const DspConfig &ref) = default; + DspConfig(DspConfig &&ref) = default; + + unsigned int hash() const { return connections.hash(); } + + bool operator==(const DspConfig &ref) const { return connections == ref.connections; } + }; + + // .......................................... + + const int m_ModeBitsSize = 80; + + // DSP parameters + const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; + + /// Temporary SigBit to SigBit helper map. + SigMap sigmap; + + // .......................................... + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_SIMD pass.\n"); + + // DSP control and config ports to consider and how to map them to ports + // of the target DSP cell + static const std::vector> m_DspCfgPorts = { + std::make_pair(ID(clock_i), ID(clk)), + std::make_pair(ID(reset_i), ID(reset)), + std::make_pair(ID(feedback_i), ID(feedback)), + std::make_pair(ID(load_acc_i), ID(load_acc)), + std::make_pair(ID(unsigned_a_i), ID(unsigned_a)), + std::make_pair(ID(unsigned_b_i), ID(unsigned_b)), + std::make_pair(ID(subtract_i), ID(subtract)), + std::make_pair(ID(output_select_i), ID(output_select)), + std::make_pair(ID(saturate_enable_i), ID(saturate_enable)), + std::make_pair(ID(shift_right_i), ID(shift_right)), + std::make_pair(ID(round_i), ID(round)), + std::make_pair(ID(register_inputs_i), ID(register_inputs)) + }; + + // DSP data ports and how to map them to ports of the target DSP cell + static const std::vector> m_DspDataPorts = { + std::make_pair(ID(a_i), ID(a)), + std::make_pair(ID(b_i), ID(b)), + std::make_pair(ID(acc_fir_i), ID(acc_fir)), + std::make_pair(ID(z_o), ID(z)), + std::make_pair(ID(dly_b_o), ID(dly_b)) + }; + + // Source DSP cell type (SISD) + static const IdString m_SisdDspType = ID(dsp_t1_10x9x32); + + // Target DSP cell types for the SIMD mode + static const IdString m_SimdDspType = ID(QL_DSP2); + + // Parse args + extra_args(a_Args, 1, a_Design); + + // Process modules + for (auto module : a_Design->selected_modules()) { + // Setup the SigMap + sigmap.set(module); + + // Assemble DSP cell groups + dict> groups; + for (auto cell : module->selected_cells()) { + // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) + if (cell->type != m_SisdDspType) + continue; + + // Skip if it has the (* keep *) attribute set + if (cell->has_keep_attr()) + continue; + + // Add to a group + const auto key = getDspConfig(cell, m_DspCfgPorts); + groups[key].push_back(cell); + } + + std::vector cellsToRemove; + + // Map cell pairs to the target DSP SIMD cell + for (const auto &it : groups) { + const auto &group = it.second; + const auto &config = it.first; + + // Ensure an even number + size_t count = group.size(); + if (count & 1) + count--; + + // Map SIMD pairs + for (size_t i = 0; i < count; i += 2) { + Cell *dsp_a = group[i]; + Cell *dsp_b = group[i + 1]; + + // Create the new cell + Cell *simd = module->addCell(NEW_ID, m_SimdDspType); + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type), + log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type)); + + // Check if the target cell is known (important to know + // its port widths) + if (!simd->known()) + log_error(" The target cell type '%s' is not known!", log_id(simd)); + + // Connect common ports + for (const auto &it : m_DspCfgPorts) + simd->setPort(it.first, config.connections.at(it.second)); + + // Connect data ports + for (const auto &it : m_DspDataPorts) { + size_t width; + bool isOutput; + + std::tie(width, isOutput) = getPortInfo(simd, it.second); + + auto getConnection = [&](const RTLIL::Cell *cell) { + RTLIL::SigSpec sigspec; + if (cell->hasPort(it.first)) { + const auto &sig = cell->getPort(it.first); + sigspec.append(sig); + } + + int padding = width / 2 - sigspec.bits().size(); + + if (padding) { + if (!isOutput) + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding)); + else + sigspec.append(module->addWire(NEW_ID, padding)); + } + return sigspec; + }; + + RTLIL::SigSpec sigspec; + sigspec.append(getConnection(dsp_a)); + sigspec.append(getConnection(dsp_b)); + simd->setPort(it.second, sigspec); + } + + // Concatenate FIR coefficient parameters into the single + // MODE_BITS parameter + Const mode_bits; + for (const auto &it : m_DspParams) { + auto val_a = dsp_a->getParam(it); + auto val_b = dsp_b->getParam(it); + + mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); + } + + // Enable the fractured mode by connecting the control + // port. + simd->setPort(ID(f_mode), State::S1); + simd->setParam(ID(MODE_BITS), mode_bits); + log_assert(mode_bits.size() == m_ModeBitsSize); + + // Handle the "is_inferred" attribute. If one of the fragments + // is not inferred mark the whole DSP as not inferred + bool is_inferred_a = dsp_a->get_bool_attribute(ID(is_inferred)); + bool is_inferred_b = dsp_b->get_bool_attribute(ID(is_inferred)); + simd->set_bool_attribute(ID(is_inferred), is_inferred_a && is_inferred_b); + + // Mark DSP parts for removal + cellsToRemove.push_back(dsp_a); + cellsToRemove.push_back(dsp_b); + } + } + + // Remove old cells + for (auto cell : cellsToRemove) + module->remove(cell); + } + } + + // .......................................... + + /// Looks up port width and direction in the cell definition and returns it. + /// Returns (0, false) if it cannot be determined. + std::pair getPortInfo(RTLIL::Cell *a_Cell, RTLIL::IdString a_Port) + { + if (!a_Cell->known()) { + return std::make_pair(0, false); + } + + // Get the module defining the cell (the previous condition ensures + // that the pointers are valid) + RTLIL::Module *mod = a_Cell->module->design->module(a_Cell->type); + if (mod == nullptr) { + return std::make_pair(0, false); + } + + // Get the wire representing the port + RTLIL::Wire *wire = mod->wire(a_Port); + if (wire == nullptr) { + return std::make_pair(0, false); + } + + return std::make_pair(wire->width, wire->port_output); + } + + /// Given a DSP cell populates and returns a DspConfig struct for it. + DspConfig getDspConfig(RTLIL::Cell *a_Cell, const std::vector> &dspCfgPorts) + { + DspConfig config; + + for (const auto &it : dspCfgPorts) { + auto port = it.first; + + // Port unconnected + if (!a_Cell->hasPort(port)) + continue; + + config.connections[port] = sigmap(a_Cell->getPort(port)); + } + + return config; + } +} QlDspSimdPass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore b/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore new file mode 100644 index 00000000000..b5ba978ce2a --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/.gitignore @@ -0,0 +1 @@ +/bram_types_sim.v diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v b/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v new file mode 100644 index 00000000000..68c2eb0aa13 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v @@ -0,0 +1,344 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module TDP18K_FIFO ( + RMODE_A_i, + RMODE_B_i, + WMODE_A_i, + WMODE_B_i, + WEN_A_i, + WEN_B_i, + REN_A_i, + REN_B_i, + CLK_A_i, + CLK_B_i, + BE_A_i, + BE_B_i, + ADDR_A_i, + ADDR_B_i, + WDATA_A_i, + WDATA_B_i, + RDATA_A_o, + RDATA_B_o, + EMPTY_o, + EPO_o, + EWM_o, + UNDERRUN_o, + FULL_o, + FMO_o, + FWM_o, + OVERRUN_o, + FLUSH_ni, + FMODE_i, +); + parameter SYNC_FIFO_i = 1'b0; + parameter POWERDN_i = 1'b0; + parameter SLEEP_i = 1'b0; + parameter PROTECT_i = 1'b0; + parameter UPAF_i = 11'b0; + parameter UPAE_i = 11'b0; + parameter [18*1024-1:0] INIT_i = 18431'bx; + + input wire [2:0] RMODE_A_i; + input wire [2:0] RMODE_B_i; + input wire [2:0] WMODE_A_i; + input wire [2:0] WMODE_B_i; + input wire WEN_A_i; + input wire WEN_B_i; + input wire REN_A_i; + input wire REN_B_i; + (* clkbuf_sink *) + input wire CLK_A_i; + (* clkbuf_sink *) + input wire CLK_B_i; + input wire [1:0] BE_A_i; + input wire [1:0] BE_B_i; + input wire [13:0] ADDR_A_i; + input wire [13:0] ADDR_B_i; + input wire [17:0] WDATA_A_i; + input wire [17:0] WDATA_B_i; + output reg [17:0] RDATA_A_o; + output reg [17:0] RDATA_B_o; + output wire EMPTY_o; + output wire EPO_o; + output wire EWM_o; + output wire UNDERRUN_o; + output wire FULL_o; + output wire FMO_o; + output wire FWM_o; + output wire OVERRUN_o; + input wire FLUSH_ni; + input wire FMODE_i; + reg [17:0] wmsk_a; + reg [17:0] wmsk_b; + wire [8:0] addr_a; + wire [8:0] addr_b; + reg [4:0] addr_a_d; + reg [4:0] addr_b_d; + wire [17:0] ram_rdata_a; + wire [17:0] ram_rdata_b; + reg [17:0] aligned_wdata_a; + reg [17:0] aligned_wdata_b; + wire ren_o; + wire [10:0] ff_raddr; + wire [10:0] ff_waddr; + wire [13:0] ram_addr_a; + wire [13:0] ram_addr_b; + wire [3:0] ram_waddr_a; + wire [3:0] ram_waddr_b; + wire initn; + wire smux_rclk; + wire smux_wclk; + wire real_fmode; + wire [3:0] raw_fflags; + reg [1:0] fifo_rmode; + reg [1:0] fifo_wmode; + wire smux_clk_a; + wire smux_clk_b; + wire ram_ren_a; + wire ram_ren_b; + wire ram_wen_a; + wire ram_wen_b; + wire cen_a; + wire cen_b; + wire cen_a_n; + wire cen_b_n; + wire ram_wen_a_n; + wire ram_wen_b_n; + localparam MODE_9 = 3'b001; + always @(*) begin + fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01); + fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01); + end + assign smux_clk_a = CLK_A_i; + assign smux_clk_b = CLK_B_i; + assign real_fmode = FMODE_i; + assign ram_ren_b = real_fmode ? ren_o : REN_B_i; + assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i; + assign ram_ren_a = FMODE_i ? 0 : REN_A_i; + assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i; + assign cen_b = ram_ren_b | ram_wen_b; + assign cen_a = ram_ren_a | ram_wen_a; + assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0]; + assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0]; + assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]}; + assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]}; + always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0]; + always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0]; + assign cen_a_n = ~cen_a; + assign ram_wen_a_n = ~ram_wen_a; + assign cen_b_n = ~cen_b; + assign ram_wen_b_n = ~ram_wen_b; + + sram1024x18 #( + .init(INIT_i) + ) uram( + .clk_a(smux_clk_a), + .cen_a(cen_a_n), + .wen_a(ram_wen_a_n), + .addr_a(ram_addr_a[13:4]), + .wmsk_a(wmsk_a), + .wdata_a(aligned_wdata_a), + .rdata_a(ram_rdata_a), + .clk_b(smux_clk_b), + .cen_b(cen_b_n), + .wen_b(ram_wen_b_n), + .addr_b(ram_addr_b[13:4]), + .wmsk_b(wmsk_b), + .wdata_b(aligned_wdata_b), + .rdata_b(ram_rdata_b) + ); + fifo_ctl #( + .ADDR_WIDTH(11), + .FIFO_WIDTH(2), + .DEPTH(6) + ) fifo_ctl( + .rclk(smux_clk_b), + .rst_R_n(FLUSH_ni), + .wclk(smux_clk_a), + .rst_W_n(FLUSH_ni), + .ren(REN_B_i), + .wen(ram_wen_a), + .sync(SYNC_FIFO_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF_i), + .upae(UPAE_i) + ); + localparam MODE_1 = 3'b101; + localparam MODE_18 = 3'b010; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : WDATA_MODE_SEL + if (ram_wen_a == 1) begin + case (WMODE_A_i) + MODE_18: begin + aligned_wdata_a = WDATA_A_i; + {wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff)); + {wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff)); + end + MODE_9: begin + aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}}; + {wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff); + {wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}}; + wmsk_a = 18'h0ffff; + wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0; + end + default: wmsk_a = 18'h3ffff; + endcase + end + else begin + aligned_wdata_a = 18'h00000; + wmsk_a = 18'h3ffff; + end + if (ram_wen_b == 1) + case (WMODE_B_i) + MODE_18: begin + aligned_wdata_b = WDATA_B_i; + {wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff); + end + MODE_9: begin + aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}}; + {wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}}; + wmsk_b = 18'h0ffff; + wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0; + end + default: wmsk_b = 18'h3ffff; + endcase + else begin + aligned_wdata_b = 18'b000000000000000000; + wmsk_b = 18'h3ffff; + end + end + always @(*) begin : RDATA_A_MODE_SEL + case (RMODE_A_i) + default: RDATA_A_o = 18'h00000; + MODE_18: RDATA_A_o = ram_rdata_a; + MODE_9: begin + {RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000; + {RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]}); + end + MODE_4: begin + RDATA_A_o[17:4] = 14'h0000; + case (ram_addr_a[3:2]) + 3: RDATA_A_o[3:0] = ram_rdata_a[15:12]; + 2: RDATA_A_o[3:0] = ram_rdata_a[11:8]; + 1: RDATA_A_o[3:0] = ram_rdata_a[7:4]; + 0: RDATA_A_o[3:0] = ram_rdata_a[3:0]; + endcase + end + MODE_2: begin + RDATA_A_o[17:2] = 16'h0000; + case (ram_addr_a[3:1]) + 7: RDATA_A_o[1:0] = ram_rdata_a[15:14]; + 6: RDATA_A_o[1:0] = ram_rdata_a[13:12]; + 5: RDATA_A_o[1:0] = ram_rdata_a[11:10]; + 4: RDATA_A_o[1:0] = ram_rdata_a[9:8]; + 3: RDATA_A_o[1:0] = ram_rdata_a[7:6]; + 2: RDATA_A_o[1:0] = ram_rdata_a[5:4]; + 1: RDATA_A_o[1:0] = ram_rdata_a[3:2]; + 0: RDATA_A_o[1:0] = ram_rdata_a[1:0]; + endcase + end + MODE_1: begin + RDATA_A_o[17:1] = 17'h00000; + RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]]; + end + endcase + end + always @(*) + case (RMODE_B_i) + default: RDATA_B_o = 18'h15566; + MODE_18: RDATA_B_o = ram_rdata_b; + MODE_9: begin + {RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000; + {RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]}); + end + MODE_4: + case (ram_addr_b[3:2]) + 3: RDATA_B_o[3:0] = ram_rdata_b[15:12]; + 2: RDATA_B_o[3:0] = ram_rdata_b[11:8]; + 1: RDATA_B_o[3:0] = ram_rdata_b[7:4]; + 0: RDATA_B_o[3:0] = ram_rdata_b[3:0]; + endcase + MODE_2: + case (ram_addr_b[3:1]) + 7: RDATA_B_o[1:0] = ram_rdata_b[15:14]; + 6: RDATA_B_o[1:0] = ram_rdata_b[13:12]; + 5: RDATA_B_o[1:0] = ram_rdata_b[11:10]; + 4: RDATA_B_o[1:0] = ram_rdata_b[9:8]; + 3: RDATA_B_o[1:0] = ram_rdata_b[7:6]; + 2: RDATA_B_o[1:0] = ram_rdata_b[5:4]; + 1: RDATA_B_o[1:0] = ram_rdata_b[3:2]; + 0: RDATA_B_o[1:0] = ram_rdata_b[1:0]; + endcase + MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}]; + endcase +endmodule +`default_nettype none diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v new file mode 100644 index 00000000000..d39a3a19f9a --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -0,0 +1,99 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 2; + parameter B_WIDTH = 2; + parameter Y_WIDTH = 2; + parameter _TECHMAP_CONSTVAL_CI_ = 0; + parameter _TECHMAP_CONSTMSK_CI_ = 0; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + + genvar i; + wire co; + + (* force_downto *) + //wire [Y_WIDTH-1:0] C = {CO, CI}; + wire [Y_WIDTH:0] C; + (* force_downto *) + wire [Y_WIDTH-1:0] S = {AA ^ BB}; + assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; + //assign CO[Y_WIDTH-1] = co; + + generate + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); + endgenerate + genvar i; + generate if (Y_WIDTH > 2) begin + for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice + adder_carry my_adder ( + .cin (C[i]), + .g (AA[i]), + .p (S[i]), + .cout (C[i+1]), + .sumout (Y[i]) + ); + end + end endgenerate + generate + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); + endgenerate + + assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + + assign X = S; +endmodule + diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v new file mode 100644 index 00000000000..ba6382a2395 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -0,0 +1,4288 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); +localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +localparam PORT_A_WRWIDTH = rwmode(PORT_A_DWIDTH); +localparam PORT_B_WRWIDTH = rwmode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule \ No newline at end of file diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v new file mode 100644 index 00000000000..de6d992335a --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -0,0 +1,10949 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +`timescale 1ns /10ps + +`default_nettype none + +module TDP36K ( + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + + function [18431:0] split_init; + input index; + integer i; + for (i = 0; i < 1024; i = i + 1) begin + split_init[i * 18 +: 18] = RAM_INIT[i * 36 + index * 18 +: 18]; + end + endfunction + + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i), + .INIT_i(split_init(0)) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i), + .INIT_i(split_init(1)) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 2'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 2'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = WR1_DATA_WIDTH *) +(* port_a2_dwidth = WR2_DATA_WIDTH *) +(* port_b1_dwidth = RD1_DATA_WIDTH *) +(* port_b2_dwidth = RD2_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 2'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 2'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = WR1_DATA_WIDTH *) +(* port_b_dwidth = RD1_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = WR_DATA_WIDTH *) +(* port_b_width = RD_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = PORT_A1_DWIDTH *) +(* port_a2_dwidth = PORT_A2_DWIDTH *) +(* port_b1_dwidth = PORT_B1_DWIDTH *) +(* port_b2_dwidth = PORT_B2_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = PORT_A1_DWIDTH *) +(* port_b_dwidth = PORT_B1_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = PORT_A_DWIDTH *) +(* port_b_width = PORT_B_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + +//=============================================================================== +module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule \ No newline at end of file diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v new file mode 100644 index 00000000000..ddfd51ee7ce --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -0,0 +1,375 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none +(* abc9_lut=1 *) +module LUT1(output wire O, input wire I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify +endmodule + +(* abc9_lut=2 *) +module LUT2(output wire O, input wire I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT3(output wire O, input wire I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT4(output wire O, input wire I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT5(output wire O, input wire I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify +endmodule + +(* abc9_lut=5 *) +module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module sh_dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + + initial Q = 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify + +endmodule + +(* abc9_box, lib_whitebox *) +(* keep *) +module adder_carry( + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin +); + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q = 1'b0; + + always @(posedge C) + Q <= D; + + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q = 1'b0; + + always @(negedge C) + Q <= D; + + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q = 1'b0; + + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q = 1'b0; + + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q = 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q = 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchnsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify + +endmodule + diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v new file mode 100644 index 00000000000..9eae617b90f --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v @@ -0,0 +1,265 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module dsp_t1_20x18x64_cfg_ports ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 # ( + .MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b0), // No fracturation + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP2 # ( + .MODE_BITS ({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b1), // Enable fractuation, Use the lower half + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v new file mode 100644 index 00000000000..127145b71a9 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -0,0 +1,102 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [19:0] a; + wire [17:0] b; + wire [37:0] z; + + assign a = (A_WIDTH == 20) ? A : + (A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(20 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 18) ? B : + (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{(18 - B_WIDTH){1'b0}}, B}; + + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + + assign Y = z; + +endmodule + +module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [ 9:0] a; + wire [ 8:0] b; + wire [18:0] z; + + assign a = (A_WIDTH == 10) ? A : + (A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(10 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 9) ? B : + (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{( 9 - B_WIDTH){1'b0}}, B}; + + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + + + assign Y = z; + +endmodule diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v new file mode 100644 index 00000000000..5f43b322912 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -0,0 +1,4527 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none + +(* blackbox *) +module QL_DSP1 ( + input wire [19:0] a, + input wire [17:0] b, + (* clkbuf_sink *) + input wire clk0, + (* clkbuf_sink *) + input wire clk1, + input wire [ 1:0] feedback0, + input wire [ 1:0] feedback1, + input wire load_acc0, + input wire load_acc1, + input wire reset0, + input wire reset1, + output reg [37:0] z +); + parameter MODE_BITS = 27'b00000000000000000000000000; +endmodule /* QL_DSP1 */ + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// --------- Control bits in ports -------- // +// ---------------------------------------- // + +module QL_DSP2 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire saturate_enable, + input wire [5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + wire [NBITS_Z-1:0] dsp_full_z; + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [NBITS_B-1:0] dsp_full_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + assign z = f_mode ? {dsp_frac1_z, dsp_frac0_z} : dsp_full_z; + assign dly_b = f_mode ? {dsp_frac1_dly_b, dsp_frac0_dly_b} : dsp_full_dly_b; + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + // Output used when fmode == 0 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A), + .NBITS_B(NBITS_B), + .NBITS_ACC(NBITS_ACC), + .NBITS_Z(NBITS_Z) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(dsp_full_z), + .dly_b_o(dsp_full_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); +endmodule + +module QL_DSP2_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .clk(1'b0), + .reset(reset), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + //.clk(1'b0), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + (subtract => z[0]) = 0; + (subtract => z[1]) = 0; + (subtract => z[2]) = 0; + (subtract => z[3]) = 0; + (subtract => z[4]) = 0; + (subtract => z[5]) = 0; + (subtract => z[6]) = 0; + (subtract => z[7]) = 0; + (subtract => z[8]) = 0; + (subtract => z[9]) = 0; + (subtract => z[10]) = 0; + (subtract => z[11]) = 0; + (subtract => z[12]) = 0; + (subtract => z[13]) = 0; + (subtract => z[14]) = 0; + (subtract => z[15]) = 0; + (subtract => z[16]) = 0; + (subtract => z[17]) = 0; + (subtract => z[18]) = 0; + (subtract => z[19]) = 0; + (subtract => z[20]) = 0; + (subtract => z[21]) = 0; + (subtract => z[22]) = 0; + (subtract => z[23]) = 0; + (subtract => z[24]) = 0; + (subtract => z[25]) = 0; + (subtract => z[26]) = 0; + (subtract => z[27]) = 0; + (subtract => z[28]) = 0; + (subtract => z[29]) = 0; + (subtract => z[30]) = 0; + (subtract => z[31]) = 0; + (subtract => z[32]) = 0; + (subtract => z[33]) = 0; + (subtract => z[34]) = 0; + (subtract => z[35]) = 0; + (subtract => z[36]) = 0; + (subtract => z[37]) = 0; + (acc_fir[0] => z[0]) = 0; + (acc_fir[1] => z[0]) = 0; + (acc_fir[2] => z[0]) = 0; + (acc_fir[3] => z[0]) = 0; + (acc_fir[4] => z[0]) = 0; + (acc_fir[5] => z[0]) = 0; + (acc_fir[0] => z[1]) = 0; + (acc_fir[1] => z[1]) = 0; + (acc_fir[2] => z[1]) = 0; + (acc_fir[3] => z[1]) = 0; + (acc_fir[4] => z[1]) = 0; + (acc_fir[5] => z[1]) = 0; + (acc_fir[0] => z[2]) = 0; + (acc_fir[1] => z[2]) = 0; + (acc_fir[2] => z[2]) = 0; + (acc_fir[3] => z[2]) = 0; + (acc_fir[4] => z[2]) = 0; + (acc_fir[5] => z[2]) = 0; + (acc_fir[0] => z[3]) = 0; + (acc_fir[1] => z[3]) = 0; + (acc_fir[2] => z[3]) = 0; + (acc_fir[3] => z[3]) = 0; + (acc_fir[4] => z[3]) = 0; + (acc_fir[5] => z[3]) = 0; + (acc_fir[0] => z[4]) = 0; + (acc_fir[1] => z[4]) = 0; + (acc_fir[2] => z[4]) = 0; + (acc_fir[3] => z[4]) = 0; + (acc_fir[4] => z[4]) = 0; + (acc_fir[5] => z[4]) = 0; + (acc_fir[0] => z[5]) = 0; + (acc_fir[1] => z[5]) = 0; + (acc_fir[2] => z[5]) = 0; + (acc_fir[3] => z[5]) = 0; + (acc_fir[4] => z[5]) = 0; + (acc_fir[5] => z[5]) = 0; + (acc_fir[0] => z[6]) = 0; + (acc_fir[1] => z[6]) = 0; + (acc_fir[2] => z[6]) = 0; + (acc_fir[3] => z[6]) = 0; + (acc_fir[4] => z[6]) = 0; + (acc_fir[5] => z[6]) = 0; + (acc_fir[0] => z[7]) = 0; + (acc_fir[1] => z[7]) = 0; + (acc_fir[2] => z[7]) = 0; + (acc_fir[3] => z[7]) = 0; + (acc_fir[4] => z[7]) = 0; + (acc_fir[5] => z[7]) = 0; + (acc_fir[0] => z[8]) = 0; + (acc_fir[1] => z[8]) = 0; + (acc_fir[2] => z[8]) = 0; + (acc_fir[3] => z[8]) = 0; + (acc_fir[4] => z[8]) = 0; + (acc_fir[5] => z[8]) = 0; + (acc_fir[0] => z[9]) = 0; + (acc_fir[1] => z[9]) = 0; + (acc_fir[2] => z[9]) = 0; + (acc_fir[3] => z[9]) = 0; + (acc_fir[4] => z[9]) = 0; + (acc_fir[5] => z[9]) = 0; + (acc_fir[0] => z[10]) = 0; + (acc_fir[1] => z[10]) = 0; + (acc_fir[2] => z[10]) = 0; + (acc_fir[3] => z[10]) = 0; + (acc_fir[4] => z[10]) = 0; + (acc_fir[5] => z[10]) = 0; + (acc_fir[0] => z[11]) = 0; + (acc_fir[1] => z[11]) = 0; + (acc_fir[2] => z[11]) = 0; + (acc_fir[3] => z[11]) = 0; + (acc_fir[4] => z[11]) = 0; + (acc_fir[5] => z[11]) = 0; + (acc_fir[0] => z[12]) = 0; + (acc_fir[1] => z[12]) = 0; + (acc_fir[2] => z[12]) = 0; + (acc_fir[3] => z[12]) = 0; + (acc_fir[4] => z[12]) = 0; + (acc_fir[5] => z[12]) = 0; + (acc_fir[0] => z[13]) = 0; + (acc_fir[1] => z[13]) = 0; + (acc_fir[2] => z[13]) = 0; + (acc_fir[3] => z[13]) = 0; + (acc_fir[4] => z[13]) = 0; + (acc_fir[5] => z[13]) = 0; + (acc_fir[0] => z[14]) = 0; + (acc_fir[1] => z[14]) = 0; + (acc_fir[2] => z[14]) = 0; + (acc_fir[3] => z[14]) = 0; + (acc_fir[4] => z[14]) = 0; + (acc_fir[5] => z[14]) = 0; + (acc_fir[0] => z[15]) = 0; + (acc_fir[1] => z[15]) = 0; + (acc_fir[2] => z[15]) = 0; + (acc_fir[3] => z[15]) = 0; + (acc_fir[4] => z[15]) = 0; + (acc_fir[5] => z[15]) = 0; + (acc_fir[0] => z[16]) = 0; + (acc_fir[1] => z[16]) = 0; + (acc_fir[2] => z[16]) = 0; + (acc_fir[3] => z[16]) = 0; + (acc_fir[4] => z[16]) = 0; + (acc_fir[5] => z[16]) = 0; + (acc_fir[0] => z[17]) = 0; + (acc_fir[1] => z[17]) = 0; + (acc_fir[2] => z[17]) = 0; + (acc_fir[3] => z[17]) = 0; + (acc_fir[4] => z[17]) = 0; + (acc_fir[5] => z[17]) = 0; + (acc_fir[0] => z[18]) = 0; + (acc_fir[1] => z[18]) = 0; + (acc_fir[2] => z[18]) = 0; + (acc_fir[3] => z[18]) = 0; + (acc_fir[4] => z[18]) = 0; + (acc_fir[5] => z[18]) = 0; + (acc_fir[0] => z[19]) = 0; + (acc_fir[1] => z[19]) = 0; + (acc_fir[2] => z[19]) = 0; + (acc_fir[3] => z[19]) = 0; + (acc_fir[4] => z[19]) = 0; + (acc_fir[5] => z[19]) = 0; + (acc_fir[0] => z[20]) = 0; + (acc_fir[1] => z[20]) = 0; + (acc_fir[2] => z[20]) = 0; + (acc_fir[3] => z[20]) = 0; + (acc_fir[4] => z[20]) = 0; + (acc_fir[5] => z[20]) = 0; + (acc_fir[0] => z[21]) = 0; + (acc_fir[1] => z[21]) = 0; + (acc_fir[2] => z[21]) = 0; + (acc_fir[3] => z[21]) = 0; + (acc_fir[4] => z[21]) = 0; + (acc_fir[5] => z[21]) = 0; + (acc_fir[0] => z[22]) = 0; + (acc_fir[1] => z[22]) = 0; + (acc_fir[2] => z[22]) = 0; + (acc_fir[3] => z[22]) = 0; + (acc_fir[4] => z[22]) = 0; + (acc_fir[5] => z[22]) = 0; + (acc_fir[0] => z[23]) = 0; + (acc_fir[1] => z[23]) = 0; + (acc_fir[2] => z[23]) = 0; + (acc_fir[3] => z[23]) = 0; + (acc_fir[4] => z[23]) = 0; + (acc_fir[5] => z[23]) = 0; + (acc_fir[0] => z[24]) = 0; + (acc_fir[1] => z[24]) = 0; + (acc_fir[2] => z[24]) = 0; + (acc_fir[3] => z[24]) = 0; + (acc_fir[4] => z[24]) = 0; + (acc_fir[5] => z[24]) = 0; + (acc_fir[0] => z[25]) = 0; + (acc_fir[1] => z[25]) = 0; + (acc_fir[2] => z[25]) = 0; + (acc_fir[3] => z[25]) = 0; + (acc_fir[4] => z[25]) = 0; + (acc_fir[5] => z[25]) = 0; + (acc_fir[0] => z[26]) = 0; + (acc_fir[1] => z[26]) = 0; + (acc_fir[2] => z[26]) = 0; + (acc_fir[3] => z[26]) = 0; + (acc_fir[4] => z[26]) = 0; + (acc_fir[5] => z[26]) = 0; + (acc_fir[0] => z[27]) = 0; + (acc_fir[1] => z[27]) = 0; + (acc_fir[2] => z[27]) = 0; + (acc_fir[3] => z[27]) = 0; + (acc_fir[4] => z[27]) = 0; + (acc_fir[5] => z[27]) = 0; + (acc_fir[0] => z[28]) = 0; + (acc_fir[1] => z[28]) = 0; + (acc_fir[2] => z[28]) = 0; + (acc_fir[3] => z[28]) = 0; + (acc_fir[4] => z[28]) = 0; + (acc_fir[5] => z[28]) = 0; + (acc_fir[0] => z[29]) = 0; + (acc_fir[1] => z[29]) = 0; + (acc_fir[2] => z[29]) = 0; + (acc_fir[3] => z[29]) = 0; + (acc_fir[4] => z[29]) = 0; + (acc_fir[5] => z[29]) = 0; + (acc_fir[0] => z[30]) = 0; + (acc_fir[1] => z[30]) = 0; + (acc_fir[2] => z[30]) = 0; + (acc_fir[3] => z[30]) = 0; + (acc_fir[4] => z[30]) = 0; + (acc_fir[5] => z[30]) = 0; + (acc_fir[0] => z[31]) = 0; + (acc_fir[1] => z[31]) = 0; + (acc_fir[2] => z[31]) = 0; + (acc_fir[3] => z[31]) = 0; + (acc_fir[4] => z[31]) = 0; + (acc_fir[5] => z[31]) = 0; + (acc_fir[0] => z[32]) = 0; + (acc_fir[1] => z[32]) = 0; + (acc_fir[2] => z[32]) = 0; + (acc_fir[3] => z[32]) = 0; + (acc_fir[4] => z[32]) = 0; + (acc_fir[5] => z[32]) = 0; + (acc_fir[0] => z[33]) = 0; + (acc_fir[1] => z[33]) = 0; + (acc_fir[2] => z[33]) = 0; + (acc_fir[3] => z[33]) = 0; + (acc_fir[4] => z[33]) = 0; + (acc_fir[5] => z[33]) = 0; + (acc_fir[0] => z[34]) = 0; + (acc_fir[1] => z[34]) = 0; + (acc_fir[2] => z[34]) = 0; + (acc_fir[3] => z[34]) = 0; + (acc_fir[4] => z[34]) = 0; + (acc_fir[5] => z[34]) = 0; + (acc_fir[0] => z[35]) = 0; + (acc_fir[1] => z[35]) = 0; + (acc_fir[2] => z[35]) = 0; + (acc_fir[3] => z[35]) = 0; + (acc_fir[4] => z[35]) = 0; + (acc_fir[5] => z[35]) = 0; + (acc_fir[0] => z[36]) = 0; + (acc_fir[1] => z[36]) = 0; + (acc_fir[2] => z[36]) = 0; + (acc_fir[3] => z[36]) = 0; + (acc_fir[4] => z[36]) = 0; + (acc_fir[5] => z[36]) = 0; + (acc_fir[0] => z[37]) = 0; + (acc_fir[1] => z[37]) = 0; + (acc_fir[2] => z[37]) = 0; + (acc_fir[3] => z[37]) = 0; + (acc_fir[4] => z[37]) = 0; + (acc_fir[5] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire load_acc, + input wire [ 2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module dsp_t1_20x18x64_cfg_ports ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .f_mode(1'b0), // 20x18x64 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP2 #( + .MODE_BITS({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) dsp ( + .a({10'd0, a_i}), + .b({9'd0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .f_mode(1'b1), // 10x9x32 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_sim_cfg_ports # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire saturate_enable_i, + input wire [2:0] output_select_i, + input wire round_i, + input wire [5:0] shift_right_i, + input wire subtract_i, + input wire register_inputs_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= shift_right_i; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = register_inputs_i ? r_a : a_i; + wire [NBITS_B-1:0] b = register_inputs_i ? r_b : b_i; + + wire [5:0] acc_fir = register_inputs_i ? r_acc_fir : acc_fir_i; + wire unsigned_a = register_inputs_i ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = register_inputs_i ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = register_inputs_i ? r_feedback : feedback_i; + wire load_acc = register_inputs_i ? r_load_acc : load_acc_i; + wire subtract = register_inputs_i ? r_subtract : subtract_i; + wire sat = register_inputs_i ? r_sat : saturate_enable_i; + wire rnd = register_inputs_i ? r_rnd : round_i; + + // Shift right control + wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i; + wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (output_select_i[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (shift_right_i != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_right_i - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> shift_right_i) : + (acc_rnd >>> shift_right_i); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (output_select_i == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (output_select_i == 3'h0) ? z0 : + (output_select_i == 3'h1) ? z2 : + (output_select_i == 3'h2) ? z2 : + (output_select_i == 3'h3) ? z2 : + (output_select_i == 3'h4) ? z1 : + (output_select_i == 3'h5) ? z1 : + (output_select_i == 3'h6) ? z1 : + z1; // if output_select_i == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v new file mode 100644 index 00000000000..43a71b425a1 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -0,0 +1,133 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +// DFF, asynchronous set/reset, enable +module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +// DFF, synchronous set or reset, enable +module \$_SDFFE_PN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_PN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +module \$_SDFFE_NN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_NN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +// Latch, no set/reset, no enable +module \$_DLATCH_P_ (input E, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +module \$_DLATCH_N_ (input E, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +// Latch with async set and reset and enable +module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$__SHREG_DFF_P_ (D, Q, C); + input D; + input C; + output Q; + + parameter DEPTH = 2; + + reg [DEPTH-2:0] q; + + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate + end: slice + endgenerate + +endmodule + diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py new file mode 100644 index 00000000000..e57c04a0887 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -0,0 +1,248 @@ +import sys +from datetime import datetime, timezone + +def generate(filename): + with open(filename, "w") as f: + f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n") + f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n") + + f.write("`timescale 1ns /10ps\n") + for a_width in [1,2,4,9,18,36]: + for b_width in [1,2,4,9,18,36]: + f.write(f""" +module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + + for a1_width in [1,2,4,9,18]: + for b1_width in [1,2,4,9,18]: + for a2_width in [1,2,4,9,18]: + for b2_width in [1,2,4,9,18]: + f.write(f""" +module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + +if __name__ == "__main__": + filename = "bram_types_sim.v" + if len(sys.argv) > 1: + filename = sys.argv[1] + generate(filename) diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt new file mode 100644 index 00000000000..3317956f822 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt @@ -0,0 +1,22 @@ +ram block $__QLF_TDP36K { + init any; + byte 9; + option "SPLIT" 0 { + abits 15; + widths 1 2 4 9 18 36 per_port; + } + option "SPLIT" 1 { + abits 14; + widths 1 2 4 9 18 per_port; + } + cost 65; + port srsw "A" "B" { + width tied; + clock posedge; + # wen causes read even when ren is low + # map clken = wen || ren + clken; + wrbe_separate; + rdwr old; + } +} diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v new file mode 100644 index 00000000000..3a5641bb880 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -0,0 +1,483 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, + PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); + +parameter INIT = 0; + +parameter OPTION_SPLIT = 0; + +parameter PORT_A_WIDTH = 1; +parameter PORT_A_WR_BE_WIDTH = 1; + +parameter PORT_B_WIDTH = 1; +parameter PORT_B_WR_BE_WIDTH = 1; + +input PORT_A_CLK; +input [14:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +input PORT_A_WR_EN; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input PORT_A_CLK_EN; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +input PORT_B_CLK; +input [14:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +input PORT_B_WR_EN; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input PORT_B_CLK_EN; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin + ri = INIT[i*36 +: 36]; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], + ri[17], ri[8], ri[16:9], ri[7:0]}; + end + if (OPTION_SPLIT) + pack_init[36863:18432] = 18432'bx; +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_WIDTH); + +assign REN_A1_i = PORT_A_CLK_EN; +assign WEN_A1_i = PORT_A_CLK_EN & PORT_A_WR_EN; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_CLK_EN; +assign WEN_B1_i = PORT_B_CLK_EN & PORT_B_WR_EN; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +case (PORT_A_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +36: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0], WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0]} = PORT_A_WR_DATA; +default: assign WDATA_A1_i = PORT_A_WR_DATA; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +36: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0], WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0]} = PORT_B_WR_DATA; +default: assign WDATA_B1_i = PORT_B_WR_DATA; // 1,2,4 +endcase + +case (PORT_A_WIDTH) +9: assign PORT_A_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +36: assign PORT_A_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0], RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0]}; +default: assign PORT_A_RD_DATA = RDATA_A1_o; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign PORT_B_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +36: assign PORT_B_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0], RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0]}; +default: assign PORT_B_RD_DATA = RDATA_B1_o; // 1,2,4 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* was_split_candidate = OPTION_SPLIT *) +(* port_a_width = PORT_A_WIDTH *) +(* port_b_width = PORT_B_WIDTH *) +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module \$__QLF_TDP36K_MERGED (...); + +parameter INIT1 = 0; + +parameter PORT_A1_WIDTH = 1; +parameter PORT_B1_WIDTH = 1; + +parameter PORT_A1_WR_BE_WIDTH = 1; +parameter PORT_B1_WR_BE_WIDTH = 1; + +input PORT_A1_CLK; +input [14:0] PORT_A1_ADDR; +input [PORT_A1_WIDTH-1:0] PORT_A1_WR_DATA; +input PORT_A1_WR_EN; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE; +input PORT_A1_CLK_EN; +output [PORT_A1_WIDTH-1:0] PORT_A1_RD_DATA; + +input PORT_B1_CLK; +input [14:0] PORT_B1_ADDR; +input [PORT_B1_WIDTH-1:0] PORT_B1_WR_DATA; +input PORT_B1_WR_EN; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE; +input PORT_B1_CLK_EN; +output [PORT_B1_WIDTH-1:0] PORT_B1_RD_DATA; + +parameter INIT2 = 0; + +parameter PORT_A2_WIDTH = 1; +parameter PORT_B2_WIDTH = 1; +parameter PORT_A2_WR_BE_WIDTH = 1; +parameter PORT_B2_WR_BE_WIDTH = 1; + +input PORT_A2_CLK; +input [14:0] PORT_A2_ADDR; +input [PORT_A2_WIDTH-1:0] PORT_A2_WR_DATA; +input PORT_A2_WR_EN; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE; +input PORT_A2_CLK_EN; +output [PORT_A2_WIDTH-1:0] PORT_A2_RD_DATA; + +input PORT_B2_CLK; +input [14:0] PORT_B2_ADDR; +input [PORT_B2_WIDTH-1:0] PORT_B2_WR_DATA; +input PORT_B2_WR_EN; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE; +input PORT_B2_CLK_EN; +output [PORT_B2_WIDTH-1:0] PORT_B2_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +default: mode = 3'b000; +endcase +endfunction + +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < 1024; i = i + 1) begin + ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]}; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]}; + end +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_WIDTH); + +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_WIDTH); + +assign REN_A1_i = PORT_A1_CLK_EN; +assign WEN_A1_i = PORT_A1_CLK_EN & PORT_A1_WR_EN; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_B1_i = PORT_B1_CLK_EN; +assign WEN_B1_i = PORT_B1_CLK_EN & PORT_B1_WR_EN; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_A2_i = PORT_A2_CLK_EN; +assign WEN_A2_i = PORT_A2_CLK_EN & PORT_A2_WR_EN; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B2_i = PORT_B2_CLK_EN; +assign WEN_B2_i = PORT_B2_CLK_EN & PORT_B2_WR_EN; +assign BE_B2_i = PORT_B2_WR_BE; + +assign ADDR_A1_i = PORT_A1_ADDR; +assign ADDR_B1_i = PORT_B1_ADDR; +assign ADDR_A2_i = PORT_A2_ADDR; +assign ADDR_B2_i = PORT_B2_ADDR; + +case (PORT_A1_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +default: assign WDATA_A1_i = PORT_A1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +default: assign WDATA_B1_i = PORT_B1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A1_WIDTH) +9: assign PORT_A1_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A1_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +default: assign PORT_A1_RD_DATA = RDATA_A1_o; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign PORT_B1_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B1_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +default: assign PORT_B1_RD_DATA = RDATA_B1_o; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign { WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +18: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +default: assign WDATA_A2_i = PORT_A2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign { WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +18: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +default: assign WDATA_B2_i = PORT_B2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign PORT_A2_RD_DATA = { RDATA_A2_o[16], RDATA_A2_o[7:0] }; +18: assign PORT_A2_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0] }; +default: assign PORT_A2_RD_DATA = RDATA_A2_o; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign PORT_B2_RD_DATA = { RDATA_B2_o[16], RDATA_B2_o[7:0] }; +18: assign PORT_B2_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0] }; +default: assign PORT_B2_RD_DATA = RDATA_B2_o; // 1,2,4,8,16 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + +(* is_inferred = 1 *) +(* is_split = 1 *) +(* port_a1_width = PORT_A1_WIDTH *) +(* port_a2_width = PORT_A2_WIDTH *) +(* port_b1_width = PORT_B1_WIDTH *) +(* port_b2_width = PORT_B2_WIDTH *) +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(WDATA_A1_i), + .WDATA_A2_i(WDATA_A2_i), + .RDATA_A1_o(RDATA_A1_o), + .RDATA_A2_o(RDATA_A2_o), + .ADDR_A1_i(ADDR_A1_i), + .ADDR_A2_i(ADDR_A2_i), + .CLK_A1_i(PORT_A1_CLK), + .CLK_A2_i(PORT_A2_CLK), + .REN_A1_i(REN_A1_i), + .REN_A2_i(REN_A2_i), + .WEN_A1_i(WEN_A1_i), + .WEN_A2_i(WEN_A2_i), + .BE_A1_i(BE_A1_i), + .BE_A2_i(BE_A2_i), + + .WDATA_B1_i(WDATA_B1_i), + .WDATA_B2_i(WDATA_B2_i), + .RDATA_B1_o(RDATA_B1_o), + .RDATA_B2_o(RDATA_B2_o), + .ADDR_B1_i(ADDR_B1_i), + .ADDR_B2_i(ADDR_B2_i), + .CLK_B1_i(PORT_B1_CLK), + .CLK_B2_i(PORT_B2_CLK), + .REN_B1_i(REN_B1_i), + .REN_B2_i(REN_B2_i), + .WEN_B1_i(WEN_B1_i), + .WEN_B2_i(WEN_B2_i), + .BE_B1_i(BE_B1_i), + .BE_B2_i(BE_B2_i), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule \ No newline at end of file diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v b/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v new file mode 100644 index 00000000000..86698ffefd3 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v @@ -0,0 +1,64 @@ +`default_nettype none +module sram1024x18 ( + clk_a, + cen_a, + wen_a, + addr_a, + wmsk_a, + wdata_a, + rdata_a, + clk_b, + cen_b, + wen_b, + addr_b, + wmsk_b, + wdata_b, + rdata_b +); + parameter [1024*18-1:0] init = 18431'bx; + (* clkbuf_sink *) + input wire clk_a; + input wire cen_a; + input wire wen_a; + input wire [9:0] addr_a; + input wire [17:0] wmsk_a; + input wire [17:0] wdata_a; + output reg [17:0] rdata_a; + (* clkbuf_sink *) + input wire clk_b; + input wire cen_b; + input wire wen_b; + input wire [9:0] addr_b; + input wire [17:0] wmsk_b; + input wire [17:0] wdata_b; + output reg [17:0] rdata_b; + reg [17:0] ram [1023:0]; + integer i; + initial begin + for (i = 0; i < 1024; i = i + 1) begin + ram[i] = init[18*i +: 18]; + end + end + + always @(posedge clk_a) begin + if (!cen_a) begin + if (!wen_a) + for (i = 0; i < 18; i++) begin + if (!wmsk_a[i]) ram[addr_a][i] <= wdata_a[i]; + end + rdata_a <= ram[addr_a]; + end + end + + always @(posedge clk_b) begin + if (!cen_b) begin + if (!wen_b) + for (i = 0; i < 18; i++) begin + if (!wmsk_b[i]) ram[addr_b][i] <= wdata_b[i]; + end + rdata_b <= ram[addr_b]; + end + end + +endmodule + diff --git a/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v b/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v new file mode 100644 index 00000000000..441f6bc4a81 --- /dev/null +++ b/yosys/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v @@ -0,0 +1,620 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module fifo_ctl ( + raddr, + waddr, + fflags, + ren_o, + sync, + rmode, + wmode, + rclk, + rst_R_n, + wclk, + rst_W_n, + ren, + wen, + upaf, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire [ADDR_WIDTH - 1:0] raddr; + output wire [ADDR_WIDTH - 1:0] waddr; + output wire [7:0] fflags; + output wire ren_o; + input wire sync; + input wire [1:0] rmode; + input wire [1:0] wmode; + (* clkbuf_sink *) + input wire rclk; + input wire rst_R_n; + (* clkbuf_sink *) + input wire wclk; + input wire rst_W_n; + input wire ren; + input wire wen; + input wire [ADDR_WIDTH - 1:0] upaf; + input wire [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg [ADDR_WIDTH:0] pushtopop1; + reg [ADDR_WIDTH:0] pushtopop2; + reg [ADDR_WIDTH:0] poptopush1; + reg [ADDR_WIDTH:0] poptopush2; + wire [ADDR_WIDTH:0] pushtopop0; + wire [ADDR_WIDTH:0] poptopush0; + wire [ADDR_WIDTH:0] smux_poptopush; + wire [ADDR_WIDTH:0] smux_pushtopop; + assign smux_poptopush = (sync ? poptopush0 : poptopush2); + assign smux_pushtopop = (sync ? pushtopop0 : pushtopop2); + always @(posedge rclk or negedge rst_R_n) + if (~rst_R_n) begin + pushtopop1 <= 'h0; + pushtopop2 <= 'h0; + end + else begin + pushtopop1 = pushtopop0; + pushtopop2 = pushtopop1; + end + always @(posedge wclk or negedge rst_W_n) + if (~rst_W_n) begin + poptopush1 <= 'h0; + poptopush2 <= 'h0; + end + else begin + poptopush1 <= poptopush0; + poptopush2 <= poptopush1; + end + fifo_push #( + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_push( + .wclk(wclk), + .wen(wen), + .rst_n(rst_W_n), + .rmode(rmode), + .wmode(wmode), + .gcout(pushtopop0), + .gcin(smux_poptopush), + .ff_waddr(waddr), + .pushflags(fflags[7:4]), + .upaf(upaf) + ); + fifo_pop #( + .ADDR_WIDTH(ADDR_WIDTH), + .FIFO_WIDTH(FIFO_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_pop( + .rclk(rclk), + .ren_in(ren), + .rst_n(rst_R_n), + .rmode(rmode), + .wmode(wmode), + .ren_o(ren_o), + .gcout(poptopush0), + .gcin(smux_pushtopop), + .out_raddr(raddr), + .popflags(fflags[3:0]), + .upae(upae) + ); +endmodule +module fifo_push ( + pushflags, + gcout, + ff_waddr, + rst_n, + wclk, + wen, + rmode, + wmode, + gcin, + upaf +); + parameter ADDR_WIDTH = 11; + parameter DEPTH = 6; + output wire [3:0] pushflags; + output wire [ADDR_WIDTH:0] gcout; + output wire [ADDR_WIDTH - 1:0] ff_waddr; + input rst_n; + (* clkbuf_sink *) + input wclk; + input wen; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upaf; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg full_next; + reg full; + reg paf_next; + reg paf; + reg fmo; + reg fmo_next; + reg overflow; + reg p1; + reg p2; + reg f1; + reg f2; + reg q1; + reg q2; + reg [1:0] gmode; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] raddr_next; + reg [ADDR_WIDTH - 1:0] paf_thresh; + wire overflow_next; + wire [ADDR_WIDTH:0] waddr_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_WIDTH:0] next_count; + wire [ADDR_WIDTH:0] count; + wire [ADDR_WIDTH:0] fbytes; + genvar i; + assign next_count = fbytes - (waddr_next >= raddr_next ? waddr_next - raddr_next : (~raddr_next + waddr_next) + 1); + assign count = fbytes - (waddr >= raddr ? waddr - raddr : (~raddr + waddr) + 1); + assign fbytes = 1 << (DEPTH + 5); + always @(*) begin + paf_thresh = wmode[1] ? upaf : (wmode[0] ? upaf << 1 : upaf << 2); + end + always @(*) + case (wmode) + 2'h0, 2'h1, 2'h2: begin + full_next = (wen ? f1 : f2); + fmo_next = (wen ? p1 : p2); + paf_next = (wen ? q1 : q2); + end + default: begin + full_next = 1'b0; + fmo_next = 1'b0; + paf_next = 1'b0; + end + endcase + always @(*) begin : PUSH_FULL_FLAGS + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + q1 = next_count < {1'b0, paf_thresh}; + q2 = count < {1'b0, paf_thresh}; + case (wmode) + 2'h0: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:2]} == raddr_next[11:2]; + f2 = {~waddr[11], waddr[10:2]} == raddr_next[11:2]; + p1 = ((waddr_next[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + p2 = ((waddr[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:2]} == raddr_next[10:2]; + f2 = {~waddr[10], waddr[9:2]} == raddr_next[10:2]; + p1 = ((waddr_next[9:2] + 1) & 8'hff) == raddr_next[9:2]; + p2 = ((waddr[9:2] + 1) & 8'hff) == raddr_next[9:2]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:2]} == raddr_next[9:2]; + f2 = {~waddr[9], waddr[8:2]} == raddr_next[9:2]; + p1 = ((waddr_next[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + p2 = ((waddr[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:2]} == raddr_next[8:2]; + f2 = {~waddr[8], waddr[7:2]} == raddr_next[8:2]; + p1 = ((waddr_next[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + p2 = ((waddr[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:2]} == raddr_next[7:2]; + f2 = {~waddr[7], waddr[6:2]} == raddr_next[7:2]; + p1 = ((waddr_next[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + p2 = ((waddr[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:2]} == raddr_next[6:2]; + f2 = {~waddr[6], waddr[5:2]} == raddr_next[6:2]; + p1 = ((waddr_next[5:2] + 1) & 4'hf) == raddr_next[5:2]; + p2 = ((waddr[5:2] + 1) & 4'hf) == raddr_next[5:2]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:2]} == raddr_next[5:2]; + f2 = {~waddr[5], waddr[4:2]} == raddr_next[5:2]; + p1 = ((waddr_next[4:2] + 1) & 3'h7) == raddr_next[4:2]; + p2 = ((waddr[4:2] + 1) & 3'h7) == raddr_next[4:2]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + p1 = ((waddr_next[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + p2 = ((waddr[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + end + endcase + 2'h1: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:1]} == raddr_next[11:1]; + f2 = {~waddr[11], waddr[10:1]} == raddr_next[11:1]; + p1 = ((waddr_next[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + p2 = ((waddr[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:1]} == raddr_next[10:1]; + f2 = {~waddr[10], waddr[9:1]} == raddr_next[10:1]; + p1 = ((waddr_next[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + p2 = ((waddr[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:1]} == raddr_next[9:1]; + f2 = {~waddr[9], waddr[8:1]} == raddr_next[9:1]; + p1 = ((waddr_next[8:1] + 1) & 8'hff) == raddr_next[8:1]; + p2 = ((waddr[8:1] + 1) & 8'hff) == raddr_next[8:1]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:1]} == raddr_next[8:1]; + f2 = {~waddr[8], waddr[7:1]} == raddr_next[8:1]; + p1 = ((waddr_next[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + p2 = ((waddr[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:1]} == raddr_next[7:1]; + f2 = {~waddr[7], waddr[6:1]} == raddr_next[7:1]; + p1 = ((waddr_next[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + p2 = ((waddr[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:1]} == raddr_next[6:1]; + f2 = {~waddr[6], waddr[5:1]} == raddr_next[6:1]; + p1 = ((waddr_next[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + p2 = ((waddr[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:1]} == raddr_next[5:1]; + f2 = {~waddr[5], waddr[4:1]} == raddr_next[5:1]; + p1 = ((waddr_next[4:1] + 1) & 4'hf) == raddr_next[4:1]; + p2 = ((waddr[4:1] + 1) & 4'hf) == raddr_next[4:1]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + p1 = ((waddr_next[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + p2 = ((waddr[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + end + endcase + 2'h2: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:0]} == raddr_next[11:0]; + f2 = {~waddr[11], waddr[10:0]} == raddr_next[11:0]; + p1 = ((waddr_next[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + p2 = ((waddr[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:0]} == raddr_next[10:0]; + f2 = {~waddr[10], waddr[9:0]} == raddr_next[10:0]; + p1 = ((waddr_next[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + p2 = ((waddr[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:0]} == raddr_next[9:0]; + f2 = {~waddr[9], waddr[8:0]} == raddr_next[9:0]; + p1 = ((waddr_next[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + p2 = ((waddr[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:0]} == raddr_next[8:0]; + f2 = {~waddr[8], waddr[7:0]} == raddr_next[8:0]; + p1 = ((waddr_next[7:0] + 1) & 8'hff) == raddr_next[7:0]; + p2 = ((waddr[7:0] + 1) & 8'hff) == raddr_next[7:0]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:0]} == raddr_next[7:0]; + f2 = {~waddr[7], waddr[6:0]} == raddr_next[7:0]; + p1 = ((waddr_next[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + p2 = ((waddr[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:0]} == raddr_next[6:0]; + f2 = {~waddr[6], waddr[5:0]} == raddr_next[6:0]; + p1 = ((waddr_next[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + p2 = ((waddr[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:0]} == raddr_next[5:0]; + f2 = {~waddr[5], waddr[4:0]} == raddr_next[5:0]; + p1 = ((waddr_next[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + p2 = ((waddr[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + p1 = ((waddr_next[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + p2 = ((waddr[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + end + endcase + 2'h3: begin + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + end + endcase + end + always @(*) + case (wmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (rmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (rmode == 2'h2 ? 2'h2 : rmode); + 2'h3: gmode = 2'h3; + endcase + assign gc8out_next = (waddr_next >> 1) ^ waddr_next; + assign gc16out_next = (waddr_next >> 2) ^ (waddr_next >> 1); + assign gc32out_next = (waddr_next >> 3) ^ (waddr_next >> 2); + always @(*) + if (wen) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + else + gcout_next = {ADDR_PLUS_ONE {1'b0}}; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + full <= 1'b0; + fmo <= 1'b0; + paf <= 1'b0; + raddr <= {ADDR_PLUS_ONE {1'b0}}; + end + else begin + full <= full_next; + fmo <= fmo_next; + paf <= paf_next; + case (gmode) + 0: raddr <= raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 1: raddr <= raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2: raddr <= raddr_next & {ADDR_WIDTH + 1 {1'b1}}; + 3: raddr <= 12'h000; + endcase + end + assign overflow_next = full & wen; + always @(posedge wclk or negedge rst_n) + if (~rst_n) + overflow <= 1'b0; + else if (wen == 1'b1) + overflow <= overflow_next; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + waddr <= {ADDR_WIDTH + 1 {1'b0}}; + gcout_reg <= {ADDR_WIDTH + 1 {1'b0}}; + end + else if (wen == 1'b1) begin + waddr <= waddr_next; + gcout_reg <= gcout_next; + end + assign gcout = gcout_reg; + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: raddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: raddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: raddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_WIDTH + 1 {1'b1}}; + default: raddr_next = {ADDR_WIDTH + 1 {1'b0}}; + endcase + assign ff_waddr = waddr[ADDR_WIDTH - 1:0]; + assign pushflags = {full, fmo, paf, overflow}; + assign waddr_next = waddr + (wmode == 2'h0 ? 'h4 : (wmode == 2'h1 ? 'h2 : 'h1)); +endmodule +module fifo_pop ( + ren_o, + popflags, + out_raddr, + gcout, + rst_n, + rclk, + ren_in, + rmode, + wmode, + gcin, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire ren_o; + output wire [3:0] popflags; + output reg [ADDR_WIDTH - 1:0] out_raddr; + output wire [ADDR_WIDTH:0] gcout; + input rst_n; + (* clkbuf_sink *) + input rclk; + input ren_in; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg empty; + reg epo; + reg pae; + reg underflow; + reg e1; + reg e2; + reg o1; + reg o2; + reg q1; + reg q2; + reg [1:0] bwl_sel; + reg [1:0] gmode; + reg [ADDR_WIDTH - 1:0] ff_raddr; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] waddr_next; + reg [ADDR_WIDTH - 1:0] pae_thresh; + wire ren_out; + wire empty_next; + wire pae_next; + wire epo_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH:0] raddr_next; + wire [ADDR_WIDTH - 1:0] ff_raddr_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_PLUS_ONE:0] next_count; + wire [ADDR_PLUS_ONE:0] count; + wire [ADDR_PLUS_ONE:0] fbytes; + genvar i; + assign next_count = waddr - raddr_next; + assign count = waddr - raddr; + assign fbytes = 1 << (DEPTH + 5); + always @(*) pae_thresh = rmode[1] ? upae : (rmode[0] ? upae << 1 : upae << 2); + assign ren_out = (empty ? 1'b1 : ren_in); + always @(*) + case (rmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (wmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (wmode == 2'h2 ? 2'h2 : wmode); + 2'h3: gmode = 2'h3; + endcase + always @(*) begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + q1 = next_count < {1'b0, pae_thresh}; + q2 = count < {1'b0, pae_thresh}; + case (rmode) + 2'h0: begin + e1 = raddr_next[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + e2 = raddr[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + o1 = (raddr_next[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + o2 = (raddr[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + end + 2'h1: begin + e1 = raddr_next[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + e2 = raddr[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + o1 = (raddr_next[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + o2 = (raddr[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + end + 2'h2: begin + e1 = raddr_next[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + e2 = raddr[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + o1 = (raddr_next[ADDR_WIDTH:0] + 1) == waddr_next[ADDR_WIDTH:0]; + o2 = (raddr[ADDR_WIDTH:0] + 1) == waddr_next[11:0]; + end + 2'h3: begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + end + endcase + end + assign empty_next = (ren_in & !empty ? e1 : e2); + assign epo_next = (ren_in & !empty ? o1 : o2); + assign pae_next = (ren_in & !empty ? q1 : q2); + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + empty <= 1'b1; + pae <= 1'b1; + epo <= 1'b0; + end + else begin + empty <= empty_next; + pae <= pae_next; + epo <= epo_next; + end + assign gc8out_next = (raddr_next >> 1) ^ raddr_next; + assign gc16out_next = (raddr_next >> 2) ^ (raddr_next >> 1); + assign gc32out_next = (raddr_next >> 3) ^ (raddr_next >> 2); + always @(*) + if (ren_in) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = 'h0; + endcase + else + gcout_next = 'h0; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + waddr <= 12'h000; + else + waddr <= waddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + underflow <= 1'b0; + bwl_sel <= 2'h0; + gcout_reg <= 12'h000; + end + else if (ren_in) begin + underflow <= empty; + if (!empty) begin + bwl_sel <= raddr_next[1:0]; + gcout_reg <= gcout_next; + end + end + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: waddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: waddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: waddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_PLUS_ONE {1'b1}}; + default: waddr_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + assign ff_raddr_next = ff_raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + assign raddr_next = raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + always @(posedge rclk or negedge rst_n) + if (~rst_n) + ff_raddr <= 1'sb0; + else if (empty & ~empty_next) + ff_raddr <= raddr_next[ADDR_WIDTH - 1:0]; + else if ((ren_in & !empty) & ~empty_next) + ff_raddr <= ff_raddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + raddr <= 12'h000; + else if (ren_in & !empty) + raddr <= raddr_next; + always @(*) + case (FIFO_WIDTH) + 3'h2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]}; + 3'h4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel}; + default: out_raddr = ff_raddr[ADDR_WIDTH - 1:0]; + endcase + assign ren_o = ren_out; + assign gcout = gcout_reg; + assign popflags = {empty, epo, pae, underflow}; +endmodule +`default_nettype none diff --git a/yosys/techlibs/quicklogic/synth_quicklogic.cc b/yosys/techlibs/quicklogic/synth_quicklogic.cc index 94bd44db008..0e7aaa75276 100644 --- a/yosys/techlibs/quicklogic/synth_quicklogic.cc +++ b/yosys/techlibs/quicklogic/synth_quicklogic.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2021 QuickLogic Corp. + * Copyright 2020-2022 F4PGA Authors * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -30,6 +31,7 @@ struct SynthQuickLogicPass : public ScriptPass { void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" synth_quicklogic [options]\n"); log("This command runs synthesis for QuickLogic FPGAs\n"); @@ -42,6 +44,21 @@ struct SynthQuickLogicPass : public ScriptPass { log(" generate the synthesis netlist for the specified family.\n"); log(" supported values:\n"); log(" - pp3: PolarPro 3 \n"); + log(" - qlf_k6n10f: K6N10f\n"); + log("\n"); + log(" -nodsp\n"); + log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); + log(" (qlf_k6n10f only).\n"); + log("\n"); + log(" -nocarry\n"); + log(" do not use adder_carry cells in output netlist.\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist.\n"); + log("\n"); + log(" -bramtypes\n"); + log(" Emit specialized BRAM cells for particular address and data width\n"); + log(" configurations.\n"); log("\n"); log(" -blif \n"); log(" write the design to the specified BLIF file. writing of an output file\n"); @@ -60,27 +77,51 @@ struct SynthQuickLogicPass : public ScriptPass { log("\n"); } - string top_opt, blif_file, family, currmodule, verilog_file; - bool abc9; + string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; + bool abc9, inferAdder, nobram, bramTypes, dsp; void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; + edif_file = ""; verilog_file = ""; currmodule = ""; family = "pp3"; abc9 = true; + inferAdder = true; + nobram = false; + bramTypes = false; + lib_path = "+/quicklogic/"; + dsp = true; + } + + void set_scratchpad_defaults(RTLIL::Design *design) { + lib_path = design->scratchpad_get_string("ql.lib_path", lib_path); + if (lib_path.back() != '/') + lib_path += "/"; + inferAdder = !design->scratchpad_get_bool("ql.nocarry", false); + nobram = design->scratchpad_get_bool("ql.nobram", false); + bramTypes = design->scratchpad_get_bool("ql.bramtypes", false); } void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); + set_scratchpad_defaults(design); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } if (args[argidx] == "-top" && argidx+1 < args.size()) { top_opt = "-top " + args[++argidx]; continue; @@ -101,6 +142,22 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } + if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") { + inferAdder = false; + continue; + } + if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") { + nobram = true; + continue; + } + if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") { + bramTypes = true; + continue; + } + if (args[argidx] == "-nodsp" || args[argidx] == "-no_dsp") { + dsp = false; + continue; + } break; } extra_args(args, argidx, design); @@ -108,7 +165,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family != "pp3") + if (family != "pp3" && family != "qlf_k6n10f") log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { @@ -126,16 +183,29 @@ struct SynthQuickLogicPass : public ScriptPass { void script() override { + if (help_mode) { + family = ""; + } + if (check_label("begin")) { - run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str())); - run("read_verilog -lib -specify +/quicklogic/lut_sim.v"); + std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str()); + if (family == "qlf_k6n10f") { + read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); + if (bramTypes) + read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + if (dsp) + read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str()); + } + run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - if (check_label("coarse")) { + if (check_label("prepare")) { run("proc"); run("flatten"); - run("tribuf -logic"); + if (help_mode || family == "pp3") { + run("tribuf -logic", " (for pp3)"); + } run("deminout"); run("opt_expr"); run("opt_clean"); @@ -147,6 +217,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("peepopt"); run("opt_clean"); run("share"); + } + + if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") + && ((dsp && family == "qlf_k6n10f") || help_mode)) { + run("wreduce t:$mul"); + run("ql_dsp_macc"); + + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); + run("chtype -set $mul t:$__soft_mul"); + + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); + run("ql_dsp_simd"); + run("techmap -map " + lib_path + family + "/dsp_final_map.v"); + run("ql_dsp_io_regs"); + } + + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); @@ -157,6 +245,17 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") + && (family == "qlf_k6n10f" || help_mode)) { + run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); + run("ql_bram_merge"); + run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); + run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); + + if (bramTypes || help_mode) + run("ql_bram_types", "(if -bramtypes)"); + } + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block " @@ -166,36 +265,67 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_gates")) { - run("techmap"); + if (inferAdder && family == "qlf_k6n10f") { + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + } else { + run("techmap"); + } run("opt -fast"); - run("muxcover -mux8 -mux4"); + if (help_mode || family == "pp3") { + run("muxcover -mux8 -mux4", "(for pp3)"); + } } if (check_label("map_ffs")) { run("opt_expr"); - run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - - run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str())); - - run("opt_expr -mux_undef"); + if (help_mode) { + run("shregmap -minlen -maxlen ", "(for qlf_k6n10f)"); + run("dfflegalize -cell "); + run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)"); + run("techmap -map " + lib_path + family + "/ffs_map.v", "(for ql_k6n10f)"); + } + if (family == "pp3") { + run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); + run("techmap -map " + lib_path + family + "/cells_map.v -map " + lib_path + family + "/ffs_map.v"); + run("opt_expr -mux_undef"); + } else if (family == "qlf_k6n10f") { + run("shregmap -minlen 8 -maxlen 20"); + // FIXME: Apparently dfflegalize leaves around $_DLATCH_[NP]_ even if + // not in the allowed set. As a workaround we put them in the allowed + // set explicitly and map them later to $_DLATCHSR_[NP]NN_. + run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0"); + run("techmap -map " + lib_path + family + "/ffs_map.v"); + } + run("opt"); } - if (check_label("map_luts")) { - run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str())); + if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/latches_map.v"); if (abc9) { - run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v"); - run("techmap -map +/quicklogic/abc9_map.v"); + run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); + run("techmap -map " + lib_path + family + "/abc9_map.v"); run("abc9 -maxlut 4 -dff"); - run("techmap -map +/quicklogic/abc9_unmap.v"); + run("techmap -map " + lib_path + family + "/abc9_unmap.v"); } else { run("abc -luts 1,2,2,4 -dress"); } run("clean"); } - if (check_label("map_cells")) { - run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str())); + if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) { + if (abc9) { + run("abc9 -maxlut 6"); + } else { + run("abc -lut 6 -dress"); + } run("clean"); + run("opt_lut"); + } + + if (check_label("map_cells", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/lut_map.v"); + run("clean"); + run("opt_lut"); } if (check_label("check")) { @@ -205,26 +335,30 @@ struct SynthQuickLogicPass : public ScriptPass { run("check -noinit"); } - if (check_label("iomap")) { + if (check_label("iomap", "(for pp3)") && (family == "pp3" || help_mode)) { run("clkbufmap -inpad ckpad Q:P"); run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top"); } if (check_label("finalize")) { - run("setundef -zero -params -undriven"); - run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top"); + if (help_mode || family == "pp3") { + run("setundef -zero -params -undriven", "(for pp3)"); + } + if (family == "pp3" || !edif_file.empty()) { + run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top", "(for pp3 or if -edif)"); + } run("opt_clean -purge"); run("check"); run("blackbox =A:whitebox"); } - if (check_label("blif")) { + if (check_label("blif", "(if -blif)")) { if (!blif_file.empty() || help_mode) { run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str())); } } - if (check_label("verilog")) { + if (check_label("verilog", "(if -verilog)")) { if (!verilog_file.empty() || help_mode) { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } diff --git a/yosys/techlibs/xilinx/tests/bram1.sh b/yosys/techlibs/xilinx/tests/bram1.sh index 7451a1b3e25..7e99368048d 100644 --- a/yosys/techlibs/xilinx/tests/bram1.sh +++ b/yosys/techlibs/xilinx/tests/bram1.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/yosys/techlibs/xilinx/tests/bram2.sh b/yosys/techlibs/xilinx/tests/bram2.sh index 5d9c84dace1..5c18d30e246 100644 --- a/yosys/techlibs/xilinx/tests/bram2.sh +++ b/yosys/techlibs/xilinx/tests/bram2.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims diff --git a/yosys/techlibs/xilinx/tests/test_dsp48_model.sh b/yosys/techlibs/xilinx/tests/test_dsp48_model.sh index 9a73f9b0c3e..bd72572d5f9 100644 --- a/yosys/techlibs/xilinx/tests/test_dsp48_model.sh +++ b/yosys/techlibs/xilinx/tests/test_dsp48_model.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex if [ -z $ISE_DIR ]; then ISE_DIR=/opt/Xilinx/ISE/14.7 diff --git a/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh b/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh index a14a78e7267..02ce2fef999 100644 --- a/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh +++ b/yosys/techlibs/xilinx/tests/test_dsp48a1_model.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex if [ -z $ISE_DIR ]; then ISE_DIR=/opt/Xilinx/ISE/14.7 diff --git a/yosys/techlibs/xilinx/tests/test_dsp_model.sh b/yosys/techlibs/xilinx/tests/test_dsp_model.sh index d005cd40c73..b2a2bb44582 100644 --- a/yosys/techlibs/xilinx/tests/test_dsp_model.sh +++ b/yosys/techlibs/xilinx/tests/test_dsp_model.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -ex if [ -z $VIVADO_DIR ]; then VIVADO_DIR=/opt/Xilinx/Vivado/2019.1 diff --git a/yosys/tests/aiger/run-test.sh b/yosys/tests/aiger/run-test.sh index bcf2b964a27..ca7339ff0b5 100755 --- a/yosys/tests/aiger/run-test.sh +++ b/yosys/tests/aiger/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/yosys/tests/arch/common/blockram.v b/yosys/tests/arch/common/blockram.v index c06ac96d5bc..4a9d45a6b4a 100644 --- a/yosys/tests/arch/common/blockram.v +++ b/yosys/tests/arch/common/blockram.v @@ -45,6 +45,113 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // wd=16, wa=9 +( + input wire clk_w, clk_r, write_enable, + input wire [WORD-1:0] data_in, + input wire [ADDRESS_WIDTH_W-1:0] address_in_w, + input wire [ADDRESS_WIDTH-1:0] address_in_r, + output wire [DATA_WIDTH-1:0] data_out +); + + localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-SHIFT_VAL; + localparam BYTE = DATA_WIDTH; + localparam WORD = DATA_WIDTH<1 +select -assert-count 1 t:dffsre + +select -assert-none t:$lut t:dffsre %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:dffsre + +select -assert-none t:dffsre %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=1 %i +select -assert-none r:WIDTH>1 +select -assert-count 1 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffnsre + +select -assert-none t:sdffnsre %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys new file mode 100644 index 00000000000..ebb6ce243eb --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/counter.ys @@ -0,0 +1,12 @@ +read_verilog ../../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:$lut +select -assert-count 8 t:adder_carry +select -assert-count 8 t:dffsre + +select -assert-none t:$lut t:adder_carry t:dffsre %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys new file mode 100644 index 00000000000..79a16c9412b --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -0,0 +1,21 @@ +read_verilog ../../common/dffs.v +rename dff my_dff # Work around conflicting module names between test and vendor cells +rename dffe my_dffe +design -save read + +hierarchy -top my_dff +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd my_dff # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D + +design -load read +hierarchy -top my_dffe +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd my_dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys new file mode 100644 index 00000000000..1e652855bbd --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/dsp.ys @@ -0,0 +1,121 @@ +read_verilog < 0) + assert(y == y_expected); + i <= i + 1; + end +end +endmodule +EOF +read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v +hierarchy -top testbench +proc +async2sync +sim -assert -q -clock clk -n 20 diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys new file mode 100644 index 00000000000..e7a9d962d6e --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/fsm.ys @@ -0,0 +1,17 @@ +read_verilog ../../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f +async2sync +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut +select -assert-count 6 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys new file mode 100644 index 00000000000..59574a1fb77 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/latches.ys @@ -0,0 +1,29 @@ +read_verilog ../../common/latches.v +design -save read + +hierarchy -top latchp +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchp +select -assert-count 1 t:latchsre +select -assert-none t:latchsre %% t:* %D + +design -load read +hierarchy -top latchn +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchn +select -assert-count 1 t:latchnsre +select -assert-none t:latchnsre %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchsr +select -assert-count 2 t:$lut +select -assert-count 1 t:latchnsre +select -assert-none t:$lut t:latchnsre %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys new file mode 100644 index 00000000000..a24d5a479f6 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/logic.ys @@ -0,0 +1,10 @@ +read_verilog ../../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut + +select -assert-none t:$lut %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py new file mode 100644 index 00000000000..b608e66eba9 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py @@ -0,0 +1,463 @@ +from __future__ import annotations + +from dataclasses import dataclass + + +blockram_template = """# ====================================== +log ** GENERATING TEST {top} WITH PARAMS{param_str} +design -reset; read_verilog -defer ../../common/blockram.v +chparam{param_str} {top} +hierarchy -top {top} +synth_quicklogic -family qlf_k6n10f -top {top} +""" +blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [ + # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + # larger sizes need an extra ram + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + # 4096x20bit *can* fit in 3, albeit somewhat awkwardly + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K", + "-assert-max 4 t:TDP36K"]), + + # smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36) + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]), + ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]), + + # 2x asymmetric (1024x36bit write / 2048x18bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + + # 4x asymmetric (1024x36bit write / 4096x9bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + + # can also use an extra TDP36K for higher width + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), + + # # SHIFT=0 should be identical to sync_ram_sdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + + # asymmetric memories assign different port widths on a and b ports + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=36 %i"]), + + # two disjoint 18K memories can share a single TDP36K + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + # but only if data width is <= 18 + ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + + # also for tdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 8)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 4)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 2)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 1)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + # still only if data width is <= 18 + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36)], "double_sync_ram_tdp", ["-assert-count 2 t:TDP36K"]), + + # sharing a TDP36K sets is_split=1 + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + # an unshared TDP36K sets is_split=0 + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + + # sharing a TDP36K sets correct port widths + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i " + + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 12), ("DATA_WIDTH_A", 4), ("DATA_WIDTH_B", 12), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=4 %i a:port_a2_width=18 %i " + + "t:TDP36K a:port_a2_width=4 %i a:port_a1_width=18 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 13), ("DATA_WIDTH_A", 2), ("DATA_WIDTH_B", 1), ("ADDRESS_WIDTH_B", 14)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=2 %i a:port_a2_width=1 %i " + + "t:TDP36K a:port_a2_width=2 %i a:port_a1_width=1 %i %u", + "-assert-count 1 t:TDP36K"]), +] + +sim_template = """\ +design -stash synthesized +design -copy-from synthesized -as {top}_synth {top} +design -delete synthesized +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +read_verilog < 1: + top_list.pop(0) + + # iterate over string substitutions + for top in top_list: + # limit number of tests per file to allow parallel make + if not f: + fn = f"t_mem{i}.ys" + f = open(fn, mode="w") + j = 0 + + # output yosys script test file + print( + blockram_template.format(param_str=param_str, top=top), + file=f + ) + for assertion in sim_test.assertions: + print("log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str}".format(param_str=param_str, top=top), file=f) + print("select {}".format(assertion), file=f) + print("", file=f) + + # prepare simulation tests + test_steps = sim_test.test_steps + if test_steps: + if top == "sync_ram_sdp": + uut_submodule = sync_ram_sdp_submodule + elif top == "sync_ram_tdp": + uut_submodule = sync_ram_tdp_submodule + elif top == "sync_ram_sdp_wwr": + uut_submodule = sync_ram_sdp_wwr_submodule + elif top == "sync_ram_sdp_wrr": + uut_submodule = sync_ram_sdp_wrr_submodule + elif top == "double_sync_ram_sdp": + uut_submodule = double_sync_ram_sdp_submodule + else: + raise NotImplementedError(f"missing submodule header for {top}") + mem_test_vector = "" + for step, test in enumerate(test_steps): + for key, val in test.items(): + key = test_val_map[key] + mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};" + print( + sim_template.format( + top=top, + mem_test_vector=mem_test_vector, + uut_submodule=uut_submodule, + param_str=param_str, + vectorlen=len(test_steps) + 2 + ), file=f + ) + # simulation counts for 2 tests + j += 1 + + # increment test counter + j += 1 + if j >= max_j: + f = f.close() + i += 1 + +if f: + f.close() diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v new file mode 100644 index 00000000000..a0d15bd6222 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -0,0 +1,84 @@ +module TB(input clk); + +parameter ADDRESS_WIDTH = 10; +parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH; +parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH; +parameter DATA_WIDTH = 36; +parameter DATA_WIDTH_A = DATA_WIDTH; +parameter DATA_WIDTH_B = DATA_WIDTH; +parameter VECTORLEN = 16; +parameter SHIFT_VAL = 0; + +// intentionally keep expected values at full width precision to allow testing +// of truncation +localparam MAX_WIDTH = 36; + +reg rce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; + +reg wce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0]; + +reg rce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; + +reg wce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0]; + +reg [$clog2(VECTORLEN)-1:0] i = 0; + +integer j; +initial begin + for (j = 0; j < VECTORLEN; j = j + 1) begin + rce_a_testvector[j] = 1'b0; + ra_a_testvector[j] = 10'h0; + wce_a_testvector[j] = 1'b0; + wa_a_testvector[j] = 10'h0; + rce_b_testvector[j] = 1'b0; + ra_b_testvector[j] = 10'h0; + wce_b_testvector[j] = 1'b0; + wa_b_testvector[j] = 10'h0; + + end + + `MEM_TEST_VECTOR + +end + + +wire rce_a = rce_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i]; +wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i]; +wire [DATA_WIDTH_A-1:0] rq_a; + +wire wce_a = wce_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i]; +wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i]; + +wire rce_b = rce_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i]; +wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i]; +wire [DATA_WIDTH_B-1:0] rq_b; + +wire wce_b = wce_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i]; +wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i]; + +`UUT_SUBMODULE + +always @(posedge clk) begin + if (i < VECTORLEN-1) begin + if (i > 0) begin + if($past(rce_a)) + assert(rq_a == rq_a_e); + if($past(rce_b)) + assert(rq_b == rq_b_e); + end + i <= i + 1; + end +end +endmodule diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v new file mode 100644 index 00000000000..46a7dcac710 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.v @@ -0,0 +1,50 @@ +module top(clk); +parameter DEPTH_LOG2 = 10; +parameter WIDTH = 36; +parameter PRIME = 237481091; +localparam DEPTH = 2**DEPTH_LOG2; + +input wire clk; + +(* syn_ramstyle = "block_ram" *) +reg [WIDTH-1:0] mem [DEPTH-1:0]; + +integer i; +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + // Make up data by multiplying a large prime with the address, + // then cropping and retaining the lower bits + mem[i] = PRIME * i; + end +end + +reg [DEPTH_LOG2-1:0] counter = 0; +reg done = 1'b0; + +reg did_read = 1'b0; +reg [DEPTH_LOG2-1:0] read_addr; +reg [WIDTH-1:0] read_val; + +always @(posedge clk) begin + if (!done) begin + did_read <= 1'b1; + read_addr <= counter; + read_val <= mem[counter]; + end else begin + did_read <= 1'b0; + end + + if (!done) + counter = counter + 1; + if (counter == 0) + done = 1; +end + +wire [WIDTH-1:0] expect_val = PRIME * read_addr; +always @(posedge clk) begin + if (did_read) begin + $display("addr %x expected %x actual %x", read_addr, expect_val, read_val); + assert(read_val == expect_val); + end +end +endmodule diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys new file mode 100644 index 00000000000..8e9849c3b46 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/meminit.ys @@ -0,0 +1,15 @@ +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 3 -set WIDTH 36 +prep +opt_dff +prep -rdff +synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram +select -assert-none t:$mem_v2 t:$mem +select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K a:is_split=0 %i +select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 12 -clock clk diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys b/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys new file mode 100644 index 00000000000..633b5fc8656 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=3 %i %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=6 %i +select -assert-none t:$lut r:WIDTH=6 %i %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 2 t:$lut r:WIDTH=6 %i +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2 +select -assert-max 1 t:$lut r:WIDTH=3 %i # and here 1 +select -assert-max 1 t:$lut r:WIDTH=4 r:WIDTH=5 %u %i +select -assert-none t:$lut r:WIDTH>2 %i %% t:* %D diff --git a/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh new file mode 100755 index 00000000000..2fe33619418 --- /dev/null +++ b/yosys/tests/arch/quicklogic/qlf_k6n10f/run-test.sh @@ -0,0 +1,5 @@ +#!/usr/bin/env bash +set -eu +python3 mem_gen.py +source ../../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash diff --git a/yosys/tests/arch/run-test.sh b/yosys/tests/arch/run-test.sh index 5d923db560b..a14b795090d 100755 --- a/yosys/tests/arch/run-test.sh +++ b/yosys/tests/arch/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/yosys/tests/arch/xilinx/dsp_abc9.ys b/yosys/tests/arch/xilinx/dsp_abc9.ys index ae4839d7f1f..1d74cfa89b2 100644 --- a/yosys/tests/arch/xilinx/dsp_abc9.ys +++ b/yosys/tests/arch/xilinx/dsp_abc9.ys @@ -30,6 +30,7 @@ module top(output [42:0] P); assert property (P == 42*42); endmodule EOT +async2sync techmap -map +/xilinx/xc7_dsp_map.v verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1 synth_xilinx -abc9 diff --git a/yosys/tests/asicworld/run-test.sh b/yosys/tests/asicworld/run-test.sh index c22ab69281f..5131ed64688 100755 --- a/yosys/tests/asicworld/run-test.sh +++ b/yosys/tests/asicworld/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash OPTIND=1 seed="" # default to no seed specified diff --git a/yosys/tests/blif/run-test.sh b/yosys/tests/blif/run-test.sh index 44ce7e6741f..e9698386e3a 100755 --- a/yosys/tests/blif/run-test.sh +++ b/yosys/tests/blif/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e for x in *.ys; do echo "Running $x.." diff --git a/yosys/tests/bram/run-single.sh b/yosys/tests/bram/run-single.sh index 429a79e3c6a..358423f3225 100644 --- a/yosys/tests/bram/run-single.sh +++ b/yosys/tests/bram/run-single.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e ../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v diff --git a/yosys/tests/bram/run-test.sh b/yosys/tests/bram/run-test.sh index d6ba0de4347..37fc91d0e56 100755 --- a/yosys/tests/bram/run-test.sh +++ b/yosys/tests/bram/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # run this test many times: # MAKE="make -j8" time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' diff --git a/yosys/tests/cxxrtl/.gitignore b/yosys/tests/cxxrtl/.gitignore new file mode 100644 index 00000000000..91caee98625 --- /dev/null +++ b/yosys/tests/cxxrtl/.gitignore @@ -0,0 +1 @@ +cxxrtl-test-* diff --git a/yosys/tests/cxxrtl/run-test.sh b/yosys/tests/cxxrtl/run-test.sh new file mode 100755 index 00000000000..89de71c6b26 --- /dev/null +++ b/yosys/tests/cxxrtl/run-test.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +set -ex + +run_subtest () { + local subtest=$1; shift + + ${CC:-gcc} -std=c++11 -O2 -o cxxrtl-test-${subtest} -I../../backends/cxxrtl/runtime test_${subtest}.cc -lstdc++ + ./cxxrtl-test-${subtest} +} + +run_subtest value +run_subtest value_fuzz diff --git a/yosys/tests/cxxrtl/test_value.cc b/yosys/tests/cxxrtl/test_value.cc new file mode 100644 index 00000000000..0750d412e4e --- /dev/null +++ b/yosys/tests/cxxrtl/test_value.cc @@ -0,0 +1,52 @@ +#include +#include + +#include "cxxrtl/cxxrtl.h" + +int main() +{ + { + // shl exceeding Bits should be masked + cxxrtl::value<6> a(1u); + cxxrtl::value<6> b(8u); + cxxrtl::value<6> c = a.shl(b); + assert(c.get() == 0); + } + + { + // sshr of unreasonably large size should sign extend correctly + cxxrtl::value<64> a(0u, 0x80000000u); + cxxrtl::value<64> b(0u, 1u); + cxxrtl::value<64> c = a.sshr(b); + assert(c.get() == 0xffffffffffffffffu); + } + + { + // sshr of exteeding Bits should sign extend correctly + cxxrtl::value<8> a(0x80u); + cxxrtl::value<8> b(10u); + cxxrtl::value<8> c = a.sshr(b); + assert(c.get() == 0xffu); + } + + { + // Sign extension should occur correctly + cxxrtl::value<64> a(0x23456789u, 0x8abcdef1u); + cxxrtl::value<8> b(32u); + cxxrtl::value<64> c = a.sshr(b); + assert(c.get() == 0xffffffff8abcdef1u); + } + + { + // ctlz should work with Bits that are a multiple of chunk size + cxxrtl::value<32> a(0x00040000u); + assert(a.ctlz() == 13); + } + + { + // bmux clears top bits of result + cxxrtl::value<8> val(0x1fu); + cxxrtl::value<1> sel(0u); + assert(val.template bmux<4>(sel).get() == 0xfu); + } +} diff --git a/yosys/tests/cxxrtl/test_value_fuzz.cc b/yosys/tests/cxxrtl/test_value_fuzz.cc new file mode 100644 index 00000000000..4428e9f6e7f --- /dev/null +++ b/yosys/tests/cxxrtl/test_value_fuzz.cc @@ -0,0 +1,251 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "cxxrtl/cxxrtl.h" + +template +T rand_int(T min = std::numeric_limits::min(), T max = std::numeric_limits::max()) +{ + static_assert(std::is_integral::value, "T must be an integral type."); + static_assert(!std::is_same::value && !std::is_same::value, + "Using char with uniform_int_distribution is undefined behavior."); + + static std::mt19937 generator = [] { + std::random_device rd; + std::mt19937 mt{rd()}; + return mt; + }(); + + std::uniform_int_distribution dist(min, max); + return dist(generator); +} + +struct BinaryOperationBase +{ + void tweak_input(uint64_t &a, uint64_t &b) {} +}; + +template +void test_binary_operation_for_bitsize(Operation &op) +{ + constexpr int iteration_count = 10000000; + + constexpr uint64_t mask = std::numeric_limits::max() >> (64 - Bits); + + using chunk_type = typename cxxrtl::value::chunk::type; + constexpr size_t chunk_bits = cxxrtl::value::chunk::bits; + + for (int iteration = 0; iteration < iteration_count; iteration++) { + uint64_t ia = rand_int() >> (64 - Bits); + uint64_t ib = rand_int() >> (64 - Bits); + op.tweak_input(ia, ib); + + cxxrtl::value va, vb; + for (size_t i = 0; i * chunk_bits < Bits; i++) { + va.data[i] = (chunk_type)(ia >> (i * chunk_bits)); + vb.data[i] = (chunk_type)(ib >> (i * chunk_bits)); + } + + uint64_t iresult = op.reference_impl(Bits, ia, ib) & mask; + cxxrtl::value vresult = op.template testing_impl(va, vb); + + for (size_t i = 0; i * chunk_bits < Bits; i++) { + if ((chunk_type)(iresult >> (i * chunk_bits)) != vresult.data[i]) { + std::printf("Test failure:\n"); + std::printf("Bits: %i\n", Bits); + std::printf("a: %016lx\n", ia); + std::printf("b: %016lx\n", ib); + std::printf("iresult: %016lx\n", iresult); + std::printf("vresult: %016lx\n", vresult.template get()); + + std::terminate(); + } + } + } + std::printf("Test passed @ Bits = %i.\n", Bits); +} + +template +void test_binary_operation(Operation &op) +{ + // Test at a variety of bitwidths + test_binary_operation_for_bitsize<8>(op); + test_binary_operation_for_bitsize<32>(op); + test_binary_operation_for_bitsize<42>(op); + test_binary_operation_for_bitsize<63>(op); + test_binary_operation_for_bitsize<64>(op); +} + +template +struct UnaryOperationWrapper : BinaryOperationBase +{ + Operation &op; + + UnaryOperationWrapper(Operation &op) : op(op) {} + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return op.reference_impl(bits, a); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return op.template testing_impl(a); + } +}; + +template +void test_unary_operation(Operation &op) +{ + UnaryOperationWrapper wrapped(op); + test_binary_operation(wrapped); +} + +struct ShlTest : BinaryOperationBase +{ + ShlTest() + { + std::printf("Randomized tests for value::shl:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return b >= 64 ? 0 : a << b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.shl(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} shl; + +struct ShrTest : BinaryOperationBase +{ + ShrTest() + { + std::printf("Randomized tests for value::shr:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return b >= 64 ? 0 : a >> b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.shr(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} shr; + +struct SshrTest : BinaryOperationBase +{ + SshrTest() + { + std::printf("Randomized tests for value::sshr:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + int64_t sa = (int64_t)(a << (64 - bits)); + return sa >> (b >= bits ? 63 : (b + 64 - bits)); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.sshr(b); + } + + void tweak_input(uint64_t &, uint64_t &b) + { + b &= 0x7f; + } +} sshr; + +struct AddTest : BinaryOperationBase +{ + AddTest() + { + std::printf("Randomized tests for value::add:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return a + b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.add(b); + } +} add; + +struct SubTest : BinaryOperationBase +{ + SubTest() + { + std::printf("Randomized tests for value::sub:\n"); + test_binary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a, uint64_t b) + { + return a - b; + } + + template + cxxrtl::value testing_impl(cxxrtl::value a, cxxrtl::value b) + { + return a.sub(b); + } +} sub; + +struct CtlzTest +{ + CtlzTest() + { + std::printf("Randomized tests for value::ctlz:\n"); + test_unary_operation(*this); + } + + uint64_t reference_impl(size_t bits, uint64_t a) + { + if (a == 0) + return bits; + return __builtin_clzl(a) - (64 - bits); + } + + template + cxxrtl::value testing_impl(cxxrtl::value a) + { + size_t result = a.ctlz(); + return cxxrtl::value((cxxrtl::chunk_t)result); + } +} ctlz; + +int main() +{ +} diff --git a/yosys/tests/fmt/.gitignore b/yosys/tests/fmt/.gitignore new file mode 100644 index 00000000000..a36a15ec464 --- /dev/null +++ b/yosys/tests/fmt/.gitignore @@ -0,0 +1,3 @@ +*.log +iverilog-* +yosys-* diff --git a/yosys/tests/fmt/always_comb.v b/yosys/tests/fmt/always_comb.v new file mode 100644 index 00000000000..7147786bebf --- /dev/null +++ b/yosys/tests/fmt/always_comb.v @@ -0,0 +1,24 @@ +module top(input clk); + reg a = 0; + reg b = 0; + wire y; + + sub s (.a(a), .b(b), .y(y)); + + always @(posedge clk) begin + a <= (!a && !b) || (a && !b); + b <= (a && !b) || (a && b); + end +endmodule + +module sub(input a, input b, output wire y); + assign y = a & b; + + // Not fit for our purposes: always @* if (a) $display(a, b, y); + // + // We compare output against iverilog, but async iverilog $display fires + // even before values have propagated -- i.e. combinations of a/b/y will be + // shown where a & b are both 1, but y has not yet taken the value 1. We + // don't, so we specify it in the conditional. + always @* if (y & (y == (a & b))) $display(a, b, y); +endmodule diff --git a/yosys/tests/fmt/always_comb_tb.cc b/yosys/tests/fmt/always_comb_tb.cc new file mode 100644 index 00000000000..5812500535a --- /dev/null +++ b/yosys/tests/fmt/always_comb_tb.cc @@ -0,0 +1,16 @@ +#include "yosys-always_comb.cc" + +int main() +{ + cxxrtl_design::p_top uut1, uut2; + + for (int i = 0; i < 20; ++i) { + uut1.p_clk.set(!uut1.p_clk); + uut1.step(); + + uut2.p_clk.set(!uut2.p_clk); + uut2.step(); + } + + return 0; +} diff --git a/yosys/tests/fmt/always_comb_tb.v b/yosys/tests/fmt/always_comb_tb.v new file mode 100644 index 00000000000..3cc4496a04f --- /dev/null +++ b/yosys/tests/fmt/always_comb_tb.v @@ -0,0 +1,9 @@ +module tb; + reg clk = 0; + + top uut1 (.clk(clk)); + top uut2 (.clk(clk)); + + always #1 clk <= ~clk; + initial #20 $finish; +endmodule diff --git a/yosys/tests/fmt/always_display.v b/yosys/tests/fmt/always_display.v new file mode 100644 index 00000000000..593c5afc08c --- /dev/null +++ b/yosys/tests/fmt/always_display.v @@ -0,0 +1,17 @@ +module m(input clk, rst, en, input [31:0] data); + +`ifdef EVENT_CLK + always @(posedge clk) +`endif +`ifdef EVENT_CLK_RST + always @(posedge clk or negedge rst) +`endif +`ifdef EVENT_STAR + always @(*) +`endif +`ifdef COND_EN + if (en) +`endif + $display("data=%d", data); + +endmodule diff --git a/yosys/tests/fmt/always_full.v b/yosys/tests/fmt/always_full.v new file mode 100644 index 00000000000..4d3df7a615c --- /dev/null +++ b/yosys/tests/fmt/always_full.v @@ -0,0 +1,236 @@ +module always_full(input clk); + + always @(posedge clk) begin + + $display("==> small unsigned %%d"); + $display(":%d:", 16'haa); + $display(":%-d:", 16'haa); + $display(":%+d:", 16'haa); + $display(":%+-d:", 16'haa); + $display(":%0d:", 16'haa); + $display(":%-0d:", 16'haa); + $display(":%+0d:", 16'haa); + $display(":%+-0d:", 16'haa); + $display(":%20d:", 16'haa); + $display(":%-20d:", 16'haa); + $display(":%+20d:", 16'haa); + $display(":%+-20d:", 16'haa); + $display(":%020d:", 16'haa); + $display(":%-020d:", 16'haa); + $display(":%+020d:", 16'haa); + $display(":%+-020d:", 16'haa); + + $display("==> big unsigned %%d"); + $display(":%d:", 16'haaaa); + $display(":%-d:", 16'haaaa); + $display(":%+d:", 16'haaaa); + $display(":%+-d:", 16'haaaa); + $display(":%0d:", 16'haaaa); + $display(":%-0d:", 16'haaaa); + $display(":%+0d:", 16'haaaa); + $display(":%+-0d:", 16'haaaa); + $display(":%20d:", 16'haaaa); + $display(":%-20d:", 16'haaaa); + $display(":%+20d:", 16'haaaa); + $display(":%+-20d:", 16'haaaa); + $display(":%020d:", 16'haaaa); + $display(":%-020d:", 16'haaaa); + $display(":%+020d:", 16'haaaa); + $display(":%+-020d:", 16'haaaa); + + $display("==> small signed %%d"); + $display(":%d:", 16'shaa); + $display(":%-d:", 16'shaa); + $display(":%+d:", 16'shaa); + $display(":%+-d:", 16'shaa); + $display(":%0d:", 16'shaa); + $display(":%-0d:", 16'shaa); + $display(":%+0d:", 16'shaa); + $display(":%+-0d:", 16'shaa); + $display(":%20d:", 16'shaa); + $display(":%-20d:", 16'shaa); + $display(":%+20d:", 16'shaa); + $display(":%+-20d:", 16'shaa); + $display(":%020d:", 16'shaa); + $display(":%-020d:", 16'shaa); + $display(":%+020d:", 16'shaa); + $display(":%+-020d:", 16'shaa); + + $display("==> big signed %%d"); + $display(":%d:", 16'shaaaa); + $display(":%-d:", 16'shaaaa); + $display(":%+d:", 16'shaaaa); + $display(":%+-d:", 16'shaaaa); + $display(":%0d:", 16'shaaaa); + $display(":%-0d:", 16'shaaaa); + $display(":%+0d:", 16'shaaaa); + $display(":%+-0d:", 16'shaaaa); + $display(":%20d:", 16'shaaaa); + $display(":%-20d:", 16'shaaaa); + $display(":%+20d:", 16'shaaaa); + $display(":%+-20d:", 16'shaaaa); + $display(":%020d:", 16'shaaaa); + $display(":%-020d:", 16'shaaaa); + $display(":%+020d:", 16'shaaaa); + $display(":%+-020d:", 16'shaaaa); + + $display("==> small unsigned %%h"); + $display(":%h:", 16'haa); + $display(":%-h:", 16'haa); + $display(":%0h:", 16'haa); + $display(":%-0h:", 16'haa); + $display(":%20h:", 16'haa); + $display(":%-20h:", 16'haa); + $display(":%020h:", 16'haa); + $display(":%-020h:", 16'haa); + + $display("==> big unsigned %%h"); + $display(":%h:", 16'haaaa); + $display(":%-h:", 16'haaaa); + $display(":%0h:", 16'haaaa); + $display(":%-0h:", 16'haaaa); + $display(":%20h:", 16'haaaa); + $display(":%-20h:", 16'haaaa); + $display(":%020h:", 16'haaaa); + $display(":%-020h:", 16'haaaa); + + $display("==> small signed %%h"); + $display(":%h:", 16'shaa); + $display(":%-h:", 16'shaa); + $display(":%0h:", 16'shaa); + $display(":%-0h:", 16'shaa); + $display(":%20h:", 16'shaa); + $display(":%-20h:", 16'shaa); + $display(":%020h:", 16'shaa); + $display(":%-020h:", 16'shaa); + + $display("==> big signed %%h"); + $display(":%h:", 16'shaaaa); + $display(":%-h:", 16'shaaaa); + $display(":%0h:", 16'shaaaa); + $display(":%-0h:", 16'shaaaa); + $display(":%20h:", 16'shaaaa); + $display(":%-20h:", 16'shaaaa); + $display(":%020h:", 16'shaaaa); + $display(":%-020h:", 16'shaaaa); + + $display("==> small unsigned %%o"); + $display(":%o:", 16'haa); + $display(":%-o:", 16'haa); + $display(":%0o:", 16'haa); + $display(":%-0o:", 16'haa); + $display(":%20o:", 16'haa); + $display(":%-20o:", 16'haa); + $display(":%020o:", 16'haa); + $display(":%-020o:", 16'haa); + + $display("==> big unsigned %%o"); + $display(":%o:", 16'haaaa); + $display(":%-o:", 16'haaaa); + $display(":%0o:", 16'haaaa); + $display(":%-0o:", 16'haaaa); + $display(":%20o:", 16'haaaa); + $display(":%-20o:", 16'haaaa); + $display(":%020o:", 16'haaaa); + $display(":%-020o:", 16'haaaa); + + $display("==> small signed %%o"); + $display(":%o:", 16'shaa); + $display(":%-o:", 16'shaa); + $display(":%0o:", 16'shaa); + $display(":%-0o:", 16'shaa); + $display(":%20o:", 16'shaa); + $display(":%-20o:", 16'shaa); + $display(":%020o:", 16'shaa); + $display(":%-020o:", 16'shaa); + + $display("==> big signed %%o"); + $display(":%o:", 16'shaaaa); + $display(":%-o:", 16'shaaaa); + $display(":%0o:", 16'shaaaa); + $display(":%-0o:", 16'shaaaa); + $display(":%20o:", 16'shaaaa); + $display(":%-20o:", 16'shaaaa); + $display(":%020o:", 16'shaaaa); + $display(":%-020o:", 16'shaaaa); + + $display("==> small unsigned %%b"); + $display(":%b:", 16'haa); + $display(":%-b:", 16'haa); + $display(":%0b:", 16'haa); + $display(":%-0b:", 16'haa); + $display(":%20b:", 16'haa); + $display(":%-20b:", 16'haa); + $display(":%020b:", 16'haa); + $display(":%-020b:", 16'haa); + + $display("==> big unsigned %%b"); + $display(":%b:", 16'haaaa); + $display(":%-b:", 16'haaaa); + $display(":%0b:", 16'haaaa); + $display(":%-0b:", 16'haaaa); + $display(":%20b:", 16'haaaa); + $display(":%-20b:", 16'haaaa); + $display(":%020b:", 16'haaaa); + $display(":%-020b:", 16'haaaa); + + $display("==> small signed %%b"); + $display(":%b:", 16'shaa); + $display(":%-b:", 16'shaa); + $display(":%0b:", 16'shaa); + $display(":%-0b:", 16'shaa); + $display(":%20b:", 16'shaa); + $display(":%-20b:", 16'shaa); + $display(":%020b:", 16'shaa); + $display(":%-020b:", 16'shaa); + + $display("==> big signed %%b"); + $display(":%b:", 16'shaaaa); + $display(":%-b:", 16'shaaaa); + $display(":%0b:", 16'shaaaa); + $display(":%-0b:", 16'shaaaa); + $display(":%20b:", 16'shaaaa); + $display(":%-20b:", 16'shaaaa); + $display(":%020b:", 16'shaaaa); + $display(":%-020b:", 16'shaaaa); + + $display("==> time %%t"); + $display(":%t:", $time); + $display(":%-t:", $time); + $display(":%0t:", $time); + $display(":%-0t:", $time); + $display(":%10t:", $time); + $display(":%-10t:", $time); + $display(":%015t:", $time); + $display(":%-015t:", $time); + + $display("===> %%s"); + $display(":%10s:", "foo"); + $display(":%010s:", "foo"); + $display(":%-10s:", "foo"); + $display(":%-010s:", "foo"); + + $display("===> %%c"); + $display(":%10c:", "foo"); + $display(":%010c:", "foo"); + $display(":%-10c:", "foo"); + $display(":%-010c:", "foo"); + + $display("==> aliases"); + $display(":%x:", 16'shaa); + $display(":%X:", 16'shaa); + $display(":%H:", 16'shaa); + $display(":%O:", 16'shaa); + $display(":%B:", 16'shaa); + + $display("==> default base"); + $displayh(16'haa); + $displayo(16'haa); + $displayb(16'haa); + + $display("==> write/format"); + $display("%d", 1, "%d", 1); + + end + +endmodule diff --git a/yosys/tests/fmt/always_full_tb.cc b/yosys/tests/fmt/always_full_tb.cc new file mode 100644 index 00000000000..94991ca25b5 --- /dev/null +++ b/yosys/tests/fmt/always_full_tb.cc @@ -0,0 +1,14 @@ +#include "yosys-always_full.cc" + +int main() +{ + struct : public performer { + int64_t vlog_time() const override { return 1; } + void on_print(const lazy_fmt &output, const cxxrtl::metadata_map &) override { std::cerr << output(); } + } performer; + + cxxrtl_design::p_always__full uut; + uut.p_clk.set(!uut.p_clk); + uut.step(&performer); + return 0; +} diff --git a/yosys/tests/fmt/always_full_tb.v b/yosys/tests/fmt/always_full_tb.v new file mode 100644 index 00000000000..0c2599cc263 --- /dev/null +++ b/yosys/tests/fmt/always_full_tb.v @@ -0,0 +1,12 @@ +module always_full_tb; + + reg clk = 0; + + always_full uut (.clk(clk)); + + always begin + #1 clk <= ~clk; + #1 $finish; + end + +endmodule diff --git a/yosys/tests/fmt/display_lm.v b/yosys/tests/fmt/display_lm.v new file mode 100644 index 00000000000..d96f233f064 --- /dev/null +++ b/yosys/tests/fmt/display_lm.v @@ -0,0 +1,12 @@ +module top; + mid mid_uut (); +endmodule + +module mid (); + bot bot_uut (); +endmodule + +module bot (); + initial $display("%%l: %l\n%%m: %m"); + always $display("%%l: %l\n%%m: %m"); +endmodule diff --git a/yosys/tests/fmt/display_lm_tb.cc b/yosys/tests/fmt/display_lm_tb.cc new file mode 100644 index 00000000000..7a593d72919 --- /dev/null +++ b/yosys/tests/fmt/display_lm_tb.cc @@ -0,0 +1,9 @@ +#include "yosys-display_lm.cc" + +int main() +{ + cxxrtl_design::p_top uut; + + uut.step(); + return 0; +} diff --git a/yosys/tests/fmt/fuzz/.gitignore b/yosys/tests/fmt/fuzz/.gitignore new file mode 100644 index 00000000000..88ea7e2ef91 --- /dev/null +++ b/yosys/tests/fmt/fuzz/.gitignore @@ -0,0 +1,2 @@ +fuzztest +build diff --git a/yosys/tests/fmt/fuzz/CMakeLists.txt b/yosys/tests/fmt/fuzz/CMakeLists.txt new file mode 100644 index 00000000000..6f7c43da888 --- /dev/null +++ b/yosys/tests/fmt/fuzz/CMakeLists.txt @@ -0,0 +1,23 @@ +cmake_minimum_required(VERSION 3.14) +project(cxxrtl_division_fuzz) + +set(CMAKE_CXX_STANDARD 17) + +add_subdirectory(fuzztest) + +enable_testing() + +include(GoogleTest) + +fuzztest_setup_fuzzing_flags() + +include_directories(../../..) + +add_executable( + x_test + x_test.cc + ../../../libs/bigint/BigUnsigned.cc +) + +link_fuzztest(x_test) +gtest_discover_tests(x_test) diff --git a/yosys/tests/fmt/fuzz/x_test.cc b/yosys/tests/fmt/fuzz/x_test.cc new file mode 100644 index 00000000000..ee061861f90 --- /dev/null +++ b/yosys/tests/fmt/fuzz/x_test.cc @@ -0,0 +1,44 @@ +#include "fuzztest/fuzztest.h" +#include "gtest/gtest.h" + +#include +#include "backends/cxxrtl/cxxrtl.h" +#include "libs/bigint/BigUnsigned.hh" + +using namespace cxxrtl_yosys; + +void Formats128BitIntegers(chunk_t x0, chunk_t x1, chunk_t x2, chunk_t x3, bool signed_) +{ + // Compare output to BigUnsigned. + value<128> v; + v = v.blit<127, 64>(value<64>{x1, x0}); + v = v.blit<63, 0>(value<64>{x3, x2}); + + std::ostringstream oss; + oss << value_formatted<128>(v, false, false, ' ', 0, 10, signed_, false, false); + auto actual = oss.str(); + + BigUnsigned u; + bool negative = signed_ && v.is_neg(); + if (negative) + v = v.neg(); + u.bitShiftLeft(v.slice<127, 64>().val().get(), 64); + u.bitOr(u, v.slice<63, 0>().val().get()); + + std::string expected; + + if (u.isZero()) { + expected = "0"; + } else { + while (!u.isZero()) { + expected += '0' + (u % 10).toInt(); + u /= 10; + } + if (negative) + expected += '-'; + std::reverse(expected.begin(), expected.end()); + } + + EXPECT_EQ(actual, expected); +} +FUZZ_TEST(CxxrtlDivisionFuzz, Formats128BitIntegers); diff --git a/yosys/tests/fmt/initial_display.v b/yosys/tests/fmt/initial_display.v new file mode 100644 index 00000000000..d3ef9ed7691 --- /dev/null +++ b/yosys/tests/fmt/initial_display.v @@ -0,0 +1,255 @@ +module m; + initial $display("<<>>"); + + initial $display("==> small unsigned %%d"); + initial $display(":%d:", 16'haa); + initial $display(":%-d:", 16'haa); + initial $display(":%+d:", 16'haa); + initial $display(":%+-d:", 16'haa); + initial $display(":%0d:", 16'haa); + initial $display(":%-0d:", 16'haa); + initial $display(":%+0d:", 16'haa); + initial $display(":%+-0d:", 16'haa); + initial $display(":%20d:", 16'haa); + initial $display(":%-20d:", 16'haa); + initial $display(":%+20d:", 16'haa); + initial $display(":%+-20d:", 16'haa); + initial $display(":%020d:", 16'haa); + initial $display(":%-020d:", 16'haa); + initial $display(":%+020d:", 16'haa); + initial $display(":%+-020d:", 16'haa); + + initial $display("==> big unsigned %%d"); + initial $display(":%d:", 16'haaaa); + initial $display(":%-d:", 16'haaaa); + initial $display(":%+d:", 16'haaaa); + initial $display(":%+-d:", 16'haaaa); + initial $display(":%0d:", 16'haaaa); + initial $display(":%-0d:", 16'haaaa); + initial $display(":%+0d:", 16'haaaa); + initial $display(":%+-0d:", 16'haaaa); + initial $display(":%20d:", 16'haaaa); + initial $display(":%-20d:", 16'haaaa); + initial $display(":%+20d:", 16'haaaa); + initial $display(":%+-20d:", 16'haaaa); + initial $display(":%020d:", 16'haaaa); + initial $display(":%-020d:", 16'haaaa); + initial $display(":%+020d:", 16'haaaa); + initial $display(":%+-020d:", 16'haaaa); + + initial $display("==> small signed %%d"); + initial $display(":%d:", 16'shaa); + initial $display(":%-d:", 16'shaa); + initial $display(":%+d:", 16'shaa); + initial $display(":%+-d:", 16'shaa); + initial $display(":%0d:", 16'shaa); + initial $display(":%-0d:", 16'shaa); + initial $display(":%+0d:", 16'shaa); + initial $display(":%+-0d:", 16'shaa); + initial $display(":%20d:", 16'shaa); + initial $display(":%-20d:", 16'shaa); + initial $display(":%+20d:", 16'shaa); + initial $display(":%+-20d:", 16'shaa); + initial $display(":%020d:", 16'shaa); + initial $display(":%-020d:", 16'shaa); + initial $display(":%+020d:", 16'shaa); + initial $display(":%+-020d:", 16'shaa); + + initial $display("==> big signed %%d"); + initial $display(":%d:", 16'shaaaa); + initial $display(":%-d:", 16'shaaaa); + initial $display(":%+d:", 16'shaaaa); + initial $display(":%+-d:", 16'shaaaa); + initial $display(":%0d:", 16'shaaaa); + initial $display(":%-0d:", 16'shaaaa); + initial $display(":%+0d:", 16'shaaaa); + initial $display(":%+-0d:", 16'shaaaa); + initial $display(":%20d:", 16'shaaaa); + initial $display(":%-20d:", 16'shaaaa); + initial $display(":%+20d:", 16'shaaaa); + initial $display(":%+-20d:", 16'shaaaa); + initial $display(":%020d:", 16'shaaaa); + initial $display(":%-020d:", 16'shaaaa); + initial $display(":%+020d:", 16'shaaaa); + initial $display(":%+-020d:", 16'shaaaa); + + initial $display("==> small unsigned %%h"); + initial $display(":%h:", 16'haa); + initial $display(":%-h:", 16'haa); + initial $display(":%0h:", 16'haa); + initial $display(":%-0h:", 16'haa); + initial $display(":%20h:", 16'haa); + initial $display(":%-20h:", 16'haa); + initial $display(":%020h:", 16'haa); + initial $display(":%-020h:", 16'haa); + + initial $display("==> big unsigned %%h"); + initial $display(":%h:", 16'haaaa); + initial $display(":%-h:", 16'haaaa); + initial $display(":%0h:", 16'haaaa); + initial $display(":%-0h:", 16'haaaa); + initial $display(":%20h:", 16'haaaa); + initial $display(":%-20h:", 16'haaaa); + initial $display(":%020h:", 16'haaaa); + initial $display(":%-020h:", 16'haaaa); + + initial $display("==> small signed %%h"); + initial $display(":%h:", 16'shaa); + initial $display(":%-h:", 16'shaa); + initial $display(":%0h:", 16'shaa); + initial $display(":%-0h:", 16'shaa); + initial $display(":%20h:", 16'shaa); + initial $display(":%-20h:", 16'shaa); + initial $display(":%020h:", 16'shaa); + initial $display(":%-020h:", 16'shaa); + + initial $display("==> big signed %%h"); + initial $display(":%h:", 16'shaaaa); + initial $display(":%-h:", 16'shaaaa); + initial $display(":%0h:", 16'shaaaa); + initial $display(":%-0h:", 16'shaaaa); + initial $display(":%20h:", 16'shaaaa); + initial $display(":%-20h:", 16'shaaaa); + initial $display(":%020h:", 16'shaaaa); + initial $display(":%-020h:", 16'shaaaa); + + initial $display("==> small unsigned %%o"); + initial $display(":%o:", 16'haa); + initial $display(":%-o:", 16'haa); + initial $display(":%0o:", 16'haa); + initial $display(":%-0o:", 16'haa); + initial $display(":%20o:", 16'haa); + initial $display(":%-20o:", 16'haa); + initial $display(":%020o:", 16'haa); + initial $display(":%-020o:", 16'haa); + + initial $display("==> big unsigned %%o"); + initial $display(":%o:", 16'haaaa); + initial $display(":%-o:", 16'haaaa); + initial $display(":%0o:", 16'haaaa); + initial $display(":%-0o:", 16'haaaa); + initial $display(":%20o:", 16'haaaa); + initial $display(":%-20o:", 16'haaaa); + initial $display(":%020o:", 16'haaaa); + initial $display(":%-020o:", 16'haaaa); + + initial $display("==> small signed %%o"); + initial $display(":%o:", 16'shaa); + initial $display(":%-o:", 16'shaa); + initial $display(":%0o:", 16'shaa); + initial $display(":%-0o:", 16'shaa); + initial $display(":%20o:", 16'shaa); + initial $display(":%-20o:", 16'shaa); + initial $display(":%020o:", 16'shaa); + initial $display(":%-020o:", 16'shaa); + + initial $display("==> big signed %%o"); + initial $display(":%o:", 16'shaaaa); + initial $display(":%-o:", 16'shaaaa); + initial $display(":%0o:", 16'shaaaa); + initial $display(":%-0o:", 16'shaaaa); + initial $display(":%20o:", 16'shaaaa); + initial $display(":%-20o:", 16'shaaaa); + initial $display(":%020o:", 16'shaaaa); + initial $display(":%-020o:", 16'shaaaa); + + initial $display("==> small unsigned %%b"); + initial $display(":%b:", 16'haa); + initial $display(":%-b:", 16'haa); + initial $display(":%0b:", 16'haa); + initial $display(":%-0b:", 16'haa); + initial $display(":%20b:", 16'haa); + initial $display(":%-20b:", 16'haa); + initial $display(":%020b:", 16'haa); + initial $display(":%-020b:", 16'haa); + + initial $display("==> big unsigned %%b"); + initial $display(":%b:", 16'haaaa); + initial $display(":%-b:", 16'haaaa); + initial $display(":%0b:", 16'haaaa); + initial $display(":%-0b:", 16'haaaa); + initial $display(":%20b:", 16'haaaa); + initial $display(":%-20b:", 16'haaaa); + initial $display(":%020b:", 16'haaaa); + initial $display(":%-020b:", 16'haaaa); + + initial $display("==> small signed %%b"); + initial $display(":%b:", 16'shaa); + initial $display(":%-b:", 16'shaa); + initial $display(":%0b:", 16'shaa); + initial $display(":%-0b:", 16'shaa); + initial $display(":%20b:", 16'shaa); + initial $display(":%-20b:", 16'shaa); + initial $display(":%020b:", 16'shaa); + initial $display(":%-020b:", 16'shaa); + + initial $display("==> big signed %%b"); + initial $display(":%b:", 16'shaaaa); + initial $display(":%-b:", 16'shaaaa); + initial $display(":%0b:", 16'shaaaa); + initial $display(":%-0b:", 16'shaaaa); + initial $display(":%20b:", 16'shaaaa); + initial $display(":%-20b:", 16'shaaaa); + initial $display(":%020b:", 16'shaaaa); + initial $display(":%-020b:", 16'shaaaa); + + initial $display("==> time %%t"); + initial $display(":%t:", $time); + initial $display(":%-t:", $time); + initial $display(":%0t:", $time); + initial $display(":%-0t:", $time); + initial $display(":%10t:", $time); + initial $display(":%-10t:", $time); + initial $display(":%015t:", $time); + initial $display(":%-015t:", $time); + + initial $display("===> %%s"); + initial $display(":%10s:", "foo"); + initial $display(":%010s:", "foo"); + initial $display(":%-10s:", "foo"); + initial $display(":%-010s:", "foo"); + + initial $display("===> %%c"); + initial $display(":%10c:", "foo"); + initial $display(":%010c:", "foo"); + initial $display(":%-10c:", "foo"); + initial $display(":%-010c:", "foo"); + + initial $display("==> aliases"); + initial $display(":%x:", 16'shaa); + initial $display(":%X:", 16'shaa); + initial $display(":%H:", 16'shaa); + initial $display(":%O:", 16'shaa); + initial $display(":%B:", 16'shaa); + + initial $display("==> x/z"); + initial $display(":%d:", 16'b1010101010101010); + initial $display(":%d:", 16'b101010101010101x); + initial $display(":%d:", 16'b101010101010101z); + initial $display(":%x:", 16'b1010101010101010); + initial $display(":%x:", 16'b101010101010101x); + initial $display(":%x:", 16'b101010101010101z); + initial $display(":%x:", 16'b101010101010xxxx); + initial $display(":%x:", 16'b101010101010zzzz); + initial $display(":%o:", 16'b1010101010101010); + initial $display(":%o:", 16'b101010101010101x); + initial $display(":%o:", 16'b101010101010101z); + initial $display(":%o:", 16'b1010101010101xxx); + initial $display(":%o:", 16'b1010101010101zzz); + initial $display(":%b:", 16'b1010101010101010); + initial $display(":%b:", 16'b101010101010101x); + initial $display(":%b:", 16'b101010101010101z); + + initial $display("==> default base"); + initial $displayh(16'haa); + initial $displayo(16'haa); + initial $displayb(16'haa); + + initial $display("==> write/format"); + initial $display("%d", 1, "%d", 1); + // this one hits a bug in iverilog: + // initial $display("%s", $sformatf("%d", 1, "%d", 1)); + + initial $display("<<>>"); + +endmodule diff --git a/yosys/tests/fmt/roundtrip.v b/yosys/tests/fmt/roundtrip.v new file mode 100644 index 00000000000..7b50039cd26 --- /dev/null +++ b/yosys/tests/fmt/roundtrip.v @@ -0,0 +1,22 @@ +module m(input clk, input `SIGN [31:0] data); + + always @(posedge clk) + // All on a single line to avoid order effects. +`ifdef BASE_DEC + $display(":%d:%-d:%+d:%+-d:%0d:%-0d:%+0d:%+-0d:%20d:%-20d:%+20d:%+-20d:%020d:%-020d:%+020d:%+-020d:", + data, data, data, data, data, data, data, data, data, data, data, data, data, data, data, data); +`endif +`ifdef BASE_HEX + $display(":%h:%-h:%0h:%-0h:%20h:%-20h:%020h:%-020h:", + data, data, data, data, data, data, data, data); +`endif +`ifdef BASE_OCT + $display(":%o:%-o:%0o:%-0o:%20o:%-20o:%020o:%-020o:", + data, data, data, data, data, data, data, data); +`endif +`ifdef BASE_BIN + $display(":%b:%-b:%0b:%-0b:%20b:%-20b:%020b:%-020b:", + data, data, data, data, data, data, data, data); +`endif + +endmodule diff --git a/yosys/tests/fmt/roundtrip_tb.v b/yosys/tests/fmt/roundtrip_tb.v new file mode 100644 index 00000000000..988b8d8c2c0 --- /dev/null +++ b/yosys/tests/fmt/roundtrip_tb.v @@ -0,0 +1,13 @@ +module tb; + reg clk = 1'b0; + reg [31:0] data; + + m dut(.clk(clk), .data(data)); + + initial begin + data = 32'haa; + #10; clk = 1; #10; clk = 0; + data = 32'haaaa; + #10; clk = 1; #10; clk = 0; + end +endmodule diff --git a/yosys/tests/fmt/run-test.sh b/yosys/tests/fmt/run-test.sh new file mode 100644 index 00000000000..998047f830c --- /dev/null +++ b/yosys/tests/fmt/run-test.sh @@ -0,0 +1,77 @@ +#!/usr/bin/env bash + +set -ex + +../../yosys -p 'read_verilog initial_display.v' | awk '/<<>>/,/<<>>/ {print $0}' >yosys-initial_display.log +iverilog -o iverilog-initial_display initial_display.v +./iverilog-initial_display >iverilog-initial_display.log +diff yosys-initial_display.log iverilog-initial_display.log + +test_always_display () { + local subtest=$1; shift + ../../yosys -p "read_verilog $* always_display.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-1.v + ../../yosys -p "read_verilog yosys-always_display-${subtest}-1.v; proc; opt_expr -mux_bool; clean" -o yosys-always_display-${subtest}-2.v + diff yosys-always_display-${subtest}-1.v yosys-always_display-${subtest}-2.v +} + +test_always_display clk -DEVENT_CLK +test_always_display clk_rst -DEVENT_CLK_RST +test_always_display star -DEVENT_STAR + +test_always_display clk_en -DEVENT_CLK -DCOND_EN +test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN +test_always_display star_en -DEVENT_STAR -DCOND_EN + +test_roundtrip () { + local subtest=$1; shift + ../../yosys -p "read_verilog $* roundtrip.v; proc; clean" -o yosys-roundtrip-${subtest}-1.v + ../../yosys -p "read_verilog yosys-roundtrip-${subtest}-1.v; proc; clean" -o yosys-roundtrip-${subtest}-2.v + diff yosys-roundtrip-${subtest}-1.v yosys-roundtrip-${subtest}-2.v + + iverilog $* -o iverilog-roundtrip-${subtest} roundtrip.v roundtrip_tb.v + ./iverilog-roundtrip-${subtest} >iverilog-roundtrip-${subtest}.log + iverilog $* -o iverilog-roundtrip-${subtest}-1 yosys-roundtrip-${subtest}-1.v roundtrip_tb.v + ./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-1.log + iverilog $* -o iverilog-roundtrip-${subtest}-2 yosys-roundtrip-${subtest}-2.v roundtrip_tb.v + ./iverilog-roundtrip-${subtest}-1 >iverilog-roundtrip-${subtest}-2.log + diff iverilog-roundtrip-${subtest}.log iverilog-roundtrip-${subtest}-1.log + diff iverilog-roundtrip-${subtest}-1.log iverilog-roundtrip-${subtest}-2.log +} + +test_roundtrip dec_unsigned -DBASE_DEC -DSIGN="" +test_roundtrip dec_signed -DBASE_DEC -DSIGN="signed" +test_roundtrip hex_unsigned -DBASE_HEX -DSIGN="" +test_roundtrip hex_signed -DBASE_HEX -DSIGN="signed" +test_roundtrip oct_unsigned -DBASE_HEX -DSIGN="" +test_roundtrip oct_signed -DBASE_HEX -DSIGN="signed" +test_roundtrip bin_unsigned -DBASE_HEX -DSIGN="" +test_roundtrip bin_signed -DBASE_HEX -DSIGN="signed" + +test_cxxrtl () { + local subtest=$1; shift + + ../../yosys -p "read_verilog ${subtest}.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-${subtest}.cc" + ${CC:-gcc} -std=c++11 -o yosys-${subtest} -I../../backends/cxxrtl/runtime ${subtest}_tb.cc -lstdc++ + ./yosys-${subtest} 2>yosys-${subtest}.log + iverilog -o iverilog-${subtest} ${subtest}.v ${subtest}_tb.v + ./iverilog-${subtest} |grep -v '\$finish called' >iverilog-${subtest}.log + diff iverilog-${subtest}.log yosys-${subtest}.log +} + +test_cxxrtl always_full +test_cxxrtl always_comb + +# Ensure Verilog backend preserves behaviour of always block with multiple $displays. +../../yosys -p "read_verilog always_full.v; prep; clean" -o yosys-always_full-1.v +iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v +./iverilog-always_full-1 |grep -v '\$finish called' >iverilog-always_full-1.log +diff iverilog-always_full.log iverilog-always_full-1.log + +../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log +../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" +${CC:-gcc} -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++ +./yosys-display_lm_cc >yosys-display_lm_cc.log +for log in yosys-display_lm.log yosys-display_lm_cc.log; do + grep "^%l: \\\\bot\$" "$log" + grep "^%m: \\\\bot\$" "$log" +done diff --git a/yosys/tests/fsm/run-test.sh b/yosys/tests/fsm/run-test.sh index fbdcbf048f0..dc60c69c4ac 100755 --- a/yosys/tests/fsm/run-test.sh +++ b/yosys/tests/fsm/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # run this test many times: # time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' diff --git a/yosys/tests/gen-tests-makefile.sh b/yosys/tests/gen-tests-makefile.sh index 3df36a963b1..6bf91b4dc34 100755 --- a/yosys/tests/gen-tests-makefile.sh +++ b/yosys/tests/gen-tests-makefile.sh @@ -75,7 +75,7 @@ generate_tests() { if [[ $do_sv = true ]]; then for x in *.sv; do if [ ! -f "${x%.sv}.ys" ]; then - generate_ys_test "$x" "-p \"prep -top top; sat -enable_undef -verify -prove-asserts\" $yosys_args" + generate_ys_test "$x" "-p \"prep -top top; async2sync; sat -enable_undef -verify -prove-asserts\" $yosys_args" fi; done fi; diff --git a/yosys/tests/hana/run-test.sh b/yosys/tests/hana/run-test.sh index 878c80b3f06..99be37f5efb 100755 --- a/yosys/tests/hana/run-test.sh +++ b/yosys/tests/hana/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash OPTIND=1 seed="" # default to no seed specified diff --git a/yosys/tests/liberty/run-test.sh b/yosys/tests/liberty/run-test.sh index 61f19b09bc7..19ce0667d51 100755 --- a/yosys/tests/liberty/run-test.sh +++ b/yosys/tests/liberty/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e for x in *.lib; do diff --git a/yosys/tests/lut/run-test.sh b/yosys/tests/lut/run-test.sh index f8964f146e5..a10559cac4b 100755 --- a/yosys/tests/lut/run-test.sh +++ b/yosys/tests/lut/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e for x in *.v; do echo "Running $x.." diff --git a/yosys/tests/memfile/run-test.sh b/yosys/tests/memfile/run-test.sh index e43ddd09374..db0ec54ee75 100755 --- a/yosys/tests/memfile/run-test.sh +++ b/yosys/tests/memfile/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/yosys/tests/memlib/generate.py b/yosys/tests/memlib/generate.py index f40210501db..46eff6b43e3 100644 --- a/yosys/tests/memlib/generate.py +++ b/yosys/tests/memlib/generate.py @@ -1513,6 +1513,28 @@ def __init__(self, name, src, libs, defs, cells): ["block_sp_full"], defs, {"RAM_BLOCK_SP": 1, "$*": add_logic} )) + +ROM_CASE = """ +module rom(input clk, input [2:0] addr, {attr}output reg [7:0] data); + +always @(posedge clk) begin + case (addr) + 3'b000: data <= 8'h12; + 3'b001: data <= 8'hAB; + 3'b010: data <= 8'h42; + 3'b011: data <= 8'h23; + 3'b100: data <= 8'h66; + 3'b101: data <= 8'hC0; + 3'b110: data <= 8'h3F; + 3'b111: data <= 8'h95; + endcase +end + +endmodule +""" + +TESTS.append(Test("rom_case", ROM_CASE.format(attr=""), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 0})) +TESTS.append(Test("rom_case_block", ROM_CASE.format(attr="(* rom_style = \"block\" *) "), ["block_sdp"], [], {"RAM_BLOCK_SDP" : 1})) with open("run-test.mk", "w") as mf: mf.write("ifneq ($(strip $(SEED)),)\n") diff --git a/yosys/tests/memlib/run-test.sh b/yosys/tests/memlib/run-test.sh index abe88a6cbcd..5f230a03e57 100755 --- a/yosys/tests/memlib/run-test.sh +++ b/yosys/tests/memlib/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -eu OPTIND=1 diff --git a/yosys/tests/memories/run-test.sh b/yosys/tests/memories/run-test.sh index c65066a9c95..4f1da7ce7c2 100755 --- a/yosys/tests/memories/run-test.sh +++ b/yosys/tests/memories/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -e diff --git a/yosys/tests/opt/run-test.sh b/yosys/tests/opt/run-test.sh index 2007cd6e4cc..74589dfeb57 100755 --- a/yosys/tests/opt/run-test.sh +++ b/yosys/tests/opt/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash set -eu source ../gen-tests-makefile.sh run_tests --yosys-scripts diff --git a/yosys/tests/opt_share/run-test.sh b/yosys/tests/opt_share/run-test.sh index e0008a259b2..e80cd4214d0 100755 --- a/yosys/tests/opt_share/run-test.sh +++ b/yosys/tests/opt_share/run-test.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash # run this test many times: # time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' diff --git a/yosys/tests/proc/clean_undef_case.ys b/yosys/tests/proc/clean_undef_case.ys new file mode 100644 index 00000000000..c874b08c017 --- /dev/null +++ b/yosys/tests/proc/clean_undef_case.ys @@ -0,0 +1,37 @@ +read_rtlil < $1.tpl <&2; exit 1' ERR @@ -37,14 +37,17 @@ EOT if ../../yosys -q -p 'verific -sv chparam1.sv'; then ../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' ../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' fi ../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' diff --git a/yosys/tests/various/clk2fflogic_effects.sh b/yosys/tests/various/clk2fflogic_effects.sh new file mode 100755 index 00000000000..b51424d1b8a --- /dev/null +++ b/yosys/tests/various/clk2fflogic_effects.sh @@ -0,0 +1,27 @@ +#!/usr/bin/env bash +set -ex + +../../yosys -p " +read_verilog -formal -DFAST clk2fflogic_effects.sv +hierarchy -top top; proc;; +tee -o clk2fflogic_effects.sim.log sim -fst /tmp/sim.fst -q -n 16 +" + +../../yosys -p " +read_verilog -formal -DFAST clk2fflogic_effects.sv +hierarchy -top top; proc;; +clk2fflogic;; + +tee -o clk2fflogic_effects.clk2fflogic.log sim -fst /tmp/sim.fst -q -n 16 +" + +iverilog -g2012 -o clk2fflogic_effects.iv.out clk2fflogic_effects.sv + +./clk2fflogic_effects.iv.out > clk2fflogic_effects.iv.log + +sort clk2fflogic_effects.iv.log > clk2fflogic_effects.iv.sorted.log +tail +3 clk2fflogic_effects.sim.log | sort > clk2fflogic_effects.sim.sorted.log +tail +3 clk2fflogic_effects.clk2fflogic.log | sort > clk2fflogic_effects.clk2fflogic.sorted.log + +cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.sim.sorted.log +cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.clk2fflogic.sorted.log diff --git a/yosys/tests/various/clk2fflogic_effects.sv b/yosys/tests/various/clk2fflogic_effects.sv new file mode 100644 index 00000000000..b571cf3fe7d --- /dev/null +++ b/yosys/tests/various/clk2fflogic_effects.sv @@ -0,0 +1,82 @@ +module top; + +(* gclk *) +reg gclk; + +reg clk = 0; +always @(posedge gclk) + clk <= !clk; + +reg [4:0] counter = 0; + +reg eff_0_trg = '0; +reg eff_0_en = '0; + +reg eff_1_trgA = '0; +reg eff_1_trgB = '0; +reg eff_1_en = '0; + +reg eff_2_trgA = '0; +reg eff_2_trgB = '0; +reg eff_2_en = '0; + +`ifdef FAST +always @(posedge gclk) begin +`else +always @(posedge clk) begin +`endif + counter <= counter + 1; + + eff_0_trg = 32'b00000000000000110011001100101010 >> counter; + eff_0_en <= 32'b00000000000001100000110110110110 >> counter; + + eff_1_trgA = 32'b00000000000000000011110000011110 >> counter; + eff_1_trgB = 32'b00000000000000001111000001111000 >> counter; + eff_1_en <= 32'b00000000000000001010101010101010 >> counter; + + eff_2_trgA = counter[0]; + eff_2_trgB = !counter[0]; + eff_2_en <= 32'b00000000000000000000001111111100 >> counter; +end + +always @(posedge eff_0_trg) + if (eff_0_en) + $display("%02d: eff0 +", counter); + +always @(negedge eff_0_trg) + if (eff_0_en) + $display("%02d: eff0 -", counter); + +always @(posedge eff_0_trg, negedge eff_0_trg) + if (eff_0_en) + $display("%02d: eff0 *", counter); + +always @(posedge eff_1_trgA, posedge eff_1_trgB) + if (eff_1_en) + $display("%02d: eff1 ++", counter); + +always @(posedge eff_1_trgA, negedge eff_1_trgB) + if (eff_1_en) + $display("%02d: eff1 +-", counter); + +always @(negedge eff_1_trgA, posedge eff_1_trgB) + if (eff_1_en) + $display("%02d: eff1 -+", counter); + +always @(negedge eff_1_trgA, negedge eff_1_trgB) + if (eff_1_en) + $display("%02d: eff1 --", counter); + +always @(posedge eff_2_trgA, posedge eff_2_trgB) + if (eff_2_en) + $display("repeated"); + +`ifdef __ICARUS__ +initial gclk = 0; +always @(gclk) gclk <= #5 !gclk; +always @(posedge gclk) + if (counter == 31) + $finish(0); +`endif + +endmodule diff --git a/yosys/tests/various/const_arg_loop.ys b/yosys/tests/various/const_arg_loop.ys index 392532213b4..01bea704499 100644 --- a/yosys/tests/various/const_arg_loop.ys +++ b/yosys/tests/various/const_arg_loop.ys @@ -3,4 +3,5 @@ hierarchy proc opt -full select -module top +async2sync sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/yosys/tests/various/const_func.ys b/yosys/tests/various/const_func.ys index 2f60acfe670..d982c3a43fa 100644 --- a/yosys/tests/various/const_func.ys +++ b/yosys/tests/various/const_func.ys @@ -4,4 +4,5 @@ proc flatten opt -full select -module top +async2sync sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/yosys/tests/various/countbits.ys b/yosys/tests/various/countbits.ys index a556f7c5d83..f2db9cfe1f6 100644 --- a/yosys/tests/various/countbits.ys +++ b/yosys/tests/various/countbits.ys @@ -4,4 +4,5 @@ proc flatten opt -full select -module top +async2sync sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/yosys/tests/various/dynamic_part_select.ys b/yosys/tests/various/dynamic_part_select.ys index 2dc061e899b..9e303b9db2e 100644 --- a/yosys/tests/various/dynamic_part_select.ys +++ b/yosys/tests/various/dynamic_part_select.ys @@ -69,6 +69,24 @@ design -copy-from gate -as gate gate miter -equiv -make_assert -make_outcmp -flatten gold gate equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv +### For-loop select, one dynamic input, (* nowrshmsk *) +design -reset +read_verilog ./dynamic_part_select/forloop_select_nowrshmsk.v +proc +rename -top gold +design -stash gold + +read_verilog ./dynamic_part_select/forloop_select_gate.v +proc +rename -top gate +design -stash gate + +design -copy-from gold -as gold gold +design -copy-from gate -as gate gate + +miter -equiv -make_assert -make_outcmp -flatten gold gate equiv +sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv + #### Double loop (part-select, reset) ### design -reset read_verilog ./dynamic_part_select/reset_test.v diff --git a/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v b/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v new file mode 100644 index 00000000000..75415c3130e --- /dev/null +++ b/yosys/tests/various/dynamic_part_select/forloop_select_nowrshmsk.v @@ -0,0 +1,20 @@ +`default_nettype none +module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) + (input wire clk, + input wire [CTRLW-1:0] ctrl, + input wire [DINW-1:0] din, + input wire en, + (* nowrshmsk *) + output reg [WIDTH-1:0] dout); + + reg [SELW:0] sel; + localparam SLICE = WIDTH/(SELW**2); + + always @(posedge clk) + begin + if (en) begin + for (sel = 0; sel <= 4'hf; sel=sel+1'b1) + dout[(ctrl*sel)+:SLICE] <= din; + end + end +endmodule diff --git a/yosys/tests/various/logger_fail.sh b/yosys/tests/various/logger_fail.sh index 19b65000718..c318b648d11 100755 --- a/yosys/tests/various/logger_fail.sh +++ b/yosys/tests/various/logger_fail.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash fail() { echo "$1" >&2 diff --git a/yosys/tests/various/param_struct.ys b/yosys/tests/various/param_struct.ys index b8de67968d5..bb26b61d586 100644 --- a/yosys/tests/various/param_struct.ys +++ b/yosys/tests/various/param_struct.ys @@ -47,4 +47,5 @@ end endmodule EOF hierarchy; proc; opt +async2sync sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/yosys/tests/various/peepopt.ys b/yosys/tests/various/peepopt.ys index 45e936a21e6..cbbd477e8b1 100644 --- a/yosys/tests/various/peepopt.ys +++ b/yosys/tests/various/peepopt.ys @@ -46,7 +46,31 @@ design -import gold -as gold peepopt_shiftmul_2 design -import gate -as gate peepopt_shiftmul_2 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter -sat -show-public -enable_undef -prove-asserts miter +sat -verify -show-public -enable_undef -prove-asserts miter +cd gate +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog <> (S*5); +endmodule +EOT + +prep +design -save gold +peepopt +design -stash gate + +design -import gold -as gold peepopt_shiftmul_3 +design -import gate -as gate peepopt_shiftmul_3 + +miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter +sat -verify -show-public -enable_undef -prove-asserts miter cd gate select -assert-count 1 t:$shr select -assert-count 1 t:$mul diff --git a/yosys/tests/various/sformatf.ys b/yosys/tests/various/sformatf.ys index 66d6b0dbe9e..f281a9cd530 100644 --- a/yosys/tests/various/sformatf.ys +++ b/yosys/tests/various/sformatf.ys @@ -5,7 +5,7 @@ module top; localparam b = $sformatf("%d", 4'b011); generate if (a != "0x5a") $error("a incorrect!"); - if (b != "3") $error("b incorrect!"); + if (b != " 3") $error("b incorrect!"); endgenerate endmodule diff --git a/yosys/tests/various/smtlib2_module-expected.smt2 b/yosys/tests/various/smtlib2_module-expected.smt2 deleted file mode 100644 index 494e7cda095..00000000000 --- a/yosys/tests/various/smtlib2_module-expected.smt2 +++ /dev/null @@ -1,96 +0,0 @@ -; SMT-LIBv2 description generated by Yosys $VERSION -; yosys-smt2-module smtlib2 -(declare-sort |smtlib2_s| 0) -(declare-fun |smtlib2_is| (|smtlib2_s|) Bool) -(declare-fun |smtlib2#0| (|smtlib2_s|) (_ BitVec 8)) ; \a -; yosys-smt2-input a 8 -; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": "a", "smtoffset": 0, "type": "input", "width": 8} -(define-fun |smtlib2_n a| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#0| state)) -(declare-fun |smtlib2#1| (|smtlib2_s|) (_ BitVec 8)) ; \b -; yosys-smt2-input b 8 -; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": "b", "smtoffset": 0, "type": "input", "width": 8} -(define-fun |smtlib2_n b| ((state |smtlib2_s|)) (_ BitVec 8) (|smtlib2#1| state)) -; yosys-smt2-output add 8 -; yosys-smt2-witness {"offset": 0, "path": ["\\add"], "smtname": "add", "smtoffset": 0, "type": "blackbox", "width": 8} -(define-fun |smtlib2_n add| ((state |smtlib2_s|)) (_ BitVec 8) (let ( -(|a| (|smtlib2_n a| state)) -(|b| (|smtlib2_n b| state)) -) -(bvadd a b) -)) -; yosys-smt2-output eq 1 -; yosys-smt2-witness {"offset": 0, "path": ["\\eq"], "smtname": "eq", "smtoffset": 0, "type": "blackbox", "width": 1} -(define-fun |smtlib2_n eq| ((state |smtlib2_s|)) Bool (let ( -(|a| (|smtlib2_n a| state)) -(|b| (|smtlib2_n b| state)) -) -(= a b) -)) -; yosys-smt2-output sub 8 -; yosys-smt2-witness {"offset": 0, "path": ["\\sub"], "smtname": "sub", "smtoffset": 0, "type": "blackbox", "width": 8} -(define-fun |smtlib2_n sub| ((state |smtlib2_s|)) (_ BitVec 8) (let ( -(|a| (|smtlib2_n a| state)) -(|b| (|smtlib2_n b| state)) -) -(bvadd a (bvneg b)) -)) -(define-fun |smtlib2_a| ((state |smtlib2_s|)) Bool true) -(define-fun |smtlib2_u| ((state |smtlib2_s|)) Bool true) -(define-fun |smtlib2_i| ((state |smtlib2_s|)) Bool true) -(define-fun |smtlib2_h| ((state |smtlib2_s|)) Bool true) -(define-fun |smtlib2_t| ((state |smtlib2_s|) (next_state |smtlib2_s|)) Bool true) ; end of module smtlib2 -; yosys-smt2-module uut -(declare-sort |uut_s| 0) -(declare-fun |uut_is| (|uut_s|) Bool) -; yosys-smt2-cell smtlib2 s -; yosys-smt2-witness {"path": ["\\s"], "smtname": "s", "type": "cell"} -(declare-fun |uut#0| (|uut_s|) (_ BitVec 8)) ; \add -(declare-fun |uut#1| (|uut_s|) Bool) ; \eq -(declare-fun |uut#2| (|uut_s|) (_ BitVec 8)) ; \sub -(declare-fun |uut_h s| (|uut_s|) |smtlib2_s|) -; yosys-smt2-anyconst uut#3 8 smtlib2_module.v:14.17-14.26 -; yosys-smt2-witness {"offset": 0, "path": ["\\a"], "smtname": 3, "smtoffset": 0, "type": "init", "width": 8} -(declare-fun |uut#3| (|uut_s|) (_ BitVec 8)) ; \a -; yosys-smt2-anyconst uut#4 8 smtlib2_module.v:14.32-14.41 -; yosys-smt2-witness {"offset": 0, "path": ["\\b"], "smtname": 4, "smtoffset": 0, "type": "init", "width": 8} -(declare-fun |uut#4| (|uut_s|) (_ BitVec 8)) ; \b -(define-fun |uut#5| ((state |uut_s|)) (_ BitVec 8) (bvadd (|uut#3| state) (|uut#4| state))) ; \add2 -(define-fun |uut#6| ((state |uut_s|)) Bool (= (|uut#0| state) (|uut#5| state))) ; $0$formal$smtlib2_module.v:28$1_CHECK[0:0]$9 -; yosys-smt2-assert 0 $assert$smtlib2_module.v:28$19 smtlib2_module.v:28.17-29.22 -(define-fun |uut_a 0| ((state |uut_s|)) Bool (or (|uut#6| state) (not true))) ; $assert$smtlib2_module.v:28$19 -(define-fun |uut#7| ((state |uut_s|)) (_ BitVec 8) (bvsub (|uut#3| state) (|uut#4| state))) ; \sub2 -(define-fun |uut#8| ((state |uut_s|)) Bool (= (|uut#2| state) (|uut#7| state))) ; $0$formal$smtlib2_module.v:29$2_CHECK[0:0]$11 -; yosys-smt2-assert 1 $assert$smtlib2_module.v:29$20 smtlib2_module.v:29.23-30.22 -(define-fun |uut_a 1| ((state |uut_s|)) Bool (or (|uut#8| state) (not true))) ; $assert$smtlib2_module.v:29$20 -(define-fun |uut#9| ((state |uut_s|)) Bool (= (|uut#3| state) (|uut#4| state))) ; $eq$smtlib2_module.v:31$17_Y -(define-fun |uut#10| ((state |uut_s|)) Bool (= (ite (|uut#1| state) #b1 #b0) (ite (|uut#9| state) #b1 #b0))) ; $0$formal$smtlib2_module.v:30$3_CHECK[0:0]$13 -; yosys-smt2-assert 2 $assert$smtlib2_module.v:30$21 smtlib2_module.v:30.23-31.25 -(define-fun |uut_a 2| ((state |uut_s|)) Bool (or (|uut#10| state) (not true))) ; $assert$smtlib2_module.v:30$21 -(define-fun |uut_a| ((state |uut_s|)) Bool (and - (|uut_a 0| state) - (|uut_a 1| state) - (|uut_a 2| state) - (|smtlib2_a| (|uut_h s| state)) -)) -(define-fun |uut_u| ((state |uut_s|)) Bool - (|smtlib2_u| (|uut_h s| state)) -) -(define-fun |uut_i| ((state |uut_s|)) Bool - (|smtlib2_i| (|uut_h s| state)) -) -(define-fun |uut_h| ((state |uut_s|)) Bool (and - (= (|uut_is| state) (|smtlib2_is| (|uut_h s| state))) - (= (|uut#3| state) (|smtlib2_n a| (|uut_h s| state))) ; smtlib2.a - (= (|uut#0| state) (|smtlib2_n add| (|uut_h s| state))) ; smtlib2.add - (= (|uut#4| state) (|smtlib2_n b| (|uut_h s| state))) ; smtlib2.b - (= (|uut#1| state) (|smtlib2_n eq| (|uut_h s| state))) ; smtlib2.eq - (= (|uut#2| state) (|smtlib2_n sub| (|uut_h s| state))) ; smtlib2.sub - (|smtlib2_h| (|uut_h s| state)) -)) -(define-fun |uut_t| ((state |uut_s|) (next_state |uut_s|)) Bool (and - (= (|uut#4| state) (|uut#4| next_state)) ; $anyconst$5 \b - (= (|uut#3| state) (|uut#3| next_state)) ; $anyconst$4 \a - (|smtlib2_t| (|uut_h s| state) (|uut_h s| next_state)) -)) ; end of module uut -; yosys-smt2-topmod uut -; end of yosys output diff --git a/yosys/tests/various/smtlib2_module.sh b/yosys/tests/various/smtlib2_module.sh deleted file mode 100755 index 491f6514877..00000000000 --- a/yosys/tests/various/smtlib2_module.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/bash -set -ex -../../yosys -q -p 'read_verilog -formal smtlib2_module.v; prep; write_smt2 smtlib2_module.smt2' -sed 's/; SMT-LIBv2 description generated by Yosys .*/; SMT-LIBv2 description generated by Yosys $VERSION/;s/ *$//' smtlib2_module.smt2 > smtlib2_module-filtered.smt2 -diff -au smtlib2_module-expected.smt2 smtlib2_module-filtered.smt2 diff --git a/yosys/tests/various/smtlib2_module.v b/yosys/tests/various/smtlib2_module.v deleted file mode 100644 index 4aad8690527..00000000000 --- a/yosys/tests/various/smtlib2_module.v +++ /dev/null @@ -1,33 +0,0 @@ -(* smtlib2_module *) -module smtlib2(a, b, add, sub, eq); - input [7:0] a, b; - (* smtlib2_comb_expr = "(bvadd a b)" *) - output [7:0] add; - (* smtlib2_comb_expr = "(bvadd a (bvneg b))" *) - output [7:0] sub; - (* smtlib2_comb_expr = "(= a b)" *) - output eq; -endmodule - -(* top *) -module uut; - wire [7:0] a = $anyconst, b = $anyconst, add, sub, add2, sub2; - wire eq; - - assign add2 = a + b; - assign sub2 = a - b; - - smtlib2 s ( - .a(a), - .b(b), - .add(add), - .sub(sub), - .eq(eq) - ); - - always @* begin - assert(add == add2); - assert(sub == sub2); - assert(eq == (a == b)); - end -endmodule diff --git a/yosys/tests/various/struct_access.ys b/yosys/tests/various/struct_access.ys index 2282edd9246..43a2ac8b827 100644 --- a/yosys/tests/various/struct_access.ys +++ b/yosys/tests/various/struct_access.ys @@ -2,4 +2,5 @@ read_verilog -sv struct_access.sv hierarchy proc opt +async2sync sat -verify -seq 1 -prove-asserts -show-all diff --git a/yosys/tests/various/sv_implicit_ports.sh b/yosys/tests/various/sv_implicit_ports.sh index 9a01447f7cf..5266fffe516 100755 --- a/yosys/tests/various/sv_implicit_ports.sh +++ b/yosys/tests/various/sv_implicit_ports.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR diff --git a/yosys/tests/various/svalways.sh b/yosys/tests/various/svalways.sh index 2cc09f801ba..7765907c708 100755 --- a/yosys/tests/various/svalways.sh +++ b/yosys/tests/various/svalways.sh @@ -1,4 +1,4 @@ -#!/bin/bash +#!/usr/bin/env bash trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR diff --git a/yosys/tests/verific/clocking.ys b/yosys/tests/verific/clocking.ys new file mode 100644 index 00000000000..bfdbeb748c1 --- /dev/null +++ b/yosys/tests/verific/clocking.ys @@ -0,0 +1,10 @@ +read -sv < data <= X"12"; + when "001" => data <= X"AB"; + when "010" => data <= X"42"; + when "011" => data <= X"23"; + when "100" => data <= X"66"; + when "101" => data <= X"C0"; + when "110" => data <= X"3F"; + when others => data <= X"95"; + end case; + end if; + end process p_rom; + +end architecture rtl; +EOF +hierarchy -top rom_example +proc +opt +opt -full +memory -nomap +dump +memory_libmap -lib ../memlib/memlib_block_sdp.txt +memory_map +stat +select -assert-count 1 t:RAM_BLOCK_SDP \ No newline at end of file diff --git a/yosys/tests/verilog/asgn_expr.sv b/yosys/tests/verilog/asgn_expr.sv new file mode 100644 index 00000000000..25f9caa33d1 --- /dev/null +++ b/yosys/tests/verilog/asgn_expr.sv @@ -0,0 +1,73 @@ +module top; + integer x, y, z; + task check; + input integer a, b, c; + assert (x == a); + assert (y == b); + assert (z == c); + endtask + always_comb begin + x = 0; y = 0; z = 0; + check(0, 0, 0); + + // post-increment/decrement statements + x++; + check(1, 0, 0); + (* bar *) y (* foo *) ++; + check(1, 1, 0); + z--; + check(1, 1, -1); + (* bar *) z (* foo *) --; + check(1, 1, -2); + + // pre-increment/decrement statements are equivalent + ++z; + check(1, 1, -1); + (* bar *) ++ (* foo *) z; + check(1, 1, 0); + --x; + check(0, 1, 0); + (* bar *) -- (* foo *) y; + check(0, 0, 0); + + // procedural pre-increment/decrement expressions + z = ++x; + check(1, 0, 1); + z = ++ (* foo *) x; + check(2, 0, 2); + y = --x; + check(1, 1, 2); + y = -- (* foo *) x; + + // procedural post-increment/decrement expressions + // TODO: support attributes on post-increment/decrement + check(0, 0, 2); + y = x++; + check(1, 0, 2); + y = x--; + check(0, 1, 2); + + // procedural assignment expressions + x = (y = (z = 99) + 1) + 1; + check(101, 100, 99); + x = (y *= 2); + check(200, 200, 99); + x = (z >>= 2) * 4; + check(96, 200, 24); + y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned + check(96, 24, 12); + + // check width of post-increment expressions + z = (y = 0); + begin + byte w; + w = 0; + x = {1'b1, ++w}; + check(257, 0, 0); + assert (w == 1); + x = {2'b10, w++}; + check(513, 0, 0); + assert (w == 2); + end + end +endmodule diff --git a/yosys/tests/verilog/asgn_expr.ys b/yosys/tests/verilog/asgn_expr.ys new file mode 100644 index 00000000000..78c005228f4 --- /dev/null +++ b/yosys/tests/verilog/asgn_expr.ys @@ -0,0 +1,4 @@ +read_verilog -sv asgn_expr.sv +proc +async2sync +sat -verify -prove-asserts -show-all diff --git a/yosys/tests/verilog/asgn_expr_not_proc_1.ys b/yosys/tests/verilog/asgn_expr_not_proc_1.ys new file mode 100644 index 00000000000..72ba0bd89dc --- /dev/null +++ b/yosys/tests/verilog/asgn_expr_not_proc_1.ys @@ -0,0 +1,7 @@ +logger -expect error "Assignments within expressions are only permitted within procedures." 1 +read_verilog -sv <